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/Linux-v6.1/Documentation/devicetree/bindings/clock/
Dti,am654-ehrpwm-tbclk.yaml38 reg = <0x4140 0x18>;
/Linux-v6.1/Documentation/devicetree/bindings/mfd/
Dti,j721e-system-controller.yaml46 "^mux-controller@[0-9a-f]+$":
51 "^clock-controller@[0-9a-f]+$":
57 "phy@[0-9a-f]+$":
76 reg = <0x00100000 0x1c000>;
83 reg = <0x00004080 0x50>;
87 <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
88 <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
89 <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
90 <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
91 <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
[all …]
/Linux-v6.1/arch/arm/boot/dts/
Dimx28-pinfunc.h13 #define MX28_PAD_GPMI_D00__GPMI_D0 0x0000
14 #define MX28_PAD_GPMI_D01__GPMI_D1 0x0010
15 #define MX28_PAD_GPMI_D02__GPMI_D2 0x0020
16 #define MX28_PAD_GPMI_D03__GPMI_D3 0x0030
17 #define MX28_PAD_GPMI_D04__GPMI_D4 0x0040
18 #define MX28_PAD_GPMI_D05__GPMI_D5 0x0050
19 #define MX28_PAD_GPMI_D06__GPMI_D6 0x0060
20 #define MX28_PAD_GPMI_D07__GPMI_D7 0x0070
21 #define MX28_PAD_GPMI_CE0N__GPMI_CE0N 0x0100
22 #define MX28_PAD_GPMI_CE1N__GPMI_CE1N 0x0110
[all …]
/Linux-v6.1/drivers/hwmon/pmbus/
Dltc2978.c33 #define LTC2978_MFR_VOUT_PEAK 0xdd
34 #define LTC2978_MFR_VIN_PEAK 0xde
35 #define LTC2978_MFR_TEMPERATURE_PEAK 0xdf
36 #define LTC2978_MFR_SPECIAL_ID 0xe7 /* Undocumented on LTC3882 */
37 #define LTC2978_MFR_COMMON 0xef
40 #define LTC2978_MFR_VOUT_MIN 0xfb
41 #define LTC2978_MFR_VIN_MIN 0xfc
42 #define LTC2978_MFR_TEMPERATURE_MIN 0xfd
45 #define LTC2974_MFR_IOUT_PEAK 0xd7
46 #define LTC2974_MFR_IOUT_MIN 0xd8
[all …]
/Linux-v6.1/drivers/clk/imx/
Dclk-imx7d.c32 { .val = 0, .div = 4, },
40 { .val = 0, .div = 1, },
393 hws[IMX7D_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx7d_clocks_init()
398 base = of_iomap(np, 0); in imx7d_clocks_init()
402 …hws[IMX7D_PLL_ARM_MAIN_SRC] = imx_clk_hw_mux("pll_arm_main_src", base + 0x60, 14, 2, pll_bypass_s… in imx7d_clocks_init()
403 …hws[IMX7D_PLL_DRAM_MAIN_SRC] = imx_clk_hw_mux("pll_dram_main_src", base + 0x70, 14, 2, pll_bypass_… in imx7d_clocks_init()
404 …hws[IMX7D_PLL_SYS_MAIN_SRC] = imx_clk_hw_mux("pll_sys_main_src", base + 0xb0, 14, 2, pll_bypass_s… in imx7d_clocks_init()
405 …hws[IMX7D_PLL_ENET_MAIN_SRC] = imx_clk_hw_mux("pll_enet_main_src", base + 0xe0, 14, 2, pll_bypass_… in imx7d_clocks_init()
406 …hws[IMX7D_PLL_AUDIO_MAIN_SRC] = imx_clk_hw_mux("pll_audio_main_src", base + 0xf0, 14, 2, pll_bypas… in imx7d_clocks_init()
407 …hws[IMX7D_PLL_VIDEO_MAIN_SRC] = imx_clk_hw_mux("pll_video_main_src", base + 0x130, 14, 2, pll_bypa… in imx7d_clocks_init()
[all …]
Dclk-imx8mn.c334 hws[IMX8MN_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx8mn_clocks_probe()
343 base = of_iomap(np, 0); in imx8mn_clocks_probe()
350 …hws[IMX8MN_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, pll_ref_se… in imx8mn_clocks_probe()
351 …hws[IMX8MN_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, pll_ref_s… in imx8mn_clocks_probe()
352 …hws[IMX8MN_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", base + 0x28, 0, 2, pll_ref_s… in imx8mn_clocks_probe()
353 …hws[IMX8MN_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels,… in imx8mn_clocks_probe()
354 …hws[IMX8MN_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, A… in imx8mn_clocks_probe()
355 …hws[IMX8MN_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", base + 0x74, 0, 2, pll_ref_sels, A… in imx8mn_clocks_probe()
356 …hws[IMX8MN_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, A… in imx8mn_clocks_probe()
357 …hws[IMX8MN_SYS_PLL3_REF_SEL] = imx_clk_hw_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels… in imx8mn_clocks_probe()
[all …]
Dclk-imx8mp.c417 anatop_base = of_iomap(np, 0); in imx8mp_clocks_probe()
423 ccm_base = devm_platform_ioremap_resource(pdev, 0); in imx8mp_clocks_probe()
438 hws[IMX8MP_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx8mp_clocks_probe()
446 …hws[IMX8MP_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", anatop_base + 0x0, 0, 2, pll… in imx8mp_clocks_probe()
447 …hws[IMX8MP_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", anatop_base + 0x14, 0, 2, pl… in imx8mp_clocks_probe()
448 …hws[IMX8MP_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", anatop_base + 0x28, 0, 2, pl… in imx8mp_clocks_probe()
449 …hws[IMX8MP_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", anatop_base + 0x50, 0, 2, pll_re… in imx8mp_clocks_probe()
450 …hws[IMX8MP_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", anatop_base + 0x64, 0, 2, pll_ref_… in imx8mp_clocks_probe()
451 …hws[IMX8MP_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", anatop_base + 0x74, 0, 2, pll_ref_… in imx8mp_clocks_probe()
452 …hws[IMX8MP_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", anatop_base + 0x84, 0, 2, pll_ref_… in imx8mp_clocks_probe()
[all …]
/Linux-v6.1/drivers/gpu/drm/i915/display/
Dintel_dsi_vbt.c51 #define MIPI_TRANSFER_MODE_SHIFT 0
56 #define VLV_GPIO_NC_0_HV_DDI0_HPD 0x4130
57 #define VLV_GPIO_NC_1_HV_DDI0_DDC_SDA 0x4120
58 #define VLV_GPIO_NC_2_HV_DDI0_DDC_SCL 0x4110
59 #define VLV_GPIO_NC_3_PANEL0_VDDEN 0x4140
60 #define VLV_GPIO_NC_4_PANEL0_BKLTEN 0x4150
61 #define VLV_GPIO_NC_5_PANEL0_BKLTCTL 0x4160
62 #define VLV_GPIO_NC_6_HV_DDI1_HPD 0x4180
63 #define VLV_GPIO_NC_7_HV_DDI1_DDC_SDA 0x4190
64 #define VLV_GPIO_NC_8_HV_DDI1_DDC_SCL 0x4170
[all …]
/Linux-v6.1/drivers/ata/
Dlibata-pmp.c36 * 0 on success, AC_ERR_* mask on failure.
52 err_mask = ata_exec_internal(pmp_dev, &tf, NULL, DMA_NONE, NULL, 0, in sata_pmp_read()
58 return 0; in sata_pmp_read()
73 * 0 on success, AC_ERR_* mask on failure.
87 tf.nsect = val & 0xff; in sata_pmp_write()
88 tf.lbal = (val >> 8) & 0xff; in sata_pmp_write()
89 tf.lbam = (val >> 16) & 0xff; in sata_pmp_write()
90 tf.lbah = (val >> 24) & 0xff; in sata_pmp_write()
92 return ata_exec_internal(pmp_dev, &tf, NULL, DMA_NONE, NULL, 0, in sata_pmp_write()
107 * ATA_DEFER_* if deferring is needed, 0 otherwise.
[all …]
Dsata_sil24.c47 SIL24_HOST_BAR = 0,
69 HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */
70 HOST_CTRL = 0x40,
71 HOST_IRQ_STAT = 0x44,
72 HOST_PHY_CFG = 0x48,
73 HOST_BIST_CTRL = 0x50,
74 HOST_BIST_PTRN = 0x54,
75 HOST_BIST_STAT = 0x58,
76 HOST_MEM_BIST_STAT = 0x5c,
77 HOST_FLASH_CMD = 0x70,
[all …]
/Linux-v6.1/drivers/net/ethernet/marvell/octeontx2/af/
Drvu_reg.h12 #define RVU_AF_MSIXTR_BASE (0x10)
13 #define RVU_AF_ECO (0x20)
14 #define RVU_AF_BLK_RST (0x30)
15 #define RVU_AF_PF_BAR4_ADDR (0x40)
16 #define RVU_AF_RAS (0x100)
17 #define RVU_AF_RAS_W1S (0x108)
18 #define RVU_AF_RAS_ENA_W1S (0x110)
19 #define RVU_AF_RAS_ENA_W1C (0x118)
20 #define RVU_AF_GEN_INT (0x120)
21 #define RVU_AF_GEN_INT_W1S (0x128)
[all …]
/Linux-v6.1/drivers/phy/rockchip/
Dphy-rockchip-typec.c58 #define CMN_SSM_BANDGAP (0x21 << 2)
59 #define CMN_SSM_BIAS (0x22 << 2)
60 #define CMN_PLLSM0_PLLEN (0x29 << 2)
61 #define CMN_PLLSM0_PLLPRE (0x2a << 2)
62 #define CMN_PLLSM0_PLLVREF (0x2b << 2)
63 #define CMN_PLLSM0_PLLLOCK (0x2c << 2)
64 #define CMN_PLLSM1_PLLEN (0x31 << 2)
65 #define CMN_PLLSM1_PLLPRE (0x32 << 2)
66 #define CMN_PLLSM1_PLLVREF (0x33 << 2)
67 #define CMN_PLLSM1_PLLLOCK (0x34 << 2)
[all …]
/Linux-v6.1/arch/arm64/boot/dts/ti/
Dk3-am65-main.dtsi12 reg = <0x0 0x70000000 0x0 0x200000>;
15 ranges = <0x0 0x0 0x70000000 0x200000>;
17 atf-sram@0 {
18 reg = <0x0 0x20000>;
22 reg = <0xf0000 0x10000>;
26 reg = <0x100000 0x100000>;
37 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
38 <0x00 0x01880000 0x00 0x90000>, /* GICR */
39 <0x00 0x6f000000 0x00 0x2000>, /* GICC */
40 <0x00 0x6f010000 0x00 0x1000>, /* GICH */
[all …]
/Linux-v6.1/drivers/gpu/drm/amd/include/asic_reg/dpcs/
Ddpcs_3_1_4_offset.h31 // base address: 0x0
32 …DPCSSYS_CR0_SUP_DIG_IDCODE_LO 0x0000
33 …DPCSSYS_CR0_SUP_DIG_IDCODE_HI 0x0001
34 …DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN 0x0002
35 …DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN 0x0003
36 …DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN 0x0004
37 …DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN 0x0005
38 …DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN 0x0006
39 …DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0 0x0007
40 …DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_1 0x0008
[all …]
Ddpcs_4_2_0_offset.h27 // base address: 0x0
28 …DPCSSYS_CR0_DPCSSYS_CR_ADDR 0x2934
30 …DPCSSYS_CR0_DPCSSYS_CR_DATA 0x2935
35 // base address: 0x360
36 …DPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c
38 …DPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d
43 // base address: 0x6c0
44 …DPCSSYS_CR2_DPCSSYS_CR_ADDR 0x2ae4
46 …DPCSSYS_CR2_DPCSSYS_CR_DATA 0x2ae5
51 // base address: 0xa20
[all …]
Ddpcs_4_2_2_offset.h14 // base address: 0x0
15 …DPCSSYS_CR0_DPCSSYS_CR_ADDR 0x2934
17 …DPCSSYS_CR0_DPCSSYS_CR_DATA 0x2935
22 // base address: 0x360
23 …DPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c
25 …DPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d
30 // base address: 0x6c0
31 …DPCSSYS_CR2_DPCSSYS_CR_ADDR 0x2ae4
33 …DPCSSYS_CR2_DPCSSYS_CR_DATA 0x2ae5
38 // base address: 0xa20
[all …]
Ddpcs_4_2_3_offset.h31 // base address: 0x0
32 …DPCSSYS_CR0_DPCSSYS_CR_ADDR 0x2934
34 …DPCSSYS_CR0_DPCSSYS_CR_DATA 0x2935
39 // base address: 0x360
40 …DPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c
42 …DPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d
47 // base address: 0x6c0
48 …DPCSSYS_CR2_DPCSSYS_CR_ADDR 0x2ae4
50 …DPCSSYS_CR2_DPCSSYS_CR_DATA 0x2ae5
55 // base address: 0xa20
[all …]
/Linux-v6.1/drivers/net/ethernet/intel/igb/
Digb_ethtool.c112 TEST_REG = 0,
129 #define IGB_PRIV_FLAGS_LEGACY_RX BIT(0)
147 0 : rd32(E1000_STATUS); in igb_get_link_ksettings()
240 /* MDI-X => 2; MDI =>1; Invalid =>0 */ in igb_get_link_ksettings()
257 return 0; in igb_get_link_ksettings()
338 /* fix up the value for auto (3 => 0) as zero is mapped in igb_set_link_ksettings()
355 return 0; in igb_set_link_ksettings()
399 int retval = 0; in igb_set_pauseparam()
435 for (i = 0; i < adapter->num_rx_queues; i++) { in igb_set_pauseparam()
472 memset(p, 0, IGB_REGS_LEN * sizeof(u32)); in igb_get_regs()
[all …]
/Linux-v6.1/drivers/net/ethernet/intel/e1000/
De1000_ethtool.c20 sizeof(((struct e1000_adapter *)0)->m), \
23 sizeof(((struct net_device *)0)->m), \
75 #define E1000_QUEUE_STATS_LEN 0
143 /* MDI-X => 1; MDI => 0 */ in e1000_get_link_ksettings()
161 return 0; in e1000_get_link_ksettings()
228 return 0; in e1000_set_link_ksettings()
271 int retval = 0; in e1000_set_pauseparam()
332 memset(p, 0, E1000_REGS_LEN * sizeof(u32)); in e1000_get_regs()
336 regs_buff[0] = er32(CTRL); in e1000_get_regs()
351 regs_buff[12] = hw->phy_type; /* PHY type (IGP=1, M88=0) */ in e1000_get_regs()
[all …]
/Linux-v6.1/drivers/mtd/nand/raw/
Dsunxi_nand.c33 #define NFC_REG_CTL 0x0000
34 #define NFC_REG_ST 0x0004
35 #define NFC_REG_INT 0x0008
36 #define NFC_REG_TIMING_CTL 0x000C
37 #define NFC_REG_TIMING_CFG 0x0010
38 #define NFC_REG_ADDR_LOW 0x0014
39 #define NFC_REG_ADDR_HIGH 0x0018
40 #define NFC_REG_SECTOR_NUM 0x001C
41 #define NFC_REG_CNT 0x0020
42 #define NFC_REG_CMD 0x0024
[all …]
/Linux-v6.1/drivers/net/ethernet/intel/e1000e/
Dethtool.c27 #define E1000E_PRIV_FLAGS_S0IX_ENABLED BIT(0)
36 .sizeof_stat = sizeof(((struct e1000_adapter *)0)->m), \
41 .sizeof_stat = sizeof(((struct rtnl_link_stats64 *)0)->m), \
179 /* MDI-X => 2; MDI =>1; Invalid =>0 */ in e1000_get_link_ksettings()
200 return 0; in e1000_get_link_ksettings()
207 mac->autoneg = 0; in e1000_set_spd_dplx()
251 return 0; in e1000_set_spd_dplx()
263 int ret_val = 0; in e1000_set_link_ksettings()
324 /* fix up the value for auto (3 => 0) as zero is mapped in e1000_set_link_ksettings()
371 int retval = 0; in e1000_set_pauseparam()
[all …]
/Linux-v6.1/sound/soc/mediatek/mt8195/
Dmt8195-reg.h13 #define AFE_SRAM_BASE (0x10880000)
14 #define AFE_SRAM_SIZE (0x10000)
16 #define AUDIO_TOP_CON0 (0x0000)
17 #define AUDIO_TOP_CON1 (0x0004)
18 #define AUDIO_TOP_CON2 (0x0008)
19 #define AUDIO_TOP_CON3 (0x000c)
20 #define AUDIO_TOP_CON4 (0x0010)
21 #define AUDIO_TOP_CON5 (0x0014)
22 #define AUDIO_TOP_CON6 (0x0018)
23 #define AFE_MAS_HADDR_MSB (0x0020)
[all …]
/Linux-v6.1/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_6_0_d.h26 #define ixATTR00 0x0000
27 #define ixATTR01 0x0001
28 #define ixATTR02 0x0002
29 #define ixATTR03 0x0003
30 #define ixATTR04 0x0004
31 #define ixATTR05 0x0005
32 #define ixATTR06 0x0006
33 #define ixATTR07 0x0007
34 #define ixATTR08 0x0008
35 #define ixATTR09 0x0009
[all …]
Ddce_8_0_d.h27 #define mmPIPE0_PG_CONFIG 0x1760
28 #define mmPIPE0_PG_ENABLE 0x1761
29 #define mmPIPE0_PG_STATUS 0x1762
30 #define mmPIPE1_PG_CONFIG 0x1764
31 #define mmPIPE1_PG_ENABLE 0x1765
32 #define mmPIPE1_PG_STATUS 0x1766
33 #define mmPIPE2_PG_CONFIG 0x1768
34 #define mmPIPE2_PG_ENABLE 0x1769
35 #define mmPIPE2_PG_STATUS 0x176a
36 #define mmPIPE3_PG_CONFIG 0x176c
[all …]
/Linux-v6.1/drivers/net/ethernet/sun/
Dcassini.h8 * vendor id: 0x108E (Sun Microsystems, Inc.)
9 * device id: 0xabba (Cassini)
10 * revision ids: 0x01 = Cassini
11 * 0x02 = Cassini rev 2
12 * 0x10 = Cassini+
13 * 0x11 = Cassini+ 0.2u
15 * vendor id: 0x100b (National Semiconductor)
16 * device id: 0x0035 (DP83065/Saturn)
17 * revision ids: 0x30 = Saturn B2
19 * rings are all offset from 0.
[all …]

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