Lines Matching +full:0 +full:x4140
27 #define E1000E_PRIV_FLAGS_S0IX_ENABLED BIT(0)
36 .sizeof_stat = sizeof(((struct e1000_adapter *)0)->m), \
41 .sizeof_stat = sizeof(((struct rtnl_link_stats64 *)0)->m), \
179 /* MDI-X => 2; MDI =>1; Invalid =>0 */ in e1000_get_link_ksettings()
200 return 0; in e1000_get_link_ksettings()
207 mac->autoneg = 0; in e1000_set_spd_dplx()
251 return 0; in e1000_set_spd_dplx()
263 int ret_val = 0; in e1000_set_link_ksettings()
324 /* fix up the value for auto (3 => 0) as zero is mapped in e1000_set_link_ksettings()
371 int retval = 0; in e1000_set_pauseparam()
445 memset(p, 0, E1000_REGS_LEN * sizeof(u32)); in e1000_get_regs()
451 regs_buff[0] = er32(CTRL); in e1000_get_regs()
455 regs_buff[3] = er32(RDLEN(0)); in e1000_get_regs()
456 regs_buff[4] = er32(RDH(0)); in e1000_get_regs()
457 regs_buff[5] = er32(RDT(0)); in e1000_get_regs()
461 regs_buff[8] = er32(TDLEN(0)); in e1000_get_regs()
462 regs_buff[9] = er32(TDH(0)); in e1000_get_regs()
463 regs_buff[10] = er32(TDT(0)); in e1000_get_regs()
466 regs_buff[12] = adapter->hw.phy.type; /* PHY type (IGP=1, M88=0) */ in e1000_get_regs()
474 regs_buff[14] = 0; /* Dummy (to align w/ IGP phy reg dump) */ in e1000_get_regs()
475 regs_buff[15] = 0; /* Dummy (to align w/ IGP phy reg dump) */ in e1000_get_regs()
476 regs_buff[16] = 0; /* Dummy (to align w/ IGP phy reg dump) */ in e1000_get_regs()
480 regs_buff[19] = 0; /* Dummy (to align w/ IGP phy reg dump) */ in e1000_get_regs()
486 regs_buff[21] = 0; /* was idle_errors */ in e1000_get_regs()
508 int ret_val = 0; in e1000_get_eeprom()
511 if (eeprom->len == 0) in e1000_get_eeprom()
531 for (i = 0; i < last_word - first_word + 1; i++) { in e1000_get_eeprom()
543 memset(eeprom_buff, 0xff, sizeof(u16) * in e1000_get_eeprom()
547 for (i = 0; i < last_word - first_word + 1; i++) in e1000_get_eeprom()
567 int ret_val = 0; in e1000_set_eeprom()
570 if (eeprom->len == 0) in e1000_set_eeprom()
595 ret_val = e1000_read_nvm(hw, first_word, 1, &eeprom_buff[0]); in e1000_set_eeprom()
608 for (i = 0; i < last_word - first_word + 1; i++) in e1000_set_eeprom()
613 for (i = 0; i < last_word - first_word + 1; i++) in e1000_set_eeprom()
649 (adapter->eeprom_vers & 0xF000) >> 12, in e1000_get_drvinfo()
650 (adapter->eeprom_vers & 0x0FF0) >> 4, in e1000_get_drvinfo()
651 (adapter->eeprom_vers & 0x000F)); in e1000_get_drvinfo()
677 int err = 0, size = sizeof(struct e1000_ring); in e1000_set_ringparam()
695 return 0; in e1000_set_ringparam()
782 0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF in reg_pattern_test()
784 for (pat = 0; pat < ARRAY_SIZE(test); pat++) { in reg_pattern_test()
789 e_err("pattern test failed (reg 0x%05X): got 0x%08X expected 0x%08X\n", in reg_pattern_test()
807 e_err("set/check test failed (reg 0x%05X): got 0x%08X expected 0x%08X\n", in reg_set_and_check()
819 } while (0)
821 REG_PATTERN_TEST_ARRAY(reg, 0, mask, write)
827 } while (0)
839 u32 wlock_mac = 0; in e1000_reg_test()
849 toggle = 0x7FFFF3FF; in e1000_reg_test()
852 toggle = 0x7FFFF033; in e1000_reg_test()
861 e_err("failed STATUS register test got: 0x%08X expected: 0x%08X\n", in e1000_reg_test()
870 REG_PATTERN_TEST(E1000_FCAL, 0xFFFFFFFF, 0xFFFFFFFF); in e1000_reg_test()
871 REG_PATTERN_TEST(E1000_FCAH, 0x0000FFFF, 0xFFFFFFFF); in e1000_reg_test()
872 REG_PATTERN_TEST(E1000_FCT, 0x0000FFFF, 0xFFFFFFFF); in e1000_reg_test()
873 REG_PATTERN_TEST(E1000_VET, 0x0000FFFF, 0xFFFFFFFF); in e1000_reg_test()
876 REG_PATTERN_TEST(E1000_RDTR, 0x0000FFFF, 0xFFFFFFFF); in e1000_reg_test()
877 REG_PATTERN_TEST(E1000_RDBAH(0), 0xFFFFFFFF, 0xFFFFFFFF); in e1000_reg_test()
878 REG_PATTERN_TEST(E1000_RDLEN(0), 0x000FFF80, 0x000FFFFF); in e1000_reg_test()
879 REG_PATTERN_TEST(E1000_RDH(0), 0x0000FFFF, 0x0000FFFF); in e1000_reg_test()
880 REG_PATTERN_TEST(E1000_RDT(0), 0x0000FFFF, 0x0000FFFF); in e1000_reg_test()
881 REG_PATTERN_TEST(E1000_FCRTH, 0x0000FFF8, 0x0000FFF8); in e1000_reg_test()
882 REG_PATTERN_TEST(E1000_FCTTV, 0x0000FFFF, 0x0000FFFF); in e1000_reg_test()
883 REG_PATTERN_TEST(E1000_TIPG, 0x3FFFFFFF, 0x3FFFFFFF); in e1000_reg_test()
884 REG_PATTERN_TEST(E1000_TDBAH(0), 0xFFFFFFFF, 0xFFFFFFFF); in e1000_reg_test()
885 REG_PATTERN_TEST(E1000_TDLEN(0), 0x000FFF80, 0x000FFFFF); in e1000_reg_test()
887 REG_SET_AND_CHECK(E1000_RCTL, 0xFFFFFFFF, 0x00000000); in e1000_reg_test()
889 before = ((adapter->flags & FLAG_IS_ICH) ? 0x06C3B33E : 0x06DFB3FE); in e1000_reg_test()
890 REG_SET_AND_CHECK(E1000_RCTL, before, 0x003FFFFB); in e1000_reg_test()
891 REG_SET_AND_CHECK(E1000_TCTL, 0xFFFFFFFF, 0x00000000); in e1000_reg_test()
893 REG_SET_AND_CHECK(E1000_RCTL, before, 0xFFFFFFFF); in e1000_reg_test()
894 REG_PATTERN_TEST(E1000_RDBAL(0), 0xFFFFFFF0, 0xFFFFFFFF); in e1000_reg_test()
896 REG_PATTERN_TEST(E1000_TXCW, 0xC000FFFF, 0x0000FFFF); in e1000_reg_test()
897 REG_PATTERN_TEST(E1000_TDBAL(0), 0xFFFFFFF0, 0xFFFFFFFF); in e1000_reg_test()
898 REG_PATTERN_TEST(E1000_TIDV, 0x0000FFFF, 0x0000FFFF); in e1000_reg_test()
899 mask = 0x8003FFFF; in e1000_reg_test()
921 for (i = 0; i < mac->rar_entry_count; i++) { in e1000_reg_test()
934 /* SHRAH[0,1,2] different than previous */ in e1000_reg_test()
936 mask &= 0xFFF4FFFF; in e1000_reg_test()
937 /* SHRAH[3] different than SHRAH[0,1,2] */ in e1000_reg_test()
941 if (i > 0) in e1000_reg_test()
946 0xFFFFFFFF); in e1000_reg_test()
952 for (i = 0; i < mac->mta_reg_count; i++) in e1000_reg_test()
953 REG_PATTERN_TEST_ARRAY(E1000_MTA, i, 0xFFFFFFFF, 0xFFFFFFFF); in e1000_reg_test()
955 *data = 0; in e1000_reg_test()
957 return 0; in e1000_reg_test()
963 u16 checksum = 0; in e1000_eeprom_test()
966 *data = 0; in e1000_eeprom_test()
968 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) { in e1000_eeprom_test()
969 if ((e1000_read_nvm(&adapter->hw, i, 1, &temp)) < 0) { in e1000_eeprom_test()
1002 int ret_val = 0; in e1000_intr_test()
1005 *data = 0; in e1000_intr_test()
1017 shared_int = 0; in e1000_intr_test()
1027 ew32(IMC, 0xFFFFFFFF); in e1000_intr_test()
1032 for (i = 0; i < 10; i++) { in e1000_intr_test()
1040 case 0x00000100: in e1000_intr_test()
1057 adapter->test_icr = 0; in e1000_intr_test()
1075 adapter->test_icr = 0; in e1000_intr_test()
1093 adapter->test_icr = 0; in e1000_intr_test()
1094 ew32(IMC, ~mask & 0x00007FFF); in e1000_intr_test()
1095 ew32(ICS, ~mask & 0x00007FFF); in e1000_intr_test()
1107 ew32(IMC, 0xFFFFFFFF); in e1000_intr_test()
1133 for (i = 0; i < tx_ring->count; i++) { in e1000_free_desc_rings()
1146 for (i = 0; i < rx_ring->count; i++) { in e1000_free_desc_rings()
1204 tx_ring->next_to_use = 0; in e1000_setup_desc_rings()
1205 tx_ring->next_to_clean = 0; in e1000_setup_desc_rings()
1207 ew32(TDBAL(0), ((u64)tx_ring->dma & 0x00000000FFFFFFFF)); in e1000_setup_desc_rings()
1208 ew32(TDBAH(0), ((u64)tx_ring->dma >> 32)); in e1000_setup_desc_rings()
1209 ew32(TDLEN(0), tx_ring->count * sizeof(struct e1000_tx_desc)); in e1000_setup_desc_rings()
1210 ew32(TDH(0), 0); in e1000_setup_desc_rings()
1211 ew32(TDT(0), 0); in e1000_setup_desc_rings()
1216 for (i = 0; i < tx_ring->count; i++) { in e1000_setup_desc_rings()
1242 tx_desc->upper.data = 0; in e1000_setup_desc_rings()
1264 rx_ring->next_to_use = 0; in e1000_setup_desc_rings()
1265 rx_ring->next_to_clean = 0; in e1000_setup_desc_rings()
1270 ew32(RDBAL(0), ((u64)rx_ring->dma & 0xFFFFFFFF)); in e1000_setup_desc_rings()
1271 ew32(RDBAH(0), ((u64)rx_ring->dma >> 32)); in e1000_setup_desc_rings()
1272 ew32(RDLEN(0), rx_ring->size); in e1000_setup_desc_rings()
1273 ew32(RDH(0), 0); in e1000_setup_desc_rings()
1274 ew32(RDT(0), 0); in e1000_setup_desc_rings()
1282 for (i = 0; i < rx_ring->count; i++) { in e1000_setup_desc_rings()
1304 memset(skb->data, 0x00, skb->len); in e1000_setup_desc_rings()
1307 return 0; in e1000_setup_desc_rings()
1317 e1e_wphy(&adapter->hw, 29, 0x001F); in e1000_phy_disable_receiver()
1318 e1e_wphy(&adapter->hw, 30, 0x8FFC); in e1000_phy_disable_receiver()
1319 e1e_wphy(&adapter->hw, 29, 0x001A); in e1000_phy_disable_receiver()
1320 e1e_wphy(&adapter->hw, 30, 0x8FF0); in e1000_phy_disable_receiver()
1326 u32 ctrl_reg = 0; in e1000_integrated_phy_loopback()
1327 u16 phy_reg = 0; in e1000_integrated_phy_loopback()
1328 s32 ret_val = 0; in e1000_integrated_phy_loopback()
1330 hw->mac.autoneg = 0; in e1000_integrated_phy_loopback()
1334 e1e_wphy(hw, MII_BMCR, 0x6100); in e1000_integrated_phy_loopback()
1348 return 0; in e1000_integrated_phy_loopback()
1355 e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, 0x0808); in e1000_integrated_phy_loopback()
1357 e1e_wphy(hw, MII_BMCR, 0x9140); in e1000_integrated_phy_loopback()
1359 e1e_wphy(hw, MII_BMCR, 0x8140); in e1000_integrated_phy_loopback()
1362 e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, 0x1CC); in e1000_integrated_phy_loopback()
1367 phy_reg &= ~0x0007; in e1000_integrated_phy_loopback()
1368 phy_reg |= 0x006; in e1000_integrated_phy_loopback()
1375 e1e_wphy(hw, PHY_REG(769, 16), phy_reg | 0x000C); in e1000_integrated_phy_loopback()
1378 e1e_wphy(hw, PHY_REG(776, 16), phy_reg | 0x0040); in e1000_integrated_phy_loopback()
1381 e1e_wphy(hw, PHY_REG(769, 16), phy_reg | 0x0040); in e1000_integrated_phy_loopback()
1384 e1e_wphy(hw, PHY_REG(769, 20), phy_reg | 0x0400); in e1000_integrated_phy_loopback()
1399 e1e_rphy(hw, PHY_REG(0, 21), &phy_reg); in e1000_integrated_phy_loopback()
1400 e1e_wphy(hw, PHY_REG(0, 21), phy_reg & ~BIT(3)); in e1000_integrated_phy_loopback()
1405 e1e_wphy(hw, I82577_PHY_LBK_CTRL, 0x8001); in e1000_integrated_phy_loopback()
1412 e1e_wphy(hw, MII_BMCR, 0x4140); in e1000_integrated_phy_loopback()
1433 if ((er32(STATUS) & E1000_STATUS_FD) == 0) in e1000_integrated_phy_loopback()
1447 return 0; in e1000_integrated_phy_loopback()
1485 return 0; in e1000_set_82571_fiber_loopback()
1516 #define KMRNCTRLSTA_OPMODE (0x1F << 16) in e1000_set_es2lan_mac_loopback()
1517 #define KMRNCTRLSTA_OPMODE_1GB_FD_GMII 0x0582 in e1000_set_es2lan_mac_loopback()
1521 return 0; in e1000_set_es2lan_mac_loopback()
1533 tarc0 = er32(TARC(0)); in e1000_setup_loopback_test()
1535 tarc0 &= 0xcfffffff; in e1000_setup_loopback_test()
1537 tarc0 |= 0x20000000; in e1000_setup_loopback_test()
1538 ew32(TARC(0), tarc0); in e1000_setup_loopback_test()
1552 return 0; in e1000_setup_loopback_test()
1581 tarc0 = er32(TARC(0)); in e1000_loopback_cleanup()
1583 /* set bit 29 (value of MULR requests is now 0) */ in e1000_loopback_cleanup()
1584 tarc0 &= 0xcfffffff; in e1000_loopback_cleanup()
1585 ew32(TARC(0), tarc0); in e1000_loopback_cleanup()
1592 adapter->tx_fifo_head = 0; in e1000_loopback_cleanup()
1608 e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, 0x180); in e1000_loopback_cleanup()
1623 memset(skb->data, 0xFF, frame_size); in e1000_create_lbtest_frame()
1625 memset(&skb->data[frame_size / 2], 0xAA, frame_size / 2 - 1); in e1000_create_lbtest_frame()
1626 skb->data[frame_size / 2 + 10] = 0xBE; in e1000_create_lbtest_frame()
1627 skb->data[frame_size / 2 + 12] = 0xAF; in e1000_create_lbtest_frame()
1634 if (*(skb->data + 3) == 0xFF) in e1000_check_lbtest_frame()
1635 if ((*(skb->data + frame_size / 2 + 10) == 0xBE) && in e1000_check_lbtest_frame()
1636 (*(skb->data + frame_size / 2 + 12) == 0xAF)) in e1000_check_lbtest_frame()
1637 return 0; in e1000_check_lbtest_frame()
1651 int ret_val = 0; in e1000_run_loopback_test()
1654 ew32(RDT(0), rx_ring->count - 1); in e1000_run_loopback_test()
1666 k = 0; in e1000_run_loopback_test()
1667 l = 0; in e1000_run_loopback_test()
1669 for (j = 0; j <= lc; j++) { in e1000_run_loopback_test()
1671 for (i = 0; i < 64; i++) { in e1000_run_loopback_test()
1681 k = 0; in e1000_run_loopback_test()
1683 ew32(TDT(0), k); in e1000_run_loopback_test()
1687 good_cnt = 0; in e1000_run_loopback_test()
1702 l = 0; in e1000_run_loopback_test()
1728 *data = 0; in e1000_loopback_test()
1753 *data = 0; in e1000_link_test()
1755 int i = 0; in e1000_link_test()
1821 adapter->hw.phy.autoneg_wait_to_complete = 0; in e1000_diag_test()
1838 if (e1000_reg_test(adapter, &data[0])) in e1000_diag_test()
1856 adapter->hw.phy.autoneg_wait_to_complete = 0; in e1000_diag_test()
1876 data[0] = 0; in e1000_diag_test()
1877 data[1] = 0; in e1000_diag_test()
1878 data[2] = 0; in e1000_diag_test()
1879 data[3] = 0; in e1000_diag_test()
1904 wol->supported = 0; in e1000_get_wol()
1905 wol->wolopts = 0; in e1000_get_wol()
1945 adapter->wol = 0; in e1000_set_wol()
1960 return 0; in e1000_set_wol()
1981 e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0); in e1000_set_phys_id()
1996 return 0; in e1000_set_phys_id()
2011 return 0; in e1000_get_coalesce()
2040 if (adapter->itr_setting != 0) in e1000_set_coalesce()
2043 e1000e_write_itr(adapter, 0); in e1000_set_coalesce()
2047 return 0; in e1000_set_coalesce()
2064 return 0; in e1000_nway_reset()
2082 for (i = 0; i < E1000_GLOBAL_STATS_LEN; i++) { in e1000_get_ethtool_stats()
2093 data[i] = 0; in e1000_get_ethtool_stats()
2113 for (i = 0; i < E1000_GLOBAL_STATS_LEN; i++) { in e1000_get_strings()
2130 info->data = 0; in e1000_get_rxnfc()
2143 return 0; in e1000_get_rxnfc()
2171 return 0; in e1000_get_rxnfc()
2294 return 0; in e1000e_set_eee()
2305 return 0; in e1000e_get_ts_info()
2328 return 0; in e1000e_get_ts_info()
2334 u32 priv_flags = 0; in e1000e_get_priv_flags()
2359 return 0; in e1000e_set_priv_flags()