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/Linux-v6.1/include/linux/ssb/
Dssb_driver_extif.h24 #define SSB_EXTIF_PCMCIA_IOBASE(x) ((x) + 0x100000)
25 #define SSB_EXTIF_PCMCIA_CFGBASE(x) ((x) + 0x200000)
26 #define SSB_EXTIF_CFGIF_BASE(x) ((x) + 0x800000)
27 #define SSB_EXTIF_FLASH_BASE(x) ((x) + 0xc00000)
47 #define SSB_EXTIF_CTL 0x0000
48 #define SSB_EXTIF_CTL_UARTEN (1 << 0) /* UART enable */
49 #define SSB_EXTIF_EXTSTAT 0x0004
50 #define SSB_EXTIF_EXTSTAT_EMODE (1 << 0) /* Endian mode (ro) */
53 #define SSB_EXTIF_PCMCIA_CFG 0x0010
54 #define SSB_EXTIF_PCMCIA_MEMWAIT 0x0014
[all …]
/Linux-v6.1/arch/arm/boot/dts/
Dmstar-v7.dtsi18 #size-cells = <0>;
20 cpu0: cpu@0 {
23 reg = <0x0>;
55 #clock-cells = <0>;
61 #clock-cells = <0>;
68 #clock-cells = <0>;
80 ranges = <0x16001000 0x16001000 0x00007000>,
81 <0x1f000000 0x1f000000 0x00400000>,
82 <0xa0000000 0xa0000000 0x20000>;
86 reg = <0x16001000 0x1000>,
[all …]
/Linux-v6.1/arch/mips/boot/dts/lantiq/
Ddanube.dtsi8 cpu@0 {
17 reg = <0x1f800000 0x800000>;
18 ranges = <0x0 0x1f800000 0x7fffff>;
24 reg = <0x80200 0x120>;
29 reg = <0x803f0 0x10>;
37 reg = <0x1f000000 0x800000>;
38 ranges = <0x0 0x1f000000 0x7fffff>;
45 reg = <0x101000 0x1000>;
50 reg = <0x102000 0x1000>;
55 reg = <0x103000 0x1000>;
[all …]
/Linux-v6.1/arch/mips/include/asm/sgi/
Dgio.h23 * 0 GFX 0x1f000000 - 0x1f3fffff 4MB
24 * 1 EXP0 0x1f400000 - 0x1f5fffff 2MB
25 * 2 EXP1 0x1f600000 - 0x1f9fffff 4MB
29 * - MISC 0x1fb00000 - 0x1fbfffff 1MB
32 * - RESERVED 0x18000000 - 0x1effffff 112MB
42 * bits 0:6 the product ID; ranges from 0x00 to 0x7F.
43 * bit 7 0=GIO Product ID is 8 bits wide
46 * bit 16 0=GIO32 and GIO32-bis, 1=GIO64.
47 * bit 17 0=no ROM present
52 * IDs above 0x50/0xd0 are of 3rd party boards.
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/interrupt-controller/
Dgoogle,goldfish-pic.txt15 #interrupt-cells = <0x1>;
16 #address-cells = <0>;
23 reg = <0x1f000000 0x1000>;
26 #interrupt-cells = <0x1>;
29 interrupts = <0x2>;
/Linux-v6.1/Documentation/devicetree/bindings/spi/
Dspi-ath79.txt9 - #size-cells: <0>, also as required by generic SPI binding.
17 reg = <0x1f000000 0x10>;
23 #size-cells = <0>;
Dmikrotik,rb4xx-spi.yaml33 #size-cells = <0>;
35 reg = <0x1f000000 0x10>;
Dqca,ar934x-spi.yaml39 reg = <0x1f000000 0x1c>;
42 #size-cells = <0>;
/Linux-v6.1/arch/mips/cobalt/
Dlcd.c13 .start = 0x1f000000,
14 .end = 0x1f00001f,
35 return 0; in cobalt_lcd_add()
/Linux-v6.1/arch/mips/boot/dts/ralink/
Drt2880_eval.dts10 memory@0 {
12 reg = <0x8000000 0x2000000>;
21 reg = <0x1f000000 0x400000>;
28 partition@0 {
30 reg = <0x0 0x30000>;
35 reg = <0x30000 0x10000>;
40 reg = <0x40000 0x10000>;
45 reg = <0x50000 0x3b0000>;
Drt3052_eval.dts10 memory@0 {
12 reg = <0x0 0x2000000>;
21 reg = <0x1f000000 0x800000>;
28 partition@0 {
30 reg = <0x0 0x30000>;
35 reg = <0x30000 0x10000>;
40 reg = <0x40000 0x10000>;
45 reg = <0x50000 0x7b0000>;
/Linux-v6.1/drivers/gpu/drm/nouveau/nvkm/subdev/fault/
Dgv100.c43 const u32 instlo = nvkm_ro32(mem, base + 0x00); in gv100_fault_buffer_process()
44 const u32 insthi = nvkm_ro32(mem, base + 0x04); in gv100_fault_buffer_process()
45 const u32 addrlo = nvkm_ro32(mem, base + 0x08); in gv100_fault_buffer_process()
46 const u32 addrhi = nvkm_ro32(mem, base + 0x0c); in gv100_fault_buffer_process()
47 const u32 timelo = nvkm_ro32(mem, base + 0x10); in gv100_fault_buffer_process()
48 const u32 timehi = nvkm_ro32(mem, base + 0x14); in gv100_fault_buffer_process()
49 const u32 info0 = nvkm_ro32(mem, base + 0x18); in gv100_fault_buffer_process()
50 const u32 info1 = nvkm_ro32(mem, base + 0x1c); in gv100_fault_buffer_process()
54 get = 0; in gv100_fault_buffer_process()
60 info.engine = (info0 & 0x000000ff); in gv100_fault_buffer_process()
[all …]
/Linux-v6.1/drivers/misc/habanalabs/include/goya/
Dgoya_packets.h14 #define PACKET_HEADER_PACKET_ID_MASK 0x1F00000000000000ull
17 PACKET_WREG_32 = 0x1,
18 PACKET_WREG_BULK = 0x2,
19 PACKET_MSG_LONG = 0x3,
20 PACKET_MSG_SHORT = 0x4,
21 PACKET_CP_DMA = 0x5,
22 PACKET_MSG_PROT = 0x7,
23 PACKET_FENCE = 0x8,
24 PACKET_LIN_DMA = 0x9,
25 PACKET_NOP = 0xA,
[all …]
/Linux-v6.1/include/linux/bcma/
Dbcma_driver_gmac_cmn.h7 #define BCMA_GMAC_CMN_STAG0 0x000
8 #define BCMA_GMAC_CMN_STAG1 0x004
9 #define BCMA_GMAC_CMN_STAG2 0x008
10 #define BCMA_GMAC_CMN_STAG3 0x00C
11 #define BCMA_GMAC_CMN_PARSER_CTL 0x020
12 #define BCMA_GMAC_CMN_MIB_MAX_LEN 0x024
13 #define BCMA_GMAC_CMN_PHY_ACCESS 0x100
14 #define BCMA_GMAC_CMN_PA_DATA_MASK 0x0000ffff
15 #define BCMA_GMAC_CMN_PA_ADDR_MASK 0x001f0000
17 #define BCMA_GMAC_CMN_PA_REG_MASK 0x1f000000
[all …]
/Linux-v6.1/drivers/misc/habanalabs/include/gaudi2/
Dgaudi2_packets.h14 #define PACKET_HEADER_PACKET_ID_MASK 0x1F00000000000000ull
17 PACKET_WREG_32 = 0x1,
18 PACKET_WREG_BULK = 0x2,
19 PACKET_MSG_LONG = 0x3,
20 PACKET_MSG_SHORT = 0x4,
21 PACKET_CP_DMA = 0x5,
22 PACKET_REPEAT = 0x6,
23 PACKET_MSG_PROT = 0x7,
24 PACKET_FENCE = 0x8,
25 PACKET_LIN_DMA = 0x9,
[all …]
/Linux-v6.1/drivers/misc/habanalabs/include/gaudi/
Dgaudi_packets.h14 #define PACKET_HEADER_PACKET_ID_MASK 0x1F00000000000000ull
17 PACKET_WREG_32 = 0x1,
18 PACKET_WREG_BULK = 0x2,
19 PACKET_MSG_LONG = 0x3,
20 PACKET_MSG_SHORT = 0x4,
21 PACKET_CP_DMA = 0x5,
22 PACKET_REPEAT = 0x6,
23 PACKET_MSG_PROT = 0x7,
24 PACKET_FENCE = 0x8,
25 PACKET_LIN_DMA = 0x9,
[all …]
/Linux-v6.1/arch/mips/boot/dts/mti/
Dmalta.dts7 /memreserve/ 0x00000000 0x00001000; /* YAMON exception vectors */
8 /memreserve/ 0x00001000 0x000ef000; /* YAMON */
9 /memreserve/ 0x000f0000 0x00010000; /* PIIX4 ISA memory */
25 reg = <0x1bdc0000 0x20000>;
56 reg = <0x1e000000 0x400000>;
66 yamon@0 {
68 reg = <0x0 0x100000>;
74 reg = <0x100000 0x2e0000>;
79 reg = <0x3e0000 0x20000>;
87 reg = <0x1f000000 0x1000>;
[all …]
/Linux-v6.1/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/
Dgf119.c35 while ((entry = dcb_gpio_entry(bios, 0, ++ent, &ver, &len))) { in gf119_gpio_reset()
37 u8 line = (data & 0x0000003f); in gf119_gpio_reset()
38 u8 defs = !!(data & 0x00000080); in gf119_gpio_reset()
39 u8 func = (data & 0x0000ff00) >> 8; in gf119_gpio_reset()
40 u8 unk0 = (data & 0x00ff0000) >> 16; in gf119_gpio_reset()
41 u8 unk1 = (data & 0x1f000000) >> 24; in gf119_gpio_reset()
47 nvkm_gpio_set(gpio, 0, func, line, defs); in gf119_gpio_reset()
49 nvkm_mask(device, 0x00d610 + (line * 4), 0xff, unk0); in gf119_gpio_reset()
51 nvkm_mask(device, 0x00d740 + (unk1 * 4), 0xff, line); in gf119_gpio_reset()
60 nvkm_mask(device, 0x00d610 + (line * 4), 0x00003000, data); in gf119_gpio_drive()
[all …]
Dga102.c33 while ((entry = dcb_gpio_entry(bios, 0, ++ent, &ver, &len))) { in ga102_gpio_reset()
35 u8 line = (data & 0x0000003f); in ga102_gpio_reset()
36 u8 defs = !!(data & 0x00000080); in ga102_gpio_reset()
37 u8 func = (data & 0x0000ff00) >> 8; in ga102_gpio_reset()
38 u8 unk0 = (data & 0x00ff0000) >> 16; in ga102_gpio_reset()
39 u8 unk1 = (data & 0x1f000000) >> 24; in ga102_gpio_reset()
45 nvkm_gpio_set(gpio, 0, func, line, defs); in ga102_gpio_reset()
47 nvkm_mask(device, 0x021200 + (line * 4), 0xff, unk0); in ga102_gpio_reset()
49 nvkm_mask(device, 0x00d740 + (unk1 * 4), 0xff, line); in ga102_gpio_reset()
58 nvkm_mask(device, 0x021200 + (line * 4), 0x00003000, data); in ga102_gpio_drive()
[all …]
/Linux-v6.1/drivers/staging/rtl8192e/rtl8192e/
Dr8192E_phyreg.h11 #define RF_DATA 0x1d4
13 #define rPMAC_Reset 0x100
14 #define rPMAC_TxStart 0x104
15 #define rPMAC_TxLegacySIG 0x108
16 #define rPMAC_TxHTSIG1 0x10c
17 #define rPMAC_TxHTSIG2 0x110
18 #define rPMAC_PHYDebug 0x114
19 #define rPMAC_TxPacketNum 0x118
20 #define rPMAC_TxIdle 0x11c
21 #define rPMAC_TxMACHeader0 0x120
[all …]
/Linux-v6.1/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
Dgp100.c33 { 0x01, "DISPLAY" },
34 { 0x03, "IFB", NULL, NVKM_ENGINE_IFB },
35 { 0x04, "BAR1", NULL, NVKM_SUBDEV_BAR },
36 { 0x05, "BAR2", NULL, NVKM_SUBDEV_INSTMEM },
37 { 0x06, "HOST0", NULL, NVKM_ENGINE_FIFO },
38 { 0x07, "HOST1", NULL, NVKM_ENGINE_FIFO },
39 { 0x08, "HOST2", NULL, NVKM_ENGINE_FIFO },
40 { 0x09, "HOST3", NULL, NVKM_ENGINE_FIFO },
41 { 0x0a, "HOST4", NULL, NVKM_ENGINE_FIFO },
42 { 0x0b, "HOST5", NULL, NVKM_ENGINE_FIFO },
[all …]
Dgm107.c36 nvkm_wo32(memory, offset + 0, chan->base.chid); in gm107_fifo_runlist_chan()
50 { 0x01, "DISPLAY" },
51 { 0x02, "CAPTURE" },
52 { 0x03, "IFB", NULL, NVKM_ENGINE_IFB },
53 { 0x04, "BAR1", NULL, NVKM_SUBDEV_BAR },
54 { 0x05, "BAR2", NULL, NVKM_SUBDEV_INSTMEM },
55 { 0x06, "SCHED" },
56 { 0x07, "HOST0", NULL, NVKM_ENGINE_FIFO },
57 { 0x08, "HOST1", NULL, NVKM_ENGINE_FIFO },
58 { 0x09, "HOST2", NULL, NVKM_ENGINE_FIFO },
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/memory-controllers/
Darm,pl172.txt11 first address cell and it may accept values 0..N-1
88 Example for pl172 with nor flash on chip select 0 shown below.
92 reg = <0x40005000 0x1000>;
97 ranges = <0 0 0x1c000000 0x1000000
98 1 0 0x1d000000 0x1000000
99 2 0 0x1e000000 0x1000000
100 3 0 0x1f000000 0x1000000>;
107 mpmc,cs = <0>;
110 mpmc,write-enable-delay = <0>;
111 mpmc,output-enable-delay = <0>;
[all …]
/Linux-v6.1/arch/mips/boot/dts/qca/
Dar9132.dtsi12 #size-cells = <0>;
14 cpu@0 {
18 reg = <0>;
30 <&ddr_ctrl 0>, <&ddr_ctrl 1>;
54 reg = <0x18000000 0x100>;
61 reg = <0x18020000 0x20>;
77 reg = <0x18040000 0x30>;
92 reg = <0x18050000 0x20>;
103 reg = <0x18060008 0x8>;
114 reg = <0x18060010 0x8>;
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/arm/mediatek/
Dmediatek,mt8192-clock.yaml56 reg = <0x10720000 0x1000>;
63 reg = <0x11007000 0x1000>;
70 reg = <0x11cb1000 0x1000>;
77 reg = <0x11d03000 0x1000>;
84 reg = <0x11d23000 0x1000>;
91 reg = <0x11e01000 0x1000>;
98 reg = <0x11f02000 0x1000>;
105 reg = <0x11f10000 0x1000>;
112 reg = <0x13fbf000 0x1000>;
119 reg = <0x15020000 0x1000>;
[all …]

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