Lines Matching +full:0 +full:x1f000000
33 { 0x01, "DISPLAY" },
34 { 0x03, "IFB", NULL, NVKM_ENGINE_IFB },
35 { 0x04, "BAR1", NULL, NVKM_SUBDEV_BAR },
36 { 0x05, "BAR2", NULL, NVKM_SUBDEV_INSTMEM },
37 { 0x06, "HOST0", NULL, NVKM_ENGINE_FIFO },
38 { 0x07, "HOST1", NULL, NVKM_ENGINE_FIFO },
39 { 0x08, "HOST2", NULL, NVKM_ENGINE_FIFO },
40 { 0x09, "HOST3", NULL, NVKM_ENGINE_FIFO },
41 { 0x0a, "HOST4", NULL, NVKM_ENGINE_FIFO },
42 { 0x0b, "HOST5", NULL, NVKM_ENGINE_FIFO },
43 { 0x0c, "HOST6", NULL, NVKM_ENGINE_FIFO },
44 { 0x0d, "HOST7", NULL, NVKM_ENGINE_FIFO },
45 { 0x0e, "HOST8", NULL, NVKM_ENGINE_FIFO },
46 { 0x0f, "HOST9", NULL, NVKM_ENGINE_FIFO },
47 { 0x10, "HOST10", NULL, NVKM_ENGINE_FIFO },
48 { 0x13, "PERF" },
49 { 0x17, "PMU" },
50 { 0x18, "PTP" },
51 { 0x1f, "PHYSICAL" },
59 u32 inst = nvkm_rd32(device, 0x002800 + (unit * 0x10)); in gp100_fifo_intr_fault()
60 u32 valo = nvkm_rd32(device, 0x002804 + (unit * 0x10)); in gp100_fifo_intr_fault()
61 u32 vahi = nvkm_rd32(device, 0x002808 + (unit * 0x10)); in gp100_fifo_intr_fault()
62 u32 type = nvkm_rd32(device, 0x00280c + (unit * 0x10)); in gp100_fifo_intr_fault()
67 info.time = 0; in gp100_fifo_intr_fault()
70 info.gpc = (type & 0x1f000000) >> 24; in gp100_fifo_intr_fault()
71 info.hub = (type & 0x00100000) >> 20; in gp100_fifo_intr_fault()
72 info.access = (type & 0x00070000) >> 16; in gp100_fifo_intr_fault()
73 info.client = (type & 0x00007f00) >> 8; in gp100_fifo_intr_fault()
74 info.reason = (type & 0x0000001f); in gp100_fifo_intr_fault()
89 .chan = {{0,0,PASCAL_CHANNEL_GPFIFO_A}, gk104_fifo_gpfifo_new },