Lines Matching +full:0 +full:x1f000000
36 nvkm_wo32(memory, offset + 0, chan->base.chid); in gm107_fifo_runlist_chan()
50 { 0x01, "DISPLAY" },
51 { 0x02, "CAPTURE" },
52 { 0x03, "IFB", NULL, NVKM_ENGINE_IFB },
53 { 0x04, "BAR1", NULL, NVKM_SUBDEV_BAR },
54 { 0x05, "BAR2", NULL, NVKM_SUBDEV_INSTMEM },
55 { 0x06, "SCHED" },
56 { 0x07, "HOST0", NULL, NVKM_ENGINE_FIFO },
57 { 0x08, "HOST1", NULL, NVKM_ENGINE_FIFO },
58 { 0x09, "HOST2", NULL, NVKM_ENGINE_FIFO },
59 { 0x0a, "HOST3", NULL, NVKM_ENGINE_FIFO },
60 { 0x0b, "HOST4", NULL, NVKM_ENGINE_FIFO },
61 { 0x0c, "HOST5", NULL, NVKM_ENGINE_FIFO },
62 { 0x0d, "HOST6", NULL, NVKM_ENGINE_FIFO },
63 { 0x0e, "HOST7", NULL, NVKM_ENGINE_FIFO },
64 { 0x0f, "HOSTSR" },
65 { 0x13, "PERF" },
66 { 0x17, "PMU" },
67 { 0x18, "PTP" },
75 u32 inst = nvkm_rd32(device, 0x002800 + (unit * 0x10)); in gm107_fifo_intr_fault()
76 u32 valo = nvkm_rd32(device, 0x002804 + (unit * 0x10)); in gm107_fifo_intr_fault()
77 u32 vahi = nvkm_rd32(device, 0x002808 + (unit * 0x10)); in gm107_fifo_intr_fault()
78 u32 type = nvkm_rd32(device, 0x00280c + (unit * 0x10)); in gm107_fifo_intr_fault()
83 info.time = 0; in gm107_fifo_intr_fault()
86 info.gpc = (type & 0x1f000000) >> 24; in gm107_fifo_intr_fault()
87 info.client = (type & 0x00003f00) >> 8; in gm107_fifo_intr_fault()
88 info.access = (type & 0x00000080) >> 7; in gm107_fifo_intr_fault()
89 info.hub = (type & 0x00000040) >> 6; in gm107_fifo_intr_fault()
90 info.reason = (type & 0x0000000f); in gm107_fifo_intr_fault()
105 .chan = {{0,0,KEPLER_CHANNEL_GPFIFO_B}, gk104_fifo_gpfifo_new },