Home
last modified time | relevance | path

Searched +full:0 +full:x1e0 (Results 1 – 25 of 187) sorted by relevance

12345678

/Linux-v5.10/Documentation/admin-guide/
Dramoops.rst27 Typically the default value of ``mem_type=0`` should be used as that sets the pstore
42 ``max_reason`` should be set to 1 (KMSG_DUMP_PANIC). Setting this to 0
67 mem=128M ramoops.mem_address=0x8000000 ramoops.ecc=1
80 reg = <0 0x8f000000 0 0x100000>;
81 record-size = <0x4000>;
82 console-size = <0x4000>;
153 0 ffffffff8101ea64 ffffffff8101bcda native_apic_mem_read <- disconnect_bsp_APIC+0x6a/0xc0
154 0 ffffffff8101ea44 ffffffff8101bcf6 native_apic_mem_write <- disconnect_bsp_APIC+0x86/0xc0
155 0 ffffffff81020084 ffffffff8101a4b5 hpet_disable <- native_machine_shutdown+0x75/0x90
156 0 ffffffff81005f94 ffffffff8101a4bb iommu_shutdown_noop <- native_machine_shutdown+0x7b/0x90
[all …]
/Linux-v5.10/drivers/firewire/
Dohci.h7 #define OHCI1394_Version 0x000
8 #define OHCI1394_GUID_ROM 0x004
9 #define OHCI1394_ATRetries 0x008
10 #define OHCI1394_CSRData 0x00C
11 #define OHCI1394_CSRCompareData 0x010
12 #define OHCI1394_CSRControl 0x014
13 #define OHCI1394_ConfigROMhdr 0x018
14 #define OHCI1394_BusID 0x01C
15 #define OHCI1394_BusOptions 0x020
16 #define OHCI1394_GUIDHi 0x024
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/pinctrl/
Daspeed,ast2500-pinctrl.yaml35 0: compatible with "aspeed,ast2500-gfx", "syscon"
81 reg = <0x1e6e2000 0x1a8>;
101 reg = <0x1e6e6000 0x1000>;
107 reg = <0x1e789000 0x1000>;
111 ranges = <0x0 0x1e789000 0x1000>;
115 reg = <0x80 0x1e0>;
120 ranges = <0x0 0x80 0x1e0>;
124 reg = <0x20 0x24>, <0x48 0x8>;
Dti,iodelay.txt24 reg = <0x4844a000 0x0d1c>;
26 #size-cells = <0>;
35 0x18c A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A19_IN */
36 0x1a4 A_DELAY_PS(265) G_DELAY_PS(360) /* CFG_GPMC_A20_IN */
37 0x1b0 A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A21_IN */
38 0x1bc A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A22_IN */
39 0x1c8 A_DELAY_PS(287) G_DELAY_PS(420) /* CFG_GPMC_A23_IN */
40 0x1d4 A_DELAY_PS(144) G_DELAY_PS(240) /* CFG_GPMC_A24_IN */
41 0x1e0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_IN */
42 0x1ec A_DELAY_PS(120) G_DELAY_PS(0) /* CFG_GPMC_A26_IN */
[all …]
/Linux-v5.10/sound/pci/ice1712/
Dwm8766.h13 #define WM8766_REG_DACL1 0x00
14 #define WM8766_REG_DACR1 0x01
15 #define WM8766_VOL_MASK 0x1ff /* incl. update bit */
17 #define WM8766_REG_DACCTRL1 0x02
18 #define WM8766_DAC_MUTEALL (1 << 0)
23 #define WM8766_DAC_PL_MASK 0x1e0
30 #define WM8766_REG_IFCTRL 0x03
31 #define WM8766_IF_FMT_RIGHTJ (0 << 0)
32 #define WM8766_IF_FMT_LEFTJ (1 << 0)
33 #define WM8766_IF_FMT_I2S (2 << 0)
[all …]
/Linux-v5.10/drivers/phy/qualcomm/
Dphy-qcom-qmp.h10 #define QSERDES_COM_BG_TIMER 0x00c
11 #define QSERDES_COM_SSC_EN_CENTER 0x010
12 #define QSERDES_COM_SSC_ADJ_PER1 0x014
13 #define QSERDES_COM_SSC_ADJ_PER2 0x018
14 #define QSERDES_COM_SSC_PER1 0x01c
15 #define QSERDES_COM_SSC_PER2 0x020
16 #define QSERDES_COM_SSC_STEP_SIZE1 0x024
17 #define QSERDES_COM_SSC_STEP_SIZE2 0x028
18 #define QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x034
19 #define QSERDES_COM_CLK_ENABLE1 0x038
[all …]
/Linux-v5.10/drivers/pinctrl/samsung/
Dpinctrl-exynos-arm.c27 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
32 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
36 #define S5P_OTHERS 0xE000
73 clk_base = of_iomap(np, 0); in s5pv210_retention_init()
93 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
94 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpa1", 0x04),
95 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
96 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
97 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
98 EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
[all …]
/Linux-v5.10/Documentation/ABI/testing/
Dsysfs-driver-jz4780-efuse10 0x000 64 bit Random Number
11 0x008 128 bit Ingenic Chip ID
12 0x018 128 bit Customer ID
13 0x028 3520 bit Reserved
14 0x1E0 8 bit Protect Segment
15 0x1E1 2296 bit HDMI Key
16 0x300 2048 bit Security boot key
/Linux-v5.10/Documentation/devicetree/bindings/mfd/
Daspeed-lpc.txt6 peripheral devices, replacing the use of the ISA bus in the age of PCI[0]. The
38 [0] http://www.intel.com/design/chipsets/industry/25128901.pdf
55 - ranges: Maps 0 to the physical address and length of the LPC memory
83 - ranges: Maps 0 to the address and length of the host-related LPC memory
90 reg = <0x1e789000 0x1000>;
94 ranges = <0x0 0x1e789000 0x1000>;
96 lpc_bmc: lpc-bmc@0 {
98 reg = <0x0 0x80>;
103 reg = <0x80 0x1e0>;
108 ranges = <0x0 0x80 0x1e0>;
[all …]
/Linux-v5.10/arch/sh/drivers/pci/
Dpci-sh7780.h13 #define PCIECR 0xFE000008
14 #define PCIECR_ENBL 0x01
17 #define SH7780_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */
18 #define SH7780_PCI_CONFIG_SIZE 0x01000000 /* Config space size */
20 #define SH7780_PCIREG_BASE 0xFE040000 /* PCI regs base address */
23 #define SH7780_PCIIR 0x114 /* PCI Interrupt Register */
24 #define SH7780_PCIIMR 0x118 /* PCI Interrupt Mask Register */
25 #define SH7780_PCIAIR 0x11C /* Error Address Register */
26 #define SH7780_PCICIR 0x120 /* Error Command/Data Register */
27 #define SH7780_PCIAINT 0x130 /* Arbiter Interrupt Register */
[all …]
/Linux-v5.10/drivers/usb/host/
Dbcma-hcd.c38 #define USB_BCMA_CLKCTLST_USB_CLK_REQ 0x00000100
56 for (i = 0; i < timeout; i++) { in bcma_wait_bits()
59 return 0; in bcma_wait_bits()
70 if (dev->bus->chipinfo.id == 0x4716) { in bcma_hcd_4716wa()
75 tmp = 0x1846b; /* set CDR to 0x11(fast) */ in bcma_hcd_4716wa()
77 tmp = 0x1046b; /* set CDR to 0x10(slow) */ in bcma_hcd_4716wa()
79 tmp = 0; in bcma_hcd_4716wa()
85 bcma_write32(dev, 0x524, 0x1); /* write sel to enable */ in bcma_hcd_4716wa()
88 bcma_write32(dev, 0x524, tmp); in bcma_hcd_4716wa()
90 bcma_write32(dev, 0x524, 0x4ab); in bcma_hcd_4716wa()
[all …]
/Linux-v5.10/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_hw_catalog.c46 #define INTF_SDM845_MASK (0)
69 .max_mixer_blendstages = 0xb,
85 .max_mixer_blendstages = 0x9,
97 .max_mixer_blendstages = 0xb,
113 .max_mixer_blendstages = 0xb,
129 .base = 0x0, .len = 0x45C,
130 .features = 0,
131 .highest_bank_bit = 0x2,
133 .reg_off = 0x2AC, .bit_off = 0},
135 .reg_off = 0x2B4, .bit_off = 0},
[all …]
/Linux-v5.10/sound/isa/sb/
Demu8000_patch.c29 for (i = 0; i < EMU8000_DRAM_VOICES; i++) { in snd_emu8000_open_dma()
35 EMU8000_VTFT_WRITE(emu, 30, 0); in snd_emu8000_open_dma()
36 EMU8000_PSST_WRITE(emu, 30, 0x1d8); in snd_emu8000_open_dma()
37 EMU8000_CSL_WRITE(emu, 30, 0x1e0); in snd_emu8000_open_dma()
38 EMU8000_CCCA_WRITE(emu, 30, 0x1d8); in snd_emu8000_open_dma()
39 EMU8000_VTFT_WRITE(emu, 31, 0); in snd_emu8000_open_dma()
40 EMU8000_PSST_WRITE(emu, 31, 0x1d8); in snd_emu8000_open_dma()
41 EMU8000_CSL_WRITE(emu, 31, 0x1e0); in snd_emu8000_open_dma()
42 EMU8000_CCCA_WRITE(emu, 31, 0x1d8); in snd_emu8000_open_dma()
44 return 0; in snd_emu8000_open_dma()
[all …]
/Linux-v5.10/arch/arm/mach-tegra/
Dirq.c26 #define SGI_MASK 0xFFFF
51 writel_relaxed(0x1E0, tegra_gic_cpu_base + GIC_CPU_CTRL); in tegra_gic_notifier()
/Linux-v5.10/drivers/media/platform/coda/
Dcoda_regs.h14 #define CODA_REG_BIT_CODE_RUN 0x000
15 #define CODA_REG_RUN_ENABLE (1 << 0)
16 #define CODA_REG_BIT_CODE_DOWN 0x004
17 #define CODA_DOWN_ADDRESS_SET(x) (((x) & 0xffff) << 16)
18 #define CODA_DOWN_DATA_SET(x) ((x) & 0xffff)
19 #define CODA_REG_BIT_HOST_IN_REQ 0x008
20 #define CODA_REG_BIT_INT_CLEAR 0x00c
21 #define CODA_REG_BIT_INT_CLEAR_SET 0x1
22 #define CODA_REG_BIT_INT_STATUS 0x010
23 #define CODA_REG_BIT_CODE_RESET 0x014
[all …]
/Linux-v5.10/drivers/net/wireless/mediatek/mt7601u/
Deeprom.h12 #define MT7601U_EE_MAX_VER 0x0d
18 MT_EE_CHIP_ID = 0x00,
19 MT_EE_VERSION_FAE = 0x02,
20 MT_EE_VERSION_EE = 0x03,
21 MT_EE_MAC_ADDR = 0x04,
22 MT_EE_NIC_CONF_0 = 0x34,
23 MT_EE_NIC_CONF_1 = 0x36,
24 MT_EE_COUNTRY_REGION = 0x39,
25 MT_EE_FREQ_OFFSET = 0x3a,
26 MT_EE_NIC_CONF_2 = 0x42,
[all …]
/Linux-v5.10/arch/arm64/boot/dts/freescale/
Dimx8mn-pinfunc.h14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0
15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3
16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0
17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3
18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0
20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
[all …]
Dimx8mp-pinfunc.h13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0
14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0
15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0
16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0
17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0
18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0
19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0
20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0
21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0
22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0
[all …]
Dimx8mq-pinfunc.h15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0…
16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0…
17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0…
18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0…
19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0…
20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
[all …]
/Linux-v5.10/arch/sh/kernel/cpu/sh4a/
Dubc.c15 #define UBC_CBR(idx) (0xff200000 + (0x20 * idx))
16 #define UBC_CRR(idx) (0xff200004 + (0x20 * idx))
17 #define UBC_CAR(idx) (0xff200008 + (0x20 * idx))
18 #define UBC_CAMR(idx) (0xff20000c + (0x20 * idx))
20 #define UBC_CCMFR 0xff200600
21 #define UBC_CBCR 0xff200620
25 #define UBC_CRR_BIE (1 << 0)
28 #define UBC_CBR_CE (1 << 0)
40 __raw_writel(0, UBC_CBR(idx)); in sh4a_ubc_disable()
41 __raw_writel(0, UBC_CAR(idx)); in sh4a_ubc_disable()
[all …]
/Linux-v5.10/arch/mips/loongson64/
Dinit.c21 #define NODE_ID_OFFSET_ADDR ((void __iomem *)TO_UNCAC(0x1001041c))
30 base = (void *)(CAC_BASE + 0x380); in mips_nmi_setup()
31 memcpy(base, except_vec_nmi, 0x80); in mips_nmi_setup()
32 flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); in mips_nmi_setup()
37 node_id_offset = ((readl(NODE_ID_OFFSET_ADDR) >> 8) & 0x1f) + 36; in ls7a_early_config()
62 /* Hardcode to CPU UART 0 */ in prom_init()
63 setup_8250_early_printk_port(TO_UNCAC(LOONGSON_REG_BASE + 0x1e0), 0, 1024); in prom_init()
76 int ret = 0; in add_legacy_isa_io()
96 if (range->io_start != 0) { in add_legacy_isa_io()
106 return 0; in add_legacy_isa_io()
[all …]
/Linux-v5.10/arch/powerpc/mm/nohash/
Dtlb.c143 return 0; in mmu_get_tsize()
209 pid = mm ? mm->context.id : 0; in __local_flush_tlb_page()
218 mmu_get_tsize(mmu_virtual_psize), 0); in local_flush_tlb_page()
240 _tlbil_pid(p ? p->pid : 0); in do_flush_tlb_mm_ipi()
340 mmu_get_tsize(mmu_virtual_psize), 0); in flush_tlb_page()
365 _tlbil_pid(0); in flush_tlb_kernel_range()
368 _tlbil_pid(0); in flush_tlb_kernel_range()
424 unsigned long rmask = 0xf000000000000000ul; in tlb_flush_pgtable()
425 unsigned long rid = (address & rmask) | 0x1000000000000000ul; in tlb_flush_pgtable()
428 vpte = (vpte >> (PAGE_SHIFT - 3)) & ~0xffful; in tlb_flush_pgtable()
[all …]
/Linux-v5.10/arch/arm/boot/dts/
Dvf610-pinfunc.h14 #define ALT0 0x0
15 #define ALT1 0x1
16 #define ALT2 0x2
17 #define ALT3 0x3
18 #define ALT4 0x4
19 #define ALT5 0x5
20 #define ALT6 0x6
21 #define ALT7 0x7
24 #define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0
25 #define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0
[all …]
/Linux-v5.10/include/dt-bindings/clock/
Ddra7.h8 #define DRA7_CLKCTRL_OFFSET 0x20
14 #define DRA7_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
17 #define _DRA7_IPU_CLKCTRL_OFFSET 0x40
19 #define DRA7_MCASP1_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x50)
20 #define DRA7_TIMER5_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x58)
21 #define DRA7_TIMER6_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x60)
22 #define DRA7_TIMER7_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x68)
23 #define DRA7_TIMER8_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x70)
24 #define DRA7_I2C5_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x78)
25 #define DRA7_UART6_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x80)
[all …]
/Linux-v5.10/drivers/net/wireless/mediatek/mt76/
Dmt76x02_eeprom.h13 MT_EE_CHIP_ID = 0x000,
14 MT_EE_VERSION = 0x002,
15 MT_EE_MAC_ADDR = 0x004,
16 MT_EE_PCI_ID = 0x00A,
17 MT_EE_ANTENNA = 0x022,
18 MT_EE_CFG1_INIT = 0x024,
19 MT_EE_NIC_CONF_0 = 0x034,
20 MT_EE_NIC_CONF_1 = 0x036,
21 MT_EE_COUNTRY_REGION_5GHZ = 0x038,
22 MT_EE_COUNTRY_REGION_2GHZ = 0x039,
[all …]

12345678