143 	return 0;  in mmu_get_tsize()
209 	pid = mm ? mm->context.id : 0;  in __local_flush_tlb_page()
218 			       mmu_get_tsize(mmu_virtual_psize), 0);  in local_flush_tlb_page()
240 	_tlbil_pid(p ? p->pid : 0);  in do_flush_tlb_mm_ipi()
340 			 mmu_get_tsize(mmu_virtual_psize), 0);  in flush_tlb_page()
365 	_tlbil_pid(0);  in flush_tlb_kernel_range()
368 	_tlbil_pid(0);  in flush_tlb_kernel_range()
424 		unsigned long rmask = 0xf000000000000000ul;  in tlb_flush_pgtable()
425 		unsigned long rid = (address & rmask) | 0x1000000000000000ul;  in tlb_flush_pgtable()
428 		vpte = (vpte >> (PAGE_SHIFT - 3)) & ~0xffful;  in tlb_flush_pgtable()
430 		__flush_tlb_page(tlb->mm, vpte, tsize, 0);  in tlb_flush_pgtable()
452 		for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) {  in setup_page_sizes()
459 			if (shift == 0 || shift & 1)  in setup_page_sizes()
486 		 * extension, indicated by PSn = 0 but SPSn != 0.  in setup_page_sizes()
491 		for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) {  in setup_page_sizes()
514 	for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) {  in setup_page_sizes()
522 	if ((tlb0cfg & TLBnCFG_IND) == 0 ||  in setup_page_sizes()
523 	    (tlb0cfg & TLBnCFG_PT) == 0)  in setup_page_sizes()
533 	for (i = 0; i < 3; i++) {  in setup_page_sizes()
536 		sps = eptcfg & 0x1f;  in setup_page_sizes()
538 		ps = eptcfg & 0x1f;  in setup_page_sizes()
542 		for (psize = 0; psize < MMU_PAGE_COUNT; psize++) {  in setup_page_sizes()
555 	for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) {  in setup_page_sizes()
563 		if (def->flags == 0) {  in setup_page_sizes()
564 			def->shift = 0;	  in setup_page_sizes()
568 			__page_type_names[def->flags & 0x3]);  in setup_page_sizes()
581 		patch_exception(0x1c0, exc_data_tlb_miss_htw_book3e);  in setup_mmu_htw()
582 		patch_exception(0x1e0, exc_instruction_tlb_miss_htw_book3e);  in setup_mmu_htw()
587 		patch_exception(0x1c0, exc_data_tlb_miss_e6500_book3e);  in setup_mmu_htw()
588 		patch_exception(0x1e0, exc_instruction_tlb_miss_e6500_book3e);  in setup_mmu_htw()
605 	mas4 = 0x4 << MAS4_WIMGED_SHIFT;  in early_init_this_mmu()
677 	/* XXX This code only checks for TLB 0 capabilities and doesn't  in early_init_mmu_global()
692 			patch_exception(0x1c0, exc_data_tlb_miss_bolted_book3e);  in early_init_mmu_global()
693 			patch_exception(0x1e0,  in early_init_mmu_global()
769 		ppc64_rma_size = min_t(u64, linear_sz, 0x40000000);  in setup_initial_memory_limit()
772 		ppc64_rma_size = min_t(u64, first_memblock_size, 0x40000000);  in setup_initial_memory_limit()