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/Linux-v5.10/arch/mips/include/asm/sn/sn0/
Daddrs.h57 #define NASID_BITMASK (0x1ffLL)
62 #define BDDIR_UPPER_MASK (UINT64_CAST 0x7ffff << 10)
63 #define BDECC_UPPER_MASK (UINT64_CAST 0x3ffffff << 3)
70 #define NASID_BITMASK (0xffLL)
76 #define BDDIR_UPPER_MASK (UINT64_CAST 0xfffff << 10)
77 #define BDECC_UPPER_MASK (UINT64_CAST 0x7ffffff << 3)
90 ((widget == 0) ? NODE_BWIN_BASE((nasid), SWIN0_BIGWIN) \
106 #define BWIN_WIDGET_MASK 0x7
150 #define MISC_PROM_BASE PHYS_TO_K0(0x01300000)
151 #define MISC_PROM_SIZE 0x200000
[all …]
/Linux-v5.10/arch/mips/alchemy/
Dboard-gpr.c42 alchemy_gpio_direction_output(4, 0); in gpr_reset()
43 alchemy_gpio_direction_output(5, 0); in gpr_reset()
48 alchemy_gpio_direction_output(1, 0); in gpr_reset()
81 [0] = {
91 .id = 0,
99 * 0x00000000-0x00200000 : "kernel"
100 * 0x00200000-0x00a00000 : "rootfs"
101 * 0x01d00000-0x01f00000 : "config"
102 * 0x01c00000-0x01d00000 : "yamon"
103 * 0x01d00000-0x01d40000 : "yamon env vars"
[all …]
Dboard-mtx1.c41 __asm__ __volatile__("jr\t%0" : : "r"(0xbfc00000)); in mtx1_reset()
57 alchemy_gpio_direction_output(204, 0); in board_setup()
64 alchemy_wrsys(~0, AU1000_SYS_TRIOUTCLR); in board_setup()
65 alchemy_gpio_direction_output(0, 0); /* Disable M66EN (PCI 66MHz) */ in board_setup()
68 alchemy_gpio_direction_output(5, 0); /* Disable eth PHY TX_ER */ in board_setup()
72 alchemy_gpio_direction_output(212, 0); /* red off */ in board_setup()
105 .dev_id = "mtx1-wdt.0",
115 .id = 0,
144 .size = 0x01C00000,
145 .offset = 0,
[all …]
/Linux-v5.10/arch/arm/mach-davinci/include/mach/
Dhardware.h25 #define IO_PHYS UL(0x01c00000)
26 #define IO_OFFSET 0xfd000000 /* Virtual IO = 0xfec00000 */
27 #define IO_SIZE 0x00400000
/Linux-v5.10/Documentation/devicetree/bindings/mfd/
Dsyscon.yaml84 reg = <0x01c00000 0x1000>;
90 reg = <0x020e0000 0x38>;
/Linux-v5.10/drivers/gpu/drm/mcde/
Dmcde_drm.h13 #define MCDE_CR 0x00000000
14 #define MCDE_CR_IFIFOEMPTYLINECOUNT_V422_SHIFT 0
15 #define MCDE_CR_IFIFOEMPTYLINECOUNT_V422_MASK 0x0000003F
22 #define MCDE_CONF0 0x00000004
23 #define MCDE_CONF0_SYNCMUX0 BIT(0)
32 #define MCDE_CONF0_IFIFOCTRLWTRMRKLVL_MASK 0x00007000
34 #define MCDE_CONF0_OUTMUX0_MASK 0x00070000
36 #define MCDE_CONF0_OUTMUX1_MASK 0x00380000
38 #define MCDE_CONF0_OUTMUX2_MASK 0x01C00000
40 #define MCDE_CONF0_OUTMUX3_MASK 0x0E000000
[all …]
/Linux-v5.10/arch/mips/include/asm/mach-rc32434/
Ddma.h17 #define DMA0_BASE_ADDR 0x18040000
31 #define DMA_DESC_COUNT_BIT 0
32 #define DMA_DESC_COUNT_MSK 0x0003ffff
34 #define DMA_DESC_DS_MSK 0x00300000
37 #define DMA_DESC_DEV_CMD_MSK 0x01c00000
40 #define DMA_DESC_DEV_CMD_BYTE 0
71 #define DMA_CHAN_RUN_BIT (1 << 0)
74 #define DMA_CHAN_MODE_MSK 0x0000000c
75 #define DMA_CHAN_MODE_AUTO 0
82 #define DMA_STAT_FINI (1 << 0)
[all …]
/Linux-v5.10/arch/arm/boot/dts/
Dsuniv-f1c100s.dtsi14 #clock-cells = <0>;
21 #clock-cells = <0>;
44 reg = <0x01c00000 0x30>;
51 reg = <0x00010000 0x1000>;
54 ranges = <0 0x00010000 0x1000>;
56 otg_sram: sram-section@0 {
59 reg = <0x0000 0x1000>;
67 reg = <0x01c20000 0x400>;
76 reg = <0x01c20400 0x400>;
83 reg = <0x01c20800 0x400>;
[all …]
Dsun8i-h3.dtsi72 #size-cells = <0>;
74 cpu0: cpu@0 {
77 reg = <0>;
155 reg = <0x01400000 0x20000>;
168 reg = <0x01c00000 0x1000>;
175 reg = <0x01d00000 0x80000>;
178 ranges = <0 0x01d00000 0x80000>;
180 ve_sram: sram-section@0 {
183 reg = <0x000000 0x80000>;
190 reg = <0x01c0e000 0x1000>;
[all …]
Dsun8i-v3s.dtsi70 #size-cells = <0>;
72 cpu@0 {
75 reg = <0>;
100 #clock-cells = <0>;
108 #clock-cells = <0>;
124 reg = <0x01000000 0x10000>;
136 reg = <0x01100000 0x100000>;
137 clocks = <&display_clocks 0>,
141 resets = <&display_clocks 0>;
145 #size-cells = <0>;
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/sram/
Dallwinner,sun4i-a10-system-control.yaml132 reg = <0x01c00000 0x30>;
137 sram_a: sram@0 {
139 reg = <0x00000000 0xc000>;
142 ranges = <0 0x00000000 0xc000>;
146 reg = <0x8000 0x4000>;
/Linux-v5.10/arch/powerpc/boot/dts/fsl/
Dmpc8569mds.dts30 reg = <0x0 0xe0005000 0x0 0x1000>;
32 ranges = <0x0 0x0 0x0 0xfe000000 0x02000000
33 0x1 0x0 0x0 0xf8000000 0x00008000
34 0x2 0x0 0x0 0xf0000000 0x04000000
35 0x3 0x0 0x0 0xfc000000 0x00008000
36 0x4 0x0 0x0 0xf8008000 0x00008000
37 0x5 0x0 0x0 0xf8010000 0x00008000>;
39 nor@0,0 {
43 reg = <0x0 0x0 0x02000000>;
46 partition@0 {
[all …]
/Linux-v5.10/arch/arm64/boot/dts/ti/
Dk3-j721e-som-p0.dtsi14 reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
15 <0x00000008 0x80000000 0x00000000 0x80000000>;
24 reg = <0x00 0x9e800000 0x00 0x01800000>;
25 alignment = <0x1000>;
31 reg = <0x00 0xa6000000 0x00 0x100000>;
37 reg = <0x00 0xa6100000 0x00 0xf00000>;
43 reg = <0x00 0xa7000000 0x00 0x100000>;
49 reg = <0x00 0xa7100000 0x00 0xf00000>;
55 reg = <0x00 0xa8000000 0x00 0x100000>;
61 reg = <0x00 0xa8100000 0x00 0xf00000>;
[all …]
/Linux-v5.10/arch/arm/mach-davinci/
Ddm646x.c39 #define DAVINCI_VPIF_BASE (0x01C12000)
42 BIT_MASK(0))
46 #define DM646X_EMAC_BASE 0x01c80000
47 #define DM646X_EMAC_MDIO_BASE (DM646X_EMAC_BASE + 0x4000)
48 #define DM646X_EMAC_CNTRL_OFFSET 0x0000
49 #define DM646X_EMAC_CNTRL_MOD_OFFSET 0x1000
50 #define DM646X_EMAC_CNTRL_RAM_OFFSET 0x2000
51 #define DM646X_EMAC_CNTRL_RAM_SIZE 0x2000
109 .id = 0,
122 MUX_CFG(DM646X, ATAEN, 0, 0, 5, 1, true)
[all …]
Ddm644x.c43 #define DM644X_EMAC_BASE 0x01c80000
44 #define DM644X_EMAC_MDIO_BASE (DM644X_EMAC_BASE + 0x4000)
45 #define DM644X_EMAC_CNTRL_OFFSET 0x0000
46 #define DM644X_EMAC_CNTRL_MOD_OFFSET 0x1000
47 #define DM644X_EMAC_CNTRL_RAM_OFFSET 0x2000
48 #define DM644X_EMAC_CNTRL_RAM_SIZE 0x2000
91 .id = 0,
104 MUX_CFG(DM644X, HDIREN, 0, 16, 1, 1, true)
105 MUX_CFG(DM644X, ATAEN, 0, 17, 1, 1, true)
106 MUX_CFG(DM644X, ATAEN_DISABLE, 0, 17, 1, 0, true)
[all …]
Ddm355.c41 #define DM355_UART2_BASE (IO_PHYS + 0x206000)
42 #define DM355_OSD_BASE (IO_PHYS + 0x70200)
43 #define DM355_VENC_BASE (IO_PHYS + 0x70400)
54 .start = 0x01c66000,
55 .end = 0x01c667ff,
73 .id = 0,
90 if (chipselect_mask & BIT(0)) in dm355_init_spi0()
102 #define INTMUX 0x18
103 #define EVTMUX 0x1c
113 MUX_CFG(DM355, MMCSD0, 4, 2, 1, 0, false)
[all …]
Ddm365.c47 #define DM365_RTC_BASE 0x01c69000
48 #define DM365_KEYSCAN_BASE 0x01c69400
49 #define DM365_OSD_BASE 0x01c71c00
50 #define DM365_VENC_BASE 0x01c71e00
51 #define DAVINCI_DM365_VC_BASE 0x01d0c000
54 #define DM365_EMAC_BASE 0x01d07000
55 #define DM365_EMAC_MDIO_BASE (DM365_EMAC_BASE + 0x4000)
56 #define DM365_EMAC_CNTRL_OFFSET 0x0000
57 #define DM365_EMAC_CNTRL_MOD_OFFSET 0x3000
58 #define DM365_EMAC_CNTRL_RAM_OFFSET 0x1000
[all …]
/Linux-v5.10/arch/arm64/boot/dts/allwinner/
Dsun50i-h5.dtsi11 #size-cells = <0>;
13 cpu0: cpu@0 {
16 reg = <0>;
84 reg = <0x01c00000 0x1000>;
91 reg = <0x00018000 0x1c000>;
94 ranges = <0 0x00018000 0x1c000>;
96 ve_sram: sram-section@0 {
99 reg = <0x000000 0x1c000>;
106 reg = <0x01c0e000 0x1000>;
117 reg = <0x01c15000 0x1000>;
[all …]
/Linux-v5.10/arch/mips/include/asm/mach-loongson64/
Dloongson.h37 for (x = 0; x < 100000; x++) \
50 #define LOONGSON_FLASH_BASE 0x1c000000
51 #define LOONGSON_FLASH_SIZE 0x02000000 /* 32M */
54 #define LOONGSON_LIO0_BASE 0x1e000000
55 #define LOONGSON_LIO0_SIZE 0x01C00000 /* 28M */
58 #define LOONGSON_BOOT_BASE 0x1fc00000
59 #define LOONGSON_BOOT_SIZE 0x00100000 /* 1M */
61 #define LOONGSON_REG_BASE 0x1fe00000
62 #define LOONGSON_REG_SIZE 0x00100000 /* 256Bytes + 256Bytes + ??? */
65 #define LOONGSON3_REG_BASE 0x3ff00000
[all …]
/Linux-v5.10/arch/mips/include/asm/mach-loongson2ef/
Dloongson.h51 for (x = 0; x < 100000; x++) \
69 #define LOONGSON_FLASH_BASE 0x1c000000
70 #define LOONGSON_FLASH_SIZE 0x02000000 /* 32M */
73 #define LOONGSON_LIO0_BASE 0x1e000000
74 #define LOONGSON_LIO0_SIZE 0x01C00000 /* 28M */
77 #define LOONGSON_BOOT_BASE 0x1fc00000
78 #define LOONGSON_BOOT_SIZE 0x00100000 /* 1M */
80 #define LOONGSON_REG_BASE 0x1fe00000
81 #define LOONGSON_REG_SIZE 0x00100000 /* 256Bytes + 256Bytes + ??? */
84 #define LOONGSON_LIO1_BASE 0x1ff00000
[all …]
/Linux-v5.10/drivers/net/ethernet/intel/ixgbevf/
Ddefines.h8 #define IXGBE_DEV_ID_82599_VF 0x10ED
9 #define IXGBE_DEV_ID_X540_VF 0x1515
10 #define IXGBE_DEV_ID_X550_VF 0x1565
11 #define IXGBE_DEV_ID_X550EM_X_VF 0x15A8
12 #define IXGBE_DEV_ID_X550EM_A_VF 0x15C5
14 #define IXGBE_DEV_ID_82599_VF_HV 0x152E
15 #define IXGBE_DEV_ID_X540_VF_HV 0x1530
16 #define IXGBE_DEV_ID_X550_VF_HV 0x1564
17 #define IXGBE_DEV_ID_X550EM_X_VF_HV 0x15A9
28 #define IXGBE_LINK_SPEED_1GB_FULL 0x0020
[all …]
/Linux-v5.10/arch/arm/net/
Dbpf_jit_32.h12 #define ARM_R0 0
29 #define ARM_COND_EQ 0x0 /* == */
30 #define ARM_COND_NE 0x1 /* != */
31 #define ARM_COND_CS 0x2 /* unsigned >= */
33 #define ARM_COND_CC 0x3 /* unsigned < */
35 #define ARM_COND_MI 0x4 /* < 0 */
36 #define ARM_COND_PL 0x5 /* >= 0 */
37 #define ARM_COND_VS 0x6 /* Signed Overflow */
38 #define ARM_COND_VC 0x7 /* No Signed Overflow */
39 #define ARM_COND_HI 0x8 /* unsigned > */
[all …]
/Linux-v5.10/arch/mips/include/asm/sgi/
Dheart.h24 #define HEART_XKPHYS_BASE ((void *)(IO_BASE | 0x000000000ff00000ULL))
47 * @__pad0: 0x0f40 bytes of padding -> next HEART register 0x01000.
49 * @__pad1: 0xeff8 bytes of padding -> next HEART register 0x10000.
56 * @__pad2: 0xffb8 bytes of padding -> next HEART register 0x20000.
58 * @__pad3: 0xfff8 bytes of padding -> next HEART register 0x30000.
60 * @__pad4: 0xfff8 bytes of padding -> next HEART register 0x40000.
62 * @__pad5: 0xfff8 bytes of padding -> next HEART register 0x50000.
64 * @__pad6: 0xfff8 bytes of padding -> next HEART register 0x60000.
79 struct ip30_heart_regs { /* 0x0ff00000 */
80 u64 mode; /* + 0x00000 */
[all …]
/Linux-v5.10/include/video/
Dnewport.h34 #define DM1_PLANES 0x00000007
35 #define DM1_NOPLANES 0x00000000
36 #define DM1_RGBPLANES 0x00000001
37 #define DM1_RGBAPLANES 0x00000002
38 #define DM1_OLAYPLANES 0x00000004
39 #define DM1_PUPPLANES 0x00000005
40 #define DM1_CIDPLANES 0x00000006
42 #define NPORT_DMODE1_DDMASK 0x00000018
43 #define NPORT_DMODE1_DD4 0x00000000
44 #define NPORT_DMODE1_DD8 0x00000008
[all …]
/Linux-v5.10/drivers/media/usb/dvb-usb/
Daf9005-fe.c54 if ((ret = af9005_write_ofdm_register(d, reglo, (u8) (value & 0xff)))) in af9005_write_word_agc()
57 (u8) ((value & 0x300) >> 8)); in af9005_write_word_agc()
71 case 0: in af9005_read_word_agc()
72 *value = ((u16) (temp1 & 0x03) << 8) + (u16) temp0; in af9005_read_word_agc()
75 *value = ((u16) (temp1 & 0x0C) << 6) + (u16) temp0; in af9005_read_word_agc()
78 *value = ((u16) (temp1 & 0x30) << 4) + (u16) temp0; in af9005_read_word_agc()
81 *value = ((u16) (temp1 & 0xC0) << 2) + (u16) temp0; in af9005_read_word_agc()
87 return 0; in af9005_read_word_agc()
112 if ((temp & 1) == 0) in af9005_is_fecmon_available()
116 return 0; in af9005_is_fecmon_available()
[all …]

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