Lines Matching +full:0 +full:x01c00000
43 #define DM644X_EMAC_BASE 0x01c80000
44 #define DM644X_EMAC_MDIO_BASE (DM644X_EMAC_BASE + 0x4000)
45 #define DM644X_EMAC_CNTRL_OFFSET 0x0000
46 #define DM644X_EMAC_CNTRL_MOD_OFFSET 0x1000
47 #define DM644X_EMAC_CNTRL_RAM_OFFSET 0x2000
48 #define DM644X_EMAC_CNTRL_RAM_SIZE 0x2000
91 .id = 0,
104 MUX_CFG(DM644X, HDIREN, 0, 16, 1, 1, true)
105 MUX_CFG(DM644X, ATAEN, 0, 17, 1, 1, true)
106 MUX_CFG(DM644X, ATAEN_DISABLE, 0, 17, 1, 0, true)
108 MUX_CFG(DM644X, HPIEN_DISABLE, 0, 29, 1, 0, true)
110 MUX_CFG(DM644X, AEAW, 0, 0, 31, 31, true)
111 MUX_CFG(DM644X, AEAW0, 0, 0, 1, 0, true)
112 MUX_CFG(DM644X, AEAW1, 0, 1, 1, 0, true)
113 MUX_CFG(DM644X, AEAW2, 0, 2, 1, 0, true)
114 MUX_CFG(DM644X, AEAW3, 0, 3, 1, 0, true)
115 MUX_CFG(DM644X, AEAW4, 0, 4, 1, 0, true)
117 MUX_CFG(DM644X, MSTK, 1, 9, 1, 0, false)
132 MUX_CFG(DM644X, VLYNQEN, 0, 15, 1, 1, false)
133 MUX_CFG(DM644X, VLSCREN, 0, 14, 1, 1, false)
134 MUX_CFG(DM644X, VLYNQWD, 0, 12, 3, 3, false)
136 MUX_CFG(DM644X, EMACEN, 0, 31, 1, 1, true)
138 MUX_CFG(DM644X, GPIO3V, 0, 31, 1, 0, true)
140 MUX_CFG(DM644X, GPIO0, 0, 24, 1, 0, true)
141 MUX_CFG(DM644X, GPIO3, 0, 25, 1, 0, false)
142 MUX_CFG(DM644X, GPIO43_44, 1, 7, 1, 0, false)
143 MUX_CFG(DM644X, GPIO46_47, 0, 22, 1, 0, true)
145 MUX_CFG(DM644X, RGB666, 0, 22, 1, 1, true)
147 MUX_CFG(DM644X, LOEEN, 0, 24, 1, 1, true)
148 MUX_CFG(DM644X, LFLDEN, 0, 25, 1, 1, false)
152 /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
224 {0, 3},
230 { "davinci-mcbsp", "tx", EDMA_FILTER_PARAM(0, 2) },
231 { "davinci-mcbsp", "rx", EDMA_FILTER_PARAM(0, 3) },
232 { "spi_davinci", "tx", EDMA_FILTER_PARAM(0, 16) },
233 { "spi_davinci", "rx", EDMA_FILTER_PARAM(0, 17) },
234 { "dm6441-mmc.0", "rx", EDMA_FILTER_PARAM(0, 26) },
235 { "dm6441-mmc.0", "tx", EDMA_FILTER_PARAM(0, 27) },
248 .start = 0x01c00000,
249 .end = 0x01c00000 + SZ_64K - 1,
254 .start = 0x01c10000,
255 .end = 0x01c10000 + SZ_1K - 1,
260 .start = 0x01c10400,
261 .end = 0x01c10400 + SZ_1K - 1,
279 .id = 0,
314 #define DM644X_VPSS_BASE 0x01c73400
321 .end = DM644X_VPSS_BASE + 0xff,
351 .start = 0x01c70400,
352 .end = 0x01c70400 + 0xff,
379 #define DM644X_OSD_BASE 0x01c72600
384 .end = DM644X_OSD_BASE + 0x1ff,
400 #define DM644X_VENC_BASE 0x01c72400
405 .end = DM644X_VENC_BASE + 0x17f,
410 #define DM644X_VPSS_MUXSEL_PLL2_MODE BIT(0)
418 int ret = 0; in dm644x_venc_setup_clock()
525 .base = 0,
549 .variant = 0x0,
550 .part_no = 0xb700,
551 .manufacturer = 0x017,
556 .variant = 0x1,
557 .part_no = 0xb700,
558 .manufacturer = 0x017,
586 .flags = 0,
599 .flags = 0,
612 .flags = 0,
645 .jtag_id_reg = 0x01c40028,
652 .sram_dma = 0x00008000,
674 clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM644X_REF_FREQ); in dm644x_init_time()
733 return 0; in dm644x_init_video()