Lines Matching +full:0 +full:x01c00000
39 #define DAVINCI_VPIF_BASE (0x01C12000)
42 BIT_MASK(0))
46 #define DM646X_EMAC_BASE 0x01c80000
47 #define DM646X_EMAC_MDIO_BASE (DM646X_EMAC_BASE + 0x4000)
48 #define DM646X_EMAC_CNTRL_OFFSET 0x0000
49 #define DM646X_EMAC_CNTRL_MOD_OFFSET 0x1000
50 #define DM646X_EMAC_CNTRL_RAM_OFFSET 0x2000
51 #define DM646X_EMAC_CNTRL_RAM_SIZE 0x2000
109 .id = 0,
122 MUX_CFG(DM646X, ATAEN, 0, 0, 5, 1, true)
124 MUX_CFG(DM646X, AUDCK1, 0, 29, 1, 0, false)
126 MUX_CFG(DM646X, AUDCK0, 0, 28, 1, 0, false)
128 MUX_CFG(DM646X, CRGMUX, 0, 24, 7, 5, true)
130 MUX_CFG(DM646X, STSOMUX_DISABLE, 0, 22, 3, 0, true)
132 MUX_CFG(DM646X, STSIMUX_DISABLE, 0, 20, 3, 0, true)
134 MUX_CFG(DM646X, PTSOMUX_DISABLE, 0, 18, 3, 0, true)
136 MUX_CFG(DM646X, PTSIMUX_DISABLE, 0, 16, 3, 0, true)
138 MUX_CFG(DM646X, STSOMUX, 0, 22, 3, 2, true)
140 MUX_CFG(DM646X, STSIMUX, 0, 20, 3, 2, true)
142 MUX_CFG(DM646X, PTSOMUX_PARALLEL, 0, 18, 3, 2, true)
144 MUX_CFG(DM646X, PTSIMUX_PARALLEL, 0, 16, 3, 2, true)
146 MUX_CFG(DM646X, PTSOMUX_SERIAL, 0, 18, 3, 3, true)
148 MUX_CFG(DM646X, PTSIMUX_SERIAL, 0, 16, 3, 3, true)
224 {0, 4},
225 {1, 0},
232 { "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 6) },
233 { "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 9) },
234 { "davinci-mcasp.1", "tx", EDMA_FILTER_PARAM(0, 12) },
235 { "spi_davinci", "tx", EDMA_FILTER_PARAM(0, 16) },
236 { "spi_davinci", "rx", EDMA_FILTER_PARAM(0, 17) },
249 .start = 0x01c00000,
250 .end = 0x01c00000 + SZ_64K - 1,
255 .start = 0x01c10000,
256 .end = 0x01c10000 + SZ_1K - 1,
261 .start = 0x01c10400,
262 .end = 0x01c10400 + SZ_1K - 1,
267 .start = 0x01c10800,
268 .end = 0x01c10800 + SZ_1K - 1,
273 .start = 0x01c10c00,
274 .end = 0x01c10c00 + SZ_1K - 1,
292 .id = 0,
354 .id = 0,
376 .end = DAVINCI_VPIF_BASE + 0x03ff,
465 .base = 0,
489 .variant = 0x0,
490 .part_no = 0xb770,
491 .manufacturer = 0x017,
496 .variant = 0x1,
497 .part_no = 0xb770,
498 .manufacturer = 0x017,
526 .flags = 0,
539 .flags = 0,
552 .flags = 0,
585 .jtag_id_reg = 0x01c40028,
592 .sram_dma = 0x10010000,
657 clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, ref_clk_rate); in dm646x_init_time()
658 clk_register_fixed_rate(NULL, "aux_clkin", NULL, 0, aux_clkin_rate); in dm646x_init_time()
714 int ret = 0; in dm646x_init_devices()
717 return 0; in dm646x_init_devices()