fail\-fast (full) in projects: Kernel-v11.1.0

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/Kernel-v11.1.0/portable/CCS/ARM_CM3/
D	port.c	5 * SPDX-License-Identifier: MIT 29 /----------------------------------------------------------- 31 ----------------------------------------------------------/ 38 …LL_INTERRUPT_PRIORITY must not be set to 0. See http: /www.FreeRTOS.org/RTOS-Cortex-M3-M4.html / 75 / The systick is a 24-bit counter. / 83 / For strict compliance with the Cortex-M spec the task start address should 84 * have bit-0 clear, as it is loaded into the PC on exit from an ISR. / 121 /-----------------------------------------------------------/ 165 /-----------------------------------------------------------*/ 179 pxTopOfStack--; in pxPortInitialiseStack() [all …]
/Kernel-v11.1.0/portable/GCC/ARM7_AT91FR40008/
D	port.c	5 * SPDX-License-Identifier: MIT 30 /----------------------------------------------------------- 37 ----------------------------------------------------------/ 58 /-----------------------------------------------------------/ 69 /-----------------------------------------------------------/ 85 / To ensure asserts in tasks.c don't fail, although in this case the assert in pxPortInitialiseStack() 87 pxTopOfStack--; in pxPortInitialiseStack() 92 /* First on the stack is the return address - which in this case is the in pxPortInitialiseStack() 96 pxTopOfStack--; in pxPortInitialiseStack() 99 pxTopOfStack--; in pxPortInitialiseStack() [all …]
/Kernel-v11.1.0/.github/workflows/
D	kernel-demos.yml	`1 name: FreeRTOS-Kernel Demos 6 bashPass: \033[32;1mPASSED - 7 bashInfo: \033[33;1mINFO - 8 bashFail: \033[31;1mFAILED - 12 WIN32-MSVC: 14 runs-on: windows-latest 16 - name: Checkout the FreeRTOS/FreeRTOS Repository 22 fetch-depth: 1 25 - name: Checkout Pull Request 30 - name: Add msbuild to PATH [all …]`
/Kernel-v11.1.0/portable/GCC/ARM_CA9/
D	port.c	5 * SPDX-License-Identifier: MIT 38 …LER_BASE_ADDRESS must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Proces… 42 …INTERFACE_OFFSET must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Proces… 46 …RRUPT_PRIORITIES must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Proces… 50 …TICK_INTERRUPT() must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Proces… 54 …TERRUPT_PRIORITY must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Proces… 143 /* Let the user override the pre-loading of the initial LR with the address of 152 /* The space on the stack required to hold the FPU registers. This is 32 64-bit 153 * registers, plus a 32-bit status register. / 156 /-----------------------------------------------------------*/ [all …]
/Kernel-v11.1.0/portable/IAR/ARM_CA9/
D	port.c	5 * SPDX-License-Identifier: MIT 40 …LER_BASE_ADDRESS must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Proces… 44 …INTERFACE_OFFSET must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Proces… 48 …RRUPT_PRIORITIES must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Proces… 52 …TICK_INTERRUPT() must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Proces… 56 …TERRUPT_PRIORITY must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Proces… 124 /-----------------------------------------------------------/ 137 /-----------------------------------------------------------/ 146 /* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero 158 /-----------------------------------------------------------/ [all …]
/Kernel-v11.1.0/portable/IAR/ARM_CM7/r0p1/
D	port.c	5 * SPDX-License-Identifier: MIT 29 /----------------------------------------------------------- 31 ----------------------------------------------------------/ 45 …LL_INTERRUPT_PRIORITY must not be set to 0. See http: /www.FreeRTOS.org/RTOS-Cortex-M3-M4.html / 96 / The systick is a 24-bit counter. / 104 / For strict compliance with the Cortex-M spec the task start address should 105 * have bit-0 clear, as it is loaded into the PC on exit from an ISR. / 152 /-----------------------------------------------------------/ 192 /-----------------------------------------------------------*/ 206 pxTopOfStack--; in pxPortInitialiseStack() [all …]
/Kernel-v11.1.0/portable/IAR/ARM_CM3/
D	port.c	5 * SPDX-License-Identifier: MIT 29 /----------------------------------------------------------- 31 ----------------------------------------------------------/ 41 …LL_INTERRUPT_PRIORITY must not be set to 0. See http: /www.FreeRTOS.org/RTOS-Cortex-M3-M4.html / 87 / The systick is a 24-bit counter. / 95 / For strict compliance with the Cortex-M spec the task start address should 96 * have bit-0 clear, as it is loaded into the PC on exit from an ISR. / 138 /-----------------------------------------------------------/ 178 /-----------------------------------------------------------/ 189 …pxTopOfStack--; / Offset added to account fo… in pxPortInitialiseStack() [all …]
/Kernel-v11.1.0/portable/CCS/ARM_CM4F/
D	port.c	5 * SPDX-License-Identifier: MIT 29 /----------------------------------------------------------- 31 ----------------------------------------------------------/ 42 …LL_INTERRUPT_PRIORITY must not be set to 0. See http: /www.FreeRTOS.org/RTOS-Cortex-M3-M4.html / 84 / The systick is a 24-bit counter. / 92 / For strict compliance with the Cortex-M spec the task start address should 93 * have bit-0 clear, as it is loaded into the PC on exit from an ISR. / 135 /-----------------------------------------------------------/ 179 /-----------------------------------------------------------*/ 193 pxTopOfStack--; in pxPortInitialiseStack() [all …]
/Kernel-v11.1.0/portable/GCC/ARM_CR5/
D	port.c	5 * SPDX-License-Identifier: MIT 38 …RESS must be defined. Refer to Cortex-A equivalent: http: /www.FreeRTOS.org/Using-FreeRTOS-on-Co… 42 …FSET must be defined. Refer to Cortex-A equivalent: http: /www.FreeRTOS.org/Using-FreeRTOS-on-Co… 46 …TIES must be defined. Refer to Cortex-A equivalent: http: /www.FreeRTOS.org/Using-FreeRTOS-on-Co… 50 …PT() must be defined. Refer to Cortex-A equivalent: http: /www.FreeRTOS.org/Using-FreeRTOS-on-Co… 54 …RITY must be defined. Refer to Cortex-A equivalent: http: /www.FreeRTOS.org/Using-FreeRTOS-on-Co… 79 usually with the -mfpu= argument and -mfloat-abi=. 173 * Let the user override the pre-loading of the initial LR with the address of 188 * The ARM Cortex R5 processor implements the VFPv3-D16 FPU 189 * architecture. This includes only 16 double-precision registers, [all …]
/Kernel-v11.1.0/portable/RVDS/ARM_CM3/
D	port.c	5 * SPDX-License-Identifier: MIT 29 /----------------------------------------------------------- 31 ----------------------------------------------------------/ 38 …LL_INTERRUPT_PRIORITY must not be set to 0. See http: /www.FreeRTOS.org/RTOS-Cortex-M3-M4.html / 84 / The systick is a 24-bit counter. / 92 / For strict compliance with the Cortex-M spec the task start address should 93 * have bit-0 clear, as it is loaded into the PC on exit from an ISR. / 132 /-----------------------------------------------------------/ 172 /-----------------------------------------------------------/ 183 …pxTopOfStack--; / Offset added to account fo… in pxPortInitialiseStack() [all …]
/Kernel-v11.1.0/portable/IAR/ARM_CM4F/
D	port.c	5 * SPDX-License-Identifier: MIT 29 /----------------------------------------------------------- 31 ----------------------------------------------------------/ 45 …LL_INTERRUPT_PRIORITY must not be set to 0. See http: /www.FreeRTOS.org/RTOS-Cortex-M3-M4.html / 66 / Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7 102 /* The systick is a 24-bit counter. / 110 / For strict compliance with the Cortex-M spec the task start address should 111 * have bit-0 clear, as it is loaded into the PC on exit from an ISR. / 158 /-----------------------------------------------------------/ 198 /-----------------------------------------------------------*/ [all …]
/Kernel-v11.1.0/portable/GCC/ARM_AARCH64/
D	port.c	5 * SPDX-License-Identifier: MIT 37 …LLER_BASE_ADDRESS must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Proces… 41 …INTERFACE_OFFSET must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Proces… 45 …RRUPT_PRIORITIES must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Proces… 49 …TICK_INTERRUPT() must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Proces… 53 …TERRUPT_PRIORITY must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Proces… 136 /-----------------------------------------------------------/ 144 /-----------------------------------------------------------/ 153 /* Saved as part of the task context. If ullPortTaskHasFPUContext is non-zero 170 /-----------------------------------------------------------/ [all …]
/Kernel-v11.1.0/portable/RVDS/ARM_CA9/
D	port.c	5 * SPDX-License-Identifier: MIT 37 …LER_BASE_ADDRESS must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Proces… 41 …INTERFACE_OFFSET must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Proces… 45 …RRUPT_PRIORITIES must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Proces… 49 …TICK_INTERRUPT() must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Proces… 53 …TERRUPT_PRIORITY must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Proces… 156 /-----------------------------------------------------------/ 169 /-----------------------------------------------------------/ 186 /* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero then 197 /-----------------------------------------------------------/ [all …]
/Kernel-v11.1.0/portable/RVDS/ARM_CM4F/
D	port.c	5 * SPDX-License-Identifier: MIT 29 /----------------------------------------------------------- 31 ----------------------------------------------------------/ 42 …LL_INTERRUPT_PRIORITY must not be set to 0. See http: /www.FreeRTOS.org/RTOS-Cortex-M3-M4.html / 68 / Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7 99 /* The systick is a 24-bit counter. / 107 / For strict compliance with the Cortex-M spec the task start address should 108 * have bit-0 clear, as it is loaded into the PC on exit from an ISR. / 152 /-----------------------------------------------------------/ 192 /-----------------------------------------------------------*/ [all …]
/Kernel-v11.1.0/portable/MikroC/ARM_CM4F/
D	port.c	5 * SPDX-License-Identifier: MIT 29 /----------------------------------------------------------- 31 ----------------------------------------------------------/ 76 / The systick is a 24-bit counter. / 96 / Let the user override the pre-loading of the initial LR with the address of 157 /-----------------------------------------------------------/ 192 /-----------------------------------------------------------/ 206 pxTopOfStack--; in pxPortInitialiseStack() 210 pxTopOfStack--; in pxPortInitialiseStack() 213 pxTopOfStack--; in pxPortInitialiseStack() [all …]
/Kernel-v11.1.0/portable/RVDS/ARM_CM7/r0p1/
D	port.c	5 * SPDX-License-Identifier: MIT 29 /----------------------------------------------------------- 31 ----------------------------------------------------------/ 42 …LL_INTERRUPT_PRIORITY must not be set to 0. See http: /www.FreeRTOS.org/RTOS-Cortex-M3-M4.html / 93 / The systick is a 24-bit counter. / 101 / For strict compliance with the Cortex-M spec the task start address should 102 * have bit-0 clear, as it is loaded into the PC on exit from an ISR. / 146 /-----------------------------------------------------------/ 186 /-----------------------------------------------------------*/ 200 pxTopOfStack--; in pxPortInitialiseStack() [all …]
/Kernel-v11.1.0/portable/GCC/ARM_CM3/
D	port.c	5 * SPDX-License-Identifier: MIT 29 /----------------------------------------------------------- 31 ----------------------------------------------------------/ 80 / The systick is a 24-bit counter. / 88 / For strict compliance with the Cortex-M spec the task start address should 89 * have bit-0 clear, as it is loaded into the PC on exit from an ISR. / 104 / Let the user override the pre-loading of the initial LR with the address of 137 /-----------------------------------------------------------/ 177 /-----------------------------------------------------------/ 188 …pxTopOfStack--; /* Offset added to account fo… in pxPortInitialiseStack() [all …]
/Kernel-v11.1.0/portable/GCC/ARM_CM7/r0p1/
D	port.c	5 * SPDX-License-Identifier: MIT 29 /----------------------------------------------------------- 31 ----------------------------------------------------------/ 89 / The systick is a 24-bit counter. / 92 / For strict compliance with the Cortex-M spec the task start address should 93 * have bit-0 clear, as it is loaded into the PC on exit from an ISR. / 113 / Let the user override the pre-loading of the initial LR with the address of 151 /-----------------------------------------------------------/ 191 /-----------------------------------------------------------/ 205 pxTopOfStack--; in pxPortInitialiseStack() [all …]
/Kernel-v11.1.0/portable/GCC/ARM_CM4F/
D	port.c	5 * SPDX-License-Identifier: MIT 29 /----------------------------------------------------------- 31 ----------------------------------------------------------/ 59 / Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7 95 /* The systick is a 24-bit counter. / 98 / For strict compliance with the Cortex-M spec the task start address should 99 * have bit-0 clear, as it is loaded into the PC on exit from an ISR. / 119 / Let the user override the pre-loading of the initial LR with the address of 157 /-----------------------------------------------------------/ 197 /-----------------------------------------------------------/ [all …]
/Kernel-v11.1.0/portable/GCC/ARM_AARCH64_SRE/
D	port.c	5 * SPDX-License-Identifier: MIT 37 …RRUPT_PRIORITIES must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Proces… 41 …TICK_INTERRUPT() must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Proces… 45 …TERRUPT_PRIORITY must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Proces… 124 /-----------------------------------------------------------/ 132 /-----------------------------------------------------------/ 141 /* Saved as part of the task context. If ullPortTaskHasFPUContext is non-zero 155 /-----------------------------------------------------------/ 168 pxTopOfStack--; in pxPortInitialiseStack() 170 pxTopOfStack--; in pxPortInitialiseStack() [all …]
/Kernel-v11.1.0/portable/IAR/ARM_CM4F_MPU/
D	port.c	5 * SPDX-License-Identifier: MIT 29 /----------------------------------------------------------- 31 ----------------------------------------------------------/ 53 …LL_INTERRUPT_PRIORITY must not be set to 0. See http: /www.FreeRTOS.org/RTOS-Cortex-M3-M4.html / 105 / Constants used to detect Cortex-M7 r0p0 and r0p1 cores, and ensure 152 /* The systick is a 24-bit counter. / 160 / For strict compliance with the Cortex-M spec the task start address should 161 * have bit-0 clear, as it is loaded into the PC on exit from an ISR. / 176 #define portADD_UINT32_WILL_OVERFLOW( a, b ) ( ( a ) > ( portUINT32_MAX - ( b ) ) ) 177 /-----------------------------------------------------------*/ [all …]
/Kernel-v11.1.0/portable/GCC/ARM_CM3_MPU/
D	port.c	5 * SPDX-License-Identifier: MIT 29 /----------------------------------------------------------- 31 ----------------------------------------------------------/ 123 / For strict compliance with the Cortex-M spec the task start address should 124 * have bit-0 clear, as it is loaded into the PC on exit from an ISR. / 139 #define portADD_UINT32_WILL_OVERFLOW( a, b ) ( ( a ) > ( portUINT32_MAX - ( b ) ) ) 140 /-----------------------------------------------------------/ 191 Bit[0] = 0 --> The processor is running privileged 192 * Bit[0] = 1 --> The processor is running unprivileged. 260 /-----------------------------------------------------------/ [all …]
/Kernel-v11.1.0/portable/RVDS/ARM_CM4_MPU/
D	port.c	5 * SPDX-License-Identifier: MIT 29 /----------------------------------------------------------- 31 ----------------------------------------------------------/ 66 / Constants used to detect Cortex-M7 r0p0 and r0p1 cores, and ensure 128 /* For strict compliance with the Cortex-M spec the task start address should 129 * have bit-0 clear, as it is loaded into the PC on exit from an ISR. / 144 #define portADD_UINT32_WILL_OVERFLOW( a, b ) ( ( a ) > ( portUINT32_MAX - ( b ) ) ) 145 /-----------------------------------------------------------/ 234 Bit[0] = 0 --> The processor is running privileged 235 * Bit[0] = 1 --> The processor is running unprivileged. [all …]
/Kernel-v11.1.0/portable/GCC/ARM_CM4_MPU/
D	port.c	5 * SPDX-License-Identifier: MIT 29 /----------------------------------------------------------- 31 ----------------------------------------------------------/ 77 / Constants used to detect Cortex-M7 r0p0 and r0p1 cores, and ensure 139 /* For strict compliance with the Cortex-M spec the task start address should 140 * have bit-0 clear, as it is loaded into the PC on exit from an ISR. / 155 #define portADD_UINT32_WILL_OVERFLOW( a, b ) ( ( a ) > ( portUINT32_MAX - ( b ) ) ) 156 /-----------------------------------------------------------/ 212 Bit[0] = 0 --> The processor is running privileged 213 * Bit[0] = 1 --> The processor is running unprivileged. [all …]
/Kernel-v11.1.0/portable/IAR/ARM_CM35P_NTZ/non_secure/
D	port.c	5 * SPDX-License-Identifier: MIT 55 * i.e. the processor boots as secure and never jumps to the non-secure side. 62 * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support: 65 * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support: 73 * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23 81 /-----------------------------------------------------------/ 87 /-----------------------------------------------------------/ 105 /-----------------------------------------------------------/ 113 /-----------------------------------------------------------/ 120 /-----------------------------------------------------------/ [all …]