1 /*
2 * FreeRTOS Kernel V11.1.0
3 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy of
8 * this software and associated documentation files (the "Software"), to deal in
9 * the Software without restriction, including without limitation the rights to
10 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
11 * the Software, and to permit persons to whom the Software is furnished to do so,
12 * subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in all
15 * copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
21 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * https://www.FreeRTOS.org
25 * https://github.com/FreeRTOS
26 *
27 */
28
29 /*-----------------------------------------------------------
30 * Implementation of functions defined in portable.h for the ARM CM3 port.
31 *----------------------------------------------------------*/
32
33 /* Scheduler includes. */
34 #include "FreeRTOS.h"
35 #include "task.h"
36
37 #if configMAX_SYSCALL_INTERRUPT_PRIORITY == 0
38 #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
39 #endif
40
41 /* Legacy macro for backward compatibility only. This macro used to be used to
42 * replace the function that configures the clock used to generate the tick
43 * interrupt (prvSetupTimerInterrupt()), but now the function is declared weak so
44 * the application writer can override it by simply defining a function of the
45 * same name (vApplicationSetupTickInterrupt()). */
46 #ifndef configOVERRIDE_DEFAULT_TICK_CONFIGURATION
47 #define configOVERRIDE_DEFAULT_TICK_CONFIGURATION 0
48 #endif
49
50 /* Constants required to manipulate the core. Registers first... */
51 #define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )
52 #define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )
53 #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) )
54 #define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
55 /* ...then bits in the registers. */
56 #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
57 #define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
58 #define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
59 #define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
60 #define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
61 #define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
62 #define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
63
64 #define portMIN_INTERRUPT_PRIORITY ( 255UL )
65 #define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
66 #define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
67
68 /* Constants required to check the validity of an interrupt priority. */
69 #define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
70 #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
71 #define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
72 #define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
73 #define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
74 #define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
75 #define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
76 #define portPRIGROUP_SHIFT ( 8UL )
77
78 /* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
79 #define portVECTACTIVE_MASK ( 0xFFUL )
80
81 /* Constants required to set up the initial stack. */
82 #define portINITIAL_XPSR ( 0x01000000 )
83
84 /* The systick is a 24-bit counter. */
85 #define portMAX_24_BIT_NUMBER ( 0xffffffUL )
86
87 /* A fiddle factor to estimate the number of SysTick counts that would have
88 * occurred while the SysTick counter is stopped during tickless idle
89 * calculations. */
90 #define portMISSED_COUNTS_FACTOR ( 94UL )
91
92 /* For strict compliance with the Cortex-M spec the task start address should
93 * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
94 #define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
95
96 /* Let the user override the default SysTick clock rate. If defined by the
97 * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the
98 * configuration register. */
99 #ifndef configSYSTICK_CLOCK_HZ
100 #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ )
101 /* Ensure the SysTick is clocked at the same frequency as the core. */
102 #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT )
103 #else
104 /* Select the option to clock SysTick not at the same frequency as the core. */
105 #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 )
106 #endif
107
108 /*
109 * Setup the timer to generate the tick interrupts. The implementation in this
110 * file is weak to allow application writers to change the timer used to
111 * generate the tick interrupt.
112 */
113 void vPortSetupTimerInterrupt( void );
114
115 /*
116 * Exception handlers.
117 */
118 void xPortPendSVHandler( void );
119 void xPortSysTickHandler( void );
120 void vPortSVCHandler( void );
121
122 /*
123 * Start first task is a separate function so it can be tested in isolation.
124 */
125 static void prvStartFirstTask( void );
126
127 /*
128 * Used to catch tasks that attempt to return from their implementing function.
129 */
130 static void prvTaskExitError( void );
131
132 /*-----------------------------------------------------------*/
133
134 /* Each task maintains its own interrupt status in the critical nesting
135 * variable. */
136 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
137
138 /*
139 * The number of SysTick increments that make up one tick period.
140 */
141 #if ( configUSE_TICKLESS_IDLE == 1 )
142 static uint32_t ulTimerCountsForOneTick = 0;
143 #endif /* configUSE_TICKLESS_IDLE */
144
145 /*
146 * The maximum number of tick periods that can be suppressed is limited by the
147 * 24 bit resolution of the SysTick timer.
148 */
149 #if ( configUSE_TICKLESS_IDLE == 1 )
150 static uint32_t xMaximumPossibleSuppressedTicks = 0;
151 #endif /* configUSE_TICKLESS_IDLE */
152
153 /*
154 * Compensate for the CPU cycles that pass while the SysTick is stopped (low
155 * power functionality only.
156 */
157 #if ( configUSE_TICKLESS_IDLE == 1 )
158 static uint32_t ulStoppedTimerCompensation = 0;
159 #endif /* configUSE_TICKLESS_IDLE */
160
161 /*
162 * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
163 * FreeRTOS API functions are not called from interrupts that have been assigned
164 * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
165 */
166 #if ( configASSERT_DEFINED == 1 )
167 static uint8_t ucMaxSysCallPriority = 0;
168 static uint32_t ulMaxPRIGROUPValue = 0;
169 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
170 #endif /* configASSERT_DEFINED */
171
172 /*-----------------------------------------------------------*/
173
174 /*
175 * See header file for description.
176 */
pxPortInitialiseStack(StackType_t * pxTopOfStack,TaskFunction_t pxCode,void * pvParameters)177 StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
178 TaskFunction_t pxCode,
179 void * pvParameters )
180 {
181 /* Simulate the stack frame as it would be created by a context switch
182 * interrupt. */
183 pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
184 *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
185 pxTopOfStack--;
186 *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
187 pxTopOfStack--;
188 *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* LR */
189
190 pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
191 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
192 pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
193
194 return pxTopOfStack;
195 }
196 /*-----------------------------------------------------------*/
197
prvTaskExitError(void)198 static void prvTaskExitError( void )
199 {
200 /* A function that implements a task must not exit or attempt to return to
201 * its caller as there is nothing to return to. If a task wants to exit it
202 * should instead call vTaskDelete( NULL ).
203 *
204 * Artificially force an assert() to be triggered if configASSERT() is
205 * defined, then stop here so application writers can catch the error. */
206 configASSERT( uxCriticalNesting == ~0UL );
207 portDISABLE_INTERRUPTS();
208
209 for( ; ; )
210 {
211 }
212 }
213 /*-----------------------------------------------------------*/
214
vPortSVCHandler(void)215 __asm void vPortSVCHandler( void )
216 {
217 /* *INDENT-OFF* */
218 PRESERVE8
219
220 ldr r3, = pxCurrentTCB /* Restore the context. */
221 ldr r1, [ r3 ] /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
222 ldr r0, [ r1 ] /* The first item in pxCurrentTCB is the task top of stack. */
223 ldmia r0 !, { r4 - r11 } /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
224 msr psp, r0 /* Restore the task stack pointer. */
225 isb
226 mov r0, # 0
227 msr basepri, r0
228 orr r14, # 0xd
229 bx r14
230 /* *INDENT-ON* */
231 }
232 /*-----------------------------------------------------------*/
233
prvStartFirstTask(void)234 __asm void prvStartFirstTask( void )
235 {
236 /* *INDENT-OFF* */
237 PRESERVE8
238
239 /* Use the NVIC offset register to locate the stack. */
240 ldr r0, =0xE000ED08
241 ldr r0, [ r0 ]
242 ldr r0, [ r0 ]
243
244 /* Set the msp back to the start of the stack. */
245 msr msp, r0
246 /* Globally enable interrupts. */
247 cpsie i
248 cpsie f
249 dsb
250 isb
251 /* Call SVC to start the first task. */
252 svc 0
253 nop
254 nop
255 /* *INDENT-ON* */
256 }
257 /*-----------------------------------------------------------*/
258
259 /*
260 * See header file for description.
261 */
xPortStartScheduler(void)262 BaseType_t xPortStartScheduler( void )
263 {
264 #if ( configASSERT_DEFINED == 1 )
265 {
266 volatile uint8_t ucOriginalPriority;
267 volatile uint32_t ulImplementedPrioBits = 0;
268 volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
269 volatile uint8_t ucMaxPriorityValue;
270
271 /* Determine the maximum priority from which ISR safe FreeRTOS API
272 * functions can be called. ISR safe functions are those that end in
273 * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
274 * ensure interrupt entry is as fast and simple as possible.
275 *
276 * Save the interrupt priority value that is about to be clobbered. */
277 ucOriginalPriority = *pucFirstUserPriorityRegister;
278
279 /* Determine the number of priority bits available. First write to all
280 * possible bits. */
281 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
282
283 /* Read the value back to see how many bits stuck. */
284 ucMaxPriorityValue = *pucFirstUserPriorityRegister;
285
286 /* Use the same mask on the maximum system call priority. */
287 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
288
289 /* Check that the maximum system call priority is nonzero after
290 * accounting for the number of priority bits supported by the
291 * hardware. A priority of 0 is invalid because setting the BASEPRI
292 * register to 0 unmasks all interrupts, and interrupts with priority 0
293 * cannot be masked using BASEPRI.
294 * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
295 configASSERT( ucMaxSysCallPriority );
296
297 /* Check that the bits not implemented in hardware are zero in
298 * configMAX_SYSCALL_INTERRUPT_PRIORITY. */
299 configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
300
301 /* Calculate the maximum acceptable priority group value for the number
302 * of bits read back. */
303
304 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
305 {
306 ulImplementedPrioBits++;
307 ucMaxPriorityValue <<= ( uint8_t ) 0x01;
308 }
309
310 if( ulImplementedPrioBits == 8 )
311 {
312 /* When the hardware implements 8 priority bits, there is no way for
313 * the software to configure PRIGROUP to not have sub-priorities. As
314 * a result, the least significant bit is always used for sub-priority
315 * and there are 128 preemption priorities and 2 sub-priorities.
316 *
317 * This may cause some confusion in some cases - for example, if
318 * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
319 * priority interrupts will be masked in Critical Sections as those
320 * are at the same preemption priority. This may appear confusing as
321 * 4 is higher (numerically lower) priority than
322 * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
323 * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
324 * to 4, this confusion does not happen and the behaviour remains the same.
325 *
326 * The following assert ensures that the sub-priority bit in the
327 * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
328 * confusion. */
329 configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
330 ulMaxPRIGROUPValue = 0;
331 }
332 else
333 {
334 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
335 }
336
337 /* Shift the priority group value back to its position within the AIRCR
338 * register. */
339 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
340 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
341
342 /* Restore the clobbered interrupt priority register to its original
343 * value. */
344 *pucFirstUserPriorityRegister = ucOriginalPriority;
345 }
346 #endif /* configASSERT_DEFINED */
347
348 /* Make PendSV and SysTick the lowest priority interrupts. */
349 portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
350
351 portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
352
353 /* Start the timer that generates the tick ISR. Interrupts are disabled
354 * here already. */
355 vPortSetupTimerInterrupt();
356
357 /* Initialise the critical nesting count ready for the first task. */
358 uxCriticalNesting = 0;
359
360 /* Start the first task. */
361 prvStartFirstTask();
362
363 /* Should not get here! */
364 return 0;
365 }
366 /*-----------------------------------------------------------*/
367
vPortEndScheduler(void)368 void vPortEndScheduler( void )
369 {
370 /* Not implemented in ports where there is nothing to return to.
371 * Artificially force an assert. */
372 configASSERT( uxCriticalNesting == 1000UL );
373 }
374 /*-----------------------------------------------------------*/
375
vPortEnterCritical(void)376 void vPortEnterCritical( void )
377 {
378 portDISABLE_INTERRUPTS();
379 uxCriticalNesting++;
380
381 /* This is not the interrupt safe version of the enter critical function so
382 * assert() if it is being called from an interrupt context. Only API
383 * functions that end in "FromISR" can be used in an interrupt. Only assert if
384 * the critical nesting count is 1 to protect against recursive calls if the
385 * assert function also uses a critical section. */
386 if( uxCriticalNesting == 1 )
387 {
388 configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
389 }
390 }
391 /*-----------------------------------------------------------*/
392
vPortExitCritical(void)393 void vPortExitCritical( void )
394 {
395 configASSERT( uxCriticalNesting );
396 uxCriticalNesting--;
397
398 if( uxCriticalNesting == 0 )
399 {
400 portENABLE_INTERRUPTS();
401 }
402 }
403 /*-----------------------------------------------------------*/
404
xPortPendSVHandler(void)405 __asm void xPortPendSVHandler( void )
406 {
407 extern uxCriticalNesting;
408 extern pxCurrentTCB;
409 extern vTaskSwitchContext;
410
411 /* *INDENT-OFF* */
412 PRESERVE8
413
414 mrs r0, psp
415 isb
416
417 ldr r3, =pxCurrentTCB /* Get the location of the current TCB. */
418 ldr r2, [ r3 ]
419
420 stmdb r0 !, { r4 - r11 } /* Save the remaining registers. */
421 str r0, [ r2 ] /* Save the new top of stack into the first member of the TCB. */
422
423 stmdb sp !, { r3, r14 }
424 mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
425 msr basepri, r0
426 dsb
427 isb
428 bl vTaskSwitchContext
429 mov r0, #0
430 msr basepri, r0
431 ldmia sp !, { r3, r14 }
432
433 ldr r1, [ r3 ]
434 ldr r0, [ r1 ] /* The first item in pxCurrentTCB is the task top of stack. */
435 ldmia r0 !, { r4 - r11 } /* Pop the registers and the critical nesting count. */
436 msr psp, r0
437 isb
438 bx r14
439 nop
440 /* *INDENT-ON* */
441 }
442 /*-----------------------------------------------------------*/
443
xPortSysTickHandler(void)444 void xPortSysTickHandler( void )
445 {
446 /* The SysTick runs at the lowest interrupt priority, so when this interrupt
447 * executes all interrupts must be unmasked. There is therefore no need to
448 * save and then restore the interrupt mask value as its value is already
449 * known - therefore the slightly faster vPortRaiseBASEPRI() function is used
450 * in place of portSET_INTERRUPT_MASK_FROM_ISR(). */
451 vPortRaiseBASEPRI();
452 traceISR_ENTER();
453 {
454 /* Increment the RTOS tick. */
455 if( xTaskIncrementTick() != pdFALSE )
456 {
457 traceISR_EXIT_TO_SCHEDULER();
458
459 /* A context switch is required. Context switching is performed in
460 * the PendSV interrupt. Pend the PendSV interrupt. */
461 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
462 }
463 else
464 {
465 traceISR_EXIT();
466 }
467 }
468
469 vPortClearBASEPRIFromISR();
470 }
471 /*-----------------------------------------------------------*/
472
473 #if ( configUSE_TICKLESS_IDLE == 1 )
474
vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime)475 __weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
476 {
477 uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
478 TickType_t xModifiableIdleTime;
479
480 /* Make sure the SysTick reload value does not overflow the counter. */
481 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
482 {
483 xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
484 }
485
486 /* Enter a critical section but don't use the taskENTER_CRITICAL()
487 * method as that will mask interrupts that should exit sleep mode. */
488 __disable_irq();
489 __dsb( portSY_FULL_READ_WRITE );
490 __isb( portSY_FULL_READ_WRITE );
491
492 /* If a context switch is pending or a task is waiting for the scheduler
493 * to be unsuspended then abandon the low power entry. */
494 if( eTaskConfirmSleepModeStatus() == eAbortSleep )
495 {
496 /* Re-enable interrupts - see comments above the __disable_irq()
497 * call above. */
498 __enable_irq();
499 }
500 else
501 {
502 /* Stop the SysTick momentarily. The time the SysTick is stopped for
503 * is accounted for as best it can be, but using the tickless mode will
504 * inevitably result in some tiny drift of the time maintained by the
505 * kernel with respect to calendar time. */
506 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
507
508 /* Use the SysTick current-value register to determine the number of
509 * SysTick decrements remaining until the next tick interrupt. If the
510 * current-value register is zero, then there are actually
511 * ulTimerCountsForOneTick decrements remaining, not zero, because the
512 * SysTick requests the interrupt when decrementing from 1 to 0. */
513 ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
514
515 if( ulSysTickDecrementsLeft == 0 )
516 {
517 ulSysTickDecrementsLeft = ulTimerCountsForOneTick;
518 }
519
520 /* Calculate the reload value required to wait xExpectedIdleTime
521 * tick periods. -1 is used because this code normally executes part
522 * way through the first tick period. But if the SysTick IRQ is now
523 * pending, then clear the IRQ, suppressing the first tick, and correct
524 * the reload value to reflect that the second tick period is already
525 * underway. The expected idle time is always at least two ticks. */
526 ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
527
528 if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )
529 {
530 portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;
531 ulReloadValue -= ulTimerCountsForOneTick;
532 }
533
534 if( ulReloadValue > ulStoppedTimerCompensation )
535 {
536 ulReloadValue -= ulStoppedTimerCompensation;
537 }
538
539 /* Set the new reload value. */
540 portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
541
542 /* Clear the SysTick count flag and set the count value back to
543 * zero. */
544 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
545
546 /* Restart SysTick. */
547 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
548
549 /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
550 * set its parameter to 0 to indicate that its implementation contains
551 * its own wait for interrupt or wait for event instruction, and so wfi
552 * should not be executed again. However, the original expected idle
553 * time variable must remain unmodified, so a copy is taken. */
554 xModifiableIdleTime = xExpectedIdleTime;
555 configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
556
557 if( xModifiableIdleTime > 0 )
558 {
559 __dsb( portSY_FULL_READ_WRITE );
560 __wfi();
561 __isb( portSY_FULL_READ_WRITE );
562 }
563
564 configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
565
566 /* Re-enable interrupts to allow the interrupt that brought the MCU
567 * out of sleep mode to execute immediately. See comments above
568 * the __disable_irq() call above. */
569 __enable_irq();
570 __dsb( portSY_FULL_READ_WRITE );
571 __isb( portSY_FULL_READ_WRITE );
572
573 /* Disable interrupts again because the clock is about to be stopped
574 * and interrupts that execute while the clock is stopped will increase
575 * any slippage between the time maintained by the RTOS and calendar
576 * time. */
577 __disable_irq();
578 __dsb( portSY_FULL_READ_WRITE );
579 __isb( portSY_FULL_READ_WRITE );
580
581 /* Disable the SysTick clock without reading the
582 * portNVIC_SYSTICK_CTRL_REG register to ensure the
583 * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again,
584 * the time the SysTick is stopped for is accounted for as best it can
585 * be, but using the tickless mode will inevitably result in some tiny
586 * drift of the time maintained by the kernel with respect to calendar
587 * time*/
588 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
589
590 /* Determine whether the SysTick has already counted to zero. */
591 if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
592 {
593 uint32_t ulCalculatedLoadValue;
594
595 /* The tick interrupt ended the sleep (or is now pending), and
596 * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG
597 * with whatever remains of the new tick period. */
598 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
599
600 /* Don't allow a tiny value, or values that have somehow
601 * underflowed because the post sleep hook did something
602 * that took too long or because the SysTick current-value register
603 * is zero. */
604 if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
605 {
606 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
607 }
608
609 portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
610
611 /* As the pending tick will be processed as soon as this
612 * function exits, the tick value maintained by the tick is stepped
613 * forward by one less than the time spent waiting. */
614 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
615 }
616 else
617 {
618 /* Something other than the tick interrupt ended the sleep. */
619
620 /* Use the SysTick current-value register to determine the
621 * number of SysTick decrements remaining until the expected idle
622 * time would have ended. */
623 ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
624 #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )
625 {
626 /* If the SysTick is not using the core clock, the current-
627 * value register might still be zero here. In that case, the
628 * SysTick didn't load from the reload register, and there are
629 * ulReloadValue decrements remaining in the expected idle
630 * time, not zero. */
631 if( ulSysTickDecrementsLeft == 0 )
632 {
633 ulSysTickDecrementsLeft = ulReloadValue;
634 }
635 }
636 #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
637
638 /* Work out how long the sleep lasted rounded to complete tick
639 * periods (not the ulReload value which accounted for part
640 * ticks). */
641 ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;
642
643 /* How many complete tick periods passed while the processor
644 * was waiting? */
645 ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
646
647 /* The reload value is set to whatever fraction of a single tick
648 * period remains. */
649 portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
650 }
651
652 /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,
653 * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If
654 * the SysTick is not using the core clock, temporarily configure it to
655 * use the core clock. This configuration forces the SysTick to load
656 * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next
657 * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready
658 * to receive the standard value immediately. */
659 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
660 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
661 #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )
662 {
663 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
664 }
665 #else
666 {
667 /* The temporary usage of the core clock has served its purpose,
668 * as described above. Resume usage of the other clock. */
669 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;
670
671 if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
672 {
673 /* The partial tick period already ended. Be sure the SysTick
674 * counts it only once. */
675 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;
676 }
677
678 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
679 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
680 }
681 #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
682
683 /* Step the tick to account for any tick periods that elapsed. */
684 vTaskStepTick( ulCompleteTickPeriods );
685
686 /* Exit with interrupts enabled. */
687 __enable_irq();
688 }
689 }
690
691 #endif /* #if configUSE_TICKLESS_IDLE */
692
693 /*-----------------------------------------------------------*/
694
695 /*
696 * Setup the SysTick timer to generate the tick interrupts at the required
697 * frequency.
698 */
699 #if ( configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0 )
700
vPortSetupTimerInterrupt(void)701 __weak void vPortSetupTimerInterrupt( void )
702 {
703 /* Calculate the constants required to configure the tick interrupt. */
704 #if ( configUSE_TICKLESS_IDLE == 1 )
705 {
706 ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
707 xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
708 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
709 }
710 #endif /* configUSE_TICKLESS_IDLE */
711
712 /* Stop and clear the SysTick. */
713 portNVIC_SYSTICK_CTRL_REG = 0UL;
714 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
715
716 /* Configure SysTick to interrupt at the requested rate. */
717 portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
718 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
719 }
720
721 #endif /* configOVERRIDE_DEFAULT_TICK_CONFIGURATION */
722 /*-----------------------------------------------------------*/
723
vPortGetIPSR(void)724 __asm uint32_t vPortGetIPSR( void )
725 {
726 /* *INDENT-OFF* */
727 PRESERVE8
728
729 mrs r0, ipsr
730 bx r14
731 /* *INDENT-ON* */
732 }
733 /*-----------------------------------------------------------*/
734
735 #if ( configASSERT_DEFINED == 1 )
736
vPortValidateInterruptPriority(void)737 void vPortValidateInterruptPriority( void )
738 {
739 uint32_t ulCurrentInterrupt;
740 uint8_t ucCurrentPriority;
741
742 /* Obtain the number of the currently executing interrupt. */
743 ulCurrentInterrupt = vPortGetIPSR();
744
745 /* Is the interrupt number a user defined interrupt? */
746 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
747 {
748 /* Look up the interrupt's priority. */
749 ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
750
751 /* The following assertion will fail if a service routine (ISR) for
752 * an interrupt that has been assigned a priority above
753 * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
754 * function. ISR safe FreeRTOS API functions must *only* be called
755 * from interrupts that have been assigned a priority at or below
756 * configMAX_SYSCALL_INTERRUPT_PRIORITY.
757 *
758 * Numerically low interrupt priority numbers represent logically high
759 * interrupt priorities, therefore the priority of the interrupt must
760 * be set to a value equal to or numerically *higher* than
761 * configMAX_SYSCALL_INTERRUPT_PRIORITY.
762 *
763 * Interrupts that use the FreeRTOS API must not be left at their
764 * default priority of zero as that is the highest possible priority,
765 * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
766 * and therefore also guaranteed to be invalid.
767 *
768 * FreeRTOS maintains separate thread and ISR API functions to ensure
769 * interrupt entry is as fast and simple as possible.
770 *
771 * The following links provide detailed information:
772 * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
773 * https://www.FreeRTOS.org/FAQHelp.html */
774 configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
775 }
776
777 /* Priority grouping: The interrupt controller (NVIC) allows the bits
778 * that define each interrupt's priority to be split between bits that
779 * define the interrupt's pre-emption priority bits and bits that define
780 * the interrupt's sub-priority. For simplicity all bits must be defined
781 * to be pre-emption priority bits. The following assertion will fail if
782 * this is not the case (if some bits represent a sub-priority).
783 *
784 * If the application only uses CMSIS libraries for interrupt
785 * configuration then the correct setting can be achieved on all Cortex-M
786 * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
787 * scheduler. Note however that some vendor specific peripheral libraries
788 * assume a non-zero priority group setting, in which cases using a value
789 * of zero will result in unpredictable behaviour. */
790 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
791 }
792
793 #endif /* configASSERT_DEFINED */
794
