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/Kernel-v11.1.0/
DCMakeLists.txt9 # DEPRECATED: FREERTOS_CONFIG_FILE_DIRECTORY - but still supported if no freertos_config defined fo…
31 …message(WARNING " Using deprecated 'FREERTOS_CONFIG_FILE_DIRECTORY' - please update your project C…
44 …message(WARNING " FREERTOS_PORT is not set. Please specify it from top-level CMake file (example):…
47 " -DFREERTOS_PORT=GCC_ARM_CM4F\n"
50 " A_CUSTOM_PORT - Compiler: User Defined Target: User Defined\n"
51 " BCC_16BIT_DOS_FLSH186 - Compiler: BCC Target: 16 bit DOS Flsh186\n"
52 " BCC_16BIT_DOS_PC - Compiler: BCC Target: 16 bit DOS PC\n"
53 " CCS_ARM_CM3 - Compiler: CCS Target: ARM Cortex-M3\n"
54 … " CCS_ARM_CM4F - Compiler: CCS Target: ARM Cortex-M4 with FPU\n"
55 " CCS_ARM_CR4 - Compiler: CCS Target: ARM Cortex-R4\n"
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DHistory.txt5 + Add ARMv7-R port with Memory Protection Unit (MPU) support.
6 + Add Memory Protection Unit (MPU) support to the Cortex-M0 port.
8 buffer when a task reads from a non-empty buffer:
9 - The task reading from a non-empty stream buffer returns immediately
11 - The task reading from a non-empty steam batching buffer blocks until the
37 + Add 64-bit support to the FreeRTOS Windows Simulator port. We thank @watsk
39 + Add support for 64-bit Microblaze processor to the MicroblazeV9 port. We
42 the MSP430F449 port to make it work with both MSP430 GCC and MSPGCC
43 compilers. We thank @Forty-Bot for their contribution.
54 POSIX timers to address issues with signal handling in non-FreeRTOS
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/Kernel-v11.1.0/portable/
DCMakeLists.txt2 include( GCC/RISC-V/chip_extensions.cmake )
6 include( IAR/RISC-V/chip_extensions.cmake )
9 # FreeRTOS internal cmake file. Do not use it in user top-level project
16 # FreeRTOS internal cmake file. Do not use it in user top-level project
23 # 16-Bit DOS ports for BCC
32 # ARMv7-M port for Texas Instruments Code Composer Studio
37 # ARMv7E-M port for Texas Instruments Code Composer Studio
42 # ARMv7-R port for Texas Instruments Code Composer Studio
44 CCS/ARM_Cortex-R4/port.c
45 CCS/ARM_Cortex-R4/portASM.asm>
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/Kernel-v11.1.0/.github/workflows/
Dkernel-demos.yml1 name: FreeRTOS-Kernel Demos
6 bashPass: \033[32;1mPASSED -
7 bashInfo: \033[33;1mINFO -
8 bashFail: \033[31;1mFAILED -
12 WIN32-MSVC:
14 runs-on: windows-latest
16 - name: Checkout the FreeRTOS/FreeRTOS Repository
22 fetch-depth: 1
25 - name: Checkout Pull Request
30 - name: Add msbuild to PATH
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/Kernel-v11.1.0/portable/GCC/ARM_CM7/
DReadMe.txt1 There are two options for running FreeRTOS on ARM Cortex-M7 microcontrollers.
2 The best option depends on the revision of the ARM Cortex-M7 core in use. The
5 revision of the Cortex-M7 core used in that microcontroller. If in doubt, use
9 The first option is to use the ARM Cortex-M4F port, and the second option is to
10 use the Cortex-M7 r0p1 port - the latter containing a minor errata workaround.
12 If the revision of the ARM Cortex-M7 core is not r0p1 then either option can be
13 used, but it is recommended to use the FreeRTOS ARM Cortex-M4F port located in
14 the /FreeRTOS/Source/portable/GCC/ARM_CM4F directory.
16 If the revision of the ARM Cortex-M7 core is r0p1 then use the FreeRTOS ARM
17 Cortex-M7 r0p1 port located in the /FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1
/Kernel-v11.1.0/portable/ThirdParty/GCC/ARM_TFM/
DREADME.md4 services in Trusted Firmware M(TF-M) through Platform Security Architecture
5 (PSA) API based on the ARM Cortex-M23, Cortex-M33, Cortex-M55 and Cortex-M85
10 …t, and certify. See [PSA Resource Page](https://www.arm.com/architecture/security-features/platfor…
12 TF-M is an open source project. It provides a reference implementation of PSA
13 for Arm M-profile architecture. Please get the details from this [link](https://www.trustedfirmware…
19 in trusted-firmware-m (tag: TF-Mv2.0.0). The implementation is based on
26 * Step 2: build the nonsecure image. Please follow the **Build the Non-Secure Side** for details.
30 ### Get the TF-M source code
32 …git.trustedfirmware.org/TF-M/trusted-firmware-m.git/) to get the source code. This port is support…
34 ### Build TF-M
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/Kernel-v11.1.0/portable/GCC/ARM7_LPC2000/
DportISR.c5 * SPDX-License-Identifier: MIT
30 /*-----------------------------------------------------------
31 * Components that can be compiled to either ARM or THUMB mode are
33 * to ARM mode, are contained in this file.
34 *----------------------------------------------------------*/
41 + The functions are now also the same for both ARM and THUMB modes.
66 /*-----------------------------------------------------------*/
72 * The scheduler can only be started from ARM mode, hence the inclusion of this
76 /*-----------------------------------------------------------*/
81 * called from ARM mode. */ in vPortISRStartFirstTask()
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/Kernel-v11.1.0/portable/GCC/ARM7_LPC23xx/
DportISR.c5 * SPDX-License-Identifier: MIT
30 /*-----------------------------------------------------------
31 * Components that can be compiled to either ARM or THUMB mode are
33 * to ARM mode, are contained in this file.
34 *----------------------------------------------------------*/
48 /*-----------------------------------------------------------*/
54 * The scheduler can only be started from ARM mode, hence the inclusion of this
58 /*-----------------------------------------------------------*/
63 * called from ARM mode. */ in vPortISRStartFirstTask()
66 /*-----------------------------------------------------------*/
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Dportmacro.h5 * SPDX-License-Identifier: MIT
32 + Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1.
55 /* *INDENT-OFF* */
59 /* *INDENT-ON* */
61 /*-----------------------------------------------------------
68 *-----------------------------------------------------------
93 /*-----------------------------------------------------------*/
96 #define portSTACK_GROWTH ( -1 )
100 /*-----------------------------------------------------------*/
107 * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but
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/Kernel-v11.1.0/portable/GCC/ARM7_AT91FR40008/
DportISR.c5 * SPDX-License-Identifier: MIT
30 /*-----------------------------------------------------------
31 * Components that can be compiled to either ARM or THUMB mode are
33 * to ARM mode, are contained in this file.
34 *----------------------------------------------------------*/
55 /*-----------------------------------------------------------*/
61 * The scheduler can only be started from ARM mode, hence the inclusion of this
65 /*-----------------------------------------------------------*/
70 * called from ARM mode. */ in vPortISRStartFirstTask()
73 /*-----------------------------------------------------------*/
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Dportmacro.h5 * SPDX-License-Identifier: MIT
32 + Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1.
55 /* *INDENT-OFF* */
59 /* *INDENT-ON* */
61 /*-----------------------------------------------------------
68 *-----------------------------------------------------------
93 /*-----------------------------------------------------------*/
96 #define portSTACK_GROWTH ( -1 )
110 /*-----------------------------------------------------------*/
116 * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but
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/Kernel-v11.1.0/portable/GCC/ARM7_AT91SAM7S/
DportISR.c5 * SPDX-License-Identifier: MIT
30 /*-----------------------------------------------------------
31 * Components that can be compiled to either ARM or THUMB mode are
33 * to ARM mode, are contained in this file.
34 *----------------------------------------------------------*/
57 /*-----------------------------------------------------------*/
63 * The scheduler can only be started from ARM mode, hence the inclusion of this
67 /*-----------------------------------------------------------*/
72 * called from ARM mode. */ in vPortISRStartFirstTask()
75 /*-----------------------------------------------------------*/
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Dportmacro.h5 * SPDX-License-Identifier: MIT
32 + Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1.
55 /* *INDENT-OFF* */
59 /* *INDENT-ON* */
61 /*-----------------------------------------------------------
68 *-----------------------------------------------------------
93 /*-----------------------------------------------------------*/
96 #define portSTACK_GROWTH ( -1 )
100 /*-----------------------------------------------------------*/
107 * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but
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/Kernel-v11.1.0/portable/GCC/ARM_CRx_MPU/
Dportmacro.h5 * SPDX-License-Identifier: MIT
33 * @brief Functions, Defines, and Structs for use in the ARM_CRx_MPU FreeRTOS-Port
46 /* ------------------------------ FreeRTOS Config Check ------------------------------ */
62 /* ----------------------------------------------------------------------------------- */
105 ( uxTopPriority ) = ( 31UL - ulPortCountLeadingZeros( ( uxTopReadyPriority ) ) )
109 /* ------------------------------ Port Type Definitions ------------------------------ */
162 * @note Using 32-bit tick type on a 32-bit architecture ensures that reads of
172 #define portSTACK_GROWTH ( -1 )
204 * @brief The no-op ARM assembly instruction.
211 * @brief The inline GCC label.
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/Kernel-v11.1.0/include/
Dlist.h5 * SPDX-License-Identifier: MIT
41 * points to this marker - even though it is at the tail of the list. This
73 * instructions generated by the IAR, ARM and GCC compilers when the respective
97 /* *INDENT-OFF* */
101 /* *INDENT-ON* */
128 …#define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) ( pxItem )->xListItemIntegrity…
129 …#define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) ( pxItem )->xListItemIntegrity…
130 …#define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ) ( pxList )->xListIntegrityValu…
131 …#define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList ) ( pxList )->xListIntegrityValu…
135 … configASSERT( ( ( pxItem )->xListItemIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) &&…
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/Kernel-v11.1.0/portable/IAR/ARM_CM4F/
Dport.c5 * SPDX-License-Identifier: MIT
29 /*-----------------------------------------------------------
30 * Implementation of functions defined in portable.h for the ARM CM4F port.
31 *----------------------------------------------------------*/
45 …LL_INTERRUPT_PRIORITY must not be set to 0. See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
66 /* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7
102 /* The systick is a 24-bit counter. */
110 /* For strict compliance with the Cortex-M spec the task start address should
111 * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
158 /*-----------------------------------------------------------*/
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/Kernel-v11.1.0/portable/RVDS/ARM_CM4F/
Dport.c5 * SPDX-License-Identifier: MIT
29 /*-----------------------------------------------------------
30 * Implementation of functions defined in portable.h for the ARM CM4F port.
31 *----------------------------------------------------------*/
42 …LL_INTERRUPT_PRIORITY must not be set to 0. See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
68 /* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7
99 /* The systick is a 24-bit counter. */
107 /* For strict compliance with the Cortex-M spec the task start address should
108 * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
152 /*-----------------------------------------------------------*/
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/Kernel-v11.1.0/portable/GCC/ARM_CM4F/
Dport.c5 * SPDX-License-Identifier: MIT
29 /*-----------------------------------------------------------
30 * Implementation of functions defined in portable.h for the ARM CM4F port.
31 *----------------------------------------------------------*/
59 /* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7
95 /* The systick is a 24-bit counter. */
98 /* For strict compliance with the Cortex-M spec the task start address should
99 * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
119 /* Let the user override the pre-loading of the initial LR with the address of
157 /*-----------------------------------------------------------*/
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