1 /*
2 * FreeRTOS Kernel V11.1.0
3 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy of
8 * this software and associated documentation files (the "Software"), to deal in
9 * the Software without restriction, including without limitation the rights to
10 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
11 * the Software, and to permit persons to whom the Software is furnished to do so,
12 * subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in all
15 * copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
21 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * https://www.FreeRTOS.org
25 * https://github.com/FreeRTOS
26 *
27 */
28
29
30 /*-----------------------------------------------------------
31 * Components that can be compiled to either ARM or THUMB mode are
32 * contained in port.c The ISR routines, which can only be compiled
33 * to ARM mode, are contained in this file.
34 *----------------------------------------------------------*/
35
36 /*
37 * Changes from V3.2.4
38 *
39 + The assembler statements are now included in a single asm block rather
40 + than each line having its own asm block.
41 */
42
43
44 /* Scheduler includes. */
45 #include "FreeRTOS.h"
46 #include "task.h"
47
48 /* Constants required to handle interrupts. */
49 #define portCLEAR_AIC_INTERRUPT ( ( uint32_t ) 0 )
50
51 /* Constants required to handle critical sections. */
52 #define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
53 volatile uint32_t ulCriticalNesting = 9999UL;
54
55 /*-----------------------------------------------------------*/
56
57 /* ISR to handle manual context switches (from a call to taskYIELD()). */
58 void vPortYieldProcessor( void ) __attribute__( ( interrupt( "SWI" ), naked ) );
59
60 /*
61 * The scheduler can only be started from ARM mode, hence the inclusion of this
62 * function here.
63 */
64 void vPortISRStartFirstTask( void );
65 /*-----------------------------------------------------------*/
66
vPortISRStartFirstTask(void)67 void vPortISRStartFirstTask( void )
68 {
69 /* Simply start the scheduler. This is included here as it can only be
70 * called from ARM mode. */
71 portRESTORE_CONTEXT();
72 }
73 /*-----------------------------------------------------------*/
74
75 /*
76 * Called by portYIELD() or taskYIELD() to manually force a context switch.
77 *
78 * When a context switch is performed from the task level the saved task
79 * context is made to look as if it occurred from within the tick ISR. This
80 * way the same restore context function can be used when restoring the context
81 * saved from the ISR or that saved from a call to vPortYieldProcessor.
82 */
vPortYieldProcessor(void)83 void vPortYieldProcessor( void )
84 {
85 /* Within an IRQ ISR the link register has an offset from the true return
86 * address, but an SWI ISR does not. Add the offset manually so the same
87 * ISR return code can be used in both cases. */
88 asm volatile ( "ADD LR, LR, #4" );
89
90 /* Perform the context switch. First save the context of the current task. */
91 portSAVE_CONTEXT();
92
93 /* Find the highest priority task that is ready to run. */
94 vTaskSwitchContext();
95
96 /* Restore the context of the new task. */
97 portRESTORE_CONTEXT();
98 }
99 /*-----------------------------------------------------------*/
100
101 /*
102 * The ISR used for the scheduler tick depends on whether the cooperative or
103 * the preemptive scheduler is being used.
104 */
105
106 #if configUSE_PREEMPTION == 0
107
108 /* The cooperative scheduler requires a normal IRQ service routine to
109 * simply increment the system tick. */
110 void vNonPreemptiveTick( void ) __attribute__( ( interrupt( "IRQ" ) ) );
vNonPreemptiveTick(void)111 void vNonPreemptiveTick( void )
112 {
113 static volatile uint32_t ulDummy;
114
115 /* Clear tick timer interrupt indication. */
116 ulDummy = portTIMER_REG_BASE_PTR->TC_SR;
117
118 xTaskIncrementTick();
119
120 /* Acknowledge the interrupt at AIC level... */
121 AT91C_BASE_AIC->AIC_EOICR = portCLEAR_AIC_INTERRUPT;
122 }
123
124 #else /* else preemption is turned on */
125
126 /* The preemptive scheduler is defined as "naked" as the full context is
127 * saved on entry as part of the context switch. */
128 void vPreemptiveTick( void ) __attribute__( ( naked ) );
vPreemptiveTick(void)129 void vPreemptiveTick( void )
130 {
131 /* Save the context of the interrupted task. */
132 portSAVE_CONTEXT();
133
134 /* WARNING - Do not use local (stack) variables here. Use globals
135 * if you must! */
136 static volatile uint32_t ulDummy;
137
138 /* Clear tick timer interrupt indication. */
139 ulDummy = portTIMER_REG_BASE_PTR->TC_SR;
140
141 /* Increment the RTOS tick count, then look for the highest priority
142 * task that is ready to run. */
143 if( xTaskIncrementTick() != pdFALSE )
144 {
145 vTaskSwitchContext();
146 }
147
148 /* Acknowledge the interrupt at AIC level... */
149 AT91C_BASE_AIC->AIC_EOICR = portCLEAR_AIC_INTERRUPT;
150
151 /* Restore the context of the new task. */
152 portRESTORE_CONTEXT();
153 }
154
155 #endif /* if configUSE_PREEMPTION == 0 */
156 /*-----------------------------------------------------------*/
157
158 /*
159 * The interrupt management utilities can only be called from ARM mode. When
160 * THUMB_INTERWORK is defined the utilities are defined as functions here to
161 * ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then
162 * the utilities are defined as macros in portmacro.h - as per other ports.
163 */
164 #ifdef THUMB_INTERWORK
165
166 void vPortDisableInterruptsFromThumb( void ) __attribute__( ( naked ) );
167 void vPortEnableInterruptsFromThumb( void ) __attribute__( ( naked ) );
168
vPortDisableInterruptsFromThumb(void)169 void vPortDisableInterruptsFromThumb( void )
170 {
171 asm volatile (
172 "STMDB SP!, {R0} \n\t" /* Push R0. */
173 "MRS R0, CPSR \n\t" /* Get CPSR. */
174 "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
175 "MSR CPSR, R0 \n\t" /* Write back modified value. */
176 "LDMIA SP!, {R0} \n\t" /* Pop R0. */
177 "BX R14" ); /* Return back to thumb. */
178 }
179
vPortEnableInterruptsFromThumb(void)180 void vPortEnableInterruptsFromThumb( void )
181 {
182 asm volatile (
183 "STMDB SP!, {R0} \n\t" /* Push R0. */
184 "MRS R0, CPSR \n\t" /* Get CPSR. */
185 "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
186 "MSR CPSR, R0 \n\t" /* Write back modified value. */
187 "LDMIA SP!, {R0} \n\t" /* Pop R0. */
188 "BX R14" ); /* Return back to thumb. */
189 }
190
191 #endif /* THUMB_INTERWORK */
192
193 /* The code generated by the GCC compiler uses the stack in different ways at
194 * different optimisation levels. The interrupt flags can therefore not always
195 * be saved to the stack. Instead the critical section nesting level is stored
196 * in a variable, which is then saved as part of the stack context. */
vPortEnterCritical(void)197 void vPortEnterCritical( void )
198 {
199 /* Disable interrupts as per portDISABLE_INTERRUPTS(); */
200 asm volatile (
201 "STMDB SP!, {R0} \n\t" /* Push R0. */
202 "MRS R0, CPSR \n\t" /* Get CPSR. */
203 "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
204 "MSR CPSR, R0 \n\t" /* Write back modified value. */
205 "LDMIA SP!, {R0}" ); /* Pop R0. */
206
207 /* Now that interrupts are disabled, ulCriticalNesting can be accessed
208 * directly. Increment ulCriticalNesting to keep a count of how many times
209 * portENTER_CRITICAL() has been called. */
210 ulCriticalNesting++;
211 }
212
vPortExitCritical(void)213 void vPortExitCritical( void )
214 {
215 if( ulCriticalNesting > portNO_CRITICAL_NESTING )
216 {
217 /* Decrement the nesting count as we are leaving a critical section. */
218 ulCriticalNesting--;
219
220 /* If the nesting level has reached zero then interrupts should be
221 * re-enabled. */
222 if( ulCriticalNesting == portNO_CRITICAL_NESTING )
223 {
224 /* Enable interrupts as per portEXIT_CRITICAL(). */
225 asm volatile (
226 "STMDB SP!, {R0} \n\t" /* Push R0. */
227 "MRS R0, CPSR \n\t" /* Get CPSR. */
228 "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
229 "MSR CPSR, R0 \n\t" /* Write back modified value. */
230 "LDMIA SP!, {R0}" ); /* Pop R0. */
231 }
232 }
233 }
234
