1 /*
2 * FreeRTOS Kernel V11.1.0
3 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy of
8 * this software and associated documentation files (the "Software"), to deal in
9 * the Software without restriction, including without limitation the rights to
10 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
11 * the Software, and to permit persons to whom the Software is furnished to do so,
12 * subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in all
15 * copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
21 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * https://www.FreeRTOS.org
25 * https://github.com/FreeRTOS
26 *
27 */
28
29
30 /*-----------------------------------------------------------
31 * Components that can be compiled to either ARM or THUMB mode are
32 * contained in port.c The ISR routines, which can only be compiled
33 * to ARM mode, are contained in this file.
34 *----------------------------------------------------------*/
35
36 /*
37 * Changes from V3.2.4
38 *
39 + The assembler statements are now included in a single asm block rather
40 + than each line having its own asm block.
41 */
42
43 /* Scheduler includes. */
44 #include "FreeRTOS.h"
45 #include "task.h"
46
47 #include "AT91SAM7X256.h"
48
49 /* Constants required to handle interrupts. */
50 #define portTIMER_MATCH_ISR_BIT ( ( uint8_t ) 0x01 )
51 #define portCLEAR_VIC_INTERRUPT ( ( uint32_t ) 0 )
52
53 /* Constants required to handle critical sections. */
54 #define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
55 volatile uint32_t ulCriticalNesting = 9999UL;
56
57 /*-----------------------------------------------------------*/
58
59 /* ISR to handle manual context switches (from a call to taskYIELD()). */
60 void vPortYieldProcessor( void ) __attribute__( ( interrupt( "SWI" ), naked ) );
61
62 /*
63 * The scheduler can only be started from ARM mode, hence the inclusion of this
64 * function here.
65 */
66 void vPortISRStartFirstTask( void );
67 /*-----------------------------------------------------------*/
68
vPortISRStartFirstTask(void)69 void vPortISRStartFirstTask( void )
70 {
71 /* Simply start the scheduler. This is included here as it can only be
72 * called from ARM mode. */
73 portRESTORE_CONTEXT();
74 }
75 /*-----------------------------------------------------------*/
76
77 /*
78 * Called by portYIELD() or taskYIELD() to manually force a context switch.
79 *
80 * When a context switch is performed from the task level the saved task
81 * context is made to look as if it occurred from within the tick ISR. This
82 * way the same restore context function can be used when restoring the context
83 * saved from the ISR or that saved from a call to vPortYieldProcessor.
84 */
vPortYieldProcessor(void)85 void vPortYieldProcessor( void )
86 {
87 /* Within an IRQ ISR the link register has an offset from the true return
88 * address, but an SWI ISR does not. Add the offset manually so the same
89 * ISR return code can be used in both cases. */
90 __asm volatile ( "ADD LR, LR, #4" );
91
92 /* Perform the context switch. First save the context of the current task. */
93 portSAVE_CONTEXT();
94
95 /* Find the highest priority task that is ready to run. */
96 vTaskSwitchContext();
97
98 /* Restore the context of the new task. */
99 portRESTORE_CONTEXT();
100 }
101 /*-----------------------------------------------------------*/
102
103 /*
104 * The ISR used for the scheduler tick depends on whether the cooperative or
105 * the preemptive scheduler is being used.
106 */
107
108 #if configUSE_PREEMPTION == 0
109
110 /* The cooperative scheduler requires a normal IRQ service routine to
111 * simply increment the system tick. */
112 void vNonPreemptiveTick( void ) __attribute__( ( interrupt( "IRQ" ) ) );
vNonPreemptiveTick(void)113 void vNonPreemptiveTick( void )
114 {
115 uint32_t ulDummy;
116
117 /* Increment the tick count - which may wake some tasks but as the
118 * preemptive scheduler is not being used any woken task is not given
119 * processor time no matter what its priority. */
120 xTaskIncrementTick();
121
122 /* Clear the PIT interrupt. */
123 ulDummy = AT91C_BASE_PITC->PITC_PIVR;
124
125 /* End the interrupt in the AIC. */
126 AT91C_BASE_AIC->AIC_EOICR = ulDummy;
127 }
128
129 #else /* if configUSE_PREEMPTION == 0 */
130
131 /* The preemptive scheduler is defined as "naked" as the full context is
132 * saved on entry as part of the context switch. */
133 void vPreemptiveTick( void ) __attribute__( ( naked ) );
vPreemptiveTick(void)134 void vPreemptiveTick( void )
135 {
136 /* Save the context of the current task. */
137 portSAVE_CONTEXT();
138
139 /* Increment the tick count - this may wake a task. */
140 if( xTaskIncrementTick() != pdFALSE )
141 {
142 /* Find the highest priority task that is ready to run. */
143 vTaskSwitchContext();
144 }
145
146 /* End the interrupt in the AIC. */
147 AT91C_BASE_AIC->AIC_EOICR = AT91C_BASE_PITC->PITC_PIVR;
148
149 portRESTORE_CONTEXT();
150 }
151
152 #endif /* if configUSE_PREEMPTION == 0 */
153 /*-----------------------------------------------------------*/
154
155 /*
156 * The interrupt management utilities can only be called from ARM mode. When
157 * THUMB_INTERWORK is defined the utilities are defined as functions here to
158 * ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then
159 * the utilities are defined as macros in portmacro.h - as per other ports.
160 */
161 void vPortDisableInterruptsFromThumb( void ) __attribute__( ( naked ) );
162 void vPortEnableInterruptsFromThumb( void ) __attribute__( ( naked ) );
163
vPortDisableInterruptsFromThumb(void)164 void vPortDisableInterruptsFromThumb( void )
165 {
166 __asm volatile (
167 "STMDB SP!, {R0} \n\t" /* Push R0. */
168 "MRS R0, CPSR \n\t" /* Get CPSR. */
169 "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
170 "MSR CPSR, R0 \n\t" /* Write back modified value. */
171 "LDMIA SP!, {R0} \n\t" /* Pop R0. */
172 "BX R14" ); /* Return back to thumb. */
173 }
174
vPortEnableInterruptsFromThumb(void)175 void vPortEnableInterruptsFromThumb( void )
176 {
177 __asm volatile (
178 "STMDB SP!, {R0} \n\t" /* Push R0. */
179 "MRS R0, CPSR \n\t" /* Get CPSR. */
180 "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
181 "MSR CPSR, R0 \n\t" /* Write back modified value. */
182 "LDMIA SP!, {R0} \n\t" /* Pop R0. */
183 "BX R14" ); /* Return back to thumb. */
184 }
185
186
187 /* The code generated by the GCC compiler uses the stack in different ways at
188 * different optimisation levels. The interrupt flags can therefore not always
189 * be saved to the stack. Instead the critical section nesting level is stored
190 * in a variable, which is then saved as part of the stack context. */
vPortEnterCritical(void)191 void vPortEnterCritical( void )
192 {
193 /* Disable interrupts as per portDISABLE_INTERRUPTS(); */
194 __asm volatile (
195 "STMDB SP!, {R0} \n\t" /* Push R0. */
196 "MRS R0, CPSR \n\t" /* Get CPSR. */
197 "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
198 "MSR CPSR, R0 \n\t" /* Write back modified value. */
199 "LDMIA SP!, {R0}" ); /* Pop R0. */
200
201 /* Now that interrupts are disabled, ulCriticalNesting can be accessed
202 * directly. Increment ulCriticalNesting to keep a count of how many times
203 * portENTER_CRITICAL() has been called. */
204 ulCriticalNesting++;
205 }
206
vPortExitCritical(void)207 void vPortExitCritical( void )
208 {
209 if( ulCriticalNesting > portNO_CRITICAL_NESTING )
210 {
211 /* Decrement the nesting count as we are leaving a critical section. */
212 ulCriticalNesting--;
213
214 /* If the nesting level has reached zero then interrupts should be
215 * re-enabled. */
216 if( ulCriticalNesting == portNO_CRITICAL_NESTING )
217 {
218 /* Enable interrupts as per portEXIT_CRITICAL(). */
219 __asm volatile (
220 "STMDB SP!, {R0} \n\t" /* Push R0. */
221 "MRS R0, CPSR \n\t" /* Get CPSR. */
222 "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
223 "MSR CPSR, R0 \n\t" /* Write back modified value. */
224 "LDMIA SP!, {R0}" ); /* Pop R0. */
225 }
226 }
227 }
228
