1/*
2 * Copyright (c) 2022 Arm Limited. All rights reserved.
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 *     http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#include "region_defs.h"
18
19LR_CODE BL2_CODE_START {
20    ER_CODE BL2_CODE_START BL2_CODE_SIZE {
21        *.o (RESET +First)
22        * (+RO)
23    }
24
25#ifdef CODE_SHARING
26    /* The code sharing between bootloader and runtime firmware requires to
27     * share the global variables.
28     */
29    TFM_SHARED_SYMBOLS S_DATA_START ALIGN 32 SHARED_SYMBOL_AREA_SIZE {
30       *platform.* (+RW)
31       *(.rodata.memset_func)
32    }
33#endif
34
35    TFM_SHARED_DATA BOOT_TFM_SHARED_DATA_BASE ALIGN 32 EMPTY BOOT_TFM_SHARED_DATA_SIZE {
36    }
37
38/* If the layout is designed so that the shared data is at the start of the bl2
39 * data section, place the data directly afterwards. Else, place it where the
40 * macro is designed to go
41 */
42#if BL2_DATA_START == BOOT_TFM_SHARED_DATA_BASE
43    ER_DATA +0 {
44#else
45    ER_DATA BL2_DATA_START {
46#endif
47        * (+ZI +RW)
48    }
49
50#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
51    /* MSP */
52    ARM_LIB_STACK +0 ALIGN 32 EMPTY BL2_MSP_STACK_SIZE - 0x8 {
53    }
54
55    STACKSEAL +0 EMPTY 0x8 {
56    }
57#else
58    /* MSP */
59    ARM_LIB_STACK +0 ALIGN 32 EMPTY BL2_MSP_STACK_SIZE {
60    }
61
62#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
63
64    ARM_LIB_HEAP +0 ALIGN 8 EMPTY BL2_HEAP_SIZE {
65    }
66
67    /* This empty, zero long execution region is here to mark the limit address
68     * of the last execution region that is allocated in SRAM.
69     */
70    SRAM_WATERMARK +0 EMPTY 0x0 {
71    }
72
73    /* Make sure that the sections allocated in the SRAM does not exceed the
74     * size of the SRAM available.
75     */
76    ScatterAssert(ImageLimit(SRAM_WATERMARK) <= BL2_DATA_START + BL2_DATA_SIZE)
77}
78