1 /* 2 * Copyright (c) 2017-2022 ARM Limited 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef __REGION_DEFS_H__ 18 #define __REGION_DEFS_H__ 19 #include "flash_layout.h" 20 21 #define BL2_HEAP_SIZE 0x0001000 22 #define BL2_MSP_STACK_SIZE 0x0001800 23 24 #ifdef ENABLE_HEAP 25 #define S_HEAP_SIZE (0x0000200) 26 #endif 27 28 #define S_MSP_STACK_SIZE 0x0000800 29 #define S_PSP_STACK_SIZE 0x0000800 30 31 #define NS_HEAP_SIZE 0x0001000 32 #define NS_STACK_SIZE 0x0001000 33 34 35 /* 36 * This size of buffer is big enough to store an attestation 37 * token produced by initial attestation service 38 */ 39 #define PSA_INITIAL_ATTEST_TOKEN_MAX_SIZE 0x250 40 41 #define _SRAM2_TOP (0x40000) /* 256Kbytes */ 42 #define _SRAM1_SIZE_MAX (0x30000) /*!< SRAM1=192k*/ 43 #define _SRAM2_SIZE_MAX (0xfc00) /*!< SRAM2=64k -0x400 */ 44 /* Flash and internal SRAMs base addresses - Non secure aliased */ 45 #define _FLASH_BASE_NS (0x08000000) /*!< FLASH(up to 512 KB) base address */ 46 #define _SRAM1_BASE_NS (0x20000000) /*!< SRAM1(up to 192 KB) base address */ 47 #define _SRAM2_BASE_NS (0x20030000) /*!< SRAM2(64 KB) base address */ 48 49 /* Flash and internal SRAMs base addresses - Secure aliased */ 50 #define _FLASH_BASE_S (0x0C000000) /*!< FLASH(up to 512 KB) base address */ 51 #define _SRAM1_BASE_S (0x30000000) /*!< SRAM1(up to 192 KB) base address */ 52 #define _SRAM2_BASE_S (0x30030000) /*!< SRAM2(64 KB) base address */ 53 54 55 #define TOTAL_ROM_SIZE FLASH_TOTAL_SIZE 56 #define TOTAL_RAM_SIZE (_SRAM1_SIZE_MAX+_SRAM2_SIZE_MAX ) 57 /* 192 + 64 Kbytes - BOOT info */ 58 /* boot info are placed and locked at top of SRAM2 */ 59 #define S_TOTAL_RAM_SIZE (0x1fc00 ) /*! size require for Secure part */ 60 #define NS_TOTAL_RAM_SIZE (TOTAL_RAM_SIZE - S_TOTAL_RAM_SIZE) 61 62 #ifdef BL2 63 #ifndef LINK_TO_SECONDARY_PARTITION 64 #define S_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_0_OFFSET) 65 #define S_IMAGE_SECONDARY_PARTITION_OFFSET (FLASH_AREA_2_OFFSET) 66 #else 67 #define S_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_2_OFFSET) 68 #define S_IMAGE_SECONDARY_PARTITION_OFFSET (FLASH_AREA_0_OFFSET) 69 #endif /* !LINK_TO_SECONDARY_PARTITION */ 70 #else 71 #define S_IMAGE_PRIMARY_PARTITION_OFFSET (0x0) 72 #endif /* BL2 */ 73 74 75 76 /* 77 * Boot partition structure if MCUBoot is used: 78 * 0x0_0000 Bootloader header 79 * 0x0_0400 Image area 80 * 0x7_0000 Trailer 81 */ 82 /* IMAGE_CODE_SIZE is the space available for the software binary image. 83 * It is less than the FLASH_PARTITION_SIZE because we reserve space 84 * for the image header and trailer introduced by the bootloader. 85 */ 86 87 #ifdef BL2 88 #ifndef LINK_TO_SECONDARY_PARTITION 89 #define S_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_0_OFFSET) 90 #define S_IMAGE_SECONDARY_PARTITION_OFFSET (FLASH_AREA_2_OFFSET) 91 #else 92 #define S_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_2_OFFSET) 93 #define S_IMAGE_SECONDARY_PARTITION_OFFSET (FLASH_AREA_0_OFFSET) 94 #endif /* !LINK_TO_SECONDARY_PARTITION */ 95 #else 96 #define S_IMAGE_PRIMARY_PARTITION_OFFSET (0x0) 97 #endif /* BL2 */ 98 #ifndef LINK_TO_SECONDARY_PARTITION 99 #define NS_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_0_OFFSET + FLASH_S_PARTITION_SIZE) 100 #else 101 #define NS_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_2_OFFSET + FLASH_S_PARTITION_SIZE) 102 #endif /* !LINK_TO_SECONDARY_PARTITION */ 103 104 #define IMAGE_S_CODE_SIZE \ 105 (FLASH_S_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE) 106 #define IMAGE_NS_CODE_SIZE \ 107 (FLASH_NS_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE) 108 109 /* Use SRAM1 memory to store Code data */ 110 #define S_ROM_ALIAS_BASE (_FLASH_BASE_S) 111 #define NS_ROM_ALIAS_BASE (_FLASH_BASE_NS) 112 113 114 #define S_RAM_ALIAS_BASE (_SRAM1_BASE_S) 115 #define NS_RAM_ALIAS_BASE (_SRAM1_BASE_NS) 116 117 /* Alias definitions for secure and non-secure areas*/ 118 #define S_ROM_ALIAS(x) (S_ROM_ALIAS_BASE + (x)) 119 #define NS_ROM_ALIAS(x) (NS_ROM_ALIAS_BASE + (x)) 120 121 #define S_RAM_ALIAS(x) (S_RAM_ALIAS_BASE + (x)) 122 #define NS_RAM_ALIAS(x) (NS_RAM_ALIAS_BASE + (x)) 123 124 125 #define S_IMAGE_PRIMARY_AREA_OFFSET (S_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE) 126 #define S_CODE_START (S_ROM_ALIAS(S_IMAGE_PRIMARY_AREA_OFFSET)) 127 128 #define S_CODE_SIZE (IMAGE_S_CODE_SIZE) 129 #define S_CODE_LIMIT ((S_CODE_START + S_CODE_SIZE) -1) 130 131 #define S_DATA_START (S_RAM_ALIAS(NS_TOTAL_RAM_SIZE)) 132 #define S_DATA_SIZE (S_TOTAL_RAM_SIZE) 133 #define S_DATA_LIMIT (S_DATA_START + S_DATA_SIZE - 1) 134 135 /* Size of vector table: 124 interrupt handlers + 4 bytes MPS initial value */ 136 #define S_CODE_VECTOR_TABLE_SIZE (0x1F4) 137 138 /* Non-secure regions */ 139 140 /* Secure regions , the end of secure regions must be aligned on page size for dual bank 0x800*/ 141 /* Offset and size definition in flash area, used by assemble.py 142 * 0x11400+0x33c00= 13000+34000 = 45000*/ 143 144 #define NS_IMAGE_PRIMARY_AREA_OFFSET (NS_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE) 145 #define NS_CODE_START (NS_ROM_ALIAS(NS_IMAGE_PRIMARY_AREA_OFFSET)) 146 #define NS_CODE_SIZE (IMAGE_NS_CODE_SIZE) 147 #define NS_CODE_LIMIT (NS_CODE_START + NS_CODE_SIZE - 1) 148 #define NS_DATA_START (NS_RAM_ALIAS(0)) 149 #define NS_NO_INIT_DATA_SIZE (0x100) 150 #define NS_DATA_SIZE (NS_TOTAL_RAM_SIZE) 151 #define NS_DATA_LIMIT (NS_DATA_START + NS_DATA_SIZE - 1) 152 153 /* NS partition information is used for GTZC and SAU configuration */ 154 #define NS_PARTITION_START (NS_CODE_START) 155 #define NS_PARTITION_SIZE (NS_CODE_SIZE) 156 157 /* Secondary partition for new images/ in case of firmware upgrade */ 158 #define SECONDARY_PARTITION_START (NS_ROM_ALIAS(S_IMAGE_SECONDARY_PARTITION_OFFSET)) 159 #define SECONDARY_PARTITION_SIZE (FLASH_AREA_2_SIZE) 160 161 #ifdef BL2 162 /* Personalized region */ 163 #define PERSO_START (S_ROM_ALIAS(FLASH_AREA_PERSO_OFFSET)) 164 #define PERSO_SIZE (FLASH_AREA_PERSO_SIZE) 165 #define PERSO_LIMIT (PERSO_START + PERSO_SIZE - 1) 166 167 /* Bootloader region protected by hdp */ 168 #define BL2_CODE_START (S_ROM_ALIAS(FLASH_AREA_BL2_OFFSET)) 169 #define BL2_CODE_SIZE (FLASH_AREA_BL2_SIZE) 170 #define BL2_CODE_LIMIT (BL2_CODE_START + BL2_CODE_SIZE - 1) 171 172 /* Bootloader region not protected by hdp */ 173 #define BL2_NOHDP_CODE_START (S_ROM_ALIAS(FLASH_AREA_BL2_NOHDP_OFFSET)) 174 #define BL2_NOHDP_CODE_SIZE (FLASH_AREA_BL2_NOHDP_SIZE) 175 #define BL2_NOHDP_CODE_LIMIT (BL2_NOHDP_CODE_START + BL2_NOHDP_CODE_SIZE - 1) 176 177 /* keep 256 bytes unsed to place while(1) for non secure to enable */ 178 /* regression from local tool with non secure attachement 179 * This avoid blocking board in case of hardening error */ 180 #define BL2_DATA_START (S_RAM_ALIAS(_SRAM1_SIZE_MAX)) 181 #define BL2_DATA_SIZE (BOOT_TFM_SHARED_DATA_BASE - BL2_DATA_START) 182 #define BL2_DATA_LIMIT (BL2_DATA_START + BL2_DATA_SIZE - 1) 183 #endif /* BL2 */ 184 185 #endif /* __REGION_DEFS_H__ */ 186
