1/*
2 * Copyright (c) 2017-2022 Arm Limited. All rights reserved.
3 * Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company)
4 * or an affiliate of Cypress Semiconductor Corporation. All rights reserved.
5 *
6 * Licensed under the Apache License, Version 2.0 (the "License");
7 * you may not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 *     http://www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an "AS IS" BASIS,
14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 */
18
19/*********** WARNING: This is an auto-generated file. Do not edit! ***********/
20
21#include "region_defs.h"
22
23LR_CODE S_CODE_START {
24
25    /****  This initial section contains common code for secure binary */
26    ER_TFM_CODE S_CODE_START S_CODE_SIZE {
27        *.o (RESET +First)
28        * (+RO)
29    }
30
31    /**** Unprivileged Secure code start here */
32    TFM_UNPRIV_CODE +0 ALIGN 32 {
33        *(SFN)
34        *armlib*
35        *libtfm_sprt.a (+RO)
36    }
37
38    /**** PSA RoT RO part (CODE + RODATA) start here */
39    /*
40     * This empty, zero long execution region is here to mark the start address
41     * of PSA RoT code.
42     */
43    TFM_PSA_CODE_START +0 ALIGN 32 EMPTY 0x0 {
44    }
45
46#ifdef TFM_PARTITION_INTERNAL_TRUSTED_STORAGE
47    TFM_SP_ITS_LINKER +0 ALIGN 32 {
48        *tfm_internal_trusted_storage* (+RO)
49        *(TFM_SP_ITS_ATTR_FN)
50    }
51#endif /* TFM_PARTITION_INTERNAL_TRUSTED_STORAGE */
52
53#ifdef TFM_PARTITION_CRYPTO
54    TFM_SP_CRYPTO_LINKER +0 ALIGN 32 {
55        *tfm_crypto* (+RO)
56        *(TFM_SP_CRYPTO_ATTR_FN)
57    }
58#endif /* TFM_PARTITION_CRYPTO */
59
60#ifdef TFM_PARTITION_PLATFORM
61    TFM_SP_PLATFORM_LINKER +0 ALIGN 32 {
62        *tfm_platform* (+RO)
63        *(TFM_SP_PLATFORM_ATTR_FN)
64    }
65#endif /* TFM_PARTITION_PLATFORM */
66
67#ifdef TFM_PARTITION_INITIAL_ATTESTATION
68    TFM_SP_INITIAL_ATTESTATION_LINKER +0 ALIGN 32 {
69        *tfm_attest* (+RO)
70        *(TFM_SP_INITIAL_ATTESTATION_ATTR_FN)
71    }
72#endif /* TFM_PARTITION_INITIAL_ATTESTATION */
73
74#ifdef TFM_PARTITION_TEST_SECURE_SERVICES
75    TFM_SP_SECURE_TEST_PARTITION_LINKER +0 ALIGN 32 {
76        *tfm_secure_client_service.* (+RO)
77        *test_framework* (+RO)
78        *uart_stdout.* (+RO)
79        *Driver_USART.* (+RO)
80        *arm_uart_drv.* (+RO)
81        *uart_pl011_drv.* (+RO)
82        *uart_cmsdk_drv* (+RO)
83        *secure_suites.* (+RO)
84        *attestation_s_interface_testsuite.* (+RO)
85        *(TFM_SP_SECURE_TEST_PARTITION_ATTR_FN)
86    }
87#endif /* TFM_PARTITION_TEST_SECURE_SERVICES */
88
89#ifdef TFM_PARTITION_TEST_CORE_IPC
90    TFM_SP_IPC_SERVICE_TEST_LINKER +0 ALIGN 32 {
91        *ipc_service_test.* (+RO)
92        *(TFM_SP_IPC_SERVICE_TEST_ATTR_FN)
93    }
94#endif /* TFM_PARTITION_TEST_CORE_IPC */
95
96#ifdef TFM_PARTITION_TEST_PS
97    TFM_SP_PS_TEST_LINKER +0 ALIGN 32 {
98        *tfm_ps_test_service.* (+RO)
99        *(TFM_SP_PS_TEST_ATTR_FN)
100    }
101#endif /* TFM_PARTITION_TEST_PS */
102
103    /*
104     * This empty, zero long execution region is here to mark the end address
105     * of PSA RoT code.
106     */
107    TFM_PSA_CODE_END +0 ALIGN 32 EMPTY 0x0 {
108    }
109
110    /**** APPLICATION RoT RO part (CODE + RODATA) start here */
111    /*
112     * This empty, zero long execution region is here to mark the start address
113     * of APP RoT code.
114     */
115    TFM_APP_CODE_START +0 ALIGN 32 EMPTY 0x0 {
116    }
117
118#ifdef TFM_PARTITION_PROTECTED_STORAGE
119    TFM_SP_PS_LINKER +0 ALIGN 32 {
120        *tfm_storage* (+RO)
121        *test_ps_nv_counters.* (+RO)
122        *(TFM_SP_PS_ATTR_FN)
123    }
124#endif /* TFM_PARTITION_PROTECTED_STORAGE */
125
126#ifdef TFM_PARTITION_TEST_CORE_IPC
127    TFM_SP_IPC_CLIENT_TEST_LINKER +0 ALIGN 32 {
128        *ipc_client_test.* (+RO)
129        *(TFM_SP_IPC_CLIENT_TEST_ATTR_FN)
130    }
131#endif /* TFM_PARTITION_TEST_CORE_IPC */
132
133#ifdef TEST_NS_SLIH_IRQ
134    TFM_SLIH_TEST_LINKER +0 ALIGN 32 {
135        *tfm_Slih_test_service.* (+RO)
136        *timer_cmsdk* (+RO)
137        *(TFM_SLIH_TEST_ATTR_FN)
138    }
139#endif /* TEST_NS_SLIH_IRQ */
140
141#ifdef TFM_PARTITION_TEST_SECURE_SERVICES
142    TFM_SP_SECURE_CLIENT_2_LINKER +0 ALIGN 32 {
143        *tfm_secure_client_2.* (+RO)
144        *(TFM_SP_SECURE_CLIENT_2_ATTR_FN)
145    }
146#endif /* TFM_PARTITION_TEST_SECURE_SERVICES */
147
148#ifdef TFM_MULTI_CORE_TEST
149    TFM_SP_MULTI_CORE_TEST_LINKER +0 ALIGN 32 {
150        *multi_core_test.* (+RO)
151        *(TFM_SP_MULTI_CORE_TEST_ATTR_FN)
152    }
153#endif /* TFM_MULTI_CORE_TEST */
154
155    /*
156     * This empty, zero long execution region is here to mark the end address
157     * of APP RoT code.
158     */
159    TFM_APP_CODE_END +0 ALIGN 32 EMPTY 0x0 {
160    }
161
162#if defined(S_CODE_SRAM_ALIAS_BASE)
163    /* eFlash driver code that gets copied from Flash to SRAM */
164    ER_CODE_SRAM S_CODE_SRAM_ALIAS_BASE ALIGN 4 {
165        Driver_GFC100_EFlash.o (+RO)
166        gfc100_eflash_drv.o (+RO)
167        musca_b1_eflash_drv.o (+RO)
168    }
169#endif
170
171    /**** Base address of secure data area */
172    TFM_SECURE_DATA_START S_DATA_START {
173    }
174
175    /* Shared area between BL2 and runtime to exchange data */
176    TFM_SHARED_DATA +0 ALIGN 32 OVERLAY EMPTY BOOT_TFM_SHARED_DATA_SIZE {
177    }
178
179    /* MSP */
180    ARM_LIB_STACK +0 ALIGN 32 OVERLAY EMPTY S_MSP_STACK_SIZE - 0x8 {
181    }
182
183    STACKSEAL +0 EMPTY 0x8 {
184    }
185
186#if defined(CONFIG_TFM_PARTITION_META)
187    TFM_SP_META_PTR +0 ALIGN 32 {
188        *(.bss.SP_META_PTR_SPRTL_INST)
189    }
190#endif
191
192    /**** APP RoT DATA start here */
193    /*
194     * This empty, zero long execution region is here to mark the start address
195     * of APP RoT RW and Stack.
196     */
197    TFM_APP_RW_STACK_START +0 ALIGN 32 EMPTY 0x0 {
198    }
199
200#ifdef TFM_PARTITION_PROTECTED_STORAGE
201    TFM_SP_PS_LINKER_DATA +0 ALIGN 32 {
202        *tfm_storage* (+RW +ZI)
203        *test_ps_nv_counters.* (+RW +ZI)
204        *(TFM_SP_PS_ATTR_RW)
205        *(TFM_SP_PS_ATTR_ZI)
206    }
207
208    TFM_SP_PS_LINKER_STACK +0 ALIGN 128 EMPTY 0x800 {
209    }
210#endif /* TFM_PARTITION_PROTECTED_STORAGE */
211
212#ifdef TFM_PARTITION_TEST_CORE_IPC
213    TFM_SP_IPC_CLIENT_TEST_LINKER_DATA +0 ALIGN 32 {
214        *ipc_client_test.* (+RW +ZI)
215        *(TFM_SP_IPC_CLIENT_TEST_ATTR_RW)
216        *(TFM_SP_IPC_CLIENT_TEST_ATTR_ZI)
217    }
218
219    TFM_SP_IPC_CLIENT_TEST_LINKER_STACK +0 ALIGN 128 EMPTY 0x0300 {
220    }
221#endif /* TFM_PARTITION_TEST_CORE_IPC */
222
223#ifdef TEST_NS_SLIH_IRQ
224    TFM_SP_SLIH_TEST_LINKER_DATA +0 ALIGN 32 {
225        *tfm_slih_test_service.* (+RW +ZI)
226        *timer_cmsdk* (+RW +ZI)
227        *(TFM_SP_SLIH_TEST_ATTR_RW)
228        *(TFM_SP_SLIH_TEST_ATTR_ZI)
229    }
230
231    TFM_SP_SLIH_TEST_LINKER_STACK +0 ALIGN 128 EMPTY 0x0400 {
232    }
233#endif /* TEST_NS_SLIH_IRQ */
234
235#ifdef TFM_PARTITION_TEST_SECURE_SERVICES
236    TFM_SP_SECURE_CLIENT_2_LINKER_DATA +0 ALIGN 32 {
237        *tfm_secure_client_2.* (+RW +ZI)
238        *(TFM_SP_SECURE_CLIENT_2_ATTR_RW)
239        *(TFM_SP_SECURE_CLIENT_2_ATTR_ZI)
240    }
241
242    TFM_SP_SECURE_CLIENT_2_LINKER_STACK +0 ALIGN 128 EMPTY 0x300 {
243    }
244#endif /* TFM_PARTITION_TEST_SECURE_SERVICES */
245
246#ifdef TFM_MULTI_CORE_TEST
247    TFM_SP_MULTI_CORE_TEST_LINKER_DATA +0 ALIGN 32 {
248        *multi_core_test.* (+RW +ZI)
249        *(TFM_SP_MULTI_CORE_TEST_ATTR_RW)
250        *(TFM_SP_MULTI_CORE_TEST_ATTR_ZI)
251    }
252
253    TFM_SP_MULTI_CORE_TEST_LINKER_STACK +0 ALIGN 128 EMPTY 0x0100 {
254    }
255#endif /* TFM_MULTI_CORE_TEST */
256
257    /*
258     * This empty, zero long execution region is here to mark the end address
259     * of APP RoT RW and Stack.
260     */
261    TFM_APP_RW_STACK_END +0 ALIGN 32 EMPTY 0x0 {
262    }
263
264    ARM_LIB_HEAP +0 ALIGN 8 EMPTY S_HEAP_SIZE {
265    }
266
267    ER_TFM_DATA +0 {
268        * (+RW +ZI)
269    }
270
271    /**** PSA RoT DATA start here */
272    /*
273     * This empty, zero long execution region is here to mark the start address
274     * of PSA RoT RW and Stack.
275     */
276    TFM_PSA_RW_STACK_START +0 ALIGN 32 EMPTY 0x0 {
277    }
278
279#ifdef TFM_PARTITION_INTERNAL_TRUSTED_STORAGE
280    TFM_SP_ITS_LINKER_DATA +0 ALIGN 32 {
281        *tfm_internal_trusted_storage* (+RW +ZI)
282        *(TFM_SP_ITS_ATTR_RW)
283        *(TFM_SP_ITS_ATTR_ZI)
284    }
285
286    TFM_SP_ITS_LINKER_STACK +0 ALIGN 128 EMPTY 0x680 {
287    }
288#endif /* TFM_PARTITION_INTERNAL_TRUSTED_STORAGE */
289
290#ifdef TFM_PARTITION_CRYPTO
291    TFM_SP_CRYPTO_LINKER_DATA +0 ALIGN 32 {
292        *tfm_crypto* (+RW +ZI)
293        *(TFM_SP_CRYPTO_ATTR_RW)
294        *(TFM_SP_CRYPTO_ATTR_ZI)
295    }
296
297    TFM_SP_CRYPTO_LINKER_STACK +0 ALIGN 128 EMPTY 0x2000 {
298    }
299#endif /* TFM_PARTITION_CRYPTO */
300
301#ifdef TFM_PARTITION_PLATFORM
302    TFM_SP_PLATFORM_LINKER_DATA +0 ALIGN 32 {
303        *tfm_platform* (+RW +ZI)
304        *(TFM_SP_PLATFORM_ATTR_RW)
305        *(TFM_SP_PLATFORM_ATTR_ZI)
306    }
307
308    TFM_SP_PLATFORM_LINKER_STACK +0 ALIGN 128 EMPTY 0x0400 {
309    }
310#endif /* TFM_PARTITION_PLATFORM */
311
312#ifdef TFM_PARTITION_INITIAL_ATTESTATION
313    TFM_SP_INITIAL_ATTESTATION_LINKER_DATA +0 ALIGN 32 {
314        *tfm_attest* (+RW +ZI)
315        *(TFM_SP_INITIAL_ATTESTATION_ATTR_RW)
316        *(TFM_SP_INITIAL_ATTESTATION_ATTR_ZI)
317    }
318
319    TFM_SP_INITIAL_ATTESTATION_LINKER_STACK +0 ALIGN 128 EMPTY 0x0A80 {
320    }
321#endif /* TFM_PARTITION_INITIAL_ATTESTATION */
322
323#ifdef TFM_PARTITION_TEST_SECURE_SERVICES
324    TFM_SP_SECURE_TEST_PARTITION_LINKER_DATA +0 ALIGN 32 {
325        *tfm_secure_client_service.* (+RW +ZI)
326        *test_framework* (+RW +ZI)
327        *uart_stdout.* (+RW +ZI)
328        *Driver_USART.* (+RW +ZI)
329        *arm_uart_drv.* (+RW +ZI)
330        *uart_pl011_drv.* (+RW +ZI)
331        *uart_cmsdk_drv* (+RW +ZI)
332        *secure_suites.* (+RW +ZI)
333        *attestation_s_interface_testsuite.* (+RW +ZI)
334        *(TFM_SP_SECURE_TEST_PARTITION_ATTR_RW)
335        *(TFM_SP_SECURE_TEST_PARTITION_ATTR_ZI)
336    }
337
338    TFM_SP_SECURE_TEST_PARTITION_LINKER_STACK +0 ALIGN 128 EMPTY 0x0D00 {
339    }
340#endif /* TFM_PARTITION_TEST_SECURE_SERVICES */
341
342#ifdef TFM_PARTITION_TEST_CORE_IPC
343    TFM_SP_IPC_SERVICE_TEST_LINKER_DATA +0 ALIGN 32 {
344        *ipc_service_test.* (+RW +ZI)
345        *(TFM_SP_IPC_SERVICE_TEST_ATTR_RW)
346        *(TFM_SP_IPC_SERVICE_TEST_ATTR_ZI)
347    }
348
349    TFM_SP_IPC_SERVICE_TEST_LINKER_STACK +0 ALIGN 128 EMPTY 0x0220 {
350    }
351#endif /* TFM_PARTITION_TEST_CORE_IPC */
352
353#ifdef TFM_PARTITION_TEST_PS
354    TFM_SP_PS_TEST_LINKER_DATA +0 ALIGN 32 {
355        *tfm_ps_test_service.* (+RW +ZI)
356        *(TFM_SP_PS_TEST_ATTR_RW)
357        *(TFM_SP_PS_TEST_ATTR_ZI)
358    }
359
360    TFM_SP_PS_TEST_LINKER_STACK +0 ALIGN 128 EMPTY 0x500 {
361    }
362#endif /* TFM_PARTITION_TEST_PS */
363
364    /*
365     * This empty, zero long execution region is here to mark the end address
366     * of PSA RoT RW and Stack.
367     */
368    TFM_PSA_RW_STACK_END +0 ALIGN 32 EMPTY 0x0 {
369    }
370
371#if defined (S_RAM_CODE_START)
372    /* Executable code allocated in RAM */
373    TFM_RAM_CODE S_RAM_CODE_START {
374        * (.ramfunc)
375    }
376#endif
377
378    /* This empty, zero long execution region is here to mark the limit address
379     * of the last execution region that is allocated in SRAM.
380     */
381    SRAM_WATERMARK +0 EMPTY 0x0 {
382    }
383
384    /* Make sure that the sections allocated in the SRAM does not exceed the
385     * size of the SRAM available.
386     */
387    ScatterAssert(ImageLimit(SRAM_WATERMARK) <= S_DATA_START + S_DATA_SIZE)
388}
389
390LR_VENEER CMSE_VENEER_REGION_START {
391    /*
392     * Place the CMSE Veneers (containing the SG instruction) in a separate
393     * 32 bytes aligned region so that the SAU can be programmed to
394     * just set this region as Non-Secure Callable.
395     */
396    CMSE_VENEER CMSE_VENEER_REGION_START CMSE_VENEER_REGION_SIZE {
397        *(Veneer$$CMSE)
398    }
399}
400
401LR_NS_PARTITION NS_PARTITION_START {
402    /* Reserved place for NS application.
403     * No code will be placed here, just address of this region is used in the
404     * secure code to configure certain HW components. This generates an empty
405     * execution region description warning during linking.
406     */
407    ER_NS_PARTITION NS_PARTITION_START UNINIT NS_PARTITION_SIZE {
408    }
409}
410
411#ifdef BL2
412LR_SECONDARY_PARTITION SECONDARY_PARTITION_START {
413    /* Reserved place for new image in case of firmware upgrade.
414     * No code will be placed here, just address of this region is used in the
415     * secure code to configure certain HW components. This generates an empty
416     * execution region description warning during linking.
417     */
418    ER_SECONDARY_PARTITION SECONDARY_PARTITION_START \
419        UNINIT SECONDARY_PARTITION_SIZE {
420    }
421}
422#endif /* BL2 */
423