/*
 * Copyright (c) 2017-2022 Arm Limited. All rights reserved.
 * Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company)
 * or an affiliate of Cypress Semiconductor Corporation. All rights reserved.
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */

/*********** WARNING: This is an auto-generated file. Do not edit! ***********/

#include "region_defs.h"

LR_CODE S_CODE_START {

    /****  This initial section contains common code for secure binary */
    ER_TFM_CODE S_CODE_START S_CODE_SIZE {
        *.o (RESET +First)
        * (+RO)
    }

    /**** Unprivileged Secure code start here */
    TFM_UNPRIV_CODE +0 ALIGN 32 {
        *(SFN)
        *armlib*
        *libtfm_sprt.a (+RO)
    }

    /**** PSA RoT RO part (CODE + RODATA) start here */
    /*
     * This empty, zero long execution region is here to mark the start address
     * of PSA RoT code.
     */
    TFM_PSA_CODE_START +0 ALIGN 32 EMPTY 0x0 {
    }

#ifdef TFM_PARTITION_INTERNAL_TRUSTED_STORAGE
    TFM_SP_ITS_LINKER +0 ALIGN 32 {
        *tfm_internal_trusted_storage* (+RO)
        *(TFM_SP_ITS_ATTR_FN)
    }
#endif /* TFM_PARTITION_INTERNAL_TRUSTED_STORAGE */

#ifdef TFM_PARTITION_CRYPTO
    TFM_SP_CRYPTO_LINKER +0 ALIGN 32 {
        *tfm_crypto* (+RO)
        *(TFM_SP_CRYPTO_ATTR_FN)
    }
#endif /* TFM_PARTITION_CRYPTO */

#ifdef TFM_PARTITION_PLATFORM
    TFM_SP_PLATFORM_LINKER +0 ALIGN 32 {
        *tfm_platform* (+RO)
        *(TFM_SP_PLATFORM_ATTR_FN)
    }
#endif /* TFM_PARTITION_PLATFORM */

#ifdef TFM_PARTITION_INITIAL_ATTESTATION
    TFM_SP_INITIAL_ATTESTATION_LINKER +0 ALIGN 32 {
        *tfm_attest* (+RO)
        *(TFM_SP_INITIAL_ATTESTATION_ATTR_FN)
    }
#endif /* TFM_PARTITION_INITIAL_ATTESTATION */

#ifdef TFM_PARTITION_TEST_SECURE_SERVICES
    TFM_SP_SECURE_TEST_PARTITION_LINKER +0 ALIGN 32 {
        *tfm_secure_client_service.* (+RO)
        *test_framework* (+RO)
        *uart_stdout.* (+RO)
        *Driver_USART.* (+RO)
        *arm_uart_drv.* (+RO)
        *uart_pl011_drv.* (+RO)
        *uart_cmsdk_drv* (+RO)
        *secure_suites.* (+RO)
        *attestation_s_interface_testsuite.* (+RO)
        *(TFM_SP_SECURE_TEST_PARTITION_ATTR_FN)
    }
#endif /* TFM_PARTITION_TEST_SECURE_SERVICES */

#ifdef TFM_PARTITION_TEST_CORE_IPC
    TFM_SP_IPC_SERVICE_TEST_LINKER +0 ALIGN 32 {
        *ipc_service_test.* (+RO)
        *(TFM_SP_IPC_SERVICE_TEST_ATTR_FN)
    }
#endif /* TFM_PARTITION_TEST_CORE_IPC */

#ifdef TFM_PARTITION_TEST_PS
    TFM_SP_PS_TEST_LINKER +0 ALIGN 32 {
        *tfm_ps_test_service.* (+RO)
        *(TFM_SP_PS_TEST_ATTR_FN)
    }
#endif /* TFM_PARTITION_TEST_PS */

    /*
     * This empty, zero long execution region is here to mark the end address
     * of PSA RoT code.
     */
    TFM_PSA_CODE_END +0 ALIGN 32 EMPTY 0x0 {
    }

    /**** APPLICATION RoT RO part (CODE + RODATA) start here */
    /*
     * This empty, zero long execution region is here to mark the start address
     * of APP RoT code.
     */
    TFM_APP_CODE_START +0 ALIGN 32 EMPTY 0x0 {
    }

#ifdef TFM_PARTITION_PROTECTED_STORAGE
    TFM_SP_PS_LINKER +0 ALIGN 32 {
        *tfm_storage* (+RO)
        *test_ps_nv_counters.* (+RO)
        *(TFM_SP_PS_ATTR_FN)
    }
#endif /* TFM_PARTITION_PROTECTED_STORAGE */

#ifdef TFM_PARTITION_TEST_CORE_IPC
    TFM_SP_IPC_CLIENT_TEST_LINKER +0 ALIGN 32 {
        *ipc_client_test.* (+RO)
        *(TFM_SP_IPC_CLIENT_TEST_ATTR_FN)
    }
#endif /* TFM_PARTITION_TEST_CORE_IPC */

#ifdef TEST_NS_SLIH_IRQ
    TFM_SLIH_TEST_LINKER +0 ALIGN 32 {
        *tfm_Slih_test_service.* (+RO)
        *timer_cmsdk* (+RO)
        *(TFM_SLIH_TEST_ATTR_FN)
    }
#endif /* TEST_NS_SLIH_IRQ */

#ifdef TFM_PARTITION_TEST_SECURE_SERVICES
    TFM_SP_SECURE_CLIENT_2_LINKER +0 ALIGN 32 {
        *tfm_secure_client_2.* (+RO)
        *(TFM_SP_SECURE_CLIENT_2_ATTR_FN)
    }
#endif /* TFM_PARTITION_TEST_SECURE_SERVICES */

#ifdef TFM_MULTI_CORE_TEST
    TFM_SP_MULTI_CORE_TEST_LINKER +0 ALIGN 32 {
        *multi_core_test.* (+RO)
        *(TFM_SP_MULTI_CORE_TEST_ATTR_FN)
    }
#endif /* TFM_MULTI_CORE_TEST */

    /*
     * This empty, zero long execution region is here to mark the end address
     * of APP RoT code.
     */
    TFM_APP_CODE_END +0 ALIGN 32 EMPTY 0x0 {
    }

#if defined(S_CODE_SRAM_ALIAS_BASE)
    /* eFlash driver code that gets copied from Flash to SRAM */
    ER_CODE_SRAM S_CODE_SRAM_ALIAS_BASE ALIGN 4 {
        Driver_GFC100_EFlash.o (+RO)
        gfc100_eflash_drv.o (+RO)
        musca_b1_eflash_drv.o (+RO)
    }
#endif

    /**** Base address of secure data area */
    TFM_SECURE_DATA_START S_DATA_START {
    }

    /* Shared area between BL2 and runtime to exchange data */
    TFM_SHARED_DATA +0 ALIGN 32 OVERLAY EMPTY BOOT_TFM_SHARED_DATA_SIZE {
    }

    /* MSP */
    ARM_LIB_STACK +0 ALIGN 32 OVERLAY EMPTY S_MSP_STACK_SIZE - 0x8 {
    }

    STACKSEAL +0 EMPTY 0x8 {
    }

#if defined(CONFIG_TFM_PARTITION_META)
    TFM_SP_META_PTR +0 ALIGN 32 {
        *(.bss.SP_META_PTR_SPRTL_INST)
    }
#endif

    /**** APP RoT DATA start here */
    /*
     * This empty, zero long execution region is here to mark the start address
     * of APP RoT RW and Stack.
     */
    TFM_APP_RW_STACK_START +0 ALIGN 32 EMPTY 0x0 {
    }

#ifdef TFM_PARTITION_PROTECTED_STORAGE
    TFM_SP_PS_LINKER_DATA +0 ALIGN 32 {
        *tfm_storage* (+RW +ZI)
        *test_ps_nv_counters.* (+RW +ZI)
        *(TFM_SP_PS_ATTR_RW)
        *(TFM_SP_PS_ATTR_ZI)
    }

    TFM_SP_PS_LINKER_STACK +0 ALIGN 128 EMPTY 0x800 {
    }
#endif /* TFM_PARTITION_PROTECTED_STORAGE */

#ifdef TFM_PARTITION_TEST_CORE_IPC
    TFM_SP_IPC_CLIENT_TEST_LINKER_DATA +0 ALIGN 32 {
        *ipc_client_test.* (+RW +ZI)
        *(TFM_SP_IPC_CLIENT_TEST_ATTR_RW)
        *(TFM_SP_IPC_CLIENT_TEST_ATTR_ZI)
    }

    TFM_SP_IPC_CLIENT_TEST_LINKER_STACK +0 ALIGN 128 EMPTY 0x0300 {
    }
#endif /* TFM_PARTITION_TEST_CORE_IPC */

#ifdef TEST_NS_SLIH_IRQ
    TFM_SP_SLIH_TEST_LINKER_DATA +0 ALIGN 32 {
        *tfm_slih_test_service.* (+RW +ZI)
        *timer_cmsdk* (+RW +ZI)
        *(TFM_SP_SLIH_TEST_ATTR_RW)
        *(TFM_SP_SLIH_TEST_ATTR_ZI)
    }

    TFM_SP_SLIH_TEST_LINKER_STACK +0 ALIGN 128 EMPTY 0x0400 {
    }
#endif /* TEST_NS_SLIH_IRQ */

#ifdef TFM_PARTITION_TEST_SECURE_SERVICES
    TFM_SP_SECURE_CLIENT_2_LINKER_DATA +0 ALIGN 32 {
        *tfm_secure_client_2.* (+RW +ZI)
        *(TFM_SP_SECURE_CLIENT_2_ATTR_RW)
        *(TFM_SP_SECURE_CLIENT_2_ATTR_ZI)
    }

    TFM_SP_SECURE_CLIENT_2_LINKER_STACK +0 ALIGN 128 EMPTY 0x300 {
    }
#endif /* TFM_PARTITION_TEST_SECURE_SERVICES */

#ifdef TFM_MULTI_CORE_TEST
    TFM_SP_MULTI_CORE_TEST_LINKER_DATA +0 ALIGN 32 {
        *multi_core_test.* (+RW +ZI)
        *(TFM_SP_MULTI_CORE_TEST_ATTR_RW)
        *(TFM_SP_MULTI_CORE_TEST_ATTR_ZI)
    }

    TFM_SP_MULTI_CORE_TEST_LINKER_STACK +0 ALIGN 128 EMPTY 0x0100 {
    }
#endif /* TFM_MULTI_CORE_TEST */

    /*
     * This empty, zero long execution region is here to mark the end address
     * of APP RoT RW and Stack.
     */
    TFM_APP_RW_STACK_END +0 ALIGN 32 EMPTY 0x0 {
    }

    ARM_LIB_HEAP +0 ALIGN 8 EMPTY S_HEAP_SIZE {
    }

    ER_TFM_DATA +0 {
        * (+RW +ZI)
    }

    /**** PSA RoT DATA start here */
    /*
     * This empty, zero long execution region is here to mark the start address
     * of PSA RoT RW and Stack.
     */
    TFM_PSA_RW_STACK_START +0 ALIGN 32 EMPTY 0x0 {
    }

#ifdef TFM_PARTITION_INTERNAL_TRUSTED_STORAGE
    TFM_SP_ITS_LINKER_DATA +0 ALIGN 32 {
        *tfm_internal_trusted_storage* (+RW +ZI)
        *(TFM_SP_ITS_ATTR_RW)
        *(TFM_SP_ITS_ATTR_ZI)
    }

    TFM_SP_ITS_LINKER_STACK +0 ALIGN 128 EMPTY 0x680 {
    }
#endif /* TFM_PARTITION_INTERNAL_TRUSTED_STORAGE */

#ifdef TFM_PARTITION_CRYPTO
    TFM_SP_CRYPTO_LINKER_DATA +0 ALIGN 32 {
        *tfm_crypto* (+RW +ZI)
        *(TFM_SP_CRYPTO_ATTR_RW)
        *(TFM_SP_CRYPTO_ATTR_ZI)
    }

    TFM_SP_CRYPTO_LINKER_STACK +0 ALIGN 128 EMPTY 0x2000 {
    }
#endif /* TFM_PARTITION_CRYPTO */

#ifdef TFM_PARTITION_PLATFORM
    TFM_SP_PLATFORM_LINKER_DATA +0 ALIGN 32 {
        *tfm_platform* (+RW +ZI)
        *(TFM_SP_PLATFORM_ATTR_RW)
        *(TFM_SP_PLATFORM_ATTR_ZI)
    }

    TFM_SP_PLATFORM_LINKER_STACK +0 ALIGN 128 EMPTY 0x0400 {
    }
#endif /* TFM_PARTITION_PLATFORM */

#ifdef TFM_PARTITION_INITIAL_ATTESTATION
    TFM_SP_INITIAL_ATTESTATION_LINKER_DATA +0 ALIGN 32 {
        *tfm_attest* (+RW +ZI)
        *(TFM_SP_INITIAL_ATTESTATION_ATTR_RW)
        *(TFM_SP_INITIAL_ATTESTATION_ATTR_ZI)
    }

    TFM_SP_INITIAL_ATTESTATION_LINKER_STACK +0 ALIGN 128 EMPTY 0x0A80 {
    }
#endif /* TFM_PARTITION_INITIAL_ATTESTATION */

#ifdef TFM_PARTITION_TEST_SECURE_SERVICES
    TFM_SP_SECURE_TEST_PARTITION_LINKER_DATA +0 ALIGN 32 {
        *tfm_secure_client_service.* (+RW +ZI)
        *test_framework* (+RW +ZI)
        *uart_stdout.* (+RW +ZI)
        *Driver_USART.* (+RW +ZI)
        *arm_uart_drv.* (+RW +ZI)
        *uart_pl011_drv.* (+RW +ZI)
        *uart_cmsdk_drv* (+RW +ZI)
        *secure_suites.* (+RW +ZI)
        *attestation_s_interface_testsuite.* (+RW +ZI)
        *(TFM_SP_SECURE_TEST_PARTITION_ATTR_RW)
        *(TFM_SP_SECURE_TEST_PARTITION_ATTR_ZI)
    }

    TFM_SP_SECURE_TEST_PARTITION_LINKER_STACK +0 ALIGN 128 EMPTY 0x0D00 {
    }
#endif /* TFM_PARTITION_TEST_SECURE_SERVICES */

#ifdef TFM_PARTITION_TEST_CORE_IPC
    TFM_SP_IPC_SERVICE_TEST_LINKER_DATA +0 ALIGN 32 {
        *ipc_service_test.* (+RW +ZI)
        *(TFM_SP_IPC_SERVICE_TEST_ATTR_RW)
        *(TFM_SP_IPC_SERVICE_TEST_ATTR_ZI)
    }

    TFM_SP_IPC_SERVICE_TEST_LINKER_STACK +0 ALIGN 128 EMPTY 0x0220 {
    }
#endif /* TFM_PARTITION_TEST_CORE_IPC */

#ifdef TFM_PARTITION_TEST_PS
    TFM_SP_PS_TEST_LINKER_DATA +0 ALIGN 32 {
        *tfm_ps_test_service.* (+RW +ZI)
        *(TFM_SP_PS_TEST_ATTR_RW)
        *(TFM_SP_PS_TEST_ATTR_ZI)
    }

    TFM_SP_PS_TEST_LINKER_STACK +0 ALIGN 128 EMPTY 0x500 {
    }
#endif /* TFM_PARTITION_TEST_PS */

    /*
     * This empty, zero long execution region is here to mark the end address
     * of PSA RoT RW and Stack.
     */
    TFM_PSA_RW_STACK_END +0 ALIGN 32 EMPTY 0x0 {
    }

#if defined (S_RAM_CODE_START)
    /* Executable code allocated in RAM */
    TFM_RAM_CODE S_RAM_CODE_START {
        * (.ramfunc)
    }
#endif

    /* This empty, zero long execution region is here to mark the limit address
     * of the last execution region that is allocated in SRAM.
     */
    SRAM_WATERMARK +0 EMPTY 0x0 {
    }

    /* Make sure that the sections allocated in the SRAM does not exceed the
     * size of the SRAM available.
     */
    ScatterAssert(ImageLimit(SRAM_WATERMARK) <= S_DATA_START + S_DATA_SIZE)
}

LR_VENEER CMSE_VENEER_REGION_START {
    /*
     * Place the CMSE Veneers (containing the SG instruction) in a separate
     * 32 bytes aligned region so that the SAU can be programmed to
     * just set this region as Non-Secure Callable.
     */
    CMSE_VENEER CMSE_VENEER_REGION_START CMSE_VENEER_REGION_SIZE {
        *(Veneer$$CMSE)
    }
}

LR_NS_PARTITION NS_PARTITION_START {
    /* Reserved place for NS application.
     * No code will be placed here, just address of this region is used in the
     * secure code to configure certain HW components. This generates an empty
     * execution region description warning during linking.
     */
    ER_NS_PARTITION NS_PARTITION_START UNINIT NS_PARTITION_SIZE {
    }
}

#ifdef BL2
LR_SECONDARY_PARTITION SECONDARY_PARTITION_START {
    /* Reserved place for new image in case of firmware upgrade.
     * No code will be placed here, just address of this region is used in the
     * secure code to configure certain HW components. This generates an empty
     * execution region description warning during linking.
     */
    ER_SECONDARY_PARTITION SECONDARY_PARTITION_START \
        UNINIT SECONDARY_PARTITION_SIZE {
    }
}
#endif /* BL2 */