1 /**
2 ******************************************************************************
3 * @file stm32h7rsxx_hal_rcc_ex.c
4 * @author MCD Application Team
5 * @brief Extended RCC HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities RCC extension peripheral:
8 * + Extended Peripheral Control functions
9 *
10 ******************************************************************************
11 * @attention
12 *
13 * Copyright (c) 2022 STMicroelectronics.
14 * All rights reserved.
15 *
16 * This software is licensed under terms that can be found in the LICENSE file
17 * in the root directory of this software component.
18 * If no LICENSE file comes with this software, it is provided AS-IS.
19 *
20 ******************************************************************************
21 */
22
23 /* Includes ------------------------------------------------------------------*/
24 #include "stm32h7rsxx_hal.h"
25
26 /** @addtogroup STM32H7RSxx_HAL_Driver
27 * @{
28 */
29
30 /** @defgroup RCCEx RCCEx
31 * @brief RCC HAL module driver
32 * @{
33 */
34
35 #ifdef HAL_RCC_MODULE_ENABLED
36
37 /* Private typedef -----------------------------------------------------------*/
38 /* Private defines -----------------------------------------------------------*/
39 /** @defgroup RCCEx_Private_defines RCCEx Private Defines
40 * @{
41 */
42
43 /**
44 * @}
45 */
46
47 /* Private macros ------------------------------------------------------------*/
48 /** @defgroup RCCEx_Private_Macros RCCEx Private Macros
49 * @{
50 */
51 /**
52 * @}
53 */
54
55 /* Private variables ---------------------------------------------------------*/
56 /* Private function prototypes -----------------------------------------------*/
57 /** @defgroup RCCEx_Private_Functions RCCEx Private Functions
58 * @{
59 */
60 static uint32_t RCC_GetCLKPFreq(void);
61 /**
62 * @}
63 */
64
65 /* Exported functions --------------------------------------------------------*/
66 /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
67 * @{
68 */
69
70 /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
71 * @brief Extended Peripheral Control functions
72 *
73 @verbatim
74 ===============================================================================
75 ##### Extended Peripheral Control functions #####
76 ===============================================================================
77 [..]
78 This subsection provides a set of functions allowing to control the RCC Clocks
79 frequencies.
80 [..]
81 (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
82 select the RTC clock source; in this case the Backup domain will be reset in
83 order to modify the RTC Clock source, as consequence RTC registers (including
84 the backup registers) and RCC_BDCR register are set to their reset values.
85
86 @endverbatim
87 * @{
88 */
89 /**
90 * @brief Initializes the RCC extended peripherals clocks according to the specified
91 * parameters in the RCC_PeriphCLKInitTypeDef.
92 * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
93 * contains the configuration information for the Extended Peripherals
94 * clocks (SDMMC12, CKPER, FMC, XSPI1, XSPI2, ADC, ADF1, CEC, FDCAN, I2C1/I3C1,
95 * I2C2, LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, LPUART1, SAI1,
96 * SAI2, SPDIF, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SAI1, USART1, USART2,
97 * USART3, UART4, UART5, UART7, UART8, ETH1, USB and RTC).
98 * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
99 * the RTC clock source; in this case the Backup domain will be reset in
100 * order to modify the RTC Clock source, as consequence RTC registers (including
101 * the backup registers) are set to their reset values.
102 *
103 * @retval HAL status
104 */
HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef * PeriphClkInit)105 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *PeriphClkInit)
106 {
107 uint32_t tmpreg;
108 uint32_t tickstart;
109 HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */
110 HAL_StatusTypeDef status = HAL_OK; /* Final status */
111
112 /* Check the parameters */
113 assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
114
115 /*---------------------------- RTC configuration -------------------------------*/
116 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
117 {
118 /* check for RTC Parameters used to output RTCCLK */
119 assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
120
121 /* As the RTC clock source selection can be changed only if the Backup Domain is reset */
122 /* reset the Backup domain only if the RTC Clock source selection is modified from default reset value */
123 tmpreg = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL);
124
125 if ((tmpreg != RCC_RTCCLKSOURCE_DISABLE) && (tmpreg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
126 {
127 /* Enable write access to Backup domain */
128 SET_BIT(PWR->CR1, PWR_CR1_DBP);
129
130 /* Read back to check Backup domain enabled */
131 if (READ_BIT(PWR->CR1, PWR_CR1_DBP) == 0U)
132 {
133 ret = HAL_ERROR;
134 }
135 else
136 {
137 /* Store the content of BDCR register before the reset of Backup Domain */
138 /* excepted the RTC clock source selection that will be changed */
139 tmpreg = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL));
140 __HAL_RCC_BACKUPRESET_FORCE();
141 __HAL_RCC_BACKUPRESET_RELEASE();
142 /* Restore the content of BDCR register */
143 WRITE_REG(RCC->BDCR, tmpreg);
144 }
145 }
146
147 if (ret == HAL_OK)
148 {
149 /* If LSE is selected as RTC clock source (and enabled prior to Backup Domain reset), wait for LSE reactivation */
150 if (PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE)
151 {
152 /* Get Start Tick*/
153 tickstart = HAL_GetTick();
154
155 /* Wait till LSE is ready */
156 while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
157 {
158 if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
159 {
160 ret = HAL_TIMEOUT;
161 break;
162 }
163 }
164 }
165
166 if (ret == HAL_OK)
167 {
168 __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
169 __HAL_RCC_RTC_ENABLE();
170 }
171 else
172 {
173 /* set overall return value */
174 status = ret;
175 }
176 }
177 else
178 {
179 /* set overall return value */
180 status = ret;
181 }
182 }
183
184 /*---------------------------- FMC configuration -------------------------------*/
185 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC)
186 {
187 /* Check the parameters */
188 assert_param(IS_RCC_FMCCLKSOURCE(PeriphClkInit->FmcClockSelection));
189
190 switch (PeriphClkInit->FmcClockSelection)
191 {
192 case RCC_FMCCLKSOURCE_HCLK: /* HCLK clock selected as FMC kernel peripheral clock */
193 break;
194
195 case RCC_FMCCLKSOURCE_PLL1Q: /* PLL1_Q is used as clock source for FMC kernel */
196 /* Enable FMC kernel clock output generated form System PLL . */
197 __HAL_RCC_PLL1CLKOUT_ENABLE(RCC_PLL_QCLK);
198 /* FMC kernel clock source configuration done later after clock selection check */
199 break;
200
201 case RCC_FMCCLKSOURCE_PLL2R: /* PLL2_R is used as clock source for FMC kernel */
202 __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_RCLK);
203 /* FMC kernel clock source configuration done later after clock selection check */
204 break;
205
206 case RCC_FMCCLKSOURCE_HSI: /* HSI oscillator is used as clock source for FMC kernel */
207 /* FMC kernel clock source configuration done later after clock selection check */
208 break;
209
210 default:
211 ret = HAL_ERROR;
212 break;
213 }
214
215 if (ret == HAL_OK)
216 {
217 /* Set the source of FMC kernel clock*/
218 __HAL_RCC_FMC_CONFIG(PeriphClkInit->FmcClockSelection);
219 }
220 else
221 {
222 /* set overall return value */
223 status = ret;
224 }
225 }
226
227 /*-------------------------- XSPI1 clock source configuration ----------------*/
228 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_XSPI1) == RCC_PERIPHCLK_XSPI1)
229 {
230 /* Check the parameters */
231 assert_param(IS_RCC_XSPI1CLKSOURCE(PeriphClkInit->Xspi1ClockSelection));
232
233 switch (PeriphClkInit->Xspi1ClockSelection)
234 {
235 case RCC_XSPI1CLKSOURCE_HCLK: /* HCLK is used as clock source for Xspi1 */
236 /* Nothing to do */
237 break;
238
239 case RCC_XSPI1CLKSOURCE_PLL2S: /* PLL2_S is used as clock source for Xspi1 */
240 __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_SCLK);
241 /* XSPI1 clock source configuration done later after clock selection check */
242 break;
243
244 case RCC_XSPI1CLKSOURCE_PLL2T: /* PLL2_T is used as clock source for Xspi1 */
245 __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_TCLK);
246 /* XSPI1 clock source configuration done later after clock selection check */
247 break;
248
249 default:
250 ret = HAL_ERROR;
251 break;
252 }
253
254 if (ret == HAL_OK)
255 {
256 /* Configure the XSPI1 clock source */
257 __HAL_RCC_XSPI1_CONFIG(PeriphClkInit->Xspi1ClockSelection);
258 }
259 else
260 {
261 /* set overall return value */
262 status = ret;
263 }
264 }
265
266 /*-------------------------- XSPI2 clock source configuration ----------------*/
267 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_XSPI2) == RCC_PERIPHCLK_XSPI2)
268 {
269 /* Check the parameters */
270 assert_param(IS_RCC_XSPI2CLKSOURCE(PeriphClkInit->Xspi2ClockSelection));
271
272 switch (PeriphClkInit->Xspi2ClockSelection)
273 {
274 case RCC_XSPI2CLKSOURCE_HCLK: /* HCLK is used as clock source for Xspi2 */
275 /* Nothing to do */
276 break;
277
278 case RCC_XSPI2CLKSOURCE_PLL2S: /* PLL2_S is used as clock source for Xspi2 */
279 __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_SCLK);
280 /* XSPI2 clock source configuration done later after clock selection check */
281 break;
282
283 case RCC_XSPI2CLKSOURCE_PLL2T: /* PLL2_T is used as clock source for Xspi2 */
284 __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_TCLK);
285 /* XSPI2 clock source configuration done later after clock selection check */
286 break;
287
288 default:
289 ret = HAL_ERROR;
290 break;
291 }
292
293 if (ret == HAL_OK)
294 {
295 /* Configure the XSPI2 clock source */
296 __HAL_RCC_XSPI2_CONFIG(PeriphClkInit->Xspi2ClockSelection);
297 }
298 else
299 {
300 /* set overall return value */
301 status = ret;
302 }
303 }
304
305 /*------------------------------------ CKPER configuration --------------------------------------*/
306 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER)
307 {
308 /* Check the parameters */
309 assert_param(IS_RCC_CKPERCLKSOURCE(PeriphClkInit->CkperClockSelection));
310
311 /* Configure the CKPER clock source */
312 __HAL_RCC_CLKP_CONFIG(PeriphClkInit->CkperClockSelection);
313 }
314
315 /*------------------------------------- SDMMC12 Configuration ------------------------------------*/
316 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_SDMMC12) == RCC_PERIPHCLK_SDMMC12)
317 {
318 /* Check the parameters */
319 assert_param(IS_RCC_SDMMC12CLKSOURCE(PeriphClkInit->Sdmmc12ClockSelection));
320
321 switch (PeriphClkInit->Sdmmc12ClockSelection)
322 {
323 case RCC_SDMMC12CLKSOURCE_PLL2S: /* PLL2_S is used as clock source for SDMMC12 kernel */
324 __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_SCLK);
325 /* SDMMC12 kernel clock source configuration done later after clock selection check */
326 break;
327
328 case RCC_SDMMC12CLKSOURCE_PLL2T: /* PLL2_T is used as clock source for SDMMC12 kernel */
329 __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_TCLK);
330 /* SDMMC12 kernel clock source configuration done later after clock selection check */
331 break;
332
333 default:
334 ret = HAL_ERROR;
335 break;
336 }
337
338 if (ret == HAL_OK)
339 {
340 /* Set the source of SDMMC12 clock*/
341 __HAL_RCC_SDMMC12_CONFIG(PeriphClkInit->Sdmmc12ClockSelection);
342 }
343 else
344 {
345 /* set overall return value */
346 status = ret;
347 }
348 }
349
350 /*---------------------------- ADC configuration -------------------------------*/
351 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
352 {
353 /* Check the parameters */
354 assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection));
355
356 switch (PeriphClkInit->AdcClockSelection)
357 {
358
359 case RCC_ADCCLKSOURCE_PLL2P: /* PLL2_P is used as clock source for ADC */
360 __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_PCLK);
361 /* ADC clock source configuration done later after clock selection check */
362 break;
363
364 case RCC_ADCCLKSOURCE_PLL3R: /* PLL3_R is used as clock source for ADC */
365 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_RCLK);
366 /* ADC clock source configuration done later after clock selection check */
367 break;
368
369 case RCC_ADCCLKSOURCE_CLKP:
370 /* HSI, HSE, or CSI oscillator is used as source of ADC clock */
371 /* ADC clock source configuration done later after clock selection check */
372 break;
373
374 default:
375 ret = HAL_ERROR;
376 break;
377 }
378
379 if (ret == HAL_OK)
380 {
381 /* Set the source of ADC clock*/
382 __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
383 }
384 else
385 {
386 /* set overall return value */
387 status = ret;
388 }
389 }
390
391 /*---------------------------- ADF1 configuration --------------------------*/
392 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_ADF1) == RCC_PERIPHCLK_ADF1)
393 {
394 /* Check the parameters */
395 assert_param(IS_RCC_ADF1CLKSOURCE(PeriphClkInit->Adf1ClockSelection));
396
397 switch (PeriphClkInit->Adf1ClockSelection)
398 {
399 case RCC_ADF1CLKSOURCE_PLL2P: /* PLL2_P is used as clock source for ADF1 */
400 __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_PCLK);
401 /* ADF1 clock source configuration done later after clock selection check */
402 break;
403
404 case RCC_ADF1CLKSOURCE_PLL3P: /* PLL3_P is used as clock source for ADF1 */
405 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_PCLK);
406 /* ADF1 clock source configuration done later after clock selection check */
407 break;
408
409 case RCC_ADF1CLKSOURCE_HCLK: /* HCLK is used as clock source for ADF1 */
410 case RCC_ADF1CLKSOURCE_PIN: /* External I2S_CKIN is used as clock source for ADF1 */
411 case RCC_ADF1CLKSOURCE_CSI: /* CSI is used as clock source for ADF1 */
412 case RCC_ADF1CLKSOURCE_HSI: /* HSI is used as clock source for ADF1 */
413 /* ADF1 clock source configuration done later after clock selection check */
414 break;
415
416 default:
417 ret = HAL_ERROR;
418 break;
419 }
420
421 if (ret == HAL_OK)
422 {
423 /* Set the source of ADF1 clock*/
424 __HAL_RCC_ADF1_CONFIG(PeriphClkInit->Adf1ClockSelection);
425 }
426 else
427 {
428 /* set overall return value */
429 status = ret;
430 }
431 }
432
433 /*---------------------- CEC configuration ---------------------------------*/
434 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
435 {
436 /* Check the parameters */
437 assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
438
439 /* Configure the CEC clock source */
440 __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
441 }
442
443 /*---------------------- ETH1 REF configuration --------------------------------*/
444 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_ETH1REF) == RCC_PERIPHCLK_ETH1REF)
445 {
446 /* Check the parameters */
447 assert_param(IS_RCC_ETH1REFCLKSOURCE(PeriphClkInit->Eth1RefClockSelection));
448
449 /* Configure the ETH1 REF clock source */
450 __HAL_RCC_ETH1REF_CONFIG(PeriphClkInit->Eth1RefClockSelection);
451 }
452
453 /*---------------------- ETH1PHY configuration --------------------------------*/
454 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_ETH1PHY) == RCC_PERIPHCLK_ETH1PHY)
455 {
456 /* Check the parameters */
457 assert_param(IS_RCC_ETH1PHYCLKSOURCE(PeriphClkInit->Eth1PhyClockSelection));
458
459 switch (PeriphClkInit->Eth1PhyClockSelection)
460 {
461 case RCC_ETH1PHYCLKSOURCE_HSE: /* HSE is used as clock source for ETH PHY */
462 /* ETH PHY clock source configuration done later after clock selection check */
463 break;
464
465 case RCC_ETH1PHYCLKSOURCE_PLL3S: /* PLL3_S is used as clock source for ETH PHY */
466 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_SCLK);
467 /* ETH PHY clock source configuration done later after clock selection check */
468 break;
469
470 default:
471 ret = HAL_ERROR;
472 break;
473 }
474
475 if (ret == HAL_OK)
476 {
477 /* Set the source of ETH PHY clock*/
478 __HAL_RCC_ETH1PHY_CONFIG(PeriphClkInit->Eth1PhyClockSelection);
479 }
480 else
481 {
482 /* set overall return value */
483 status = ret;
484 }
485 }
486
487 /*---------------------- FDCAN configuration -------------------------------*/
488 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN)
489 {
490 /* Check the parameters */
491 assert_param(IS_RCC_FDCANCLKSOURCE(PeriphClkInit->FdcanClockSelection));
492
493 switch (PeriphClkInit->FdcanClockSelection)
494 {
495 case RCC_FDCANCLKSOURCE_PLL1Q: /* PLL1_Q is used as clock source for FDCAN kernel */
496 /* Enable FDCAN Clock output generated form System PLL . */
497 __HAL_RCC_PLL1CLKOUT_ENABLE(RCC_PLL_QCLK);
498 /* FDCAN clock source configuration done later after clock selection check */
499 break;
500
501 case RCC_FDCANCLKSOURCE_PLL2P: /* PLL2_P is used as clock source for FDCAN kernel */
502 __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_PCLK);
503 /* FDCAN clock source configuration done later after clock selection check */
504 break;
505
506 case RCC_FDCANCLKSOURCE_HSE: /* HSE is used as clock source for FDCAN kernel */
507 /* FDCAN clock source configuration done later after clock selection check */
508 break;
509
510 default:
511 ret = HAL_ERROR;
512 break;
513 }
514
515 if (ret == HAL_OK)
516 {
517 /* Set the source of FDCAN clock*/
518 __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection);
519 }
520 else
521 {
522 /* set overall return value */
523 status = ret;
524 }
525 }
526
527 /*------------------------------ I2C1/I3C1 Configuration ------------------------*/
528 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_I2C1_I3C1) == RCC_PERIPHCLK_I2C1_I3C1)
529 {
530 /* Check the parameters */
531 assert_param(IS_RCC_I2C1_I3C1CLKSOURCE(PeriphClkInit->I2c1_I3c1ClockSelection));
532
533 switch (PeriphClkInit->I2c1_I3c1ClockSelection)
534 {
535 case RCC_I2C1_I3C1CLKSOURCE_PLL3R: /* PLL3_R is used as clock source for I2C1/I3C1*/
536 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_RCLK);
537 /* I2C1/I3C1 clock source configuration done later after clock selection check */
538 break;
539
540 case RCC_I2C1_I3C1CLKSOURCE_PCLK1: /* PCLK1 is used as clock source for I2C1/I3C1*/
541 case RCC_I2C1_I3C1CLKSOURCE_HSI: /* HSI is used as clock source for I2C1/I3C1*/
542 case RCC_I2C1_I3C1CLKSOURCE_CSI: /* CSI is used as clock source for I2C1/I3C1*/
543 /* I2C1/I3C1 clock source configuration done later after clock selection check */
544 break;
545
546 default:
547 ret = HAL_ERROR;
548 break;
549 }
550
551 if (ret == HAL_OK)
552 {
553 /* Set the source of I2C1/I3C1 clock*/
554 __HAL_RCC_I2C1_I3C1_CONFIG(PeriphClkInit->I2c1_I3c1ClockSelection);
555 }
556 else
557 {
558 /* set overall return value */
559 status = ret;
560 }
561 }
562
563 /*------------------------------ I2C2/I2C3 Configuration -------------------*/
564 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_I2C23) == RCC_PERIPHCLK_I2C23)
565 {
566 /* Check the parameters */
567 assert_param(IS_RCC_I2C23CLKSOURCE(PeriphClkInit->I2c23ClockSelection));
568
569 switch (PeriphClkInit->I2c23ClockSelection)
570 {
571 case RCC_I2C23CLKSOURCE_PLL3R: /* PLL3_R is used as clock source for I2C2/I2C3 */
572 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_RCLK);
573 /* I2C2/I2C3 clock source configuration done later after clock selection check */
574 break;
575
576 case RCC_I2C23CLKSOURCE_PCLK1: /* PCLK1 is used as clock source for I2C2/I2C3 */
577 case RCC_I2C23CLKSOURCE_HSI: /* HSI is used as clock source for I2C2/I2C3 */
578 case RCC_I2C23CLKSOURCE_CSI: /* CSI is used as clock source for I2C2/I2C3 */
579 /* I2C2/I2C3 clock source configuration done later after clock selection check */
580 break;
581
582 default:
583 ret = HAL_ERROR;
584 break;
585 }
586
587 if (ret == HAL_OK)
588 {
589 /* Set the source of I2C2/I2C3 clock*/
590 __HAL_RCC_I2C23_CONFIG(PeriphClkInit->I2c23ClockSelection);
591 }
592 else
593 {
594 /* set overall return value */
595 status = ret;
596 }
597 }
598
599 /*---------------------------- LPTIM1 configuration -------------------------------*/
600 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
601 {
602 /* Check the parameters */
603 assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection));
604
605 switch (PeriphClkInit->Lptim1ClockSelection)
606 {
607 case RCC_LPTIM1CLKSOURCE_PCLK1: /* PCLK1 as clock source for LPTIM1 */
608 /* LPTIM1 clock source configuration done later after clock selection check */
609 break;
610
611 case RCC_LPTIM1CLKSOURCE_PLL2P: /* PLL2_P is used as clock source for LPTIM1 */
612 __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_PCLK);
613 /* LPTIM1 clock source configuration done later after clock selection check */
614 break;
615
616 case RCC_LPTIM1CLKSOURCE_PLL3R: /* PLL3_R is used as clock source for LPTIM1 */
617 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_RCLK);
618 /* LPTIM1 clock source configuration done later after clock selection check */
619 break;
620
621 case RCC_LPTIM1CLKSOURCE_LSE:
622 /* External low speed OSC clock is used as clock source for LPTIM1 */
623 /* LPTIM1 clock source configuration done later after clock selection check */
624 break;
625
626 case RCC_LPTIM1CLKSOURCE_LSI:
627 /* Internal low speed OSC clock is used as clock source for LPTIM1 */
628 /* LPTIM1 clock source configuration done later after clock selection check */
629 break;
630
631 case RCC_LPTIM1CLKSOURCE_CLKP:
632 /* HSI, HSE, or CSI oscillator is used as clock source for LPTIM1 */
633 /* LPTIM1 clock source configuration done later after clock selection check */
634 break;
635
636 default:
637 ret = HAL_ERROR;
638 break;
639 }
640
641 if (ret == HAL_OK)
642 {
643 /* Set the source of LPTIM1 clock*/
644 __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
645 }
646 else
647 {
648 /* set overall return value */
649 status = ret;
650 }
651 }
652
653 /*---------------------------- LPTIM2/LPTIM3 configuration -----------------*/
654 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_LPTIM23) == RCC_PERIPHCLK_LPTIM23)
655 {
656 switch (PeriphClkInit->Lptim23ClockSelection)
657 {
658 case RCC_LPTIM23CLKSOURCE_PCLK4: /* PCLK4 as clock source for LPTIM2/LPTIM3 */
659 /* LPTIM2/LPTIM3 clock source configuration done later after clock selection check */
660 break;
661
662 case RCC_LPTIM23CLKSOURCE_PLL2P: /* PLL2_P is used as clock source for LPTIM2/LPTIM3 */
663 __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_PCLK);
664 /* LPTIM2/LPTIM3 clock source configuration done later after clock selection check */
665 break;
666
667 case RCC_LPTIM23CLKSOURCE_PLL3R: /* PLL3_R is used as clock source for LPTIM2/LPTIM3 */
668 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_RCLK);
669 /* LPTIM2/LPTIM3 clock source configuration done later after clock selection check */
670 break;
671
672 case RCC_LPTIM23CLKSOURCE_LSE:
673 /* External low speed OSC clock is used as clock source for LPTIM2/LPTIM3 */
674 /* LPTIM2/LPTIM3 clock source configuration done later after clock selection check */
675 break;
676
677 case RCC_LPTIM23CLKSOURCE_LSI:
678 /* Internal low speed OSC clock is used as clock source for LPTIM2/LPTIM3 */
679 /* LPTIM2/LPTIM3 clock source configuration done later after clock selection check */
680 break;
681
682 case RCC_LPTIM23CLKSOURCE_CLKP:
683 /* HSI, HSE, or CSI oscillator is used as source of LPTIM2 clock */
684 /* LPTIM2/LPTIM3 clock source configuration done later after clock selection check */
685 break;
686
687 default:
688 ret = HAL_ERROR;
689 break;
690 }
691
692 if (ret == HAL_OK)
693 {
694 /* Set the source of LPTIM2/LPTIM3 clock*/
695 __HAL_RCC_LPTIM23_CONFIG(PeriphClkInit->Lptim23ClockSelection);
696 }
697 else
698 {
699 /* set overall return value */
700 status = ret;
701 }
702 }
703
704 /*---------------------------- LPTIM4/LPTIM5 configuration -----------------*/
705 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_LPTIM45) == RCC_PERIPHCLK_LPTIM45)
706 {
707 switch (PeriphClkInit->Lptim45ClockSelection)
708 {
709 case RCC_LPTIM45CLKSOURCE_PCLK4: /* PCLK4 as clock source for LPTIM4/LPTIM5 */
710 /* LPTIM4/LPTIM5 clock source configuration done later after clock selection check */
711 break;
712
713 case RCC_LPTIM45CLKSOURCE_PLL2P: /* PLL2 is used as clock source for LPTIM4/LPTIM5 */
714 __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_PCLK);
715 /* LPTIM4/LPTIM5 clock source configuration done later after clock selection check */
716 break;
717
718 case RCC_LPTIM45CLKSOURCE_PLL3R: /* PLL3 is used as clock source for LPTIM4/LPTIM5 */
719 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_RCLK);
720 /* LPTIM4/LPTIM5 clock source configuration done later after clock selection check */
721 break;
722
723 case RCC_LPTIM45CLKSOURCE_LSE:
724 /* External low speed OSC clock is used as source of LPTIM4/LPTIM5 clock */
725 /* LPTIM4/LPTIM5 clock source configuration done later after clock selection check */
726 break;
727
728 case RCC_LPTIM45CLKSOURCE_LSI:
729 /* Internal low speed OSC clock is used as source of LPTIM4/LPTIM5 clock */
730 /* LPTIM4/LPTIM5 clock source configuration done later after clock selection check */
731 break;
732
733 case RCC_LPTIM45CLKSOURCE_CLKP:
734 /* HSI, HSE, or CSI oscillator is used as source of LPTIM4/LPTIM5 clock */
735 /* LPTIM4/LPTIM5 clock source configuration done later after clock selection check */
736 break;
737
738 default:
739 ret = HAL_ERROR;
740 break;
741 }
742
743 if (ret == HAL_OK)
744 {
745 /* Set the source of LPTIM4/LPTIM5 clock */
746 __HAL_RCC_LPTIM45_CONFIG(PeriphClkInit->Lptim45ClockSelection);
747 }
748 else
749 {
750 /* set overall return value */
751 status = ret;
752 }
753 }
754
755 /*-------------------------- LPUART1 Configuration -------------------------*/
756 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
757 {
758 /* Check the parameters */
759 assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));
760
761 switch (PeriphClkInit->Lpuart1ClockSelection)
762 {
763 case RCC_LPUART1CLKSOURCE_PCLK4: /* PCLK4 selected as clock source for LPUART1 */
764 /* LPUART1 clock source configuration done later after clock selection check */
765 break;
766
767 case RCC_LPUART1CLKSOURCE_PLL2Q: /* PLL2_Q is used as clock source for LPUART1 */
768 __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_QCLK);
769 /* LPUART1 clock source configuration done later after clock selection check */
770 break;
771
772 case RCC_LPUART1CLKSOURCE_PLL3Q: /* PLL3_Q is used as clock source for LPUART1 */
773 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_QCLK);
774 /* LPUART1 clock source configuration done later after clock selection check */
775 break;
776
777 case RCC_LPUART1CLKSOURCE_HSI:
778 /* HSI oscillator clock is used as source of LPUART1 clock */
779 /* LPUART1 clock source configuration done later after clock selection check */
780 break;
781
782 case RCC_LPUART1CLKSOURCE_CSI:
783 /* CSI oscillator clock is used as source of LPUART1 clock */
784 /* LPUART1 clock source configuration done later after clock selection check */
785 break;
786
787 case RCC_LPUART1CLKSOURCE_LSE:
788 /* LSE, oscillator is used as source of LPUART1 clock */
789 /* LPUART1 clock source configuration done later after clock selection check */
790 break;
791
792 default:
793 ret = HAL_ERROR;
794 break;
795 }
796
797 if (ret == HAL_OK)
798 {
799 /* Set the source of LPUART1 clock */
800 __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
801 }
802 else
803 {
804 /* set overall return value */
805 status = ret;
806 }
807 }
808
809 /*-------------------------- LTDC Configuration ----------------------------*/
810 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)
811 {
812 /* LTDC internally connected to PLL3_R output clock */
813 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_RCLK);
814 }
815
816 /*---------------------------- PSSI configuration --------------------------*/
817 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PSSI) == RCC_PERIPHCLK_PSSI)
818 {
819 /* Check the parameters */
820 assert_param(IS_RCC_PSSICLKSOURCE(PeriphClkInit->PssiClockSelection));
821
822 switch (PeriphClkInit->PssiClockSelection)
823 {
824 case RCC_PSSICLKSOURCE_PLL3R: /* PLL3_R is used as clock source for PSSI */
825 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_RCLK);
826 /* PSSI clock source configuration done later after clock selection check */
827 break;
828
829 case RCC_PSSICLKSOURCE_CLKP:
830 /* HSI, HSE, or CSI oscillator is used as source of PSSI clock */
831 /* PSSI clock source configuration done later after clock selection check */
832 break;
833
834 default:
835 ret = HAL_ERROR;
836 break;
837 }
838
839 if (ret == HAL_OK)
840 {
841 /* Set the source of PSSI clock*/
842 __HAL_RCC_PSSI_CONFIG(PeriphClkInit->PssiClockSelection);
843 }
844 else
845 {
846 /* set overall return value */
847 status = ret;
848 }
849 }
850
851 /*---------------------------- SAI1 configuration --------------------------*/
852 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)
853 {
854 /* Check the parameters */
855 assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
856
857 switch (PeriphClkInit->Sai1ClockSelection)
858 {
859 case RCC_SAI1CLKSOURCE_PLL1Q: /* PLL1_Q is used as clock source for SAI1 */
860 /* Enable SAI Clock output generated form System PLL . */
861 __HAL_RCC_PLL1CLKOUT_ENABLE(RCC_PLL_QCLK);
862 /* SAI1 clock source configuration done later after clock selection check */
863 break;
864
865 case RCC_SAI1CLKSOURCE_PLL2P: /* PLL2_P is used as clock source for SAI1 */
866 __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_PCLK);
867 /* SAI1 clock source configuration done later after clock selection check */
868 break;
869
870 case RCC_SAI1CLKSOURCE_PLL3P: /* PLL3_P is used as clock source for SAI1 */
871 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_PCLK);
872 /* SAI1 clock source configuration done later after clock selection check */
873 break;
874
875 case RCC_SAI1CLKSOURCE_PIN: /* External clock is used as source of SAI1 clock */
876 /* SAI1 clock source configuration done later after clock selection check */
877 break;
878
879 case RCC_SAI1CLKSOURCE_CLKP:
880 /* HSI, HSE, or CSI oscillator is used as source of SAI1 clock */
881 /* SAI1 clock source configuration done later after clock selection check */
882 break;
883
884 default:
885 ret = HAL_ERROR;
886 break;
887 }
888
889 if (ret == HAL_OK)
890 {
891 /* Set the source of SAI1 clock*/
892 __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
893 }
894 else
895 {
896 /* set overall return value */
897 status = ret;
898 }
899 }
900
901 /*---------------------------- SAI2 configuration --------------------------*/
902 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2)
903 {
904 /* Check the parameters */
905 assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));
906
907 switch (PeriphClkInit->Sai2ClockSelection)
908 {
909 case RCC_SAI2CLKSOURCE_PLL1Q: /* PLL1_Q is used as clock source for SAI2 */
910 /* Enable SAI Clock output generated form System PLL . */
911 __HAL_RCC_PLL1CLKOUT_ENABLE(RCC_PLL_QCLK);
912 /* SAI2 clock source configuration done later after clock selection check */
913 break;
914
915 case RCC_SAI2CLKSOURCE_PLL2P: /* PLL2_P is used as clock source for SAI2 */
916 __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_PCLK);
917 /* SAI2 clock source configuration done later after clock selection check */
918 break;
919
920 case RCC_SAI2CLKSOURCE_PLL3P: /* PLL3_P is used as clock source for SAI2 */
921 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_PCLK);
922 /* SAI2 clock source configuration done later after clock selection check */
923 break;
924
925 case RCC_SAI2CLKSOURCE_PIN: /* External clock is used as source of SAI2 clock */
926 /* SAI2 clock source configuration done later after clock selection check */
927 break;
928
929 case RCC_SAI2CLKSOURCE_CLKP:
930 /* HSI, HSE, or CSI oscillator is used as source of SAI2 clock */
931 /* SAI2 clock source configuration done later after clock selection check */
932 break;
933
934 case RCC_SAI2CLKSOURCE_SPDIF: /* SPDIF clock is used as source of SAI2 clock */
935 /* SAI2 clock source configuration done later after clock selection check */
936 break;
937
938 default:
939 ret = HAL_ERROR;
940 break;
941 }
942
943 if (ret == HAL_OK)
944 {
945 /* Set the source of SAI2 clock*/
946 __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
947 }
948 else
949 {
950 /* set overall return value */
951 status = ret;
952 }
953 }
954
955 /*---------------------------- SPDIFRX configuration -------------------------------*/
956 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
957 {
958 /* Check the parameters */
959 assert_param(IS_RCC_SPDIFRXCLKSOURCE(PeriphClkInit->SpdifrxClockSelection));
960
961 switch (PeriphClkInit->SpdifrxClockSelection)
962 {
963 case RCC_SPDIFRXCLKSOURCE_PLL1Q: /* PLL1_Q is used as clock source for SPDIFRX */
964 /* Enable PLL1Q Clock output generated form System PLL . */
965 __HAL_RCC_PLL1CLKOUT_ENABLE(RCC_PLL_QCLK);
966 /* SPDIFRX clock source configuration done later after clock selection check */
967 break;
968
969 case RCC_SPDIFRXCLKSOURCE_PLL2R: /* PLL2_R is used as clock source for SPDIFRX */
970 __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_RCLK);
971 /* SPDIFRX clock source configuration done later after clock selection check */
972 break;
973
974 case RCC_SPDIFRXCLKSOURCE_PLL3R: /* PLL3_R is used as clock source for SPDIFRX */
975 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_RCLK);
976 /* SPDIFRX clock source configuration done later after clock selection check */
977 break;
978
979 case RCC_SPDIFRXCLKSOURCE_HSI:
980 /* Internal OSC clock is used as source of SPDIFRX clock*/
981 /* SPDIFRX clock source configuration done later after clock selection check */
982 break;
983
984 default:
985 ret = HAL_ERROR;
986 break;
987 }
988
989 if (ret == HAL_OK)
990 {
991 /* Set the source of SPDIFRX clock */
992 __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifrxClockSelection);
993 }
994 else
995 {
996 /* set overall return value */
997 status = ret;
998 }
999 }
1000
1001 /*---------------------------- SPI1 configuration --------------------------*/
1002 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_SPI1) == RCC_PERIPHCLK_SPI1)
1003 {
1004 /* Check the parameters */
1005 assert_param(IS_RCC_SPI1CLKSOURCE(PeriphClkInit->Spi1ClockSelection));
1006
1007 switch (PeriphClkInit->Spi1ClockSelection)
1008 {
1009 case RCC_SPI1CLKSOURCE_PLL1Q: /* PLL1_Q is used as clock source for SPI1 */
1010 /* Enable SPI Clock output generated form System PLL . */
1011 __HAL_RCC_PLL1CLKOUT_ENABLE(RCC_PLL_QCLK);
1012 /* SPI1 clock source configuration done later after clock selection check */
1013 break;
1014
1015 case RCC_SPI1CLKSOURCE_PLL2P: /* PLL2_P is used as clock source for SPI1 */
1016 __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_PCLK);
1017 /* SPI1 clock source configuration done later after clock selection check */
1018 break;
1019
1020 case RCC_SPI1CLKSOURCE_PLL3P: /* PLL3_P is used as clock source for SPI1 */
1021 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_PCLK);
1022 /* SPI1 clock source configuration done later after clock selection check */
1023 break;
1024
1025 case RCC_SPI1CLKSOURCE_PIN: /* External I2S_CKIN is used as clock source for SPI1 */
1026 /* SPI1 clock source configuration done later after clock selection check */
1027 break;
1028
1029 case RCC_SPI1CLKSOURCE_CLKP: /* HSI, HSE, or CSI oscillator is used as source of SPI1 clock */
1030 /* SPI1 clock source configuration done later after clock selection check */
1031 break;
1032
1033 default:
1034 ret = HAL_ERROR;
1035 break;
1036 }
1037
1038 if (ret == HAL_OK)
1039 {
1040 /* Set the source of SPI1 clock*/
1041 __HAL_RCC_SPI1_CONFIG(PeriphClkInit->Spi1ClockSelection);
1042 }
1043 else
1044 {
1045 /* set overall return value */
1046 status = ret;
1047 }
1048 }
1049
1050 /*---------------------------- SPI2/SPI3 configuration ---------------------*/
1051 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_SPI23) == RCC_PERIPHCLK_SPI23)
1052 {
1053 /* Check the parameters */
1054 assert_param(IS_RCC_SPI23CLKSOURCE(PeriphClkInit->Spi23ClockSelection));
1055
1056 switch (PeriphClkInit->Spi23ClockSelection)
1057 {
1058 case RCC_SPI23CLKSOURCE_PLL1Q: /* PLL1_Q is used as clock source for SPI2/SPI3 */
1059 /* Enable SPI Clock output generated form System PLL . */
1060 __HAL_RCC_PLL1CLKOUT_ENABLE(RCC_PLL_QCLK);
1061 /* SPI2/SPI3 clock source configuration done later after clock selection check */
1062 break;
1063
1064 case RCC_SPI23CLKSOURCE_PLL2P: /* PLL2_P is used as clock source for SPI2/SPI3 */
1065 __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_PCLK);
1066 /* SPI2/SPI3 clock source configuration done later after clock selection check */
1067 break;
1068
1069 case RCC_SPI23CLKSOURCE_PLL3P: /* PLL3_P is used as clock source for SPI2/SPI3 */
1070 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_PCLK);
1071 /* SPI2/SPI3 clock source configuration done later after clock selection check */
1072 break;
1073
1074 case RCC_SPI23CLKSOURCE_PIN: /* External clock I2S_CKIN is used as clock source for SPI2/SPI3 */
1075 /* SPI2/SPI3 clock source configuration done later after clock selection check */
1076 break;
1077
1078 case RCC_SPI23CLKSOURCE_CLKP: /* HSI, HSE, or CSI oscillator is used as source of SPI2/SPI3 clock */
1079 /* SPI2/SPI3 clock source configuration done later after clock selection check */
1080 break;
1081
1082 default:
1083 ret = HAL_ERROR;
1084 break;
1085 }
1086
1087 if (ret == HAL_OK)
1088 {
1089 /* Set the source of SPI2/SPI3 clock*/
1090 __HAL_RCC_SPI23_CONFIG(PeriphClkInit->Spi23ClockSelection);
1091 }
1092 else
1093 {
1094 /* set overall return value */
1095 status = ret;
1096 }
1097 }
1098
1099 /*---------------------------- SPI4/5 configuration -------------------------------*/
1100 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_SPI45) == RCC_PERIPHCLK_SPI45)
1101 {
1102 /* Check the parameters */
1103 assert_param(IS_RCC_SPI45CLKSOURCE(PeriphClkInit->Spi45ClockSelection));
1104
1105 switch (PeriphClkInit->Spi45ClockSelection)
1106 {
1107 case RCC_SPI45CLKSOURCE_PCLK2: /* PCLK2 as clock source for SPI4/SPI5 */
1108 /* SPI4/SPI5 clock source configuration done later after clock selection check */
1109 break;
1110
1111 case RCC_SPI45CLKSOURCE_PLL2Q: /* PLL2_Q is used as clock source for SPI4/SPI5 */
1112 __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_QCLK);
1113 /* SPI4/SPI5 clock source configuration done later after clock selection check */
1114 break;
1115
1116 case RCC_SPI45CLKSOURCE_PLL3Q: /* PLL3_Q is used as clock source for SPI4/SPI5 */
1117 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_QCLK);
1118 /* SPI4/SPI5 clock source configuration done later after clock selection check */
1119 break;
1120
1121 case RCC_SPI45CLKSOURCE_HSI: /* HSI oscillator clock is used as source of SPI4/SPI5 */
1122 /* SPI4/SPI5 clock source configuration done later after clock selection check */
1123 break;
1124
1125 case RCC_SPI45CLKSOURCE_CSI: /* CSI oscillator clock is used as source of SPI4/SPI5 */
1126 /* SPI4/SPI5 clock source configuration done later after clock selection check */
1127 break;
1128
1129 case RCC_SPI45CLKSOURCE_HSE: /* HSE oscillator clock is used as source of SPI4/SPI5 */
1130 /* SPI4/SPI5 clock source configuration done later after clock selection check */
1131 break;
1132
1133 default:
1134 ret = HAL_ERROR;
1135 break;
1136 }
1137
1138 if (ret == HAL_OK)
1139 {
1140 /* Set the source of SPI4/SPI5 clock */
1141 __HAL_RCC_SPI45_CONFIG(PeriphClkInit->Spi45ClockSelection);
1142 }
1143 else
1144 {
1145 /* set overall return value */
1146 status = ret;
1147 }
1148 }
1149
1150 /*---------------------------- SPI6 configuration --------------------------*/
1151 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6)
1152 {
1153 /* Check the parameters */
1154 assert_param(IS_RCC_SPI6CLKSOURCE(PeriphClkInit->Spi6ClockSelection));
1155
1156 switch (PeriphClkInit->Spi6ClockSelection)
1157 {
1158 case RCC_SPI6CLKSOURCE_PCLK4: /* PCLK4 as clock source for SPI6 */
1159 /* SPI6 clock source configuration done later after clock selection check */
1160 break;
1161
1162 case RCC_SPI6CLKSOURCE_PLL2Q: /* PLL2_Q is used as clock source for SPI6 */
1163 __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_QCLK);
1164 /* SPI6 clock source configuration done later after clock selection check */
1165 break;
1166
1167 case RCC_SPI6CLKSOURCE_PLL3Q: /* PLL3_Q is used as clock source for SPI6 */
1168 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_QCLK);
1169 /* SPI6 clock source configuration done later after clock selection check */
1170 break;
1171
1172 case RCC_SPI6CLKSOURCE_HSI: /* HSI oscillator clock is used as source for SPI6 */
1173 /* SPI6 clock source configuration done later after clock selection check */
1174 break;
1175
1176 case RCC_SPI6CLKSOURCE_CSI: /* CSI oscillator clock is used as source for SPI6 */
1177 /* SPI6 clock source configuration done later after clock selection check */
1178 break;
1179
1180 case RCC_SPI6CLKSOURCE_HSE: /* HSE oscillator is used as source for SPI6 */
1181 /* SPI6 clock source configuration done later after clock selection check */
1182 break;
1183
1184 default:
1185 ret = HAL_ERROR;
1186 break;
1187 }
1188
1189 if (ret == HAL_OK)
1190 {
1191 /* Set the source of SPI6 clock*/
1192 __HAL_RCC_SPI6_CONFIG(PeriphClkInit->Spi6ClockSelection);
1193 }
1194 else
1195 {
1196 /* set overall return value */
1197 status = ret;
1198 }
1199 }
1200
1201 /*-------------------------- USART1 configuration --------------------------*/
1202 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
1203 {
1204 /* Check the parameters */
1205 assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
1206
1207 switch (PeriphClkInit->Usart1ClockSelection)
1208 {
1209 case RCC_USART1CLKSOURCE_PCLK2: /* PCLK2 as clock source for USART1 */
1210 /* USART1 clock source configuration done later after clock selection check */
1211 break;
1212
1213 case RCC_USART1CLKSOURCE_PLL2Q: /* PLL2_Q is used as clock source for USART1 */
1214 __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_QCLK);
1215 /* USART1 clock source configuration done later after clock selection check */
1216 break;
1217
1218 case RCC_USART1CLKSOURCE_PLL3Q: /* PLL3_Q is used as clock source for USART1 */
1219 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_QCLK);
1220 /* USART1 clock source configuration done later after clock selection check */
1221 break;
1222
1223 case RCC_USART1CLKSOURCE_HSI: /* HSI oscillator clock is used as source for USART1 */
1224 /* USART1 clock source configuration done later after clock selection check */
1225 break;
1226
1227 case RCC_USART1CLKSOURCE_CSI: /* CSI oscillator clock is used as source for USART1 */
1228 /* USART1 clock source configuration done later after clock selection check */
1229 break;
1230
1231 case RCC_USART1CLKSOURCE_LSE: /* LSE oscillator is used as source for USART1 */
1232 /* USART1 clock source configuration done later after clock selection check */
1233 break;
1234
1235 default:
1236 ret = HAL_ERROR;
1237 break;
1238 }
1239
1240 if (ret == HAL_OK)
1241 {
1242 /* Set the source of USART1 clock */
1243 __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
1244 }
1245 else
1246 {
1247 /* set overall return value */
1248 status = ret;
1249 }
1250 }
1251
1252 /*------------- USART2/USART3/UART4/UART5/UART7/UART8 Configuration --------*/
1253 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_USART234578) == RCC_PERIPHCLK_USART234578)
1254 {
1255 /* Check the parameters */
1256 assert_param(IS_RCC_USART234578CLKSOURCE(PeriphClkInit->Usart234578ClockSelection));
1257
1258 switch (PeriphClkInit->Usart234578ClockSelection)
1259 {
1260 case RCC_USART234578CLKSOURCE_PCLK1: /* PCLK1 as clock source for USART2/USART3/UART4/UART5/UART7/UART8 */
1261 /* USART2/USART3/UART4/UART5/UART7/UART8 clock source configuration done later after clock selection check */
1262 break;
1263
1264 case RCC_USART234578CLKSOURCE_PLL2Q: /* PLL2_Q is used as clock source for USART2/USART3/UART4/UART5/UART7/UART8 */
1265 __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_QCLK);
1266 /* USART2/USART3/UART4/UART5/UART7/UART8 clock source configuration done later after clock selection check */
1267 break;
1268
1269 case RCC_USART234578CLKSOURCE_PLL3Q: /* PLL3_Q is used as clock source for USART2/USART3/UART4/UART5/UART7/UART8 */
1270 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_QCLK);
1271 /* USART2/USART3/UART4/UART5/UART7/UART8 clock source configuration done later after clock selection check */
1272 break;
1273
1274 case RCC_USART234578CLKSOURCE_HSI:
1275 /* HSI oscillator clock is used as source of USART2/USART3/UART4/UART5/UART7/UART8 clock */
1276 /* USART2/USART3/UART4/UART5/UART7/UART8 clock source configuration done later after clock selection check */
1277 break;
1278
1279 case RCC_USART234578CLKSOURCE_CSI:
1280 /* CSI oscillator clock is used as source of USART2/USART3/UART4/UART5/UART7/UART8 clock */
1281 /* USART2/USART3/UART4/UART5/UART7/UART8 clock source configuration done later after clock selection check */
1282 break;
1283
1284 case RCC_USART234578CLKSOURCE_LSE:
1285 /* LSE, oscillator is used as source of USART2/USART3/UART4/UART5/UART7/UART8 clock */
1286 /* USART2/USART3/UART4/UART5/UART7/UART8 clock source configuration done later after clock selection check */
1287 break;
1288
1289 default:
1290 ret = HAL_ERROR;
1291 break;
1292 }
1293
1294 if (ret == HAL_OK)
1295 {
1296 /* Set the source of USART2/USART3/UART4/UART5/UART7/UART8 clock */
1297 __HAL_RCC_USART234578_CONFIG(PeriphClkInit->Usart234578ClockSelection);
1298 }
1299 else
1300 {
1301 /* set overall return value */
1302 status = ret;
1303 }
1304 }
1305
1306 /*------------------------------ USBPHYC Configuration ---------------------*/
1307 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_USBPHYC) == RCC_PERIPHCLK_USBPHYC)
1308 {
1309 /* Check the parameters */
1310 assert_param(IS_RCC_USBPHYCCLKSOURCE(PeriphClkInit->UsbPhycClockSelection));
1311
1312 switch (PeriphClkInit->UsbPhycClockSelection)
1313 {
1314 case RCC_USBPHYCCLKSOURCE_PLL3Q: /* PLL3_Q is used as clock source for USBPHYC */
1315 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_QCLK);
1316 /* USBPHYC clock source configuration done later after clock selection check */
1317 break;
1318
1319 case RCC_USBPHYCCLKSOURCE_HSE: /* HSE is used as clock source for USBPHYC */
1320 case RCC_USBPHYCCLKSOURCE_HSE_DIV2: /* HSE divided by 2 is used as clock source for USBPHYC */
1321 /* USBPHYC clock source configuration done later after clock selection check */
1322 break;
1323
1324 default:
1325 ret = HAL_ERROR;
1326 break;
1327 }
1328
1329 if (ret == HAL_OK)
1330 {
1331 /* Set the source of USBPHYC clock*/
1332 __HAL_RCC_USBPHYC_CONFIG(PeriphClkInit->UsbPhycClockSelection);
1333 }
1334 else
1335 {
1336 /* set overall return value */
1337 status = ret;
1338 }
1339 }
1340
1341 /*------------------------------ USBOTGFS Configuration ---------------------*/
1342 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_USBOTGFS) == RCC_PERIPHCLK_USBOTGFS)
1343 {
1344 /* Check the parameters */
1345 assert_param(IS_RCC_USBOTGFSCLKSOURCE(PeriphClkInit->UsbOtgFsClockSelection));
1346
1347 switch (PeriphClkInit->UsbOtgFsClockSelection)
1348 {
1349 case RCC_USBOTGFSCLKSOURCE_PLL3Q: /* PLL3_Q is used as clock source for USB OTG FS */
1350 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_QCLK);
1351 /* USB OTG FS clock source configuration done later after clock selection check */
1352 break;
1353
1354 case RCC_USBOTGFSCLKSOURCE_HSI48: /* HSI48 is used as clock source for USB OTG FS */
1355 case RCC_USBOTGFSCLKSOURCE_HSE: /* HSE is used as clock source for USB OTG FS */
1356 case RCC_USBOTGFSCLKSOURCE_CLK48: /* USBPHYC CLK48 is used as clock source for USB OTG FS */
1357 /* USB OTG FS clock source configuration done later after clock selection check */
1358 break;
1359
1360 default:
1361 ret = HAL_ERROR;
1362 break;
1363 }
1364
1365 if (ret == HAL_OK)
1366 {
1367 /* Set the source of USBPHYC clock*/
1368 __HAL_RCC_USBOTGFS_CONFIG(PeriphClkInit->UsbOtgFsClockSelection);
1369 }
1370 else
1371 {
1372 /* set overall return value */
1373 status = ret;
1374 }
1375 }
1376
1377 /*------------------------------------ TIM configuration --------------------------------------*/
1378 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM)
1379 {
1380 /* Check the parameters */
1381 assert_param(IS_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection));
1382
1383 /* Configure Timer Prescaler */
1384 __HAL_RCC_TIMCLKPRESCALER_CONFIG(PeriphClkInit->TIMPresSelection);
1385 }
1386
1387 if (status == HAL_OK)
1388 {
1389 return HAL_OK;
1390 }
1391 return HAL_ERROR;
1392 }
1393
1394 /**
1395 * @brief Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
1396 * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
1397 * returns the configuration information for the Extended Peripherals clocks :
1398 * (SDMMC12, CKPER, FMC, ADC, ADF1, CEC, FDCAN, I2C2/I2C3, I3C1, LPTIM1,
1399 * LPTIM2/LPTIM3, LPTIM4/LPTIM5, LTDC, LPUART1, XSPI1, XSPI2, PSSI, RTC, SAI1, SAI2,
1400 * SPDIF, SPI1, SPI2/SPI3, SPI4/SPI5, SPI6, TIM, USART1, USART2/USART3/UART4/UART5/UART7/UART8
1401 * USBPHYC, USB OTGFS).
1402 * @retval None
1403 */
HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef * PeriphClkInit)1404 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
1405 {
1406 /* Set all possible values for the extended clock type parameter------------*/
1407 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_ADF1 | RCC_PERIPHCLK_CEC | \
1408 RCC_PERIPHCLK_CKPER | RCC_PERIPHCLK_ETH1REF | RCC_PERIPHCLK_ETH1PHY | \
1409 RCC_PERIPHCLK_FDCAN | RCC_PERIPHCLK_FMC | RCC_PERIPHCLK_I2C1_I3C1 | \
1410 RCC_PERIPHCLK_I2C23 | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM23 | \
1411 RCC_PERIPHCLK_LPTIM45 | RCC_PERIPHCLK_LTDC | RCC_PERIPHCLK_LPUART1 | \
1412 RCC_PERIPHCLK_XSPI1 | RCC_PERIPHCLK_XSPI2 | RCC_PERIPHCLK_PSSI | \
1413 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \
1414 RCC_PERIPHCLK_SDMMC12 | RCC_PERIPHCLK_SPDIFRX | RCC_PERIPHCLK_SPI1 | \
1415 RCC_PERIPHCLK_SPI23 | RCC_PERIPHCLK_SPI45 | RCC_PERIPHCLK_SPI6 | \
1416 RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART234578 | \
1417 RCC_PERIPHCLK_USBPHYC | RCC_PERIPHCLK_USBOTGFS;
1418
1419 /* Get the ADC clock source ------------------------------------------------*/
1420 PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE();
1421 /* Get the ADF1 clock source -----------------------------------------------*/
1422 PeriphClkInit->Adf1ClockSelection = __HAL_RCC_GET_ADF1_SOURCE();
1423 /* Get the CEC clock source ------------------------------------------------*/
1424 PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE();
1425 /* Get the CKPER clock source ----------------------------------------------*/
1426 PeriphClkInit->CkperClockSelection = __HAL_RCC_GET_CLKP_SOURCE();
1427 /* Get the ETH1 clock source ----------------------------------------------*/
1428 PeriphClkInit->Eth1RefClockSelection = __HAL_RCC_GET_ETH1REF_SOURCE();
1429 /* Get the ETH1PHY clock source ----------------------------------------------*/
1430 PeriphClkInit->Eth1PhyClockSelection = __HAL_RCC_GET_ETH1PHY_SOURCE();
1431 /* Get the FDCAN kernel clock source ---------------------------------------*/
1432 PeriphClkInit->FdcanClockSelection = __HAL_RCC_GET_FDCAN_SOURCE();
1433 /* Get the FMC kernel clock source -----------------------------------------*/
1434 PeriphClkInit->FmcClockSelection = __HAL_RCC_GET_FMC_SOURCE();
1435 /* Get the I2C1 clock source -----------------------------------------------*/
1436 PeriphClkInit->I2c1_I3c1ClockSelection = __HAL_RCC_GET_I2C1_I3C1_SOURCE();
1437 /* Get the I2C2/I2C3 clock source ------------------------------------------*/
1438 PeriphClkInit->I2c23ClockSelection = __HAL_RCC_GET_I2C23_SOURCE();
1439 /* Get the LPTIM1 clock source ---------------------------------------------*/
1440 PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE();
1441 /* Get the LPTIM2/LPTIM3 clock source --------------------------------------*/
1442 PeriphClkInit->Lptim23ClockSelection = __HAL_RCC_GET_LPTIM23_SOURCE();
1443 /* Get the LPTIM4/LPTIM5 clock source --------------------------------------*/
1444 PeriphClkInit->Lptim45ClockSelection = __HAL_RCC_GET_LPTIM45_SOURCE();
1445 /* Get the LPUART1 clock source --------------------------------------------*/
1446 PeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE();
1447 /* Get the LTDC clock source -----------------------------------------------*/
1448 PeriphClkInit->LtdcClockSelection = __HAL_RCC_GET_LTDC_SOURCE();
1449 /* Get the XSPI1 clock source -----------------------------------------------*/
1450 PeriphClkInit->Xspi1ClockSelection = __HAL_RCC_GET_XSPI1_SOURCE();
1451 /* Get the XSPI2 clock source -----------------------------------------------*/
1452 PeriphClkInit->Xspi2ClockSelection = __HAL_RCC_GET_XSPI2_SOURCE();
1453 /* Get the PSSI clock source -----------------------------------------------*/
1454 PeriphClkInit->PssiClockSelection = __HAL_RCC_GET_PSSI_SOURCE();
1455 /* Get the RTC clock source -----------------------------------------------*/
1456 PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE();
1457 /* Get the SAI1 clock source -----------------------------------------------*/
1458 PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();
1459 /* Get the SAI2 clock source -----------------------------------------------*/
1460 PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE();
1461 /* Get the SDMMC clock source ----------------------------------------------*/
1462 PeriphClkInit->Sdmmc12ClockSelection = __HAL_RCC_GET_SDMMC12_SOURCE();
1463 /* Get the SPDIFRX clock source --------------------------------------------*/
1464 PeriphClkInit->SpdifrxClockSelection = __HAL_RCC_GET_SPDIFRX_SOURCE();
1465 /* Get the SPI1 clock source -----------------------------------------------*/
1466 PeriphClkInit->Spi1ClockSelection = __HAL_RCC_GET_SPI1_SOURCE();
1467 /* Get the SPI2/SPI3 clock source ------------------------------------------*/
1468 PeriphClkInit->Spi23ClockSelection = __HAL_RCC_GET_SPI23_SOURCE();
1469 /* Get the SPI4/SPI5 clock source ------------------------------------------*/
1470 PeriphClkInit->Spi45ClockSelection = __HAL_RCC_GET_SPI45_SOURCE();
1471 /* Get the SPI6 clock source -----------------------------------------------*/
1472 PeriphClkInit->Spi6ClockSelection = __HAL_RCC_GET_SPI6_SOURCE();
1473 /* Get the TIM Prescaler configuration -------------------------------------*/
1474 if ((RCC->CFGR & RCC_CFGR_TIMPRE) == 0U)
1475 {
1476 PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DISABLE;
1477 }
1478 else
1479 {
1480 PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ENABLE;
1481 }
1482 /* Get the USART1 configuration --------------------------------------------*/
1483 PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();
1484 /* Get the USART2/USART3/UART4/UART5/UART7/UART8 clock source --------------*/
1485 PeriphClkInit->Usart234578ClockSelection = __HAL_RCC_GET_USART234578_SOURCE();
1486 /* Get the USBPHYC clock source --------------------------------------------*/
1487 PeriphClkInit->UsbPhycClockSelection = __HAL_RCC_GET_USBPHYC_SOURCE();
1488 /* Get the USB OTG FS clock source -----------------------------------------*/
1489 PeriphClkInit->UsbOtgFsClockSelection = __HAL_RCC_GET_USBOTGFS_SOURCE();
1490 }
1491
1492 /**
1493 * @brief Return the peripheral clock frequency for a given peripheral (SAI..)
1494 * @note Return 0 if peripheral clock identifier not managed by this API or
1495 * if the selected clock source is not enabled (HSI, PLLs clock output..)
1496 * @param PeriphClk: Peripheral clock identifier
1497 * This parameter can be one of the following values:
1498 * @arg RCC_PERIPHCLK_FMC : FMC peripheral clock
1499 * @arg RCC_PERIPHCLK_XSPI1 : Xspi1 peripheral clock
1500 * @arg RCC_PERIPHCLK_XSPI2 : Xspi2 peripheral clock
1501 * @arg RCC_PERIPHCLK_CKPER : CKPER peripheral clock
1502 * @arg RCC_PERIPHCLK_ADC : ADC peripheral clock
1503 * @arg RCC_PERIPHCLK_ADF1 : ADF1 peripheral clock
1504 * @arg RCC_PERIPHCLK_CEC : CEC peripheral clock
1505 * @arg RCC_PERIPHCLK_ETH1REF : ETH1REF peripheral clock
1506 * @arg RCC_PERIPHCLK_ETH1PHY : ETH1PHY peripheral clock
1507 * @arg RCC_PERIPHCLK_FDCAN : FDCAN peripheral clock
1508 * @arg RCC_PERIPHCLK_I2C23 : I2C2/I2C3 peripheral clock
1509 * @arg RCC_PERIPHCLK_I2C1_I3C1 : I2C1/I3C1 peripheral clock
1510 * @arg RCC_PERIPHCLK_LPTIM1 : LPTIM1 peripheral clock
1511 * @arg RCC_PERIPHCLK_LPTIM23 : LPTIM23 peripheral clock
1512 * @arg RCC_PERIPHCLK_LPTIM45 : LPTIM45 peripheral clock
1513 * @arg RCC_PERIPHCLK_LPUART1 : LPUART1 peripheral clock
1514 * @arg RCC_PERIPHCLK_LTDC : LTDC peripheral clock
1515 * @arg RCC_PERIPHCLK_PSSI : PSSI peripheral clock
1516 * @arg RCC_PERIPHCLK_RTC : RTC peripheral clock
1517 * @arg RCC_PERIPHCLK_SAI1 : SAI1 peripheral clock
1518 * @arg RCC_PERIPHCLK_SAI2 : SAI2 peripheral clock
1519 * @arg RCC_PERIPHCLK_SDMMC12 : SDMMC12 peripheral clock
1520 * @arg RCC_PERIPHCLK_SPDIFRX : SPDIFRX peripheral clock
1521 * @arg RCC_PERIPHCLK_SPI1 : SPI1 peripheral clock
1522 * @arg RCC_PERIPHCLK_SPI23 : SPI2/SPI3 peripheral clock
1523 * @arg RCC_PERIPHCLK_SPI45 : SPI4/SPI5 peripheral clock
1524 * @arg RCC_PERIPHCLK_SPI6 : SPI6 peripheral clock
1525 * @arg RCC_PERIPHCLK_USART1 : USART1 peripheral clock
1526 * @arg RCC_PERIPHCLK_USART234578 : USART2/3/5/7/8 peripheral clock
1527 * @arg RCC_PERIPHCLK_USBOTGFS : USBOTGFS peripheral clock
1528 * @retval Frequency in KHz
1529 */
HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)1530 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
1531 {
1532 uint32_t frequency = 0; /* Set to 0 for returned value if no source clock */
1533 uint32_t clocksource;
1534 uint32_t ethclocksource;
1535 uint32_t prescaler;
1536
1537 switch (PeriphClk)
1538 {
1539 case RCC_PERIPHCLK_FMC:
1540 clocksource = __HAL_RCC_GET_FMC_SOURCE();
1541
1542 switch (clocksource)
1543 {
1544 case RCC_FMCCLKSOURCE_HCLK: /* HCLK is the clock source for FMC kernel peripheral clock */
1545 frequency = HAL_RCC_GetHCLKFreq();
1546 break;
1547 case RCC_FMCCLKSOURCE_PLL1Q: /* PLL1 'Q' is the clock source for FMC kernel peripheral clock */
1548 if (__HAL_RCC_GET_PLL1CLKOUT_CONFIG(RCC_PLL_QCLK) != 0U)
1549 {
1550 frequency = HAL_RCC_GetPLL1QFreq();
1551 }
1552 break;
1553 case RCC_FMCCLKSOURCE_PLL2R: /* PLL2 'R' is the clock source for FMC kernel peripheral clock */
1554 if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_RCLK) != 0U)
1555 {
1556 frequency = HAL_RCC_GetPLL2RFreq();
1557 }
1558 break;
1559 case RCC_FMCCLKSOURCE_HSI: /* HSI is the clock source for FMC kernel peripheral clock */
1560 if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
1561 {
1562 if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0U)
1563 {
1564 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
1565 }
1566 else
1567 {
1568 /* Can't retrieve HSIDIV value */
1569 }
1570 }
1571 break;
1572 case RCC_FMCCLKSOURCE_HCLK_DIV4: /* HCLK/4 is the clock source for FMC kernel peripheral clock */
1573 frequency = (HAL_RCC_GetHCLKFreq() / 4U);
1574 break;
1575 default:
1576 /* Nothing to do, frequency is by default set to 0 */
1577 break;
1578 }
1579 break;
1580
1581 case RCC_PERIPHCLK_XSPI1:
1582 clocksource = __HAL_RCC_GET_XSPI1_SOURCE();
1583
1584 switch (clocksource)
1585 {
1586 case RCC_XSPI1CLKSOURCE_HCLK: /* HCLK is the clock source for XSPI1 kernel peripheral clock */
1587 frequency = HAL_RCC_GetHCLKFreq();
1588 break;
1589 case RCC_XSPI1CLKSOURCE_PLL2S: /* PLL2 'S' is the clock source for XSPI1 kernel peripheral clock */
1590 if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_SCLK) != 0U)
1591 {
1592 frequency = HAL_RCC_GetPLL2SFreq();
1593 }
1594 break;
1595 case RCC_XSPI1CLKSOURCE_PLL2T: /* PLL2 'T' is the clock source for XSPI1 kernel peripheral clock */
1596 if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_TCLK) != 0U)
1597 {
1598 frequency = HAL_RCC_GetPLL2TFreq();
1599 }
1600 break;
1601 case RCC_XSPI1CLKSOURCE_HCLK_DIV4: /* HCLK/4 is the clock source for XSPI1 kernel peripheral clock */
1602 frequency = (HAL_RCC_GetHCLKFreq() / 4U);
1603 break;
1604 default:
1605 /* Nothing to do, frequency is by default set to 0 */
1606 break;
1607 }
1608 break;
1609
1610 case RCC_PERIPHCLK_XSPI2:
1611 clocksource = __HAL_RCC_GET_XSPI2_SOURCE();
1612
1613 switch (clocksource)
1614 {
1615 case RCC_XSPI2CLKSOURCE_HCLK: /* HCLK is the clock source for XSPI2 kernel peripheral clock */
1616 frequency = HAL_RCC_GetHCLKFreq();
1617 break;
1618 case RCC_XSPI2CLKSOURCE_PLL2S: /* PLL2 'S' is the clock source for XSPI2 kernel peripheral clock */
1619 if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_SCLK) != 0U)
1620 {
1621 frequency = HAL_RCC_GetPLL2SFreq();
1622 }
1623 break;
1624 case RCC_XSPI2CLKSOURCE_PLL2T: /* PLL2 'T' is the clock source for XSPI2 kernel peripheral clock */
1625 if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_TCLK) != 0U)
1626 {
1627 frequency = HAL_RCC_GetPLL2TFreq();
1628 }
1629 break;
1630 case RCC_XSPI2CLKSOURCE_HCLK_DIV4: /* HCLK/4 is the clock source for XSPI2 kernel peripheral clock */
1631 frequency = (HAL_RCC_GetHCLKFreq() / 4U);
1632 break;
1633 default:
1634 /* Nothing to do, frequency is by default set to 0 */
1635 break;
1636 }
1637 break;
1638
1639 case RCC_PERIPHCLK_CKPER:
1640 clocksource = __HAL_RCC_GET_CLKP_SOURCE();
1641
1642 switch (clocksource)
1643 {
1644 case RCC_CLKPSOURCE_HSI: /* HSI is the clock source for CKPER */
1645 if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
1646 {
1647 if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0U)
1648 {
1649 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
1650 }
1651 else
1652 {
1653 /* Can't retrieve HSIDIV value */
1654 }
1655 }
1656 break;
1657 case RCC_CLKPSOURCE_CSI: /* CSI is the clock source for CKPER */
1658 if (READ_BIT(RCC->CR, RCC_CR_CSIRDY) != 0U)
1659 {
1660 frequency = CSI_VALUE;
1661 }
1662 break;
1663 case RCC_CLKPSOURCE_HSE: /* HSE is the clock source for CKPER */
1664 if (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
1665 {
1666 frequency = HSE_VALUE;
1667 }
1668 break;
1669
1670 default:
1671 /* Nothing to do, frequency is by default set to 0 */
1672 break;
1673 }
1674 break;
1675
1676 case RCC_PERIPHCLK_ADC:
1677 clocksource = __HAL_RCC_GET_ADC_SOURCE();
1678
1679 switch (clocksource)
1680 {
1681 case RCC_ADCCLKSOURCE_PLL2P: /* PLL2 'P' is the clock source for ADC */
1682 if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_PCLK) != 0U)
1683 {
1684 frequency = HAL_RCC_GetPLL2PFreq();
1685 }
1686 break;
1687 case RCC_ADCCLKSOURCE_PLL3R: /* PLL3 'R' is the clock source for ADC */
1688 if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_RCLK) != 0U)
1689 {
1690 frequency = HAL_RCC_GetPLL3RFreq();
1691 }
1692 break;
1693 case RCC_ADCCLKSOURCE_CLKP: /* CKPER is the clock source for ADC */
1694 frequency = RCC_GetCLKPFreq();
1695 break;
1696 default:
1697 /* Nothing to do, frequency is by default set to 0 */
1698 break;
1699 }
1700 break;
1701
1702 case RCC_PERIPHCLK_ADF1:
1703 clocksource = __HAL_RCC_GET_ADF1_SOURCE();
1704
1705 switch (clocksource)
1706 {
1707 case RCC_ADF1CLKSOURCE_HCLK: /* HCLK is the clock source for ADF1 */
1708 frequency = HAL_RCC_GetHCLKFreq();
1709 break;
1710 case RCC_ADF1CLKSOURCE_PLL2P: /* PLL2 'P' is the clock source for ADF1 */
1711 if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_PCLK) != 0U)
1712 {
1713 frequency = HAL_RCC_GetPLL2PFreq();
1714 }
1715 break;
1716 case RCC_ADF1CLKSOURCE_PLL3P: /* PLL3 'P' is the clock source for ADF1 */
1717 if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_PCLK) != 0U)
1718 {
1719 frequency = HAL_RCC_GetPLL3PFreq();
1720 }
1721 break;
1722 case RCC_ADF1CLKSOURCE_PIN: /* External I2S_CKIN is used as clock source for ADF1 */
1723 frequency = EXTERNAL_CLOCK_VALUE;
1724 break;
1725 case RCC_ADF1CLKSOURCE_CSI: /* CSI is the clock source for ADF1 */
1726 if (READ_BIT(RCC->CR, RCC_CR_CSIRDY) != 0U)
1727 {
1728 frequency = CSI_VALUE;
1729 }
1730 break;
1731 case RCC_ADF1CLKSOURCE_HSI: /* HSI is the clock source for ADF1 */
1732 if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
1733 {
1734 if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0U)
1735 {
1736 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
1737 }
1738 else
1739 {
1740 /* Can't retrieve HSIDIV value */
1741 }
1742 }
1743 break;
1744 default:
1745 /* Nothing to do, frequency is by default set to 0 */
1746 break;
1747 }
1748 break;
1749
1750 case RCC_PERIPHCLK_CEC:
1751 clocksource = __HAL_RCC_GET_CEC_SOURCE();
1752
1753 switch (clocksource)
1754 {
1755 case RCC_CECCLKSOURCE_LSE: /* LSE is the clock source for CEC */
1756 if (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
1757 {
1758 frequency = LSE_VALUE;
1759 }
1760 break;
1761 case RCC_CECCLKSOURCE_LSI: /* LSI is the clock source for CEC */
1762 if (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
1763 {
1764 frequency = LSI_VALUE;
1765 }
1766 break;
1767 case RCC_CECCLKSOURCE_CSI: /* CSI is the clock source for CEC */
1768 if (READ_BIT(RCC->CR, RCC_CR_CSIRDY) != 0U)
1769 {
1770 frequency = CSI_VALUE;
1771 }
1772 break;
1773 default:
1774 /* Nothing to do, frequency is by default set to 0 */
1775 break;
1776 }
1777 break;
1778
1779 case RCC_PERIPHCLK_ETH1REF:
1780 clocksource = __HAL_RCC_GET_ETH1REF_SOURCE();
1781
1782 switch (clocksource)
1783 {
1784 case RCC_ETH1REFCLKSOURCE_PHY: /* PHY is the clock source for ETH1REF */
1785 /* Can't retrieve this source's frequency, it is by default set to 0 */
1786 break;
1787 case RCC_ETH1REFCLKSOURCE_HSE: /* HSE is the clock source for ETH1REF */
1788 if (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
1789 {
1790 frequency = HSE_VALUE;
1791 }
1792 break;
1793 case RCC_ETH1REFCLKSOURCE_ETH: /* ETH is the clock source for ETH1REF */
1794 ethclocksource = __HAL_RCC_GET_ETH1PHY_SOURCE();
1795
1796 switch (ethclocksource)
1797 {
1798 case RCC_ETH1PHYCLKSOURCE_HSE:
1799 if (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
1800 {
1801 frequency = HSE_VALUE;
1802 }
1803 break;
1804 case RCC_ETH1PHYCLKSOURCE_PLL3S:
1805 if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_SCLK) != 0U)
1806 {
1807 frequency = HAL_RCC_GetPLL3SFreq();
1808 }
1809 break;
1810 default:
1811 /* Nothing to do, frequency is by default set to 0 */
1812 break;
1813 }
1814 break;
1815 default:
1816 /* Nothing to do, frequency is by default set to 0 */
1817 break;
1818 }
1819 break;
1820
1821 case RCC_PERIPHCLK_ETH1PHY:
1822 clocksource = __HAL_RCC_GET_ETH1PHY_SOURCE();
1823
1824 switch (clocksource)
1825 {
1826 case RCC_ETH1PHYCLKSOURCE_HSE:
1827 if (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
1828 {
1829 frequency = HSE_VALUE;
1830 }
1831 break;
1832 case RCC_ETH1PHYCLKSOURCE_PLL3S:
1833 if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_SCLK) != 0U)
1834 {
1835 frequency = HAL_RCC_GetPLL3SFreq();
1836 }
1837 break;
1838 default:
1839 /* Nothing to do, frequency is by default set to 0 */
1840 break;
1841 }
1842 break;
1843
1844 case RCC_PERIPHCLK_FDCAN:
1845 clocksource = __HAL_RCC_GET_FDCAN_SOURCE();
1846
1847 switch (clocksource)
1848 {
1849 case RCC_FDCANCLKSOURCE_HSE: /*!< HSE is the clock source for FDCAN */
1850 if (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
1851 {
1852 frequency = HSE_VALUE;
1853 }
1854 break;
1855 case RCC_FDCANCLKSOURCE_PLL1Q: /*!< PLL1 'Q' ois the clock source for FDCAN */
1856 if (__HAL_RCC_GET_PLL1CLKOUT_CONFIG(RCC_PLL_QCLK) != 0U)
1857 {
1858 frequency = HAL_RCC_GetPLL1QFreq();
1859 }
1860 break;
1861 case RCC_FDCANCLKSOURCE_PLL2P: /*!< PLL2 'P' is the clock source for FDCAN */
1862 if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_PCLK) != 0U)
1863 {
1864 frequency = HAL_RCC_GetPLL2PFreq();
1865 }
1866 break;
1867 default:
1868 /* Nothing to do, frequency is by default set to 0 */
1869 break;
1870 }
1871 break;
1872
1873 case RCC_PERIPHCLK_I2C23:
1874 clocksource = __HAL_RCC_GET_I2C23_SOURCE();
1875
1876 switch (clocksource)
1877 {
1878 case RCC_I2C23CLKSOURCE_PCLK1: /*!< PCLK1 is the clock source for I2C23 */
1879 frequency = HAL_RCC_GetPCLK1Freq();
1880 break;
1881 case RCC_I2C23CLKSOURCE_PLL3R: /*!< PLL3R is the clock source for I2C23 */
1882 if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_RCLK) != 0U)
1883 {
1884 frequency = HAL_RCC_GetPLL3RFreq();
1885 }
1886 break;
1887 case RCC_I2C23CLKSOURCE_HSI: /*!< HSI is the clock source for I2C23 */
1888 if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
1889 {
1890 if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0U)
1891 {
1892 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
1893 }
1894 else
1895 {
1896 /* Can't retrieve HSIDIV value */
1897 }
1898 }
1899 break;
1900 case RCC_I2C23CLKSOURCE_CSI: /*!< CSI is the clock source for I2C23 */
1901 if (READ_BIT(RCC->CR, RCC_CR_CSIRDY) != 0U)
1902 {
1903 frequency = CSI_VALUE;
1904 }
1905 break;
1906 default:
1907 /* Nothing to do, frequency is by default set to 0 */
1908 break;
1909 }
1910 break;
1911
1912 case RCC_PERIPHCLK_I2C1_I3C1:
1913 clocksource = __HAL_RCC_GET_I2C1_I3C1_SOURCE();
1914
1915 switch (clocksource)
1916 {
1917 case RCC_I2C1_I3C1CLKSOURCE_PCLK1: /*!< PCLK1 is the clock source for I2C1/I3C1 */
1918 frequency = HAL_RCC_GetPCLK1Freq();
1919 break;
1920 case RCC_I2C1_I3C1CLKSOURCE_PLL3R: /*!< PLL3 'R' is the clock source for I2C1/I3C1 */
1921 if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_RCLK) != 0U)
1922 {
1923 frequency = HAL_RCC_GetPLL3RFreq();
1924 }
1925 break;
1926 case RCC_I2C1_I3C1CLKSOURCE_HSI: /*!< HSI is the clock source for I2C1/I3C1 */
1927 if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
1928 {
1929 if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0U)
1930 {
1931 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
1932 }
1933 else
1934 {
1935 /* Can't retrieve HSIDIV value */
1936 }
1937 }
1938 break;
1939 case RCC_I2C1_I3C1CLKSOURCE_CSI: /*!< CSI is the clock source for I2C1/I3C1 */
1940 if (READ_BIT(RCC->CR, RCC_CR_CSIRDY) != 0U)
1941 {
1942 frequency = CSI_VALUE;
1943 }
1944 break;
1945 default:
1946 /* Nothing to do, frequency is by default set to 0 */
1947 break;
1948 }
1949 break;
1950
1951 case RCC_PERIPHCLK_LPTIM1:
1952 clocksource = __HAL_RCC_GET_LPTIM1_SOURCE();
1953
1954 switch (clocksource)
1955 {
1956 case RCC_LPTIM1CLKSOURCE_PCLK1: /* PCLK1 is the clock source for LPTIM1 */
1957 frequency = HAL_RCC_GetPCLK1Freq();
1958 break;
1959 case RCC_LPTIM1CLKSOURCE_PLL2P: /* PLL2 'P' is the clock source for LPTIM1 */
1960 if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_PCLK) != 0U)
1961 {
1962 frequency = HAL_RCC_GetPLL2PFreq();
1963 }
1964 break;
1965 case RCC_LPTIM1CLKSOURCE_PLL3R: /* PLL3 'R' is the clock source for LPTIM1 */
1966 if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_RCLK) != 0U)
1967 {
1968 frequency = HAL_RCC_GetPLL3RFreq();
1969 }
1970 break;
1971 case RCC_LPTIM1CLKSOURCE_LSE: /* LSE is the clock source for LPTIM1 */
1972 if (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
1973 {
1974 frequency = LSE_VALUE;
1975 }
1976 break;
1977 case RCC_LPTIM1CLKSOURCE_LSI: /* LSI is the clock source for LPTIM1 */
1978 if (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
1979 {
1980 frequency = LSI_VALUE;
1981 }
1982 break;
1983 case RCC_LPTIM1CLKSOURCE_CLKP: /* CKPER is the clock source for LPTIM1 */
1984 frequency = RCC_GetCLKPFreq();
1985 break;
1986 default:
1987 /* Nothing to do, frequency is by default set to 0 */
1988 break;
1989 }
1990 break;
1991
1992 case RCC_PERIPHCLK_LPTIM23:
1993 clocksource = __HAL_RCC_GET_LPTIM23_SOURCE();
1994
1995 switch (clocksource)
1996 {
1997 case RCC_LPTIM23CLKSOURCE_PCLK4: /* PCLK4 is the clock source for LPTIM2/LPTIM3 */
1998 frequency = HAL_RCC_GetPCLK4Freq();
1999 break;
2000 case RCC_LPTIM23CLKSOURCE_PLL2P: /* PLL2 'P' is the clock source for LPTIM2/LPTIM3 */
2001 if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_PCLK) != 0U)
2002 {
2003 frequency = HAL_RCC_GetPLL2PFreq();
2004 }
2005 break;
2006 case RCC_LPTIM23CLKSOURCE_PLL3R: /* PLL3 'R' is the clock source for LPTIM2/LPTIM3 */
2007 if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_RCLK) != 0U)
2008 {
2009 frequency = HAL_RCC_GetPLL3RFreq();
2010 }
2011 break;
2012 case RCC_LPTIM23CLKSOURCE_LSE: /* LSE is the clock source for LPTIM2/LPTIM3 */
2013 if (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
2014 {
2015 frequency = LSE_VALUE;
2016 }
2017 break;
2018 case RCC_LPTIM23CLKSOURCE_LSI: /* LSI is the clock source for LPTIM2/LPTIM3 */
2019 if (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
2020 {
2021 frequency = LSI_VALUE;
2022 }
2023 break;
2024 case RCC_LPTIM23CLKSOURCE_CLKP: /* CKPER is the clock source for LPTIM2/LPTIM3 */
2025 frequency = RCC_GetCLKPFreq();
2026 break;
2027 default:
2028 /* Nothing to do, frequency is by default set to 0 */
2029 break;
2030 }
2031 break;
2032
2033 case RCC_PERIPHCLK_LPTIM45:
2034 clocksource = __HAL_RCC_GET_LPTIM45_SOURCE();
2035
2036 switch (clocksource)
2037 {
2038 case RCC_LPTIM45CLKSOURCE_PCLK4: /* PCLK4 is the clock source for LPTIM4/LPTIM5 */
2039 frequency = HAL_RCC_GetPCLK4Freq();
2040 break;
2041 case RCC_LPTIM45CLKSOURCE_PLL2P: /* PLL2 'P' is the clock source for LPTIM4/LPTIM5 */
2042 if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_PCLK) != 0U)
2043 {
2044 frequency = HAL_RCC_GetPLL2PFreq();
2045 }
2046 break;
2047 case RCC_LPTIM45CLKSOURCE_PLL3R: /* PLL3 'R' is the clock source for LPTIM4/LPTIM5 */
2048 if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_RCLK) != 0U)
2049 {
2050 frequency = HAL_RCC_GetPLL3RFreq();
2051 }
2052 break;
2053 case RCC_LPTIM45CLKSOURCE_LSE: /* LSE is the clock source for LPTIM4/LPTIM5 */
2054 if (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
2055 {
2056 frequency = LSE_VALUE;
2057 }
2058 break;
2059 case RCC_LPTIM45CLKSOURCE_LSI: /* LSI is the clock source for LPTIM4/LPTIM5 */
2060 if (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
2061 {
2062 frequency = LSI_VALUE;
2063 }
2064 break;
2065 case RCC_LPTIM45CLKSOURCE_CLKP: /* CKPER is the clock source for LPTIM4/LPTIM5 */
2066 frequency = RCC_GetCLKPFreq();
2067 break;
2068 default:
2069 /* Nothing to do, frequency is by default set to 0 */
2070 break;
2071 }
2072 break;
2073
2074 case RCC_PERIPHCLK_LPUART1:
2075 clocksource = __HAL_RCC_GET_LPUART1_SOURCE();
2076
2077 switch (clocksource)
2078 {
2079 case RCC_LPUART1CLKSOURCE_PCLK4: /*!< PCLK4 is the clock source for LPUART1 */
2080 frequency = HAL_RCC_GetPCLK4Freq();
2081 break;
2082 case RCC_LPUART1CLKSOURCE_PLL2Q: /*!< PLL2 'Q' is the clock source for LPUART1 */
2083 if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_QCLK) != 0U)
2084 {
2085 frequency = HAL_RCC_GetPLL2QFreq();
2086 }
2087 break;
2088 case RCC_LPUART1CLKSOURCE_PLL3Q: /*!< PLL3 'Q' is the clock source for LPUART1 */
2089 if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_QCLK) != 0U)
2090 {
2091 frequency = HAL_RCC_GetPLL3QFreq();
2092 }
2093 break;
2094 case RCC_LPUART1CLKSOURCE_HSI: /*!< HSI is the clock source for LPUART1 */
2095 if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
2096 {
2097 if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0U)
2098 {
2099 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
2100 }
2101 else
2102 {
2103 /* Can't retrieve HSIDIV value */
2104 }
2105 }
2106 break;
2107 case RCC_LPUART1CLKSOURCE_CSI: /*!< CSI is the clock source for LPUART1 */
2108 if (READ_BIT(RCC->CR, RCC_CR_CSIRDY) != 0U)
2109 {
2110 frequency = CSI_VALUE;
2111 }
2112 break;
2113 case RCC_LPUART1CLKSOURCE_LSE: /*!< LSE is the clock source for LPUART1 */
2114 if (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
2115 {
2116 frequency = LSE_VALUE;
2117 }
2118 break;
2119 default:
2120 /* Nothing to do, frequency is by default set to 0 */
2121 break;
2122 }
2123 break;
2124
2125 case RCC_PERIPHCLK_LTDC:
2126 /* Unique PLL3 'R' clock source */
2127 if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_RCLK) != 0U)
2128 {
2129 frequency = HAL_RCC_GetPLL3RFreq();
2130 }
2131 break;
2132
2133 case RCC_PERIPHCLK_PSSI:
2134 clocksource = __HAL_RCC_GET_PSSI_SOURCE();
2135
2136 switch (clocksource)
2137 {
2138 case RCC_PSSICLKSOURCE_PLL3R: /*!< PLL3 'R' is the clock source for PSSI */
2139 if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_RCLK) != 0U)
2140 {
2141 frequency = HAL_RCC_GetPLL3RFreq();
2142 }
2143 break;
2144 case RCC_PSSICLKSOURCE_CLKP: /*!< CLKP is the clock source for PSSI */
2145 frequency = RCC_GetCLKPFreq();
2146 break;
2147 default:
2148 /* Nothing to do, frequency is by default set to 0 */
2149 break;
2150 }
2151 break;
2152
2153 case RCC_PERIPHCLK_RTC:
2154 clocksource = __HAL_RCC_GET_RTC_SOURCE();
2155
2156 switch (clocksource)
2157 {
2158 case RCC_RTCCLKSOURCE_DISABLE:
2159 /* Nothing to do, frequency is by default set to 0 */
2160 break;
2161 case RCC_RTCCLKSOURCE_LSE: /*!< LSE is the clock source for RTC */
2162 if (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
2163 {
2164 frequency = LSE_VALUE;
2165 }
2166 break;
2167 case RCC_RTCCLKSOURCE_LSI: /*!< LSI is the clock source for RTC */
2168 if (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
2169 {
2170 frequency = LSI_VALUE;
2171 }
2172 break;
2173 default:
2174 if (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) /*!< HSE is the clock source for RTC */
2175 {
2176 if (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
2177 {
2178 prescaler = READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) >> RCC_CFGR_RTCPRE_Pos;
2179 if (prescaler > 1U)
2180 {
2181 frequency = HSE_VALUE / prescaler;
2182 }
2183 }
2184 }
2185 else
2186 {
2187 /* Nothing to do, frequency is by default set to 0 */
2188 }
2189 break;
2190 }
2191 break;
2192
2193 case RCC_PERIPHCLK_SAI1:
2194 clocksource = __HAL_RCC_GET_SAI1_SOURCE();
2195
2196 switch (clocksource)
2197 {
2198 case RCC_SAI1CLKSOURCE_PLL1Q: /* PLL1 'Q' is the clock source for SAI1 */
2199 if (__HAL_RCC_GET_PLL1CLKOUT_CONFIG(RCC_PLL_QCLK) != 0U)
2200 {
2201 frequency = HAL_RCC_GetPLL1QFreq();
2202 }
2203 break;
2204 case RCC_SAI1CLKSOURCE_PLL2P: /* PLL2 'P' is the clock source for SAI1 */
2205 if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_PCLK) != 0U)
2206 {
2207 frequency = HAL_RCC_GetPLL2PFreq();
2208 }
2209 break;
2210 case RCC_SAI1CLKSOURCE_PLL3P: /* PLL3 'P' is the clock source for SAI1 */
2211 if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_PCLK) != 0U)
2212 {
2213 frequency = HAL_RCC_GetPLL3PFreq();
2214 }
2215 break;
2216 case RCC_SAI1CLKSOURCE_CLKP: /* CKPER is the clock source for SAI1 */
2217 frequency = RCC_GetCLKPFreq();
2218 break;
2219 case RCC_SAI1CLKSOURCE_PIN: /* External clock is the clock source for SAI1 */
2220 frequency = EXTERNAL_CLOCK_VALUE;
2221 break;
2222 default:
2223 /* Nothing to do, frequency is by default set to 0 */
2224 break;
2225 }
2226 break;
2227
2228 case RCC_PERIPHCLK_SAI2:
2229 clocksource = __HAL_RCC_GET_SAI2_SOURCE();
2230
2231 switch (clocksource)
2232 {
2233 case RCC_SAI2CLKSOURCE_PLL1Q: /* PLL1 'Q' is the clock source for SAI2 */
2234 if (__HAL_RCC_GET_PLL1CLKOUT_CONFIG(RCC_PLL_QCLK) != 0U)
2235 {
2236 frequency = HAL_RCC_GetPLL1QFreq();
2237 }
2238 break;
2239 case RCC_SAI2CLKSOURCE_PLL2P: /* PLL2 'P' is the clock source for SAI2 */
2240 if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_PCLK) != 0U)
2241 {
2242 frequency = HAL_RCC_GetPLL2PFreq();
2243 }
2244 break;
2245 case RCC_SAI2CLKSOURCE_PLL3P: /* PLL3 'P' is the clock source for SAI2 */
2246 if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_PCLK) != 0U)
2247 {
2248 frequency = HAL_RCC_GetPLL3PFreq();
2249 }
2250 break;
2251 case RCC_SAI2CLKSOURCE_CLKP: /* CKPER is the clock source for SAI2 */
2252 frequency = RCC_GetCLKPFreq();
2253 break;
2254 case RCC_SAI2CLKSOURCE_SPDIF:
2255 /* Can't retrieve this source's frequency, it is by default set to 0 */
2256 break;
2257 case RCC_SAI2CLKSOURCE_PIN: /* External clock is the clock source for SAI2 */
2258 frequency = EXTERNAL_CLOCK_VALUE;
2259 break;
2260 default:
2261 /* Nothing to do, frequency is by default set to 0 */
2262 break;
2263 }
2264 break;
2265
2266 case RCC_PERIPHCLK_SDMMC12: /* SDMMC1 and SDMMC2 */
2267
2268 clocksource = __HAL_RCC_GET_SDMMC12_SOURCE();
2269
2270 if (clocksource ==
2271 RCC_SDMMC12CLKSOURCE_PLL2S) /* PLL2 'S' is the clock source for SDMMC1 and SDMMC2 kernel peripheral clock */
2272 {
2273 if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_SCLK) != 0U)
2274 {
2275 frequency = HAL_RCC_GetPLL2SFreq();
2276 }
2277 }
2278 else /* PLL2 'T' is the clock source for SDMMC1 and SDMMC2 kernel peripheral clock */
2279 {
2280 if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_TCLK) != 0U)
2281 {
2282 frequency = HAL_RCC_GetPLL2TFreq();
2283 }
2284 }
2285 break;
2286
2287 case RCC_PERIPHCLK_SPDIFRX:
2288 clocksource = __HAL_RCC_GET_SPDIFRX_SOURCE();
2289
2290 switch (clocksource)
2291 {
2292 case RCC_SPDIFRXCLKSOURCE_PLL1Q: /* PLL1 'Q' is the clock source for SPDIFRX */
2293 if (__HAL_RCC_GET_PLL1CLKOUT_CONFIG(RCC_PLL_QCLK) != 0U)
2294 {
2295 frequency = HAL_RCC_GetPLL1QFreq();
2296 }
2297 break;
2298 case RCC_SPDIFRXCLKSOURCE_PLL2R: /* PLL2 'R' is the clock source for SPDIFRX */
2299 if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_RCLK) != 0U)
2300 {
2301 frequency = HAL_RCC_GetPLL2RFreq();
2302 }
2303 break;
2304 case RCC_SPDIFRXCLKSOURCE_PLL3R: /* PLL3 'R' is the clock source for SPDIFRX */
2305 if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_RCLK) != 0U)
2306 {
2307 frequency = HAL_RCC_GetPLL3RFreq();
2308 }
2309 break;
2310 case RCC_SPDIFRXCLKSOURCE_HSI: /* HSI is the clock source for SPDIFRX */
2311 if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
2312 {
2313 if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0U)
2314 {
2315 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
2316 }
2317 else
2318 {
2319 /* Can't retrieve HSIDIV value */
2320 }
2321 }
2322 break;
2323 default:
2324 /* Nothing to do, frequency is by default set to 0 */
2325 break;
2326 }
2327 break;
2328
2329 case RCC_PERIPHCLK_SPI1:
2330 clocksource = __HAL_RCC_GET_SPI1_SOURCE();
2331
2332 switch (clocksource)
2333 {
2334 case RCC_SPI1CLKSOURCE_PLL1Q: /* PLL1 'Q' is the clock source for SPI1 */
2335 if (__HAL_RCC_GET_PLL1CLKOUT_CONFIG(RCC_PLL_QCLK) != 0U)
2336 {
2337 frequency = HAL_RCC_GetPLL1QFreq();
2338 }
2339 break;
2340 case RCC_SPI1CLKSOURCE_PLL2P: /* PLL2 'P' is the clock source for SPI1 */
2341 if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_PCLK) != 0U)
2342 {
2343 frequency = HAL_RCC_GetPLL2PFreq();
2344 }
2345 break;
2346 case RCC_SPI1CLKSOURCE_PLL3P: /* PLL3 'P' is the clock source for SPI1 */
2347 if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_PCLK) != 0U)
2348 {
2349 frequency = HAL_RCC_GetPLL3PFreq();
2350 }
2351 break;
2352 case RCC_SPI1CLKSOURCE_CLKP: /* CKPER is the clock source for SPI1 */
2353 frequency = RCC_GetCLKPFreq();
2354 break;
2355 case RCC_SPI1CLKSOURCE_PIN: /* External I2S_CKIN is used as clock source for SPI1 */
2356 frequency = EXTERNAL_CLOCK_VALUE;
2357 break;
2358 default:
2359 /* Nothing to do, frequency is by default set to 0 */
2360 break;
2361 }
2362 break;
2363
2364 case RCC_PERIPHCLK_SPI23:
2365 clocksource = __HAL_RCC_GET_SPI23_SOURCE();
2366
2367 switch (clocksource)
2368 {
2369 case RCC_SPI23CLKSOURCE_PLL1Q: /* PLL1 'Q' is the clock source for SPI2/SPI3 */
2370 if (__HAL_RCC_GET_PLL1CLKOUT_CONFIG(RCC_PLL_QCLK) != 0U)
2371 {
2372 frequency = HAL_RCC_GetPLL1QFreq();
2373 }
2374 break;
2375 case RCC_SPI23CLKSOURCE_PLL2P: /* PLL2 'P' is the clock source for SPI2/SPI3 */
2376 if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_PCLK) != 0U)
2377 {
2378 frequency = HAL_RCC_GetPLL2PFreq();
2379 }
2380 break;
2381 case RCC_SPI23CLKSOURCE_PLL3P: /* PLL3 'P' is the clock source for SPI2/SPI3 */
2382 if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_PCLK) != 0U)
2383 {
2384 frequency = HAL_RCC_GetPLL3PFreq();
2385 }
2386 break;
2387 case RCC_SPI23CLKSOURCE_CLKP: /* CKPER is the clock source for SPI2/SPI3 */
2388 frequency = RCC_GetCLKPFreq();
2389 break;
2390 case RCC_SPI23CLKSOURCE_PIN: /* External I2S_CKIN is used as clock source for SPI2/SPI3 */
2391 frequency = EXTERNAL_CLOCK_VALUE;
2392 break;
2393 default:
2394 /* Nothing to do, frequency is by default set to 0 */
2395 break;
2396 }
2397 break;
2398
2399 case RCC_PERIPHCLK_SPI45:
2400 clocksource = __HAL_RCC_GET_SPI45_SOURCE();
2401
2402 switch (clocksource)
2403 {
2404 case RCC_SPI45CLKSOURCE_PCLK2: /* PCLK2 is the clock source for SPI4/SPI5 */
2405 frequency = HAL_RCC_GetPCLK2Freq();
2406 break;
2407 case RCC_SPI45CLKSOURCE_PLL2Q: /* PLL2 'Q' is the clock source for SPI4/SPI5 */
2408 if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_QCLK) != 0U)
2409 {
2410 frequency = HAL_RCC_GetPLL2QFreq();
2411 }
2412 break;
2413 case RCC_SPI45CLKSOURCE_PLL3Q: /* PLL3 'Q' is the clock source for SPI4/SPI5 */
2414 if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_QCLK) != 0U)
2415 {
2416 frequency = HAL_RCC_GetPLL3QFreq();
2417 }
2418 break;
2419 case RCC_SPI45CLKSOURCE_HSI: /* HSI is the clock source for SPI4/SPI5 */
2420 if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
2421 {
2422 if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0U)
2423 {
2424 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
2425 }
2426 else
2427 {
2428 /* Can't retrieve HSIDIV value */
2429 }
2430 }
2431 break;
2432 case RCC_SPI45CLKSOURCE_CSI: /* CSI is the clock source for SPI4/SPI5 */
2433 if (READ_BIT(RCC->CR, RCC_CR_CSIRDY) != 0U)
2434 {
2435 frequency = CSI_VALUE;
2436 }
2437 break;
2438 case RCC_SPI45CLKSOURCE_HSE: /* HSE is the clock source for SPI4/SPI5 */
2439 if (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
2440 {
2441 frequency = HSE_VALUE;
2442 }
2443 break;
2444 default:
2445 /* Nothing to do, frequency is by default set to 0 */
2446 break;
2447 }
2448 break;
2449
2450 case RCC_PERIPHCLK_SPI6:
2451 clocksource = __HAL_RCC_GET_SPI6_SOURCE();
2452
2453 switch (clocksource)
2454 {
2455 case RCC_SPI6CLKSOURCE_PCLK4: /* PCLK4 is the clock source for SPI6 */
2456 frequency = HAL_RCC_GetPCLK4Freq();
2457 break;
2458 case RCC_SPI6CLKSOURCE_PLL2Q: /* PLL2 'Q' is the clock source for SPI6 */
2459 if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_QCLK) != 0U)
2460 {
2461 frequency = HAL_RCC_GetPLL2QFreq();
2462 }
2463 break;
2464 case RCC_SPI6CLKSOURCE_PLL3Q: /* PLL3 'Q' is the clock source for SPI6 */
2465 if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_QCLK) != 0U)
2466 {
2467 frequency = HAL_RCC_GetPLL3QFreq();
2468 }
2469 break;
2470 case RCC_SPI6CLKSOURCE_HSI: /* HSI is the clock source for SPI6 */
2471 if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
2472 {
2473 if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0U)
2474 {
2475 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
2476 }
2477 else
2478 {
2479 /* Can't retrieve HSIDIV value */
2480 }
2481 }
2482 break;
2483 case RCC_SPI6CLKSOURCE_CSI: /* CSI is the clock source for SPI6 */
2484 if (READ_BIT(RCC->CR, RCC_CR_CSIRDY) != 0U)
2485 {
2486 frequency = CSI_VALUE;
2487 }
2488 break;
2489 case RCC_SPI6CLKSOURCE_HSE: /* HSE is the clock source for SPI6 */
2490 if (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
2491 {
2492 frequency = HSE_VALUE;
2493 }
2494 break;
2495 default:
2496 /* Nothing to do, frequency is by default set to 0 */
2497 break;
2498 }
2499 break;
2500
2501 case RCC_PERIPHCLK_USART1:
2502 clocksource = __HAL_RCC_GET_USART1_SOURCE();
2503
2504 switch (clocksource)
2505 {
2506 case RCC_USART1CLKSOURCE_PCLK2: /*!< PCLK2 is the clock source for USART1 */
2507 frequency = HAL_RCC_GetPCLK2Freq();
2508 break;
2509 case RCC_USART1CLKSOURCE_PLL2Q: /*!< PLL2 'Q' is the clock source for USART1 */
2510 if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_QCLK) != 0U)
2511 {
2512 frequency = HAL_RCC_GetPLL2QFreq();
2513 }
2514 break;
2515 case RCC_USART1CLKSOURCE_PLL3Q: /*!< PLL3 'Q' is the clock source for USART1 */
2516 if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_QCLK) != 0U)
2517 {
2518 frequency = HAL_RCC_GetPLL3QFreq();
2519 }
2520 break;
2521 case RCC_USART1CLKSOURCE_HSI: /*!< HSI is the clock source for USART1 */
2522 if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
2523 {
2524 if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0U)
2525 {
2526 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
2527 }
2528 else
2529 {
2530 /* Can't retrieve HSIDIV value */
2531 }
2532 }
2533 break;
2534 case RCC_USART1CLKSOURCE_CSI: /*!< CSI is the clock source for USART1 */
2535 if (READ_BIT(RCC->CR, RCC_CR_CSIRDY) != 0U)
2536 {
2537 frequency = CSI_VALUE;
2538 }
2539 break;
2540 case RCC_USART1CLKSOURCE_LSE: /*!< LSE is the clock source for USART1 */
2541 if (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
2542 {
2543 frequency = LSE_VALUE;
2544 }
2545 break;
2546 default:
2547 /* Nothing to do, frequency is by default set to 0 */
2548 break;
2549 }
2550 break;
2551
2552 case RCC_PERIPHCLK_USART234578:
2553 clocksource = __HAL_RCC_GET_USART234578_SOURCE();
2554
2555 switch (clocksource)
2556 {
2557 case RCC_USART234578CLKSOURCE_PCLK1: /*!< PCLK2 is the clock source for USART234578 */
2558 frequency = HAL_RCC_GetPCLK1Freq();
2559 break;
2560 case RCC_USART234578CLKSOURCE_PLL2Q: /*!< PLL2 'Q' is the clock source for USART234578 */
2561 if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_QCLK) != 0U)
2562 {
2563 frequency = HAL_RCC_GetPLL2QFreq();
2564 }
2565 break;
2566 case RCC_USART234578CLKSOURCE_PLL3Q: /*!< PLL3 'Q' is the clock source for USART234578 */
2567 if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_QCLK) != 0U)
2568 {
2569 frequency = HAL_RCC_GetPLL3QFreq();
2570 }
2571 break;
2572 case RCC_USART234578CLKSOURCE_HSI: /*!< HSI is the clock source for USART234578 */
2573 if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
2574 {
2575 if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0U)
2576 {
2577 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
2578 }
2579 else
2580 {
2581 /* Can't retrieve HSIDIV value */
2582 }
2583 }
2584 break;
2585 case RCC_USART234578CLKSOURCE_CSI: /*!< CSI is the clock source for USART234578 */
2586 if (READ_BIT(RCC->CR, RCC_CR_CSIRDY) != 0U)
2587 {
2588 frequency = CSI_VALUE;
2589 }
2590 break;
2591 case RCC_USART234578CLKSOURCE_LSE: /*!< LSE is the clock source for USART234578 */
2592 if (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
2593 {
2594 frequency = LSE_VALUE;
2595 }
2596 break;
2597 default:
2598 /* Nothing to do, frequency is by default set to 0 */
2599 break;
2600 }
2601 break;
2602
2603 case RCC_PERIPHCLK_USBPHYC:
2604 clocksource = __HAL_RCC_GET_USBPHYC_SOURCE();
2605
2606 switch (clocksource)
2607 {
2608 case RCC_USBPHYCCLKSOURCE_HSE: /*!< HSE is the clock source for USBPHYC */
2609 if (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
2610 {
2611 frequency = HSE_VALUE;
2612 }
2613 break;
2614 case RCC_USBPHYCCLKSOURCE_HSE_DIV2: /*!< HSE/2 is the clock source for USBPHYC */
2615 if (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
2616 {
2617 frequency = (HSE_VALUE >> 1UL);
2618 }
2619 break;
2620 case RCC_USBPHYCCLKSOURCE_PLL3Q: /*!< PLL3Q is the clock source for USBPHYC */
2621 if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_QCLK) != 0U)
2622 {
2623 frequency = HAL_RCC_GetPLL3QFreq();
2624 }
2625 break;
2626 default:
2627 /* Nothing to do, frequency is by default set to 0 */
2628 break;
2629 }
2630 break;
2631
2632 case RCC_PERIPHCLK_USBOTGFS:
2633 clocksource = __HAL_RCC_GET_USBOTGFS_SOURCE();
2634
2635 switch (clocksource)
2636 {
2637 case RCC_USBOTGFSCLKSOURCE_HSI48: /*!< HSI48 is the clock source for USBOTGFS */
2638 if (READ_BIT(RCC->CR, RCC_CR_HSI48RDY) != 0U)
2639 {
2640 frequency = HSI48_VALUE;
2641 }
2642 break;
2643 case RCC_USBOTGFSCLKSOURCE_PLL3Q: /*!< PLL3Q is the clock source for USBOTGFS */
2644 if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_QCLK) != 0U)
2645 {
2646 frequency = HAL_RCC_GetPLL3QFreq();
2647 }
2648 break;
2649 case RCC_USBOTGFSCLKSOURCE_HSE: /*!< HSE is the clock source for USBOTGFS */
2650 if (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
2651 {
2652 frequency = HSE_VALUE;
2653 }
2654 break;
2655 case RCC_USBOTGFSCLKSOURCE_CLK48: /*!< CLK48 is the clock source for USBOTGFS */
2656 /* Can't retrieve this source's frequency, it is by default set to 0 */
2657 break;
2658 default:
2659 /* Nothing to do, frequency is by default set to 0 */
2660 break;
2661 }
2662 break;
2663
2664 default:
2665 /* Nothing to do, frequency is by default set to 0 */
2666 break;
2667 }
2668
2669 return frequency;
2670 }
2671
2672 /**
2673 * @brief Enable clock protection.
2674 * @note When set, this prevents disabling accidentally clock related data.
2675 * @param ProtectClk Clock(s) to enable protection on
2676 * This parameter can be one or a combination of the following
2677 * @arg RCC_CLOCKPROTECT_FMC FMC clock protection
2678 * @arg RCC_CLOCKPROTECT_XSPI XSPIs clock protection
2679 * @retval None
2680 */
HAL_RCCEx_EnableClockProtection(uint32_t ProtectClk)2681 void HAL_RCCEx_EnableClockProtection(uint32_t ProtectClk)
2682 {
2683 /* Check the parameter */
2684 assert_param(IS_RCC_CLOCKPROTECTION(ProtectClk));
2685
2686 SET_BIT(RCC->CKPROTR, ProtectClk);
2687 }
2688
2689 /**
2690 * @brief Disable clock protection.
2691 * @param ProtectClk Clock(s) to disable protection on
2692 * This parameter can be one or a combination of the following
2693 * @arg RCC_CLOCKPROTECT_FMC FMC clock protection
2694 * @arg RCC_CLOCKPROTECT_XSPI XSPIs clock protection
2695 * @retval None
2696 */
HAL_RCCEx_DisableClockProtection(uint32_t ProtectClk)2697 void HAL_RCCEx_DisableClockProtection(uint32_t ProtectClk)
2698 {
2699 /* Check the parameter */
2700 assert_param(IS_RCC_CLOCKPROTECTION(ProtectClk));
2701
2702 CLEAR_BIT(RCC->CKPROTR, ProtectClk);
2703 }
2704
2705 /**
2706 * @}
2707 */
2708
2709 /** @defgroup RCCEx_Exported_Functions_Group2 Extended System Control functions
2710 * @brief Extended Peripheral Control functions
2711 * @{
2712 */
2713 /**
2714 * @brief Enables the LSE Clock Security System.
2715 * @note Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled
2716 * with HAL_RCC_OscConfig() and the LSE oscillator clock is to be selected as RTC
2717 * clock with HAL_RCCEx_PeriphCLKConfig().
2718 * @note Backup domain access should be enabled
2719 * @retval None
2720 */
HAL_RCCEx_EnableLSECSS(void)2721 void HAL_RCCEx_EnableLSECSS(void)
2722 {
2723 SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
2724 }
2725
2726 /**
2727 * @brief Disables the LSE Clock Security System.
2728 * @note LSE Clock Security System can only be disabled after a LSE failure detection.
2729 * @note Backup domain access should be enabled
2730 * @retval None
2731 */
HAL_RCCEx_DisableLSECSS(void)2732 void HAL_RCCEx_DisableLSECSS(void)
2733 {
2734 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
2735 /* Disable LSE CSS IT if any */
2736 __HAL_RCC_DISABLE_IT(RCC_IT_LSECSS);
2737 }
2738
2739 /**
2740 * @brief Enable the LSE Clock Security System Interrupt & corresponding EXTI line.
2741 * @note LSE Clock Security System Interrupt is mapped on EXTI line 18
2742 * @retval None
2743 */
HAL_RCCEx_EnableLSECSS_IT(void)2744 void HAL_RCCEx_EnableLSECSS_IT(void)
2745 {
2746 /* Enable LSE CSS */
2747 SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
2748
2749 /* Enable LSE CSS IT */
2750 __HAL_RCC_ENABLE_IT(RCC_IT_LSECSS);
2751
2752 /* Enable IT on EXTI Line 18 */
2753 __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE();
2754 __HAL_RCC_LSECSS_EXTI_ENABLE_IT();
2755 }
2756
2757 /**
2758 * @brief Configure the oscillator clock source for wakeup from Stop and CSS backup clock
2759 * @param WakeUpClk: Wakeup clock
2760 * This parameter can be one of the following values:
2761 * @arg RCC_STOP_WAKEUPCLOCK_CSI: CSI oscillator selection
2762 * @arg RCC_STOP_WAKEUPCLOCK_HSI: HSI oscillator selection
2763 * @note This function shall not be called after the Clock Security System on HSE has been
2764 * enabled.
2765 * @retval None
2766 */
HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk)2767 void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk)
2768 {
2769 assert_param(IS_RCC_STOP_WAKEUPCLOCK(WakeUpClk));
2770
2771 __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(WakeUpClk);
2772 }
2773
2774 /**
2775 * @brief Configure the oscillator Kernel clock source for wakeup from Stop
2776 * @param WakeUpClk: Kernel Wakeup clock
2777 * This parameter can be one of the following values:
2778 * @arg RCC_STOP_KERWAKEUPCLOCK_CSI: CSI oscillator selection
2779 * @arg RCC_STOP_KERWAKEUPCLOCK_HSI: HSI oscillator selection
2780 * @retval None
2781 */
HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk)2782 void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk)
2783 {
2784 assert_param(IS_RCC_STOP_KERWAKEUPCLOCK(WakeUpClk));
2785
2786 __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(WakeUpClk);
2787 }
2788
2789 /**
2790 * @brief Handle the RCC LSE Clock Security System interrupt request.
2791 * @retval None
2792 */
HAL_RCCEx_LSECSS_IRQHandler(void)2793 void HAL_RCCEx_LSECSS_IRQHandler(void)
2794 {
2795 /* Check RCC LSE CSSF flag */
2796 if (__HAL_RCC_GET_IT(RCC_IT_LSECSS))
2797 {
2798 /* Clear RCC LSE CSS pending bit */
2799 __HAL_RCC_CLEAR_IT(RCC_IT_LSECSS);
2800
2801 /* RCC LSE Clock Security System interrupt user callback */
2802 HAL_RCCEx_LSECSS_Callback();
2803 }
2804 }
2805
2806 /**
2807 * @brief RCCEx LSE Clock Security System interrupt callback.
2808 * @retval none
2809 */
HAL_RCCEx_LSECSS_Callback(void)2810 __weak void HAL_RCCEx_LSECSS_Callback(void)
2811 {
2812 /* NOTE : This function should not be modified, when the callback is needed,
2813 the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file
2814 */
2815 }
2816
2817 /**
2818 * @}
2819 */
2820
2821 /** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions
2822 * @brief Extended Clock Recovery System Control functions
2823 *
2824 @verbatim
2825 ===============================================================================
2826 ##### Extended Clock Recovery System Control functions #####
2827 ===============================================================================
2828 [..]
2829 For devices with Clock Recovery System feature (CRS), RCC Extension HAL driver can be used as follows:
2830
2831 (#) In System clock config, HSI48 needs to be enabled
2832
2833 (#) Enable CRS clock
2834
2835 (#) Call CRS functions as follows:
2836 (##) Prepare synchronization configuration necessary for HSI48 calibration
2837 (+++) Default values can be set for frequency Error Measurement (reload and error limit)
2838 and also HSI48 oscillator smooth trimming.
2839 (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate
2840 directly reload value with target and synchronization frequencies values
2841 (##) Call function HAL_RCCEx_CRSConfig which
2842 (+++) Resets CRS registers to their default values.
2843 (+++) Configures CRS registers with synchronization configuration
2844 (+++) Enables automatic calibration and frequency error counter feature
2845 Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the
2846 periodic USB SOF will not be generated by the host. No SYNC signal will therefore be
2847 provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock
2848 precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs
2849 should be used as SYNC signal.
2850
2851 (##) A polling function is provided to wait for complete synchronization
2852 (+++) Call function HAL_RCCEx_CRSWaitSynchronization()
2853 (+++) According to CRS status, user can decide to adjust again the calibration or continue
2854 application if synchronization is OK
2855
2856 (#) User can retrieve information related to synchronization in calling function
2857 HAL_RCCEx_CRSGetSynchronizationInfo()
2858
2859 (#) Regarding synchronization status and synchronization information, user can try a new calibration
2860 in changing synchronization configuration and call again HAL_RCCEx_CRSConfig.
2861 Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value),
2862 it means that the actual frequency is lower than the target (and so, that the TRIM value should be
2863 incremented), while when it is detected during the upcounting phase it means that the actual frequency
2864 is higher (and that the TRIM value should be decremented).
2865
2866 (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go
2867 through CRS Handler (CRS_IRQn/CRS_IRQHandler)
2868 (++) Call function HAL_RCCEx_CRSConfig()
2869 (++) Enable CRS_IRQn (thanks to NVIC functions)
2870 (++) Enable CRS interrupt (__HAL_RCC_CRS_ENABLE_IT)
2871 (++) Implement CRS status management in the following user callbacks called from
2872 HAL_RCCEx_CRS_IRQHandler():
2873 (+++) HAL_RCCEx_CRS_SyncOkCallback()
2874 (+++) HAL_RCCEx_CRS_SyncWarnCallback()
2875 (+++) HAL_RCCEx_CRS_ExpectedSyncCallback()
2876 (+++) HAL_RCCEx_CRS_ErrorCallback()
2877
2878 (#) To force a SYNC EVENT, user can use the function HAL_RCCEx_CRSSoftwareSynchronizationGenerate().
2879 This function can be called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler)
2880
2881 @endverbatim
2882 * @{
2883 */
2884
2885 /**
2886 * @brief Start automatic synchronization for polling mode.
2887 * @param pInit Pointer on RCC_CRSInitTypeDef structure
2888 * @retval None
2889 */
HAL_RCCEx_CRSConfig(const RCC_CRSInitTypeDef * pInit)2890 void HAL_RCCEx_CRSConfig(const RCC_CRSInitTypeDef *pInit)
2891 {
2892 uint32_t value;
2893
2894 /* Check the parameters */
2895 assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler));
2896 assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source));
2897 assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity));
2898 assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue));
2899 assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue));
2900 assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue));
2901
2902 /* CONFIGURATION */
2903
2904 /* Before configuration, reset CRS registers to their default values*/
2905 __HAL_RCC_CRS_FORCE_RESET();
2906 __HAL_RCC_CRS_RELEASE_RESET();
2907
2908 /* Set the SYNCDIV[2:0] bits according to Prescaler value */
2909 /* Set the SYNCSRC[1:0] bits according to Source value */
2910 /* Set the SYNCSPOL bit according to Polarity value */
2911 value = (pInit->Prescaler | pInit->Source | pInit->Polarity);
2912 /* Set the RELOAD[15:0] bits according to ReloadValue value */
2913 value |= pInit->ReloadValue;
2914 /* Set the FELIM[7:0] bits according to ErrorLimitValue value */
2915 value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos);
2916 WRITE_REG(CRS->CFGR, value);
2917
2918 /* Adjust HSI48 oscillator smooth trimming */
2919 /* Set the TRIM[5:0] bits according to HSI48CalibrationValue value */
2920 MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_Pos));
2921
2922 /* START AUTOMATIC SYNCHRONIZATION*/
2923
2924 /* Enable Automatic trimming & Frequency error counter */
2925 SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN);
2926 }
2927
2928 /**
2929 * @brief Generate the software synchronization event.
2930 * @retval None
2931 */
HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void)2932 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void)
2933 {
2934 SET_BIT(CRS->CR, CRS_CR_SWSYNC);
2935 }
2936
2937 /**
2938 * @brief Return synchronization info.
2939 * @param pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure
2940 * @retval None
2941 */
HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef * pSynchroInfo)2942 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo)
2943 {
2944 /* Check the parameter */
2945 assert_param(pSynchroInfo != (void *)NULL);
2946
2947 /* Get the reload value */
2948 pSynchroInfo->ReloadValue = (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
2949
2950 /* Get HSI48 oscillator smooth trimming */
2951 pSynchroInfo->HSI48CalibrationValue = (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);
2952
2953 /* Get Frequency error capture */
2954 pSynchroInfo->FreqErrorCapture = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);
2955
2956 /* Get Frequency error direction */
2957 pSynchroInfo->FreqErrorDirection = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
2958 }
2959
2960 /**
2961 * @brief Wait for CRS Synchronization status.
2962 * @param Timeout Duration of the timeout
2963 * @note Timeout is based on the maximum time to receive a SYNC event based on synchronization
2964 * frequency.
2965 * @note If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned.
2966 * @retval Combination of Synchronization status
2967 * This parameter can be a combination of the following values:
2968 * @arg @ref RCC_CRS_TIMEOUT
2969 * @arg @ref RCC_CRS_SYNCOK
2970 * @arg @ref RCC_CRS_SYNCWARN
2971 * @arg @ref RCC_CRS_SYNCERR
2972 * @arg @ref RCC_CRS_SYNCMISS
2973 * @arg @ref RCC_CRS_TRIMOVF
2974 */
HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)2975 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
2976 {
2977 uint32_t crsstatus = RCC_CRS_NONE;
2978 uint32_t tickstart;
2979
2980 /* Get timeout */
2981 tickstart = HAL_GetTick();
2982
2983 /* Wait for CRS flag or timeout detection */
2984 do
2985 {
2986 if (Timeout != HAL_MAX_DELAY)
2987 {
2988 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
2989 {
2990 crsstatus = RCC_CRS_TIMEOUT;
2991 }
2992 }
2993 /* Check CRS SYNCOK flag */
2994 if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK))
2995 {
2996 /* CRS SYNC event OK */
2997 crsstatus |= RCC_CRS_SYNCOK;
2998
2999 /* Clear CRS SYNC event OK bit */
3000 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK);
3001 }
3002
3003 /* Check CRS SYNCWARN flag */
3004 if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN))
3005 {
3006 /* CRS SYNC warning */
3007 crsstatus |= RCC_CRS_SYNCWARN;
3008
3009 /* Clear CRS SYNCWARN bit */
3010 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN);
3011 }
3012
3013 /* Check CRS TRIM overflow flag */
3014 if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF))
3015 {
3016 /* CRS SYNC Error */
3017 crsstatus |= RCC_CRS_TRIMOVF;
3018
3019 /* Clear CRS Error bit */
3020 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF);
3021 }
3022
3023 /* Check CRS Error flag */
3024 if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR))
3025 {
3026 /* CRS SYNC Error */
3027 crsstatus |= RCC_CRS_SYNCERR;
3028
3029 /* Clear CRS Error bit */
3030 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR);
3031 }
3032
3033 /* Check CRS SYNC Missed flag */
3034 if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS))
3035 {
3036 /* CRS SYNC Missed */
3037 crsstatus |= RCC_CRS_SYNCMISS;
3038
3039 /* Clear CRS SYNC Missed bit */
3040 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS);
3041 }
3042
3043 /* Check CRS Expected SYNC flag */
3044 if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC))
3045 {
3046 /* frequency error counter reached a zero value */
3047 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC);
3048 }
3049 } while (RCC_CRS_NONE == crsstatus);
3050
3051 return crsstatus;
3052 }
3053
3054 /**
3055 * @brief Handle the Clock Recovery System interrupt request.
3056 * @retval None
3057 */
HAL_RCCEx_CRS_IRQHandler(void)3058 void HAL_RCCEx_CRS_IRQHandler(void)
3059 {
3060 uint32_t crserror = RCC_CRS_NONE;
3061 /* Get current IT flags and IT sources values */
3062 uint32_t itflags = READ_REG(CRS->ISR);
3063 uint32_t itsources = READ_REG(CRS->CR);
3064
3065 /* Check CRS SYNCOK flag */
3066 if (((itflags & RCC_CRS_FLAG_SYNCOK) != 0U) && ((itsources & RCC_CRS_IT_SYNCOK) != 0U))
3067 {
3068 /* Clear CRS SYNC event OK flag */
3069 WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
3070
3071 /* user callback */
3072 HAL_RCCEx_CRS_SyncOkCallback();
3073 }
3074 /* Check CRS SYNCWARN flag */
3075 else if (((itflags & RCC_CRS_FLAG_SYNCWARN) != 0U) && ((itsources & RCC_CRS_IT_SYNCWARN) != 0U))
3076 {
3077 /* Clear CRS SYNCWARN flag */
3078 WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
3079
3080 /* user callback */
3081 HAL_RCCEx_CRS_SyncWarnCallback();
3082 }
3083 /* Check CRS Expected SYNC flag */
3084 else if (((itflags & RCC_CRS_FLAG_ESYNC) != 0U) && ((itsources & RCC_CRS_IT_ESYNC) != 0U))
3085 {
3086 /* frequency error counter reached a zero value */
3087 WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
3088
3089 /* user callback */
3090 HAL_RCCEx_CRS_ExpectedSyncCallback();
3091 }
3092 /* Check CRS Error flags */
3093 else
3094 {
3095 if (((itflags & RCC_CRS_FLAG_ERR) != 0U) && ((itsources & RCC_CRS_IT_ERR) != 0U))
3096 {
3097 if ((itflags & RCC_CRS_FLAG_SYNCERR) != 0U)
3098 {
3099 crserror |= RCC_CRS_SYNCERR;
3100 }
3101 if ((itflags & RCC_CRS_FLAG_SYNCMISS) != 0U)
3102 {
3103 crserror |= RCC_CRS_SYNCMISS;
3104 }
3105 if ((itflags & RCC_CRS_FLAG_TRIMOVF) != 0U)
3106 {
3107 crserror |= RCC_CRS_TRIMOVF;
3108 }
3109
3110 /* Clear CRS Error flags */
3111 WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
3112
3113 /* user error callback */
3114 HAL_RCCEx_CRS_ErrorCallback(crserror);
3115 }
3116 }
3117 }
3118
3119 /**
3120 * @brief RCCEx Clock Recovery System SYNCOK interrupt callback.
3121 * @retval none
3122 */
HAL_RCCEx_CRS_SyncOkCallback(void)3123 __weak void HAL_RCCEx_CRS_SyncOkCallback(void)
3124 {
3125 /* NOTE : This function should not be modified, when the callback is needed,
3126 the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file
3127 */
3128 }
3129
3130 /**
3131 * @brief RCCEx Clock Recovery System SYNCWARN interrupt callback.
3132 * @retval none
3133 */
HAL_RCCEx_CRS_SyncWarnCallback(void)3134 __weak void HAL_RCCEx_CRS_SyncWarnCallback(void)
3135 {
3136 /* NOTE : This function should not be modified, when the callback is needed,
3137 the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file
3138 */
3139 }
3140
3141 /**
3142 * @brief RCCEx Clock Recovery System Expected SYNC interrupt callback.
3143 * @retval none
3144 */
HAL_RCCEx_CRS_ExpectedSyncCallback(void)3145 __weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void)
3146 {
3147 /* NOTE : This function should not be modified, when the callback is needed,
3148 the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file
3149 */
3150 }
3151
3152 /**
3153 * @brief RCCEx Clock Recovery System Error interrupt callback.
3154 * @param Error Combination of Error status.
3155 * This parameter can be a combination of the following values:
3156 * @arg @ref RCC_CRS_SYNCERR
3157 * @arg @ref RCC_CRS_SYNCMISS
3158 * @arg @ref RCC_CRS_TRIMOVF
3159 * @retval none
3160 */
HAL_RCCEx_CRS_ErrorCallback(uint32_t Error)3161 __weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error)
3162 {
3163 /* Prevent unused argument(s) compilation warning */
3164 UNUSED(Error);
3165
3166 /* NOTE : This function should not be modified, when the callback is needed,
3167 the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file
3168 */
3169 }
3170
3171 /**
3172 * @}
3173 */
3174
3175 /* Private functions ---------------------------------------------------------*/
3176 /** @addtogroup RCC_Private_Functions
3177 * @{
3178 */
3179
3180 /**
3181 * @brief Compute PLL2 VCO output frequency
3182 * @retval Value of PLL2 VCO output frequency
3183 */
RCC_GetCLKPFreq(void)3184 static uint32_t RCC_GetCLKPFreq(void)
3185 {
3186 uint32_t frequency = 0U;
3187 uint32_t ckpclocksource;
3188
3189 ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
3190
3191 if (ckpclocksource == RCC_CLKPSOURCE_HSI)
3192 {
3193 if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
3194 {
3195 if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0U)
3196 {
3197 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
3198 }
3199 else
3200 {
3201 /* Can't retrieve HSIDIV value */
3202 }
3203 }
3204 }
3205 else if (ckpclocksource == RCC_CLKPSOURCE_CSI)
3206 {
3207 if (READ_BIT(RCC->CR, RCC_CR_CSIRDY) != 0U)
3208 {
3209 frequency = CSI_VALUE;
3210 }
3211 }
3212 else if (ckpclocksource == RCC_CLKPSOURCE_HSE)
3213 {
3214 if (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
3215 {
3216 frequency = HSE_VALUE;
3217 }
3218 }
3219 else
3220 {
3221 /* Nothing to do, case the CKPER is disabled */
3222 /* frequency is by default set to 0 */
3223 }
3224
3225 return frequency;
3226 }
3227 /**
3228 * @}
3229 */
3230
3231 /**
3232 * @}
3233 */
3234 #endif /* HAL_RCC_MODULE_ENABLED */
3235
3236 /**
3237 * @}
3238 */
3239
3240 /**
3241 * @}
3242 */
3243
