1# Configuration file for pinctrl generation (F1 series only). 2# 3# This file contains a list of pin configuration templates used to generate the 4# pinctrl files. Each entry can have the following fields: 5# 6# - name (mandatory): This is the pin function name, e.g. UART_TX. It is used 7# to group pin configurations alphabetically in the generated pinctrl files. 8# 9# - match (mandatory): This is a regular expression used to match against 10# STM32 xml database pin configuration names. The regular expression should 11# be as precise as possible. Note that it needs to be escaped here in the 12# configuration file. 13# Note: Specific "ANALOG" value allows generation of analog pins 14# configuration 15# 16# - mode (mandatory): Mode setting (analog, alternate, input). Mode needs to 17# be set according to the following rules: 18# * Pin operates in analog configuration: analog 19# * Pin operates in alternate function input configuration: input 20# * Pin operates in alternate function output/bidirectional configuration: 21# alternate 22# 23# - bias (optional): Bias setting (disable, pull-up, pull-down). This setting 24# only applies to "input" mode. Equivalent to "disable" (a.k.a floating) if 25# not set. 26# 27# - drive (optional): Drive setting (push-pull, open-drain). Equivalent to 28# "push-pull" if not set. 29# 30# - slew-rate (optional): Slew rate setting (max-speed-10mhz, max-speed-2mhz, 31# max-speed-50mhz). Equivalent to "max-speed-10mhz" if not set. 32# 33# - variant (optional): Defines an alternative pin configuration. This is used 34# to provide multiple configurations of a pin function (slave, master, 35# low-power, ...). 36# 37 38--- 39- name: Analog 40 match: "ANALOG" 41 mode: analog 42 43- name: ADC_IN 44 match: "^ADC\\d+_IN\\d+$" 45 mode: analog 46 47- name: CAN_RX 48 match: "^CAN\\d*_RX$" 49 mode: input 50 51- name: CAN_TX 52 match: "^CAN\\d*_TX$" 53 mode: alternate 54 55- name: DAC_OUT 56 match: "^DAC_OUT\\d+$" 57 mode: analog 58 59- name: ETH_COL 60 match: "^ETH_COL$" 61 mode: input 62 63- name: ETH_CRS 64 match: "^ETH_CRS$" 65 mode: input 66 67- name: ETH_CRS_DV 68 match: "^ETH_CRS_DV$" 69 mode: input 70 71- name: ETH_MDC 72 match: "^ETH_MDC$" 73 mode: alternate 74 slew-rate: max-speed-50mhz 75 76- name: ETH_MDIO 77 match: "^ETH_MDIO$" 78 mode: alternate 79 slew-rate: max-speed-50mhz 80 81- name: ETH_PPS_OUT 82 match: "^ETH_PPS_OUT$" 83 mode: alternate 84 slew-rate: max-speed-50mhz 85 86- name: ETH_REF_CLK 87 match: "^ETH_REF_CLK$" 88 mode: input 89 90- name: ETH_RX_CLK 91 match: "^ETH_RX_CLK$" 92 mode: input 93 94- name: ETH_RX_DV 95 match: "^ETH_RX_DV$" 96 mode: input 97 98- name: ETH_RX_ER 99 match: "^ETH_RX_ER$" 100 mode: input 101 102- name: ETH_RXD0 103 match: "^ETH_RXD0$" 104 mode: input 105 106- name: ETH_RXD1 107 match: "^ETH_RXD1$" 108 mode: input 109 110- name: ETH_RXD2 111 match: "^ETH_RXD2$" 112 mode: input 113 114- name: ETH_RXD3 115 match: "^ETH_RXD3$" 116 mode: input 117 118- name: ETH_TX_CLK 119 match: "^ETH_TX_CLK$" 120 mode: input 121 122- name: ETH_TX_EN 123 match: "^ETH_TX_EN$" 124 mode: alternate 125 slew-rate: max-speed-50mhz 126 127- name: ETH_TXD0 128 match: "^ETH_TXD0$" 129 mode: alternate 130 slew-rate: max-speed-50mhz 131 132- name: ETH_TXD1 133 match: "^ETH_TXD1$" 134 mode: alternate 135 slew-rate: max-speed-50mhz 136 137- name: ETH_TXD2 138 match: "^ETH_TXD2$" 139 mode: alternate 140 slew-rate: max-speed-50mhz 141 142- name: ETH_TXD3 143 match: "^ETH_TXD3$" 144 mode: alternate 145 slew-rate: max-speed-50mhz 146 147- name: I2C_SCL 148 match: "^I2C\\d+_SCL$" 149 drive: open-drain 150 mode: alternate 151 152- name: I2C_SDA 153 match: "^I2C\\d+_SDA$" 154 drive: open-drain 155 mode: alternate 156 157- name: I2C_SMBA 158 match: "^I2C\\d+_SMBA$" 159 mode: alternate 160 161- name: I2S_CK 162 match: "^I2S\\d+_CK$" 163 mode: alternate 164 165- name: I2S_WS 166 match: "^I2S\\d+_WS$" 167 mode: alternate 168 169- name: I2S_SD 170 match: "^I2S\\d+_SD$" 171 mode: alternate 172 173- name: JTAG PORT 174 match: "^(SYS|DEBUG)_((JTMS-)?SWDIO|(JTCK-)?SWCLK|JTDI|JTDO(-TRACESWO|-SWO)?|(NJ)?JTRST)$" 175 mode: alternate 176 177- name: RCC_MCO 178 match: "^RCC_MCO_?(\\d+)?$" 179 mode: alternate 180 181- name: SPI_MASTER_MISO 182 match: "^SPI\\d+_MISO$" 183 bias: pull-down 184 mode: input 185 variant: master 186 187- name: SPI_MASTER_MOSI 188 match: "^SPI\\d+_MOSI$" 189 mode: alternate 190 variant: master 191 192- name: SPI_MASTER_SCK 193 match: "^SPI\\d+_SCK$" 194 mode: alternate 195 variant: master 196 197- name: SPI_MASTER_NSS 198 match: "^SPI\\d+_NSS$" 199 mode: alternate 200 variant: master 201 202- name: SPI_SLAVE_MISO 203 match: "^SPI\\d+_MISO$" 204 mode: alternate 205 variant: slave 206 207- name: SPI_SLAVE_MOSI 208 match: "^SPI\\d+_MOSI$" 209 mode: input 210 variant: slave 211 212- name: SPI_SLAVE_SCK 213 match: "^SPI\\d+_SCK$" 214 mode: input 215 variant: slave 216 217- name: SPI_SLAVE_NSS 218 match: "^SPI\\d+_NSS$" 219 bias: pull-up 220 mode: input 221 variant: slave 222 223- name: TIM_BKIN 224 match: "^TIM\\d+_BKIN$" 225 mode: input 226 227- name: TIM_CH_PWM_OUT / TIM_CHN_PWM_OUT 228 match: "^TIM\\d+_CH\\d+N?$" 229 mode: alternate 230 variant: pwm_out 231 232- name: TIM_CH_PWM_IN / TIM_CHN_PWM_IN 233 match: "^TIM\\d+_CH\\d+N?$" 234 mode: input 235 variant: pwm_in 236 237- name: TSC 238 match: "^TSC_(?:G\\d+_IO\\d+|SYNC)$" 239 mode: alternate 240 241- name: UART_CTS / USART_CTS 242 match: "^US?ART\\d+_CTS$" 243 drive: open-drain 244 bias: pull-up 245 mode: input 246 247- name: UART_RTS / USART_RTS 248 match: "^US?ART\\d+_RTS$" 249 mode: alternate 250 251- name: UART_TX / USART_TX 252 match: "^US?ART\\d+_TX$" 253 mode: alternate 254 255- name: UART_RX / USART_RX 256 match: "^US?ART\\d+_RX$" 257 mode: input 258 259- name: USB_OTG_FS 260 match: "^USB_OTG_FS_(?:DM)?(?:DP)?(?:SOF)?(?:ID)?(?:VBUS)?$" 261 mode: input 262 263- name: USB 264 match: "^USB_(?:DM)?(?:DP)?$" 265 mode: input 266 267