# Configuration file for pinctrl generation (F1 series only).
#
# This file contains a list of pin configuration templates used to generate the
# pinctrl files. Each entry can have the following fields:
#
#   - name (mandatory): This is the pin function name, e.g. UART_TX. It is used
#     to group pin configurations alphabetically in the generated pinctrl files.
#
#   - match (mandatory): This is a regular expression used to match against
#     STM32 xml database pin configuration names. The regular expression should
#     be as precise as possible. Note that it needs to be escaped here in the
#     configuration file.
#     Note: Specific "ANALOG" value allows generation of analog pins
#     configuration
#
#   - mode (mandatory): Mode setting (analog, alternate, input). Mode needs to
#     be set according to the following rules:
#       * Pin operates in analog configuration: analog
#       * Pin operates in alternate function input configuration: input
#       * Pin operates in alternate function output/bidirectional configuration:
#         alternate
#
#   - bias (optional): Bias setting (disable, pull-up, pull-down). This setting
#     only applies to "input" mode. Equivalent to "disable" (a.k.a floating) if
#     not set.
#
#   - drive (optional): Drive setting (push-pull, open-drain). Equivalent to
#     "push-pull" if not set.
#
#   - slew-rate (optional): Slew rate setting (max-speed-10mhz, max-speed-2mhz,
#     max-speed-50mhz). Equivalent to "max-speed-10mhz" if not set.
#
#   - variant (optional): Defines an alternative pin configuration. This is used
#     to provide multiple configurations of a pin function (slave, master,
#     low-power, ...).
#

---
- name: Analog
  match: "ANALOG"
  mode: analog

- name: ADC_IN
  match: "^ADC\\d+_IN\\d+$"
  mode: analog

- name: CAN_RX
  match: "^CAN\\d*_RX$"
  mode: input

- name: CAN_TX
  match: "^CAN\\d*_TX$"
  mode: alternate

- name: DAC_OUT
  match: "^DAC_OUT\\d+$"
  mode: analog

- name: ETH_COL
  match: "^ETH_COL$"
  mode: input

- name: ETH_CRS
  match: "^ETH_CRS$"
  mode: input

- name: ETH_CRS_DV
  match: "^ETH_CRS_DV$"
  mode: input

- name: ETH_MDC
  match: "^ETH_MDC$"
  mode: alternate
  slew-rate: max-speed-50mhz

- name: ETH_MDIO
  match: "^ETH_MDIO$"
  mode: alternate
  slew-rate: max-speed-50mhz

- name: ETH_PPS_OUT
  match: "^ETH_PPS_OUT$"
  mode: alternate
  slew-rate: max-speed-50mhz

- name: ETH_REF_CLK
  match: "^ETH_REF_CLK$"
  mode: input

- name: ETH_RX_CLK
  match: "^ETH_RX_CLK$"
  mode: input

- name: ETH_RX_DV
  match: "^ETH_RX_DV$"
  mode: input

- name: ETH_RX_ER
  match: "^ETH_RX_ER$"
  mode: input

- name: ETH_RXD0
  match: "^ETH_RXD0$"
  mode: input

- name: ETH_RXD1
  match: "^ETH_RXD1$"
  mode: input

- name: ETH_RXD2
  match: "^ETH_RXD2$"
  mode: input

- name: ETH_RXD3
  match: "^ETH_RXD3$"
  mode: input

- name: ETH_TX_CLK
  match: "^ETH_TX_CLK$"
  mode: input

- name: ETH_TX_EN
  match: "^ETH_TX_EN$"
  mode: alternate
  slew-rate: max-speed-50mhz

- name: ETH_TXD0
  match: "^ETH_TXD0$"
  mode: alternate
  slew-rate: max-speed-50mhz

- name: ETH_TXD1
  match: "^ETH_TXD1$"
  mode: alternate
  slew-rate: max-speed-50mhz

- name: ETH_TXD2
  match: "^ETH_TXD2$"
  mode: alternate
  slew-rate: max-speed-50mhz

- name: ETH_TXD3
  match: "^ETH_TXD3$"
  mode: alternate
  slew-rate: max-speed-50mhz

- name: I2C_SCL
  match: "^I2C\\d+_SCL$"
  drive: open-drain
  mode: alternate

- name: I2C_SDA
  match: "^I2C\\d+_SDA$"
  drive: open-drain
  mode: alternate

- name: I2C_SMBA
  match: "^I2C\\d+_SMBA$"
  mode: alternate

- name: I2S_CK
  match: "^I2S\\d+_CK$"
  mode: alternate

- name: I2S_WS
  match: "^I2S\\d+_WS$"
  mode: alternate

- name: I2S_SD
  match: "^I2S\\d+_SD$"
  mode: alternate

- name: JTAG PORT
  match: "^(SYS|DEBUG)_((JTMS-)?SWDIO|(JTCK-)?SWCLK|JTDI|JTDO(-TRACESWO|-SWO)?|(NJ)?JTRST)$"
  mode: alternate

- name: RCC_MCO
  match: "^RCC_MCO_?(\\d+)?$"
  mode: alternate

- name: SPI_MASTER_MISO
  match: "^SPI\\d+_MISO$"
  bias: pull-down
  mode: input
  variant: master

- name: SPI_MASTER_MOSI
  match: "^SPI\\d+_MOSI$"
  mode: alternate
  variant: master

- name: SPI_MASTER_SCK
  match: "^SPI\\d+_SCK$"
  mode: alternate
  variant: master

- name: SPI_MASTER_NSS
  match: "^SPI\\d+_NSS$"
  mode: alternate
  variant: master

- name: SPI_SLAVE_MISO
  match: "^SPI\\d+_MISO$"
  mode: alternate
  variant: slave

- name: SPI_SLAVE_MOSI
  match: "^SPI\\d+_MOSI$"
  mode: input
  variant: slave

- name: SPI_SLAVE_SCK
  match: "^SPI\\d+_SCK$"
  mode: input
  variant: slave

- name: SPI_SLAVE_NSS
  match: "^SPI\\d+_NSS$"
  bias: pull-up
  mode: input
  variant: slave

- name: TIM_BKIN
  match: "^TIM\\d+_BKIN$"
  mode: input

- name: TIM_CH_PWM_OUT / TIM_CHN_PWM_OUT
  match: "^TIM\\d+_CH\\d+N?$"
  mode: alternate
  variant: pwm_out

- name: TIM_CH_PWM_IN / TIM_CHN_PWM_IN
  match: "^TIM\\d+_CH\\d+N?$"
  mode: input
  variant: pwm_in

- name: TSC
  match: "^TSC_(?:G\\d+_IO\\d+|SYNC)$"
  mode: alternate

- name: UART_CTS / USART_CTS
  match: "^US?ART\\d+_CTS$"
  drive: open-drain
  bias: pull-up
  mode: input

- name: UART_RTS / USART_RTS
  match: "^US?ART\\d+_RTS$"
  mode: alternate

- name: UART_TX / USART_TX
  match: "^US?ART\\d+_TX$"
  mode: alternate

- name: UART_RX / USART_RX
  match: "^US?ART\\d+_RX$"
  mode: input

- name: USB_OTG_FS
  match: "^USB_OTG_FS_(?:DM)?(?:DP)?(?:SOF)?(?:ID)?(?:VBUS)?$"
  mode: input

- name: USB
  match: "^USB_(?:DM)?(?:DP)?$"
  mode: input

