1 /*
2  * Copyright 2024 NXP
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef _FSL_PM_DEVICE_H_
8 #define _FSL_PM_DEVICE_H_
9 
10 #include "fsl_common.h"
11 
12 #include "fsl_pm_config.h"
13 
14 /*!
15  * @addtogroup PM Framework: Power Manager Framework
16  * @brief This section includes Power Mode macros, System Constraints macros, and Wakeup source macros.
17  * @{
18  */
19 
20 /*!
21  * @name Power Mode Definition
22  * @{
23  */
24 
25 /* Power Mode Index */
26 #define PM_LP_STATE_SLEEP                (0U)
27 #define PM_LP_STATE_DEEP_SLEEP           (1U)
28 #define PM_LP_STATE_DSR                  (2U)
29 #define PM_LP_STATE_DEEP_POWER_DOWN      (3U)
30 #define PM_LP_STATE_FULL_DEEP_POWER_DOWN (4U)
31 #define PM_LP_STATE_NO_CONSTRAINT        (0xFFU)
32 
33 /*! @} */
34 
35 /* Helper macros */
36 #define PM_RESC_MASK(resc_masks, resc) \
37     (((resc_masks)->rescMask[(uint32_t)(resc) / 32U] >> ((uint32_t)(resc) % 32U)) & 1U)
38 #define PM_RESC_GROUP(resc_groups, resc) \
39     (((resc_groups)->groupSlice[(uint32_t)(resc) / 8U] >> (4U * ((uint32_t)(resc) % 8U))) & 0xFU)
40 
41 /*!
42  * @name System basic resource constraints definitions.
43  * @{
44  */
45 
46 /*! @brief Available constraints for resources
47  *
48  *  The constraints below are grouped together in 3 groups
49  */
50 
51 typedef enum _resc_name
52 {
53 /* Peripherals and RAMs that do not have separate retention bit in SLEEPCON */
54 #if defined(PMC0)
55     kResc_COMP_MAINCLK = 0, /*!< Compute Main Clock */
56     kResc_SENSEP_MAINCLK,   /*!< VDD1_SENSE Domain private main clock */
57 #else
58     kResc_SENSEP_MAINCLK = 0, /*!< VDD1_SENSE Domain private main clock */
59 #endif
60     kResc_SENSES_MAINCLK, /*!< VDD1_SENSE Domain shared main clock */
61     kResc_RAM0CLK,        /*!< RAM_ARBITER0 common_ram_clk */
62     kResc_RAM1CLK,        /*!< RAM_ARBITER1 sense_ram_clk */
63     kResc_COMN_MAINCLK,   /*!< VDDN_COM Domain common_vddn_clk */
64     kResc_MEDIA_MAINCLK,  /*!< VDD2_MEDIA and VDDN_MEDIA Domains media_main_clk and media_vddn_clk */
65     kResc_XTAL,           /*!< XTAL */
66 #if defined(PMC0)
67     kResc_FRO0,           /*!< FRO0 power control */
68     kResc_FRO1,           /*!< FRO1 power control*/
69 #endif
70     kResc_FRO2,           /*!< FRO2 */
71     kResc_LPOSC,          /*!< LPOSC */
72     kResc_PLLANA,         /*!< PLLANA */
73     kResc_PLLLDO,         /*!< PLLLDO */
74     kResc_AUDPLLANA,      /*!< AUDPLLANA */
75     kResc_AUDPLLLDO,      /*!< AUDPLLLDO */
76     kResc_ADC0,           /*!< ADC0 */
77 #if defined(PMC0)
78     kResc_FRO0_EN,        /*!< FRO0 gate control */
79 #endif
80     kResc_FRO2_EN,        /*!< FRO2 gate control */
81 
82     /* Peripherals and RAMs that do not have separate retention bit in PMC PDSLEECFG0-1 */
83     kResc_V2NMED,     /*!< Power Switch and DSR for VDD2 and VDDN Media */
84     kResc_VNCOM,      /*!< Power Switch and DSR for VDDN_COM */
85     kResc_V2DSP,      /*!< Power Switch and DSR for VDD2_DSP */
86     kResc_V2MIPI,     /*!< Power Switch for MIPI PHY */
87     kResc_DCDC_HP,    /*!< DCDC in high-power mode */
88 
89     kResc_PMC_TEMP,   /*!< PMC Temperature sensor */
90     kResc_PMCREF_HP,  /*!< PMC Reference */
91     kResc_HVD1V8,     /*!< 1.8V High-Voltage Detect */
92     kResc_PORVDD1_HP, /*!< VDD1 Power-On Reset monitor */
93     kResc_LVDVDD1_HP, /*!< VDD1 Low-Voltage Dectect */
94     kResc_HVDVDD1,    /*!< VDD1 High-Voltage Dectect */
95     kResc_AGDET1,     /*!< VDD1 analog glitch detect */
96     kResc_PORVDD2_HP, /*!< VDD2 Power-On Reset monitor */
97     kResc_LVDVDD2_HP, /*!< VDD2 Low-Voltage Dectect */
98     kResc_HVDVDD2,    /*!< VDD2 High-Voltage Dectect */
99     kResc_AGDET2,     /*!< VDD2 analog glitch detect */
100     kResc_PORVDDN_HP, /*!< VDDN Power-On Reset monitor */
101     kResc_LVDVDDN_HP, /*!< VDDN Low-Voltage Dectect */
102     kResc_HVDVDDN,    /*!< VDDN High-Voltage Dectect */
103     kResc_OTP,        /*!< OTP */
104     kResc_ROM,        /*!< ROM */
105 
106     /* System SRAMs that have bits in both PDSLEEPCFG2 & 3 */
107     kResc_SRAM0_32KB,   /*!< SRAM partition0 */
108     kResc_SRAM1_32KB,   /*!< SRAM partition1 */
109     kResc_SRAM2_32KB,   /*!< SRAM partition2 */
110     kResc_SRAM3_32KB,   /*!< SRAM partition3 */
111     kResc_SRAM4_64KB,   /*!< SRAM partition4 */
112     kResc_SRAM5_64KB,   /*!< SRAM partition5 */
113     kResc_SRAM6_128KB,  /*!< SRAM partition6 */
114     kResc_SRAM7_128KB,  /*!< SRAM partition7 */
115     kResc_SRAM8_256KB,  /*!< SRAM partition8 */
116     kResc_SRAM9_256KB,  /*!< SRAM partition9 */
117     kResc_SRAM10_512KB, /*!< SRAM partition10 */
118     kResc_SRAM11_512KB, /*!< SRAM partition11 */
119     kResc_SRAM12_1MB,   /*!< SRAM partition12 */
120     kResc_SRAM13_1MB,   /*!< SRAM partition13 */
121     kResc_SRAM14_512KB, /*!< SRAM partition14 */
122     kResc_SRAM15_512KB, /*!< SRAM partition15 */
123     kResc_SRAM16_256KB, /*!< SRAM partition16 */
124     kResc_SRAM17_256KB, /*!< SRAM partition17 */
125     kResc_SRAM18_32KB,  /*!< SRAM partition18 */
126     kResc_SRAM19_32KB,  /*!< SRAM partition19 */
127     kResc_SRAM20_32KB,  /*!< SRAM partition20 */
128     kResc_SRAM21_32KB,  /*!< SRAM partition21 */
129     kResc_SRAM22_64KB,  /*!< SRAM partition22 */
130     kResc_SRAM23_64KB,  /*!< SRAM partition23 */
131     kResc_SRAM24_128KB, /*!< SRAM partition24 */
132     kResc_SRAM25_128KB, /*!< SRAM partition25 */
133     kResc_SRAM26_512KB, /*!< SRAM partition26 */
134     kResc_SRAM27_512KB, /*!< SRAM partition27 */
135     kResc_SRAM28_256KB, /*!< SRAM partition28 */
136     kResc_SRAM29_256KB, /*!< SRAM partition29 */
137 
138     /* dedicated peripheral SRAMs that have 2 bits each in PDSLEEPCFG4 & 5 */
139     kResc_SRAM_USDHC0,      /*!< uSDHC0 SRAM */
140     kResc_SRAM_USDHC1,      /*!< uSDHC1 SRAM */
141     kResc_SRAM_USB0,        /*!< USB0 SRAM */
142     kResc_SRAM_USB1,        /*!< USB1 SRAM */
143     kResc_SRAM_JPEGDEC,     /*!< JPEGDEC SRAM */
144     kResc_SRAM_PNGDEC,      /*!< PNGDEC SRAM */
145     kResc_SRAM_MIPI,        /*!< MIPI PHY SRAM */
146     kResc_SRAM_GPU,         /*!< VGPU SRAM */
147     kResc_SRAM_DMA23,       /*!< DMA2 and DMA3 SRAM */
148     kResc_SRAM_DMA01PE,     /*!< DMA0-1, PKC, and ETF SRAM */
149     kResc_SRAM_CPU0_ICACHE, /*!< CPU0 Code cache RAM */
150     kResc_SRAM_CPU0_DCACHE, /*!< CPU0 System cache RAM */
151     kResc_SRAM_DSP_ICACHE,  /*!< HiFi4 instruction cache RAM*/
152     kResc_SRAM_DSP_DCACHE,  /*!< HiFi4 data cache RAM */
153     kResc_SRAM_DSP_ITCM,    /*!< HiFi4 instruction TCM RAM*/
154     kResc_SRAM_DSP_DTCM,    /*!< HiFi4 data TCM RAM */
155     kResc_SRAM_EZHV,        /*!< EZHV TCM RAM */
156     kResc_SRAM_NPU,         /*!< NPU TCM RAM */
157     kResc_SRAM_XSPI0,       /*!< XSPI0, MMU0 and Cache SRAM */
158     kResc_SRAM_XSPI1,       /*!< XSPI1, MMU1 and Cache SRAM */
159     kResc_SRAM_XSPI2,       /*!< XSPI2 and MMU2 SRAM */
160     kResc_SRAM_LCDIF,       /*!< LCDIF SRAM */
161     kResc_SRAM_OCOTP,       /*!< OCOTP SRAM */
162 
163     kResc_MaxNum,           /*!< Maximum number of supported constraints */
164 } resc_name_t;
165 
166 /* Macros for Resource Constraint Group Types */
167 #define RESC_GROUP_SRAMS_START kResc_SRAM0_32KB
168 #define RESC_GROUP_SRAMS_END   kResc_SRAM_OCOTP
169 #define RESC_GROUP_SRAMS_SIZE  RESC_GROUP_SRAMS_END - RESC_GROUP_SRAMS_START + 1
170 
171 #if defined(PMC0)
172 #define RESC_GROUP_PERIPHERALS_START kResc_COMP_MAINCLK
173 #else
174 #define RESC_GROUP_PERIPHERALS_START kResc_SENSEP_MAINCLK
175 #endif
176 #define RESC_GROUP_PERIPHERALS_END  kResc_ROM
177 #define RESC_GROUP_PERIPHERALS_SIZE RESC_GROUP_PERIPHERALS_END - RESC_GROUP_PERIPHERALS_START + 1
178 
179 /*!
180  * @brief Structure for other peripheral resources, or bit in PDSLEEPCFG
181  *
182  */
183 typedef struct _enabled_resources
184 {
185     uint8_t group; /*!< PDSLEECFG Group for this enabled resource, SLEEPCON->SLEECFG0, PMC->PDSLEEPCFG0-5 */
186     uint32_t mask; /*!< Mask in group for this enabled resource */
187 } enabled_resources_t;
188 
189 /* Constraints used by application. */
190 #if defined(PMC0)
191 #define PM_RESC_COMP_MAINCLK_ON PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_COMP_MAINCLK)
192 #endif
193 #define PM_RESC_SENSEP_MAINCLK_ON PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SENSEP_MAINCLK)
194 #define PM_RESC_SENSES_MAINCLK_ON PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SENSES_MAINCLK)
195 #define PM_RESC_RAM0CLK_ON        PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_RAM0CLK)
196 #define PM_RESC_RAM1CLK_ON        PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_RAM1CLK)
197 #define PM_RESC_COMN_MAINCLK_ON   PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_COMN_MAINCLK)
198 #define PM_RESC_MEDIA_MAINCLK_ON  PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_MEDIA_MAINCLK)
199 #define PM_RESC_XTAL_ON           PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_XTAL)
200 #if defined(PMC0)
201 #define PM_RESC_FRO0_ON PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_FRO0)
202 #define PM_RESC_FRO1_ON PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_FRO1)
203 #endif
204 #define PM_RESC_FRO2_ON      PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_FRO2)
205 #define PM_RESC_LPOSC_ON     PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_LPOSC)
206 #define PM_RESC_PLLANA_ON    PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_PLLANA)
207 #define PM_RESC_PLLLDO_ON    PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_PLLLDO)
208 #define PM_RESC_AUDPLLANA_ON PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_AUDPLLANA)
209 #define PM_RESC_AUDPLLLDO_ON PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_AUDPLLLDO)
210 #define PM_RESC_ADC0_ON      PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_ADC0)
211 #define PM_RESC_FRO0_EN      PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_FRO0_EN)
212 #define PM_RESC_FRO2_EN      PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_FRO2_EN)
213 
214 #define PM_RESC_V2NMED_ON   PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_V2NMED)
215 #define PM_RESC_VNCOM_ON    PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_VNCOM)
216 #define PM_RESC_V2DSP_ON    PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_V2DSP)
217 #define PM_RESC_V2MIPI_ON   PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_V2MIPI)
218 #define PM_RESC_DCDC_HP     PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_DCDC_HP)
219 #define PM_RESC_PMC_TEMP_ON PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_PMC_TEMP)
220 #define PM_RESC_PMCREF_HP   PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_PMCREF_HP)
221 #define PM_RESC_HVD1V8_ON   PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_HVD1V8)
222 #define PM_RESC_PORVDD1_HP  PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_PORVDD1_HP)
223 #define PM_RESC_LVDVDD1_HP  PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_LVDVDD1_HP)
224 #define PM_RESC_HVDVDD1_ON  PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_HVDVDD1)
225 #define PM_RESC_AGDET1_ON   PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_AGDET1)
226 #define PM_RESC_PORVDD2_HP  PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_PORVDD2_HP)
227 #define PM_RESC_LVDVDD2_HP  PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_LVDVDD2_HP)
228 #define PM_RESC_HVDVDD2_ON  PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_HVDVDD2)
229 #define PM_RESC_AGDET2_ON   PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_AGDET2)
230 #define PM_RESC_PORVDDN_HP  PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_PORVDDN_HP)
231 #define PM_RESC_LVDVDDN_HP  PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_LVDVDDN_HP)
232 #define PM_RESC_HVDVDDN_ON  PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_HVDVDDN)
233 #define PM_RESC_OTP_ON      PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_OTP)
234 #define PM_RESC_ROM_ON      PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_ROM)
235 
236 #define PM_RESC_SRAM0_32KB_ACTIVE   PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM0_32KB)
237 #define PM_RESC_SRAM1_32KB_ACTIVE   PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM1_32KB)
238 #define PM_RESC_SRAM2_32KB_ACTIVE   PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM2_32KB)
239 #define PM_RESC_SRAM3_32KB_ACTIVE   PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM3_32KB)
240 #define PM_RESC_SRAM4_64KB_ACTIVE   PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM4_64KB)
241 #define PM_RESC_SRAM5_64KB_ACTIVE   PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM5_64KB)
242 #define PM_RESC_SRAM6_128KB_ACTIVE  PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM6_128KB)
243 #define PM_RESC_SRAM7_128KB_ACTIVE  PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM7_128KB)
244 #define PM_RESC_SRAM8_256KB_ACTIVE  PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM8_256KB)
245 #define PM_RESC_SRAM9_256KB_ACTIVE  PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM9_256KB)
246 #define PM_RESC_SRAM10_512KB_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM10_512KB)
247 #define PM_RESC_SRAM11_512KB_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM11_512KB)
248 #define PM_RESC_SRAM12_1MB_ACTIVE   PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM12_1MB)
249 #define PM_RESC_SRAM13_1MB_ACTIVE   PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM13_1MB)
250 #define PM_RESC_SRAM14_512KB_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM14_512KB)
251 #define PM_RESC_SRAM15_512KB_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM15_512KB)
252 #define PM_RESC_SRAM16_256KB_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM16_256KB)
253 #define PM_RESC_SRAM17_256KB_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM17_256KB)
254 #define PM_RESC_SRAM18_32KB_ACTIVE  PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM18_32KB)
255 #define PM_RESC_SRAM19_32KB_ACTIVE  PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM19_32KB)
256 #define PM_RESC_SRAM20_32KB_ACTIVE  PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM20_32KB)
257 #define PM_RESC_SRAM21_32KB_ACTIVE  PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM21_32KB)
258 #define PM_RESC_SRAM22_64KB_ACTIVE  PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM22_64KB)
259 #define PM_RESC_SRAM23_64KB_ACTIVE  PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM23_64KB)
260 #define PM_RESC_SRAM24_128KB_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM24_128KB)
261 #define PM_RESC_SRAM25_128KB_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM25_128KB)
262 #define PM_RESC_SRAM26_512KB_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM26_512KB)
263 #define PM_RESC_SRAM27_512KB_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM27_512KB)
264 #define PM_RESC_SRAM28_256KB_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM28_256KB)
265 #define PM_RESC_SRAM29_256KB_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM29_256KB)
266 
267 #define PM_RESC_SRAM0_32KB_RETENTION   PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM0_32KB)
268 #define PM_RESC_SRAM1_32KB_RETENTION   PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM1_32KB)
269 #define PM_RESC_SRAM2_32KB_RETENTION   PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM2_32KB)
270 #define PM_RESC_SRAM3_32KB_RETENTION   PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM3_32KB)
271 #define PM_RESC_SRAM4_64KB_RETENTION   PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM4_64KB)
272 #define PM_RESC_SRAM5_64KB_RETENTION   PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM5_64KB)
273 #define PM_RESC_SRAM6_128KB_RETENTION  PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM6_128KB)
274 #define PM_RESC_SRAM7_128KB_RETENTION  PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM7_128KB)
275 #define PM_RESC_SRAM8_256KB_RETENTION  PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM8_256KB)
276 #define PM_RESC_SRAM9_256KB_RETENTION  PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM9_256KB)
277 #define PM_RESC_SRAM10_512KB_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM10_512KB)
278 #define PM_RESC_SRAM11_512KB_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM11_512KB)
279 #define PM_RESC_SRAM12_1MB_RETENTION   PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM12_1MB)
280 #define PM_RESC_SRAM13_1MB_RETENTION   PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM13_1MB)
281 #define PM_RESC_SRAM14_512KB_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM14_512KB)
282 #define PM_RESC_SRAM15_512KB_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM15_512KB)
283 #define PM_RESC_SRAM16_256KB_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM16_256KB)
284 #define PM_RESC_SRAM17_256KB_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM17_256KB)
285 #define PM_RESC_SRAM18_32KB_RETENTION  PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM18_32KB)
286 #define PM_RESC_SRAM19_32KB_RETENTION  PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM19_32KB)
287 #define PM_RESC_SRAM20_32KB_RETENTION  PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM20_32KB)
288 #define PM_RESC_SRAM21_32KB_RETENTION  PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM21_32KB)
289 #define PM_RESC_SRAM22_64KB_RETENTION  PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM22_64KB)
290 #define PM_RESC_SRAM23_64KB_RETENTION  PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM23_64KB)
291 #define PM_RESC_SRAM24_128KB_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM24_128KB)
292 #define PM_RESC_SRAM25_128KB_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM25_128KB)
293 #define PM_RESC_SRAM26_512KB_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM26_512KB)
294 #define PM_RESC_SRAM27_512KB_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM27_512KB)
295 #define PM_RESC_SRAM28_256KB_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM28_256KB)
296 #define PM_RESC_SRAM29_256KB_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM29_256KB)
297 
298 #define PM_RESC_SRAM_USDHC0_ACTIVE      PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM_USDHC0)
299 #define PM_RESC_SRAM_USDHC1_ACTIVE      PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM_USDHC1)
300 #define PM_RESC_SRAM_USB0_ACTIVE        PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM_USB0)
301 #define PM_RESC_SRAM_USB1_ACTIVE        PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM_USB1)
302 #define PM_RESC_SRAM_JPEGDEC_ACTIVE     PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM_JPEGDEC)
303 #define PM_RESC_SRAM_PNGDEC_ACTIVE      PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM_PNGDEC)
304 #define PM_RESC_SRAM_MIPI_ACTIVE        PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM_MIPI)
305 #define PM_RESC_SRAM_GPU_ACTIVE         PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM_GPU)
306 #define PM_RESC_SRAM_DMA23_ACTIVE       PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM_DMA23)
307 #define PM_RESC_SRAM_DMA01PE_ACTIVE     PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM_DMA01PE)
308 #define PM_RESC_SRAM_CPU0_ICACHE_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM_CPU0_ICACHE)
309 #define PM_RESC_SRAM_CPU0_DCACHE_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM_CPU0_DCACHE)
310 #define PM_RESC_SRAM_DSP_ICACHE_ACTIVE  PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM_DSP_ICACHE)
311 #define PM_RESC_SRAM_DSP_DCACHE_ACTIVE  PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM_DSP_DCACHE)
312 #define PM_RESC_SRAM_DSP_ITCM_ACTIVE    PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM_DSP_ITCM)
313 #define PM_RESC_SRAM_DSP_DTCM_ACTIVE    PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM_DSP_DTCM)
314 #define PM_RESC_SRAM_EZHV_ACTIVE        PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM_EZHV)
315 #define PM_RESC_SRAM_NPU_ACTIVE         PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM_NPU)
316 #define PM_RESC_SRAM_XSPI0_ACTIVE       PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM_XSPI0)
317 #define PM_RESC_SRAM_XSPI1_ACTIVE       PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM_XSPI1)
318 #define PM_RESC_SRAM_XSPI2_ACTIVE       PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM_XSPI2)
319 #define PM_RESC_SRAM_LCDIF_ACTIVE       PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM_LCDIF)
320 #define PM_RESC_SRAM_OCOTP_ACTIVE       PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM_OCOTP)
321 
322 #define PM_RESC_SRAM_USDHC0_RETENTION      PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM_USDHC0)
323 #define PM_RESC_SRAM_USDHC1_RETENTION      PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM_USDHC1)
324 #define PM_RESC_SRAM_USB0_RETENTION        PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM_USB0)
325 #define PM_RESC_SRAM_USB1_RETENTION        PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM_USB1)
326 #define PM_RESC_SRAM_JPEGDEC_RETENTION     PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM_JPEGDEC)
327 #define PM_RESC_SRAM_PNGDEC_RETENTION      PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM_PNGDEC)
328 #define PM_RESC_SRAM_MIPI_RETENTION        PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM_MIPI)
329 #define PM_RESC_SRAM_GPU_RETENTION         PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM_GPU)
330 #define PM_RESC_SRAM_DMA23_RETENTION       PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM_DMA23)
331 #define PM_RESC_SRAM_DMA01PE_RETENTION     PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM_DMA01PE)
332 #define PM_RESC_SRAM_CPU0_ICACHE_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM_CPU0_ICACHE)
333 #define PM_RESC_SRAM_CPU0_DCACHE_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM_CPU0_DCACHE)
334 #define PM_RESC_SRAM_DSP_ICACHE_RETENTION  PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM_DSP_ICACHE)
335 #define PM_RESC_SRAM_DSP_DCACHE_RETENTION  PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM_DSP_DCACHE)
336 #define PM_RESC_SRAM_DSP_ITCM_RETENTION    PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM_DSP_ITCM)
337 #define PM_RESC_SRAM_DSP_DTCM_RETENTION    PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM_DSP_DTCM)
338 #define PM_RESC_SRAM_EZHV_RETENTION        PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM_EZHV)
339 #define PM_RESC_SRAM_NPU_RETENTION         PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM_NPU)
340 #define PM_RESC_SRAM_XSPI0_RETENTION       PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM_XSPI0)
341 #define PM_RESC_SRAM_XSPI1_RETENTION       PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM_XSPI1)
342 #define PM_RESC_SRAM_XSPI2_RETENTION       PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM_XSPI2)
343 #define PM_RESC_SRAM_LCDIF_RETENTION       PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM_LCDIF)
344 #define PM_RESC_SRAM_OCOTP_RETENTION       PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM_OCOTP)
345 
346 #endif /* _FSL_PM_DEVICE_H_ */
347