/* * Copyright 2024 NXP * * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_PM_DEVICE_H_ #define _FSL_PM_DEVICE_H_ #include "fsl_common.h" #include "fsl_pm_config.h" /*! * @addtogroup PM Framework: Power Manager Framework * @brief This section includes Power Mode macros, System Constraints macros, and Wakeup source macros. * @{ */ /*! * @name Power Mode Definition * @{ */ /* Power Mode Index */ #define PM_LP_STATE_SLEEP (0U) #define PM_LP_STATE_DEEP_SLEEP (1U) #define PM_LP_STATE_DSR (2U) #define PM_LP_STATE_DEEP_POWER_DOWN (3U) #define PM_LP_STATE_FULL_DEEP_POWER_DOWN (4U) #define PM_LP_STATE_NO_CONSTRAINT (0xFFU) /*! @} */ /* Helper macros */ #define PM_RESC_MASK(resc_masks, resc) \ (((resc_masks)->rescMask[(uint32_t)(resc) / 32U] >> ((uint32_t)(resc) % 32U)) & 1U) #define PM_RESC_GROUP(resc_groups, resc) \ (((resc_groups)->groupSlice[(uint32_t)(resc) / 8U] >> (4U * ((uint32_t)(resc) % 8U))) & 0xFU) /*! * @name System basic resource constraints definitions. * @{ */ /*! @brief Available constraints for resources * * The constraints below are grouped together in 3 groups */ typedef enum _resc_name { /* Peripherals and RAMs that do not have separate retention bit in SLEEPCON */ #if defined(PMC0) kResc_COMP_MAINCLK = 0, /*!< Compute Main Clock */ kResc_SENSEP_MAINCLK, /*!< VDD1_SENSE Domain private main clock */ #else kResc_SENSEP_MAINCLK = 0, /*!< VDD1_SENSE Domain private main clock */ #endif kResc_SENSES_MAINCLK, /*!< VDD1_SENSE Domain shared main clock */ kResc_RAM0CLK, /*!< RAM_ARBITER0 common_ram_clk */ kResc_RAM1CLK, /*!< RAM_ARBITER1 sense_ram_clk */ kResc_COMN_MAINCLK, /*!< VDDN_COM Domain common_vddn_clk */ kResc_MEDIA_MAINCLK, /*!< VDD2_MEDIA and VDDN_MEDIA Domains media_main_clk and media_vddn_clk */ kResc_XTAL, /*!< XTAL */ #if defined(PMC0) kResc_FRO0, /*!< FRO0 power control */ kResc_FRO1, /*!< FRO1 power control*/ #endif kResc_FRO2, /*!< FRO2 */ kResc_LPOSC, /*!< LPOSC */ kResc_PLLANA, /*!< PLLANA */ kResc_PLLLDO, /*!< PLLLDO */ kResc_AUDPLLANA, /*!< AUDPLLANA */ kResc_AUDPLLLDO, /*!< AUDPLLLDO */ kResc_ADC0, /*!< ADC0 */ #if defined(PMC0) kResc_FRO0_EN, /*!< FRO0 gate control */ #endif kResc_FRO2_EN, /*!< FRO2 gate control */ /* Peripherals and RAMs that do not have separate retention bit in PMC PDSLEECFG0-1 */ kResc_V2NMED, /*!< Power Switch and DSR for VDD2 and VDDN Media */ kResc_VNCOM, /*!< Power Switch and DSR for VDDN_COM */ kResc_V2DSP, /*!< Power Switch and DSR for VDD2_DSP */ kResc_V2MIPI, /*!< Power Switch for MIPI PHY */ kResc_DCDC_HP, /*!< DCDC in high-power mode */ kResc_PMC_TEMP, /*!< PMC Temperature sensor */ kResc_PMCREF_HP, /*!< PMC Reference */ kResc_HVD1V8, /*!< 1.8V High-Voltage Detect */ kResc_PORVDD1_HP, /*!< VDD1 Power-On Reset monitor */ kResc_LVDVDD1_HP, /*!< VDD1 Low-Voltage Dectect */ kResc_HVDVDD1, /*!< VDD1 High-Voltage Dectect */ kResc_AGDET1, /*!< VDD1 analog glitch detect */ kResc_PORVDD2_HP, /*!< VDD2 Power-On Reset monitor */ kResc_LVDVDD2_HP, /*!< VDD2 Low-Voltage Dectect */ kResc_HVDVDD2, /*!< VDD2 High-Voltage Dectect */ kResc_AGDET2, /*!< VDD2 analog glitch detect */ kResc_PORVDDN_HP, /*!< VDDN Power-On Reset monitor */ kResc_LVDVDDN_HP, /*!< VDDN Low-Voltage Dectect */ kResc_HVDVDDN, /*!< VDDN High-Voltage Dectect */ kResc_OTP, /*!< OTP */ kResc_ROM, /*!< ROM */ /* System SRAMs that have bits in both PDSLEEPCFG2 & 3 */ kResc_SRAM0_32KB, /*!< SRAM partition0 */ kResc_SRAM1_32KB, /*!< SRAM partition1 */ kResc_SRAM2_32KB, /*!< SRAM partition2 */ kResc_SRAM3_32KB, /*!< SRAM partition3 */ kResc_SRAM4_64KB, /*!< SRAM partition4 */ kResc_SRAM5_64KB, /*!< SRAM partition5 */ kResc_SRAM6_128KB, /*!< SRAM partition6 */ kResc_SRAM7_128KB, /*!< SRAM partition7 */ kResc_SRAM8_256KB, /*!< SRAM partition8 */ kResc_SRAM9_256KB, /*!< SRAM partition9 */ kResc_SRAM10_512KB, /*!< SRAM partition10 */ kResc_SRAM11_512KB, /*!< SRAM partition11 */ kResc_SRAM12_1MB, /*!< SRAM partition12 */ kResc_SRAM13_1MB, /*!< SRAM partition13 */ kResc_SRAM14_512KB, /*!< SRAM partition14 */ kResc_SRAM15_512KB, /*!< SRAM partition15 */ kResc_SRAM16_256KB, /*!< SRAM partition16 */ kResc_SRAM17_256KB, /*!< SRAM partition17 */ kResc_SRAM18_32KB, /*!< SRAM partition18 */ kResc_SRAM19_32KB, /*!< SRAM partition19 */ kResc_SRAM20_32KB, /*!< SRAM partition20 */ kResc_SRAM21_32KB, /*!< SRAM partition21 */ kResc_SRAM22_64KB, /*!< SRAM partition22 */ kResc_SRAM23_64KB, /*!< SRAM partition23 */ kResc_SRAM24_128KB, /*!< SRAM partition24 */ kResc_SRAM25_128KB, /*!< SRAM partition25 */ kResc_SRAM26_512KB, /*!< SRAM partition26 */ kResc_SRAM27_512KB, /*!< SRAM partition27 */ kResc_SRAM28_256KB, /*!< SRAM partition28 */ kResc_SRAM29_256KB, /*!< SRAM partition29 */ /* dedicated peripheral SRAMs that have 2 bits each in PDSLEEPCFG4 & 5 */ kResc_SRAM_USDHC0, /*!< uSDHC0 SRAM */ kResc_SRAM_USDHC1, /*!< uSDHC1 SRAM */ kResc_SRAM_USB0, /*!< USB0 SRAM */ kResc_SRAM_USB1, /*!< USB1 SRAM */ kResc_SRAM_JPEGDEC, /*!< JPEGDEC SRAM */ kResc_SRAM_PNGDEC, /*!< PNGDEC SRAM */ kResc_SRAM_MIPI, /*!< MIPI PHY SRAM */ kResc_SRAM_GPU, /*!< VGPU SRAM */ kResc_SRAM_DMA23, /*!< DMA2 and DMA3 SRAM */ kResc_SRAM_DMA01PE, /*!< DMA0-1, PKC, and ETF SRAM */ kResc_SRAM_CPU0_ICACHE, /*!< CPU0 Code cache RAM */ kResc_SRAM_CPU0_DCACHE, /*!< CPU0 System cache RAM */ kResc_SRAM_DSP_ICACHE, /*!< HiFi4 instruction cache RAM*/ kResc_SRAM_DSP_DCACHE, /*!< HiFi4 data cache RAM */ kResc_SRAM_DSP_ITCM, /*!< HiFi4 instruction TCM RAM*/ kResc_SRAM_DSP_DTCM, /*!< HiFi4 data TCM RAM */ kResc_SRAM_EZHV, /*!< EZHV TCM RAM */ kResc_SRAM_NPU, /*!< NPU TCM RAM */ kResc_SRAM_XSPI0, /*!< XSPI0, MMU0 and Cache SRAM */ kResc_SRAM_XSPI1, /*!< XSPI1, MMU1 and Cache SRAM */ kResc_SRAM_XSPI2, /*!< XSPI2 and MMU2 SRAM */ kResc_SRAM_LCDIF, /*!< LCDIF SRAM */ kResc_SRAM_OCOTP, /*!< OCOTP SRAM */ kResc_MaxNum, /*!< Maximum number of supported constraints */ } resc_name_t; /* Macros for Resource Constraint Group Types */ #define RESC_GROUP_SRAMS_START kResc_SRAM0_32KB #define RESC_GROUP_SRAMS_END kResc_SRAM_OCOTP #define RESC_GROUP_SRAMS_SIZE RESC_GROUP_SRAMS_END - RESC_GROUP_SRAMS_START + 1 #if defined(PMC0) #define RESC_GROUP_PERIPHERALS_START kResc_COMP_MAINCLK #else #define RESC_GROUP_PERIPHERALS_START kResc_SENSEP_MAINCLK #endif #define RESC_GROUP_PERIPHERALS_END kResc_ROM #define RESC_GROUP_PERIPHERALS_SIZE RESC_GROUP_PERIPHERALS_END - RESC_GROUP_PERIPHERALS_START + 1 /*! * @brief Structure for other peripheral resources, or bit in PDSLEEPCFG * */ typedef struct _enabled_resources { uint8_t group; /*!< PDSLEECFG Group for this enabled resource, SLEEPCON->SLEECFG0, PMC->PDSLEEPCFG0-5 */ uint32_t mask; /*!< Mask in group for this enabled resource */ } enabled_resources_t; /* Constraints used by application. */ #if defined(PMC0) #define PM_RESC_COMP_MAINCLK_ON PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_COMP_MAINCLK) #endif #define PM_RESC_SENSEP_MAINCLK_ON PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SENSEP_MAINCLK) #define PM_RESC_SENSES_MAINCLK_ON PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SENSES_MAINCLK) #define PM_RESC_RAM0CLK_ON PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_RAM0CLK) #define PM_RESC_RAM1CLK_ON PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_RAM1CLK) #define PM_RESC_COMN_MAINCLK_ON PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_COMN_MAINCLK) #define PM_RESC_MEDIA_MAINCLK_ON PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_MEDIA_MAINCLK) #define PM_RESC_XTAL_ON PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_XTAL) #if defined(PMC0) #define PM_RESC_FRO0_ON PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_FRO0) #define PM_RESC_FRO1_ON PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_FRO1) #endif #define PM_RESC_FRO2_ON PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_FRO2) #define PM_RESC_LPOSC_ON PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_LPOSC) #define PM_RESC_PLLANA_ON PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_PLLANA) #define PM_RESC_PLLLDO_ON PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_PLLLDO) #define PM_RESC_AUDPLLANA_ON PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_AUDPLLANA) #define PM_RESC_AUDPLLLDO_ON PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_AUDPLLLDO) #define PM_RESC_ADC0_ON PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_ADC0) #define PM_RESC_FRO0_EN PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_FRO0_EN) #define PM_RESC_FRO2_EN PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_FRO2_EN) #define PM_RESC_V2NMED_ON PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_V2NMED) #define PM_RESC_VNCOM_ON PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_VNCOM) #define PM_RESC_V2DSP_ON PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_V2DSP) #define PM_RESC_V2MIPI_ON PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_V2MIPI) #define PM_RESC_DCDC_HP PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_DCDC_HP) #define PM_RESC_PMC_TEMP_ON PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_PMC_TEMP) #define PM_RESC_PMCREF_HP PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_PMCREF_HP) #define PM_RESC_HVD1V8_ON PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_HVD1V8) #define PM_RESC_PORVDD1_HP PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_PORVDD1_HP) #define PM_RESC_LVDVDD1_HP PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_LVDVDD1_HP) #define PM_RESC_HVDVDD1_ON PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_HVDVDD1) #define PM_RESC_AGDET1_ON PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_AGDET1) #define PM_RESC_PORVDD2_HP PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_PORVDD2_HP) #define PM_RESC_LVDVDD2_HP PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_LVDVDD2_HP) #define PM_RESC_HVDVDD2_ON PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_HVDVDD2) #define PM_RESC_AGDET2_ON PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_AGDET2) #define PM_RESC_PORVDDN_HP PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_PORVDDN_HP) #define PM_RESC_LVDVDDN_HP PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_LVDVDDN_HP) #define PM_RESC_HVDVDDN_ON PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_HVDVDDN) #define PM_RESC_OTP_ON PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_OTP) #define PM_RESC_ROM_ON PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_ROM) #define PM_RESC_SRAM0_32KB_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM0_32KB) #define PM_RESC_SRAM1_32KB_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM1_32KB) #define PM_RESC_SRAM2_32KB_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM2_32KB) #define PM_RESC_SRAM3_32KB_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM3_32KB) #define PM_RESC_SRAM4_64KB_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM4_64KB) #define PM_RESC_SRAM5_64KB_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM5_64KB) #define PM_RESC_SRAM6_128KB_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM6_128KB) #define PM_RESC_SRAM7_128KB_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM7_128KB) #define PM_RESC_SRAM8_256KB_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM8_256KB) #define PM_RESC_SRAM9_256KB_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM9_256KB) #define PM_RESC_SRAM10_512KB_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM10_512KB) #define PM_RESC_SRAM11_512KB_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM11_512KB) #define PM_RESC_SRAM12_1MB_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM12_1MB) #define PM_RESC_SRAM13_1MB_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM13_1MB) #define PM_RESC_SRAM14_512KB_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM14_512KB) #define PM_RESC_SRAM15_512KB_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM15_512KB) #define PM_RESC_SRAM16_256KB_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM16_256KB) #define PM_RESC_SRAM17_256KB_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM17_256KB) #define PM_RESC_SRAM18_32KB_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM18_32KB) #define PM_RESC_SRAM19_32KB_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM19_32KB) #define PM_RESC_SRAM20_32KB_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM20_32KB) #define PM_RESC_SRAM21_32KB_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM21_32KB) #define PM_RESC_SRAM22_64KB_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM22_64KB) #define PM_RESC_SRAM23_64KB_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM23_64KB) #define PM_RESC_SRAM24_128KB_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM24_128KB) #define PM_RESC_SRAM25_128KB_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM25_128KB) #define PM_RESC_SRAM26_512KB_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM26_512KB) #define PM_RESC_SRAM27_512KB_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM27_512KB) #define PM_RESC_SRAM28_256KB_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM28_256KB) #define PM_RESC_SRAM29_256KB_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM29_256KB) #define PM_RESC_SRAM0_32KB_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM0_32KB) #define PM_RESC_SRAM1_32KB_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM1_32KB) #define PM_RESC_SRAM2_32KB_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM2_32KB) #define PM_RESC_SRAM3_32KB_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM3_32KB) #define PM_RESC_SRAM4_64KB_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM4_64KB) #define PM_RESC_SRAM5_64KB_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM5_64KB) #define PM_RESC_SRAM6_128KB_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM6_128KB) #define PM_RESC_SRAM7_128KB_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM7_128KB) #define PM_RESC_SRAM8_256KB_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM8_256KB) #define PM_RESC_SRAM9_256KB_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM9_256KB) #define PM_RESC_SRAM10_512KB_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM10_512KB) #define PM_RESC_SRAM11_512KB_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM11_512KB) #define PM_RESC_SRAM12_1MB_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM12_1MB) #define PM_RESC_SRAM13_1MB_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM13_1MB) #define PM_RESC_SRAM14_512KB_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM14_512KB) #define PM_RESC_SRAM15_512KB_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM15_512KB) #define PM_RESC_SRAM16_256KB_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM16_256KB) #define PM_RESC_SRAM17_256KB_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM17_256KB) #define PM_RESC_SRAM18_32KB_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM18_32KB) #define PM_RESC_SRAM19_32KB_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM19_32KB) #define PM_RESC_SRAM20_32KB_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM20_32KB) #define PM_RESC_SRAM21_32KB_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM21_32KB) #define PM_RESC_SRAM22_64KB_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM22_64KB) #define PM_RESC_SRAM23_64KB_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM23_64KB) #define PM_RESC_SRAM24_128KB_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM24_128KB) #define PM_RESC_SRAM25_128KB_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM25_128KB) #define PM_RESC_SRAM26_512KB_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM26_512KB) #define PM_RESC_SRAM27_512KB_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM27_512KB) #define PM_RESC_SRAM28_256KB_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM28_256KB) #define PM_RESC_SRAM29_256KB_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM29_256KB) #define PM_RESC_SRAM_USDHC0_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM_USDHC0) #define PM_RESC_SRAM_USDHC1_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM_USDHC1) #define PM_RESC_SRAM_USB0_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM_USB0) #define PM_RESC_SRAM_USB1_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM_USB1) #define PM_RESC_SRAM_JPEGDEC_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM_JPEGDEC) #define PM_RESC_SRAM_PNGDEC_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM_PNGDEC) #define PM_RESC_SRAM_MIPI_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM_MIPI) #define PM_RESC_SRAM_GPU_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM_GPU) #define PM_RESC_SRAM_DMA23_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM_DMA23) #define PM_RESC_SRAM_DMA01PE_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM_DMA01PE) #define PM_RESC_SRAM_CPU0_ICACHE_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM_CPU0_ICACHE) #define PM_RESC_SRAM_CPU0_DCACHE_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM_CPU0_DCACHE) #define PM_RESC_SRAM_DSP_ICACHE_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM_DSP_ICACHE) #define PM_RESC_SRAM_DSP_DCACHE_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM_DSP_DCACHE) #define PM_RESC_SRAM_DSP_ITCM_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM_DSP_ITCM) #define PM_RESC_SRAM_DSP_DTCM_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM_DSP_DTCM) #define PM_RESC_SRAM_EZHV_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM_EZHV) #define PM_RESC_SRAM_NPU_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM_NPU) #define PM_RESC_SRAM_XSPI0_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM_XSPI0) #define PM_RESC_SRAM_XSPI1_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM_XSPI1) #define PM_RESC_SRAM_XSPI2_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM_XSPI2) #define PM_RESC_SRAM_LCDIF_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM_LCDIF) #define PM_RESC_SRAM_OCOTP_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM_OCOTP) #define PM_RESC_SRAM_USDHC0_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM_USDHC0) #define PM_RESC_SRAM_USDHC1_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM_USDHC1) #define PM_RESC_SRAM_USB0_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM_USB0) #define PM_RESC_SRAM_USB1_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM_USB1) #define PM_RESC_SRAM_JPEGDEC_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM_JPEGDEC) #define PM_RESC_SRAM_PNGDEC_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM_PNGDEC) #define PM_RESC_SRAM_MIPI_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM_MIPI) #define PM_RESC_SRAM_GPU_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM_GPU) #define PM_RESC_SRAM_DMA23_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM_DMA23) #define PM_RESC_SRAM_DMA01PE_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM_DMA01PE) #define PM_RESC_SRAM_CPU0_ICACHE_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM_CPU0_ICACHE) #define PM_RESC_SRAM_CPU0_DCACHE_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM_CPU0_DCACHE) #define PM_RESC_SRAM_DSP_ICACHE_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM_DSP_ICACHE) #define PM_RESC_SRAM_DSP_DCACHE_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM_DSP_DCACHE) #define PM_RESC_SRAM_DSP_ITCM_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM_DSP_ITCM) #define PM_RESC_SRAM_DSP_DTCM_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM_DSP_DTCM) #define PM_RESC_SRAM_EZHV_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM_EZHV) #define PM_RESC_SRAM_NPU_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM_NPU) #define PM_RESC_SRAM_XSPI0_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM_XSPI0) #define PM_RESC_SRAM_XSPI1_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM_XSPI1) #define PM_RESC_SRAM_XSPI2_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM_XSPI2) #define PM_RESC_SRAM_LCDIF_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM_LCDIF) #define PM_RESC_SRAM_OCOTP_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM_OCOTP) #endif /* _FSL_PM_DEVICE_H_ */