1/* 2 * Copyright (c) 2022, NXP 3 * SPDX-License-Identifier: Apache-2.0 4 * 5 * Note: File generated by imx_cfg_utils.py 6 * from configuration data for MIMX8ML8DVNLZ 7 */ 8 9/* 10 * SOC level pinctrl defintions 11 * These definitions define SOC level defaults for each pin, 12 * and select the pinmux for the pin. Pinmux entries are a tuple of: 13 * <mux_register mux_mode input_register input_daisy config_register> 14 * the mux_register and input_daisy reside in the IOMUXC peripheral, and 15 * the pinctrl driver will write the mux_mode and input_daisy values into 16 * each register, respectively. The config_register is used to configure 17 * the pin based on the devicetree properties set 18 */ 19 20&iomuxc { 21 /omit-if-no-ref/ iomuxc_boot_mode0_src_boot_mode_src_boot_mode0: IOMUXC_BOOT_MODE0_SRC_BOOT_MODE_SRC_BOOT_MODE0 { 22 pinmux = <0x0 0 0x0 0 0x30330250>; 23 }; 24 /omit-if-no-ref/ iomuxc_boot_mode1_src_boot_mode_src_boot_mode1: IOMUXC_BOOT_MODE1_SRC_BOOT_MODE_SRC_BOOT_MODE1 { 25 pinmux = <0x0 0 0x0 0 0x30330254>; 26 }; 27 /omit-if-no-ref/ iomuxc_boot_mode2_src_boot_mode_src_boot_mode2: IOMUXC_BOOT_MODE2_SRC_BOOT_MODE_SRC_BOOT_MODE2 { 28 pinmux = <0x0 0 0x0 0 0x30330258>; 29 }; 30 /omit-if-no-ref/ iomuxc_boot_mode3_src_boot_mode_src_boot_mode3: IOMUXC_BOOT_MODE3_SRC_BOOT_MODE_SRC_BOOT_MODE3 { 31 pinmux = <0x0 0 0x0 0 0x3033025c>; 32 }; 33 /omit-if-no-ref/ iomuxc_ecspi1_miso_ecspi_miso_ecspi1_miso: IOMUXC_ECSPI1_MISO_ECSPI_MISO_ECSPI1_MISO { 34 pinmux = <0x303301e8 0 0x3033055c 0 0x30330448>; 35 }; 36 /omit-if-no-ref/ iomuxc_ecspi1_miso_gpio_io_gpio5_io8: IOMUXC_ECSPI1_MISO_GPIO_IO_GPIO5_IO8 { 37 pinmux = <0x303301e8 5 0x0 0 0x30330448>; 38 }; 39 /omit-if-no-ref/ iomuxc_ecspi1_miso_i2c_scl_i2c2_scl: IOMUXC_ECSPI1_MISO_I2C_SCL_I2C2_SCL { 40 pinmux = <0x303301e8 2 0x303305ac 1 0x30330448>; 41 }; 42 /omit-if-no-ref/ iomuxc_ecspi1_miso_sai_rx_data_sai7_rx_data0: IOMUXC_ECSPI1_MISO_SAI_RX_DATA_SAI7_RX_DATA0 { 43 pinmux = <0x303301e8 3 0x30330534 1 0x30330448>; 44 }; 45 /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_cts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_CTS_B_UART3_CTS_B { 46 pinmux = <0x303301e8 1 0x0 0 0x30330448>; 47 }; 48 /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_rts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_RTS_B_UART3_CTS_B { 49 pinmux = <0x303301e8 1 0x303305f4 2 0x30330448>; 50 }; 51 /omit-if-no-ref/ iomuxc_ecspi1_mosi_ecspi_mosi_ecspi1_mosi: IOMUXC_ECSPI1_MOSI_ECSPI_MOSI_ECSPI1_MOSI { 52 pinmux = <0x303301e4 0 0x30330560 0 0x30330444>; 53 }; 54 /omit-if-no-ref/ iomuxc_ecspi1_mosi_gpio_io_gpio5_io7: IOMUXC_ECSPI1_MOSI_GPIO_IO_GPIO5_IO7 { 55 pinmux = <0x303301e4 5 0x0 0 0x30330444>; 56 }; 57 /omit-if-no-ref/ iomuxc_ecspi1_mosi_i2c_sda_i2c1_sda: IOMUXC_ECSPI1_MOSI_I2C_SDA_I2C1_SDA { 58 pinmux = <0x303301e4 2 0x303305a8 1 0x30330444>; 59 }; 60 /omit-if-no-ref/ iomuxc_ecspi1_mosi_sai_rx_bclk_sai7_rx_bclk: IOMUXC_ECSPI1_MOSI_SAI_RX_BCLK_SAI7_RX_BCLK { 61 pinmux = <0x303301e4 3 0x30330530 1 0x30330444>; 62 }; 63 /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_rx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_RX_UART3_TX { 64 pinmux = <0x303301e4 1 0x303305f8 5 0x30330444>; 65 }; 66 /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_tx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_TX_UART3_TX { 67 pinmux = <0x303301e4 1 0x0 0 0x30330444>; 68 }; 69 /omit-if-no-ref/ iomuxc_ecspi1_sclk_ecspi_sclk_ecspi1_sclk: IOMUXC_ECSPI1_SCLK_ECSPI_SCLK_ECSPI1_SCLK { 70 pinmux = <0x303301e0 0 0x30330558 0 0x30330440>; 71 }; 72 /omit-if-no-ref/ iomuxc_ecspi1_sclk_gpio_io_gpio5_io6: IOMUXC_ECSPI1_SCLK_GPIO_IO_GPIO5_IO6 { 73 pinmux = <0x303301e0 5 0x0 0 0x30330440>; 74 }; 75 /omit-if-no-ref/ iomuxc_ecspi1_sclk_i2c_scl_i2c1_scl: IOMUXC_ECSPI1_SCLK_I2C_SCL_I2C1_SCL { 76 pinmux = <0x303301e0 2 0x303305a4 1 0x30330440>; 77 }; 78 /omit-if-no-ref/ iomuxc_ecspi1_sclk_sai_rx_sync_sai7_rx_sync: IOMUXC_ECSPI1_SCLK_SAI_RX_SYNC_SAI7_RX_SYNC { 79 pinmux = <0x303301e0 3 0x30330538 1 0x30330440>; 80 }; 81 /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_rx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_RX_UART3_RX { 82 pinmux = <0x303301e0 1 0x303305f8 4 0x30330440>; 83 }; 84 /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_tx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_TX_UART3_RX { 85 pinmux = <0x303301e0 1 0x0 0 0x30330440>; 86 }; 87 /omit-if-no-ref/ iomuxc_ecspi1_ss0_ecspi_ss_ecspi1_ss0: IOMUXC_ECSPI1_SS0_ECSPI_SS_ECSPI1_SS0 { 88 pinmux = <0x303301ec 0 0x30330564 0 0x3033044c>; 89 }; 90 /omit-if-no-ref/ iomuxc_ecspi1_ss0_gpio_io_gpio5_io9: IOMUXC_ECSPI1_SS0_GPIO_IO_GPIO5_IO9 { 91 pinmux = <0x303301ec 5 0x0 0 0x3033044c>; 92 }; 93 /omit-if-no-ref/ iomuxc_ecspi1_ss0_i2c_sda_i2c2_sda: IOMUXC_ECSPI1_SS0_I2C_SDA_I2C2_SDA { 94 pinmux = <0x303301ec 2 0x303305b0 1 0x3033044c>; 95 }; 96 /omit-if-no-ref/ iomuxc_ecspi1_ss0_sai_tx_sync_sai7_tx_sync: IOMUXC_ECSPI1_SS0_SAI_TX_SYNC_SAI7_TX_SYNC { 97 pinmux = <0x303301ec 3 0x30330540 1 0x3033044c>; 98 }; 99 /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_cts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_CTS_B_UART3_RTS_B { 100 pinmux = <0x303301ec 1 0x0 0 0x3033044c>; 101 }; 102 /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_rts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_RTS_B_UART3_RTS_B { 103 pinmux = <0x303301ec 1 0x303305f4 3 0x3033044c>; 104 }; 105 /omit-if-no-ref/ iomuxc_ecspi2_miso_ccm_clko_ccm_clko1: IOMUXC_ECSPI2_MISO_CCM_CLKO_CCM_CLKO1 { 106 pinmux = <0x303301f8 4 0x0 0 0x30330458>; 107 }; 108 /omit-if-no-ref/ iomuxc_ecspi2_miso_ecspi_miso_ecspi2_miso: IOMUXC_ECSPI2_MISO_ECSPI_MISO_ECSPI2_MISO { 109 pinmux = <0x303301f8 0 0x3033056c 1 0x30330458>; 110 }; 111 /omit-if-no-ref/ iomuxc_ecspi2_miso_gpio_io_gpio5_io12: IOMUXC_ECSPI2_MISO_GPIO_IO_GPIO5_IO12 { 112 pinmux = <0x303301f8 5 0x0 0 0x30330458>; 113 }; 114 /omit-if-no-ref/ iomuxc_ecspi2_miso_i2c_scl_i2c4_scl: IOMUXC_ECSPI2_MISO_I2C_SCL_I2C4_SCL { 115 pinmux = <0x303301f8 2 0x303305bc 4 0x30330458>; 116 }; 117 /omit-if-no-ref/ iomuxc_ecspi2_miso_sai_mclk_sai7_mclk: IOMUXC_ECSPI2_MISO_SAI_MCLK_SAI7_MCLK { 118 pinmux = <0x303301f8 3 0x3033052c 1 0x30330458>; 119 }; 120 /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_cts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_CTS_B_UART4_CTS_B { 121 pinmux = <0x303301f8 1 0x0 0 0x30330458>; 122 }; 123 /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_rts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_RTS_B_UART4_CTS_B { 124 pinmux = <0x303301f8 1 0x303305fc 2 0x30330458>; 125 }; 126 /omit-if-no-ref/ iomuxc_ecspi2_mosi_ecspi_mosi_ecspi2_mosi: IOMUXC_ECSPI2_MOSI_ECSPI_MOSI_ECSPI2_MOSI { 127 pinmux = <0x303301f4 0 0x30330570 1 0x30330454>; 128 }; 129 /omit-if-no-ref/ iomuxc_ecspi2_mosi_gpio_io_gpio5_io11: IOMUXC_ECSPI2_MOSI_GPIO_IO_GPIO5_IO11 { 130 pinmux = <0x303301f4 5 0x0 0 0x30330454>; 131 }; 132 /omit-if-no-ref/ iomuxc_ecspi2_mosi_i2c_sda_i2c3_sda: IOMUXC_ECSPI2_MOSI_I2C_SDA_I2C3_SDA { 133 pinmux = <0x303301f4 2 0x303305b8 3 0x30330454>; 134 }; 135 /omit-if-no-ref/ iomuxc_ecspi2_mosi_sai_tx_data_sai7_tx_data0: IOMUXC_ECSPI2_MOSI_SAI_TX_DATA_SAI7_TX_DATA0 { 136 pinmux = <0x303301f4 3 0x0 0 0x30330454>; 137 }; 138 /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_rx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_RX_UART4_TX { 139 pinmux = <0x303301f4 1 0x30330600 7 0x30330454>; 140 }; 141 /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_tx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_TX_UART4_TX { 142 pinmux = <0x303301f4 1 0x0 0 0x30330454>; 143 }; 144 /omit-if-no-ref/ iomuxc_ecspi2_sclk_ecspi_sclk_ecspi2_sclk: IOMUXC_ECSPI2_SCLK_ECSPI_SCLK_ECSPI2_SCLK { 145 pinmux = <0x303301f0 0 0x30330568 1 0x30330450>; 146 }; 147 /omit-if-no-ref/ iomuxc_ecspi2_sclk_gpio_io_gpio5_io10: IOMUXC_ECSPI2_SCLK_GPIO_IO_GPIO5_IO10 { 148 pinmux = <0x303301f0 5 0x0 0 0x30330450>; 149 }; 150 /omit-if-no-ref/ iomuxc_ecspi2_sclk_i2c_scl_i2c3_scl: IOMUXC_ECSPI2_SCLK_I2C_SCL_I2C3_SCL { 151 pinmux = <0x303301f0 2 0x303305b4 3 0x30330450>; 152 }; 153 /omit-if-no-ref/ iomuxc_ecspi2_sclk_sai_tx_bclk_sai7_tx_bclk: IOMUXC_ECSPI2_SCLK_SAI_TX_BCLK_SAI7_TX_BCLK { 154 pinmux = <0x303301f0 3 0x3033053c 1 0x30330450>; 155 }; 156 /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_rx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_RX_UART4_RX { 157 pinmux = <0x303301f0 1 0x30330600 6 0x30330450>; 158 }; 159 /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_tx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_TX_UART4_RX { 160 pinmux = <0x303301f0 1 0x0 0 0x30330450>; 161 }; 162 /omit-if-no-ref/ iomuxc_ecspi2_ss0_ccm_clko_ccm_clko2: IOMUXC_ECSPI2_SS0_CCM_CLKO_CCM_CLKO2 { 163 pinmux = <0x303301fc 4 0x0 0 0x3033045c>; 164 }; 165 /omit-if-no-ref/ iomuxc_ecspi2_ss0_ecspi_ss_ecspi2_ss0: IOMUXC_ECSPI2_SS0_ECSPI_SS_ECSPI2_SS0 { 166 pinmux = <0x303301fc 0 0x30330574 1 0x3033045c>; 167 }; 168 /omit-if-no-ref/ iomuxc_ecspi2_ss0_gpio_io_gpio5_io13: IOMUXC_ECSPI2_SS0_GPIO_IO_GPIO5_IO13 { 169 pinmux = <0x303301fc 5 0x0 0 0x3033045c>; 170 }; 171 /omit-if-no-ref/ iomuxc_ecspi2_ss0_i2c_sda_i2c4_sda: IOMUXC_ECSPI2_SS0_I2C_SDA_I2C4_SDA { 172 pinmux = <0x303301fc 2 0x303305c0 4 0x3033045c>; 173 }; 174 /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_cts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_CTS_B_UART4_RTS_B { 175 pinmux = <0x303301fc 1 0x0 0 0x3033045c>; 176 }; 177 /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_rts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_RTS_B_UART4_RTS_B { 178 pinmux = <0x303301fc 1 0x303305fc 3 0x3033045c>; 179 }; 180 /omit-if-no-ref/ iomuxc_enet_mdc_enet_qos_mdc_enet_qos_mdc: IOMUXC_ENET_MDC_ENET_QOS_MDC_ENET_QOS_MDC { 181 pinmux = <0x30330054 0 0x0 0 0x303302b4>; 182 }; 183 /omit-if-no-ref/ iomuxc_enet_mdc_gpio_io_gpio1_io16: IOMUXC_ENET_MDC_GPIO_IO_GPIO1_IO16 { 184 pinmux = <0x30330054 5 0x0 0 0x303302b4>; 185 }; 186 /omit-if-no-ref/ iomuxc_enet_mdc_sai_tx_data_sai6_tx_data0: IOMUXC_ENET_MDC_SAI_TX_DATA_SAI6_TX_DATA0 { 187 pinmux = <0x30330054 2 0x0 0 0x303302b4>; 188 }; 189 /omit-if-no-ref/ iomuxc_enet_mdc_usdhc_strobe_usdhc3_strobe: IOMUXC_ENET_MDC_USDHC_STROBE_USDHC3_STROBE { 190 pinmux = <0x30330054 6 0x30330630 0 0x303302b4>; 191 }; 192 /omit-if-no-ref/ iomuxc_enet_mdio_enet_qos_mdio_enet_qos_mdio: IOMUXC_ENET_MDIO_ENET_QOS_MDIO_ENET_QOS_MDIO { 193 pinmux = <0x30330058 0 0x30330590 1 0x303302b8>; 194 }; 195 /omit-if-no-ref/ iomuxc_enet_mdio_gpio_io_gpio1_io17: IOMUXC_ENET_MDIO_GPIO_IO_GPIO1_IO17 { 196 pinmux = <0x30330058 5 0x0 0 0x303302b8>; 197 }; 198 /omit-if-no-ref/ iomuxc_enet_mdio_pdm_bit_stream_pdm_bit_stream3: IOMUXC_ENET_MDIO_PDM_BIT_STREAM_PDM_BIT_STREAM3 { 199 pinmux = <0x30330058 3 0x303304cc 0 0x303302b8>; 200 }; 201 /omit-if-no-ref/ iomuxc_enet_mdio_sai_tx_sync_sai6_tx_sync: IOMUXC_ENET_MDIO_SAI_TX_SYNC_SAI6_TX_SYNC { 202 pinmux = <0x30330058 2 0x30330528 0 0x303302b8>; 203 }; 204 /omit-if-no-ref/ iomuxc_enet_mdio_usdhc_data_usdhc3_data5: IOMUXC_ENET_MDIO_USDHC_DATA_USDHC3_DATA5 { 205 pinmux = <0x30330058 6 0x30330624 0 0x303302b8>; 206 }; 207 /omit-if-no-ref/ iomuxc_enet_rd0_enet_qos_rgmii_rd_enet_qos_rgmii_rd0: IOMUXC_ENET_RD0_ENET_QOS_RGMII_RD_ENET_QOS_RGMII_RD0 { 208 pinmux = <0x3033007c 0 0x0 0 0x303302dc>; 209 }; 210 /omit-if-no-ref/ iomuxc_enet_rd0_gpio_io_gpio1_io26: IOMUXC_ENET_RD0_GPIO_IO_GPIO1_IO26 { 211 pinmux = <0x3033007c 5 0x0 0 0x303302dc>; 212 }; 213 /omit-if-no-ref/ iomuxc_enet_rd0_pdm_bit_stream_pdm_bit_stream1: IOMUXC_ENET_RD0_PDM_BIT_STREAM_PDM_BIT_STREAM1 { 214 pinmux = <0x3033007c 3 0x303304c4 1 0x303302dc>; 215 }; 216 /omit-if-no-ref/ iomuxc_enet_rd0_sai_rx_data_sai7_rx_data0: IOMUXC_ENET_RD0_SAI_RX_DATA_SAI7_RX_DATA0 { 217 pinmux = <0x3033007c 2 0x30330534 0 0x303302dc>; 218 }; 219 /omit-if-no-ref/ iomuxc_enet_rd0_usdhc_data_usdhc3_data4: IOMUXC_ENET_RD0_USDHC_DATA_USDHC3_DATA4 { 220 pinmux = <0x3033007c 6 0x30330620 0 0x303302dc>; 221 }; 222 /omit-if-no-ref/ iomuxc_enet_rd1_enet_qos_rgmii_rd_enet_qos_rgmii_rd1: IOMUXC_ENET_RD1_ENET_QOS_RGMII_RD_ENET_QOS_RGMII_RD1 { 223 pinmux = <0x30330080 0 0x0 0 0x303302e0>; 224 }; 225 /omit-if-no-ref/ iomuxc_enet_rd1_gpio_io_gpio1_io27: IOMUXC_ENET_RD1_GPIO_IO_GPIO1_IO27 { 226 pinmux = <0x30330080 5 0x0 0 0x303302e0>; 227 }; 228 /omit-if-no-ref/ iomuxc_enet_rd1_pdm_bit_stream_pdm_bit_stream0: IOMUXC_ENET_RD1_PDM_BIT_STREAM_PDM_BIT_STREAM0 { 229 pinmux = <0x30330080 3 0x303304c0 1 0x303302e0>; 230 }; 231 /omit-if-no-ref/ iomuxc_enet_rd1_sai_rx_sync_sai7_rx_sync: IOMUXC_ENET_RD1_SAI_RX_SYNC_SAI7_RX_SYNC { 232 pinmux = <0x30330080 2 0x30330538 0 0x303302e0>; 233 }; 234 /omit-if-no-ref/ iomuxc_enet_rd1_usdhc_reset_b_usdhc3_reset_b: IOMUXC_ENET_RD1_USDHC_RESET_B_USDHC3_RESET_B { 235 pinmux = <0x30330080 6 0x0 0 0x303302e0>; 236 }; 237 /omit-if-no-ref/ iomuxc_enet_rd2_enet_qos_rgmii_rd_enet_qos_rgmii_rd2: IOMUXC_ENET_RD2_ENET_QOS_RGMII_RD_ENET_QOS_RGMII_RD2 { 238 pinmux = <0x30330084 0 0x0 0 0x303302e4>; 239 }; 240 /omit-if-no-ref/ iomuxc_enet_rd2_gpio_io_gpio1_io28: IOMUXC_ENET_RD2_GPIO_IO_GPIO1_IO28 { 241 pinmux = <0x30330084 5 0x0 0 0x303302e4>; 242 }; 243 /omit-if-no-ref/ iomuxc_enet_rd2_pdm_clk_pdm_clk: IOMUXC_ENET_RD2_PDM_CLK_PDM_CLK { 244 pinmux = <0x30330084 3 0x0 0 0x303302e4>; 245 }; 246 /omit-if-no-ref/ iomuxc_enet_rd2_sai_rx_bclk_sai7_rx_bclk: IOMUXC_ENET_RD2_SAI_RX_BCLK_SAI7_RX_BCLK { 247 pinmux = <0x30330084 2 0x30330530 0 0x303302e4>; 248 }; 249 /omit-if-no-ref/ iomuxc_enet_rd2_usdhc_clk_usdhc3_clk: IOMUXC_ENET_RD2_USDHC_CLK_USDHC3_CLK { 250 pinmux = <0x30330084 6 0x30330604 0 0x303302e4>; 251 }; 252 /omit-if-no-ref/ iomuxc_enet_rd3_enet_qos_rgmii_rd_enet_qos_rgmii_rd3: IOMUXC_ENET_RD3_ENET_QOS_RGMII_RD_ENET_QOS_RGMII_RD3 { 253 pinmux = <0x30330088 0 0x0 0 0x303302e8>; 254 }; 255 /omit-if-no-ref/ iomuxc_enet_rd3_gpio_io_gpio1_io29: IOMUXC_ENET_RD3_GPIO_IO_GPIO1_IO29 { 256 pinmux = <0x30330088 5 0x0 0 0x303302e8>; 257 }; 258 /omit-if-no-ref/ iomuxc_enet_rd3_sai_mclk_sai7_mclk: IOMUXC_ENET_RD3_SAI_MCLK_SAI7_MCLK { 259 pinmux = <0x30330088 2 0x3033052c 0 0x303302e8>; 260 }; 261 /omit-if-no-ref/ iomuxc_enet_rd3_spdif_in_spdif1_in: IOMUXC_ENET_RD3_SPDIF_IN_SPDIF1_IN { 262 pinmux = <0x30330088 3 0x30330544 0 0x303302e8>; 263 }; 264 /omit-if-no-ref/ iomuxc_enet_rd3_usdhc_cmd_usdhc3_cmd: IOMUXC_ENET_RD3_USDHC_CMD_USDHC3_CMD { 265 pinmux = <0x30330088 6 0x3033060c 0 0x303302e8>; 266 }; 267 /omit-if-no-ref/ iomuxc_enet_rxc_enet_qos_rgmii_rxc_enet_qos_rgmii_rxc: IOMUXC_ENET_RXC_ENET_QOS_RGMII_RXC_ENET_QOS_RGMII_RXC { 268 pinmux = <0x30330078 0 0x0 0 0x303302d8>; 269 }; 270 /omit-if-no-ref/ iomuxc_enet_rxc_enet_qos_rx_er_enet_qos_rx_er: IOMUXC_ENET_RXC_ENET_QOS_RX_ER_ENET_QOS_RX_ER { 271 pinmux = <0x30330078 1 0x0 0 0x303302d8>; 272 }; 273 /omit-if-no-ref/ iomuxc_enet_rxc_gpio_io_gpio1_io25: IOMUXC_ENET_RXC_GPIO_IO_GPIO1_IO25 { 274 pinmux = <0x30330078 5 0x0 0 0x303302d8>; 275 }; 276 /omit-if-no-ref/ iomuxc_enet_rxc_pdm_bit_stream_pdm_bit_stream2: IOMUXC_ENET_RXC_PDM_BIT_STREAM_PDM_BIT_STREAM2 { 277 pinmux = <0x30330078 3 0x303304c8 1 0x303302d8>; 278 }; 279 /omit-if-no-ref/ iomuxc_enet_rxc_sai_tx_bclk_sai7_tx_bclk: IOMUXC_ENET_RXC_SAI_TX_BCLK_SAI7_TX_BCLK { 280 pinmux = <0x30330078 2 0x3033053c 0 0x303302d8>; 281 }; 282 /omit-if-no-ref/ iomuxc_enet_rxc_usdhc_data_usdhc3_data3: IOMUXC_ENET_RXC_USDHC_DATA_USDHC3_DATA3 { 283 pinmux = <0x30330078 6 0x3033061c 0 0x303302d8>; 284 }; 285 /omit-if-no-ref/ iomuxc_enet_rx_ctl_enet_qos_rgmii_rx_ctl_enet_qos_rgmii_rx_ctl: IOMUXC_ENET_RX_CTL_ENET_QOS_RGMII_RX_CTL_ENET_QOS_RGMII_RX_CTL { 286 pinmux = <0x30330074 0 0x0 0 0x303302d4>; 287 }; 288 /omit-if-no-ref/ iomuxc_enet_rx_ctl_gpio_io_gpio1_io24: IOMUXC_ENET_RX_CTL_GPIO_IO_GPIO1_IO24 { 289 pinmux = <0x30330074 5 0x0 0 0x303302d4>; 290 }; 291 /omit-if-no-ref/ iomuxc_enet_rx_ctl_pdm_bit_stream_pdm_bit_stream3: IOMUXC_ENET_RX_CTL_PDM_BIT_STREAM_PDM_BIT_STREAM3 { 292 pinmux = <0x30330074 3 0x303304cc 1 0x303302d4>; 293 }; 294 /omit-if-no-ref/ iomuxc_enet_rx_ctl_sai_tx_sync_sai7_tx_sync: IOMUXC_ENET_RX_CTL_SAI_TX_SYNC_SAI7_TX_SYNC { 295 pinmux = <0x30330074 2 0x30330540 0 0x303302d4>; 296 }; 297 /omit-if-no-ref/ iomuxc_enet_rx_ctl_usdhc_data_usdhc3_data2: IOMUXC_ENET_RX_CTL_USDHC_DATA_USDHC3_DATA2 { 298 pinmux = <0x30330074 6 0x30330618 0 0x303302d4>; 299 }; 300 /omit-if-no-ref/ iomuxc_enet_td0_enet_qos_rgmii_td_enet_qos_rgmii_td0: IOMUXC_ENET_TD0_ENET_QOS_RGMII_TD_ENET_QOS_RGMII_TD0 { 301 pinmux = <0x30330068 0 0x0 0 0x303302c8>; 302 }; 303 /omit-if-no-ref/ iomuxc_enet_td0_gpio_io_gpio1_io21: IOMUXC_ENET_TD0_GPIO_IO_GPIO1_IO21 { 304 pinmux = <0x30330068 5 0x0 0 0x303302c8>; 305 }; 306 /omit-if-no-ref/ iomuxc_enet_td0_pdm_clk_pdm_clk: IOMUXC_ENET_TD0_PDM_CLK_PDM_CLK { 307 pinmux = <0x30330068 3 0x0 0 0x303302c8>; 308 }; 309 /omit-if-no-ref/ iomuxc_enet_td0_sai_rx_bclk_sai6_rx_bclk: IOMUXC_ENET_TD0_SAI_RX_BCLK_SAI6_RX_BCLK { 310 pinmux = <0x30330068 2 0x30330518 0 0x303302c8>; 311 }; 312 /omit-if-no-ref/ iomuxc_enet_td0_usdhc_wp_usdhc3_wp: IOMUXC_ENET_TD0_USDHC_WP_USDHC3_WP { 313 pinmux = <0x30330068 6 0x30330634 1 0x303302c8>; 314 }; 315 /omit-if-no-ref/ iomuxc_enet_td1_enet_qos_rgmii_td_enet_qos_rgmii_td1: IOMUXC_ENET_TD1_ENET_QOS_RGMII_TD_ENET_QOS_RGMII_TD1 { 316 pinmux = <0x30330064 0 0x0 0 0x303302c4>; 317 }; 318 /omit-if-no-ref/ iomuxc_enet_td1_gpio_io_gpio1_io20: IOMUXC_ENET_TD1_GPIO_IO_GPIO1_IO20 { 319 pinmux = <0x30330064 5 0x0 0 0x303302c4>; 320 }; 321 /omit-if-no-ref/ iomuxc_enet_td1_pdm_bit_stream_pdm_bit_stream0: IOMUXC_ENET_TD1_PDM_BIT_STREAM_PDM_BIT_STREAM0 { 322 pinmux = <0x30330064 3 0x303304c0 0 0x303302c4>; 323 }; 324 /omit-if-no-ref/ iomuxc_enet_td1_sai_rx_sync_sai6_rx_sync: IOMUXC_ENET_TD1_SAI_RX_SYNC_SAI6_RX_SYNC { 325 pinmux = <0x30330064 2 0x30330520 0 0x303302c4>; 326 }; 327 /omit-if-no-ref/ iomuxc_enet_td1_usdhc_cd_b_usdhc3_cd_b: IOMUXC_ENET_TD1_USDHC_CD_B_USDHC3_CD_B { 328 pinmux = <0x30330064 6 0x30330608 1 0x303302c4>; 329 }; 330 /omit-if-no-ref/ iomuxc_enet_td2_enet_qos_rgmii_td_enet_qos_rgmii_td2: IOMUXC_ENET_TD2_ENET_QOS_RGMII_TD_ENET_QOS_RGMII_TD2 { 331 pinmux = <0x30330060 0 0x0 0 0x303302c0>; 332 }; 333 /omit-if-no-ref/ iomuxc_enet_td2_enet_qos_tx_clk_enet_qos_tx_clk: IOMUXC_ENET_TD2_ENET_QOS_TX_CLK_ENET_QOS_TX_CLK { 334 pinmux = <0x30330060 1 0x0 0 0x303302c0>; 335 }; 336 /omit-if-no-ref/ iomuxc_enet_td2_gpio_io_gpio1_io19: IOMUXC_ENET_TD2_GPIO_IO_GPIO1_IO19 { 337 pinmux = <0x30330060 5 0x0 0 0x303302c0>; 338 }; 339 /omit-if-no-ref/ iomuxc_enet_td2_pdm_bit_stream_pdm_bit_stream1: IOMUXC_ENET_TD2_PDM_BIT_STREAM_PDM_BIT_STREAM1 { 340 pinmux = <0x30330060 3 0x303304c4 0 0x303302c0>; 341 }; 342 /omit-if-no-ref/ iomuxc_enet_td2_sai_rx_data_sai6_rx_data0: IOMUXC_ENET_TD2_SAI_RX_DATA_SAI6_RX_DATA0 { 343 pinmux = <0x30330060 2 0x3033051c 0 0x303302c0>; 344 }; 345 /omit-if-no-ref/ iomuxc_enet_td2_usdhc_data_usdhc3_data7: IOMUXC_ENET_TD2_USDHC_DATA_USDHC3_DATA7 { 346 pinmux = <0x30330060 6 0x3033062c 0 0x303302c0>; 347 }; 348 /omit-if-no-ref/ iomuxc_enet_td3_enet_qos_rgmii_td_enet_qos_rgmii_td3: IOMUXC_ENET_TD3_ENET_QOS_RGMII_TD_ENET_QOS_RGMII_TD3 { 349 pinmux = <0x3033005c 0 0x0 0 0x303302bc>; 350 }; 351 /omit-if-no-ref/ iomuxc_enet_td3_gpio_io_gpio1_io18: IOMUXC_ENET_TD3_GPIO_IO_GPIO1_IO18 { 352 pinmux = <0x3033005c 5 0x0 0 0x303302bc>; 353 }; 354 /omit-if-no-ref/ iomuxc_enet_td3_pdm_bit_stream_pdm_bit_stream2: IOMUXC_ENET_TD3_PDM_BIT_STREAM_PDM_BIT_STREAM2 { 355 pinmux = <0x3033005c 3 0x303304c8 0 0x303302bc>; 356 }; 357 /omit-if-no-ref/ iomuxc_enet_td3_sai_tx_bclk_sai6_tx_bclk: IOMUXC_ENET_TD3_SAI_TX_BCLK_SAI6_TX_BCLK { 358 pinmux = <0x3033005c 2 0x30330524 0 0x303302bc>; 359 }; 360 /omit-if-no-ref/ iomuxc_enet_td3_usdhc_data_usdhc3_data6: IOMUXC_ENET_TD3_USDHC_DATA_USDHC3_DATA6 { 361 pinmux = <0x3033005c 6 0x30330628 0 0x303302bc>; 362 }; 363 /omit-if-no-ref/ iomuxc_enet_txc_enet_qos_rgmii_txc_enet_qos_rgmii_txc: IOMUXC_ENET_TXC_ENET_QOS_RGMII_TXC_ENET_QOS_RGMII_TXC { 364 pinmux = <0x30330070 0 0x0 0 0x303302d0>; 365 }; 366 /omit-if-no-ref/ iomuxc_enet_txc_enet_qos_tx_er_enet_qos_tx_er: IOMUXC_ENET_TXC_ENET_QOS_TX_ER_ENET_QOS_TX_ER { 367 pinmux = <0x30330070 1 0x0 0 0x303302d0>; 368 }; 369 /omit-if-no-ref/ iomuxc_enet_txc_gpio_io_gpio1_io23: IOMUXC_ENET_TXC_GPIO_IO_GPIO1_IO23 { 370 pinmux = <0x30330070 5 0x0 0 0x303302d0>; 371 }; 372 /omit-if-no-ref/ iomuxc_enet_txc_sai_tx_data_sai7_tx_data0: IOMUXC_ENET_TXC_SAI_TX_DATA_SAI7_TX_DATA0 { 373 pinmux = <0x30330070 2 0x0 0 0x303302d0>; 374 }; 375 /omit-if-no-ref/ iomuxc_enet_txc_usdhc_data_usdhc3_data1: IOMUXC_ENET_TXC_USDHC_DATA_USDHC3_DATA1 { 376 pinmux = <0x30330070 6 0x30330614 0 0x303302d0>; 377 }; 378 /omit-if-no-ref/ iomuxc_enet_tx_ctl_enet_qos_rgmii_tx_ctl_enet_qos_rgmii_tx_ctl: IOMUXC_ENET_TX_CTL_ENET_QOS_RGMII_TX_CTL_ENET_QOS_RGMII_TX_CTL { 379 pinmux = <0x3033006c 0 0x0 0 0x303302cc>; 380 }; 381 /omit-if-no-ref/ iomuxc_enet_tx_ctl_gpio_io_gpio1_io22: IOMUXC_ENET_TX_CTL_GPIO_IO_GPIO1_IO22 { 382 pinmux = <0x3033006c 5 0x0 0 0x303302cc>; 383 }; 384 /omit-if-no-ref/ iomuxc_enet_tx_ctl_sai_mclk_sai6_mclk: IOMUXC_ENET_TX_CTL_SAI_MCLK_SAI6_MCLK { 385 pinmux = <0x3033006c 2 0x30330514 0 0x303302cc>; 386 }; 387 /omit-if-no-ref/ iomuxc_enet_tx_ctl_spdif_out_spdif1_out: IOMUXC_ENET_TX_CTL_SPDIF_OUT_SPDIF1_OUT { 388 pinmux = <0x3033006c 3 0x0 0 0x303302cc>; 389 }; 390 /omit-if-no-ref/ iomuxc_enet_tx_ctl_usdhc_data_usdhc3_data0: IOMUXC_ENET_TX_CTL_USDHC_DATA_USDHC3_DATA0 { 391 pinmux = <0x3033006c 6 0x30330610 0 0x303302cc>; 392 }; 393 /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_enet_phy_ref_clk_root_ccm_enet_phy_ref_clk_root: IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT_CCM_ENET_PHY_REF_CLK_ROOT { 394 pinmux = <0x30330014 1 0x0 0 0x30330274>; 395 }; 396 /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_ext_clk_ccm_ext_clk1: IOMUXC_GPIO1_IO00_CCM_EXT_CLK_CCM_EXT_CLK1 { 397 pinmux = <0x30330014 6 0x0 0 0x30330274>; 398 }; 399 /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_ref_clk_32k_ccm_ref_clk_32k: IOMUXC_GPIO1_IO00_CCM_REF_CLK_32K_CCM_REF_CLK_32K { 400 pinmux = <0x30330014 5 0x0 0 0x30330274>; 401 }; 402 /omit-if-no-ref/ iomuxc_gpio1_io00_gpio_io_gpio1_io0: IOMUXC_GPIO1_IO00_GPIO_IO_GPIO1_IO0 { 403 pinmux = <0x30330014 0 0x0 0 0x30330274>; 404 }; 405 /omit-if-no-ref/ iomuxc_gpio1_io00_isp_fl_trig_isp_fl_trig_0: IOMUXC_GPIO1_IO00_ISP_FL_TRIG_ISP_FL_TRIG_0 { 406 pinmux = <0x30330014 3 0x303305d4 0 0x30330274>; 407 }; 408 /omit-if-no-ref/ iomuxc_gpio1_io01_ccm_ext_clk_ccm_ext_clk2: IOMUXC_GPIO1_IO01_CCM_EXT_CLK_CCM_EXT_CLK2 { 409 pinmux = <0x30330018 6 0x0 0 0x30330278>; 410 }; 411 /omit-if-no-ref/ iomuxc_gpio1_io01_ccm_ref_clk_24m_ccm_ref_clk_24m: IOMUXC_GPIO1_IO01_CCM_REF_CLK_24M_CCM_REF_CLK_24M { 412 pinmux = <0x30330018 5 0x0 0 0x30330278>; 413 }; 414 /omit-if-no-ref/ iomuxc_gpio1_io01_gpio_io_gpio1_io1: IOMUXC_GPIO1_IO01_GPIO_IO_GPIO1_IO1 { 415 pinmux = <0x30330018 0 0x0 0 0x30330278>; 416 }; 417 /omit-if-no-ref/ iomuxc_gpio1_io01_isp_shutter_trig_isp_shutter_trig_0: IOMUXC_GPIO1_IO01_ISP_SHUTTER_TRIG_ISP_SHUTTER_TRIG_0 { 418 pinmux = <0x30330018 3 0x303305dc 0 0x30330278>; 419 }; 420 /omit-if-no-ref/ iomuxc_gpio1_io01_pwm_out_pwm1_out: IOMUXC_GPIO1_IO01_PWM_OUT_PWM1_OUT { 421 pinmux = <0x30330018 1 0x0 0 0x30330278>; 422 }; 423 /omit-if-no-ref/ iomuxc_gpio1_io02_gpio_io_gpio1_io2: IOMUXC_GPIO1_IO02_GPIO_IO_GPIO1_IO2 { 424 pinmux = <0x3033001c 0 0x0 0 0x3033027c>; 425 }; 426 /omit-if-no-ref/ iomuxc_gpio1_io02_isp_flash_trig_isp_flash_trig_0: IOMUXC_GPIO1_IO02_ISP_FLASH_TRIG_ISP_FLASH_TRIG_0 { 427 pinmux = <0x3033001c 3 0x0 0 0x3033027c>; 428 }; 429 /omit-if-no-ref/ iomuxc_gpio1_io02_sjc_de_b_sjc_de_b: IOMUXC_GPIO1_IO02_SJC_DE_B_SJC_DE_B { 430 pinmux = <0x3033001c 7 0x0 0 0x3033027c>; 431 }; 432 /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_any_wdog1_wdog_any: IOMUXC_GPIO1_IO02_WDOG_WDOG_ANY_WDOG1_WDOG_ANY { 433 pinmux = <0x3033001c 5 0x0 0 0x3033027c>; 434 }; 435 /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_b_wdog1_wdog_b: IOMUXC_GPIO1_IO02_WDOG_WDOG_B_WDOG1_WDOG_B { 436 pinmux = <0x3033001c 1 0x0 0 0x3033027c>; 437 }; 438 /omit-if-no-ref/ iomuxc_gpio1_io03_gpio_io_gpio1_io3: IOMUXC_GPIO1_IO03_GPIO_IO_GPIO1_IO3 { 439 pinmux = <0x30330020 0 0x0 0 0x30330280>; 440 }; 441 /omit-if-no-ref/ iomuxc_gpio1_io03_isp_prelight_trig_isp_prelight_trig_0: IOMUXC_GPIO1_IO03_ISP_PRELIGHT_TRIG_ISP_PRELIGHT_TRIG_0 { 442 pinmux = <0x30330020 3 0x0 0 0x30330280>; 443 }; 444 /omit-if-no-ref/ iomuxc_gpio1_io03_sdma_ext_event_sdma1_ext_event0: IOMUXC_GPIO1_IO03_SDMA_EXT_EVENT_SDMA1_EXT_EVENT0 { 445 pinmux = <0x30330020 5 0x0 0 0x30330280>; 446 }; 447 /omit-if-no-ref/ iomuxc_gpio1_io03_usdhc_vselect_usdhc1_vselect: IOMUXC_GPIO1_IO03_USDHC_VSELECT_USDHC1_VSELECT { 448 pinmux = <0x30330020 1 0x0 0 0x30330280>; 449 }; 450 /omit-if-no-ref/ iomuxc_gpio1_io04_gpio_io_gpio1_io4: IOMUXC_GPIO1_IO04_GPIO_IO_GPIO1_IO4 { 451 pinmux = <0x30330024 0 0x0 0 0x30330284>; 452 }; 453 /omit-if-no-ref/ iomuxc_gpio1_io04_isp_shutter_open_isp_shutter_open_0: IOMUXC_GPIO1_IO04_ISP_SHUTTER_OPEN_ISP_SHUTTER_OPEN_0 { 454 pinmux = <0x30330024 3 0x0 0 0x30330284>; 455 }; 456 /omit-if-no-ref/ iomuxc_gpio1_io04_sdma_ext_event_sdma1_ext_event1: IOMUXC_GPIO1_IO04_SDMA_EXT_EVENT_SDMA1_EXT_EVENT1 { 457 pinmux = <0x30330024 5 0x0 0 0x30330284>; 458 }; 459 /omit-if-no-ref/ iomuxc_gpio1_io04_usdhc_vselect_usdhc2_vselect: IOMUXC_GPIO1_IO04_USDHC_VSELECT_USDHC2_VSELECT { 460 pinmux = <0x30330024 1 0x0 0 0x30330284>; 461 }; 462 /omit-if-no-ref/ iomuxc_gpio1_io05_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO05_CCM_PMIC_READY_CCM_PMIC_READY { 463 pinmux = <0x30330028 5 0x30330554 0 0x30330288>; 464 }; 465 /omit-if-no-ref/ iomuxc_gpio1_io05_gpio_io_gpio1_io5: IOMUXC_GPIO1_IO05_GPIO_IO_GPIO1_IO5 { 466 pinmux = <0x30330028 0 0x0 0 0x30330288>; 467 }; 468 /omit-if-no-ref/ iomuxc_gpio1_io05_isp_fl_trig_isp_fl_trig_1: IOMUXC_GPIO1_IO05_ISP_FL_TRIG_ISP_FL_TRIG_1 { 469 pinmux = <0x30330028 3 0x303305d8 0 0x30330288>; 470 }; 471 /omit-if-no-ref/ iomuxc_gpio1_io05_m7_nmi_m7_nmi: IOMUXC_GPIO1_IO05_M7_NMI_M7_NMI { 472 pinmux = <0x30330028 1 0x0 0 0x30330288>; 473 }; 474 /omit-if-no-ref/ iomuxc_gpio1_io06_ccm_ext_clk_ccm_ext_clk3: IOMUXC_GPIO1_IO06_CCM_EXT_CLK_CCM_EXT_CLK3 { 475 pinmux = <0x3033002c 6 0x0 0 0x3033028c>; 476 }; 477 /omit-if-no-ref/ iomuxc_gpio1_io06_enet_qos_mdc_enet_qos_mdc: IOMUXC_GPIO1_IO06_ENET_QOS_MDC_ENET_QOS_MDC { 478 pinmux = <0x3033002c 1 0x0 0 0x3033028c>; 479 }; 480 /omit-if-no-ref/ iomuxc_gpio1_io06_gpio_io_gpio1_io6: IOMUXC_GPIO1_IO06_GPIO_IO_GPIO1_IO6 { 481 pinmux = <0x3033002c 0 0x0 0 0x3033028c>; 482 }; 483 /omit-if-no-ref/ iomuxc_gpio1_io06_isp_shutter_trig_isp_shutter_trig_1: IOMUXC_GPIO1_IO06_ISP_SHUTTER_TRIG_ISP_SHUTTER_TRIG_1 { 484 pinmux = <0x3033002c 3 0x303305e0 0 0x3033028c>; 485 }; 486 /omit-if-no-ref/ iomuxc_gpio1_io06_usdhc_cd_b_usdhc1_cd_b: IOMUXC_GPIO1_IO06_USDHC_CD_B_USDHC1_CD_B { 487 pinmux = <0x3033002c 5 0x0 0 0x3033028c>; 488 }; 489 /omit-if-no-ref/ iomuxc_gpio1_io07_ccm_ext_clk_ccm_ext_clk4: IOMUXC_GPIO1_IO07_CCM_EXT_CLK_CCM_EXT_CLK4 { 490 pinmux = <0x30330030 6 0x0 0 0x30330290>; 491 }; 492 /omit-if-no-ref/ iomuxc_gpio1_io07_enet_qos_mdio_enet_qos_mdio: IOMUXC_GPIO1_IO07_ENET_QOS_MDIO_ENET_QOS_MDIO { 493 pinmux = <0x30330030 1 0x30330590 0 0x30330290>; 494 }; 495 /omit-if-no-ref/ iomuxc_gpio1_io07_gpio_io_gpio1_io7: IOMUXC_GPIO1_IO07_GPIO_IO_GPIO1_IO7 { 496 pinmux = <0x30330030 0 0x0 0 0x30330290>; 497 }; 498 /omit-if-no-ref/ iomuxc_gpio1_io07_isp_flash_trig_isp_flash_trig_1: IOMUXC_GPIO1_IO07_ISP_FLASH_TRIG_ISP_FLASH_TRIG_1 { 499 pinmux = <0x30330030 3 0x0 0 0x30330290>; 500 }; 501 /omit-if-no-ref/ iomuxc_gpio1_io07_usdhc_wp_usdhc1_wp: IOMUXC_GPIO1_IO07_USDHC_WP_USDHC1_WP { 502 pinmux = <0x30330030 5 0x0 0 0x30330290>; 503 }; 504 /omit-if-no-ref/ iomuxc_gpio1_io08_enet_qos_1588_event0_aux_in_enet_qos_1588_event0_aux_in: IOMUXC_GPIO1_IO08_ENET_QOS_1588_EVENT0_AUX_IN_ENET_QOS_1588_EVENT0_AUX_IN { 505 pinmux = <0x30330034 4 0x0 0 0x30330294>; 506 }; 507 /omit-if-no-ref/ iomuxc_gpio1_io08_enet_qos_1588_event0_in_enet_qos_1588_event0_in: IOMUXC_GPIO1_IO08_ENET_QOS_1588_EVENT0_IN_ENET_QOS_1588_EVENT0_IN { 508 pinmux = <0x30330034 1 0x0 0 0x30330294>; 509 }; 510 /omit-if-no-ref/ iomuxc_gpio1_io08_gpio_io_gpio1_io8: IOMUXC_GPIO1_IO08_GPIO_IO_GPIO1_IO8 { 511 pinmux = <0x30330034 0 0x0 0 0x30330294>; 512 }; 513 /omit-if-no-ref/ iomuxc_gpio1_io08_isp_prelight_trig_isp_prelight_trig_1: IOMUXC_GPIO1_IO08_ISP_PRELIGHT_TRIG_ISP_PRELIGHT_TRIG_1 { 514 pinmux = <0x30330034 3 0x0 0 0x30330294>; 515 }; 516 /omit-if-no-ref/ iomuxc_gpio1_io08_pwm_out_pwm1_out: IOMUXC_GPIO1_IO08_PWM_OUT_PWM1_OUT { 517 pinmux = <0x30330034 2 0x0 0 0x30330294>; 518 }; 519 /omit-if-no-ref/ iomuxc_gpio1_io08_usdhc_reset_b_usdhc2_reset_b: IOMUXC_GPIO1_IO08_USDHC_RESET_B_USDHC2_RESET_B { 520 pinmux = <0x30330034 5 0x0 0 0x30330294>; 521 }; 522 /omit-if-no-ref/ iomuxc_gpio1_io09_enet_qos_1588_event0_out_enet_qos_1588_event0_out: IOMUXC_GPIO1_IO09_ENET_QOS_1588_EVENT0_OUT_ENET_QOS_1588_EVENT0_OUT { 523 pinmux = <0x30330038 1 0x0 0 0x30330298>; 524 }; 525 /omit-if-no-ref/ iomuxc_gpio1_io09_gpio_io_gpio1_io9: IOMUXC_GPIO1_IO09_GPIO_IO_GPIO1_IO9 { 526 pinmux = <0x30330038 0 0x0 0 0x30330298>; 527 }; 528 /omit-if-no-ref/ iomuxc_gpio1_io09_isp_shutter_open_isp_shutter_open_1: IOMUXC_GPIO1_IO09_ISP_SHUTTER_OPEN_ISP_SHUTTER_OPEN_1 { 529 pinmux = <0x30330038 3 0x0 0 0x30330298>; 530 }; 531 /omit-if-no-ref/ iomuxc_gpio1_io09_pwm_out_pwm2_out: IOMUXC_GPIO1_IO09_PWM_OUT_PWM2_OUT { 532 pinmux = <0x30330038 2 0x0 0 0x30330298>; 533 }; 534 /omit-if-no-ref/ iomuxc_gpio1_io09_sdma_ext_event_sdma2_ext_event0: IOMUXC_GPIO1_IO09_SDMA_EXT_EVENT_SDMA2_EXT_EVENT0 { 535 pinmux = <0x30330038 5 0x0 0 0x30330298>; 536 }; 537 /omit-if-no-ref/ iomuxc_gpio1_io09_usdhc_reset_b_usdhc3_reset_b: IOMUXC_GPIO1_IO09_USDHC_RESET_B_USDHC3_RESET_B { 538 pinmux = <0x30330038 4 0x0 0 0x30330298>; 539 }; 540 /omit-if-no-ref/ iomuxc_gpio1_io10_gpio_io_gpio1_io10: IOMUXC_GPIO1_IO10_GPIO_IO_GPIO1_IO10 { 541 pinmux = <0x3033003c 0 0x0 0 0x3033029c>; 542 }; 543 /omit-if-no-ref/ iomuxc_gpio1_io10_pwm_out_pwm3_out: IOMUXC_GPIO1_IO10_PWM_OUT_PWM3_OUT { 544 pinmux = <0x3033003c 2 0x0 0 0x3033029c>; 545 }; 546 /omit-if-no-ref/ iomuxc_gpio1_io10_usb_id_usb1_id: IOMUXC_GPIO1_IO10_USB_ID_USB1_ID { 547 pinmux = <0x3033003c 1 0x0 0 0x3033029c>; 548 }; 549 /omit-if-no-ref/ iomuxc_gpio1_io11_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO11_CCM_PMIC_READY_CCM_PMIC_READY { 550 pinmux = <0x30330040 5 0x30330554 1 0x303302a0>; 551 }; 552 /omit-if-no-ref/ iomuxc_gpio1_io11_gpio_io_gpio1_io11: IOMUXC_GPIO1_IO11_GPIO_IO_GPIO1_IO11 { 553 pinmux = <0x30330040 0 0x0 0 0x303302a0>; 554 }; 555 /omit-if-no-ref/ iomuxc_gpio1_io11_pwm_out_pwm2_out: IOMUXC_GPIO1_IO11_PWM_OUT_PWM2_OUT { 556 pinmux = <0x30330040 2 0x0 0 0x303302a0>; 557 }; 558 /omit-if-no-ref/ iomuxc_gpio1_io11_usb_id_usb2_id: IOMUXC_GPIO1_IO11_USB_ID_USB2_ID { 559 pinmux = <0x30330040 1 0x0 0 0x303302a0>; 560 }; 561 /omit-if-no-ref/ iomuxc_gpio1_io11_usdhc_vselect_usdhc3_vselect: IOMUXC_GPIO1_IO11_USDHC_VSELECT_USDHC3_VSELECT { 562 pinmux = <0x30330040 4 0x0 0 0x303302a0>; 563 }; 564 /omit-if-no-ref/ iomuxc_gpio1_io12_gpio_io_gpio1_io12: IOMUXC_GPIO1_IO12_GPIO_IO_GPIO1_IO12 { 565 pinmux = <0x30330044 0 0x0 0 0x303302a4>; 566 }; 567 /omit-if-no-ref/ iomuxc_gpio1_io12_sdma_ext_event_sdma2_ext_event1: IOMUXC_GPIO1_IO12_SDMA_EXT_EVENT_SDMA2_EXT_EVENT1 { 568 pinmux = <0x30330044 5 0x0 0 0x303302a4>; 569 }; 570 /omit-if-no-ref/ iomuxc_gpio1_io12_usb_pwr_usb1_pwr: IOMUXC_GPIO1_IO12_USB_PWR_USB1_PWR { 571 pinmux = <0x30330044 1 0x0 0 0x303302a4>; 572 }; 573 /omit-if-no-ref/ iomuxc_gpio1_io13_gpio_io_gpio1_io13: IOMUXC_GPIO1_IO13_GPIO_IO_GPIO1_IO13 { 574 pinmux = <0x30330048 0 0x0 0 0x303302a8>; 575 }; 576 /omit-if-no-ref/ iomuxc_gpio1_io13_pwm_out_pwm2_out: IOMUXC_GPIO1_IO13_PWM_OUT_PWM2_OUT { 577 pinmux = <0x30330048 5 0x0 0 0x303302a8>; 578 }; 579 /omit-if-no-ref/ iomuxc_gpio1_io13_usb_oc_usb1_oc: IOMUXC_GPIO1_IO13_USB_OC_USB1_OC { 580 pinmux = <0x30330048 1 0x0 0 0x303302a8>; 581 }; 582 /omit-if-no-ref/ iomuxc_gpio1_io14_ccm_clko_ccm_clko1: IOMUXC_GPIO1_IO14_CCM_CLKO_CCM_CLKO1 { 583 pinmux = <0x3033004c 6 0x0 0 0x303302ac>; 584 }; 585 /omit-if-no-ref/ iomuxc_gpio1_io14_gpio_io_gpio1_io14: IOMUXC_GPIO1_IO14_GPIO_IO_GPIO1_IO14 { 586 pinmux = <0x3033004c 0 0x0 0 0x303302ac>; 587 }; 588 /omit-if-no-ref/ iomuxc_gpio1_io14_pwm_out_pwm3_out: IOMUXC_GPIO1_IO14_PWM_OUT_PWM3_OUT { 589 pinmux = <0x3033004c 5 0x0 0 0x303302ac>; 590 }; 591 /omit-if-no-ref/ iomuxc_gpio1_io14_usb_pwr_usb2_pwr: IOMUXC_GPIO1_IO14_USB_PWR_USB2_PWR { 592 pinmux = <0x3033004c 1 0x0 0 0x303302ac>; 593 }; 594 /omit-if-no-ref/ iomuxc_gpio1_io14_usdhc_cd_b_usdhc3_cd_b: IOMUXC_GPIO1_IO14_USDHC_CD_B_USDHC3_CD_B { 595 pinmux = <0x3033004c 4 0x30330608 0 0x303302ac>; 596 }; 597 /omit-if-no-ref/ iomuxc_gpio1_io15_ccm_clko_ccm_clko2: IOMUXC_GPIO1_IO15_CCM_CLKO_CCM_CLKO2 { 598 pinmux = <0x30330050 6 0x0 0 0x303302b0>; 599 }; 600 /omit-if-no-ref/ iomuxc_gpio1_io15_gpio_io_gpio1_io15: IOMUXC_GPIO1_IO15_GPIO_IO_GPIO1_IO15 { 601 pinmux = <0x30330050 0 0x0 0 0x303302b0>; 602 }; 603 /omit-if-no-ref/ iomuxc_gpio1_io15_pwm_out_pwm4_out: IOMUXC_GPIO1_IO15_PWM_OUT_PWM4_OUT { 604 pinmux = <0x30330050 5 0x0 0 0x303302b0>; 605 }; 606 /omit-if-no-ref/ iomuxc_gpio1_io15_usb_oc_usb2_oc: IOMUXC_GPIO1_IO15_USB_OC_USB2_OC { 607 pinmux = <0x30330050 1 0x0 0 0x303302b0>; 608 }; 609 /omit-if-no-ref/ iomuxc_gpio1_io15_usdhc_wp_usdhc3_wp: IOMUXC_GPIO1_IO15_USDHC_WP_USDHC3_WP { 610 pinmux = <0x30330050 4 0x30330634 0 0x303302b0>; 611 }; 612 /omit-if-no-ref/ iomuxc_hdmi_cec_can_tx_can2_tx: IOMUXC_HDMI_CEC_CAN_TX_CAN2_TX { 613 pinmux = <0x30330248 4 0x0 0 0x303304a8>; 614 }; 615 /omit-if-no-ref/ iomuxc_hdmi_cec_gpio_io_gpio3_io28: IOMUXC_HDMI_CEC_GPIO_IO_GPIO3_IO28 { 616 pinmux = <0x30330248 5 0x0 0 0x303304a8>; 617 }; 618 /omit-if-no-ref/ iomuxc_hdmi_cec_hdmi_cec_hdmi_cec: IOMUXC_HDMI_CEC_HDMI_CEC_HDMI_CEC { 619 pinmux = <0x30330248 0 0x0 0 0x303304a8>; 620 }; 621 /omit-if-no-ref/ iomuxc_hdmi_cec_i2c_scl_i2c6_scl: IOMUXC_HDMI_CEC_I2C_SCL_I2C6_SCL { 622 pinmux = <0x30330248 3 0x303305cc 3 0x303304a8>; 623 }; 624 /omit-if-no-ref/ iomuxc_hdmi_ddc_scl_can_tx_can1_tx: IOMUXC_HDMI_DDC_SCL_CAN_TX_CAN1_TX { 625 pinmux = <0x30330240 4 0x0 0 0x303304a0>; 626 }; 627 /omit-if-no-ref/ iomuxc_hdmi_ddc_scl_gpio_io_gpio3_io26: IOMUXC_HDMI_DDC_SCL_GPIO_IO_GPIO3_IO26 { 628 pinmux = <0x30330240 5 0x0 0 0x303304a0>; 629 }; 630 /omit-if-no-ref/ iomuxc_hdmi_ddc_scl_hdmi_scl_hdmi_scl: IOMUXC_HDMI_DDC_SCL_HDMI_SCL_HDMI_SCL { 631 pinmux = <0x30330240 0 0x0 0 0x303304a0>; 632 }; 633 /omit-if-no-ref/ iomuxc_hdmi_ddc_scl_i2c_scl_i2c5_scl: IOMUXC_HDMI_DDC_SCL_I2C_SCL_I2C5_SCL { 634 pinmux = <0x30330240 3 0x303305c4 3 0x303304a0>; 635 }; 636 /omit-if-no-ref/ iomuxc_hdmi_ddc_sda_can_rx_can1_rx: IOMUXC_HDMI_DDC_SDA_CAN_RX_CAN1_RX { 637 pinmux = <0x30330244 4 0x3033054c 3 0x303304a4>; 638 }; 639 /omit-if-no-ref/ iomuxc_hdmi_ddc_sda_gpio_io_gpio3_io27: IOMUXC_HDMI_DDC_SDA_GPIO_IO_GPIO3_IO27 { 640 pinmux = <0x30330244 5 0x0 0 0x303304a4>; 641 }; 642 /omit-if-no-ref/ iomuxc_hdmi_ddc_sda_hdmi_sda_hdmi_sda: IOMUXC_HDMI_DDC_SDA_HDMI_SDA_HDMI_SDA { 643 pinmux = <0x30330244 0 0x0 0 0x303304a4>; 644 }; 645 /omit-if-no-ref/ iomuxc_hdmi_ddc_sda_i2c_sda_i2c5_sda: IOMUXC_HDMI_DDC_SDA_I2C_SDA_I2C5_SDA { 646 pinmux = <0x30330244 3 0x303305c8 3 0x303304a4>; 647 }; 648 /omit-if-no-ref/ iomuxc_hdmi_hpd_can_rx_can2_rx: IOMUXC_HDMI_HPD_CAN_RX_CAN2_RX { 649 pinmux = <0x3033024c 4 0x30330550 3 0x303304ac>; 650 }; 651 /omit-if-no-ref/ iomuxc_hdmi_hpd_gpio_io_gpio3_io29: IOMUXC_HDMI_HPD_GPIO_IO_GPIO3_IO29 { 652 pinmux = <0x3033024c 5 0x0 0 0x303304ac>; 653 }; 654 /omit-if-no-ref/ iomuxc_hdmi_hpd_hdmi_hpd_hdmi_hpd: IOMUXC_HDMI_HPD_HDMI_HPD_HDMI_HPD { 655 pinmux = <0x3033024c 0 0x0 0 0x303304ac>; 656 }; 657 /omit-if-no-ref/ iomuxc_hdmi_hpd_hdmi_hpd_o_hdmi_hpd_o: IOMUXC_HDMI_HPD_HDMI_HPD_O_HDMI_HPD_O { 658 pinmux = <0x3033024c 1 0x0 0 0x303304ac>; 659 }; 660 /omit-if-no-ref/ iomuxc_hdmi_hpd_i2c_sda_i2c6_sda: IOMUXC_HDMI_HPD_I2C_SDA_I2C6_SDA { 661 pinmux = <0x3033024c 3 0x303305d0 3 0x303304ac>; 662 }; 663 /omit-if-no-ref/ iomuxc_i2c1_scl_ecspi_sclk_ecspi1_sclk: IOMUXC_I2C1_SCL_ECSPI_SCLK_ECSPI1_SCLK { 664 pinmux = <0x30330200 3 0x30330558 1 0x30330460>; 665 }; 666 /omit-if-no-ref/ iomuxc_i2c1_scl_enet_qos_mdc_enet_qos_mdc: IOMUXC_I2C1_SCL_ENET_QOS_MDC_ENET_QOS_MDC { 667 pinmux = <0x30330200 1 0x0 0 0x30330460>; 668 }; 669 /omit-if-no-ref/ iomuxc_i2c1_scl_gpio_io_gpio5_io14: IOMUXC_I2C1_SCL_GPIO_IO_GPIO5_IO14 { 670 pinmux = <0x30330200 5 0x0 0 0x30330460>; 671 }; 672 /omit-if-no-ref/ iomuxc_i2c1_scl_i2c_scl_i2c1_scl: IOMUXC_I2C1_SCL_I2C_SCL_I2C1_SCL { 673 pinmux = <0x30330200 0 0x303305a4 2 0x30330460>; 674 }; 675 /omit-if-no-ref/ iomuxc_i2c1_sda_ecspi_mosi_ecspi1_mosi: IOMUXC_I2C1_SDA_ECSPI_MOSI_ECSPI1_MOSI { 676 pinmux = <0x30330204 3 0x30330560 1 0x30330464>; 677 }; 678 /omit-if-no-ref/ iomuxc_i2c1_sda_enet_qos_mdio_enet_qos_mdio: IOMUXC_I2C1_SDA_ENET_QOS_MDIO_ENET_QOS_MDIO { 679 pinmux = <0x30330204 1 0x30330590 2 0x30330464>; 680 }; 681 /omit-if-no-ref/ iomuxc_i2c1_sda_gpio_io_gpio5_io15: IOMUXC_I2C1_SDA_GPIO_IO_GPIO5_IO15 { 682 pinmux = <0x30330204 5 0x0 0 0x30330464>; 683 }; 684 /omit-if-no-ref/ iomuxc_i2c1_sda_i2c_sda_i2c1_sda: IOMUXC_I2C1_SDA_I2C_SDA_I2C1_SDA { 685 pinmux = <0x30330204 0 0x303305a8 2 0x30330464>; 686 }; 687 /omit-if-no-ref/ iomuxc_i2c2_scl_ecspi_miso_ecspi1_miso: IOMUXC_I2C2_SCL_ECSPI_MISO_ECSPI1_MISO { 688 pinmux = <0x30330208 3 0x3033055c 1 0x30330468>; 689 }; 690 /omit-if-no-ref/ iomuxc_i2c2_scl_enet_qos_1588_event1_aux_in_enet_qos_1588_event1_aux_in: IOMUXC_I2C2_SCL_ENET_QOS_1588_EVENT1_AUX_IN_ENET_QOS_1588_EVENT1_AUX_IN { 691 pinmux = <0x30330208 4 0x0 0 0x30330468>; 692 }; 693 /omit-if-no-ref/ iomuxc_i2c2_scl_enet_qos_1588_event1_in_enet_qos_1588_event1_in: IOMUXC_I2C2_SCL_ENET_QOS_1588_EVENT1_IN_ENET_QOS_1588_EVENT1_IN { 694 pinmux = <0x30330208 1 0x0 0 0x30330468>; 695 }; 696 /omit-if-no-ref/ iomuxc_i2c2_scl_gpio_io_gpio5_io16: IOMUXC_I2C2_SCL_GPIO_IO_GPIO5_IO16 { 697 pinmux = <0x30330208 5 0x0 0 0x30330468>; 698 }; 699 /omit-if-no-ref/ iomuxc_i2c2_scl_i2c_scl_i2c2_scl: IOMUXC_I2C2_SCL_I2C_SCL_I2C2_SCL { 700 pinmux = <0x30330208 0 0x303305ac 2 0x30330468>; 701 }; 702 /omit-if-no-ref/ iomuxc_i2c2_scl_usdhc_cd_b_usdhc3_cd_b: IOMUXC_I2C2_SCL_USDHC_CD_B_USDHC3_CD_B { 703 pinmux = <0x30330208 2 0x30330608 3 0x30330468>; 704 }; 705 /omit-if-no-ref/ iomuxc_i2c2_sda_ecspi_ss_ecspi1_ss0: IOMUXC_I2C2_SDA_ECSPI_SS_ECSPI1_SS0 { 706 pinmux = <0x3033020c 3 0x30330564 1 0x3033046c>; 707 }; 708 /omit-if-no-ref/ iomuxc_i2c2_sda_enet_qos_1588_event1_out_enet_qos_1588_event1_out: IOMUXC_I2C2_SDA_ENET_QOS_1588_EVENT1_OUT_ENET_QOS_1588_EVENT1_OUT { 709 pinmux = <0x3033020c 1 0x0 0 0x3033046c>; 710 }; 711 /omit-if-no-ref/ iomuxc_i2c2_sda_gpio_io_gpio5_io17: IOMUXC_I2C2_SDA_GPIO_IO_GPIO5_IO17 { 712 pinmux = <0x3033020c 5 0x0 0 0x3033046c>; 713 }; 714 /omit-if-no-ref/ iomuxc_i2c2_sda_i2c_sda_i2c2_sda: IOMUXC_I2C2_SDA_I2C_SDA_I2C2_SDA { 715 pinmux = <0x3033020c 0 0x303305b0 2 0x3033046c>; 716 }; 717 /omit-if-no-ref/ iomuxc_i2c2_sda_usdhc_wp_usdhc3_wp: IOMUXC_I2C2_SDA_USDHC_WP_USDHC3_WP { 718 pinmux = <0x3033020c 2 0x30330634 3 0x3033046c>; 719 }; 720 /omit-if-no-ref/ iomuxc_i2c3_scl_ecspi_sclk_ecspi2_sclk: IOMUXC_I2C3_SCL_ECSPI_SCLK_ECSPI2_SCLK { 721 pinmux = <0x30330210 3 0x30330568 2 0x30330470>; 722 }; 723 /omit-if-no-ref/ iomuxc_i2c3_scl_gpio_io_gpio5_io18: IOMUXC_I2C3_SCL_GPIO_IO_GPIO5_IO18 { 724 pinmux = <0x30330210 5 0x0 0 0x30330470>; 725 }; 726 /omit-if-no-ref/ iomuxc_i2c3_scl_gpt_clk_gpt2_clk: IOMUXC_I2C3_SCL_GPT_CLK_GPT2_CLK { 727 pinmux = <0x30330210 2 0x0 0 0x30330470>; 728 }; 729 /omit-if-no-ref/ iomuxc_i2c3_scl_i2c_scl_i2c3_scl: IOMUXC_I2C3_SCL_I2C_SCL_I2C3_SCL { 730 pinmux = <0x30330210 0 0x303305b4 4 0x30330470>; 731 }; 732 /omit-if-no-ref/ iomuxc_i2c3_scl_pwm_out_pwm4_out: IOMUXC_I2C3_SCL_PWM_OUT_PWM4_OUT { 733 pinmux = <0x30330210 1 0x0 0 0x30330470>; 734 }; 735 /omit-if-no-ref/ iomuxc_i2c3_sda_ecspi_mosi_ecspi2_mosi: IOMUXC_I2C3_SDA_ECSPI_MOSI_ECSPI2_MOSI { 736 pinmux = <0x30330214 3 0x30330570 2 0x30330474>; 737 }; 738 /omit-if-no-ref/ iomuxc_i2c3_sda_gpio_io_gpio5_io19: IOMUXC_I2C3_SDA_GPIO_IO_GPIO5_IO19 { 739 pinmux = <0x30330214 5 0x0 0 0x30330474>; 740 }; 741 /omit-if-no-ref/ iomuxc_i2c3_sda_gpt_clk_gpt3_clk: IOMUXC_I2C3_SDA_GPT_CLK_GPT3_CLK { 742 pinmux = <0x30330214 2 0x0 0 0x30330474>; 743 }; 744 /omit-if-no-ref/ iomuxc_i2c3_sda_i2c_sda_i2c3_sda: IOMUXC_I2C3_SDA_I2C_SDA_I2C3_SDA { 745 pinmux = <0x30330214 0 0x303305b8 4 0x30330474>; 746 }; 747 /omit-if-no-ref/ iomuxc_i2c3_sda_pwm_out_pwm3_out: IOMUXC_I2C3_SDA_PWM_OUT_PWM3_OUT { 748 pinmux = <0x30330214 1 0x0 0 0x30330474>; 749 }; 750 /omit-if-no-ref/ iomuxc_i2c4_scl_ecspi_miso_ecspi2_miso: IOMUXC_I2C4_SCL_ECSPI_MISO_ECSPI2_MISO { 751 pinmux = <0x30330218 3 0x3033056c 2 0x30330478>; 752 }; 753 /omit-if-no-ref/ iomuxc_i2c4_scl_gpio_io_gpio5_io20: IOMUXC_I2C4_SCL_GPIO_IO_GPIO5_IO20 { 754 pinmux = <0x30330218 5 0x0 0 0x30330478>; 755 }; 756 /omit-if-no-ref/ iomuxc_i2c4_scl_i2c_scl_i2c4_scl: IOMUXC_I2C4_SCL_I2C_SCL_I2C4_SCL { 757 pinmux = <0x30330218 0 0x303305bc 5 0x30330478>; 758 }; 759 /omit-if-no-ref/ iomuxc_i2c4_scl_pcie_clkreq_b_pcie1_clkreq_b: IOMUXC_I2C4_SCL_PCIE_CLKREQ_B_PCIE1_CLKREQ_B { 760 pinmux = <0x30330218 2 0x303305a0 0 0x30330478>; 761 }; 762 /omit-if-no-ref/ iomuxc_i2c4_scl_pwm_out_pwm2_out: IOMUXC_I2C4_SCL_PWM_OUT_PWM2_OUT { 763 pinmux = <0x30330218 1 0x0 0 0x30330478>; 764 }; 765 /omit-if-no-ref/ iomuxc_i2c4_sda_ecspi_ss_ecspi2_ss0: IOMUXC_I2C4_SDA_ECSPI_SS_ECSPI2_SS0 { 766 pinmux = <0x3033021c 3 0x30330574 2 0x3033047c>; 767 }; 768 /omit-if-no-ref/ iomuxc_i2c4_sda_gpio_io_gpio5_io21: IOMUXC_I2C4_SDA_GPIO_IO_GPIO5_IO21 { 769 pinmux = <0x3033021c 5 0x0 0 0x3033047c>; 770 }; 771 /omit-if-no-ref/ iomuxc_i2c4_sda_i2c_sda_i2c4_sda: IOMUXC_I2C4_SDA_I2C_SDA_I2C4_SDA { 772 pinmux = <0x3033021c 0 0x303305c0 5 0x3033047c>; 773 }; 774 /omit-if-no-ref/ iomuxc_i2c4_sda_pwm_out_pwm1_out: IOMUXC_I2C4_SDA_PWM_OUT_PWM1_OUT { 775 pinmux = <0x3033021c 1 0x0 0 0x3033047c>; 776 }; 777 /omit-if-no-ref/ iomuxc_jtag_mod_jtag_mode_jtag_mode: IOMUXC_JTAG_MOD_JTAG_MODE_JTAG_MODE { 778 pinmux = <0x0 0 0x0 0 0x30330260>; 779 }; 780 /omit-if-no-ref/ iomuxc_jtag_tck_jtag_tck_jtag_tck: IOMUXC_JTAG_TCK_JTAG_TCK_JTAG_TCK { 781 pinmux = <0x0 0 0x0 0 0x3033026c>; 782 }; 783 /omit-if-no-ref/ iomuxc_jtag_tdi_jtag_tdi_jtag_tdi: IOMUXC_JTAG_TDI_JTAG_TDI_JTAG_TDI { 784 pinmux = <0x0 0 0x0 0 0x30330264>; 785 }; 786 /omit-if-no-ref/ iomuxc_jtag_tdo_jtag_tdo_jtag_tdo: IOMUXC_JTAG_TDO_JTAG_TDO_JTAG_TDO { 787 pinmux = <0x0 0 0x0 0 0x30330270>; 788 }; 789 /omit-if-no-ref/ iomuxc_jtag_tms_jtag_tms_jtag_tms: IOMUXC_JTAG_TMS_JTAG_TMS_JTAG_TMS { 790 pinmux = <0x0 0 0x0 0 0x30330268>; 791 }; 792 /omit-if-no-ref/ iomuxc_nand_ale_coresight_trace_clk_coresight_trace_clk: IOMUXC_NAND_ALE_CORESIGHT_TRACE_CLK_CORESIGHT_TRACE_CLK { 793 pinmux = <0x303300e0 6 0x0 0 0x30330340>; 794 }; 795 /omit-if-no-ref/ iomuxc_nand_ale_gpio_io_gpio3_io0: IOMUXC_NAND_ALE_GPIO_IO_GPIO3_IO0 { 796 pinmux = <0x303300e0 5 0x0 0 0x30330340>; 797 }; 798 /omit-if-no-ref/ iomuxc_nand_ale_isp_fl_trig_isp_fl_trig_0: IOMUXC_NAND_ALE_ISP_FL_TRIG_ISP_FL_TRIG_0 { 799 pinmux = <0x303300e0 3 0x303305d4 1 0x30330340>; 800 }; 801 /omit-if-no-ref/ iomuxc_nand_ale_nand_ale_nand_ale: IOMUXC_NAND_ALE_NAND_ALE_NAND_ALE { 802 pinmux = <0x303300e0 0 0x0 0 0x30330340>; 803 }; 804 /omit-if-no-ref/ iomuxc_nand_ale_qspi_a_sclk_qspi_a_sclk: IOMUXC_NAND_ALE_QSPI_A_SCLK_QSPI_A_SCLK { 805 pinmux = <0x303300e0 1 0x0 0 0x30330340>; 806 }; 807 /omit-if-no-ref/ iomuxc_nand_ale_sai_tx_bclk_sai3_tx_bclk: IOMUXC_NAND_ALE_SAI_TX_BCLK_SAI3_TX_BCLK { 808 pinmux = <0x303300e0 2 0x303304e8 0 0x30330340>; 809 }; 810 /omit-if-no-ref/ iomuxc_nand_ale_uart_rx_uart3_rx: IOMUXC_NAND_ALE_UART_RX_UART3_RX { 811 pinmux = <0x303300e0 4 0x303305f8 2 0x30330340>; 812 }; 813 /omit-if-no-ref/ iomuxc_nand_ale_uart_tx_uart3_rx: IOMUXC_NAND_ALE_UART_TX_UART3_RX { 814 pinmux = <0x303300e0 4 0x0 0 0x30330340>; 815 }; 816 /omit-if-no-ref/ iomuxc_nand_ce0_b_coresight_trace_ctl_coresight_trace_ctl: IOMUXC_NAND_CE0_B_CORESIGHT_TRACE_CTL_CORESIGHT_TRACE_CTL { 817 pinmux = <0x303300e4 6 0x0 0 0x30330344>; 818 }; 819 /omit-if-no-ref/ iomuxc_nand_ce0_b_gpio_io_gpio3_io1: IOMUXC_NAND_CE0_B_GPIO_IO_GPIO3_IO1 { 820 pinmux = <0x303300e4 5 0x0 0 0x30330344>; 821 }; 822 /omit-if-no-ref/ iomuxc_nand_ce0_b_isp_shutter_trig_isp_shutter_trig_0: IOMUXC_NAND_CE0_B_ISP_SHUTTER_TRIG_ISP_SHUTTER_TRIG_0 { 823 pinmux = <0x303300e4 3 0x303305dc 1 0x30330344>; 824 }; 825 /omit-if-no-ref/ iomuxc_nand_ce0_b_nand_ce0_b_nand_ce0_b: IOMUXC_NAND_CE0_B_NAND_CE0_B_NAND_CE0_B { 826 pinmux = <0x303300e4 0 0x0 0 0x30330344>; 827 }; 828 /omit-if-no-ref/ iomuxc_nand_ce0_b_qspi_a_ss0_b_qspi_a_ss0_b: IOMUXC_NAND_CE0_B_QSPI_A_SS0_B_QSPI_A_SS0_B { 829 pinmux = <0x303300e4 1 0x0 0 0x30330344>; 830 }; 831 /omit-if-no-ref/ iomuxc_nand_ce0_b_sai_tx_data_sai3_tx_data0: IOMUXC_NAND_CE0_B_SAI_TX_DATA_SAI3_TX_DATA0 { 832 pinmux = <0x303300e4 2 0x0 0 0x30330344>; 833 }; 834 /omit-if-no-ref/ iomuxc_nand_ce0_b_uart_rx_uart3_tx: IOMUXC_NAND_CE0_B_UART_RX_UART3_TX { 835 pinmux = <0x303300e4 4 0x303305f8 3 0x30330344>; 836 }; 837 /omit-if-no-ref/ iomuxc_nand_ce0_b_uart_tx_uart3_tx: IOMUXC_NAND_CE0_B_UART_TX_UART3_TX { 838 pinmux = <0x303300e4 4 0x0 0 0x30330344>; 839 }; 840 /omit-if-no-ref/ iomuxc_nand_ce1_b_coresight_trace_coresight_trace0: IOMUXC_NAND_CE1_B_CORESIGHT_TRACE_CORESIGHT_TRACE0 { 841 pinmux = <0x303300e8 6 0x0 0 0x30330348>; 842 }; 843 /omit-if-no-ref/ iomuxc_nand_ce1_b_gpio_io_gpio3_io2: IOMUXC_NAND_CE1_B_GPIO_IO_GPIO3_IO2 { 844 pinmux = <0x303300e8 5 0x0 0 0x30330348>; 845 }; 846 /omit-if-no-ref/ iomuxc_nand_ce1_b_i2c_scl_i2c4_scl: IOMUXC_NAND_CE1_B_I2C_SCL_I2C4_SCL { 847 pinmux = <0x303300e8 4 0x303305bc 2 0x30330348>; 848 }; 849 /omit-if-no-ref/ iomuxc_nand_ce1_b_nand_ce1_b_nand_ce1_b: IOMUXC_NAND_CE1_B_NAND_CE1_B_NAND_CE1_B { 850 pinmux = <0x303300e8 0 0x0 0 0x30330348>; 851 }; 852 /omit-if-no-ref/ iomuxc_nand_ce1_b_qspi_a_ss1_b_qspi_a_ss1_b: IOMUXC_NAND_CE1_B_QSPI_A_SS1_B_QSPI_A_SS1_B { 853 pinmux = <0x303300e8 1 0x0 0 0x30330348>; 854 }; 855 /omit-if-no-ref/ iomuxc_nand_ce1_b_usdhc_strobe_usdhc3_strobe: IOMUXC_NAND_CE1_B_USDHC_STROBE_USDHC3_STROBE { 856 pinmux = <0x303300e8 2 0x30330630 1 0x30330348>; 857 }; 858 /omit-if-no-ref/ iomuxc_nand_ce2_b_coresight_trace_coresight_trace1: IOMUXC_NAND_CE2_B_CORESIGHT_TRACE_CORESIGHT_TRACE1 { 859 pinmux = <0x303300ec 6 0x0 0 0x3033034c>; 860 }; 861 /omit-if-no-ref/ iomuxc_nand_ce2_b_gpio_io_gpio3_io3: IOMUXC_NAND_CE2_B_GPIO_IO_GPIO3_IO3 { 862 pinmux = <0x303300ec 5 0x0 0 0x3033034c>; 863 }; 864 /omit-if-no-ref/ iomuxc_nand_ce2_b_i2c_sda_i2c4_sda: IOMUXC_NAND_CE2_B_I2C_SDA_I2C4_SDA { 865 pinmux = <0x303300ec 4 0x303305c0 2 0x3033034c>; 866 }; 867 /omit-if-no-ref/ iomuxc_nand_ce2_b_nand_ce2_b_nand_ce2_b: IOMUXC_NAND_CE2_B_NAND_CE2_B_NAND_CE2_B { 868 pinmux = <0x303300ec 0 0x0 0 0x3033034c>; 869 }; 870 /omit-if-no-ref/ iomuxc_nand_ce2_b_qspi_b_ss0_b_qspi_b_ss0_b: IOMUXC_NAND_CE2_B_QSPI_B_SS0_B_QSPI_B_SS0_B { 871 pinmux = <0x303300ec 1 0x0 0 0x3033034c>; 872 }; 873 /omit-if-no-ref/ iomuxc_nand_ce2_b_usdhc_data_usdhc3_data5: IOMUXC_NAND_CE2_B_USDHC_DATA_USDHC3_DATA5 { 874 pinmux = <0x303300ec 2 0x30330624 1 0x3033034c>; 875 }; 876 /omit-if-no-ref/ iomuxc_nand_ce3_b_coresight_trace_coresight_trace2: IOMUXC_NAND_CE3_B_CORESIGHT_TRACE_CORESIGHT_TRACE2 { 877 pinmux = <0x303300f0 6 0x0 0 0x30330350>; 878 }; 879 /omit-if-no-ref/ iomuxc_nand_ce3_b_gpio_io_gpio3_io4: IOMUXC_NAND_CE3_B_GPIO_IO_GPIO3_IO4 { 880 pinmux = <0x303300f0 5 0x0 0 0x30330350>; 881 }; 882 /omit-if-no-ref/ iomuxc_nand_ce3_b_i2c_sda_i2c3_sda: IOMUXC_NAND_CE3_B_I2C_SDA_I2C3_SDA { 883 pinmux = <0x303300f0 4 0x303305b8 1 0x30330350>; 884 }; 885 /omit-if-no-ref/ iomuxc_nand_ce3_b_nand_ce3_b_nand_ce3_b: IOMUXC_NAND_CE3_B_NAND_CE3_B_NAND_CE3_B { 886 pinmux = <0x303300f0 0 0x0 0 0x30330350>; 887 }; 888 /omit-if-no-ref/ iomuxc_nand_ce3_b_qspi_b_ss1_b_qspi_b_ss1_b: IOMUXC_NAND_CE3_B_QSPI_B_SS1_B_QSPI_B_SS1_B { 889 pinmux = <0x303300f0 1 0x0 0 0x30330350>; 890 }; 891 /omit-if-no-ref/ iomuxc_nand_ce3_b_usdhc_data_usdhc3_data6: IOMUXC_NAND_CE3_B_USDHC_DATA_USDHC3_DATA6 { 892 pinmux = <0x303300f0 2 0x30330628 1 0x30330350>; 893 }; 894 /omit-if-no-ref/ iomuxc_nand_cle_coresight_trace_coresight_trace3: IOMUXC_NAND_CLE_CORESIGHT_TRACE_CORESIGHT_TRACE3 { 895 pinmux = <0x303300f4 6 0x0 0 0x30330354>; 896 }; 897 /omit-if-no-ref/ iomuxc_nand_cle_gpio_io_gpio3_io5: IOMUXC_NAND_CLE_GPIO_IO_GPIO3_IO5 { 898 pinmux = <0x303300f4 5 0x0 0 0x30330354>; 899 }; 900 /omit-if-no-ref/ iomuxc_nand_cle_nand_cle_nand_cle: IOMUXC_NAND_CLE_NAND_CLE_NAND_CLE { 901 pinmux = <0x303300f4 0 0x0 0 0x30330354>; 902 }; 903 /omit-if-no-ref/ iomuxc_nand_cle_qspi_b_sclk_qspi_b_sclk: IOMUXC_NAND_CLE_QSPI_B_SCLK_QSPI_B_SCLK { 904 pinmux = <0x303300f4 1 0x0 0 0x30330354>; 905 }; 906 /omit-if-no-ref/ iomuxc_nand_cle_uart_rx_uart4_rx: IOMUXC_NAND_CLE_UART_RX_UART4_RX { 907 pinmux = <0x303300f4 4 0x30330600 2 0x30330354>; 908 }; 909 /omit-if-no-ref/ iomuxc_nand_cle_uart_tx_uart4_rx: IOMUXC_NAND_CLE_UART_TX_UART4_RX { 910 pinmux = <0x303300f4 4 0x0 0 0x30330354>; 911 }; 912 /omit-if-no-ref/ iomuxc_nand_cle_usdhc_data_usdhc3_data7: IOMUXC_NAND_CLE_USDHC_DATA_USDHC3_DATA7 { 913 pinmux = <0x303300f4 2 0x3033062c 1 0x30330354>; 914 }; 915 /omit-if-no-ref/ iomuxc_nand_data00_coresight_trace_coresight_trace4: IOMUXC_NAND_DATA00_CORESIGHT_TRACE_CORESIGHT_TRACE4 { 916 pinmux = <0x303300f8 6 0x0 0 0x30330358>; 917 }; 918 /omit-if-no-ref/ iomuxc_nand_data00_gpio_io_gpio3_io6: IOMUXC_NAND_DATA00_GPIO_IO_GPIO3_IO6 { 919 pinmux = <0x303300f8 5 0x0 0 0x30330358>; 920 }; 921 /omit-if-no-ref/ iomuxc_nand_data00_isp_flash_trig_isp_flash_trig_0: IOMUXC_NAND_DATA00_ISP_FLASH_TRIG_ISP_FLASH_TRIG_0 { 922 pinmux = <0x303300f8 3 0x0 0 0x30330358>; 923 }; 924 /omit-if-no-ref/ iomuxc_nand_data00_nand_data_nand_data00: IOMUXC_NAND_DATA00_NAND_DATA_NAND_DATA00 { 925 pinmux = <0x303300f8 0 0x0 0 0x30330358>; 926 }; 927 /omit-if-no-ref/ iomuxc_nand_data00_qspi_a_data_qspi_a_data0: IOMUXC_NAND_DATA00_QSPI_A_DATA_QSPI_A_DATA0 { 928 pinmux = <0x303300f8 1 0x0 0 0x30330358>; 929 }; 930 /omit-if-no-ref/ iomuxc_nand_data00_sai_rx_data_sai3_rx_data0: IOMUXC_NAND_DATA00_SAI_RX_DATA_SAI3_RX_DATA0 { 931 pinmux = <0x303300f8 2 0x303304e4 0 0x30330358>; 932 }; 933 /omit-if-no-ref/ iomuxc_nand_data00_uart_rx_uart4_rx: IOMUXC_NAND_DATA00_UART_RX_UART4_RX { 934 pinmux = <0x303300f8 4 0x30330600 3 0x30330358>; 935 }; 936 /omit-if-no-ref/ iomuxc_nand_data00_uart_tx_uart4_rx: IOMUXC_NAND_DATA00_UART_TX_UART4_RX { 937 pinmux = <0x303300f8 4 0x0 0 0x30330358>; 938 }; 939 /omit-if-no-ref/ iomuxc_nand_data01_coresight_trace_coresight_trace5: IOMUXC_NAND_DATA01_CORESIGHT_TRACE_CORESIGHT_TRACE5 { 940 pinmux = <0x303300fc 6 0x0 0 0x3033035c>; 941 }; 942 /omit-if-no-ref/ iomuxc_nand_data01_gpio_io_gpio3_io7: IOMUXC_NAND_DATA01_GPIO_IO_GPIO3_IO7 { 943 pinmux = <0x303300fc 5 0x0 0 0x3033035c>; 944 }; 945 /omit-if-no-ref/ iomuxc_nand_data01_isp_prelight_trig_isp_prelight_trig_0: IOMUXC_NAND_DATA01_ISP_PRELIGHT_TRIG_ISP_PRELIGHT_TRIG_0 { 946 pinmux = <0x303300fc 3 0x0 0 0x3033035c>; 947 }; 948 /omit-if-no-ref/ iomuxc_nand_data01_nand_data_nand_data01: IOMUXC_NAND_DATA01_NAND_DATA_NAND_DATA01 { 949 pinmux = <0x303300fc 0 0x0 0 0x3033035c>; 950 }; 951 /omit-if-no-ref/ iomuxc_nand_data01_qspi_a_data_qspi_a_data1: IOMUXC_NAND_DATA01_QSPI_A_DATA_QSPI_A_DATA1 { 952 pinmux = <0x303300fc 1 0x0 0 0x3033035c>; 953 }; 954 /omit-if-no-ref/ iomuxc_nand_data01_sai_tx_sync_sai3_tx_sync: IOMUXC_NAND_DATA01_SAI_TX_SYNC_SAI3_TX_SYNC { 955 pinmux = <0x303300fc 2 0x303304ec 0 0x3033035c>; 956 }; 957 /omit-if-no-ref/ iomuxc_nand_data01_uart_rx_uart4_tx: IOMUXC_NAND_DATA01_UART_RX_UART4_TX { 958 pinmux = <0x303300fc 4 0x30330600 4 0x3033035c>; 959 }; 960 /omit-if-no-ref/ iomuxc_nand_data01_uart_tx_uart4_tx: IOMUXC_NAND_DATA01_UART_TX_UART4_TX { 961 pinmux = <0x303300fc 4 0x0 0 0x3033035c>; 962 }; 963 /omit-if-no-ref/ iomuxc_nand_data02_coresight_trace_coresight_trace6: IOMUXC_NAND_DATA02_CORESIGHT_TRACE_CORESIGHT_TRACE6 { 964 pinmux = <0x30330100 6 0x0 0 0x30330360>; 965 }; 966 /omit-if-no-ref/ iomuxc_nand_data02_gpio_io_gpio3_io8: IOMUXC_NAND_DATA02_GPIO_IO_GPIO3_IO8 { 967 pinmux = <0x30330100 5 0x0 0 0x30330360>; 968 }; 969 /omit-if-no-ref/ iomuxc_nand_data02_i2c_sda_i2c4_sda: IOMUXC_NAND_DATA02_I2C_SDA_I2C4_SDA { 970 pinmux = <0x30330100 4 0x303305c0 3 0x30330360>; 971 }; 972 /omit-if-no-ref/ iomuxc_nand_data02_nand_data_nand_data02: IOMUXC_NAND_DATA02_NAND_DATA_NAND_DATA02 { 973 pinmux = <0x30330100 0 0x0 0 0x30330360>; 974 }; 975 /omit-if-no-ref/ iomuxc_nand_data02_qspi_a_data_qspi_a_data2: IOMUXC_NAND_DATA02_QSPI_A_DATA_QSPI_A_DATA2 { 976 pinmux = <0x30330100 1 0x0 0 0x30330360>; 977 }; 978 /omit-if-no-ref/ iomuxc_nand_data02_uart_cts_b_uart4_cts_b: IOMUXC_NAND_DATA02_UART_CTS_B_UART4_CTS_B { 979 pinmux = <0x30330100 3 0x0 0 0x30330360>; 980 }; 981 /omit-if-no-ref/ iomuxc_nand_data02_uart_rts_b_uart4_cts_b: IOMUXC_NAND_DATA02_UART_RTS_B_UART4_CTS_B { 982 pinmux = <0x30330100 3 0x303305fc 0 0x30330360>; 983 }; 984 /omit-if-no-ref/ iomuxc_nand_data02_usdhc_cd_b_usdhc3_cd_b: IOMUXC_NAND_DATA02_USDHC_CD_B_USDHC3_CD_B { 985 pinmux = <0x30330100 2 0x30330608 2 0x30330360>; 986 }; 987 /omit-if-no-ref/ iomuxc_nand_data03_coresight_trace_coresight_trace7: IOMUXC_NAND_DATA03_CORESIGHT_TRACE_CORESIGHT_TRACE7 { 988 pinmux = <0x30330104 6 0x0 0 0x30330364>; 989 }; 990 /omit-if-no-ref/ iomuxc_nand_data03_gpio_io_gpio3_io9: IOMUXC_NAND_DATA03_GPIO_IO_GPIO3_IO9 { 991 pinmux = <0x30330104 5 0x0 0 0x30330364>; 992 }; 993 /omit-if-no-ref/ iomuxc_nand_data03_isp_fl_trig_isp_fl_trig_1: IOMUXC_NAND_DATA03_ISP_FL_TRIG_ISP_FL_TRIG_1 { 994 pinmux = <0x30330104 4 0x303305d8 1 0x30330364>; 995 }; 996 /omit-if-no-ref/ iomuxc_nand_data03_nand_data_nand_data03: IOMUXC_NAND_DATA03_NAND_DATA_NAND_DATA03 { 997 pinmux = <0x30330104 0 0x0 0 0x30330364>; 998 }; 999 /omit-if-no-ref/ iomuxc_nand_data03_qspi_a_data_qspi_a_data3: IOMUXC_NAND_DATA03_QSPI_A_DATA_QSPI_A_DATA3 { 1000 pinmux = <0x30330104 1 0x0 0 0x30330364>; 1001 }; 1002 /omit-if-no-ref/ iomuxc_nand_data03_uart_cts_b_uart4_rts_b: IOMUXC_NAND_DATA03_UART_CTS_B_UART4_RTS_B { 1003 pinmux = <0x30330104 3 0x0 0 0x30330364>; 1004 }; 1005 /omit-if-no-ref/ iomuxc_nand_data03_uart_rts_b_uart4_rts_b: IOMUXC_NAND_DATA03_UART_RTS_B_UART4_RTS_B { 1006 pinmux = <0x30330104 3 0x303305fc 1 0x30330364>; 1007 }; 1008 /omit-if-no-ref/ iomuxc_nand_data03_usdhc_wp_usdhc3_wp: IOMUXC_NAND_DATA03_USDHC_WP_USDHC3_WP { 1009 pinmux = <0x30330104 2 0x30330634 2 0x30330364>; 1010 }; 1011 /omit-if-no-ref/ iomuxc_nand_data04_coresight_trace_coresight_trace8: IOMUXC_NAND_DATA04_CORESIGHT_TRACE_CORESIGHT_TRACE8 { 1012 pinmux = <0x30330108 6 0x0 0 0x30330368>; 1013 }; 1014 /omit-if-no-ref/ iomuxc_nand_data04_gpio_io_gpio3_io10: IOMUXC_NAND_DATA04_GPIO_IO_GPIO3_IO10 { 1015 pinmux = <0x30330108 5 0x0 0 0x30330368>; 1016 }; 1017 /omit-if-no-ref/ iomuxc_nand_data04_isp_shutter_trig_isp_shutter_trig_1: IOMUXC_NAND_DATA04_ISP_SHUTTER_TRIG_ISP_SHUTTER_TRIG_1 { 1018 pinmux = <0x30330108 4 0x303305e0 1 0x30330368>; 1019 }; 1020 /omit-if-no-ref/ iomuxc_nand_data04_nand_data_nand_data04: IOMUXC_NAND_DATA04_NAND_DATA_NAND_DATA04 { 1021 pinmux = <0x30330108 0 0x0 0 0x30330368>; 1022 }; 1023 /omit-if-no-ref/ iomuxc_nand_data04_qspi_a_data_qspi_a_data4: IOMUXC_NAND_DATA04_QSPI_A_DATA_QSPI_A_DATA4 { 1024 pinmux = <0x30330108 3 0x0 0 0x30330368>; 1025 }; 1026 /omit-if-no-ref/ iomuxc_nand_data04_qspi_b_data_qspi_b_data0: IOMUXC_NAND_DATA04_QSPI_B_DATA_QSPI_B_DATA0 { 1027 pinmux = <0x30330108 1 0x0 0 0x30330368>; 1028 }; 1029 /omit-if-no-ref/ iomuxc_nand_data04_usdhc_data_usdhc3_data0: IOMUXC_NAND_DATA04_USDHC_DATA_USDHC3_DATA0 { 1030 pinmux = <0x30330108 2 0x30330610 1 0x30330368>; 1031 }; 1032 /omit-if-no-ref/ iomuxc_nand_data05_coresight_trace_coresight_trace9: IOMUXC_NAND_DATA05_CORESIGHT_TRACE_CORESIGHT_TRACE9 { 1033 pinmux = <0x3033010c 6 0x0 0 0x3033036c>; 1034 }; 1035 /omit-if-no-ref/ iomuxc_nand_data05_gpio_io_gpio3_io11: IOMUXC_NAND_DATA05_GPIO_IO_GPIO3_IO11 { 1036 pinmux = <0x3033010c 5 0x0 0 0x3033036c>; 1037 }; 1038 /omit-if-no-ref/ iomuxc_nand_data05_isp_flash_trig_isp_flash_trig_1: IOMUXC_NAND_DATA05_ISP_FLASH_TRIG_ISP_FLASH_TRIG_1 { 1039 pinmux = <0x3033010c 4 0x0 0 0x3033036c>; 1040 }; 1041 /omit-if-no-ref/ iomuxc_nand_data05_nand_data_nand_data05: IOMUXC_NAND_DATA05_NAND_DATA_NAND_DATA05 { 1042 pinmux = <0x3033010c 0 0x0 0 0x3033036c>; 1043 }; 1044 /omit-if-no-ref/ iomuxc_nand_data05_qspi_a_data_qspi_a_data5: IOMUXC_NAND_DATA05_QSPI_A_DATA_QSPI_A_DATA5 { 1045 pinmux = <0x3033010c 3 0x0 0 0x3033036c>; 1046 }; 1047 /omit-if-no-ref/ iomuxc_nand_data05_qspi_b_data_qspi_b_data1: IOMUXC_NAND_DATA05_QSPI_B_DATA_QSPI_B_DATA1 { 1048 pinmux = <0x3033010c 1 0x0 0 0x3033036c>; 1049 }; 1050 /omit-if-no-ref/ iomuxc_nand_data05_usdhc_data_usdhc3_data1: IOMUXC_NAND_DATA05_USDHC_DATA_USDHC3_DATA1 { 1051 pinmux = <0x3033010c 2 0x30330614 1 0x3033036c>; 1052 }; 1053 /omit-if-no-ref/ iomuxc_nand_data06_coresight_trace_coresight_trace10: IOMUXC_NAND_DATA06_CORESIGHT_TRACE_CORESIGHT_TRACE10 { 1054 pinmux = <0x30330110 6 0x0 0 0x30330370>; 1055 }; 1056 /omit-if-no-ref/ iomuxc_nand_data06_gpio_io_gpio3_io12: IOMUXC_NAND_DATA06_GPIO_IO_GPIO3_IO12 { 1057 pinmux = <0x30330110 5 0x0 0 0x30330370>; 1058 }; 1059 /omit-if-no-ref/ iomuxc_nand_data06_isp_prelight_trig_isp_prelight_trig_1: IOMUXC_NAND_DATA06_ISP_PRELIGHT_TRIG_ISP_PRELIGHT_TRIG_1 { 1060 pinmux = <0x30330110 4 0x0 0 0x30330370>; 1061 }; 1062 /omit-if-no-ref/ iomuxc_nand_data06_nand_data_nand_data06: IOMUXC_NAND_DATA06_NAND_DATA_NAND_DATA06 { 1063 pinmux = <0x30330110 0 0x0 0 0x30330370>; 1064 }; 1065 /omit-if-no-ref/ iomuxc_nand_data06_qspi_a_data_qspi_a_data6: IOMUXC_NAND_DATA06_QSPI_A_DATA_QSPI_A_DATA6 { 1066 pinmux = <0x30330110 3 0x0 0 0x30330370>; 1067 }; 1068 /omit-if-no-ref/ iomuxc_nand_data06_qspi_b_data_qspi_b_data2: IOMUXC_NAND_DATA06_QSPI_B_DATA_QSPI_B_DATA2 { 1069 pinmux = <0x30330110 1 0x0 0 0x30330370>; 1070 }; 1071 /omit-if-no-ref/ iomuxc_nand_data06_usdhc_data_usdhc3_data2: IOMUXC_NAND_DATA06_USDHC_DATA_USDHC3_DATA2 { 1072 pinmux = <0x30330110 2 0x30330618 1 0x30330370>; 1073 }; 1074 /omit-if-no-ref/ iomuxc_nand_data07_coresight_trace_coresight_trace11: IOMUXC_NAND_DATA07_CORESIGHT_TRACE_CORESIGHT_TRACE11 { 1075 pinmux = <0x30330114 6 0x0 0 0x30330374>; 1076 }; 1077 /omit-if-no-ref/ iomuxc_nand_data07_gpio_io_gpio3_io13: IOMUXC_NAND_DATA07_GPIO_IO_GPIO3_IO13 { 1078 pinmux = <0x30330114 5 0x0 0 0x30330374>; 1079 }; 1080 /omit-if-no-ref/ iomuxc_nand_data07_isp_shutter_open_isp_shutter_open_1: IOMUXC_NAND_DATA07_ISP_SHUTTER_OPEN_ISP_SHUTTER_OPEN_1 { 1081 pinmux = <0x30330114 4 0x0 0 0x30330374>; 1082 }; 1083 /omit-if-no-ref/ iomuxc_nand_data07_nand_data_nand_data07: IOMUXC_NAND_DATA07_NAND_DATA_NAND_DATA07 { 1084 pinmux = <0x30330114 0 0x0 0 0x30330374>; 1085 }; 1086 /omit-if-no-ref/ iomuxc_nand_data07_qspi_a_data_qspi_a_data7: IOMUXC_NAND_DATA07_QSPI_A_DATA_QSPI_A_DATA7 { 1087 pinmux = <0x30330114 3 0x0 0 0x30330374>; 1088 }; 1089 /omit-if-no-ref/ iomuxc_nand_data07_qspi_b_data_qspi_b_data3: IOMUXC_NAND_DATA07_QSPI_B_DATA_QSPI_B_DATA3 { 1090 pinmux = <0x30330114 1 0x0 0 0x30330374>; 1091 }; 1092 /omit-if-no-ref/ iomuxc_nand_data07_usdhc_data_usdhc3_data3: IOMUXC_NAND_DATA07_USDHC_DATA_USDHC3_DATA3 { 1093 pinmux = <0x30330114 2 0x3033061c 1 0x30330374>; 1094 }; 1095 /omit-if-no-ref/ iomuxc_nand_dqs_coresight_trace_coresight_trace12: IOMUXC_NAND_DQS_CORESIGHT_TRACE_CORESIGHT_TRACE12 { 1096 pinmux = <0x30330118 6 0x0 0 0x30330378>; 1097 }; 1098 /omit-if-no-ref/ iomuxc_nand_dqs_gpio_io_gpio3_io14: IOMUXC_NAND_DQS_GPIO_IO_GPIO3_IO14 { 1099 pinmux = <0x30330118 5 0x0 0 0x30330378>; 1100 }; 1101 /omit-if-no-ref/ iomuxc_nand_dqs_i2c_scl_i2c3_scl: IOMUXC_NAND_DQS_I2C_SCL_I2C3_SCL { 1102 pinmux = <0x30330118 4 0x303305b4 1 0x30330378>; 1103 }; 1104 /omit-if-no-ref/ iomuxc_nand_dqs_isp_shutter_open_isp_shutter_open_0: IOMUXC_NAND_DQS_ISP_SHUTTER_OPEN_ISP_SHUTTER_OPEN_0 { 1105 pinmux = <0x30330118 3 0x0 0 0x30330378>; 1106 }; 1107 /omit-if-no-ref/ iomuxc_nand_dqs_nand_dqs_nand_dqs: IOMUXC_NAND_DQS_NAND_DQS_NAND_DQS { 1108 pinmux = <0x30330118 0 0x0 0 0x30330378>; 1109 }; 1110 /omit-if-no-ref/ iomuxc_nand_dqs_qspi_a_dqs_qspi_a_dqs: IOMUXC_NAND_DQS_QSPI_A_DQS_QSPI_A_DQS { 1111 pinmux = <0x30330118 1 0x0 0 0x30330378>; 1112 }; 1113 /omit-if-no-ref/ iomuxc_nand_dqs_sai_mclk_sai3_mclk: IOMUXC_NAND_DQS_SAI_MCLK_SAI3_MCLK { 1114 pinmux = <0x30330118 2 0x303304e0 0 0x30330378>; 1115 }; 1116 /omit-if-no-ref/ iomuxc_nand_ready_b_coresight_trace_coresight_trace14: IOMUXC_NAND_READY_B_CORESIGHT_TRACE_CORESIGHT_TRACE14 { 1117 pinmux = <0x30330120 6 0x0 0 0x30330380>; 1118 }; 1119 /omit-if-no-ref/ iomuxc_nand_ready_b_gpio_io_gpio3_io16: IOMUXC_NAND_READY_B_GPIO_IO_GPIO3_IO16 { 1120 pinmux = <0x30330120 5 0x0 0 0x30330380>; 1121 }; 1122 /omit-if-no-ref/ iomuxc_nand_ready_b_i2c_scl_i2c3_scl: IOMUXC_NAND_READY_B_I2C_SCL_I2C3_SCL { 1123 pinmux = <0x30330120 4 0x303305b4 2 0x30330380>; 1124 }; 1125 /omit-if-no-ref/ iomuxc_nand_ready_b_nand_ready_b_nand_ready_b: IOMUXC_NAND_READY_B_NAND_READY_B_NAND_READY_B { 1126 pinmux = <0x30330120 0 0x0 0 0x30330380>; 1127 }; 1128 /omit-if-no-ref/ iomuxc_nand_ready_b_usdhc_reset_b_usdhc3_reset_b: IOMUXC_NAND_READY_B_USDHC_RESET_B_USDHC3_RESET_B { 1129 pinmux = <0x30330120 2 0x0 0 0x30330380>; 1130 }; 1131 /omit-if-no-ref/ iomuxc_nand_re_b_coresight_trace_coresight_trace13: IOMUXC_NAND_RE_B_CORESIGHT_TRACE_CORESIGHT_TRACE13 { 1132 pinmux = <0x3033011c 6 0x0 0 0x3033037c>; 1133 }; 1134 /omit-if-no-ref/ iomuxc_nand_re_b_gpio_io_gpio3_io15: IOMUXC_NAND_RE_B_GPIO_IO_GPIO3_IO15 { 1135 pinmux = <0x3033011c 5 0x0 0 0x3033037c>; 1136 }; 1137 /omit-if-no-ref/ iomuxc_nand_re_b_nand_re_b_nand_re_b: IOMUXC_NAND_RE_B_NAND_RE_B_NAND_RE_B { 1138 pinmux = <0x3033011c 0 0x0 0 0x3033037c>; 1139 }; 1140 /omit-if-no-ref/ iomuxc_nand_re_b_qspi_b_dqs_qspi_b_dqs: IOMUXC_NAND_RE_B_QSPI_B_DQS_QSPI_B_DQS { 1141 pinmux = <0x3033011c 1 0x0 0 0x3033037c>; 1142 }; 1143 /omit-if-no-ref/ iomuxc_nand_re_b_uart_rx_uart4_tx: IOMUXC_NAND_RE_B_UART_RX_UART4_TX { 1144 pinmux = <0x3033011c 4 0x30330600 5 0x3033037c>; 1145 }; 1146 /omit-if-no-ref/ iomuxc_nand_re_b_uart_tx_uart4_tx: IOMUXC_NAND_RE_B_UART_TX_UART4_TX { 1147 pinmux = <0x3033011c 4 0x0 0 0x3033037c>; 1148 }; 1149 /omit-if-no-ref/ iomuxc_nand_re_b_usdhc_data_usdhc3_data4: IOMUXC_NAND_RE_B_USDHC_DATA_USDHC3_DATA4 { 1150 pinmux = <0x3033011c 2 0x30330620 1 0x3033037c>; 1151 }; 1152 /omit-if-no-ref/ iomuxc_nand_we_b_coresight_trace_coresight_trace15: IOMUXC_NAND_WE_B_CORESIGHT_TRACE_CORESIGHT_TRACE15 { 1153 pinmux = <0x30330124 6 0x0 0 0x30330384>; 1154 }; 1155 /omit-if-no-ref/ iomuxc_nand_we_b_gpio_io_gpio3_io17: IOMUXC_NAND_WE_B_GPIO_IO_GPIO3_IO17 { 1156 pinmux = <0x30330124 5 0x0 0 0x30330384>; 1157 }; 1158 /omit-if-no-ref/ iomuxc_nand_we_b_i2c_sda_i2c3_sda: IOMUXC_NAND_WE_B_I2C_SDA_I2C3_SDA { 1159 pinmux = <0x30330124 4 0x303305b8 2 0x30330384>; 1160 }; 1161 /omit-if-no-ref/ iomuxc_nand_we_b_nand_we_b_nand_we_b: IOMUXC_NAND_WE_B_NAND_WE_B_NAND_WE_B { 1162 pinmux = <0x30330124 0 0x0 0 0x30330384>; 1163 }; 1164 /omit-if-no-ref/ iomuxc_nand_we_b_usdhc_clk_usdhc3_clk: IOMUXC_NAND_WE_B_USDHC_CLK_USDHC3_CLK { 1165 pinmux = <0x30330124 2 0x30330604 1 0x30330384>; 1166 }; 1167 /omit-if-no-ref/ iomuxc_nand_wp_b_coresight_evento_coresight_evento: IOMUXC_NAND_WP_B_CORESIGHT_EVENTO_CORESIGHT_EVENTO { 1168 pinmux = <0x30330128 6 0x0 0 0x30330388>; 1169 }; 1170 /omit-if-no-ref/ iomuxc_nand_wp_b_gpio_io_gpio3_io18: IOMUXC_NAND_WP_B_GPIO_IO_GPIO3_IO18 { 1171 pinmux = <0x30330128 5 0x0 0 0x30330388>; 1172 }; 1173 /omit-if-no-ref/ iomuxc_nand_wp_b_i2c_scl_i2c4_scl: IOMUXC_NAND_WP_B_I2C_SCL_I2C4_SCL { 1174 pinmux = <0x30330128 4 0x303305bc 3 0x30330388>; 1175 }; 1176 /omit-if-no-ref/ iomuxc_nand_wp_b_nand_wp_b_nand_wp_b: IOMUXC_NAND_WP_B_NAND_WP_B_NAND_WP_B { 1177 pinmux = <0x30330128 0 0x0 0 0x30330388>; 1178 }; 1179 /omit-if-no-ref/ iomuxc_nand_wp_b_usdhc_cmd_usdhc3_cmd: IOMUXC_NAND_WP_B_USDHC_CMD_USDHC3_CMD { 1180 pinmux = <0x30330128 2 0x3033060c 1 0x30330388>; 1181 }; 1182 /omit-if-no-ref/ iomuxc_sai1_mclk_enet_tx_clk_enet1_tx_clk: IOMUXC_SAI1_MCLK_ENET_TX_CLK_ENET1_TX_CLK { 1183 pinmux = <0x30330198 4 0x30330578 1 0x303303f8>; 1184 }; 1185 /omit-if-no-ref/ iomuxc_sai1_mclk_gpio_io_gpio4_io20: IOMUXC_SAI1_MCLK_GPIO_IO_GPIO4_IO20 { 1186 pinmux = <0x30330198 5 0x0 0 0x303303f8>; 1187 }; 1188 /omit-if-no-ref/ iomuxc_sai1_mclk_sai_mclk_sai1_mclk: IOMUXC_SAI1_MCLK_SAI_MCLK_SAI1_MCLK { 1189 pinmux = <0x30330198 0 0x0 0 0x303303f8>; 1190 }; 1191 /omit-if-no-ref/ iomuxc_sai1_mclk_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI1_MCLK_SAI_TX_BCLK_SAI1_TX_BCLK { 1192 pinmux = <0x30330198 2 0x303304d4 2 0x303303f8>; 1193 }; 1194 /omit-if-no-ref/ iomuxc_sai1_rxc_enet_1588_event0_out_enet1_1588_event0_out: IOMUXC_SAI1_RXC_ENET_1588_EVENT0_OUT_ENET1_1588_EVENT0_OUT { 1195 pinmux = <0x3033014c 4 0x0 0 0x303303ac>; 1196 }; 1197 /omit-if-no-ref/ iomuxc_sai1_rxc_gpio_io_gpio4_io1: IOMUXC_SAI1_RXC_GPIO_IO_GPIO4_IO1 { 1198 pinmux = <0x3033014c 5 0x0 0 0x303303ac>; 1199 }; 1200 /omit-if-no-ref/ iomuxc_sai1_rxc_pdm_clk_pdm_clk: IOMUXC_SAI1_RXC_PDM_CLK_PDM_CLK { 1201 pinmux = <0x3033014c 3 0x0 0 0x303303ac>; 1202 }; 1203 /omit-if-no-ref/ iomuxc_sai1_rxc_sai_rx_bclk_sai1_rx_bclk: IOMUXC_SAI1_RXC_SAI_RX_BCLK_SAI1_RX_BCLK { 1204 pinmux = <0x3033014c 0 0x0 0 0x303303ac>; 1205 }; 1206 /omit-if-no-ref/ iomuxc_sai1_rxd0_enet_1588_event1_in_enet1_1588_event1_in: IOMUXC_SAI1_RXD0_ENET_1588_EVENT1_IN_ENET1_1588_EVENT1_IN { 1207 pinmux = <0x30330150 4 0x0 0 0x303303b0>; 1208 }; 1209 /omit-if-no-ref/ iomuxc_sai1_rxd0_gpio_io_gpio4_io2: IOMUXC_SAI1_RXD0_GPIO_IO_GPIO4_IO2 { 1210 pinmux = <0x30330150 5 0x0 0 0x303303b0>; 1211 }; 1212 /omit-if-no-ref/ iomuxc_sai1_rxd0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI1_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { 1213 pinmux = <0x30330150 3 0x303304c0 4 0x303303b0>; 1214 }; 1215 /omit-if-no-ref/ iomuxc_sai1_rxd0_sai_rx_data_sai1_rx_data0: IOMUXC_SAI1_RXD0_SAI_RX_DATA_SAI1_RX_DATA0 { 1216 pinmux = <0x30330150 0 0x0 0 0x303303b0>; 1217 }; 1218 /omit-if-no-ref/ iomuxc_sai1_rxd0_sai_tx_data_sai1_tx_data1: IOMUXC_SAI1_RXD0_SAI_TX_DATA_SAI1_TX_DATA1 { 1219 pinmux = <0x30330150 2 0x0 0 0x303303b0>; 1220 }; 1221 /omit-if-no-ref/ iomuxc_sai1_rxd1_enet_1588_event1_out_enet1_1588_event1_out: IOMUXC_SAI1_RXD1_ENET_1588_EVENT1_OUT_ENET1_1588_EVENT1_OUT { 1222 pinmux = <0x30330154 4 0x0 0 0x303303b4>; 1223 }; 1224 /omit-if-no-ref/ iomuxc_sai1_rxd1_gpio_io_gpio4_io3: IOMUXC_SAI1_RXD1_GPIO_IO_GPIO4_IO3 { 1225 pinmux = <0x30330154 5 0x0 0 0x303303b4>; 1226 }; 1227 /omit-if-no-ref/ iomuxc_sai1_rxd1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI1_RXD1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { 1228 pinmux = <0x30330154 3 0x303304c4 4 0x303303b4>; 1229 }; 1230 /omit-if-no-ref/ iomuxc_sai1_rxd1_sai_rx_data_sai1_rx_data1: IOMUXC_SAI1_RXD1_SAI_RX_DATA_SAI1_RX_DATA1 { 1231 pinmux = <0x30330154 0 0x0 0 0x303303b4>; 1232 }; 1233 /omit-if-no-ref/ iomuxc_sai1_rxd2_enet_mdc_enet1_mdc: IOMUXC_SAI1_RXD2_ENET_MDC_ENET1_MDC { 1234 pinmux = <0x30330158 4 0x0 0 0x303303b8>; 1235 }; 1236 /omit-if-no-ref/ iomuxc_sai1_rxd2_gpio_io_gpio4_io4: IOMUXC_SAI1_RXD2_GPIO_IO_GPIO4_IO4 { 1237 pinmux = <0x30330158 5 0x0 0 0x303303b8>; 1238 }; 1239 /omit-if-no-ref/ iomuxc_sai1_rxd2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI1_RXD2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { 1240 pinmux = <0x30330158 3 0x303304c8 4 0x303303b8>; 1241 }; 1242 /omit-if-no-ref/ iomuxc_sai1_rxd2_sai_rx_data_sai1_rx_data2: IOMUXC_SAI1_RXD2_SAI_RX_DATA_SAI1_RX_DATA2 { 1243 pinmux = <0x30330158 0 0x0 0 0x303303b8>; 1244 }; 1245 /omit-if-no-ref/ iomuxc_sai1_rxd3_enet_mdio_enet1_mdio: IOMUXC_SAI1_RXD3_ENET_MDIO_ENET1_MDIO { 1246 pinmux = <0x3033015c 4 0x3033057c 1 0x303303bc>; 1247 }; 1248 /omit-if-no-ref/ iomuxc_sai1_rxd3_gpio_io_gpio4_io5: IOMUXC_SAI1_RXD3_GPIO_IO_GPIO4_IO5 { 1249 pinmux = <0x3033015c 5 0x0 0 0x303303bc>; 1250 }; 1251 /omit-if-no-ref/ iomuxc_sai1_rxd3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI1_RXD3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { 1252 pinmux = <0x3033015c 3 0x303304cc 4 0x303303bc>; 1253 }; 1254 /omit-if-no-ref/ iomuxc_sai1_rxd3_sai_rx_data_sai1_rx_data3: IOMUXC_SAI1_RXD3_SAI_RX_DATA_SAI1_RX_DATA3 { 1255 pinmux = <0x3033015c 0 0x0 0 0x303303bc>; 1256 }; 1257 /omit-if-no-ref/ iomuxc_sai1_rxd4_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC_SAI1_RXD4_ENET_RGMII_RD_ENET1_RGMII_RD0 { 1258 pinmux = <0x30330160 4 0x30330580 1 0x303303c0>; 1259 }; 1260 /omit-if-no-ref/ iomuxc_sai1_rxd4_gpio_io_gpio4_io6: IOMUXC_SAI1_RXD4_GPIO_IO_GPIO4_IO6 { 1261 pinmux = <0x30330160 5 0x0 0 0x303303c0>; 1262 }; 1263 /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_rx_bclk_sai6_rx_bclk: IOMUXC_SAI1_RXD4_SAI_RX_BCLK_SAI6_RX_BCLK { 1264 pinmux = <0x30330160 2 0x30330518 1 0x303303c0>; 1265 }; 1266 /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_rx_data_sai1_rx_data4: IOMUXC_SAI1_RXD4_SAI_RX_DATA_SAI1_RX_DATA4 { 1267 pinmux = <0x30330160 0 0x0 0 0x303303c0>; 1268 }; 1269 /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_tx_bclk_sai6_tx_bclk: IOMUXC_SAI1_RXD4_SAI_TX_BCLK_SAI6_TX_BCLK { 1270 pinmux = <0x30330160 1 0x30330524 1 0x303303c0>; 1271 }; 1272 /omit-if-no-ref/ iomuxc_sai1_rxd5_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC_SAI1_RXD5_ENET_RGMII_RD_ENET1_RGMII_RD1 { 1273 pinmux = <0x30330164 4 0x30330584 1 0x303303c4>; 1274 }; 1275 /omit-if-no-ref/ iomuxc_sai1_rxd5_gpio_io_gpio4_io7: IOMUXC_SAI1_RXD5_GPIO_IO_GPIO4_IO7 { 1276 pinmux = <0x30330164 5 0x0 0 0x303303c4>; 1277 }; 1278 /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_data_sai1_rx_data5: IOMUXC_SAI1_RXD5_SAI_RX_DATA_SAI1_RX_DATA5 { 1279 pinmux = <0x30330164 0 0x0 0 0x303303c4>; 1280 }; 1281 /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_data_sai6_rx_data0: IOMUXC_SAI1_RXD5_SAI_RX_DATA_SAI6_RX_DATA0 { 1282 pinmux = <0x30330164 2 0x3033051c 1 0x303303c4>; 1283 }; 1284 /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_sync_sai1_rx_sync: IOMUXC_SAI1_RXD5_SAI_RX_SYNC_SAI1_RX_SYNC { 1285 pinmux = <0x30330164 3 0x303304d0 1 0x303303c4>; 1286 }; 1287 /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_tx_data_sai6_tx_data0: IOMUXC_SAI1_RXD5_SAI_TX_DATA_SAI6_TX_DATA0 { 1288 pinmux = <0x30330164 1 0x0 0 0x303303c4>; 1289 }; 1290 /omit-if-no-ref/ iomuxc_sai1_rxd6_enet_rgmii_rd_enet1_rgmii_rd2: IOMUXC_SAI1_RXD6_ENET_RGMII_RD_ENET1_RGMII_RD2 { 1291 pinmux = <0x30330168 4 0x0 0 0x303303c8>; 1292 }; 1293 /omit-if-no-ref/ iomuxc_sai1_rxd6_gpio_io_gpio4_io8: IOMUXC_SAI1_RXD6_GPIO_IO_GPIO4_IO8 { 1294 pinmux = <0x30330168 5 0x0 0 0x303303c8>; 1295 }; 1296 /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_rx_data_sai1_rx_data6: IOMUXC_SAI1_RXD6_SAI_RX_DATA_SAI1_RX_DATA6 { 1297 pinmux = <0x30330168 0 0x0 0 0x303303c8>; 1298 }; 1299 /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_rx_sync_sai6_rx_sync: IOMUXC_SAI1_RXD6_SAI_RX_SYNC_SAI6_RX_SYNC { 1300 pinmux = <0x30330168 2 0x30330520 1 0x303303c8>; 1301 }; 1302 /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_tx_sync_sai6_tx_sync: IOMUXC_SAI1_RXD6_SAI_TX_SYNC_SAI6_TX_SYNC { 1303 pinmux = <0x30330168 1 0x30330528 1 0x303303c8>; 1304 }; 1305 /omit-if-no-ref/ iomuxc_sai1_rxd7_enet_rgmii_rd_enet1_rgmii_rd3: IOMUXC_SAI1_RXD7_ENET_RGMII_RD_ENET1_RGMII_RD3 { 1306 pinmux = <0x3033016c 4 0x0 0 0x303303cc>; 1307 }; 1308 /omit-if-no-ref/ iomuxc_sai1_rxd7_gpio_io_gpio4_io9: IOMUXC_SAI1_RXD7_GPIO_IO_GPIO4_IO9 { 1309 pinmux = <0x3033016c 5 0x0 0 0x303303cc>; 1310 }; 1311 /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_mclk_sai6_mclk: IOMUXC_SAI1_RXD7_SAI_MCLK_SAI6_MCLK { 1312 pinmux = <0x3033016c 1 0x30330514 1 0x303303cc>; 1313 }; 1314 /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_rx_data_sai1_rx_data7: IOMUXC_SAI1_RXD7_SAI_RX_DATA_SAI1_RX_DATA7 { 1315 pinmux = <0x3033016c 0 0x0 0 0x303303cc>; 1316 }; 1317 /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_tx_data_sai1_tx_data4: IOMUXC_SAI1_RXD7_SAI_TX_DATA_SAI1_TX_DATA4 { 1318 pinmux = <0x3033016c 3 0x0 0 0x303303cc>; 1319 }; 1320 /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI1_RXD7_SAI_TX_SYNC_SAI1_TX_SYNC { 1321 pinmux = <0x3033016c 2 0x303304d8 3 0x303303cc>; 1322 }; 1323 /omit-if-no-ref/ iomuxc_sai1_rxfs_enet_1588_event0_in_enet1_1588_event0_in: IOMUXC_SAI1_RXFS_ENET_1588_EVENT0_IN_ENET1_1588_EVENT0_IN { 1324 pinmux = <0x30330148 4 0x0 0 0x303303a8>; 1325 }; 1326 /omit-if-no-ref/ iomuxc_sai1_rxfs_gpio_io_gpio4_io0: IOMUXC_SAI1_RXFS_GPIO_IO_GPIO4_IO0 { 1327 pinmux = <0x30330148 5 0x0 0 0x303303a8>; 1328 }; 1329 /omit-if-no-ref/ iomuxc_sai1_rxfs_sai_rx_sync_sai1_rx_sync: IOMUXC_SAI1_RXFS_SAI_RX_SYNC_SAI1_RX_SYNC { 1330 pinmux = <0x30330148 0 0x303304d0 0 0x303303a8>; 1331 }; 1332 /omit-if-no-ref/ iomuxc_sai1_txc_enet_rgmii_rxc_enet1_rgmii_rxc: IOMUXC_SAI1_TXC_ENET_RGMII_RXC_ENET1_RGMII_RXC { 1333 pinmux = <0x30330174 4 0x0 0 0x303303d4>; 1334 }; 1335 /omit-if-no-ref/ iomuxc_sai1_txc_gpio_io_gpio4_io11: IOMUXC_SAI1_TXC_GPIO_IO_GPIO4_IO11 { 1336 pinmux = <0x30330174 5 0x0 0 0x303303d4>; 1337 }; 1338 /omit-if-no-ref/ iomuxc_sai1_txc_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI1_TXC_SAI_TX_BCLK_SAI1_TX_BCLK { 1339 pinmux = <0x30330174 0 0x303304d4 1 0x303303d4>; 1340 }; 1341 /omit-if-no-ref/ iomuxc_sai1_txd0_enet_rgmii_td_enet1_rgmii_td0: IOMUXC_SAI1_TXD0_ENET_RGMII_TD_ENET1_RGMII_TD0 { 1342 pinmux = <0x30330178 4 0x0 0 0x303303d8>; 1343 }; 1344 /omit-if-no-ref/ iomuxc_sai1_txd0_gpio_io_gpio4_io12: IOMUXC_SAI1_TXD0_GPIO_IO_GPIO4_IO12 { 1345 pinmux = <0x30330178 5 0x0 0 0x303303d8>; 1346 }; 1347 /omit-if-no-ref/ iomuxc_sai1_txd0_sai_tx_data_sai1_tx_data0: IOMUXC_SAI1_TXD0_SAI_TX_DATA_SAI1_TX_DATA0 { 1348 pinmux = <0x30330178 0 0x0 0 0x303303d8>; 1349 }; 1350 /omit-if-no-ref/ iomuxc_sai1_txd1_enet_rgmii_td_enet1_rgmii_td1: IOMUXC_SAI1_TXD1_ENET_RGMII_TD_ENET1_RGMII_TD1 { 1351 pinmux = <0x3033017c 4 0x0 0 0x303303dc>; 1352 }; 1353 /omit-if-no-ref/ iomuxc_sai1_txd1_gpio_io_gpio4_io13: IOMUXC_SAI1_TXD1_GPIO_IO_GPIO4_IO13 { 1354 pinmux = <0x3033017c 5 0x0 0 0x303303dc>; 1355 }; 1356 /omit-if-no-ref/ iomuxc_sai1_txd1_sai_tx_data_sai1_tx_data1: IOMUXC_SAI1_TXD1_SAI_TX_DATA_SAI1_TX_DATA1 { 1357 pinmux = <0x3033017c 0 0x0 0 0x303303dc>; 1358 }; 1359 /omit-if-no-ref/ iomuxc_sai1_txd2_enet_rgmii_td_enet1_rgmii_td2: IOMUXC_SAI1_TXD2_ENET_RGMII_TD_ENET1_RGMII_TD2 { 1360 pinmux = <0x30330180 4 0x0 0 0x303303e0>; 1361 }; 1362 /omit-if-no-ref/ iomuxc_sai1_txd2_gpio_io_gpio4_io14: IOMUXC_SAI1_TXD2_GPIO_IO_GPIO4_IO14 { 1363 pinmux = <0x30330180 5 0x0 0 0x303303e0>; 1364 }; 1365 /omit-if-no-ref/ iomuxc_sai1_txd2_sai_tx_data_sai1_tx_data2: IOMUXC_SAI1_TXD2_SAI_TX_DATA_SAI1_TX_DATA2 { 1366 pinmux = <0x30330180 0 0x0 0 0x303303e0>; 1367 }; 1368 /omit-if-no-ref/ iomuxc_sai1_txd3_enet_rgmii_td_enet1_rgmii_td3: IOMUXC_SAI1_TXD3_ENET_RGMII_TD_ENET1_RGMII_TD3 { 1369 pinmux = <0x30330184 4 0x0 0 0x303303e4>; 1370 }; 1371 /omit-if-no-ref/ iomuxc_sai1_txd3_gpio_io_gpio4_io15: IOMUXC_SAI1_TXD3_GPIO_IO_GPIO4_IO15 { 1372 pinmux = <0x30330184 5 0x0 0 0x303303e4>; 1373 }; 1374 /omit-if-no-ref/ iomuxc_sai1_txd3_sai_tx_data_sai1_tx_data3: IOMUXC_SAI1_TXD3_SAI_TX_DATA_SAI1_TX_DATA3 { 1375 pinmux = <0x30330184 0 0x0 0 0x303303e4>; 1376 }; 1377 /omit-if-no-ref/ iomuxc_sai1_txd4_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC_SAI1_TXD4_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { 1378 pinmux = <0x30330188 4 0x0 0 0x303303e8>; 1379 }; 1380 /omit-if-no-ref/ iomuxc_sai1_txd4_gpio_io_gpio4_io16: IOMUXC_SAI1_TXD4_GPIO_IO_GPIO4_IO16 { 1381 pinmux = <0x30330188 5 0x0 0 0x303303e8>; 1382 }; 1383 /omit-if-no-ref/ iomuxc_sai1_txd4_sai_rx_bclk_sai6_rx_bclk: IOMUXC_SAI1_TXD4_SAI_RX_BCLK_SAI6_RX_BCLK { 1384 pinmux = <0x30330188 1 0x30330518 2 0x303303e8>; 1385 }; 1386 /omit-if-no-ref/ iomuxc_sai1_txd4_sai_tx_bclk_sai6_tx_bclk: IOMUXC_SAI1_TXD4_SAI_TX_BCLK_SAI6_TX_BCLK { 1387 pinmux = <0x30330188 2 0x30330524 2 0x303303e8>; 1388 }; 1389 /omit-if-no-ref/ iomuxc_sai1_txd4_sai_tx_data_sai1_tx_data4: IOMUXC_SAI1_TXD4_SAI_TX_DATA_SAI1_TX_DATA4 { 1390 pinmux = <0x30330188 0 0x0 0 0x303303e8>; 1391 }; 1392 /omit-if-no-ref/ iomuxc_sai1_txd5_enet_rgmii_txc_enet1_rgmii_txc: IOMUXC_SAI1_TXD5_ENET_RGMII_TXC_ENET1_RGMII_TXC { 1393 pinmux = <0x3033018c 4 0x0 0 0x303303ec>; 1394 }; 1395 /omit-if-no-ref/ iomuxc_sai1_txd5_gpio_io_gpio4_io17: IOMUXC_SAI1_TXD5_GPIO_IO_GPIO4_IO17 { 1396 pinmux = <0x3033018c 5 0x0 0 0x303303ec>; 1397 }; 1398 /omit-if-no-ref/ iomuxc_sai1_txd5_sai_rx_data_sai6_rx_data0: IOMUXC_SAI1_TXD5_SAI_RX_DATA_SAI6_RX_DATA0 { 1399 pinmux = <0x3033018c 1 0x3033051c 2 0x303303ec>; 1400 }; 1401 /omit-if-no-ref/ iomuxc_sai1_txd5_sai_tx_data_sai1_tx_data5: IOMUXC_SAI1_TXD5_SAI_TX_DATA_SAI1_TX_DATA5 { 1402 pinmux = <0x3033018c 0 0x0 0 0x303303ec>; 1403 }; 1404 /omit-if-no-ref/ iomuxc_sai1_txd5_sai_tx_data_sai6_tx_data0: IOMUXC_SAI1_TXD5_SAI_TX_DATA_SAI6_TX_DATA0 { 1405 pinmux = <0x3033018c 2 0x0 0 0x303303ec>; 1406 }; 1407 /omit-if-no-ref/ iomuxc_sai1_txd6_enet_rx_er_enet1_rx_er: IOMUXC_SAI1_TXD6_ENET_RX_ER_ENET1_RX_ER { 1408 pinmux = <0x30330190 4 0x3033058c 1 0x303303f0>; 1409 }; 1410 /omit-if-no-ref/ iomuxc_sai1_txd6_gpio_io_gpio4_io18: IOMUXC_SAI1_TXD6_GPIO_IO_GPIO4_IO18 { 1411 pinmux = <0x30330190 5 0x0 0 0x303303f0>; 1412 }; 1413 /omit-if-no-ref/ iomuxc_sai1_txd6_sai_rx_sync_sai6_rx_sync: IOMUXC_SAI1_TXD6_SAI_RX_SYNC_SAI6_RX_SYNC { 1414 pinmux = <0x30330190 1 0x30330520 2 0x303303f0>; 1415 }; 1416 /omit-if-no-ref/ iomuxc_sai1_txd6_sai_tx_data_sai1_tx_data6: IOMUXC_SAI1_TXD6_SAI_TX_DATA_SAI1_TX_DATA6 { 1417 pinmux = <0x30330190 0 0x0 0 0x303303f0>; 1418 }; 1419 /omit-if-no-ref/ iomuxc_sai1_txd6_sai_tx_sync_sai6_tx_sync: IOMUXC_SAI1_TXD6_SAI_TX_SYNC_SAI6_TX_SYNC { 1420 pinmux = <0x30330190 2 0x30330528 2 0x303303f0>; 1421 }; 1422 /omit-if-no-ref/ iomuxc_sai1_txd7_enet_tx_er_enet1_tx_er: IOMUXC_SAI1_TXD7_ENET_TX_ER_ENET1_TX_ER { 1423 pinmux = <0x30330194 4 0x0 0 0x303303f4>; 1424 }; 1425 /omit-if-no-ref/ iomuxc_sai1_txd7_gpio_io_gpio4_io19: IOMUXC_SAI1_TXD7_GPIO_IO_GPIO4_IO19 { 1426 pinmux = <0x30330194 5 0x0 0 0x303303f4>; 1427 }; 1428 /omit-if-no-ref/ iomuxc_sai1_txd7_pdm_clk_pdm_clk: IOMUXC_SAI1_TXD7_PDM_CLK_PDM_CLK { 1429 pinmux = <0x30330194 3 0x0 0 0x303303f4>; 1430 }; 1431 /omit-if-no-ref/ iomuxc_sai1_txd7_sai_mclk_sai6_mclk: IOMUXC_SAI1_TXD7_SAI_MCLK_SAI6_MCLK { 1432 pinmux = <0x30330194 1 0x30330514 2 0x303303f4>; 1433 }; 1434 /omit-if-no-ref/ iomuxc_sai1_txd7_sai_tx_data_sai1_tx_data7: IOMUXC_SAI1_TXD7_SAI_TX_DATA_SAI1_TX_DATA7 { 1435 pinmux = <0x30330194 0 0x0 0 0x303303f4>; 1436 }; 1437 /omit-if-no-ref/ iomuxc_sai1_txfs_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC_SAI1_TXFS_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { 1438 pinmux = <0x30330170 4 0x30330588 1 0x303303d0>; 1439 }; 1440 /omit-if-no-ref/ iomuxc_sai1_txfs_gpio_io_gpio4_io10: IOMUXC_SAI1_TXFS_GPIO_IO_GPIO4_IO10 { 1441 pinmux = <0x30330170 5 0x0 0 0x303303d0>; 1442 }; 1443 /omit-if-no-ref/ iomuxc_sai1_txfs_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI1_TXFS_SAI_TX_SYNC_SAI1_TX_SYNC { 1444 pinmux = <0x30330170 0 0x303304d8 4 0x303303d0>; 1445 }; 1446 /omit-if-no-ref/ iomuxc_sai2_mclk_can_rx_can2_rx: IOMUXC_SAI2_MCLK_CAN_RX_CAN2_RX { 1447 pinmux = <0x303301b4 3 0x30330550 1 0x30330414>; 1448 }; 1449 /omit-if-no-ref/ iomuxc_sai2_mclk_enet_qos_1588_event3_aux_in_enet_qos_1588_event3_aux_in: IOMUXC_SAI2_MCLK_ENET_QOS_1588_EVENT3_AUX_IN_ENET_QOS_1588_EVENT3_AUX_IN { 1450 pinmux = <0x303301b4 4 0x0 0 0x30330414>; 1451 }; 1452 /omit-if-no-ref/ iomuxc_sai2_mclk_enet_qos_1588_event3_in_enet_qos_1588_event3_in: IOMUXC_SAI2_MCLK_ENET_QOS_1588_EVENT3_IN_ENET_QOS_1588_EVENT3_IN { 1453 pinmux = <0x303301b4 2 0x0 0 0x30330414>; 1454 }; 1455 /omit-if-no-ref/ iomuxc_sai2_mclk_gpio_io_gpio4_io27: IOMUXC_SAI2_MCLK_GPIO_IO_GPIO4_IO27 { 1456 pinmux = <0x303301b4 5 0x0 0 0x30330414>; 1457 }; 1458 /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai2_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI2_MCLK { 1459 pinmux = <0x303301b4 0 0x0 0 0x30330414>; 1460 }; 1461 /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai3_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI3_MCLK { 1462 pinmux = <0x303301b4 6 0x303304e0 1 0x30330414>; 1463 }; 1464 /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI5_MCLK { 1465 pinmux = <0x303301b4 1 0x303304f0 2 0x30330414>; 1466 }; 1467 /omit-if-no-ref/ iomuxc_sai2_rxc_can_tx_can1_tx: IOMUXC_SAI2_RXC_CAN_TX_CAN1_TX { 1468 pinmux = <0x303301a0 3 0x0 0 0x30330400>; 1469 }; 1470 /omit-if-no-ref/ iomuxc_sai2_rxc_gpio_io_gpio4_io22: IOMUXC_SAI2_RXC_GPIO_IO_GPIO4_IO22 { 1471 pinmux = <0x303301a0 5 0x0 0 0x30330400>; 1472 }; 1473 /omit-if-no-ref/ iomuxc_sai2_rxc_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI2_RXC_PDM_BIT_STREAM_PDM_BIT_STREAM1 { 1474 pinmux = <0x303301a0 6 0x303304c4 5 0x30330400>; 1475 }; 1476 /omit-if-no-ref/ iomuxc_sai2_rxc_sai_rx_bclk_sai2_rx_bclk: IOMUXC_SAI2_RXC_SAI_RX_BCLK_SAI2_RX_BCLK { 1477 pinmux = <0x303301a0 0 0x0 0 0x30330400>; 1478 }; 1479 /omit-if-no-ref/ iomuxc_sai2_rxc_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI2_RXC_SAI_TX_BCLK_SAI5_TX_BCLK { 1480 pinmux = <0x303301a0 1 0x3033050c 2 0x30330400>; 1481 }; 1482 /omit-if-no-ref/ iomuxc_sai2_rxc_uart_rx_uart1_rx: IOMUXC_SAI2_RXC_UART_RX_UART1_RX { 1483 pinmux = <0x303301a0 4 0x303305e8 3 0x30330400>; 1484 }; 1485 /omit-if-no-ref/ iomuxc_sai2_rxc_uart_tx_uart1_rx: IOMUXC_SAI2_RXC_UART_TX_UART1_RX { 1486 pinmux = <0x303301a0 4 0x0 0 0x30330400>; 1487 }; 1488 /omit-if-no-ref/ iomuxc_sai2_rxd0_enet_qos_1588_event2_out_enet_qos_1588_event2_out: IOMUXC_SAI2_RXD0_ENET_QOS_1588_EVENT2_OUT_ENET_QOS_1588_EVENT2_OUT { 1489 pinmux = <0x303301a4 2 0x0 0 0x30330404>; 1490 }; 1491 /omit-if-no-ref/ iomuxc_sai2_rxd0_gpio_io_gpio4_io23: IOMUXC_SAI2_RXD0_GPIO_IO_GPIO4_IO23 { 1492 pinmux = <0x303301a4 5 0x0 0 0x30330404>; 1493 }; 1494 /omit-if-no-ref/ iomuxc_sai2_rxd0_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI2_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM3 { 1495 pinmux = <0x303301a4 6 0x303304cc 5 0x30330404>; 1496 }; 1497 /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_rx_data_sai2_rx_data0: IOMUXC_SAI2_RXD0_SAI_RX_DATA_SAI2_RX_DATA0 { 1498 pinmux = <0x303301a4 0 0x0 0 0x30330404>; 1499 }; 1500 /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_tx_data_sai2_tx_data1: IOMUXC_SAI2_RXD0_SAI_TX_DATA_SAI2_TX_DATA1 { 1501 pinmux = <0x303301a4 3 0x0 0 0x30330404>; 1502 }; 1503 /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_tx_data_sai5_tx_data0: IOMUXC_SAI2_RXD0_SAI_TX_DATA_SAI5_TX_DATA0 { 1504 pinmux = <0x303301a4 1 0x0 0 0x30330404>; 1505 }; 1506 /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_cts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_CTS_B_UART1_RTS_B { 1507 pinmux = <0x303301a4 4 0x0 0 0x30330404>; 1508 }; 1509 /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_rts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_RTS_B_UART1_RTS_B { 1510 pinmux = <0x303301a4 4 0x303305e4 2 0x30330404>; 1511 }; 1512 /omit-if-no-ref/ iomuxc_sai2_rxfs_gpio_io_gpio4_io21: IOMUXC_SAI2_RXFS_GPIO_IO_GPIO4_IO21 { 1513 pinmux = <0x3033019c 5 0x0 0 0x303303fc>; 1514 }; 1515 /omit-if-no-ref/ iomuxc_sai2_rxfs_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI2_RXFS_PDM_BIT_STREAM_PDM_BIT_STREAM2 { 1516 pinmux = <0x3033019c 6 0x303304c8 5 0x303303fc>; 1517 }; 1518 /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_data_sai2_rx_data1: IOMUXC_SAI2_RXFS_SAI_RX_DATA_SAI2_RX_DATA1 { 1519 pinmux = <0x3033019c 3 0x303304dc 0 0x303303fc>; 1520 }; 1521 /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_sync_sai2_rx_sync: IOMUXC_SAI2_RXFS_SAI_RX_SYNC_SAI2_RX_SYNC { 1522 pinmux = <0x3033019c 0 0x0 0 0x303303fc>; 1523 }; 1524 /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_RXFS_SAI_TX_DATA_SAI5_TX_DATA1 { 1525 pinmux = <0x3033019c 2 0x0 0 0x303303fc>; 1526 }; 1527 /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI2_RXFS_SAI_TX_SYNC_SAI5_TX_SYNC { 1528 pinmux = <0x3033019c 1 0x30330510 2 0x303303fc>; 1529 }; 1530 /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_rx_uart1_tx: IOMUXC_SAI2_RXFS_UART_RX_UART1_TX { 1531 pinmux = <0x3033019c 4 0x303305e8 2 0x303303fc>; 1532 }; 1533 /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_tx_uart1_tx: IOMUXC_SAI2_RXFS_UART_TX_UART1_TX { 1534 pinmux = <0x3033019c 4 0x0 0 0x303303fc>; 1535 }; 1536 /omit-if-no-ref/ iomuxc_sai2_txc_can_rx_can1_rx: IOMUXC_SAI2_TXC_CAN_RX_CAN1_RX { 1537 pinmux = <0x303301ac 3 0x3033054c 1 0x3033040c>; 1538 }; 1539 /omit-if-no-ref/ iomuxc_sai2_txc_gpio_io_gpio4_io25: IOMUXC_SAI2_TXC_GPIO_IO_GPIO4_IO25 { 1540 pinmux = <0x303301ac 5 0x0 0 0x3033040c>; 1541 }; 1542 /omit-if-no-ref/ iomuxc_sai2_txc_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI2_TXC_PDM_BIT_STREAM_PDM_BIT_STREAM1 { 1543 pinmux = <0x303301ac 6 0x303304c4 6 0x3033040c>; 1544 }; 1545 /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_bclk_sai2_tx_bclk: IOMUXC_SAI2_TXC_SAI_TX_BCLK_SAI2_TX_BCLK { 1546 pinmux = <0x303301ac 0 0x0 0 0x3033040c>; 1547 }; 1548 /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_data_sai5_tx_data2: IOMUXC_SAI2_TXC_SAI_TX_DATA_SAI5_TX_DATA2 { 1549 pinmux = <0x303301ac 1 0x0 0 0x3033040c>; 1550 }; 1551 /omit-if-no-ref/ iomuxc_sai2_txd0_can_tx_can2_tx: IOMUXC_SAI2_TXD0_CAN_TX_CAN2_TX { 1552 pinmux = <0x303301b0 3 0x0 0 0x30330410>; 1553 }; 1554 /omit-if-no-ref/ iomuxc_sai2_txd0_enet_qos_1588_event2_aux_in_enet_qos_1588_event2_aux_in: IOMUXC_SAI2_TXD0_ENET_QOS_1588_EVENT2_AUX_IN_ENET_QOS_1588_EVENT2_AUX_IN { 1555 pinmux = <0x303301b0 4 0x0 0 0x30330410>; 1556 }; 1557 /omit-if-no-ref/ iomuxc_sai2_txd0_enet_qos_1588_event2_in_enet_qos_1588_event2_in: IOMUXC_SAI2_TXD0_ENET_QOS_1588_EVENT2_IN_ENET_QOS_1588_EVENT2_IN { 1558 pinmux = <0x303301b0 2 0x0 0 0x30330410>; 1559 }; 1560 /omit-if-no-ref/ iomuxc_sai2_txd0_gpio_io_gpio4_io26: IOMUXC_SAI2_TXD0_GPIO_IO_GPIO4_IO26 { 1561 pinmux = <0x303301b0 5 0x0 0 0x30330410>; 1562 }; 1563 /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai2_tx_data0: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI2_TX_DATA0 { 1564 pinmux = <0x303301b0 0 0x0 0 0x30330410>; 1565 }; 1566 /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai5_tx_data3: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI5_TX_DATA3 { 1567 pinmux = <0x303301b0 1 0x0 0 0x30330410>; 1568 }; 1569 /omit-if-no-ref/ iomuxc_sai2_txfs_enet_qos_1588_event3_out_enet_qos_1588_event3_out: IOMUXC_SAI2_TXFS_ENET_QOS_1588_EVENT3_OUT_ENET_QOS_1588_EVENT3_OUT { 1570 pinmux = <0x303301a8 2 0x0 0 0x30330408>; 1571 }; 1572 /omit-if-no-ref/ iomuxc_sai2_txfs_gpio_io_gpio4_io24: IOMUXC_SAI2_TXFS_GPIO_IO_GPIO4_IO24 { 1573 pinmux = <0x303301a8 5 0x0 0 0x30330408>; 1574 }; 1575 /omit-if-no-ref/ iomuxc_sai2_txfs_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI2_TXFS_PDM_BIT_STREAM_PDM_BIT_STREAM2 { 1576 pinmux = <0x303301a8 6 0x303304c8 6 0x30330408>; 1577 }; 1578 /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai2_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI2_TX_DATA1 { 1579 pinmux = <0x303301a8 3 0x0 0 0x30330408>; 1580 }; 1581 /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI5_TX_DATA1 { 1582 pinmux = <0x303301a8 1 0x0 0 0x30330408>; 1583 }; 1584 /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_sync_sai2_tx_sync: IOMUXC_SAI2_TXFS_SAI_TX_SYNC_SAI2_TX_SYNC { 1585 pinmux = <0x303301a8 0 0x0 0 0x30330408>; 1586 }; 1587 /omit-if-no-ref/ iomuxc_sai2_txfs_uart_cts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_CTS_B_UART1_CTS_B { 1588 pinmux = <0x303301a8 4 0x0 0 0x30330408>; 1589 }; 1590 /omit-if-no-ref/ iomuxc_sai2_txfs_uart_rts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_RTS_B_UART1_CTS_B { 1591 pinmux = <0x303301a8 4 0x303305e4 3 0x30330408>; 1592 }; 1593 /omit-if-no-ref/ iomuxc_sai3_mclk_gpio_io_gpio5_io2: IOMUXC_SAI3_MCLK_GPIO_IO_GPIO5_IO2 { 1594 pinmux = <0x303301d0 5 0x0 0 0x30330430>; 1595 }; 1596 /omit-if-no-ref/ iomuxc_sai3_mclk_pwm_out_pwm4_out: IOMUXC_SAI3_MCLK_PWM_OUT_PWM4_OUT { 1597 pinmux = <0x303301d0 1 0x0 0 0x30330430>; 1598 }; 1599 /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai3_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI3_MCLK { 1600 pinmux = <0x303301d0 0 0x303304e0 2 0x30330430>; 1601 }; 1602 /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI5_MCLK { 1603 pinmux = <0x303301d0 2 0x303304f0 3 0x30330430>; 1604 }; 1605 /omit-if-no-ref/ iomuxc_sai3_mclk_spdif_in_spdif1_in: IOMUXC_SAI3_MCLK_SPDIF_IN_SPDIF1_IN { 1606 pinmux = <0x303301d0 6 0x30330544 3 0x30330430>; 1607 }; 1608 /omit-if-no-ref/ iomuxc_sai3_mclk_spdif_out_spdif1_out: IOMUXC_SAI3_MCLK_SPDIF_OUT_SPDIF1_OUT { 1609 pinmux = <0x303301d0 4 0x0 0 0x30330430>; 1610 }; 1611 /omit-if-no-ref/ iomuxc_sai3_rxc_gpio_io_gpio4_io29: IOMUXC_SAI3_RXC_GPIO_IO_GPIO4_IO29 { 1612 pinmux = <0x303301bc 5 0x0 0 0x3033041c>; 1613 }; 1614 /omit-if-no-ref/ iomuxc_sai3_rxc_gpt_clk_gpt1_clk: IOMUXC_SAI3_RXC_GPT_CLK_GPT1_CLK { 1615 pinmux = <0x303301bc 3 0x3033059c 0 0x3033041c>; 1616 }; 1617 /omit-if-no-ref/ iomuxc_sai3_rxc_pdm_clk_pdm_clk: IOMUXC_SAI3_RXC_PDM_CLK_PDM_CLK { 1618 pinmux = <0x303301bc 6 0x0 0 0x3033041c>; 1619 }; 1620 /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai3_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI3_RX_BCLK { 1621 pinmux = <0x303301bc 0 0x0 0 0x3033041c>; 1622 }; 1623 /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { 1624 pinmux = <0x303301bc 2 0x303304f4 2 0x3033041c>; 1625 }; 1626 /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_data_sai2_rx_data2: IOMUXC_SAI3_RXC_SAI_RX_DATA_SAI2_RX_DATA2 { 1627 pinmux = <0x303301bc 1 0x0 0 0x3033041c>; 1628 }; 1629 /omit-if-no-ref/ iomuxc_sai3_rxc_uart_cts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_CTS_B_UART2_CTS_B { 1630 pinmux = <0x303301bc 4 0x0 0 0x3033041c>; 1631 }; 1632 /omit-if-no-ref/ iomuxc_sai3_rxc_uart_rts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_RTS_B_UART2_CTS_B { 1633 pinmux = <0x303301bc 4 0x303305ec 2 0x3033041c>; 1634 }; 1635 /omit-if-no-ref/ iomuxc_sai3_rxd_gpio_io_gpio4_io30: IOMUXC_SAI3_RXD_GPIO_IO_GPIO4_IO30 { 1636 pinmux = <0x303301c0 5 0x0 0 0x30330420>; 1637 }; 1638 /omit-if-no-ref/ iomuxc_sai3_rxd_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI3_RXD_PDM_BIT_STREAM_PDM_BIT_STREAM1 { 1639 pinmux = <0x303301c0 6 0x303304c4 7 0x30330420>; 1640 }; 1641 /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai2_rx_data3: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI2_RX_DATA3 { 1642 pinmux = <0x303301c0 1 0x0 0 0x30330420>; 1643 }; 1644 /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai3_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI3_RX_DATA0 { 1645 pinmux = <0x303301c0 0 0x303304e4 1 0x30330420>; 1646 }; 1647 /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai5_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI5_RX_DATA0 { 1648 pinmux = <0x303301c0 2 0x303304f8 2 0x30330420>; 1649 }; 1650 /omit-if-no-ref/ iomuxc_sai3_rxd_uart_cts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_CTS_B_UART2_RTS_B { 1651 pinmux = <0x303301c0 4 0x0 0 0x30330420>; 1652 }; 1653 /omit-if-no-ref/ iomuxc_sai3_rxd_uart_rts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_RTS_B_UART2_RTS_B { 1654 pinmux = <0x303301c0 4 0x303305ec 3 0x30330420>; 1655 }; 1656 /omit-if-no-ref/ iomuxc_sai3_rxfs_gpio_io_gpio4_io28: IOMUXC_SAI3_RXFS_GPIO_IO_GPIO4_IO28 { 1657 pinmux = <0x303301b8 5 0x0 0 0x30330418>; 1658 }; 1659 /omit-if-no-ref/ iomuxc_sai3_rxfs_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI3_RXFS_PDM_BIT_STREAM_PDM_BIT_STREAM0 { 1660 pinmux = <0x303301b8 6 0x303304c0 5 0x30330418>; 1661 }; 1662 /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_data_sai2_rx_data1: IOMUXC_SAI3_RXFS_SAI_RX_DATA_SAI2_RX_DATA1 { 1663 pinmux = <0x303301b8 1 0x303304dc 1 0x30330418>; 1664 }; 1665 /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_data_sai3_rx_data1: IOMUXC_SAI3_RXFS_SAI_RX_DATA_SAI3_RX_DATA1 { 1666 pinmux = <0x303301b8 3 0x0 0 0x30330418>; 1667 }; 1668 /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai3_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI3_RX_SYNC { 1669 pinmux = <0x303301b8 0 0x0 0 0x30330418>; 1670 }; 1671 /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { 1672 pinmux = <0x303301b8 2 0x30330508 2 0x30330418>; 1673 }; 1674 /omit-if-no-ref/ iomuxc_sai3_rxfs_spdif_in_spdif1_in: IOMUXC_SAI3_RXFS_SPDIF_IN_SPDIF1_IN { 1675 pinmux = <0x303301b8 4 0x30330544 2 0x30330418>; 1676 }; 1677 /omit-if-no-ref/ iomuxc_sai3_txc_gpio_io_gpio5_io0: IOMUXC_SAI3_TXC_GPIO_IO_GPIO5_IO0 { 1678 pinmux = <0x303301c8 5 0x0 0 0x30330428>; 1679 }; 1680 /omit-if-no-ref/ iomuxc_sai3_txc_gpt_capture_gpt1_capture1: IOMUXC_SAI3_TXC_GPT_CAPTURE_GPT1_CAPTURE1 { 1681 pinmux = <0x303301c8 3 0x30330594 0 0x30330428>; 1682 }; 1683 /omit-if-no-ref/ iomuxc_sai3_txc_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI3_TXC_PDM_BIT_STREAM_PDM_BIT_STREAM2 { 1684 pinmux = <0x303301c8 6 0x303304c8 7 0x30330428>; 1685 }; 1686 /omit-if-no-ref/ iomuxc_sai3_txc_sai_rx_data_sai5_rx_data2: IOMUXC_SAI3_TXC_SAI_RX_DATA_SAI5_RX_DATA2 { 1687 pinmux = <0x303301c8 2 0x30330500 2 0x30330428>; 1688 }; 1689 /omit-if-no-ref/ iomuxc_sai3_txc_sai_tx_bclk_sai3_tx_bclk: IOMUXC_SAI3_TXC_SAI_TX_BCLK_SAI3_TX_BCLK { 1690 pinmux = <0x303301c8 0 0x303304e8 1 0x30330428>; 1691 }; 1692 /omit-if-no-ref/ iomuxc_sai3_txc_sai_tx_data_sai2_tx_data2: IOMUXC_SAI3_TXC_SAI_TX_DATA_SAI2_TX_DATA2 { 1693 pinmux = <0x303301c8 1 0x0 0 0x30330428>; 1694 }; 1695 /omit-if-no-ref/ iomuxc_sai3_txc_uart_rx_uart2_tx: IOMUXC_SAI3_TXC_UART_RX_UART2_TX { 1696 pinmux = <0x303301c8 4 0x303305f0 5 0x30330428>; 1697 }; 1698 /omit-if-no-ref/ iomuxc_sai3_txc_uart_tx_uart2_tx: IOMUXC_SAI3_TXC_UART_TX_UART2_TX { 1699 pinmux = <0x303301c8 4 0x0 0 0x30330428>; 1700 }; 1701 /omit-if-no-ref/ iomuxc_sai3_txd_gpio_io_gpio5_io1: IOMUXC_SAI3_TXD_GPIO_IO_GPIO5_IO1 { 1702 pinmux = <0x303301cc 5 0x0 0 0x3033042c>; 1703 }; 1704 /omit-if-no-ref/ iomuxc_sai3_txd_gpt_capture_gpt1_capture2: IOMUXC_SAI3_TXD_GPT_CAPTURE_GPT1_CAPTURE2 { 1705 pinmux = <0x303301cc 3 0x30330598 0 0x3033042c>; 1706 }; 1707 /omit-if-no-ref/ iomuxc_sai3_txd_sai_rx_data_sai5_rx_data3: IOMUXC_SAI3_TXD_SAI_RX_DATA_SAI5_RX_DATA3 { 1708 pinmux = <0x303301cc 2 0x30330504 2 0x3033042c>; 1709 }; 1710 /omit-if-no-ref/ iomuxc_sai3_txd_sai_tx_data_sai2_tx_data3: IOMUXC_SAI3_TXD_SAI_TX_DATA_SAI2_TX_DATA3 { 1711 pinmux = <0x303301cc 1 0x0 0 0x3033042c>; 1712 }; 1713 /omit-if-no-ref/ iomuxc_sai3_txd_sai_tx_data_sai3_tx_data0: IOMUXC_SAI3_TXD_SAI_TX_DATA_SAI3_TX_DATA0 { 1714 pinmux = <0x303301cc 0 0x0 0 0x3033042c>; 1715 }; 1716 /omit-if-no-ref/ iomuxc_sai3_txd_spdif_ext_clk_spdif1_ext_clk: IOMUXC_SAI3_TXD_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { 1717 pinmux = <0x303301cc 4 0x30330548 0 0x3033042c>; 1718 }; 1719 /omit-if-no-ref/ iomuxc_sai3_txfs_gpio_io_gpio4_io31: IOMUXC_SAI3_TXFS_GPIO_IO_GPIO4_IO31 { 1720 pinmux = <0x303301c4 5 0x0 0 0x30330424>; 1721 }; 1722 /omit-if-no-ref/ iomuxc_sai3_txfs_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI3_TXFS_PDM_BIT_STREAM_PDM_BIT_STREAM3 { 1723 pinmux = <0x303301c4 6 0x303304cc 6 0x30330424>; 1724 }; 1725 /omit-if-no-ref/ iomuxc_sai3_txfs_sai_rx_data_sai5_rx_data1: IOMUXC_SAI3_TXFS_SAI_RX_DATA_SAI5_RX_DATA1 { 1726 pinmux = <0x303301c4 2 0x303304fc 2 0x30330424>; 1727 }; 1728 /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_data_sai2_tx_data1: IOMUXC_SAI3_TXFS_SAI_TX_DATA_SAI2_TX_DATA1 { 1729 pinmux = <0x303301c4 1 0x0 0 0x30330424>; 1730 }; 1731 /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_data_sai3_tx_data1: IOMUXC_SAI3_TXFS_SAI_TX_DATA_SAI3_TX_DATA1 { 1732 pinmux = <0x303301c4 3 0x0 0 0x30330424>; 1733 }; 1734 /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_sync_sai3_tx_sync: IOMUXC_SAI3_TXFS_SAI_TX_SYNC_SAI3_TX_SYNC { 1735 pinmux = <0x303301c4 0 0x303304ec 1 0x30330424>; 1736 }; 1737 /omit-if-no-ref/ iomuxc_sai3_txfs_uart_rx_uart2_rx: IOMUXC_SAI3_TXFS_UART_RX_UART2_RX { 1738 pinmux = <0x303301c4 4 0x303305f0 4 0x30330424>; 1739 }; 1740 /omit-if-no-ref/ iomuxc_sai3_txfs_uart_tx_uart2_rx: IOMUXC_SAI3_TXFS_UART_TX_UART2_RX { 1741 pinmux = <0x303301c4 4 0x0 0 0x30330424>; 1742 }; 1743 /omit-if-no-ref/ iomuxc_sai5_mclk_can_rx_can2_rx: IOMUXC_SAI5_MCLK_CAN_RX_CAN2_RX { 1744 pinmux = <0x30330144 6 0x30330550 0 0x303303a4>; 1745 }; 1746 /omit-if-no-ref/ iomuxc_sai5_mclk_gpio_io_gpio3_io25: IOMUXC_SAI5_MCLK_GPIO_IO_GPIO3_IO25 { 1747 pinmux = <0x30330144 5 0x0 0 0x303303a4>; 1748 }; 1749 /omit-if-no-ref/ iomuxc_sai5_mclk_i2c_sda_i2c5_sda: IOMUXC_SAI5_MCLK_I2C_SDA_I2C5_SDA { 1750 pinmux = <0x30330144 3 0x303305c8 1 0x303303a4>; 1751 }; 1752 /omit-if-no-ref/ iomuxc_sai5_mclk_pwm_out_pwm1_out: IOMUXC_SAI5_MCLK_PWM_OUT_PWM1_OUT { 1753 pinmux = <0x30330144 2 0x0 0 0x303303a4>; 1754 }; 1755 /omit-if-no-ref/ iomuxc_sai5_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI5_MCLK_SAI_MCLK_SAI5_MCLK { 1756 pinmux = <0x30330144 0 0x303304f0 0 0x303303a4>; 1757 }; 1758 /omit-if-no-ref/ iomuxc_sai5_mclk_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI5_MCLK_SAI_TX_BCLK_SAI1_TX_BCLK { 1759 pinmux = <0x30330144 1 0x303304d4 0 0x303303a4>; 1760 }; 1761 /omit-if-no-ref/ iomuxc_sai5_rxc_gpio_io_gpio3_io20: IOMUXC_SAI5_RXC_GPIO_IO_GPIO3_IO20 { 1762 pinmux = <0x30330130 5 0x0 0 0x30330390>; 1763 }; 1764 /omit-if-no-ref/ iomuxc_sai5_rxc_i2c_sda_i2c6_sda: IOMUXC_SAI5_RXC_I2C_SDA_I2C6_SDA { 1765 pinmux = <0x30330130 3 0x303305d0 1 0x30330390>; 1766 }; 1767 /omit-if-no-ref/ iomuxc_sai5_rxc_pdm_clk_pdm_clk: IOMUXC_SAI5_RXC_PDM_CLK_PDM_CLK { 1768 pinmux = <0x30330130 4 0x0 0 0x30330390>; 1769 }; 1770 /omit-if-no-ref/ iomuxc_sai5_rxc_pwm_out_pwm3_out: IOMUXC_SAI5_RXC_PWM_OUT_PWM3_OUT { 1771 pinmux = <0x30330130 2 0x0 0 0x30330390>; 1772 }; 1773 /omit-if-no-ref/ iomuxc_sai5_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI5_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { 1774 pinmux = <0x30330130 0 0x303304f4 0 0x30330390>; 1775 }; 1776 /omit-if-no-ref/ iomuxc_sai5_rxc_sai_tx_data_sai1_tx_data1: IOMUXC_SAI5_RXC_SAI_TX_DATA_SAI1_TX_DATA1 { 1777 pinmux = <0x30330130 1 0x0 0 0x30330390>; 1778 }; 1779 /omit-if-no-ref/ iomuxc_sai5_rxd0_gpio_io_gpio3_io21: IOMUXC_SAI5_RXD0_GPIO_IO_GPIO3_IO21 { 1780 pinmux = <0x30330134 5 0x0 0 0x30330394>; 1781 }; 1782 /omit-if-no-ref/ iomuxc_sai5_rxd0_i2c_scl_i2c5_scl: IOMUXC_SAI5_RXD0_I2C_SCL_I2C5_SCL { 1783 pinmux = <0x30330134 3 0x303305c4 1 0x30330394>; 1784 }; 1785 /omit-if-no-ref/ iomuxc_sai5_rxd0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI5_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { 1786 pinmux = <0x30330134 4 0x303304c0 3 0x30330394>; 1787 }; 1788 /omit-if-no-ref/ iomuxc_sai5_rxd0_pwm_out_pwm2_out: IOMUXC_SAI5_RXD0_PWM_OUT_PWM2_OUT { 1789 pinmux = <0x30330134 2 0x0 0 0x30330394>; 1790 }; 1791 /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_rx_data_sai5_rx_data0: IOMUXC_SAI5_RXD0_SAI_RX_DATA_SAI5_RX_DATA0 { 1792 pinmux = <0x30330134 0 0x303304f8 0 0x30330394>; 1793 }; 1794 /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_tx_data_sai1_tx_data2: IOMUXC_SAI5_RXD0_SAI_TX_DATA_SAI1_TX_DATA2 { 1795 pinmux = <0x30330134 1 0x0 0 0x30330394>; 1796 }; 1797 /omit-if-no-ref/ iomuxc_sai5_rxd1_can_tx_can1_tx: IOMUXC_SAI5_RXD1_CAN_TX_CAN1_TX { 1798 pinmux = <0x30330138 6 0x0 0 0x30330398>; 1799 }; 1800 /omit-if-no-ref/ iomuxc_sai5_rxd1_gpio_io_gpio3_io22: IOMUXC_SAI5_RXD1_GPIO_IO_GPIO3_IO22 { 1801 pinmux = <0x30330138 5 0x0 0 0x30330398>; 1802 }; 1803 /omit-if-no-ref/ iomuxc_sai5_rxd1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI5_RXD1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { 1804 pinmux = <0x30330138 4 0x303304c4 3 0x30330398>; 1805 }; 1806 /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_rx_data_sai5_rx_data1: IOMUXC_SAI5_RXD1_SAI_RX_DATA_SAI5_RX_DATA1 { 1807 pinmux = <0x30330138 0 0x303304fc 0 0x30330398>; 1808 }; 1809 /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_data_sai1_tx_data3: IOMUXC_SAI5_RXD1_SAI_TX_DATA_SAI1_TX_DATA3 { 1810 pinmux = <0x30330138 1 0x0 0 0x30330398>; 1811 }; 1812 /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI1_TX_SYNC { 1813 pinmux = <0x30330138 2 0x303304d8 0 0x30330398>; 1814 }; 1815 /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI5_TX_SYNC { 1816 pinmux = <0x30330138 3 0x30330510 0 0x30330398>; 1817 }; 1818 /omit-if-no-ref/ iomuxc_sai5_rxd2_can_rx_can1_rx: IOMUXC_SAI5_RXD2_CAN_RX_CAN1_RX { 1819 pinmux = <0x3033013c 6 0x3033054c 0 0x3033039c>; 1820 }; 1821 /omit-if-no-ref/ iomuxc_sai5_rxd2_gpio_io_gpio3_io23: IOMUXC_SAI5_RXD2_GPIO_IO_GPIO3_IO23 { 1822 pinmux = <0x3033013c 5 0x0 0 0x3033039c>; 1823 }; 1824 /omit-if-no-ref/ iomuxc_sai5_rxd2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI5_RXD2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { 1825 pinmux = <0x3033013c 4 0x303304c8 3 0x3033039c>; 1826 }; 1827 /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_rx_data_sai5_rx_data2: IOMUXC_SAI5_RXD2_SAI_RX_DATA_SAI5_RX_DATA2 { 1828 pinmux = <0x3033013c 0 0x30330500 0 0x3033039c>; 1829 }; 1830 /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI5_RXD2_SAI_TX_BCLK_SAI5_TX_BCLK { 1831 pinmux = <0x3033013c 3 0x3033050c 0 0x3033039c>; 1832 }; 1833 /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_data_sai1_tx_data4: IOMUXC_SAI5_RXD2_SAI_TX_DATA_SAI1_TX_DATA4 { 1834 pinmux = <0x3033013c 1 0x0 0 0x3033039c>; 1835 }; 1836 /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD2_SAI_TX_SYNC_SAI1_TX_SYNC { 1837 pinmux = <0x3033013c 2 0x303304d8 1 0x3033039c>; 1838 }; 1839 /omit-if-no-ref/ iomuxc_sai5_rxd3_can_tx_can2_tx: IOMUXC_SAI5_RXD3_CAN_TX_CAN2_TX { 1840 pinmux = <0x30330140 6 0x0 0 0x303303a0>; 1841 }; 1842 /omit-if-no-ref/ iomuxc_sai5_rxd3_gpio_io_gpio3_io24: IOMUXC_SAI5_RXD3_GPIO_IO_GPIO3_IO24 { 1843 pinmux = <0x30330140 5 0x0 0 0x303303a0>; 1844 }; 1845 /omit-if-no-ref/ iomuxc_sai5_rxd3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI5_RXD3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { 1846 pinmux = <0x30330140 4 0x303304cc 3 0x303303a0>; 1847 }; 1848 /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_rx_data_sai5_rx_data3: IOMUXC_SAI5_RXD3_SAI_RX_DATA_SAI5_RX_DATA3 { 1849 pinmux = <0x30330140 0 0x30330504 0 0x303303a0>; 1850 }; 1851 /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai1_tx_data5: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI1_TX_DATA5 { 1852 pinmux = <0x30330140 1 0x0 0 0x303303a0>; 1853 }; 1854 /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai5_tx_data0: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI5_TX_DATA0 { 1855 pinmux = <0x30330140 3 0x0 0 0x303303a0>; 1856 }; 1857 /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD3_SAI_TX_SYNC_SAI1_TX_SYNC { 1858 pinmux = <0x30330140 2 0x303304d8 2 0x303303a0>; 1859 }; 1860 /omit-if-no-ref/ iomuxc_sai5_rxfs_gpio_io_gpio3_io19: IOMUXC_SAI5_RXFS_GPIO_IO_GPIO3_IO19 { 1861 pinmux = <0x3033012c 5 0x0 0 0x3033038c>; 1862 }; 1863 /omit-if-no-ref/ iomuxc_sai5_rxfs_i2c_scl_i2c6_scl: IOMUXC_SAI5_RXFS_I2C_SCL_I2C6_SCL { 1864 pinmux = <0x3033012c 3 0x303305cc 1 0x3033038c>; 1865 }; 1866 /omit-if-no-ref/ iomuxc_sai5_rxfs_pwm_out_pwm4_out: IOMUXC_SAI5_RXFS_PWM_OUT_PWM4_OUT { 1867 pinmux = <0x3033012c 2 0x0 0 0x3033038c>; 1868 }; 1869 /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI5_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { 1870 pinmux = <0x3033012c 0 0x30330508 0 0x3033038c>; 1871 }; 1872 /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_tx_data_sai1_tx_data0: IOMUXC_SAI5_RXFS_SAI_TX_DATA_SAI1_TX_DATA0 { 1873 pinmux = <0x3033012c 1 0x0 0 0x3033038c>; 1874 }; 1875 /omit-if-no-ref/ iomuxc_sd1_clk_enet_mdc_enet1_mdc: IOMUXC_SD1_CLK_ENET_MDC_ENET1_MDC { 1876 pinmux = <0x3033008c 1 0x0 0 0x303302ec>; 1877 }; 1878 /omit-if-no-ref/ iomuxc_sd1_clk_gpio_io_gpio2_io0: IOMUXC_SD1_CLK_GPIO_IO_GPIO2_IO0 { 1879 pinmux = <0x3033008c 5 0x0 0 0x303302ec>; 1880 }; 1881 /omit-if-no-ref/ iomuxc_sd1_clk_i2c_scl_i2c5_scl: IOMUXC_SD1_CLK_I2C_SCL_I2C5_SCL { 1882 pinmux = <0x3033008c 3 0x303305c4 0 0x303302ec>; 1883 }; 1884 /omit-if-no-ref/ iomuxc_sd1_clk_uart_rx_uart1_tx: IOMUXC_SD1_CLK_UART_RX_UART1_TX { 1885 pinmux = <0x3033008c 4 0x303305e8 0 0x303302ec>; 1886 }; 1887 /omit-if-no-ref/ iomuxc_sd1_clk_uart_tx_uart1_tx: IOMUXC_SD1_CLK_UART_TX_UART1_TX { 1888 pinmux = <0x3033008c 4 0x0 0 0x303302ec>; 1889 }; 1890 /omit-if-no-ref/ iomuxc_sd1_clk_usdhc_clk_usdhc1_clk: IOMUXC_SD1_CLK_USDHC_CLK_USDHC1_CLK { 1891 pinmux = <0x3033008c 0 0x0 0 0x303302ec>; 1892 }; 1893 /omit-if-no-ref/ iomuxc_sd1_cmd_enet_mdio_enet1_mdio: IOMUXC_SD1_CMD_ENET_MDIO_ENET1_MDIO { 1894 pinmux = <0x30330090 1 0x3033057c 0 0x303302f0>; 1895 }; 1896 /omit-if-no-ref/ iomuxc_sd1_cmd_gpio_io_gpio2_io1: IOMUXC_SD1_CMD_GPIO_IO_GPIO2_IO1 { 1897 pinmux = <0x30330090 5 0x0 0 0x303302f0>; 1898 }; 1899 /omit-if-no-ref/ iomuxc_sd1_cmd_i2c_sda_i2c5_sda: IOMUXC_SD1_CMD_I2C_SDA_I2C5_SDA { 1900 pinmux = <0x30330090 3 0x303305c8 0 0x303302f0>; 1901 }; 1902 /omit-if-no-ref/ iomuxc_sd1_cmd_uart_rx_uart1_rx: IOMUXC_SD1_CMD_UART_RX_UART1_RX { 1903 pinmux = <0x30330090 4 0x303305e8 1 0x303302f0>; 1904 }; 1905 /omit-if-no-ref/ iomuxc_sd1_cmd_uart_tx_uart1_rx: IOMUXC_SD1_CMD_UART_TX_UART1_RX { 1906 pinmux = <0x30330090 4 0x0 0 0x303302f0>; 1907 }; 1908 /omit-if-no-ref/ iomuxc_sd1_cmd_usdhc_cmd_usdhc1_cmd: IOMUXC_SD1_CMD_USDHC_CMD_USDHC1_CMD { 1909 pinmux = <0x30330090 0 0x0 0 0x303302f0>; 1910 }; 1911 /omit-if-no-ref/ iomuxc_sd1_data0_enet_rgmii_td_enet1_rgmii_td1: IOMUXC_SD1_DATA0_ENET_RGMII_TD_ENET1_RGMII_TD1 { 1912 pinmux = <0x30330094 1 0x0 0 0x303302f4>; 1913 }; 1914 /omit-if-no-ref/ iomuxc_sd1_data0_gpio_io_gpio2_io2: IOMUXC_SD1_DATA0_GPIO_IO_GPIO2_IO2 { 1915 pinmux = <0x30330094 5 0x0 0 0x303302f4>; 1916 }; 1917 /omit-if-no-ref/ iomuxc_sd1_data0_i2c_scl_i2c6_scl: IOMUXC_SD1_DATA0_I2C_SCL_I2C6_SCL { 1918 pinmux = <0x30330094 3 0x303305cc 0 0x303302f4>; 1919 }; 1920 /omit-if-no-ref/ iomuxc_sd1_data0_uart_cts_b_uart1_rts_b: IOMUXC_SD1_DATA0_UART_CTS_B_UART1_RTS_B { 1921 pinmux = <0x30330094 4 0x0 0 0x303302f4>; 1922 }; 1923 /omit-if-no-ref/ iomuxc_sd1_data0_uart_rts_b_uart1_rts_b: IOMUXC_SD1_DATA0_UART_RTS_B_UART1_RTS_B { 1924 pinmux = <0x30330094 4 0x303305e4 0 0x303302f4>; 1925 }; 1926 /omit-if-no-ref/ iomuxc_sd1_data0_usdhc_data_usdhc1_data0: IOMUXC_SD1_DATA0_USDHC_DATA_USDHC1_DATA0 { 1927 pinmux = <0x30330094 0 0x0 0 0x303302f4>; 1928 }; 1929 /omit-if-no-ref/ iomuxc_sd1_data1_enet_rgmii_td_enet1_rgmii_td0: IOMUXC_SD1_DATA1_ENET_RGMII_TD_ENET1_RGMII_TD0 { 1930 pinmux = <0x30330098 1 0x0 0 0x303302f8>; 1931 }; 1932 /omit-if-no-ref/ iomuxc_sd1_data1_gpio_io_gpio2_io3: IOMUXC_SD1_DATA1_GPIO_IO_GPIO2_IO3 { 1933 pinmux = <0x30330098 5 0x0 0 0x303302f8>; 1934 }; 1935 /omit-if-no-ref/ iomuxc_sd1_data1_i2c_sda_i2c6_sda: IOMUXC_SD1_DATA1_I2C_SDA_I2C6_SDA { 1936 pinmux = <0x30330098 3 0x303305d0 0 0x303302f8>; 1937 }; 1938 /omit-if-no-ref/ iomuxc_sd1_data1_uart_cts_b_uart1_cts_b: IOMUXC_SD1_DATA1_UART_CTS_B_UART1_CTS_B { 1939 pinmux = <0x30330098 4 0x0 0 0x303302f8>; 1940 }; 1941 /omit-if-no-ref/ iomuxc_sd1_data1_uart_rts_b_uart1_cts_b: IOMUXC_SD1_DATA1_UART_RTS_B_UART1_CTS_B { 1942 pinmux = <0x30330098 4 0x303305e4 1 0x303302f8>; 1943 }; 1944 /omit-if-no-ref/ iomuxc_sd1_data1_usdhc_data_usdhc1_data1: IOMUXC_SD1_DATA1_USDHC_DATA_USDHC1_DATA1 { 1945 pinmux = <0x30330098 0 0x0 0 0x303302f8>; 1946 }; 1947 /omit-if-no-ref/ iomuxc_sd1_data2_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC_SD1_DATA2_ENET_RGMII_RD_ENET1_RGMII_RD0 { 1948 pinmux = <0x3033009c 1 0x30330580 0 0x303302fc>; 1949 }; 1950 /omit-if-no-ref/ iomuxc_sd1_data2_gpio_io_gpio2_io4: IOMUXC_SD1_DATA2_GPIO_IO_GPIO2_IO4 { 1951 pinmux = <0x3033009c 5 0x0 0 0x303302fc>; 1952 }; 1953 /omit-if-no-ref/ iomuxc_sd1_data2_i2c_scl_i2c4_scl: IOMUXC_SD1_DATA2_I2C_SCL_I2C4_SCL { 1954 pinmux = <0x3033009c 3 0x303305bc 0 0x303302fc>; 1955 }; 1956 /omit-if-no-ref/ iomuxc_sd1_data2_uart_rx_uart2_tx: IOMUXC_SD1_DATA2_UART_RX_UART2_TX { 1957 pinmux = <0x3033009c 4 0x303305f0 0 0x303302fc>; 1958 }; 1959 /omit-if-no-ref/ iomuxc_sd1_data2_uart_tx_uart2_tx: IOMUXC_SD1_DATA2_UART_TX_UART2_TX { 1960 pinmux = <0x3033009c 4 0x0 0 0x303302fc>; 1961 }; 1962 /omit-if-no-ref/ iomuxc_sd1_data2_usdhc_data_usdhc1_data2: IOMUXC_SD1_DATA2_USDHC_DATA_USDHC1_DATA2 { 1963 pinmux = <0x3033009c 0 0x0 0 0x303302fc>; 1964 }; 1965 /omit-if-no-ref/ iomuxc_sd1_data3_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC_SD1_DATA3_ENET_RGMII_RD_ENET1_RGMII_RD1 { 1966 pinmux = <0x303300a0 1 0x30330584 0 0x30330300>; 1967 }; 1968 /omit-if-no-ref/ iomuxc_sd1_data3_gpio_io_gpio2_io5: IOMUXC_SD1_DATA3_GPIO_IO_GPIO2_IO5 { 1969 pinmux = <0x303300a0 5 0x0 0 0x30330300>; 1970 }; 1971 /omit-if-no-ref/ iomuxc_sd1_data3_i2c_sda_i2c4_sda: IOMUXC_SD1_DATA3_I2C_SDA_I2C4_SDA { 1972 pinmux = <0x303300a0 3 0x303305c0 0 0x30330300>; 1973 }; 1974 /omit-if-no-ref/ iomuxc_sd1_data3_uart_rx_uart2_rx: IOMUXC_SD1_DATA3_UART_RX_UART2_RX { 1975 pinmux = <0x303300a0 4 0x303305f0 1 0x30330300>; 1976 }; 1977 /omit-if-no-ref/ iomuxc_sd1_data3_uart_tx_uart2_rx: IOMUXC_SD1_DATA3_UART_TX_UART2_RX { 1978 pinmux = <0x303300a0 4 0x0 0 0x30330300>; 1979 }; 1980 /omit-if-no-ref/ iomuxc_sd1_data3_usdhc_data_usdhc1_data3: IOMUXC_SD1_DATA3_USDHC_DATA_USDHC1_DATA3 { 1981 pinmux = <0x303300a0 0 0x0 0 0x30330300>; 1982 }; 1983 /omit-if-no-ref/ iomuxc_sd1_data4_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC_SD1_DATA4_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { 1984 pinmux = <0x303300a4 1 0x0 0 0x30330304>; 1985 }; 1986 /omit-if-no-ref/ iomuxc_sd1_data4_gpio_io_gpio2_io6: IOMUXC_SD1_DATA4_GPIO_IO_GPIO2_IO6 { 1987 pinmux = <0x303300a4 5 0x0 0 0x30330304>; 1988 }; 1989 /omit-if-no-ref/ iomuxc_sd1_data4_i2c_scl_i2c1_scl: IOMUXC_SD1_DATA4_I2C_SCL_I2C1_SCL { 1990 pinmux = <0x303300a4 3 0x303305a4 0 0x30330304>; 1991 }; 1992 /omit-if-no-ref/ iomuxc_sd1_data4_uart_cts_b_uart2_rts_b: IOMUXC_SD1_DATA4_UART_CTS_B_UART2_RTS_B { 1993 pinmux = <0x303300a4 4 0x0 0 0x30330304>; 1994 }; 1995 /omit-if-no-ref/ iomuxc_sd1_data4_uart_rts_b_uart2_rts_b: IOMUXC_SD1_DATA4_UART_RTS_B_UART2_RTS_B { 1996 pinmux = <0x303300a4 4 0x303305ec 0 0x30330304>; 1997 }; 1998 /omit-if-no-ref/ iomuxc_sd1_data4_usdhc_data_usdhc1_data4: IOMUXC_SD1_DATA4_USDHC_DATA_USDHC1_DATA4 { 1999 pinmux = <0x303300a4 0 0x0 0 0x30330304>; 2000 }; 2001 /omit-if-no-ref/ iomuxc_sd1_data5_enet_tx_er_enet1_tx_er: IOMUXC_SD1_DATA5_ENET_TX_ER_ENET1_TX_ER { 2002 pinmux = <0x303300a8 1 0x0 0 0x30330308>; 2003 }; 2004 /omit-if-no-ref/ iomuxc_sd1_data5_gpio_io_gpio2_io7: IOMUXC_SD1_DATA5_GPIO_IO_GPIO2_IO7 { 2005 pinmux = <0x303300a8 5 0x0 0 0x30330308>; 2006 }; 2007 /omit-if-no-ref/ iomuxc_sd1_data5_i2c_sda_i2c1_sda: IOMUXC_SD1_DATA5_I2C_SDA_I2C1_SDA { 2008 pinmux = <0x303300a8 3 0x303305a8 0 0x30330308>; 2009 }; 2010 /omit-if-no-ref/ iomuxc_sd1_data5_uart_cts_b_uart2_cts_b: IOMUXC_SD1_DATA5_UART_CTS_B_UART2_CTS_B { 2011 pinmux = <0x303300a8 4 0x0 0 0x30330308>; 2012 }; 2013 /omit-if-no-ref/ iomuxc_sd1_data5_uart_rts_b_uart2_cts_b: IOMUXC_SD1_DATA5_UART_RTS_B_UART2_CTS_B { 2014 pinmux = <0x303300a8 4 0x303305ec 1 0x30330308>; 2015 }; 2016 /omit-if-no-ref/ iomuxc_sd1_data5_usdhc_data_usdhc1_data5: IOMUXC_SD1_DATA5_USDHC_DATA_USDHC1_DATA5 { 2017 pinmux = <0x303300a8 0 0x0 0 0x30330308>; 2018 }; 2019 /omit-if-no-ref/ iomuxc_sd1_data6_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC_SD1_DATA6_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { 2020 pinmux = <0x303300ac 1 0x30330588 0 0x3033030c>; 2021 }; 2022 /omit-if-no-ref/ iomuxc_sd1_data6_gpio_io_gpio2_io8: IOMUXC_SD1_DATA6_GPIO_IO_GPIO2_IO8 { 2023 pinmux = <0x303300ac 5 0x0 0 0x3033030c>; 2024 }; 2025 /omit-if-no-ref/ iomuxc_sd1_data6_i2c_scl_i2c2_scl: IOMUXC_SD1_DATA6_I2C_SCL_I2C2_SCL { 2026 pinmux = <0x303300ac 3 0x303305ac 0 0x3033030c>; 2027 }; 2028 /omit-if-no-ref/ iomuxc_sd1_data6_uart_rx_uart3_tx: IOMUXC_SD1_DATA6_UART_RX_UART3_TX { 2029 pinmux = <0x303300ac 4 0x303305f8 0 0x3033030c>; 2030 }; 2031 /omit-if-no-ref/ iomuxc_sd1_data6_uart_tx_uart3_tx: IOMUXC_SD1_DATA6_UART_TX_UART3_TX { 2032 pinmux = <0x303300ac 4 0x0 0 0x3033030c>; 2033 }; 2034 /omit-if-no-ref/ iomuxc_sd1_data6_usdhc_data_usdhc1_data6: IOMUXC_SD1_DATA6_USDHC_DATA_USDHC1_DATA6 { 2035 pinmux = <0x303300ac 0 0x0 0 0x3033030c>; 2036 }; 2037 /omit-if-no-ref/ iomuxc_sd1_data7_enet_rx_er_enet1_rx_er: IOMUXC_SD1_DATA7_ENET_RX_ER_ENET1_RX_ER { 2038 pinmux = <0x303300b0 1 0x3033058c 0 0x30330310>; 2039 }; 2040 /omit-if-no-ref/ iomuxc_sd1_data7_gpio_io_gpio2_io9: IOMUXC_SD1_DATA7_GPIO_IO_GPIO2_IO9 { 2041 pinmux = <0x303300b0 5 0x0 0 0x30330310>; 2042 }; 2043 /omit-if-no-ref/ iomuxc_sd1_data7_i2c_sda_i2c2_sda: IOMUXC_SD1_DATA7_I2C_SDA_I2C2_SDA { 2044 pinmux = <0x303300b0 3 0x303305b0 0 0x30330310>; 2045 }; 2046 /omit-if-no-ref/ iomuxc_sd1_data7_uart_rx_uart3_rx: IOMUXC_SD1_DATA7_UART_RX_UART3_RX { 2047 pinmux = <0x303300b0 4 0x303305f8 1 0x30330310>; 2048 }; 2049 /omit-if-no-ref/ iomuxc_sd1_data7_uart_tx_uart3_rx: IOMUXC_SD1_DATA7_UART_TX_UART3_RX { 2050 pinmux = <0x303300b0 4 0x0 0 0x30330310>; 2051 }; 2052 /omit-if-no-ref/ iomuxc_sd1_data7_usdhc_data_usdhc1_data7: IOMUXC_SD1_DATA7_USDHC_DATA_USDHC1_DATA7 { 2053 pinmux = <0x303300b0 0 0x0 0 0x30330310>; 2054 }; 2055 /omit-if-no-ref/ iomuxc_sd1_reset_b_enet_tx_clk_enet1_tx_clk: IOMUXC_SD1_RESET_B_ENET_TX_CLK_ENET1_TX_CLK { 2056 pinmux = <0x303300b4 1 0x30330578 0 0x30330314>; 2057 }; 2058 /omit-if-no-ref/ iomuxc_sd1_reset_b_gpio_io_gpio2_io10: IOMUXC_SD1_RESET_B_GPIO_IO_GPIO2_IO10 { 2059 pinmux = <0x303300b4 5 0x0 0 0x30330314>; 2060 }; 2061 /omit-if-no-ref/ iomuxc_sd1_reset_b_i2c_scl_i2c3_scl: IOMUXC_SD1_RESET_B_I2C_SCL_I2C3_SCL { 2062 pinmux = <0x303300b4 3 0x303305b4 0 0x30330314>; 2063 }; 2064 /omit-if-no-ref/ iomuxc_sd1_reset_b_uart_cts_b_uart3_rts_b: IOMUXC_SD1_RESET_B_UART_CTS_B_UART3_RTS_B { 2065 pinmux = <0x303300b4 4 0x0 0 0x30330314>; 2066 }; 2067 /omit-if-no-ref/ iomuxc_sd1_reset_b_uart_rts_b_uart3_rts_b: IOMUXC_SD1_RESET_B_UART_RTS_B_UART3_RTS_B { 2068 pinmux = <0x303300b4 4 0x303305f4 0 0x30330314>; 2069 }; 2070 /omit-if-no-ref/ iomuxc_sd1_reset_b_usdhc_reset_b_usdhc1_reset_b: IOMUXC_SD1_RESET_B_USDHC_RESET_B_USDHC1_RESET_B { 2071 pinmux = <0x303300b4 0 0x0 0 0x30330314>; 2072 }; 2073 /omit-if-no-ref/ iomuxc_sd1_strobe_gpio_io_gpio2_io11: IOMUXC_SD1_STROBE_GPIO_IO_GPIO2_IO11 { 2074 pinmux = <0x303300b8 5 0x0 0 0x30330318>; 2075 }; 2076 /omit-if-no-ref/ iomuxc_sd1_strobe_i2c_sda_i2c3_sda: IOMUXC_SD1_STROBE_I2C_SDA_I2C3_SDA { 2077 pinmux = <0x303300b8 3 0x303305b8 0 0x30330318>; 2078 }; 2079 /omit-if-no-ref/ iomuxc_sd1_strobe_uart_cts_b_uart3_cts_b: IOMUXC_SD1_STROBE_UART_CTS_B_UART3_CTS_B { 2080 pinmux = <0x303300b8 4 0x0 0 0x30330318>; 2081 }; 2082 /omit-if-no-ref/ iomuxc_sd1_strobe_uart_rts_b_uart3_cts_b: IOMUXC_SD1_STROBE_UART_RTS_B_UART3_CTS_B { 2083 pinmux = <0x303300b8 4 0x303305f4 1 0x30330318>; 2084 }; 2085 /omit-if-no-ref/ iomuxc_sd1_strobe_usdhc_strobe_usdhc1_strobe: IOMUXC_SD1_STROBE_USDHC_STROBE_USDHC1_STROBE { 2086 pinmux = <0x303300b8 0 0x0 0 0x30330318>; 2087 }; 2088 /omit-if-no-ref/ iomuxc_sd2_cd_b_gpio_io_gpio2_io12: IOMUXC_SD2_CD_B_GPIO_IO_GPIO2_IO12 { 2089 pinmux = <0x303300bc 5 0x0 0 0x3033031c>; 2090 }; 2091 /omit-if-no-ref/ iomuxc_sd2_cd_b_usdhc_cd_b_usdhc2_cd_b: IOMUXC_SD2_CD_B_USDHC_CD_B_USDHC2_CD_B { 2092 pinmux = <0x303300bc 0 0x0 0 0x3033031c>; 2093 }; 2094 /omit-if-no-ref/ iomuxc_sd2_clk_ecspi_sclk_ecspi2_sclk: IOMUXC_SD2_CLK_ECSPI_SCLK_ECSPI2_SCLK { 2095 pinmux = <0x303300c0 2 0x30330568 0 0x30330320>; 2096 }; 2097 /omit-if-no-ref/ iomuxc_sd2_clk_gpio_io_gpio2_io13: IOMUXC_SD2_CLK_GPIO_IO_GPIO2_IO13 { 2098 pinmux = <0x303300c0 5 0x0 0 0x30330320>; 2099 }; 2100 /omit-if-no-ref/ iomuxc_sd2_clk_uart_rx_uart4_rx: IOMUXC_SD2_CLK_UART_RX_UART4_RX { 2101 pinmux = <0x303300c0 3 0x30330600 0 0x30330320>; 2102 }; 2103 /omit-if-no-ref/ iomuxc_sd2_clk_uart_tx_uart4_rx: IOMUXC_SD2_CLK_UART_TX_UART4_RX { 2104 pinmux = <0x303300c0 3 0x0 0 0x30330320>; 2105 }; 2106 /omit-if-no-ref/ iomuxc_sd2_clk_usdhc_clk_usdhc2_clk: IOMUXC_SD2_CLK_USDHC_CLK_USDHC2_CLK { 2107 pinmux = <0x303300c0 0 0x0 0 0x30330320>; 2108 }; 2109 /omit-if-no-ref/ iomuxc_sd2_cmd_ecspi_mosi_ecspi2_mosi: IOMUXC_SD2_CMD_ECSPI_MOSI_ECSPI2_MOSI { 2110 pinmux = <0x303300c4 2 0x30330570 0 0x30330324>; 2111 }; 2112 /omit-if-no-ref/ iomuxc_sd2_cmd_gpio_io_gpio2_io14: IOMUXC_SD2_CMD_GPIO_IO_GPIO2_IO14 { 2113 pinmux = <0x303300c4 5 0x0 0 0x30330324>; 2114 }; 2115 /omit-if-no-ref/ iomuxc_sd2_cmd_pdm_clk_pdm_clk: IOMUXC_SD2_CMD_PDM_CLK_PDM_CLK { 2116 pinmux = <0x303300c4 4 0x0 0 0x30330324>; 2117 }; 2118 /omit-if-no-ref/ iomuxc_sd2_cmd_uart_rx_uart4_tx: IOMUXC_SD2_CMD_UART_RX_UART4_TX { 2119 pinmux = <0x303300c4 3 0x30330600 1 0x30330324>; 2120 }; 2121 /omit-if-no-ref/ iomuxc_sd2_cmd_uart_tx_uart4_tx: IOMUXC_SD2_CMD_UART_TX_UART4_TX { 2122 pinmux = <0x303300c4 3 0x0 0 0x30330324>; 2123 }; 2124 /omit-if-no-ref/ iomuxc_sd2_cmd_usdhc_cmd_usdhc2_cmd: IOMUXC_SD2_CMD_USDHC_CMD_USDHC2_CMD { 2125 pinmux = <0x303300c4 0 0x0 0 0x30330324>; 2126 }; 2127 /omit-if-no-ref/ iomuxc_sd2_data0_gpio_io_gpio2_io15: IOMUXC_SD2_DATA0_GPIO_IO_GPIO2_IO15 { 2128 pinmux = <0x303300c8 5 0x0 0 0x30330328>; 2129 }; 2130 /omit-if-no-ref/ iomuxc_sd2_data0_i2c_sda_i2c4_sda: IOMUXC_SD2_DATA0_I2C_SDA_I2C4_SDA { 2131 pinmux = <0x303300c8 2 0x303305c0 1 0x30330328>; 2132 }; 2133 /omit-if-no-ref/ iomuxc_sd2_data0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SD2_DATA0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { 2134 pinmux = <0x303300c8 4 0x303304c0 2 0x30330328>; 2135 }; 2136 /omit-if-no-ref/ iomuxc_sd2_data0_uart_rx_uart2_rx: IOMUXC_SD2_DATA0_UART_RX_UART2_RX { 2137 pinmux = <0x303300c8 3 0x303305f0 2 0x30330328>; 2138 }; 2139 /omit-if-no-ref/ iomuxc_sd2_data0_uart_tx_uart2_rx: IOMUXC_SD2_DATA0_UART_TX_UART2_RX { 2140 pinmux = <0x303300c8 3 0x0 0 0x30330328>; 2141 }; 2142 /omit-if-no-ref/ iomuxc_sd2_data0_usdhc_data_usdhc2_data0: IOMUXC_SD2_DATA0_USDHC_DATA_USDHC2_DATA0 { 2143 pinmux = <0x303300c8 0 0x0 0 0x30330328>; 2144 }; 2145 /omit-if-no-ref/ iomuxc_sd2_data1_gpio_io_gpio2_io16: IOMUXC_SD2_DATA1_GPIO_IO_GPIO2_IO16 { 2146 pinmux = <0x303300cc 5 0x0 0 0x3033032c>; 2147 }; 2148 /omit-if-no-ref/ iomuxc_sd2_data1_i2c_scl_i2c4_scl: IOMUXC_SD2_DATA1_I2C_SCL_I2C4_SCL { 2149 pinmux = <0x303300cc 2 0x303305bc 1 0x3033032c>; 2150 }; 2151 /omit-if-no-ref/ iomuxc_sd2_data1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SD2_DATA1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { 2152 pinmux = <0x303300cc 4 0x303304c4 2 0x3033032c>; 2153 }; 2154 /omit-if-no-ref/ iomuxc_sd2_data1_uart_rx_uart2_tx: IOMUXC_SD2_DATA1_UART_RX_UART2_TX { 2155 pinmux = <0x303300cc 3 0x303305f0 3 0x3033032c>; 2156 }; 2157 /omit-if-no-ref/ iomuxc_sd2_data1_uart_tx_uart2_tx: IOMUXC_SD2_DATA1_UART_TX_UART2_TX { 2158 pinmux = <0x303300cc 3 0x0 0 0x3033032c>; 2159 }; 2160 /omit-if-no-ref/ iomuxc_sd2_data1_usdhc_data_usdhc2_data1: IOMUXC_SD2_DATA1_USDHC_DATA_USDHC2_DATA1 { 2161 pinmux = <0x303300cc 0 0x0 0 0x3033032c>; 2162 }; 2163 /omit-if-no-ref/ iomuxc_sd2_data2_ecspi_ss_ecspi2_ss0: IOMUXC_SD2_DATA2_ECSPI_SS_ECSPI2_SS0 { 2164 pinmux = <0x303300d0 2 0x30330574 0 0x30330330>; 2165 }; 2166 /omit-if-no-ref/ iomuxc_sd2_data2_gpio_io_gpio2_io17: IOMUXC_SD2_DATA2_GPIO_IO_GPIO2_IO17 { 2167 pinmux = <0x303300d0 5 0x0 0 0x30330330>; 2168 }; 2169 /omit-if-no-ref/ iomuxc_sd2_data2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SD2_DATA2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { 2170 pinmux = <0x303300d0 4 0x303304c8 2 0x30330330>; 2171 }; 2172 /omit-if-no-ref/ iomuxc_sd2_data2_spdif_out_spdif1_out: IOMUXC_SD2_DATA2_SPDIF_OUT_SPDIF1_OUT { 2173 pinmux = <0x303300d0 3 0x0 0 0x30330330>; 2174 }; 2175 /omit-if-no-ref/ iomuxc_sd2_data2_usdhc_data_usdhc2_data2: IOMUXC_SD2_DATA2_USDHC_DATA_USDHC2_DATA2 { 2176 pinmux = <0x303300d0 0 0x0 0 0x30330330>; 2177 }; 2178 /omit-if-no-ref/ iomuxc_sd2_data3_ecspi_miso_ecspi2_miso: IOMUXC_SD2_DATA3_ECSPI_MISO_ECSPI2_MISO { 2179 pinmux = <0x303300d4 2 0x3033056c 0 0x30330334>; 2180 }; 2181 /omit-if-no-ref/ iomuxc_sd2_data3_gpio_io_gpio2_io18: IOMUXC_SD2_DATA3_GPIO_IO_GPIO2_IO18 { 2182 pinmux = <0x303300d4 5 0x0 0 0x30330334>; 2183 }; 2184 /omit-if-no-ref/ iomuxc_sd2_data3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SD2_DATA3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { 2185 pinmux = <0x303300d4 4 0x303304cc 2 0x30330334>; 2186 }; 2187 /omit-if-no-ref/ iomuxc_sd2_data3_spdif_in_spdif1_in: IOMUXC_SD2_DATA3_SPDIF_IN_SPDIF1_IN { 2188 pinmux = <0x303300d4 3 0x30330544 1 0x30330334>; 2189 }; 2190 /omit-if-no-ref/ iomuxc_sd2_data3_usdhc_data_usdhc2_data3: IOMUXC_SD2_DATA3_USDHC_DATA_USDHC2_DATA3 { 2191 pinmux = <0x303300d4 0 0x0 0 0x30330334>; 2192 }; 2193 /omit-if-no-ref/ iomuxc_sd2_reset_b_gpio_io_gpio2_io19: IOMUXC_SD2_RESET_B_GPIO_IO_GPIO2_IO19 { 2194 pinmux = <0x303300d8 5 0x0 0 0x30330338>; 2195 }; 2196 /omit-if-no-ref/ iomuxc_sd2_reset_b_usdhc_reset_b_usdhc2_reset_b: IOMUXC_SD2_RESET_B_USDHC_RESET_B_USDHC2_RESET_B { 2197 pinmux = <0x303300d8 0 0x0 0 0x30330338>; 2198 }; 2199 /omit-if-no-ref/ iomuxc_sd2_wp_coresight_eventi_coresight_eventi: IOMUXC_SD2_WP_CORESIGHT_EVENTI_CORESIGHT_EVENTI { 2200 pinmux = <0x303300dc 6 0x0 0 0x3033033c>; 2201 }; 2202 /omit-if-no-ref/ iomuxc_sd2_wp_gpio_io_gpio2_io20: IOMUXC_SD2_WP_GPIO_IO_GPIO2_IO20 { 2203 pinmux = <0x303300dc 5 0x0 0 0x3033033c>; 2204 }; 2205 /omit-if-no-ref/ iomuxc_sd2_wp_usdhc_wp_usdhc2_wp: IOMUXC_SD2_WP_USDHC_WP_USDHC2_WP { 2206 pinmux = <0x303300dc 0 0x0 0 0x3033033c>; 2207 }; 2208 /omit-if-no-ref/ iomuxc_spdif_ext_clk_gpio_io_gpio5_io5: IOMUXC_SPDIF_EXT_CLK_GPIO_IO_GPIO5_IO5 { 2209 pinmux = <0x303301dc 5 0x0 0 0x3033043c>; 2210 }; 2211 /omit-if-no-ref/ iomuxc_spdif_ext_clk_gpt_compare_gpt1_compare3: IOMUXC_SPDIF_EXT_CLK_GPT_COMPARE_GPT1_COMPARE3 { 2212 pinmux = <0x303301dc 3 0x0 0 0x3033043c>; 2213 }; 2214 /omit-if-no-ref/ iomuxc_spdif_ext_clk_pwm_out_pwm1_out: IOMUXC_SPDIF_EXT_CLK_PWM_OUT_PWM1_OUT { 2215 pinmux = <0x303301dc 1 0x0 0 0x3033043c>; 2216 }; 2217 /omit-if-no-ref/ iomuxc_spdif_ext_clk_spdif_ext_clk_spdif1_ext_clk: IOMUXC_SPDIF_EXT_CLK_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { 2218 pinmux = <0x303301dc 0 0x30330548 1 0x3033043c>; 2219 }; 2220 /omit-if-no-ref/ iomuxc_spdif_rx_can_rx_can1_rx: IOMUXC_SPDIF_RX_CAN_RX_CAN1_RX { 2221 pinmux = <0x303301d8 4 0x3033054c 2 0x30330438>; 2222 }; 2223 /omit-if-no-ref/ iomuxc_spdif_rx_gpio_io_gpio5_io4: IOMUXC_SPDIF_RX_GPIO_IO_GPIO5_IO4 { 2224 pinmux = <0x303301d8 5 0x0 0 0x30330438>; 2225 }; 2226 /omit-if-no-ref/ iomuxc_spdif_rx_gpt_compare_gpt1_compare2: IOMUXC_SPDIF_RX_GPT_COMPARE_GPT1_COMPARE2 { 2227 pinmux = <0x303301d8 3 0x0 0 0x30330438>; 2228 }; 2229 /omit-if-no-ref/ iomuxc_spdif_rx_i2c_sda_i2c5_sda: IOMUXC_SPDIF_RX_I2C_SDA_I2C5_SDA { 2230 pinmux = <0x303301d8 2 0x303305c8 2 0x30330438>; 2231 }; 2232 /omit-if-no-ref/ iomuxc_spdif_rx_pwm_out_pwm2_out: IOMUXC_SPDIF_RX_PWM_OUT_PWM2_OUT { 2233 pinmux = <0x303301d8 1 0x0 0 0x30330438>; 2234 }; 2235 /omit-if-no-ref/ iomuxc_spdif_rx_spdif_in_spdif1_in: IOMUXC_SPDIF_RX_SPDIF_IN_SPDIF1_IN { 2236 pinmux = <0x303301d8 0 0x30330544 4 0x30330438>; 2237 }; 2238 /omit-if-no-ref/ iomuxc_spdif_tx_can_tx_can1_tx: IOMUXC_SPDIF_TX_CAN_TX_CAN1_TX { 2239 pinmux = <0x303301d4 4 0x0 0 0x30330434>; 2240 }; 2241 /omit-if-no-ref/ iomuxc_spdif_tx_gpio_io_gpio5_io3: IOMUXC_SPDIF_TX_GPIO_IO_GPIO5_IO3 { 2242 pinmux = <0x303301d4 5 0x0 0 0x30330434>; 2243 }; 2244 /omit-if-no-ref/ iomuxc_spdif_tx_gpt_compare_gpt1_compare1: IOMUXC_SPDIF_TX_GPT_COMPARE_GPT1_COMPARE1 { 2245 pinmux = <0x303301d4 3 0x0 0 0x30330434>; 2246 }; 2247 /omit-if-no-ref/ iomuxc_spdif_tx_i2c_scl_i2c5_scl: IOMUXC_SPDIF_TX_I2C_SCL_I2C5_SCL { 2248 pinmux = <0x303301d4 2 0x303305c4 2 0x30330434>; 2249 }; 2250 /omit-if-no-ref/ iomuxc_spdif_tx_pwm_out_pwm3_out: IOMUXC_SPDIF_TX_PWM_OUT_PWM3_OUT { 2251 pinmux = <0x303301d4 1 0x0 0 0x30330434>; 2252 }; 2253 /omit-if-no-ref/ iomuxc_spdif_tx_spdif_out_spdif1_out: IOMUXC_SPDIF_TX_SPDIF_OUT_SPDIF1_OUT { 2254 pinmux = <0x303301d4 0 0x0 0 0x30330434>; 2255 }; 2256 /omit-if-no-ref/ iomuxc_uart1_rxd_ecspi_sclk_ecspi3_sclk: IOMUXC_UART1_RXD_ECSPI_SCLK_ECSPI3_SCLK { 2257 pinmux = <0x30330220 1 0x0 0 0x30330480>; 2258 }; 2259 /omit-if-no-ref/ iomuxc_uart1_rxd_gpio_io_gpio5_io22: IOMUXC_UART1_RXD_GPIO_IO_GPIO5_IO22 { 2260 pinmux = <0x30330220 5 0x0 0 0x30330480>; 2261 }; 2262 /omit-if-no-ref/ iomuxc_uart1_rxd_uart_rx_uart1_rx: IOMUXC_UART1_RXD_UART_RX_UART1_RX { 2263 pinmux = <0x30330220 0 0x303305e8 4 0x30330480>; 2264 }; 2265 /omit-if-no-ref/ iomuxc_uart1_rxd_uart_tx_uart1_rx: IOMUXC_UART1_RXD_UART_TX_UART1_RX { 2266 pinmux = <0x30330220 0 0x0 0 0x30330480>; 2267 }; 2268 /omit-if-no-ref/ iomuxc_uart1_txd_ecspi_mosi_ecspi3_mosi: IOMUXC_UART1_TXD_ECSPI_MOSI_ECSPI3_MOSI { 2269 pinmux = <0x30330224 1 0x0 0 0x30330484>; 2270 }; 2271 /omit-if-no-ref/ iomuxc_uart1_txd_gpio_io_gpio5_io23: IOMUXC_UART1_TXD_GPIO_IO_GPIO5_IO23 { 2272 pinmux = <0x30330224 5 0x0 0 0x30330484>; 2273 }; 2274 /omit-if-no-ref/ iomuxc_uart1_txd_uart_rx_uart1_tx: IOMUXC_UART1_TXD_UART_RX_UART1_TX { 2275 pinmux = <0x30330224 0 0x303305e8 5 0x30330484>; 2276 }; 2277 /omit-if-no-ref/ iomuxc_uart1_txd_uart_tx_uart1_tx: IOMUXC_UART1_TXD_UART_TX_UART1_TX { 2278 pinmux = <0x30330224 0 0x0 0 0x30330484>; 2279 }; 2280 /omit-if-no-ref/ iomuxc_uart2_rxd_ecspi_miso_ecspi3_miso: IOMUXC_UART2_RXD_ECSPI_MISO_ECSPI3_MISO { 2281 pinmux = <0x30330228 1 0x0 0 0x30330488>; 2282 }; 2283 /omit-if-no-ref/ iomuxc_uart2_rxd_gpio_io_gpio5_io24: IOMUXC_UART2_RXD_GPIO_IO_GPIO5_IO24 { 2284 pinmux = <0x30330228 5 0x0 0 0x30330488>; 2285 }; 2286 /omit-if-no-ref/ iomuxc_uart2_rxd_gpt_compare_gpt1_compare3: IOMUXC_UART2_RXD_GPT_COMPARE_GPT1_COMPARE3 { 2287 pinmux = <0x30330228 3 0x0 0 0x30330488>; 2288 }; 2289 /omit-if-no-ref/ iomuxc_uart2_rxd_uart_rx_uart2_rx: IOMUXC_UART2_RXD_UART_RX_UART2_RX { 2290 pinmux = <0x30330228 0 0x303305f0 6 0x30330488>; 2291 }; 2292 /omit-if-no-ref/ iomuxc_uart2_rxd_uart_tx_uart2_rx: IOMUXC_UART2_RXD_UART_TX_UART2_RX { 2293 pinmux = <0x30330228 0 0x0 0 0x30330488>; 2294 }; 2295 /omit-if-no-ref/ iomuxc_uart2_txd_ecspi_ss_ecspi3_ss0: IOMUXC_UART2_TXD_ECSPI_SS_ECSPI3_SS0 { 2296 pinmux = <0x3033022c 1 0x0 0 0x3033048c>; 2297 }; 2298 /omit-if-no-ref/ iomuxc_uart2_txd_gpio_io_gpio5_io25: IOMUXC_UART2_TXD_GPIO_IO_GPIO5_IO25 { 2299 pinmux = <0x3033022c 5 0x0 0 0x3033048c>; 2300 }; 2301 /omit-if-no-ref/ iomuxc_uart2_txd_gpt_compare_gpt1_compare2: IOMUXC_UART2_TXD_GPT_COMPARE_GPT1_COMPARE2 { 2302 pinmux = <0x3033022c 3 0x0 0 0x3033048c>; 2303 }; 2304 /omit-if-no-ref/ iomuxc_uart2_txd_uart_rx_uart2_tx: IOMUXC_UART2_TXD_UART_RX_UART2_TX { 2305 pinmux = <0x3033022c 0 0x303305f0 7 0x3033048c>; 2306 }; 2307 /omit-if-no-ref/ iomuxc_uart2_txd_uart_tx_uart2_tx: IOMUXC_UART2_TXD_UART_TX_UART2_TX { 2308 pinmux = <0x3033022c 0 0x0 0 0x3033048c>; 2309 }; 2310 /omit-if-no-ref/ iomuxc_uart3_rxd_can_tx_can2_tx: IOMUXC_UART3_RXD_CAN_TX_CAN2_TX { 2311 pinmux = <0x30330230 4 0x0 0 0x30330490>; 2312 }; 2313 /omit-if-no-ref/ iomuxc_uart3_rxd_gpio_io_gpio5_io26: IOMUXC_UART3_RXD_GPIO_IO_GPIO5_IO26 { 2314 pinmux = <0x30330230 5 0x0 0 0x30330490>; 2315 }; 2316 /omit-if-no-ref/ iomuxc_uart3_rxd_gpt_capture_gpt1_capture2: IOMUXC_UART3_RXD_GPT_CAPTURE_GPT1_CAPTURE2 { 2317 pinmux = <0x30330230 3 0x30330598 1 0x30330490>; 2318 }; 2319 /omit-if-no-ref/ iomuxc_uart3_rxd_uart_cts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_CTS_B_UART1_CTS_B { 2320 pinmux = <0x30330230 1 0x0 0 0x30330490>; 2321 }; 2322 /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_RTS_B_UART1_CTS_B { 2323 pinmux = <0x30330230 1 0x303305e4 4 0x30330490>; 2324 }; 2325 /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rx_uart3_rx: IOMUXC_UART3_RXD_UART_RX_UART3_RX { 2326 pinmux = <0x30330230 0 0x303305f8 6 0x30330490>; 2327 }; 2328 /omit-if-no-ref/ iomuxc_uart3_rxd_uart_tx_uart3_rx: IOMUXC_UART3_RXD_UART_TX_UART3_RX { 2329 pinmux = <0x30330230 0 0x0 0 0x30330490>; 2330 }; 2331 /omit-if-no-ref/ iomuxc_uart3_rxd_usdhc_reset_b_usdhc3_reset_b: IOMUXC_UART3_RXD_USDHC_RESET_B_USDHC3_RESET_B { 2332 pinmux = <0x30330230 2 0x0 0 0x30330490>; 2333 }; 2334 /omit-if-no-ref/ iomuxc_uart3_txd_can_rx_can2_rx: IOMUXC_UART3_TXD_CAN_RX_CAN2_RX { 2335 pinmux = <0x30330234 4 0x30330550 2 0x30330494>; 2336 }; 2337 /omit-if-no-ref/ iomuxc_uart3_txd_gpio_io_gpio5_io27: IOMUXC_UART3_TXD_GPIO_IO_GPIO5_IO27 { 2338 pinmux = <0x30330234 5 0x0 0 0x30330494>; 2339 }; 2340 /omit-if-no-ref/ iomuxc_uart3_txd_gpt_clk_gpt1_clk: IOMUXC_UART3_TXD_GPT_CLK_GPT1_CLK { 2341 pinmux = <0x30330234 3 0x3033059c 1 0x30330494>; 2342 }; 2343 /omit-if-no-ref/ iomuxc_uart3_txd_uart_cts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_CTS_B_UART1_RTS_B { 2344 pinmux = <0x30330234 1 0x0 0 0x30330494>; 2345 }; 2346 /omit-if-no-ref/ iomuxc_uart3_txd_uart_rts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_RTS_B_UART1_RTS_B { 2347 pinmux = <0x30330234 1 0x303305e4 5 0x30330494>; 2348 }; 2349 /omit-if-no-ref/ iomuxc_uart3_txd_uart_rx_uart3_tx: IOMUXC_UART3_TXD_UART_RX_UART3_TX { 2350 pinmux = <0x30330234 0 0x303305f8 7 0x30330494>; 2351 }; 2352 /omit-if-no-ref/ iomuxc_uart3_txd_uart_tx_uart3_tx: IOMUXC_UART3_TXD_UART_TX_UART3_TX { 2353 pinmux = <0x30330234 0 0x0 0 0x30330494>; 2354 }; 2355 /omit-if-no-ref/ iomuxc_uart3_txd_usdhc_vselect_usdhc3_vselect: IOMUXC_UART3_TXD_USDHC_VSELECT_USDHC3_VSELECT { 2356 pinmux = <0x30330234 2 0x0 0 0x30330494>; 2357 }; 2358 /omit-if-no-ref/ iomuxc_uart4_rxd_gpio_io_gpio5_io28: IOMUXC_UART4_RXD_GPIO_IO_GPIO5_IO28 { 2359 pinmux = <0x30330238 5 0x0 0 0x30330498>; 2360 }; 2361 /omit-if-no-ref/ iomuxc_uart4_rxd_gpt_compare_gpt1_compare1: IOMUXC_UART4_RXD_GPT_COMPARE_GPT1_COMPARE1 { 2362 pinmux = <0x30330238 3 0x0 0 0x30330498>; 2363 }; 2364 /omit-if-no-ref/ iomuxc_uart4_rxd_i2c_scl_i2c6_scl: IOMUXC_UART4_RXD_I2C_SCL_I2C6_SCL { 2365 pinmux = <0x30330238 4 0x303305cc 2 0x30330498>; 2366 }; 2367 /omit-if-no-ref/ iomuxc_uart4_rxd_pcie_clkreq_b_pcie1_clkreq_b: IOMUXC_UART4_RXD_PCIE_CLKREQ_B_PCIE1_CLKREQ_B { 2368 pinmux = <0x30330238 2 0x303305a0 1 0x30330498>; 2369 }; 2370 /omit-if-no-ref/ iomuxc_uart4_rxd_uart_cts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_CTS_B_UART2_CTS_B { 2371 pinmux = <0x30330238 1 0x0 0 0x30330498>; 2372 }; 2373 /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_RTS_B_UART2_CTS_B { 2374 pinmux = <0x30330238 1 0x303305ec 4 0x30330498>; 2375 }; 2376 /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rx_uart4_rx: IOMUXC_UART4_RXD_UART_RX_UART4_RX { 2377 pinmux = <0x30330238 0 0x30330600 8 0x30330498>; 2378 }; 2379 /omit-if-no-ref/ iomuxc_uart4_rxd_uart_tx_uart4_rx: IOMUXC_UART4_RXD_UART_TX_UART4_RX { 2380 pinmux = <0x30330238 0 0x0 0 0x30330498>; 2381 }; 2382 /omit-if-no-ref/ iomuxc_uart4_txd_gpio_io_gpio5_io29: IOMUXC_UART4_TXD_GPIO_IO_GPIO5_IO29 { 2383 pinmux = <0x3033023c 5 0x0 0 0x3033049c>; 2384 }; 2385 /omit-if-no-ref/ iomuxc_uart4_txd_gpt_capture_gpt1_capture1: IOMUXC_UART4_TXD_GPT_CAPTURE_GPT1_CAPTURE1 { 2386 pinmux = <0x3033023c 3 0x30330594 1 0x3033049c>; 2387 }; 2388 /omit-if-no-ref/ iomuxc_uart4_txd_i2c_sda_i2c6_sda: IOMUXC_UART4_TXD_I2C_SDA_I2C6_SDA { 2389 pinmux = <0x3033023c 4 0x303305d0 2 0x3033049c>; 2390 }; 2391 /omit-if-no-ref/ iomuxc_uart4_txd_uart_cts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_CTS_B_UART2_RTS_B { 2392 pinmux = <0x3033023c 1 0x0 0 0x3033049c>; 2393 }; 2394 /omit-if-no-ref/ iomuxc_uart4_txd_uart_rts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_RTS_B_UART2_RTS_B { 2395 pinmux = <0x3033023c 1 0x303305ec 5 0x3033049c>; 2396 }; 2397 /omit-if-no-ref/ iomuxc_uart4_txd_uart_rx_uart4_tx: IOMUXC_UART4_TXD_UART_RX_UART4_TX { 2398 pinmux = <0x3033023c 0 0x30330600 9 0x3033049c>; 2399 }; 2400 /omit-if-no-ref/ iomuxc_uart4_txd_uart_tx_uart4_tx: IOMUXC_UART4_TXD_UART_TX_UART4_TX { 2401 pinmux = <0x3033023c 0 0x0 0 0x3033049c>; 2402 }; 2403}; 2404 2405
