/* * Copyright (c) 2022, NXP * SPDX-License-Identifier: Apache-2.0 * * Note: File generated by imx_cfg_utils.py * from configuration data for MIMX8ML8DVNLZ */ /* * SOC level pinctrl defintions * These definitions define SOC level defaults for each pin, * and select the pinmux for the pin. Pinmux entries are a tuple of: * * the mux_register and input_daisy reside in the IOMUXC peripheral, and * the pinctrl driver will write the mux_mode and input_daisy values into * each register, respectively. The config_register is used to configure * the pin based on the devicetree properties set */ &iomuxc { /omit-if-no-ref/ iomuxc_boot_mode0_src_boot_mode_src_boot_mode0: IOMUXC_BOOT_MODE0_SRC_BOOT_MODE_SRC_BOOT_MODE0 { pinmux = <0x0 0 0x0 0 0x30330250>; }; /omit-if-no-ref/ iomuxc_boot_mode1_src_boot_mode_src_boot_mode1: IOMUXC_BOOT_MODE1_SRC_BOOT_MODE_SRC_BOOT_MODE1 { pinmux = <0x0 0 0x0 0 0x30330254>; }; /omit-if-no-ref/ iomuxc_boot_mode2_src_boot_mode_src_boot_mode2: IOMUXC_BOOT_MODE2_SRC_BOOT_MODE_SRC_BOOT_MODE2 { pinmux = <0x0 0 0x0 0 0x30330258>; }; /omit-if-no-ref/ iomuxc_boot_mode3_src_boot_mode_src_boot_mode3: IOMUXC_BOOT_MODE3_SRC_BOOT_MODE_SRC_BOOT_MODE3 { pinmux = <0x0 0 0x0 0 0x3033025c>; }; /omit-if-no-ref/ iomuxc_ecspi1_miso_ecspi_miso_ecspi1_miso: IOMUXC_ECSPI1_MISO_ECSPI_MISO_ECSPI1_MISO { pinmux = <0x303301e8 0 0x3033055c 0 0x30330448>; }; /omit-if-no-ref/ iomuxc_ecspi1_miso_gpio_io_gpio5_io8: IOMUXC_ECSPI1_MISO_GPIO_IO_GPIO5_IO8 { pinmux = <0x303301e8 5 0x0 0 0x30330448>; }; /omit-if-no-ref/ iomuxc_ecspi1_miso_i2c_scl_i2c2_scl: IOMUXC_ECSPI1_MISO_I2C_SCL_I2C2_SCL { pinmux = <0x303301e8 2 0x303305ac 1 0x30330448>; }; /omit-if-no-ref/ iomuxc_ecspi1_miso_sai_rx_data_sai7_rx_data0: IOMUXC_ECSPI1_MISO_SAI_RX_DATA_SAI7_RX_DATA0 { pinmux = <0x303301e8 3 0x30330534 1 0x30330448>; }; /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_cts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_CTS_B_UART3_CTS_B { pinmux = <0x303301e8 1 0x0 0 0x30330448>; }; /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_rts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_RTS_B_UART3_CTS_B { pinmux = <0x303301e8 1 0x303305f4 2 0x30330448>; }; /omit-if-no-ref/ iomuxc_ecspi1_mosi_ecspi_mosi_ecspi1_mosi: IOMUXC_ECSPI1_MOSI_ECSPI_MOSI_ECSPI1_MOSI { pinmux = <0x303301e4 0 0x30330560 0 0x30330444>; }; /omit-if-no-ref/ iomuxc_ecspi1_mosi_gpio_io_gpio5_io7: IOMUXC_ECSPI1_MOSI_GPIO_IO_GPIO5_IO7 { pinmux = <0x303301e4 5 0x0 0 0x30330444>; }; /omit-if-no-ref/ iomuxc_ecspi1_mosi_i2c_sda_i2c1_sda: IOMUXC_ECSPI1_MOSI_I2C_SDA_I2C1_SDA { pinmux = <0x303301e4 2 0x303305a8 1 0x30330444>; }; /omit-if-no-ref/ iomuxc_ecspi1_mosi_sai_rx_bclk_sai7_rx_bclk: IOMUXC_ECSPI1_MOSI_SAI_RX_BCLK_SAI7_RX_BCLK { pinmux = <0x303301e4 3 0x30330530 1 0x30330444>; }; /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_rx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_RX_UART3_TX { pinmux = <0x303301e4 1 0x303305f8 5 0x30330444>; }; /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_tx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_TX_UART3_TX { pinmux = <0x303301e4 1 0x0 0 0x30330444>; }; /omit-if-no-ref/ iomuxc_ecspi1_sclk_ecspi_sclk_ecspi1_sclk: IOMUXC_ECSPI1_SCLK_ECSPI_SCLK_ECSPI1_SCLK { pinmux = <0x303301e0 0 0x30330558 0 0x30330440>; }; /omit-if-no-ref/ iomuxc_ecspi1_sclk_gpio_io_gpio5_io6: IOMUXC_ECSPI1_SCLK_GPIO_IO_GPIO5_IO6 { pinmux = <0x303301e0 5 0x0 0 0x30330440>; }; /omit-if-no-ref/ iomuxc_ecspi1_sclk_i2c_scl_i2c1_scl: IOMUXC_ECSPI1_SCLK_I2C_SCL_I2C1_SCL { pinmux = <0x303301e0 2 0x303305a4 1 0x30330440>; }; /omit-if-no-ref/ iomuxc_ecspi1_sclk_sai_rx_sync_sai7_rx_sync: IOMUXC_ECSPI1_SCLK_SAI_RX_SYNC_SAI7_RX_SYNC { pinmux = <0x303301e0 3 0x30330538 1 0x30330440>; }; /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_rx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_RX_UART3_RX { pinmux = <0x303301e0 1 0x303305f8 4 0x30330440>; }; /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_tx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_TX_UART3_RX { pinmux = <0x303301e0 1 0x0 0 0x30330440>; }; /omit-if-no-ref/ iomuxc_ecspi1_ss0_ecspi_ss_ecspi1_ss0: IOMUXC_ECSPI1_SS0_ECSPI_SS_ECSPI1_SS0 { pinmux = <0x303301ec 0 0x30330564 0 0x3033044c>; }; /omit-if-no-ref/ iomuxc_ecspi1_ss0_gpio_io_gpio5_io9: IOMUXC_ECSPI1_SS0_GPIO_IO_GPIO5_IO9 { pinmux = <0x303301ec 5 0x0 0 0x3033044c>; }; /omit-if-no-ref/ iomuxc_ecspi1_ss0_i2c_sda_i2c2_sda: IOMUXC_ECSPI1_SS0_I2C_SDA_I2C2_SDA { pinmux = <0x303301ec 2 0x303305b0 1 0x3033044c>; }; /omit-if-no-ref/ iomuxc_ecspi1_ss0_sai_tx_sync_sai7_tx_sync: IOMUXC_ECSPI1_SS0_SAI_TX_SYNC_SAI7_TX_SYNC { pinmux = <0x303301ec 3 0x30330540 1 0x3033044c>; }; /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_cts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_CTS_B_UART3_RTS_B { pinmux = <0x303301ec 1 0x0 0 0x3033044c>; }; /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_rts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_RTS_B_UART3_RTS_B { pinmux = <0x303301ec 1 0x303305f4 3 0x3033044c>; }; /omit-if-no-ref/ iomuxc_ecspi2_miso_ccm_clko_ccm_clko1: IOMUXC_ECSPI2_MISO_CCM_CLKO_CCM_CLKO1 { pinmux = <0x303301f8 4 0x0 0 0x30330458>; }; /omit-if-no-ref/ iomuxc_ecspi2_miso_ecspi_miso_ecspi2_miso: IOMUXC_ECSPI2_MISO_ECSPI_MISO_ECSPI2_MISO { pinmux = <0x303301f8 0 0x3033056c 1 0x30330458>; }; /omit-if-no-ref/ iomuxc_ecspi2_miso_gpio_io_gpio5_io12: IOMUXC_ECSPI2_MISO_GPIO_IO_GPIO5_IO12 { pinmux = <0x303301f8 5 0x0 0 0x30330458>; }; /omit-if-no-ref/ iomuxc_ecspi2_miso_i2c_scl_i2c4_scl: IOMUXC_ECSPI2_MISO_I2C_SCL_I2C4_SCL { pinmux = <0x303301f8 2 0x303305bc 4 0x30330458>; }; /omit-if-no-ref/ iomuxc_ecspi2_miso_sai_mclk_sai7_mclk: IOMUXC_ECSPI2_MISO_SAI_MCLK_SAI7_MCLK { pinmux = <0x303301f8 3 0x3033052c 1 0x30330458>; }; /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_cts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_CTS_B_UART4_CTS_B { pinmux = <0x303301f8 1 0x0 0 0x30330458>; }; /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_rts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_RTS_B_UART4_CTS_B { pinmux = <0x303301f8 1 0x303305fc 2 0x30330458>; }; /omit-if-no-ref/ iomuxc_ecspi2_mosi_ecspi_mosi_ecspi2_mosi: IOMUXC_ECSPI2_MOSI_ECSPI_MOSI_ECSPI2_MOSI { pinmux = <0x303301f4 0 0x30330570 1 0x30330454>; }; /omit-if-no-ref/ iomuxc_ecspi2_mosi_gpio_io_gpio5_io11: IOMUXC_ECSPI2_MOSI_GPIO_IO_GPIO5_IO11 { pinmux = <0x303301f4 5 0x0 0 0x30330454>; }; /omit-if-no-ref/ iomuxc_ecspi2_mosi_i2c_sda_i2c3_sda: IOMUXC_ECSPI2_MOSI_I2C_SDA_I2C3_SDA { pinmux = <0x303301f4 2 0x303305b8 3 0x30330454>; }; /omit-if-no-ref/ iomuxc_ecspi2_mosi_sai_tx_data_sai7_tx_data0: IOMUXC_ECSPI2_MOSI_SAI_TX_DATA_SAI7_TX_DATA0 { pinmux = <0x303301f4 3 0x0 0 0x30330454>; }; /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_rx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_RX_UART4_TX { pinmux = <0x303301f4 1 0x30330600 7 0x30330454>; }; /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_tx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_TX_UART4_TX { pinmux = <0x303301f4 1 0x0 0 0x30330454>; }; /omit-if-no-ref/ iomuxc_ecspi2_sclk_ecspi_sclk_ecspi2_sclk: IOMUXC_ECSPI2_SCLK_ECSPI_SCLK_ECSPI2_SCLK { pinmux = <0x303301f0 0 0x30330568 1 0x30330450>; }; /omit-if-no-ref/ iomuxc_ecspi2_sclk_gpio_io_gpio5_io10: IOMUXC_ECSPI2_SCLK_GPIO_IO_GPIO5_IO10 { pinmux = <0x303301f0 5 0x0 0 0x30330450>; }; /omit-if-no-ref/ iomuxc_ecspi2_sclk_i2c_scl_i2c3_scl: IOMUXC_ECSPI2_SCLK_I2C_SCL_I2C3_SCL { pinmux = <0x303301f0 2 0x303305b4 3 0x30330450>; }; /omit-if-no-ref/ iomuxc_ecspi2_sclk_sai_tx_bclk_sai7_tx_bclk: IOMUXC_ECSPI2_SCLK_SAI_TX_BCLK_SAI7_TX_BCLK { pinmux = <0x303301f0 3 0x3033053c 1 0x30330450>; }; /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_rx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_RX_UART4_RX { pinmux = <0x303301f0 1 0x30330600 6 0x30330450>; }; /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_tx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_TX_UART4_RX { pinmux = <0x303301f0 1 0x0 0 0x30330450>; }; /omit-if-no-ref/ iomuxc_ecspi2_ss0_ccm_clko_ccm_clko2: IOMUXC_ECSPI2_SS0_CCM_CLKO_CCM_CLKO2 { pinmux = <0x303301fc 4 0x0 0 0x3033045c>; }; /omit-if-no-ref/ iomuxc_ecspi2_ss0_ecspi_ss_ecspi2_ss0: IOMUXC_ECSPI2_SS0_ECSPI_SS_ECSPI2_SS0 { pinmux = <0x303301fc 0 0x30330574 1 0x3033045c>; }; /omit-if-no-ref/ iomuxc_ecspi2_ss0_gpio_io_gpio5_io13: IOMUXC_ECSPI2_SS0_GPIO_IO_GPIO5_IO13 { pinmux = <0x303301fc 5 0x0 0 0x3033045c>; }; /omit-if-no-ref/ iomuxc_ecspi2_ss0_i2c_sda_i2c4_sda: IOMUXC_ECSPI2_SS0_I2C_SDA_I2C4_SDA { pinmux = <0x303301fc 2 0x303305c0 4 0x3033045c>; }; /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_cts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_CTS_B_UART4_RTS_B { pinmux = <0x303301fc 1 0x0 0 0x3033045c>; }; /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_rts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_RTS_B_UART4_RTS_B { pinmux = <0x303301fc 1 0x303305fc 3 0x3033045c>; }; /omit-if-no-ref/ iomuxc_enet_mdc_enet_qos_mdc_enet_qos_mdc: IOMUXC_ENET_MDC_ENET_QOS_MDC_ENET_QOS_MDC { pinmux = <0x30330054 0 0x0 0 0x303302b4>; }; /omit-if-no-ref/ iomuxc_enet_mdc_gpio_io_gpio1_io16: IOMUXC_ENET_MDC_GPIO_IO_GPIO1_IO16 { pinmux = <0x30330054 5 0x0 0 0x303302b4>; }; /omit-if-no-ref/ iomuxc_enet_mdc_sai_tx_data_sai6_tx_data0: IOMUXC_ENET_MDC_SAI_TX_DATA_SAI6_TX_DATA0 { pinmux = <0x30330054 2 0x0 0 0x303302b4>; }; /omit-if-no-ref/ iomuxc_enet_mdc_usdhc_strobe_usdhc3_strobe: IOMUXC_ENET_MDC_USDHC_STROBE_USDHC3_STROBE { pinmux = <0x30330054 6 0x30330630 0 0x303302b4>; }; /omit-if-no-ref/ iomuxc_enet_mdio_enet_qos_mdio_enet_qos_mdio: IOMUXC_ENET_MDIO_ENET_QOS_MDIO_ENET_QOS_MDIO { pinmux = <0x30330058 0 0x30330590 1 0x303302b8>; }; /omit-if-no-ref/ iomuxc_enet_mdio_gpio_io_gpio1_io17: IOMUXC_ENET_MDIO_GPIO_IO_GPIO1_IO17 { pinmux = <0x30330058 5 0x0 0 0x303302b8>; }; /omit-if-no-ref/ iomuxc_enet_mdio_pdm_bit_stream_pdm_bit_stream3: IOMUXC_ENET_MDIO_PDM_BIT_STREAM_PDM_BIT_STREAM3 { pinmux = <0x30330058 3 0x303304cc 0 0x303302b8>; }; /omit-if-no-ref/ iomuxc_enet_mdio_sai_tx_sync_sai6_tx_sync: IOMUXC_ENET_MDIO_SAI_TX_SYNC_SAI6_TX_SYNC { pinmux = <0x30330058 2 0x30330528 0 0x303302b8>; }; /omit-if-no-ref/ iomuxc_enet_mdio_usdhc_data_usdhc3_data5: IOMUXC_ENET_MDIO_USDHC_DATA_USDHC3_DATA5 { pinmux = <0x30330058 6 0x30330624 0 0x303302b8>; }; /omit-if-no-ref/ iomuxc_enet_rd0_enet_qos_rgmii_rd_enet_qos_rgmii_rd0: IOMUXC_ENET_RD0_ENET_QOS_RGMII_RD_ENET_QOS_RGMII_RD0 { pinmux = <0x3033007c 0 0x0 0 0x303302dc>; }; /omit-if-no-ref/ iomuxc_enet_rd0_gpio_io_gpio1_io26: IOMUXC_ENET_RD0_GPIO_IO_GPIO1_IO26 { pinmux = <0x3033007c 5 0x0 0 0x303302dc>; }; /omit-if-no-ref/ iomuxc_enet_rd0_pdm_bit_stream_pdm_bit_stream1: IOMUXC_ENET_RD0_PDM_BIT_STREAM_PDM_BIT_STREAM1 { pinmux = <0x3033007c 3 0x303304c4 1 0x303302dc>; }; /omit-if-no-ref/ iomuxc_enet_rd0_sai_rx_data_sai7_rx_data0: IOMUXC_ENET_RD0_SAI_RX_DATA_SAI7_RX_DATA0 { pinmux = <0x3033007c 2 0x30330534 0 0x303302dc>; }; /omit-if-no-ref/ iomuxc_enet_rd0_usdhc_data_usdhc3_data4: IOMUXC_ENET_RD0_USDHC_DATA_USDHC3_DATA4 { pinmux = <0x3033007c 6 0x30330620 0 0x303302dc>; }; /omit-if-no-ref/ iomuxc_enet_rd1_enet_qos_rgmii_rd_enet_qos_rgmii_rd1: IOMUXC_ENET_RD1_ENET_QOS_RGMII_RD_ENET_QOS_RGMII_RD1 { pinmux = <0x30330080 0 0x0 0 0x303302e0>; }; /omit-if-no-ref/ iomuxc_enet_rd1_gpio_io_gpio1_io27: IOMUXC_ENET_RD1_GPIO_IO_GPIO1_IO27 { pinmux = <0x30330080 5 0x0 0 0x303302e0>; }; /omit-if-no-ref/ iomuxc_enet_rd1_pdm_bit_stream_pdm_bit_stream0: IOMUXC_ENET_RD1_PDM_BIT_STREAM_PDM_BIT_STREAM0 { pinmux = <0x30330080 3 0x303304c0 1 0x303302e0>; }; /omit-if-no-ref/ iomuxc_enet_rd1_sai_rx_sync_sai7_rx_sync: IOMUXC_ENET_RD1_SAI_RX_SYNC_SAI7_RX_SYNC { pinmux = <0x30330080 2 0x30330538 0 0x303302e0>; }; /omit-if-no-ref/ iomuxc_enet_rd1_usdhc_reset_b_usdhc3_reset_b: IOMUXC_ENET_RD1_USDHC_RESET_B_USDHC3_RESET_B { pinmux = <0x30330080 6 0x0 0 0x303302e0>; }; /omit-if-no-ref/ iomuxc_enet_rd2_enet_qos_rgmii_rd_enet_qos_rgmii_rd2: IOMUXC_ENET_RD2_ENET_QOS_RGMII_RD_ENET_QOS_RGMII_RD2 { pinmux = <0x30330084 0 0x0 0 0x303302e4>; }; /omit-if-no-ref/ iomuxc_enet_rd2_gpio_io_gpio1_io28: IOMUXC_ENET_RD2_GPIO_IO_GPIO1_IO28 { pinmux = <0x30330084 5 0x0 0 0x303302e4>; }; /omit-if-no-ref/ iomuxc_enet_rd2_pdm_clk_pdm_clk: IOMUXC_ENET_RD2_PDM_CLK_PDM_CLK { pinmux = <0x30330084 3 0x0 0 0x303302e4>; }; /omit-if-no-ref/ iomuxc_enet_rd2_sai_rx_bclk_sai7_rx_bclk: IOMUXC_ENET_RD2_SAI_RX_BCLK_SAI7_RX_BCLK { pinmux = <0x30330084 2 0x30330530 0 0x303302e4>; }; /omit-if-no-ref/ iomuxc_enet_rd2_usdhc_clk_usdhc3_clk: IOMUXC_ENET_RD2_USDHC_CLK_USDHC3_CLK { pinmux = <0x30330084 6 0x30330604 0 0x303302e4>; }; /omit-if-no-ref/ iomuxc_enet_rd3_enet_qos_rgmii_rd_enet_qos_rgmii_rd3: IOMUXC_ENET_RD3_ENET_QOS_RGMII_RD_ENET_QOS_RGMII_RD3 { pinmux = <0x30330088 0 0x0 0 0x303302e8>; }; /omit-if-no-ref/ iomuxc_enet_rd3_gpio_io_gpio1_io29: IOMUXC_ENET_RD3_GPIO_IO_GPIO1_IO29 { pinmux = <0x30330088 5 0x0 0 0x303302e8>; }; /omit-if-no-ref/ iomuxc_enet_rd3_sai_mclk_sai7_mclk: IOMUXC_ENET_RD3_SAI_MCLK_SAI7_MCLK { pinmux = <0x30330088 2 0x3033052c 0 0x303302e8>; }; /omit-if-no-ref/ iomuxc_enet_rd3_spdif_in_spdif1_in: IOMUXC_ENET_RD3_SPDIF_IN_SPDIF1_IN { pinmux = <0x30330088 3 0x30330544 0 0x303302e8>; }; /omit-if-no-ref/ iomuxc_enet_rd3_usdhc_cmd_usdhc3_cmd: IOMUXC_ENET_RD3_USDHC_CMD_USDHC3_CMD { pinmux = <0x30330088 6 0x3033060c 0 0x303302e8>; }; /omit-if-no-ref/ iomuxc_enet_rxc_enet_qos_rgmii_rxc_enet_qos_rgmii_rxc: IOMUXC_ENET_RXC_ENET_QOS_RGMII_RXC_ENET_QOS_RGMII_RXC { pinmux = <0x30330078 0 0x0 0 0x303302d8>; }; /omit-if-no-ref/ iomuxc_enet_rxc_enet_qos_rx_er_enet_qos_rx_er: IOMUXC_ENET_RXC_ENET_QOS_RX_ER_ENET_QOS_RX_ER { pinmux = <0x30330078 1 0x0 0 0x303302d8>; }; /omit-if-no-ref/ iomuxc_enet_rxc_gpio_io_gpio1_io25: IOMUXC_ENET_RXC_GPIO_IO_GPIO1_IO25 { pinmux = <0x30330078 5 0x0 0 0x303302d8>; }; /omit-if-no-ref/ iomuxc_enet_rxc_pdm_bit_stream_pdm_bit_stream2: IOMUXC_ENET_RXC_PDM_BIT_STREAM_PDM_BIT_STREAM2 { pinmux = <0x30330078 3 0x303304c8 1 0x303302d8>; }; /omit-if-no-ref/ iomuxc_enet_rxc_sai_tx_bclk_sai7_tx_bclk: IOMUXC_ENET_RXC_SAI_TX_BCLK_SAI7_TX_BCLK { pinmux = <0x30330078 2 0x3033053c 0 0x303302d8>; }; /omit-if-no-ref/ iomuxc_enet_rxc_usdhc_data_usdhc3_data3: IOMUXC_ENET_RXC_USDHC_DATA_USDHC3_DATA3 { pinmux = <0x30330078 6 0x3033061c 0 0x303302d8>; }; /omit-if-no-ref/ iomuxc_enet_rx_ctl_enet_qos_rgmii_rx_ctl_enet_qos_rgmii_rx_ctl: IOMUXC_ENET_RX_CTL_ENET_QOS_RGMII_RX_CTL_ENET_QOS_RGMII_RX_CTL { pinmux = <0x30330074 0 0x0 0 0x303302d4>; }; /omit-if-no-ref/ iomuxc_enet_rx_ctl_gpio_io_gpio1_io24: IOMUXC_ENET_RX_CTL_GPIO_IO_GPIO1_IO24 { pinmux = <0x30330074 5 0x0 0 0x303302d4>; }; /omit-if-no-ref/ iomuxc_enet_rx_ctl_pdm_bit_stream_pdm_bit_stream3: IOMUXC_ENET_RX_CTL_PDM_BIT_STREAM_PDM_BIT_STREAM3 { pinmux = <0x30330074 3 0x303304cc 1 0x303302d4>; }; /omit-if-no-ref/ iomuxc_enet_rx_ctl_sai_tx_sync_sai7_tx_sync: IOMUXC_ENET_RX_CTL_SAI_TX_SYNC_SAI7_TX_SYNC { pinmux = <0x30330074 2 0x30330540 0 0x303302d4>; }; /omit-if-no-ref/ iomuxc_enet_rx_ctl_usdhc_data_usdhc3_data2: IOMUXC_ENET_RX_CTL_USDHC_DATA_USDHC3_DATA2 { pinmux = <0x30330074 6 0x30330618 0 0x303302d4>; }; /omit-if-no-ref/ iomuxc_enet_td0_enet_qos_rgmii_td_enet_qos_rgmii_td0: IOMUXC_ENET_TD0_ENET_QOS_RGMII_TD_ENET_QOS_RGMII_TD0 { pinmux = <0x30330068 0 0x0 0 0x303302c8>; }; /omit-if-no-ref/ iomuxc_enet_td0_gpio_io_gpio1_io21: IOMUXC_ENET_TD0_GPIO_IO_GPIO1_IO21 { pinmux = <0x30330068 5 0x0 0 0x303302c8>; }; /omit-if-no-ref/ iomuxc_enet_td0_pdm_clk_pdm_clk: IOMUXC_ENET_TD0_PDM_CLK_PDM_CLK { pinmux = <0x30330068 3 0x0 0 0x303302c8>; }; /omit-if-no-ref/ iomuxc_enet_td0_sai_rx_bclk_sai6_rx_bclk: IOMUXC_ENET_TD0_SAI_RX_BCLK_SAI6_RX_BCLK { pinmux = <0x30330068 2 0x30330518 0 0x303302c8>; }; /omit-if-no-ref/ iomuxc_enet_td0_usdhc_wp_usdhc3_wp: IOMUXC_ENET_TD0_USDHC_WP_USDHC3_WP { pinmux = <0x30330068 6 0x30330634 1 0x303302c8>; }; /omit-if-no-ref/ iomuxc_enet_td1_enet_qos_rgmii_td_enet_qos_rgmii_td1: IOMUXC_ENET_TD1_ENET_QOS_RGMII_TD_ENET_QOS_RGMII_TD1 { pinmux = <0x30330064 0 0x0 0 0x303302c4>; }; /omit-if-no-ref/ iomuxc_enet_td1_gpio_io_gpio1_io20: IOMUXC_ENET_TD1_GPIO_IO_GPIO1_IO20 { pinmux = <0x30330064 5 0x0 0 0x303302c4>; }; /omit-if-no-ref/ iomuxc_enet_td1_pdm_bit_stream_pdm_bit_stream0: IOMUXC_ENET_TD1_PDM_BIT_STREAM_PDM_BIT_STREAM0 { pinmux = <0x30330064 3 0x303304c0 0 0x303302c4>; }; /omit-if-no-ref/ iomuxc_enet_td1_sai_rx_sync_sai6_rx_sync: IOMUXC_ENET_TD1_SAI_RX_SYNC_SAI6_RX_SYNC { pinmux = <0x30330064 2 0x30330520 0 0x303302c4>; }; /omit-if-no-ref/ iomuxc_enet_td1_usdhc_cd_b_usdhc3_cd_b: IOMUXC_ENET_TD1_USDHC_CD_B_USDHC3_CD_B { pinmux = <0x30330064 6 0x30330608 1 0x303302c4>; }; /omit-if-no-ref/ iomuxc_enet_td2_enet_qos_rgmii_td_enet_qos_rgmii_td2: IOMUXC_ENET_TD2_ENET_QOS_RGMII_TD_ENET_QOS_RGMII_TD2 { pinmux = <0x30330060 0 0x0 0 0x303302c0>; }; /omit-if-no-ref/ iomuxc_enet_td2_enet_qos_tx_clk_enet_qos_tx_clk: IOMUXC_ENET_TD2_ENET_QOS_TX_CLK_ENET_QOS_TX_CLK { pinmux = <0x30330060 1 0x0 0 0x303302c0>; }; /omit-if-no-ref/ iomuxc_enet_td2_gpio_io_gpio1_io19: IOMUXC_ENET_TD2_GPIO_IO_GPIO1_IO19 { pinmux = <0x30330060 5 0x0 0 0x303302c0>; }; /omit-if-no-ref/ iomuxc_enet_td2_pdm_bit_stream_pdm_bit_stream1: IOMUXC_ENET_TD2_PDM_BIT_STREAM_PDM_BIT_STREAM1 { pinmux = <0x30330060 3 0x303304c4 0 0x303302c0>; }; /omit-if-no-ref/ iomuxc_enet_td2_sai_rx_data_sai6_rx_data0: IOMUXC_ENET_TD2_SAI_RX_DATA_SAI6_RX_DATA0 { pinmux = <0x30330060 2 0x3033051c 0 0x303302c0>; }; /omit-if-no-ref/ iomuxc_enet_td2_usdhc_data_usdhc3_data7: IOMUXC_ENET_TD2_USDHC_DATA_USDHC3_DATA7 { pinmux = <0x30330060 6 0x3033062c 0 0x303302c0>; }; /omit-if-no-ref/ iomuxc_enet_td3_enet_qos_rgmii_td_enet_qos_rgmii_td3: IOMUXC_ENET_TD3_ENET_QOS_RGMII_TD_ENET_QOS_RGMII_TD3 { pinmux = <0x3033005c 0 0x0 0 0x303302bc>; }; /omit-if-no-ref/ iomuxc_enet_td3_gpio_io_gpio1_io18: IOMUXC_ENET_TD3_GPIO_IO_GPIO1_IO18 { pinmux = <0x3033005c 5 0x0 0 0x303302bc>; }; /omit-if-no-ref/ iomuxc_enet_td3_pdm_bit_stream_pdm_bit_stream2: IOMUXC_ENET_TD3_PDM_BIT_STREAM_PDM_BIT_STREAM2 { pinmux = <0x3033005c 3 0x303304c8 0 0x303302bc>; }; /omit-if-no-ref/ iomuxc_enet_td3_sai_tx_bclk_sai6_tx_bclk: IOMUXC_ENET_TD3_SAI_TX_BCLK_SAI6_TX_BCLK { pinmux = <0x3033005c 2 0x30330524 0 0x303302bc>; }; /omit-if-no-ref/ iomuxc_enet_td3_usdhc_data_usdhc3_data6: IOMUXC_ENET_TD3_USDHC_DATA_USDHC3_DATA6 { pinmux = <0x3033005c 6 0x30330628 0 0x303302bc>; }; /omit-if-no-ref/ iomuxc_enet_txc_enet_qos_rgmii_txc_enet_qos_rgmii_txc: IOMUXC_ENET_TXC_ENET_QOS_RGMII_TXC_ENET_QOS_RGMII_TXC { pinmux = <0x30330070 0 0x0 0 0x303302d0>; }; /omit-if-no-ref/ iomuxc_enet_txc_enet_qos_tx_er_enet_qos_tx_er: IOMUXC_ENET_TXC_ENET_QOS_TX_ER_ENET_QOS_TX_ER { pinmux = <0x30330070 1 0x0 0 0x303302d0>; }; /omit-if-no-ref/ iomuxc_enet_txc_gpio_io_gpio1_io23: IOMUXC_ENET_TXC_GPIO_IO_GPIO1_IO23 { pinmux = <0x30330070 5 0x0 0 0x303302d0>; }; /omit-if-no-ref/ iomuxc_enet_txc_sai_tx_data_sai7_tx_data0: IOMUXC_ENET_TXC_SAI_TX_DATA_SAI7_TX_DATA0 { pinmux = <0x30330070 2 0x0 0 0x303302d0>; }; /omit-if-no-ref/ iomuxc_enet_txc_usdhc_data_usdhc3_data1: IOMUXC_ENET_TXC_USDHC_DATA_USDHC3_DATA1 { pinmux = <0x30330070 6 0x30330614 0 0x303302d0>; }; /omit-if-no-ref/ iomuxc_enet_tx_ctl_enet_qos_rgmii_tx_ctl_enet_qos_rgmii_tx_ctl: IOMUXC_ENET_TX_CTL_ENET_QOS_RGMII_TX_CTL_ENET_QOS_RGMII_TX_CTL { pinmux = <0x3033006c 0 0x0 0 0x303302cc>; }; /omit-if-no-ref/ iomuxc_enet_tx_ctl_gpio_io_gpio1_io22: IOMUXC_ENET_TX_CTL_GPIO_IO_GPIO1_IO22 { pinmux = <0x3033006c 5 0x0 0 0x303302cc>; }; /omit-if-no-ref/ iomuxc_enet_tx_ctl_sai_mclk_sai6_mclk: IOMUXC_ENET_TX_CTL_SAI_MCLK_SAI6_MCLK { pinmux = <0x3033006c 2 0x30330514 0 0x303302cc>; }; /omit-if-no-ref/ iomuxc_enet_tx_ctl_spdif_out_spdif1_out: IOMUXC_ENET_TX_CTL_SPDIF_OUT_SPDIF1_OUT { pinmux = <0x3033006c 3 0x0 0 0x303302cc>; }; /omit-if-no-ref/ iomuxc_enet_tx_ctl_usdhc_data_usdhc3_data0: IOMUXC_ENET_TX_CTL_USDHC_DATA_USDHC3_DATA0 { pinmux = <0x3033006c 6 0x30330610 0 0x303302cc>; }; /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_enet_phy_ref_clk_root_ccm_enet_phy_ref_clk_root: IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT_CCM_ENET_PHY_REF_CLK_ROOT { pinmux = <0x30330014 1 0x0 0 0x30330274>; }; /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_ext_clk_ccm_ext_clk1: IOMUXC_GPIO1_IO00_CCM_EXT_CLK_CCM_EXT_CLK1 { pinmux = <0x30330014 6 0x0 0 0x30330274>; }; /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_ref_clk_32k_ccm_ref_clk_32k: IOMUXC_GPIO1_IO00_CCM_REF_CLK_32K_CCM_REF_CLK_32K { pinmux = <0x30330014 5 0x0 0 0x30330274>; }; /omit-if-no-ref/ iomuxc_gpio1_io00_gpio_io_gpio1_io0: IOMUXC_GPIO1_IO00_GPIO_IO_GPIO1_IO0 { pinmux = <0x30330014 0 0x0 0 0x30330274>; }; /omit-if-no-ref/ iomuxc_gpio1_io00_isp_fl_trig_isp_fl_trig_0: IOMUXC_GPIO1_IO00_ISP_FL_TRIG_ISP_FL_TRIG_0 { pinmux = <0x30330014 3 0x303305d4 0 0x30330274>; }; /omit-if-no-ref/ iomuxc_gpio1_io01_ccm_ext_clk_ccm_ext_clk2: IOMUXC_GPIO1_IO01_CCM_EXT_CLK_CCM_EXT_CLK2 { pinmux = <0x30330018 6 0x0 0 0x30330278>; }; /omit-if-no-ref/ iomuxc_gpio1_io01_ccm_ref_clk_24m_ccm_ref_clk_24m: IOMUXC_GPIO1_IO01_CCM_REF_CLK_24M_CCM_REF_CLK_24M { pinmux = <0x30330018 5 0x0 0 0x30330278>; }; /omit-if-no-ref/ iomuxc_gpio1_io01_gpio_io_gpio1_io1: IOMUXC_GPIO1_IO01_GPIO_IO_GPIO1_IO1 { pinmux = <0x30330018 0 0x0 0 0x30330278>; }; /omit-if-no-ref/ iomuxc_gpio1_io01_isp_shutter_trig_isp_shutter_trig_0: IOMUXC_GPIO1_IO01_ISP_SHUTTER_TRIG_ISP_SHUTTER_TRIG_0 { pinmux = <0x30330018 3 0x303305dc 0 0x30330278>; }; /omit-if-no-ref/ iomuxc_gpio1_io01_pwm_out_pwm1_out: IOMUXC_GPIO1_IO01_PWM_OUT_PWM1_OUT { pinmux = <0x30330018 1 0x0 0 0x30330278>; }; /omit-if-no-ref/ iomuxc_gpio1_io02_gpio_io_gpio1_io2: IOMUXC_GPIO1_IO02_GPIO_IO_GPIO1_IO2 { pinmux = <0x3033001c 0 0x0 0 0x3033027c>; }; /omit-if-no-ref/ iomuxc_gpio1_io02_isp_flash_trig_isp_flash_trig_0: IOMUXC_GPIO1_IO02_ISP_FLASH_TRIG_ISP_FLASH_TRIG_0 { pinmux = <0x3033001c 3 0x0 0 0x3033027c>; }; /omit-if-no-ref/ iomuxc_gpio1_io02_sjc_de_b_sjc_de_b: IOMUXC_GPIO1_IO02_SJC_DE_B_SJC_DE_B { pinmux = <0x3033001c 7 0x0 0 0x3033027c>; }; /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_any_wdog1_wdog_any: IOMUXC_GPIO1_IO02_WDOG_WDOG_ANY_WDOG1_WDOG_ANY { pinmux = <0x3033001c 5 0x0 0 0x3033027c>; }; /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_b_wdog1_wdog_b: IOMUXC_GPIO1_IO02_WDOG_WDOG_B_WDOG1_WDOG_B { pinmux = <0x3033001c 1 0x0 0 0x3033027c>; }; /omit-if-no-ref/ iomuxc_gpio1_io03_gpio_io_gpio1_io3: IOMUXC_GPIO1_IO03_GPIO_IO_GPIO1_IO3 { pinmux = <0x30330020 0 0x0 0 0x30330280>; }; /omit-if-no-ref/ iomuxc_gpio1_io03_isp_prelight_trig_isp_prelight_trig_0: IOMUXC_GPIO1_IO03_ISP_PRELIGHT_TRIG_ISP_PRELIGHT_TRIG_0 { pinmux = <0x30330020 3 0x0 0 0x30330280>; }; /omit-if-no-ref/ iomuxc_gpio1_io03_sdma_ext_event_sdma1_ext_event0: IOMUXC_GPIO1_IO03_SDMA_EXT_EVENT_SDMA1_EXT_EVENT0 { pinmux = <0x30330020 5 0x0 0 0x30330280>; }; /omit-if-no-ref/ iomuxc_gpio1_io03_usdhc_vselect_usdhc1_vselect: IOMUXC_GPIO1_IO03_USDHC_VSELECT_USDHC1_VSELECT { pinmux = <0x30330020 1 0x0 0 0x30330280>; }; /omit-if-no-ref/ iomuxc_gpio1_io04_gpio_io_gpio1_io4: IOMUXC_GPIO1_IO04_GPIO_IO_GPIO1_IO4 { pinmux = <0x30330024 0 0x0 0 0x30330284>; }; /omit-if-no-ref/ iomuxc_gpio1_io04_isp_shutter_open_isp_shutter_open_0: IOMUXC_GPIO1_IO04_ISP_SHUTTER_OPEN_ISP_SHUTTER_OPEN_0 { pinmux = <0x30330024 3 0x0 0 0x30330284>; }; /omit-if-no-ref/ iomuxc_gpio1_io04_sdma_ext_event_sdma1_ext_event1: IOMUXC_GPIO1_IO04_SDMA_EXT_EVENT_SDMA1_EXT_EVENT1 { pinmux = <0x30330024 5 0x0 0 0x30330284>; }; /omit-if-no-ref/ iomuxc_gpio1_io04_usdhc_vselect_usdhc2_vselect: IOMUXC_GPIO1_IO04_USDHC_VSELECT_USDHC2_VSELECT { pinmux = <0x30330024 1 0x0 0 0x30330284>; }; /omit-if-no-ref/ iomuxc_gpio1_io05_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO05_CCM_PMIC_READY_CCM_PMIC_READY { pinmux = <0x30330028 5 0x30330554 0 0x30330288>; }; /omit-if-no-ref/ iomuxc_gpio1_io05_gpio_io_gpio1_io5: IOMUXC_GPIO1_IO05_GPIO_IO_GPIO1_IO5 { pinmux = <0x30330028 0 0x0 0 0x30330288>; }; /omit-if-no-ref/ iomuxc_gpio1_io05_isp_fl_trig_isp_fl_trig_1: IOMUXC_GPIO1_IO05_ISP_FL_TRIG_ISP_FL_TRIG_1 { pinmux = <0x30330028 3 0x303305d8 0 0x30330288>; }; /omit-if-no-ref/ iomuxc_gpio1_io05_m7_nmi_m7_nmi: IOMUXC_GPIO1_IO05_M7_NMI_M7_NMI { pinmux = <0x30330028 1 0x0 0 0x30330288>; }; /omit-if-no-ref/ iomuxc_gpio1_io06_ccm_ext_clk_ccm_ext_clk3: IOMUXC_GPIO1_IO06_CCM_EXT_CLK_CCM_EXT_CLK3 { pinmux = <0x3033002c 6 0x0 0 0x3033028c>; }; /omit-if-no-ref/ iomuxc_gpio1_io06_enet_qos_mdc_enet_qos_mdc: IOMUXC_GPIO1_IO06_ENET_QOS_MDC_ENET_QOS_MDC { pinmux = <0x3033002c 1 0x0 0 0x3033028c>; }; /omit-if-no-ref/ iomuxc_gpio1_io06_gpio_io_gpio1_io6: IOMUXC_GPIO1_IO06_GPIO_IO_GPIO1_IO6 { pinmux = <0x3033002c 0 0x0 0 0x3033028c>; }; /omit-if-no-ref/ iomuxc_gpio1_io06_isp_shutter_trig_isp_shutter_trig_1: IOMUXC_GPIO1_IO06_ISP_SHUTTER_TRIG_ISP_SHUTTER_TRIG_1 { pinmux = <0x3033002c 3 0x303305e0 0 0x3033028c>; }; /omit-if-no-ref/ iomuxc_gpio1_io06_usdhc_cd_b_usdhc1_cd_b: IOMUXC_GPIO1_IO06_USDHC_CD_B_USDHC1_CD_B { pinmux = <0x3033002c 5 0x0 0 0x3033028c>; }; /omit-if-no-ref/ iomuxc_gpio1_io07_ccm_ext_clk_ccm_ext_clk4: IOMUXC_GPIO1_IO07_CCM_EXT_CLK_CCM_EXT_CLK4 { pinmux = <0x30330030 6 0x0 0 0x30330290>; }; /omit-if-no-ref/ iomuxc_gpio1_io07_enet_qos_mdio_enet_qos_mdio: IOMUXC_GPIO1_IO07_ENET_QOS_MDIO_ENET_QOS_MDIO { pinmux = <0x30330030 1 0x30330590 0 0x30330290>; }; /omit-if-no-ref/ iomuxc_gpio1_io07_gpio_io_gpio1_io7: IOMUXC_GPIO1_IO07_GPIO_IO_GPIO1_IO7 { pinmux = <0x30330030 0 0x0 0 0x30330290>; }; /omit-if-no-ref/ iomuxc_gpio1_io07_isp_flash_trig_isp_flash_trig_1: IOMUXC_GPIO1_IO07_ISP_FLASH_TRIG_ISP_FLASH_TRIG_1 { pinmux = <0x30330030 3 0x0 0 0x30330290>; }; /omit-if-no-ref/ iomuxc_gpio1_io07_usdhc_wp_usdhc1_wp: IOMUXC_GPIO1_IO07_USDHC_WP_USDHC1_WP { pinmux = <0x30330030 5 0x0 0 0x30330290>; }; /omit-if-no-ref/ iomuxc_gpio1_io08_enet_qos_1588_event0_aux_in_enet_qos_1588_event0_aux_in: IOMUXC_GPIO1_IO08_ENET_QOS_1588_EVENT0_AUX_IN_ENET_QOS_1588_EVENT0_AUX_IN { pinmux = <0x30330034 4 0x0 0 0x30330294>; }; /omit-if-no-ref/ iomuxc_gpio1_io08_enet_qos_1588_event0_in_enet_qos_1588_event0_in: IOMUXC_GPIO1_IO08_ENET_QOS_1588_EVENT0_IN_ENET_QOS_1588_EVENT0_IN { pinmux = <0x30330034 1 0x0 0 0x30330294>; }; /omit-if-no-ref/ iomuxc_gpio1_io08_gpio_io_gpio1_io8: IOMUXC_GPIO1_IO08_GPIO_IO_GPIO1_IO8 { pinmux = <0x30330034 0 0x0 0 0x30330294>; }; /omit-if-no-ref/ iomuxc_gpio1_io08_isp_prelight_trig_isp_prelight_trig_1: IOMUXC_GPIO1_IO08_ISP_PRELIGHT_TRIG_ISP_PRELIGHT_TRIG_1 { pinmux = <0x30330034 3 0x0 0 0x30330294>; }; /omit-if-no-ref/ iomuxc_gpio1_io08_pwm_out_pwm1_out: IOMUXC_GPIO1_IO08_PWM_OUT_PWM1_OUT { pinmux = <0x30330034 2 0x0 0 0x30330294>; }; /omit-if-no-ref/ iomuxc_gpio1_io08_usdhc_reset_b_usdhc2_reset_b: IOMUXC_GPIO1_IO08_USDHC_RESET_B_USDHC2_RESET_B { pinmux = <0x30330034 5 0x0 0 0x30330294>; }; /omit-if-no-ref/ iomuxc_gpio1_io09_enet_qos_1588_event0_out_enet_qos_1588_event0_out: IOMUXC_GPIO1_IO09_ENET_QOS_1588_EVENT0_OUT_ENET_QOS_1588_EVENT0_OUT { pinmux = <0x30330038 1 0x0 0 0x30330298>; }; /omit-if-no-ref/ iomuxc_gpio1_io09_gpio_io_gpio1_io9: IOMUXC_GPIO1_IO09_GPIO_IO_GPIO1_IO9 { pinmux = <0x30330038 0 0x0 0 0x30330298>; }; /omit-if-no-ref/ iomuxc_gpio1_io09_isp_shutter_open_isp_shutter_open_1: IOMUXC_GPIO1_IO09_ISP_SHUTTER_OPEN_ISP_SHUTTER_OPEN_1 { pinmux = <0x30330038 3 0x0 0 0x30330298>; }; /omit-if-no-ref/ iomuxc_gpio1_io09_pwm_out_pwm2_out: IOMUXC_GPIO1_IO09_PWM_OUT_PWM2_OUT { pinmux = <0x30330038 2 0x0 0 0x30330298>; }; /omit-if-no-ref/ iomuxc_gpio1_io09_sdma_ext_event_sdma2_ext_event0: IOMUXC_GPIO1_IO09_SDMA_EXT_EVENT_SDMA2_EXT_EVENT0 { pinmux = <0x30330038 5 0x0 0 0x30330298>; }; /omit-if-no-ref/ iomuxc_gpio1_io09_usdhc_reset_b_usdhc3_reset_b: IOMUXC_GPIO1_IO09_USDHC_RESET_B_USDHC3_RESET_B { pinmux = <0x30330038 4 0x0 0 0x30330298>; }; /omit-if-no-ref/ iomuxc_gpio1_io10_gpio_io_gpio1_io10: IOMUXC_GPIO1_IO10_GPIO_IO_GPIO1_IO10 { pinmux = <0x3033003c 0 0x0 0 0x3033029c>; }; /omit-if-no-ref/ iomuxc_gpio1_io10_pwm_out_pwm3_out: IOMUXC_GPIO1_IO10_PWM_OUT_PWM3_OUT { pinmux = <0x3033003c 2 0x0 0 0x3033029c>; }; /omit-if-no-ref/ iomuxc_gpio1_io10_usb_id_usb1_id: IOMUXC_GPIO1_IO10_USB_ID_USB1_ID { pinmux = <0x3033003c 1 0x0 0 0x3033029c>; }; /omit-if-no-ref/ iomuxc_gpio1_io11_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO11_CCM_PMIC_READY_CCM_PMIC_READY { pinmux = <0x30330040 5 0x30330554 1 0x303302a0>; }; /omit-if-no-ref/ iomuxc_gpio1_io11_gpio_io_gpio1_io11: IOMUXC_GPIO1_IO11_GPIO_IO_GPIO1_IO11 { pinmux = <0x30330040 0 0x0 0 0x303302a0>; }; /omit-if-no-ref/ iomuxc_gpio1_io11_pwm_out_pwm2_out: IOMUXC_GPIO1_IO11_PWM_OUT_PWM2_OUT { pinmux = <0x30330040 2 0x0 0 0x303302a0>; }; /omit-if-no-ref/ iomuxc_gpio1_io11_usb_id_usb2_id: IOMUXC_GPIO1_IO11_USB_ID_USB2_ID { pinmux = <0x30330040 1 0x0 0 0x303302a0>; }; /omit-if-no-ref/ iomuxc_gpio1_io11_usdhc_vselect_usdhc3_vselect: IOMUXC_GPIO1_IO11_USDHC_VSELECT_USDHC3_VSELECT { pinmux = <0x30330040 4 0x0 0 0x303302a0>; }; /omit-if-no-ref/ iomuxc_gpio1_io12_gpio_io_gpio1_io12: IOMUXC_GPIO1_IO12_GPIO_IO_GPIO1_IO12 { pinmux = <0x30330044 0 0x0 0 0x303302a4>; }; /omit-if-no-ref/ iomuxc_gpio1_io12_sdma_ext_event_sdma2_ext_event1: IOMUXC_GPIO1_IO12_SDMA_EXT_EVENT_SDMA2_EXT_EVENT1 { pinmux = <0x30330044 5 0x0 0 0x303302a4>; }; /omit-if-no-ref/ iomuxc_gpio1_io12_usb_pwr_usb1_pwr: IOMUXC_GPIO1_IO12_USB_PWR_USB1_PWR { pinmux = <0x30330044 1 0x0 0 0x303302a4>; }; /omit-if-no-ref/ iomuxc_gpio1_io13_gpio_io_gpio1_io13: IOMUXC_GPIO1_IO13_GPIO_IO_GPIO1_IO13 { pinmux = <0x30330048 0 0x0 0 0x303302a8>; }; /omit-if-no-ref/ iomuxc_gpio1_io13_pwm_out_pwm2_out: IOMUXC_GPIO1_IO13_PWM_OUT_PWM2_OUT { pinmux = <0x30330048 5 0x0 0 0x303302a8>; }; /omit-if-no-ref/ iomuxc_gpio1_io13_usb_oc_usb1_oc: IOMUXC_GPIO1_IO13_USB_OC_USB1_OC { pinmux = <0x30330048 1 0x0 0 0x303302a8>; }; /omit-if-no-ref/ iomuxc_gpio1_io14_ccm_clko_ccm_clko1: IOMUXC_GPIO1_IO14_CCM_CLKO_CCM_CLKO1 { pinmux = <0x3033004c 6 0x0 0 0x303302ac>; }; /omit-if-no-ref/ iomuxc_gpio1_io14_gpio_io_gpio1_io14: IOMUXC_GPIO1_IO14_GPIO_IO_GPIO1_IO14 { pinmux = <0x3033004c 0 0x0 0 0x303302ac>; }; /omit-if-no-ref/ iomuxc_gpio1_io14_pwm_out_pwm3_out: IOMUXC_GPIO1_IO14_PWM_OUT_PWM3_OUT { pinmux = <0x3033004c 5 0x0 0 0x303302ac>; }; /omit-if-no-ref/ iomuxc_gpio1_io14_usb_pwr_usb2_pwr: IOMUXC_GPIO1_IO14_USB_PWR_USB2_PWR { pinmux = <0x3033004c 1 0x0 0 0x303302ac>; }; /omit-if-no-ref/ iomuxc_gpio1_io14_usdhc_cd_b_usdhc3_cd_b: IOMUXC_GPIO1_IO14_USDHC_CD_B_USDHC3_CD_B { pinmux = <0x3033004c 4 0x30330608 0 0x303302ac>; }; /omit-if-no-ref/ iomuxc_gpio1_io15_ccm_clko_ccm_clko2: IOMUXC_GPIO1_IO15_CCM_CLKO_CCM_CLKO2 { pinmux = <0x30330050 6 0x0 0 0x303302b0>; }; /omit-if-no-ref/ iomuxc_gpio1_io15_gpio_io_gpio1_io15: IOMUXC_GPIO1_IO15_GPIO_IO_GPIO1_IO15 { pinmux = <0x30330050 0 0x0 0 0x303302b0>; }; /omit-if-no-ref/ iomuxc_gpio1_io15_pwm_out_pwm4_out: IOMUXC_GPIO1_IO15_PWM_OUT_PWM4_OUT { pinmux = <0x30330050 5 0x0 0 0x303302b0>; }; /omit-if-no-ref/ iomuxc_gpio1_io15_usb_oc_usb2_oc: IOMUXC_GPIO1_IO15_USB_OC_USB2_OC { pinmux = <0x30330050 1 0x0 0 0x303302b0>; }; /omit-if-no-ref/ iomuxc_gpio1_io15_usdhc_wp_usdhc3_wp: IOMUXC_GPIO1_IO15_USDHC_WP_USDHC3_WP { pinmux = <0x30330050 4 0x30330634 0 0x303302b0>; }; /omit-if-no-ref/ iomuxc_hdmi_cec_can_tx_can2_tx: IOMUXC_HDMI_CEC_CAN_TX_CAN2_TX { pinmux = <0x30330248 4 0x0 0 0x303304a8>; }; /omit-if-no-ref/ iomuxc_hdmi_cec_gpio_io_gpio3_io28: IOMUXC_HDMI_CEC_GPIO_IO_GPIO3_IO28 { pinmux = <0x30330248 5 0x0 0 0x303304a8>; }; /omit-if-no-ref/ iomuxc_hdmi_cec_hdmi_cec_hdmi_cec: IOMUXC_HDMI_CEC_HDMI_CEC_HDMI_CEC { pinmux = <0x30330248 0 0x0 0 0x303304a8>; }; /omit-if-no-ref/ iomuxc_hdmi_cec_i2c_scl_i2c6_scl: IOMUXC_HDMI_CEC_I2C_SCL_I2C6_SCL { pinmux = <0x30330248 3 0x303305cc 3 0x303304a8>; }; /omit-if-no-ref/ iomuxc_hdmi_ddc_scl_can_tx_can1_tx: IOMUXC_HDMI_DDC_SCL_CAN_TX_CAN1_TX { pinmux = <0x30330240 4 0x0 0 0x303304a0>; }; /omit-if-no-ref/ iomuxc_hdmi_ddc_scl_gpio_io_gpio3_io26: IOMUXC_HDMI_DDC_SCL_GPIO_IO_GPIO3_IO26 { pinmux = <0x30330240 5 0x0 0 0x303304a0>; }; /omit-if-no-ref/ iomuxc_hdmi_ddc_scl_hdmi_scl_hdmi_scl: IOMUXC_HDMI_DDC_SCL_HDMI_SCL_HDMI_SCL { pinmux = <0x30330240 0 0x0 0 0x303304a0>; }; /omit-if-no-ref/ iomuxc_hdmi_ddc_scl_i2c_scl_i2c5_scl: IOMUXC_HDMI_DDC_SCL_I2C_SCL_I2C5_SCL { pinmux = <0x30330240 3 0x303305c4 3 0x303304a0>; }; /omit-if-no-ref/ iomuxc_hdmi_ddc_sda_can_rx_can1_rx: IOMUXC_HDMI_DDC_SDA_CAN_RX_CAN1_RX { pinmux = <0x30330244 4 0x3033054c 3 0x303304a4>; }; /omit-if-no-ref/ iomuxc_hdmi_ddc_sda_gpio_io_gpio3_io27: IOMUXC_HDMI_DDC_SDA_GPIO_IO_GPIO3_IO27 { pinmux = <0x30330244 5 0x0 0 0x303304a4>; }; /omit-if-no-ref/ iomuxc_hdmi_ddc_sda_hdmi_sda_hdmi_sda: IOMUXC_HDMI_DDC_SDA_HDMI_SDA_HDMI_SDA { pinmux = <0x30330244 0 0x0 0 0x303304a4>; }; /omit-if-no-ref/ iomuxc_hdmi_ddc_sda_i2c_sda_i2c5_sda: IOMUXC_HDMI_DDC_SDA_I2C_SDA_I2C5_SDA { pinmux = <0x30330244 3 0x303305c8 3 0x303304a4>; }; /omit-if-no-ref/ iomuxc_hdmi_hpd_can_rx_can2_rx: IOMUXC_HDMI_HPD_CAN_RX_CAN2_RX { pinmux = <0x3033024c 4 0x30330550 3 0x303304ac>; }; /omit-if-no-ref/ iomuxc_hdmi_hpd_gpio_io_gpio3_io29: IOMUXC_HDMI_HPD_GPIO_IO_GPIO3_IO29 { pinmux = <0x3033024c 5 0x0 0 0x303304ac>; }; /omit-if-no-ref/ iomuxc_hdmi_hpd_hdmi_hpd_hdmi_hpd: IOMUXC_HDMI_HPD_HDMI_HPD_HDMI_HPD { pinmux = <0x3033024c 0 0x0 0 0x303304ac>; }; /omit-if-no-ref/ iomuxc_hdmi_hpd_hdmi_hpd_o_hdmi_hpd_o: IOMUXC_HDMI_HPD_HDMI_HPD_O_HDMI_HPD_O { pinmux = <0x3033024c 1 0x0 0 0x303304ac>; }; /omit-if-no-ref/ iomuxc_hdmi_hpd_i2c_sda_i2c6_sda: IOMUXC_HDMI_HPD_I2C_SDA_I2C6_SDA { pinmux = <0x3033024c 3 0x303305d0 3 0x303304ac>; }; /omit-if-no-ref/ iomuxc_i2c1_scl_ecspi_sclk_ecspi1_sclk: IOMUXC_I2C1_SCL_ECSPI_SCLK_ECSPI1_SCLK { pinmux = <0x30330200 3 0x30330558 1 0x30330460>; }; /omit-if-no-ref/ iomuxc_i2c1_scl_enet_qos_mdc_enet_qos_mdc: IOMUXC_I2C1_SCL_ENET_QOS_MDC_ENET_QOS_MDC { pinmux = <0x30330200 1 0x0 0 0x30330460>; }; /omit-if-no-ref/ iomuxc_i2c1_scl_gpio_io_gpio5_io14: IOMUXC_I2C1_SCL_GPIO_IO_GPIO5_IO14 { pinmux = <0x30330200 5 0x0 0 0x30330460>; }; /omit-if-no-ref/ iomuxc_i2c1_scl_i2c_scl_i2c1_scl: IOMUXC_I2C1_SCL_I2C_SCL_I2C1_SCL { pinmux = <0x30330200 0 0x303305a4 2 0x30330460>; }; /omit-if-no-ref/ iomuxc_i2c1_sda_ecspi_mosi_ecspi1_mosi: IOMUXC_I2C1_SDA_ECSPI_MOSI_ECSPI1_MOSI { pinmux = <0x30330204 3 0x30330560 1 0x30330464>; }; /omit-if-no-ref/ iomuxc_i2c1_sda_enet_qos_mdio_enet_qos_mdio: IOMUXC_I2C1_SDA_ENET_QOS_MDIO_ENET_QOS_MDIO { pinmux = <0x30330204 1 0x30330590 2 0x30330464>; }; /omit-if-no-ref/ iomuxc_i2c1_sda_gpio_io_gpio5_io15: IOMUXC_I2C1_SDA_GPIO_IO_GPIO5_IO15 { pinmux = <0x30330204 5 0x0 0 0x30330464>; }; /omit-if-no-ref/ iomuxc_i2c1_sda_i2c_sda_i2c1_sda: IOMUXC_I2C1_SDA_I2C_SDA_I2C1_SDA { pinmux = <0x30330204 0 0x303305a8 2 0x30330464>; }; /omit-if-no-ref/ iomuxc_i2c2_scl_ecspi_miso_ecspi1_miso: IOMUXC_I2C2_SCL_ECSPI_MISO_ECSPI1_MISO { pinmux = <0x30330208 3 0x3033055c 1 0x30330468>; }; /omit-if-no-ref/ iomuxc_i2c2_scl_enet_qos_1588_event1_aux_in_enet_qos_1588_event1_aux_in: IOMUXC_I2C2_SCL_ENET_QOS_1588_EVENT1_AUX_IN_ENET_QOS_1588_EVENT1_AUX_IN { pinmux = <0x30330208 4 0x0 0 0x30330468>; }; /omit-if-no-ref/ iomuxc_i2c2_scl_enet_qos_1588_event1_in_enet_qos_1588_event1_in: IOMUXC_I2C2_SCL_ENET_QOS_1588_EVENT1_IN_ENET_QOS_1588_EVENT1_IN { pinmux = <0x30330208 1 0x0 0 0x30330468>; }; /omit-if-no-ref/ iomuxc_i2c2_scl_gpio_io_gpio5_io16: IOMUXC_I2C2_SCL_GPIO_IO_GPIO5_IO16 { pinmux = <0x30330208 5 0x0 0 0x30330468>; }; /omit-if-no-ref/ iomuxc_i2c2_scl_i2c_scl_i2c2_scl: IOMUXC_I2C2_SCL_I2C_SCL_I2C2_SCL { pinmux = <0x30330208 0 0x303305ac 2 0x30330468>; }; /omit-if-no-ref/ iomuxc_i2c2_scl_usdhc_cd_b_usdhc3_cd_b: IOMUXC_I2C2_SCL_USDHC_CD_B_USDHC3_CD_B { pinmux = <0x30330208 2 0x30330608 3 0x30330468>; }; /omit-if-no-ref/ iomuxc_i2c2_sda_ecspi_ss_ecspi1_ss0: IOMUXC_I2C2_SDA_ECSPI_SS_ECSPI1_SS0 { pinmux = <0x3033020c 3 0x30330564 1 0x3033046c>; }; /omit-if-no-ref/ iomuxc_i2c2_sda_enet_qos_1588_event1_out_enet_qos_1588_event1_out: IOMUXC_I2C2_SDA_ENET_QOS_1588_EVENT1_OUT_ENET_QOS_1588_EVENT1_OUT { pinmux = <0x3033020c 1 0x0 0 0x3033046c>; }; /omit-if-no-ref/ iomuxc_i2c2_sda_gpio_io_gpio5_io17: IOMUXC_I2C2_SDA_GPIO_IO_GPIO5_IO17 { pinmux = <0x3033020c 5 0x0 0 0x3033046c>; }; /omit-if-no-ref/ iomuxc_i2c2_sda_i2c_sda_i2c2_sda: IOMUXC_I2C2_SDA_I2C_SDA_I2C2_SDA { pinmux = <0x3033020c 0 0x303305b0 2 0x3033046c>; }; /omit-if-no-ref/ iomuxc_i2c2_sda_usdhc_wp_usdhc3_wp: IOMUXC_I2C2_SDA_USDHC_WP_USDHC3_WP { pinmux = <0x3033020c 2 0x30330634 3 0x3033046c>; }; /omit-if-no-ref/ iomuxc_i2c3_scl_ecspi_sclk_ecspi2_sclk: IOMUXC_I2C3_SCL_ECSPI_SCLK_ECSPI2_SCLK { pinmux = <0x30330210 3 0x30330568 2 0x30330470>; }; /omit-if-no-ref/ iomuxc_i2c3_scl_gpio_io_gpio5_io18: IOMUXC_I2C3_SCL_GPIO_IO_GPIO5_IO18 { pinmux = <0x30330210 5 0x0 0 0x30330470>; }; /omit-if-no-ref/ iomuxc_i2c3_scl_gpt_clk_gpt2_clk: IOMUXC_I2C3_SCL_GPT_CLK_GPT2_CLK { pinmux = <0x30330210 2 0x0 0 0x30330470>; }; /omit-if-no-ref/ iomuxc_i2c3_scl_i2c_scl_i2c3_scl: IOMUXC_I2C3_SCL_I2C_SCL_I2C3_SCL { pinmux = <0x30330210 0 0x303305b4 4 0x30330470>; }; /omit-if-no-ref/ iomuxc_i2c3_scl_pwm_out_pwm4_out: IOMUXC_I2C3_SCL_PWM_OUT_PWM4_OUT { pinmux = <0x30330210 1 0x0 0 0x30330470>; }; /omit-if-no-ref/ iomuxc_i2c3_sda_ecspi_mosi_ecspi2_mosi: IOMUXC_I2C3_SDA_ECSPI_MOSI_ECSPI2_MOSI { pinmux = <0x30330214 3 0x30330570 2 0x30330474>; }; /omit-if-no-ref/ iomuxc_i2c3_sda_gpio_io_gpio5_io19: IOMUXC_I2C3_SDA_GPIO_IO_GPIO5_IO19 { pinmux = <0x30330214 5 0x0 0 0x30330474>; }; /omit-if-no-ref/ iomuxc_i2c3_sda_gpt_clk_gpt3_clk: IOMUXC_I2C3_SDA_GPT_CLK_GPT3_CLK { pinmux = <0x30330214 2 0x0 0 0x30330474>; }; /omit-if-no-ref/ iomuxc_i2c3_sda_i2c_sda_i2c3_sda: IOMUXC_I2C3_SDA_I2C_SDA_I2C3_SDA { pinmux = <0x30330214 0 0x303305b8 4 0x30330474>; }; /omit-if-no-ref/ iomuxc_i2c3_sda_pwm_out_pwm3_out: IOMUXC_I2C3_SDA_PWM_OUT_PWM3_OUT { pinmux = <0x30330214 1 0x0 0 0x30330474>; }; /omit-if-no-ref/ iomuxc_i2c4_scl_ecspi_miso_ecspi2_miso: IOMUXC_I2C4_SCL_ECSPI_MISO_ECSPI2_MISO { pinmux = <0x30330218 3 0x3033056c 2 0x30330478>; }; /omit-if-no-ref/ iomuxc_i2c4_scl_gpio_io_gpio5_io20: IOMUXC_I2C4_SCL_GPIO_IO_GPIO5_IO20 { pinmux = <0x30330218 5 0x0 0 0x30330478>; }; /omit-if-no-ref/ iomuxc_i2c4_scl_i2c_scl_i2c4_scl: IOMUXC_I2C4_SCL_I2C_SCL_I2C4_SCL { pinmux = <0x30330218 0 0x303305bc 5 0x30330478>; }; /omit-if-no-ref/ iomuxc_i2c4_scl_pcie_clkreq_b_pcie1_clkreq_b: IOMUXC_I2C4_SCL_PCIE_CLKREQ_B_PCIE1_CLKREQ_B { pinmux = <0x30330218 2 0x303305a0 0 0x30330478>; }; /omit-if-no-ref/ iomuxc_i2c4_scl_pwm_out_pwm2_out: IOMUXC_I2C4_SCL_PWM_OUT_PWM2_OUT { pinmux = <0x30330218 1 0x0 0 0x30330478>; }; /omit-if-no-ref/ iomuxc_i2c4_sda_ecspi_ss_ecspi2_ss0: IOMUXC_I2C4_SDA_ECSPI_SS_ECSPI2_SS0 { pinmux = <0x3033021c 3 0x30330574 2 0x3033047c>; }; /omit-if-no-ref/ iomuxc_i2c4_sda_gpio_io_gpio5_io21: IOMUXC_I2C4_SDA_GPIO_IO_GPIO5_IO21 { pinmux = <0x3033021c 5 0x0 0 0x3033047c>; }; /omit-if-no-ref/ iomuxc_i2c4_sda_i2c_sda_i2c4_sda: IOMUXC_I2C4_SDA_I2C_SDA_I2C4_SDA { pinmux = <0x3033021c 0 0x303305c0 5 0x3033047c>; }; /omit-if-no-ref/ iomuxc_i2c4_sda_pwm_out_pwm1_out: IOMUXC_I2C4_SDA_PWM_OUT_PWM1_OUT { pinmux = <0x3033021c 1 0x0 0 0x3033047c>; }; /omit-if-no-ref/ iomuxc_jtag_mod_jtag_mode_jtag_mode: IOMUXC_JTAG_MOD_JTAG_MODE_JTAG_MODE { pinmux = <0x0 0 0x0 0 0x30330260>; }; /omit-if-no-ref/ iomuxc_jtag_tck_jtag_tck_jtag_tck: IOMUXC_JTAG_TCK_JTAG_TCK_JTAG_TCK { pinmux = <0x0 0 0x0 0 0x3033026c>; }; /omit-if-no-ref/ iomuxc_jtag_tdi_jtag_tdi_jtag_tdi: IOMUXC_JTAG_TDI_JTAG_TDI_JTAG_TDI { pinmux = <0x0 0 0x0 0 0x30330264>; }; /omit-if-no-ref/ iomuxc_jtag_tdo_jtag_tdo_jtag_tdo: IOMUXC_JTAG_TDO_JTAG_TDO_JTAG_TDO { pinmux = <0x0 0 0x0 0 0x30330270>; }; /omit-if-no-ref/ iomuxc_jtag_tms_jtag_tms_jtag_tms: IOMUXC_JTAG_TMS_JTAG_TMS_JTAG_TMS { pinmux = <0x0 0 0x0 0 0x30330268>; }; /omit-if-no-ref/ iomuxc_nand_ale_coresight_trace_clk_coresight_trace_clk: IOMUXC_NAND_ALE_CORESIGHT_TRACE_CLK_CORESIGHT_TRACE_CLK { pinmux = <0x303300e0 6 0x0 0 0x30330340>; }; /omit-if-no-ref/ iomuxc_nand_ale_gpio_io_gpio3_io0: IOMUXC_NAND_ALE_GPIO_IO_GPIO3_IO0 { pinmux = <0x303300e0 5 0x0 0 0x30330340>; }; /omit-if-no-ref/ iomuxc_nand_ale_isp_fl_trig_isp_fl_trig_0: IOMUXC_NAND_ALE_ISP_FL_TRIG_ISP_FL_TRIG_0 { pinmux = <0x303300e0 3 0x303305d4 1 0x30330340>; }; /omit-if-no-ref/ iomuxc_nand_ale_nand_ale_nand_ale: IOMUXC_NAND_ALE_NAND_ALE_NAND_ALE { pinmux = <0x303300e0 0 0x0 0 0x30330340>; }; /omit-if-no-ref/ iomuxc_nand_ale_qspi_a_sclk_qspi_a_sclk: IOMUXC_NAND_ALE_QSPI_A_SCLK_QSPI_A_SCLK { pinmux = <0x303300e0 1 0x0 0 0x30330340>; }; /omit-if-no-ref/ iomuxc_nand_ale_sai_tx_bclk_sai3_tx_bclk: IOMUXC_NAND_ALE_SAI_TX_BCLK_SAI3_TX_BCLK { pinmux = <0x303300e0 2 0x303304e8 0 0x30330340>; }; /omit-if-no-ref/ iomuxc_nand_ale_uart_rx_uart3_rx: IOMUXC_NAND_ALE_UART_RX_UART3_RX { pinmux = <0x303300e0 4 0x303305f8 2 0x30330340>; }; /omit-if-no-ref/ iomuxc_nand_ale_uart_tx_uart3_rx: IOMUXC_NAND_ALE_UART_TX_UART3_RX { pinmux = <0x303300e0 4 0x0 0 0x30330340>; }; /omit-if-no-ref/ iomuxc_nand_ce0_b_coresight_trace_ctl_coresight_trace_ctl: IOMUXC_NAND_CE0_B_CORESIGHT_TRACE_CTL_CORESIGHT_TRACE_CTL { pinmux = <0x303300e4 6 0x0 0 0x30330344>; }; /omit-if-no-ref/ iomuxc_nand_ce0_b_gpio_io_gpio3_io1: IOMUXC_NAND_CE0_B_GPIO_IO_GPIO3_IO1 { pinmux = <0x303300e4 5 0x0 0 0x30330344>; }; /omit-if-no-ref/ iomuxc_nand_ce0_b_isp_shutter_trig_isp_shutter_trig_0: IOMUXC_NAND_CE0_B_ISP_SHUTTER_TRIG_ISP_SHUTTER_TRIG_0 { pinmux = <0x303300e4 3 0x303305dc 1 0x30330344>; }; /omit-if-no-ref/ iomuxc_nand_ce0_b_nand_ce0_b_nand_ce0_b: IOMUXC_NAND_CE0_B_NAND_CE0_B_NAND_CE0_B { pinmux = <0x303300e4 0 0x0 0 0x30330344>; }; /omit-if-no-ref/ iomuxc_nand_ce0_b_qspi_a_ss0_b_qspi_a_ss0_b: IOMUXC_NAND_CE0_B_QSPI_A_SS0_B_QSPI_A_SS0_B { pinmux = <0x303300e4 1 0x0 0 0x30330344>; }; /omit-if-no-ref/ iomuxc_nand_ce0_b_sai_tx_data_sai3_tx_data0: IOMUXC_NAND_CE0_B_SAI_TX_DATA_SAI3_TX_DATA0 { pinmux = <0x303300e4 2 0x0 0 0x30330344>; }; /omit-if-no-ref/ iomuxc_nand_ce0_b_uart_rx_uart3_tx: IOMUXC_NAND_CE0_B_UART_RX_UART3_TX { pinmux = <0x303300e4 4 0x303305f8 3 0x30330344>; }; /omit-if-no-ref/ iomuxc_nand_ce0_b_uart_tx_uart3_tx: IOMUXC_NAND_CE0_B_UART_TX_UART3_TX { pinmux = <0x303300e4 4 0x0 0 0x30330344>; }; /omit-if-no-ref/ iomuxc_nand_ce1_b_coresight_trace_coresight_trace0: IOMUXC_NAND_CE1_B_CORESIGHT_TRACE_CORESIGHT_TRACE0 { pinmux = <0x303300e8 6 0x0 0 0x30330348>; }; /omit-if-no-ref/ iomuxc_nand_ce1_b_gpio_io_gpio3_io2: IOMUXC_NAND_CE1_B_GPIO_IO_GPIO3_IO2 { pinmux = <0x303300e8 5 0x0 0 0x30330348>; }; /omit-if-no-ref/ iomuxc_nand_ce1_b_i2c_scl_i2c4_scl: IOMUXC_NAND_CE1_B_I2C_SCL_I2C4_SCL { pinmux = <0x303300e8 4 0x303305bc 2 0x30330348>; }; /omit-if-no-ref/ iomuxc_nand_ce1_b_nand_ce1_b_nand_ce1_b: IOMUXC_NAND_CE1_B_NAND_CE1_B_NAND_CE1_B { pinmux = <0x303300e8 0 0x0 0 0x30330348>; }; /omit-if-no-ref/ iomuxc_nand_ce1_b_qspi_a_ss1_b_qspi_a_ss1_b: IOMUXC_NAND_CE1_B_QSPI_A_SS1_B_QSPI_A_SS1_B { pinmux = <0x303300e8 1 0x0 0 0x30330348>; }; /omit-if-no-ref/ iomuxc_nand_ce1_b_usdhc_strobe_usdhc3_strobe: IOMUXC_NAND_CE1_B_USDHC_STROBE_USDHC3_STROBE { pinmux = <0x303300e8 2 0x30330630 1 0x30330348>; }; /omit-if-no-ref/ iomuxc_nand_ce2_b_coresight_trace_coresight_trace1: IOMUXC_NAND_CE2_B_CORESIGHT_TRACE_CORESIGHT_TRACE1 { pinmux = <0x303300ec 6 0x0 0 0x3033034c>; }; /omit-if-no-ref/ iomuxc_nand_ce2_b_gpio_io_gpio3_io3: IOMUXC_NAND_CE2_B_GPIO_IO_GPIO3_IO3 { pinmux = <0x303300ec 5 0x0 0 0x3033034c>; }; /omit-if-no-ref/ iomuxc_nand_ce2_b_i2c_sda_i2c4_sda: IOMUXC_NAND_CE2_B_I2C_SDA_I2C4_SDA { pinmux = <0x303300ec 4 0x303305c0 2 0x3033034c>; }; /omit-if-no-ref/ iomuxc_nand_ce2_b_nand_ce2_b_nand_ce2_b: IOMUXC_NAND_CE2_B_NAND_CE2_B_NAND_CE2_B { pinmux = <0x303300ec 0 0x0 0 0x3033034c>; }; /omit-if-no-ref/ iomuxc_nand_ce2_b_qspi_b_ss0_b_qspi_b_ss0_b: IOMUXC_NAND_CE2_B_QSPI_B_SS0_B_QSPI_B_SS0_B { pinmux = <0x303300ec 1 0x0 0 0x3033034c>; }; /omit-if-no-ref/ iomuxc_nand_ce2_b_usdhc_data_usdhc3_data5: IOMUXC_NAND_CE2_B_USDHC_DATA_USDHC3_DATA5 { pinmux = <0x303300ec 2 0x30330624 1 0x3033034c>; }; /omit-if-no-ref/ iomuxc_nand_ce3_b_coresight_trace_coresight_trace2: IOMUXC_NAND_CE3_B_CORESIGHT_TRACE_CORESIGHT_TRACE2 { pinmux = <0x303300f0 6 0x0 0 0x30330350>; }; /omit-if-no-ref/ iomuxc_nand_ce3_b_gpio_io_gpio3_io4: IOMUXC_NAND_CE3_B_GPIO_IO_GPIO3_IO4 { pinmux = <0x303300f0 5 0x0 0 0x30330350>; }; /omit-if-no-ref/ iomuxc_nand_ce3_b_i2c_sda_i2c3_sda: IOMUXC_NAND_CE3_B_I2C_SDA_I2C3_SDA { pinmux = <0x303300f0 4 0x303305b8 1 0x30330350>; }; /omit-if-no-ref/ iomuxc_nand_ce3_b_nand_ce3_b_nand_ce3_b: IOMUXC_NAND_CE3_B_NAND_CE3_B_NAND_CE3_B { pinmux = <0x303300f0 0 0x0 0 0x30330350>; }; /omit-if-no-ref/ iomuxc_nand_ce3_b_qspi_b_ss1_b_qspi_b_ss1_b: IOMUXC_NAND_CE3_B_QSPI_B_SS1_B_QSPI_B_SS1_B { pinmux = <0x303300f0 1 0x0 0 0x30330350>; }; /omit-if-no-ref/ iomuxc_nand_ce3_b_usdhc_data_usdhc3_data6: IOMUXC_NAND_CE3_B_USDHC_DATA_USDHC3_DATA6 { pinmux = <0x303300f0 2 0x30330628 1 0x30330350>; }; /omit-if-no-ref/ iomuxc_nand_cle_coresight_trace_coresight_trace3: IOMUXC_NAND_CLE_CORESIGHT_TRACE_CORESIGHT_TRACE3 { pinmux = <0x303300f4 6 0x0 0 0x30330354>; }; /omit-if-no-ref/ iomuxc_nand_cle_gpio_io_gpio3_io5: IOMUXC_NAND_CLE_GPIO_IO_GPIO3_IO5 { pinmux = <0x303300f4 5 0x0 0 0x30330354>; }; /omit-if-no-ref/ iomuxc_nand_cle_nand_cle_nand_cle: IOMUXC_NAND_CLE_NAND_CLE_NAND_CLE { pinmux = <0x303300f4 0 0x0 0 0x30330354>; }; /omit-if-no-ref/ iomuxc_nand_cle_qspi_b_sclk_qspi_b_sclk: IOMUXC_NAND_CLE_QSPI_B_SCLK_QSPI_B_SCLK { pinmux = <0x303300f4 1 0x0 0 0x30330354>; }; /omit-if-no-ref/ iomuxc_nand_cle_uart_rx_uart4_rx: IOMUXC_NAND_CLE_UART_RX_UART4_RX { pinmux = <0x303300f4 4 0x30330600 2 0x30330354>; }; /omit-if-no-ref/ iomuxc_nand_cle_uart_tx_uart4_rx: IOMUXC_NAND_CLE_UART_TX_UART4_RX { pinmux = <0x303300f4 4 0x0 0 0x30330354>; }; /omit-if-no-ref/ iomuxc_nand_cle_usdhc_data_usdhc3_data7: IOMUXC_NAND_CLE_USDHC_DATA_USDHC3_DATA7 { pinmux = <0x303300f4 2 0x3033062c 1 0x30330354>; }; /omit-if-no-ref/ iomuxc_nand_data00_coresight_trace_coresight_trace4: IOMUXC_NAND_DATA00_CORESIGHT_TRACE_CORESIGHT_TRACE4 { pinmux = <0x303300f8 6 0x0 0 0x30330358>; }; /omit-if-no-ref/ iomuxc_nand_data00_gpio_io_gpio3_io6: IOMUXC_NAND_DATA00_GPIO_IO_GPIO3_IO6 { pinmux = <0x303300f8 5 0x0 0 0x30330358>; }; /omit-if-no-ref/ iomuxc_nand_data00_isp_flash_trig_isp_flash_trig_0: IOMUXC_NAND_DATA00_ISP_FLASH_TRIG_ISP_FLASH_TRIG_0 { pinmux = <0x303300f8 3 0x0 0 0x30330358>; }; /omit-if-no-ref/ iomuxc_nand_data00_nand_data_nand_data00: IOMUXC_NAND_DATA00_NAND_DATA_NAND_DATA00 { pinmux = <0x303300f8 0 0x0 0 0x30330358>; }; /omit-if-no-ref/ iomuxc_nand_data00_qspi_a_data_qspi_a_data0: IOMUXC_NAND_DATA00_QSPI_A_DATA_QSPI_A_DATA0 { pinmux = <0x303300f8 1 0x0 0 0x30330358>; }; /omit-if-no-ref/ iomuxc_nand_data00_sai_rx_data_sai3_rx_data0: IOMUXC_NAND_DATA00_SAI_RX_DATA_SAI3_RX_DATA0 { pinmux = <0x303300f8 2 0x303304e4 0 0x30330358>; }; /omit-if-no-ref/ iomuxc_nand_data00_uart_rx_uart4_rx: IOMUXC_NAND_DATA00_UART_RX_UART4_RX { pinmux = <0x303300f8 4 0x30330600 3 0x30330358>; }; /omit-if-no-ref/ iomuxc_nand_data00_uart_tx_uart4_rx: IOMUXC_NAND_DATA00_UART_TX_UART4_RX { pinmux = <0x303300f8 4 0x0 0 0x30330358>; }; /omit-if-no-ref/ iomuxc_nand_data01_coresight_trace_coresight_trace5: IOMUXC_NAND_DATA01_CORESIGHT_TRACE_CORESIGHT_TRACE5 { pinmux = <0x303300fc 6 0x0 0 0x3033035c>; }; /omit-if-no-ref/ iomuxc_nand_data01_gpio_io_gpio3_io7: IOMUXC_NAND_DATA01_GPIO_IO_GPIO3_IO7 { pinmux = <0x303300fc 5 0x0 0 0x3033035c>; }; /omit-if-no-ref/ iomuxc_nand_data01_isp_prelight_trig_isp_prelight_trig_0: IOMUXC_NAND_DATA01_ISP_PRELIGHT_TRIG_ISP_PRELIGHT_TRIG_0 { pinmux = <0x303300fc 3 0x0 0 0x3033035c>; }; /omit-if-no-ref/ iomuxc_nand_data01_nand_data_nand_data01: IOMUXC_NAND_DATA01_NAND_DATA_NAND_DATA01 { pinmux = <0x303300fc 0 0x0 0 0x3033035c>; }; /omit-if-no-ref/ iomuxc_nand_data01_qspi_a_data_qspi_a_data1: IOMUXC_NAND_DATA01_QSPI_A_DATA_QSPI_A_DATA1 { pinmux = <0x303300fc 1 0x0 0 0x3033035c>; }; /omit-if-no-ref/ iomuxc_nand_data01_sai_tx_sync_sai3_tx_sync: IOMUXC_NAND_DATA01_SAI_TX_SYNC_SAI3_TX_SYNC { pinmux = <0x303300fc 2 0x303304ec 0 0x3033035c>; }; /omit-if-no-ref/ iomuxc_nand_data01_uart_rx_uart4_tx: IOMUXC_NAND_DATA01_UART_RX_UART4_TX { pinmux = <0x303300fc 4 0x30330600 4 0x3033035c>; }; /omit-if-no-ref/ iomuxc_nand_data01_uart_tx_uart4_tx: IOMUXC_NAND_DATA01_UART_TX_UART4_TX { pinmux = <0x303300fc 4 0x0 0 0x3033035c>; }; /omit-if-no-ref/ iomuxc_nand_data02_coresight_trace_coresight_trace6: IOMUXC_NAND_DATA02_CORESIGHT_TRACE_CORESIGHT_TRACE6 { pinmux = <0x30330100 6 0x0 0 0x30330360>; }; /omit-if-no-ref/ iomuxc_nand_data02_gpio_io_gpio3_io8: IOMUXC_NAND_DATA02_GPIO_IO_GPIO3_IO8 { pinmux = <0x30330100 5 0x0 0 0x30330360>; }; /omit-if-no-ref/ iomuxc_nand_data02_i2c_sda_i2c4_sda: IOMUXC_NAND_DATA02_I2C_SDA_I2C4_SDA { pinmux = <0x30330100 4 0x303305c0 3 0x30330360>; }; /omit-if-no-ref/ iomuxc_nand_data02_nand_data_nand_data02: IOMUXC_NAND_DATA02_NAND_DATA_NAND_DATA02 { pinmux = <0x30330100 0 0x0 0 0x30330360>; }; /omit-if-no-ref/ iomuxc_nand_data02_qspi_a_data_qspi_a_data2: IOMUXC_NAND_DATA02_QSPI_A_DATA_QSPI_A_DATA2 { pinmux = <0x30330100 1 0x0 0 0x30330360>; }; /omit-if-no-ref/ iomuxc_nand_data02_uart_cts_b_uart4_cts_b: IOMUXC_NAND_DATA02_UART_CTS_B_UART4_CTS_B { pinmux = <0x30330100 3 0x0 0 0x30330360>; }; /omit-if-no-ref/ iomuxc_nand_data02_uart_rts_b_uart4_cts_b: IOMUXC_NAND_DATA02_UART_RTS_B_UART4_CTS_B { pinmux = <0x30330100 3 0x303305fc 0 0x30330360>; }; /omit-if-no-ref/ iomuxc_nand_data02_usdhc_cd_b_usdhc3_cd_b: IOMUXC_NAND_DATA02_USDHC_CD_B_USDHC3_CD_B { pinmux = <0x30330100 2 0x30330608 2 0x30330360>; }; /omit-if-no-ref/ iomuxc_nand_data03_coresight_trace_coresight_trace7: IOMUXC_NAND_DATA03_CORESIGHT_TRACE_CORESIGHT_TRACE7 { pinmux = <0x30330104 6 0x0 0 0x30330364>; }; /omit-if-no-ref/ iomuxc_nand_data03_gpio_io_gpio3_io9: IOMUXC_NAND_DATA03_GPIO_IO_GPIO3_IO9 { pinmux = <0x30330104 5 0x0 0 0x30330364>; }; /omit-if-no-ref/ iomuxc_nand_data03_isp_fl_trig_isp_fl_trig_1: IOMUXC_NAND_DATA03_ISP_FL_TRIG_ISP_FL_TRIG_1 { pinmux = <0x30330104 4 0x303305d8 1 0x30330364>; }; /omit-if-no-ref/ iomuxc_nand_data03_nand_data_nand_data03: IOMUXC_NAND_DATA03_NAND_DATA_NAND_DATA03 { pinmux = <0x30330104 0 0x0 0 0x30330364>; }; /omit-if-no-ref/ iomuxc_nand_data03_qspi_a_data_qspi_a_data3: IOMUXC_NAND_DATA03_QSPI_A_DATA_QSPI_A_DATA3 { pinmux = <0x30330104 1 0x0 0 0x30330364>; }; /omit-if-no-ref/ iomuxc_nand_data03_uart_cts_b_uart4_rts_b: IOMUXC_NAND_DATA03_UART_CTS_B_UART4_RTS_B { pinmux = <0x30330104 3 0x0 0 0x30330364>; }; /omit-if-no-ref/ iomuxc_nand_data03_uart_rts_b_uart4_rts_b: IOMUXC_NAND_DATA03_UART_RTS_B_UART4_RTS_B { pinmux = <0x30330104 3 0x303305fc 1 0x30330364>; }; /omit-if-no-ref/ iomuxc_nand_data03_usdhc_wp_usdhc3_wp: IOMUXC_NAND_DATA03_USDHC_WP_USDHC3_WP { pinmux = <0x30330104 2 0x30330634 2 0x30330364>; }; /omit-if-no-ref/ iomuxc_nand_data04_coresight_trace_coresight_trace8: IOMUXC_NAND_DATA04_CORESIGHT_TRACE_CORESIGHT_TRACE8 { pinmux = <0x30330108 6 0x0 0 0x30330368>; }; /omit-if-no-ref/ iomuxc_nand_data04_gpio_io_gpio3_io10: IOMUXC_NAND_DATA04_GPIO_IO_GPIO3_IO10 { pinmux = <0x30330108 5 0x0 0 0x30330368>; }; /omit-if-no-ref/ iomuxc_nand_data04_isp_shutter_trig_isp_shutter_trig_1: IOMUXC_NAND_DATA04_ISP_SHUTTER_TRIG_ISP_SHUTTER_TRIG_1 { pinmux = <0x30330108 4 0x303305e0 1 0x30330368>; }; /omit-if-no-ref/ iomuxc_nand_data04_nand_data_nand_data04: IOMUXC_NAND_DATA04_NAND_DATA_NAND_DATA04 { pinmux = <0x30330108 0 0x0 0 0x30330368>; }; /omit-if-no-ref/ iomuxc_nand_data04_qspi_a_data_qspi_a_data4: IOMUXC_NAND_DATA04_QSPI_A_DATA_QSPI_A_DATA4 { pinmux = <0x30330108 3 0x0 0 0x30330368>; }; /omit-if-no-ref/ iomuxc_nand_data04_qspi_b_data_qspi_b_data0: IOMUXC_NAND_DATA04_QSPI_B_DATA_QSPI_B_DATA0 { pinmux = <0x30330108 1 0x0 0 0x30330368>; }; /omit-if-no-ref/ iomuxc_nand_data04_usdhc_data_usdhc3_data0: IOMUXC_NAND_DATA04_USDHC_DATA_USDHC3_DATA0 { pinmux = <0x30330108 2 0x30330610 1 0x30330368>; }; /omit-if-no-ref/ iomuxc_nand_data05_coresight_trace_coresight_trace9: IOMUXC_NAND_DATA05_CORESIGHT_TRACE_CORESIGHT_TRACE9 { pinmux = <0x3033010c 6 0x0 0 0x3033036c>; }; /omit-if-no-ref/ iomuxc_nand_data05_gpio_io_gpio3_io11: IOMUXC_NAND_DATA05_GPIO_IO_GPIO3_IO11 { pinmux = <0x3033010c 5 0x0 0 0x3033036c>; }; /omit-if-no-ref/ iomuxc_nand_data05_isp_flash_trig_isp_flash_trig_1: IOMUXC_NAND_DATA05_ISP_FLASH_TRIG_ISP_FLASH_TRIG_1 { pinmux = <0x3033010c 4 0x0 0 0x3033036c>; }; /omit-if-no-ref/ iomuxc_nand_data05_nand_data_nand_data05: IOMUXC_NAND_DATA05_NAND_DATA_NAND_DATA05 { pinmux = <0x3033010c 0 0x0 0 0x3033036c>; }; /omit-if-no-ref/ iomuxc_nand_data05_qspi_a_data_qspi_a_data5: IOMUXC_NAND_DATA05_QSPI_A_DATA_QSPI_A_DATA5 { pinmux = <0x3033010c 3 0x0 0 0x3033036c>; }; /omit-if-no-ref/ iomuxc_nand_data05_qspi_b_data_qspi_b_data1: IOMUXC_NAND_DATA05_QSPI_B_DATA_QSPI_B_DATA1 { pinmux = <0x3033010c 1 0x0 0 0x3033036c>; }; /omit-if-no-ref/ iomuxc_nand_data05_usdhc_data_usdhc3_data1: IOMUXC_NAND_DATA05_USDHC_DATA_USDHC3_DATA1 { pinmux = <0x3033010c 2 0x30330614 1 0x3033036c>; }; /omit-if-no-ref/ iomuxc_nand_data06_coresight_trace_coresight_trace10: IOMUXC_NAND_DATA06_CORESIGHT_TRACE_CORESIGHT_TRACE10 { pinmux = <0x30330110 6 0x0 0 0x30330370>; }; /omit-if-no-ref/ iomuxc_nand_data06_gpio_io_gpio3_io12: IOMUXC_NAND_DATA06_GPIO_IO_GPIO3_IO12 { pinmux = <0x30330110 5 0x0 0 0x30330370>; }; /omit-if-no-ref/ iomuxc_nand_data06_isp_prelight_trig_isp_prelight_trig_1: IOMUXC_NAND_DATA06_ISP_PRELIGHT_TRIG_ISP_PRELIGHT_TRIG_1 { pinmux = <0x30330110 4 0x0 0 0x30330370>; }; /omit-if-no-ref/ iomuxc_nand_data06_nand_data_nand_data06: IOMUXC_NAND_DATA06_NAND_DATA_NAND_DATA06 { pinmux = <0x30330110 0 0x0 0 0x30330370>; }; /omit-if-no-ref/ iomuxc_nand_data06_qspi_a_data_qspi_a_data6: IOMUXC_NAND_DATA06_QSPI_A_DATA_QSPI_A_DATA6 { pinmux = <0x30330110 3 0x0 0 0x30330370>; }; /omit-if-no-ref/ iomuxc_nand_data06_qspi_b_data_qspi_b_data2: IOMUXC_NAND_DATA06_QSPI_B_DATA_QSPI_B_DATA2 { pinmux = <0x30330110 1 0x0 0 0x30330370>; }; /omit-if-no-ref/ iomuxc_nand_data06_usdhc_data_usdhc3_data2: IOMUXC_NAND_DATA06_USDHC_DATA_USDHC3_DATA2 { pinmux = <0x30330110 2 0x30330618 1 0x30330370>; }; /omit-if-no-ref/ iomuxc_nand_data07_coresight_trace_coresight_trace11: IOMUXC_NAND_DATA07_CORESIGHT_TRACE_CORESIGHT_TRACE11 { pinmux = <0x30330114 6 0x0 0 0x30330374>; }; /omit-if-no-ref/ iomuxc_nand_data07_gpio_io_gpio3_io13: IOMUXC_NAND_DATA07_GPIO_IO_GPIO3_IO13 { pinmux = <0x30330114 5 0x0 0 0x30330374>; }; /omit-if-no-ref/ iomuxc_nand_data07_isp_shutter_open_isp_shutter_open_1: IOMUXC_NAND_DATA07_ISP_SHUTTER_OPEN_ISP_SHUTTER_OPEN_1 { pinmux = <0x30330114 4 0x0 0 0x30330374>; }; /omit-if-no-ref/ iomuxc_nand_data07_nand_data_nand_data07: IOMUXC_NAND_DATA07_NAND_DATA_NAND_DATA07 { pinmux = <0x30330114 0 0x0 0 0x30330374>; }; /omit-if-no-ref/ iomuxc_nand_data07_qspi_a_data_qspi_a_data7: IOMUXC_NAND_DATA07_QSPI_A_DATA_QSPI_A_DATA7 { pinmux = <0x30330114 3 0x0 0 0x30330374>; }; /omit-if-no-ref/ iomuxc_nand_data07_qspi_b_data_qspi_b_data3: IOMUXC_NAND_DATA07_QSPI_B_DATA_QSPI_B_DATA3 { pinmux = <0x30330114 1 0x0 0 0x30330374>; }; /omit-if-no-ref/ iomuxc_nand_data07_usdhc_data_usdhc3_data3: IOMUXC_NAND_DATA07_USDHC_DATA_USDHC3_DATA3 { pinmux = <0x30330114 2 0x3033061c 1 0x30330374>; }; /omit-if-no-ref/ iomuxc_nand_dqs_coresight_trace_coresight_trace12: IOMUXC_NAND_DQS_CORESIGHT_TRACE_CORESIGHT_TRACE12 { pinmux = <0x30330118 6 0x0 0 0x30330378>; }; /omit-if-no-ref/ iomuxc_nand_dqs_gpio_io_gpio3_io14: IOMUXC_NAND_DQS_GPIO_IO_GPIO3_IO14 { pinmux = <0x30330118 5 0x0 0 0x30330378>; }; /omit-if-no-ref/ iomuxc_nand_dqs_i2c_scl_i2c3_scl: IOMUXC_NAND_DQS_I2C_SCL_I2C3_SCL { pinmux = <0x30330118 4 0x303305b4 1 0x30330378>; }; /omit-if-no-ref/ iomuxc_nand_dqs_isp_shutter_open_isp_shutter_open_0: IOMUXC_NAND_DQS_ISP_SHUTTER_OPEN_ISP_SHUTTER_OPEN_0 { pinmux = <0x30330118 3 0x0 0 0x30330378>; }; /omit-if-no-ref/ iomuxc_nand_dqs_nand_dqs_nand_dqs: IOMUXC_NAND_DQS_NAND_DQS_NAND_DQS { pinmux = <0x30330118 0 0x0 0 0x30330378>; }; /omit-if-no-ref/ iomuxc_nand_dqs_qspi_a_dqs_qspi_a_dqs: IOMUXC_NAND_DQS_QSPI_A_DQS_QSPI_A_DQS { pinmux = <0x30330118 1 0x0 0 0x30330378>; }; /omit-if-no-ref/ iomuxc_nand_dqs_sai_mclk_sai3_mclk: IOMUXC_NAND_DQS_SAI_MCLK_SAI3_MCLK { pinmux = <0x30330118 2 0x303304e0 0 0x30330378>; }; /omit-if-no-ref/ iomuxc_nand_ready_b_coresight_trace_coresight_trace14: IOMUXC_NAND_READY_B_CORESIGHT_TRACE_CORESIGHT_TRACE14 { pinmux = <0x30330120 6 0x0 0 0x30330380>; }; /omit-if-no-ref/ iomuxc_nand_ready_b_gpio_io_gpio3_io16: IOMUXC_NAND_READY_B_GPIO_IO_GPIO3_IO16 { pinmux = <0x30330120 5 0x0 0 0x30330380>; }; /omit-if-no-ref/ iomuxc_nand_ready_b_i2c_scl_i2c3_scl: IOMUXC_NAND_READY_B_I2C_SCL_I2C3_SCL { pinmux = <0x30330120 4 0x303305b4 2 0x30330380>; }; /omit-if-no-ref/ iomuxc_nand_ready_b_nand_ready_b_nand_ready_b: IOMUXC_NAND_READY_B_NAND_READY_B_NAND_READY_B { pinmux = <0x30330120 0 0x0 0 0x30330380>; }; /omit-if-no-ref/ iomuxc_nand_ready_b_usdhc_reset_b_usdhc3_reset_b: IOMUXC_NAND_READY_B_USDHC_RESET_B_USDHC3_RESET_B { pinmux = <0x30330120 2 0x0 0 0x30330380>; }; /omit-if-no-ref/ iomuxc_nand_re_b_coresight_trace_coresight_trace13: IOMUXC_NAND_RE_B_CORESIGHT_TRACE_CORESIGHT_TRACE13 { pinmux = <0x3033011c 6 0x0 0 0x3033037c>; }; /omit-if-no-ref/ iomuxc_nand_re_b_gpio_io_gpio3_io15: IOMUXC_NAND_RE_B_GPIO_IO_GPIO3_IO15 { pinmux = <0x3033011c 5 0x0 0 0x3033037c>; }; /omit-if-no-ref/ iomuxc_nand_re_b_nand_re_b_nand_re_b: IOMUXC_NAND_RE_B_NAND_RE_B_NAND_RE_B { pinmux = <0x3033011c 0 0x0 0 0x3033037c>; }; /omit-if-no-ref/ iomuxc_nand_re_b_qspi_b_dqs_qspi_b_dqs: IOMUXC_NAND_RE_B_QSPI_B_DQS_QSPI_B_DQS { pinmux = <0x3033011c 1 0x0 0 0x3033037c>; }; /omit-if-no-ref/ iomuxc_nand_re_b_uart_rx_uart4_tx: IOMUXC_NAND_RE_B_UART_RX_UART4_TX { pinmux = <0x3033011c 4 0x30330600 5 0x3033037c>; }; /omit-if-no-ref/ iomuxc_nand_re_b_uart_tx_uart4_tx: IOMUXC_NAND_RE_B_UART_TX_UART4_TX { pinmux = <0x3033011c 4 0x0 0 0x3033037c>; }; /omit-if-no-ref/ iomuxc_nand_re_b_usdhc_data_usdhc3_data4: IOMUXC_NAND_RE_B_USDHC_DATA_USDHC3_DATA4 { pinmux = <0x3033011c 2 0x30330620 1 0x3033037c>; }; /omit-if-no-ref/ iomuxc_nand_we_b_coresight_trace_coresight_trace15: IOMUXC_NAND_WE_B_CORESIGHT_TRACE_CORESIGHT_TRACE15 { pinmux = <0x30330124 6 0x0 0 0x30330384>; }; /omit-if-no-ref/ iomuxc_nand_we_b_gpio_io_gpio3_io17: IOMUXC_NAND_WE_B_GPIO_IO_GPIO3_IO17 { pinmux = <0x30330124 5 0x0 0 0x30330384>; }; /omit-if-no-ref/ iomuxc_nand_we_b_i2c_sda_i2c3_sda: IOMUXC_NAND_WE_B_I2C_SDA_I2C3_SDA { pinmux = <0x30330124 4 0x303305b8 2 0x30330384>; }; /omit-if-no-ref/ iomuxc_nand_we_b_nand_we_b_nand_we_b: IOMUXC_NAND_WE_B_NAND_WE_B_NAND_WE_B { pinmux = <0x30330124 0 0x0 0 0x30330384>; }; /omit-if-no-ref/ iomuxc_nand_we_b_usdhc_clk_usdhc3_clk: IOMUXC_NAND_WE_B_USDHC_CLK_USDHC3_CLK { pinmux = <0x30330124 2 0x30330604 1 0x30330384>; }; /omit-if-no-ref/ iomuxc_nand_wp_b_coresight_evento_coresight_evento: IOMUXC_NAND_WP_B_CORESIGHT_EVENTO_CORESIGHT_EVENTO { pinmux = <0x30330128 6 0x0 0 0x30330388>; }; /omit-if-no-ref/ iomuxc_nand_wp_b_gpio_io_gpio3_io18: IOMUXC_NAND_WP_B_GPIO_IO_GPIO3_IO18 { pinmux = <0x30330128 5 0x0 0 0x30330388>; }; /omit-if-no-ref/ iomuxc_nand_wp_b_i2c_scl_i2c4_scl: IOMUXC_NAND_WP_B_I2C_SCL_I2C4_SCL { pinmux = <0x30330128 4 0x303305bc 3 0x30330388>; }; /omit-if-no-ref/ iomuxc_nand_wp_b_nand_wp_b_nand_wp_b: IOMUXC_NAND_WP_B_NAND_WP_B_NAND_WP_B { pinmux = <0x30330128 0 0x0 0 0x30330388>; }; /omit-if-no-ref/ iomuxc_nand_wp_b_usdhc_cmd_usdhc3_cmd: IOMUXC_NAND_WP_B_USDHC_CMD_USDHC3_CMD { pinmux = <0x30330128 2 0x3033060c 1 0x30330388>; }; /omit-if-no-ref/ iomuxc_sai1_mclk_enet_tx_clk_enet1_tx_clk: IOMUXC_SAI1_MCLK_ENET_TX_CLK_ENET1_TX_CLK { pinmux = <0x30330198 4 0x30330578 1 0x303303f8>; }; /omit-if-no-ref/ iomuxc_sai1_mclk_gpio_io_gpio4_io20: IOMUXC_SAI1_MCLK_GPIO_IO_GPIO4_IO20 { pinmux = <0x30330198 5 0x0 0 0x303303f8>; }; /omit-if-no-ref/ iomuxc_sai1_mclk_sai_mclk_sai1_mclk: IOMUXC_SAI1_MCLK_SAI_MCLK_SAI1_MCLK { pinmux = <0x30330198 0 0x0 0 0x303303f8>; }; /omit-if-no-ref/ iomuxc_sai1_mclk_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI1_MCLK_SAI_TX_BCLK_SAI1_TX_BCLK { pinmux = <0x30330198 2 0x303304d4 2 0x303303f8>; }; /omit-if-no-ref/ iomuxc_sai1_rxc_enet_1588_event0_out_enet1_1588_event0_out: IOMUXC_SAI1_RXC_ENET_1588_EVENT0_OUT_ENET1_1588_EVENT0_OUT { pinmux = <0x3033014c 4 0x0 0 0x303303ac>; }; /omit-if-no-ref/ iomuxc_sai1_rxc_gpio_io_gpio4_io1: IOMUXC_SAI1_RXC_GPIO_IO_GPIO4_IO1 { pinmux = <0x3033014c 5 0x0 0 0x303303ac>; }; /omit-if-no-ref/ iomuxc_sai1_rxc_pdm_clk_pdm_clk: IOMUXC_SAI1_RXC_PDM_CLK_PDM_CLK { pinmux = <0x3033014c 3 0x0 0 0x303303ac>; }; /omit-if-no-ref/ iomuxc_sai1_rxc_sai_rx_bclk_sai1_rx_bclk: IOMUXC_SAI1_RXC_SAI_RX_BCLK_SAI1_RX_BCLK { pinmux = <0x3033014c 0 0x0 0 0x303303ac>; }; /omit-if-no-ref/ iomuxc_sai1_rxd0_enet_1588_event1_in_enet1_1588_event1_in: IOMUXC_SAI1_RXD0_ENET_1588_EVENT1_IN_ENET1_1588_EVENT1_IN { pinmux = <0x30330150 4 0x0 0 0x303303b0>; }; /omit-if-no-ref/ iomuxc_sai1_rxd0_gpio_io_gpio4_io2: IOMUXC_SAI1_RXD0_GPIO_IO_GPIO4_IO2 { pinmux = <0x30330150 5 0x0 0 0x303303b0>; }; /omit-if-no-ref/ iomuxc_sai1_rxd0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI1_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { pinmux = <0x30330150 3 0x303304c0 4 0x303303b0>; }; /omit-if-no-ref/ iomuxc_sai1_rxd0_sai_rx_data_sai1_rx_data0: IOMUXC_SAI1_RXD0_SAI_RX_DATA_SAI1_RX_DATA0 { pinmux = <0x30330150 0 0x0 0 0x303303b0>; }; /omit-if-no-ref/ iomuxc_sai1_rxd0_sai_tx_data_sai1_tx_data1: IOMUXC_SAI1_RXD0_SAI_TX_DATA_SAI1_TX_DATA1 { pinmux = <0x30330150 2 0x0 0 0x303303b0>; }; /omit-if-no-ref/ iomuxc_sai1_rxd1_enet_1588_event1_out_enet1_1588_event1_out: IOMUXC_SAI1_RXD1_ENET_1588_EVENT1_OUT_ENET1_1588_EVENT1_OUT { pinmux = <0x30330154 4 0x0 0 0x303303b4>; }; /omit-if-no-ref/ iomuxc_sai1_rxd1_gpio_io_gpio4_io3: IOMUXC_SAI1_RXD1_GPIO_IO_GPIO4_IO3 { pinmux = <0x30330154 5 0x0 0 0x303303b4>; }; /omit-if-no-ref/ iomuxc_sai1_rxd1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI1_RXD1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { pinmux = <0x30330154 3 0x303304c4 4 0x303303b4>; }; /omit-if-no-ref/ iomuxc_sai1_rxd1_sai_rx_data_sai1_rx_data1: IOMUXC_SAI1_RXD1_SAI_RX_DATA_SAI1_RX_DATA1 { pinmux = <0x30330154 0 0x0 0 0x303303b4>; }; /omit-if-no-ref/ iomuxc_sai1_rxd2_enet_mdc_enet1_mdc: IOMUXC_SAI1_RXD2_ENET_MDC_ENET1_MDC { pinmux = <0x30330158 4 0x0 0 0x303303b8>; }; /omit-if-no-ref/ iomuxc_sai1_rxd2_gpio_io_gpio4_io4: IOMUXC_SAI1_RXD2_GPIO_IO_GPIO4_IO4 { pinmux = <0x30330158 5 0x0 0 0x303303b8>; }; /omit-if-no-ref/ iomuxc_sai1_rxd2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI1_RXD2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { pinmux = <0x30330158 3 0x303304c8 4 0x303303b8>; }; /omit-if-no-ref/ iomuxc_sai1_rxd2_sai_rx_data_sai1_rx_data2: IOMUXC_SAI1_RXD2_SAI_RX_DATA_SAI1_RX_DATA2 { pinmux = <0x30330158 0 0x0 0 0x303303b8>; }; /omit-if-no-ref/ iomuxc_sai1_rxd3_enet_mdio_enet1_mdio: IOMUXC_SAI1_RXD3_ENET_MDIO_ENET1_MDIO { pinmux = <0x3033015c 4 0x3033057c 1 0x303303bc>; }; /omit-if-no-ref/ iomuxc_sai1_rxd3_gpio_io_gpio4_io5: IOMUXC_SAI1_RXD3_GPIO_IO_GPIO4_IO5 { pinmux = <0x3033015c 5 0x0 0 0x303303bc>; }; /omit-if-no-ref/ iomuxc_sai1_rxd3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI1_RXD3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { pinmux = <0x3033015c 3 0x303304cc 4 0x303303bc>; }; /omit-if-no-ref/ iomuxc_sai1_rxd3_sai_rx_data_sai1_rx_data3: IOMUXC_SAI1_RXD3_SAI_RX_DATA_SAI1_RX_DATA3 { pinmux = <0x3033015c 0 0x0 0 0x303303bc>; }; /omit-if-no-ref/ iomuxc_sai1_rxd4_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC_SAI1_RXD4_ENET_RGMII_RD_ENET1_RGMII_RD0 { pinmux = <0x30330160 4 0x30330580 1 0x303303c0>; }; /omit-if-no-ref/ iomuxc_sai1_rxd4_gpio_io_gpio4_io6: IOMUXC_SAI1_RXD4_GPIO_IO_GPIO4_IO6 { pinmux = <0x30330160 5 0x0 0 0x303303c0>; }; /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_rx_bclk_sai6_rx_bclk: IOMUXC_SAI1_RXD4_SAI_RX_BCLK_SAI6_RX_BCLK { pinmux = <0x30330160 2 0x30330518 1 0x303303c0>; }; /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_rx_data_sai1_rx_data4: IOMUXC_SAI1_RXD4_SAI_RX_DATA_SAI1_RX_DATA4 { pinmux = <0x30330160 0 0x0 0 0x303303c0>; }; /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_tx_bclk_sai6_tx_bclk: IOMUXC_SAI1_RXD4_SAI_TX_BCLK_SAI6_TX_BCLK { pinmux = <0x30330160 1 0x30330524 1 0x303303c0>; }; /omit-if-no-ref/ iomuxc_sai1_rxd5_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC_SAI1_RXD5_ENET_RGMII_RD_ENET1_RGMII_RD1 { pinmux = <0x30330164 4 0x30330584 1 0x303303c4>; }; /omit-if-no-ref/ iomuxc_sai1_rxd5_gpio_io_gpio4_io7: IOMUXC_SAI1_RXD5_GPIO_IO_GPIO4_IO7 { pinmux = <0x30330164 5 0x0 0 0x303303c4>; }; /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_data_sai1_rx_data5: IOMUXC_SAI1_RXD5_SAI_RX_DATA_SAI1_RX_DATA5 { pinmux = <0x30330164 0 0x0 0 0x303303c4>; }; /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_data_sai6_rx_data0: IOMUXC_SAI1_RXD5_SAI_RX_DATA_SAI6_RX_DATA0 { pinmux = <0x30330164 2 0x3033051c 1 0x303303c4>; }; /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_sync_sai1_rx_sync: IOMUXC_SAI1_RXD5_SAI_RX_SYNC_SAI1_RX_SYNC { pinmux = <0x30330164 3 0x303304d0 1 0x303303c4>; }; /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_tx_data_sai6_tx_data0: IOMUXC_SAI1_RXD5_SAI_TX_DATA_SAI6_TX_DATA0 { pinmux = <0x30330164 1 0x0 0 0x303303c4>; }; /omit-if-no-ref/ iomuxc_sai1_rxd6_enet_rgmii_rd_enet1_rgmii_rd2: IOMUXC_SAI1_RXD6_ENET_RGMII_RD_ENET1_RGMII_RD2 { pinmux = <0x30330168 4 0x0 0 0x303303c8>; }; /omit-if-no-ref/ iomuxc_sai1_rxd6_gpio_io_gpio4_io8: IOMUXC_SAI1_RXD6_GPIO_IO_GPIO4_IO8 { pinmux = <0x30330168 5 0x0 0 0x303303c8>; }; /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_rx_data_sai1_rx_data6: IOMUXC_SAI1_RXD6_SAI_RX_DATA_SAI1_RX_DATA6 { pinmux = <0x30330168 0 0x0 0 0x303303c8>; }; /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_rx_sync_sai6_rx_sync: IOMUXC_SAI1_RXD6_SAI_RX_SYNC_SAI6_RX_SYNC { pinmux = <0x30330168 2 0x30330520 1 0x303303c8>; }; /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_tx_sync_sai6_tx_sync: IOMUXC_SAI1_RXD6_SAI_TX_SYNC_SAI6_TX_SYNC { pinmux = <0x30330168 1 0x30330528 1 0x303303c8>; }; /omit-if-no-ref/ iomuxc_sai1_rxd7_enet_rgmii_rd_enet1_rgmii_rd3: IOMUXC_SAI1_RXD7_ENET_RGMII_RD_ENET1_RGMII_RD3 { pinmux = <0x3033016c 4 0x0 0 0x303303cc>; }; /omit-if-no-ref/ iomuxc_sai1_rxd7_gpio_io_gpio4_io9: IOMUXC_SAI1_RXD7_GPIO_IO_GPIO4_IO9 { pinmux = <0x3033016c 5 0x0 0 0x303303cc>; }; /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_mclk_sai6_mclk: IOMUXC_SAI1_RXD7_SAI_MCLK_SAI6_MCLK { pinmux = <0x3033016c 1 0x30330514 1 0x303303cc>; }; /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_rx_data_sai1_rx_data7: IOMUXC_SAI1_RXD7_SAI_RX_DATA_SAI1_RX_DATA7 { pinmux = <0x3033016c 0 0x0 0 0x303303cc>; }; /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_tx_data_sai1_tx_data4: IOMUXC_SAI1_RXD7_SAI_TX_DATA_SAI1_TX_DATA4 { pinmux = <0x3033016c 3 0x0 0 0x303303cc>; }; /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI1_RXD7_SAI_TX_SYNC_SAI1_TX_SYNC { pinmux = <0x3033016c 2 0x303304d8 3 0x303303cc>; }; /omit-if-no-ref/ iomuxc_sai1_rxfs_enet_1588_event0_in_enet1_1588_event0_in: IOMUXC_SAI1_RXFS_ENET_1588_EVENT0_IN_ENET1_1588_EVENT0_IN { pinmux = <0x30330148 4 0x0 0 0x303303a8>; }; /omit-if-no-ref/ iomuxc_sai1_rxfs_gpio_io_gpio4_io0: IOMUXC_SAI1_RXFS_GPIO_IO_GPIO4_IO0 { pinmux = <0x30330148 5 0x0 0 0x303303a8>; }; /omit-if-no-ref/ iomuxc_sai1_rxfs_sai_rx_sync_sai1_rx_sync: IOMUXC_SAI1_RXFS_SAI_RX_SYNC_SAI1_RX_SYNC { pinmux = <0x30330148 0 0x303304d0 0 0x303303a8>; }; /omit-if-no-ref/ iomuxc_sai1_txc_enet_rgmii_rxc_enet1_rgmii_rxc: IOMUXC_SAI1_TXC_ENET_RGMII_RXC_ENET1_RGMII_RXC { pinmux = <0x30330174 4 0x0 0 0x303303d4>; }; /omit-if-no-ref/ iomuxc_sai1_txc_gpio_io_gpio4_io11: IOMUXC_SAI1_TXC_GPIO_IO_GPIO4_IO11 { pinmux = <0x30330174 5 0x0 0 0x303303d4>; }; /omit-if-no-ref/ iomuxc_sai1_txc_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI1_TXC_SAI_TX_BCLK_SAI1_TX_BCLK { pinmux = <0x30330174 0 0x303304d4 1 0x303303d4>; }; /omit-if-no-ref/ iomuxc_sai1_txd0_enet_rgmii_td_enet1_rgmii_td0: IOMUXC_SAI1_TXD0_ENET_RGMII_TD_ENET1_RGMII_TD0 { pinmux = <0x30330178 4 0x0 0 0x303303d8>; }; /omit-if-no-ref/ iomuxc_sai1_txd0_gpio_io_gpio4_io12: IOMUXC_SAI1_TXD0_GPIO_IO_GPIO4_IO12 { pinmux = <0x30330178 5 0x0 0 0x303303d8>; }; /omit-if-no-ref/ iomuxc_sai1_txd0_sai_tx_data_sai1_tx_data0: IOMUXC_SAI1_TXD0_SAI_TX_DATA_SAI1_TX_DATA0 { pinmux = <0x30330178 0 0x0 0 0x303303d8>; }; /omit-if-no-ref/ iomuxc_sai1_txd1_enet_rgmii_td_enet1_rgmii_td1: IOMUXC_SAI1_TXD1_ENET_RGMII_TD_ENET1_RGMII_TD1 { pinmux = <0x3033017c 4 0x0 0 0x303303dc>; }; /omit-if-no-ref/ iomuxc_sai1_txd1_gpio_io_gpio4_io13: IOMUXC_SAI1_TXD1_GPIO_IO_GPIO4_IO13 { pinmux = <0x3033017c 5 0x0 0 0x303303dc>; }; /omit-if-no-ref/ iomuxc_sai1_txd1_sai_tx_data_sai1_tx_data1: IOMUXC_SAI1_TXD1_SAI_TX_DATA_SAI1_TX_DATA1 { pinmux = <0x3033017c 0 0x0 0 0x303303dc>; }; /omit-if-no-ref/ iomuxc_sai1_txd2_enet_rgmii_td_enet1_rgmii_td2: IOMUXC_SAI1_TXD2_ENET_RGMII_TD_ENET1_RGMII_TD2 { pinmux = <0x30330180 4 0x0 0 0x303303e0>; }; /omit-if-no-ref/ iomuxc_sai1_txd2_gpio_io_gpio4_io14: IOMUXC_SAI1_TXD2_GPIO_IO_GPIO4_IO14 { pinmux = <0x30330180 5 0x0 0 0x303303e0>; }; /omit-if-no-ref/ iomuxc_sai1_txd2_sai_tx_data_sai1_tx_data2: IOMUXC_SAI1_TXD2_SAI_TX_DATA_SAI1_TX_DATA2 { pinmux = <0x30330180 0 0x0 0 0x303303e0>; }; /omit-if-no-ref/ iomuxc_sai1_txd3_enet_rgmii_td_enet1_rgmii_td3: IOMUXC_SAI1_TXD3_ENET_RGMII_TD_ENET1_RGMII_TD3 { pinmux = <0x30330184 4 0x0 0 0x303303e4>; }; /omit-if-no-ref/ iomuxc_sai1_txd3_gpio_io_gpio4_io15: IOMUXC_SAI1_TXD3_GPIO_IO_GPIO4_IO15 { pinmux = <0x30330184 5 0x0 0 0x303303e4>; }; /omit-if-no-ref/ iomuxc_sai1_txd3_sai_tx_data_sai1_tx_data3: IOMUXC_SAI1_TXD3_SAI_TX_DATA_SAI1_TX_DATA3 { pinmux = <0x30330184 0 0x0 0 0x303303e4>; }; /omit-if-no-ref/ iomuxc_sai1_txd4_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC_SAI1_TXD4_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { pinmux = <0x30330188 4 0x0 0 0x303303e8>; }; /omit-if-no-ref/ iomuxc_sai1_txd4_gpio_io_gpio4_io16: IOMUXC_SAI1_TXD4_GPIO_IO_GPIO4_IO16 { pinmux = <0x30330188 5 0x0 0 0x303303e8>; }; /omit-if-no-ref/ iomuxc_sai1_txd4_sai_rx_bclk_sai6_rx_bclk: IOMUXC_SAI1_TXD4_SAI_RX_BCLK_SAI6_RX_BCLK { pinmux = <0x30330188 1 0x30330518 2 0x303303e8>; }; /omit-if-no-ref/ iomuxc_sai1_txd4_sai_tx_bclk_sai6_tx_bclk: IOMUXC_SAI1_TXD4_SAI_TX_BCLK_SAI6_TX_BCLK { pinmux = <0x30330188 2 0x30330524 2 0x303303e8>; }; /omit-if-no-ref/ iomuxc_sai1_txd4_sai_tx_data_sai1_tx_data4: IOMUXC_SAI1_TXD4_SAI_TX_DATA_SAI1_TX_DATA4 { pinmux = <0x30330188 0 0x0 0 0x303303e8>; }; /omit-if-no-ref/ iomuxc_sai1_txd5_enet_rgmii_txc_enet1_rgmii_txc: IOMUXC_SAI1_TXD5_ENET_RGMII_TXC_ENET1_RGMII_TXC { pinmux = <0x3033018c 4 0x0 0 0x303303ec>; }; /omit-if-no-ref/ iomuxc_sai1_txd5_gpio_io_gpio4_io17: IOMUXC_SAI1_TXD5_GPIO_IO_GPIO4_IO17 { pinmux = <0x3033018c 5 0x0 0 0x303303ec>; }; /omit-if-no-ref/ iomuxc_sai1_txd5_sai_rx_data_sai6_rx_data0: IOMUXC_SAI1_TXD5_SAI_RX_DATA_SAI6_RX_DATA0 { pinmux = <0x3033018c 1 0x3033051c 2 0x303303ec>; }; /omit-if-no-ref/ iomuxc_sai1_txd5_sai_tx_data_sai1_tx_data5: IOMUXC_SAI1_TXD5_SAI_TX_DATA_SAI1_TX_DATA5 { pinmux = <0x3033018c 0 0x0 0 0x303303ec>; }; /omit-if-no-ref/ iomuxc_sai1_txd5_sai_tx_data_sai6_tx_data0: IOMUXC_SAI1_TXD5_SAI_TX_DATA_SAI6_TX_DATA0 { pinmux = <0x3033018c 2 0x0 0 0x303303ec>; }; /omit-if-no-ref/ iomuxc_sai1_txd6_enet_rx_er_enet1_rx_er: IOMUXC_SAI1_TXD6_ENET_RX_ER_ENET1_RX_ER { pinmux = <0x30330190 4 0x3033058c 1 0x303303f0>; }; /omit-if-no-ref/ iomuxc_sai1_txd6_gpio_io_gpio4_io18: IOMUXC_SAI1_TXD6_GPIO_IO_GPIO4_IO18 { pinmux = <0x30330190 5 0x0 0 0x303303f0>; }; /omit-if-no-ref/ iomuxc_sai1_txd6_sai_rx_sync_sai6_rx_sync: IOMUXC_SAI1_TXD6_SAI_RX_SYNC_SAI6_RX_SYNC { pinmux = <0x30330190 1 0x30330520 2 0x303303f0>; }; /omit-if-no-ref/ iomuxc_sai1_txd6_sai_tx_data_sai1_tx_data6: IOMUXC_SAI1_TXD6_SAI_TX_DATA_SAI1_TX_DATA6 { pinmux = <0x30330190 0 0x0 0 0x303303f0>; }; /omit-if-no-ref/ iomuxc_sai1_txd6_sai_tx_sync_sai6_tx_sync: IOMUXC_SAI1_TXD6_SAI_TX_SYNC_SAI6_TX_SYNC { pinmux = <0x30330190 2 0x30330528 2 0x303303f0>; }; /omit-if-no-ref/ iomuxc_sai1_txd7_enet_tx_er_enet1_tx_er: IOMUXC_SAI1_TXD7_ENET_TX_ER_ENET1_TX_ER { pinmux = <0x30330194 4 0x0 0 0x303303f4>; }; /omit-if-no-ref/ iomuxc_sai1_txd7_gpio_io_gpio4_io19: IOMUXC_SAI1_TXD7_GPIO_IO_GPIO4_IO19 { pinmux = <0x30330194 5 0x0 0 0x303303f4>; }; /omit-if-no-ref/ iomuxc_sai1_txd7_pdm_clk_pdm_clk: IOMUXC_SAI1_TXD7_PDM_CLK_PDM_CLK { pinmux = <0x30330194 3 0x0 0 0x303303f4>; }; /omit-if-no-ref/ iomuxc_sai1_txd7_sai_mclk_sai6_mclk: IOMUXC_SAI1_TXD7_SAI_MCLK_SAI6_MCLK { pinmux = <0x30330194 1 0x30330514 2 0x303303f4>; }; /omit-if-no-ref/ iomuxc_sai1_txd7_sai_tx_data_sai1_tx_data7: IOMUXC_SAI1_TXD7_SAI_TX_DATA_SAI1_TX_DATA7 { pinmux = <0x30330194 0 0x0 0 0x303303f4>; }; /omit-if-no-ref/ iomuxc_sai1_txfs_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC_SAI1_TXFS_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { pinmux = <0x30330170 4 0x30330588 1 0x303303d0>; }; /omit-if-no-ref/ iomuxc_sai1_txfs_gpio_io_gpio4_io10: IOMUXC_SAI1_TXFS_GPIO_IO_GPIO4_IO10 { pinmux = <0x30330170 5 0x0 0 0x303303d0>; }; /omit-if-no-ref/ iomuxc_sai1_txfs_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI1_TXFS_SAI_TX_SYNC_SAI1_TX_SYNC { pinmux = <0x30330170 0 0x303304d8 4 0x303303d0>; }; /omit-if-no-ref/ iomuxc_sai2_mclk_can_rx_can2_rx: IOMUXC_SAI2_MCLK_CAN_RX_CAN2_RX { pinmux = <0x303301b4 3 0x30330550 1 0x30330414>; }; /omit-if-no-ref/ iomuxc_sai2_mclk_enet_qos_1588_event3_aux_in_enet_qos_1588_event3_aux_in: IOMUXC_SAI2_MCLK_ENET_QOS_1588_EVENT3_AUX_IN_ENET_QOS_1588_EVENT3_AUX_IN { pinmux = <0x303301b4 4 0x0 0 0x30330414>; }; /omit-if-no-ref/ iomuxc_sai2_mclk_enet_qos_1588_event3_in_enet_qos_1588_event3_in: IOMUXC_SAI2_MCLK_ENET_QOS_1588_EVENT3_IN_ENET_QOS_1588_EVENT3_IN { pinmux = <0x303301b4 2 0x0 0 0x30330414>; }; /omit-if-no-ref/ iomuxc_sai2_mclk_gpio_io_gpio4_io27: IOMUXC_SAI2_MCLK_GPIO_IO_GPIO4_IO27 { pinmux = <0x303301b4 5 0x0 0 0x30330414>; }; /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai2_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI2_MCLK { pinmux = <0x303301b4 0 0x0 0 0x30330414>; }; /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai3_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI3_MCLK { pinmux = <0x303301b4 6 0x303304e0 1 0x30330414>; }; /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI5_MCLK { pinmux = <0x303301b4 1 0x303304f0 2 0x30330414>; }; /omit-if-no-ref/ iomuxc_sai2_rxc_can_tx_can1_tx: IOMUXC_SAI2_RXC_CAN_TX_CAN1_TX { pinmux = <0x303301a0 3 0x0 0 0x30330400>; }; /omit-if-no-ref/ iomuxc_sai2_rxc_gpio_io_gpio4_io22: IOMUXC_SAI2_RXC_GPIO_IO_GPIO4_IO22 { pinmux = <0x303301a0 5 0x0 0 0x30330400>; }; /omit-if-no-ref/ iomuxc_sai2_rxc_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI2_RXC_PDM_BIT_STREAM_PDM_BIT_STREAM1 { pinmux = <0x303301a0 6 0x303304c4 5 0x30330400>; }; /omit-if-no-ref/ iomuxc_sai2_rxc_sai_rx_bclk_sai2_rx_bclk: IOMUXC_SAI2_RXC_SAI_RX_BCLK_SAI2_RX_BCLK { pinmux = <0x303301a0 0 0x0 0 0x30330400>; }; /omit-if-no-ref/ iomuxc_sai2_rxc_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI2_RXC_SAI_TX_BCLK_SAI5_TX_BCLK { pinmux = <0x303301a0 1 0x3033050c 2 0x30330400>; }; /omit-if-no-ref/ iomuxc_sai2_rxc_uart_rx_uart1_rx: IOMUXC_SAI2_RXC_UART_RX_UART1_RX { pinmux = <0x303301a0 4 0x303305e8 3 0x30330400>; }; /omit-if-no-ref/ iomuxc_sai2_rxc_uart_tx_uart1_rx: IOMUXC_SAI2_RXC_UART_TX_UART1_RX { pinmux = <0x303301a0 4 0x0 0 0x30330400>; }; /omit-if-no-ref/ iomuxc_sai2_rxd0_enet_qos_1588_event2_out_enet_qos_1588_event2_out: IOMUXC_SAI2_RXD0_ENET_QOS_1588_EVENT2_OUT_ENET_QOS_1588_EVENT2_OUT { pinmux = <0x303301a4 2 0x0 0 0x30330404>; }; /omit-if-no-ref/ iomuxc_sai2_rxd0_gpio_io_gpio4_io23: IOMUXC_SAI2_RXD0_GPIO_IO_GPIO4_IO23 { pinmux = <0x303301a4 5 0x0 0 0x30330404>; }; /omit-if-no-ref/ iomuxc_sai2_rxd0_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI2_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM3 { pinmux = <0x303301a4 6 0x303304cc 5 0x30330404>; }; /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_rx_data_sai2_rx_data0: IOMUXC_SAI2_RXD0_SAI_RX_DATA_SAI2_RX_DATA0 { pinmux = <0x303301a4 0 0x0 0 0x30330404>; }; /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_tx_data_sai2_tx_data1: IOMUXC_SAI2_RXD0_SAI_TX_DATA_SAI2_TX_DATA1 { pinmux = <0x303301a4 3 0x0 0 0x30330404>; }; /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_tx_data_sai5_tx_data0: IOMUXC_SAI2_RXD0_SAI_TX_DATA_SAI5_TX_DATA0 { pinmux = <0x303301a4 1 0x0 0 0x30330404>; }; /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_cts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_CTS_B_UART1_RTS_B { pinmux = <0x303301a4 4 0x0 0 0x30330404>; }; /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_rts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_RTS_B_UART1_RTS_B { pinmux = <0x303301a4 4 0x303305e4 2 0x30330404>; }; /omit-if-no-ref/ iomuxc_sai2_rxfs_gpio_io_gpio4_io21: IOMUXC_SAI2_RXFS_GPIO_IO_GPIO4_IO21 { pinmux = <0x3033019c 5 0x0 0 0x303303fc>; }; /omit-if-no-ref/ iomuxc_sai2_rxfs_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI2_RXFS_PDM_BIT_STREAM_PDM_BIT_STREAM2 { pinmux = <0x3033019c 6 0x303304c8 5 0x303303fc>; }; /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_data_sai2_rx_data1: IOMUXC_SAI2_RXFS_SAI_RX_DATA_SAI2_RX_DATA1 { pinmux = <0x3033019c 3 0x303304dc 0 0x303303fc>; }; /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_sync_sai2_rx_sync: IOMUXC_SAI2_RXFS_SAI_RX_SYNC_SAI2_RX_SYNC { pinmux = <0x3033019c 0 0x0 0 0x303303fc>; }; /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_RXFS_SAI_TX_DATA_SAI5_TX_DATA1 { pinmux = <0x3033019c 2 0x0 0 0x303303fc>; }; /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI2_RXFS_SAI_TX_SYNC_SAI5_TX_SYNC { pinmux = <0x3033019c 1 0x30330510 2 0x303303fc>; }; /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_rx_uart1_tx: IOMUXC_SAI2_RXFS_UART_RX_UART1_TX { pinmux = <0x3033019c 4 0x303305e8 2 0x303303fc>; }; /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_tx_uart1_tx: IOMUXC_SAI2_RXFS_UART_TX_UART1_TX { pinmux = <0x3033019c 4 0x0 0 0x303303fc>; }; /omit-if-no-ref/ iomuxc_sai2_txc_can_rx_can1_rx: IOMUXC_SAI2_TXC_CAN_RX_CAN1_RX { pinmux = <0x303301ac 3 0x3033054c 1 0x3033040c>; }; /omit-if-no-ref/ iomuxc_sai2_txc_gpio_io_gpio4_io25: IOMUXC_SAI2_TXC_GPIO_IO_GPIO4_IO25 { pinmux = <0x303301ac 5 0x0 0 0x3033040c>; }; /omit-if-no-ref/ iomuxc_sai2_txc_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI2_TXC_PDM_BIT_STREAM_PDM_BIT_STREAM1 { pinmux = <0x303301ac 6 0x303304c4 6 0x3033040c>; }; /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_bclk_sai2_tx_bclk: IOMUXC_SAI2_TXC_SAI_TX_BCLK_SAI2_TX_BCLK { pinmux = <0x303301ac 0 0x0 0 0x3033040c>; }; /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_data_sai5_tx_data2: IOMUXC_SAI2_TXC_SAI_TX_DATA_SAI5_TX_DATA2 { pinmux = <0x303301ac 1 0x0 0 0x3033040c>; }; /omit-if-no-ref/ iomuxc_sai2_txd0_can_tx_can2_tx: IOMUXC_SAI2_TXD0_CAN_TX_CAN2_TX { pinmux = <0x303301b0 3 0x0 0 0x30330410>; }; /omit-if-no-ref/ iomuxc_sai2_txd0_enet_qos_1588_event2_aux_in_enet_qos_1588_event2_aux_in: IOMUXC_SAI2_TXD0_ENET_QOS_1588_EVENT2_AUX_IN_ENET_QOS_1588_EVENT2_AUX_IN { pinmux = <0x303301b0 4 0x0 0 0x30330410>; }; /omit-if-no-ref/ iomuxc_sai2_txd0_enet_qos_1588_event2_in_enet_qos_1588_event2_in: IOMUXC_SAI2_TXD0_ENET_QOS_1588_EVENT2_IN_ENET_QOS_1588_EVENT2_IN { pinmux = <0x303301b0 2 0x0 0 0x30330410>; }; /omit-if-no-ref/ iomuxc_sai2_txd0_gpio_io_gpio4_io26: IOMUXC_SAI2_TXD0_GPIO_IO_GPIO4_IO26 { pinmux = <0x303301b0 5 0x0 0 0x30330410>; }; /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai2_tx_data0: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI2_TX_DATA0 { pinmux = <0x303301b0 0 0x0 0 0x30330410>; }; /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai5_tx_data3: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI5_TX_DATA3 { pinmux = <0x303301b0 1 0x0 0 0x30330410>; }; /omit-if-no-ref/ iomuxc_sai2_txfs_enet_qos_1588_event3_out_enet_qos_1588_event3_out: IOMUXC_SAI2_TXFS_ENET_QOS_1588_EVENT3_OUT_ENET_QOS_1588_EVENT3_OUT { pinmux = <0x303301a8 2 0x0 0 0x30330408>; }; /omit-if-no-ref/ iomuxc_sai2_txfs_gpio_io_gpio4_io24: IOMUXC_SAI2_TXFS_GPIO_IO_GPIO4_IO24 { pinmux = <0x303301a8 5 0x0 0 0x30330408>; }; /omit-if-no-ref/ iomuxc_sai2_txfs_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI2_TXFS_PDM_BIT_STREAM_PDM_BIT_STREAM2 { pinmux = <0x303301a8 6 0x303304c8 6 0x30330408>; }; /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai2_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI2_TX_DATA1 { pinmux = <0x303301a8 3 0x0 0 0x30330408>; }; /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI5_TX_DATA1 { pinmux = <0x303301a8 1 0x0 0 0x30330408>; }; /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_sync_sai2_tx_sync: IOMUXC_SAI2_TXFS_SAI_TX_SYNC_SAI2_TX_SYNC { pinmux = <0x303301a8 0 0x0 0 0x30330408>; }; /omit-if-no-ref/ iomuxc_sai2_txfs_uart_cts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_CTS_B_UART1_CTS_B { pinmux = <0x303301a8 4 0x0 0 0x30330408>; }; /omit-if-no-ref/ iomuxc_sai2_txfs_uart_rts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_RTS_B_UART1_CTS_B { pinmux = <0x303301a8 4 0x303305e4 3 0x30330408>; }; /omit-if-no-ref/ iomuxc_sai3_mclk_gpio_io_gpio5_io2: IOMUXC_SAI3_MCLK_GPIO_IO_GPIO5_IO2 { pinmux = <0x303301d0 5 0x0 0 0x30330430>; }; /omit-if-no-ref/ iomuxc_sai3_mclk_pwm_out_pwm4_out: IOMUXC_SAI3_MCLK_PWM_OUT_PWM4_OUT { pinmux = <0x303301d0 1 0x0 0 0x30330430>; }; /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai3_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI3_MCLK { pinmux = <0x303301d0 0 0x303304e0 2 0x30330430>; }; /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI5_MCLK { pinmux = <0x303301d0 2 0x303304f0 3 0x30330430>; }; /omit-if-no-ref/ iomuxc_sai3_mclk_spdif_in_spdif1_in: IOMUXC_SAI3_MCLK_SPDIF_IN_SPDIF1_IN { pinmux = <0x303301d0 6 0x30330544 3 0x30330430>; }; /omit-if-no-ref/ iomuxc_sai3_mclk_spdif_out_spdif1_out: IOMUXC_SAI3_MCLK_SPDIF_OUT_SPDIF1_OUT { pinmux = <0x303301d0 4 0x0 0 0x30330430>; }; /omit-if-no-ref/ iomuxc_sai3_rxc_gpio_io_gpio4_io29: IOMUXC_SAI3_RXC_GPIO_IO_GPIO4_IO29 { pinmux = <0x303301bc 5 0x0 0 0x3033041c>; }; /omit-if-no-ref/ iomuxc_sai3_rxc_gpt_clk_gpt1_clk: IOMUXC_SAI3_RXC_GPT_CLK_GPT1_CLK { pinmux = <0x303301bc 3 0x3033059c 0 0x3033041c>; }; /omit-if-no-ref/ iomuxc_sai3_rxc_pdm_clk_pdm_clk: IOMUXC_SAI3_RXC_PDM_CLK_PDM_CLK { pinmux = <0x303301bc 6 0x0 0 0x3033041c>; }; /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai3_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI3_RX_BCLK { pinmux = <0x303301bc 0 0x0 0 0x3033041c>; }; /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { pinmux = <0x303301bc 2 0x303304f4 2 0x3033041c>; }; /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_data_sai2_rx_data2: IOMUXC_SAI3_RXC_SAI_RX_DATA_SAI2_RX_DATA2 { pinmux = <0x303301bc 1 0x0 0 0x3033041c>; }; /omit-if-no-ref/ iomuxc_sai3_rxc_uart_cts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_CTS_B_UART2_CTS_B { pinmux = <0x303301bc 4 0x0 0 0x3033041c>; }; /omit-if-no-ref/ iomuxc_sai3_rxc_uart_rts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_RTS_B_UART2_CTS_B { pinmux = <0x303301bc 4 0x303305ec 2 0x3033041c>; }; /omit-if-no-ref/ iomuxc_sai3_rxd_gpio_io_gpio4_io30: IOMUXC_SAI3_RXD_GPIO_IO_GPIO4_IO30 { pinmux = <0x303301c0 5 0x0 0 0x30330420>; }; /omit-if-no-ref/ iomuxc_sai3_rxd_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI3_RXD_PDM_BIT_STREAM_PDM_BIT_STREAM1 { pinmux = <0x303301c0 6 0x303304c4 7 0x30330420>; }; /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai2_rx_data3: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI2_RX_DATA3 { pinmux = <0x303301c0 1 0x0 0 0x30330420>; }; /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai3_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI3_RX_DATA0 { pinmux = <0x303301c0 0 0x303304e4 1 0x30330420>; }; /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai5_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI5_RX_DATA0 { pinmux = <0x303301c0 2 0x303304f8 2 0x30330420>; }; /omit-if-no-ref/ iomuxc_sai3_rxd_uart_cts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_CTS_B_UART2_RTS_B { pinmux = <0x303301c0 4 0x0 0 0x30330420>; }; /omit-if-no-ref/ iomuxc_sai3_rxd_uart_rts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_RTS_B_UART2_RTS_B { pinmux = <0x303301c0 4 0x303305ec 3 0x30330420>; }; /omit-if-no-ref/ iomuxc_sai3_rxfs_gpio_io_gpio4_io28: IOMUXC_SAI3_RXFS_GPIO_IO_GPIO4_IO28 { pinmux = <0x303301b8 5 0x0 0 0x30330418>; }; /omit-if-no-ref/ iomuxc_sai3_rxfs_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI3_RXFS_PDM_BIT_STREAM_PDM_BIT_STREAM0 { pinmux = <0x303301b8 6 0x303304c0 5 0x30330418>; }; /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_data_sai2_rx_data1: IOMUXC_SAI3_RXFS_SAI_RX_DATA_SAI2_RX_DATA1 { pinmux = <0x303301b8 1 0x303304dc 1 0x30330418>; }; /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_data_sai3_rx_data1: IOMUXC_SAI3_RXFS_SAI_RX_DATA_SAI3_RX_DATA1 { pinmux = <0x303301b8 3 0x0 0 0x30330418>; }; /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai3_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI3_RX_SYNC { pinmux = <0x303301b8 0 0x0 0 0x30330418>; }; /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { pinmux = <0x303301b8 2 0x30330508 2 0x30330418>; }; /omit-if-no-ref/ iomuxc_sai3_rxfs_spdif_in_spdif1_in: IOMUXC_SAI3_RXFS_SPDIF_IN_SPDIF1_IN { pinmux = <0x303301b8 4 0x30330544 2 0x30330418>; }; /omit-if-no-ref/ iomuxc_sai3_txc_gpio_io_gpio5_io0: IOMUXC_SAI3_TXC_GPIO_IO_GPIO5_IO0 { pinmux = <0x303301c8 5 0x0 0 0x30330428>; }; /omit-if-no-ref/ iomuxc_sai3_txc_gpt_capture_gpt1_capture1: IOMUXC_SAI3_TXC_GPT_CAPTURE_GPT1_CAPTURE1 { pinmux = <0x303301c8 3 0x30330594 0 0x30330428>; }; /omit-if-no-ref/ iomuxc_sai3_txc_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI3_TXC_PDM_BIT_STREAM_PDM_BIT_STREAM2 { pinmux = <0x303301c8 6 0x303304c8 7 0x30330428>; }; /omit-if-no-ref/ iomuxc_sai3_txc_sai_rx_data_sai5_rx_data2: IOMUXC_SAI3_TXC_SAI_RX_DATA_SAI5_RX_DATA2 { pinmux = <0x303301c8 2 0x30330500 2 0x30330428>; }; /omit-if-no-ref/ iomuxc_sai3_txc_sai_tx_bclk_sai3_tx_bclk: IOMUXC_SAI3_TXC_SAI_TX_BCLK_SAI3_TX_BCLK { pinmux = <0x303301c8 0 0x303304e8 1 0x30330428>; }; /omit-if-no-ref/ iomuxc_sai3_txc_sai_tx_data_sai2_tx_data2: IOMUXC_SAI3_TXC_SAI_TX_DATA_SAI2_TX_DATA2 { pinmux = <0x303301c8 1 0x0 0 0x30330428>; }; /omit-if-no-ref/ iomuxc_sai3_txc_uart_rx_uart2_tx: IOMUXC_SAI3_TXC_UART_RX_UART2_TX { pinmux = <0x303301c8 4 0x303305f0 5 0x30330428>; }; /omit-if-no-ref/ iomuxc_sai3_txc_uart_tx_uart2_tx: IOMUXC_SAI3_TXC_UART_TX_UART2_TX { pinmux = <0x303301c8 4 0x0 0 0x30330428>; }; /omit-if-no-ref/ iomuxc_sai3_txd_gpio_io_gpio5_io1: IOMUXC_SAI3_TXD_GPIO_IO_GPIO5_IO1 { pinmux = <0x303301cc 5 0x0 0 0x3033042c>; }; /omit-if-no-ref/ iomuxc_sai3_txd_gpt_capture_gpt1_capture2: IOMUXC_SAI3_TXD_GPT_CAPTURE_GPT1_CAPTURE2 { pinmux = <0x303301cc 3 0x30330598 0 0x3033042c>; }; /omit-if-no-ref/ iomuxc_sai3_txd_sai_rx_data_sai5_rx_data3: IOMUXC_SAI3_TXD_SAI_RX_DATA_SAI5_RX_DATA3 { pinmux = <0x303301cc 2 0x30330504 2 0x3033042c>; }; /omit-if-no-ref/ iomuxc_sai3_txd_sai_tx_data_sai2_tx_data3: IOMUXC_SAI3_TXD_SAI_TX_DATA_SAI2_TX_DATA3 { pinmux = <0x303301cc 1 0x0 0 0x3033042c>; }; /omit-if-no-ref/ iomuxc_sai3_txd_sai_tx_data_sai3_tx_data0: IOMUXC_SAI3_TXD_SAI_TX_DATA_SAI3_TX_DATA0 { pinmux = <0x303301cc 0 0x0 0 0x3033042c>; }; /omit-if-no-ref/ iomuxc_sai3_txd_spdif_ext_clk_spdif1_ext_clk: IOMUXC_SAI3_TXD_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { pinmux = <0x303301cc 4 0x30330548 0 0x3033042c>; }; /omit-if-no-ref/ iomuxc_sai3_txfs_gpio_io_gpio4_io31: IOMUXC_SAI3_TXFS_GPIO_IO_GPIO4_IO31 { pinmux = <0x303301c4 5 0x0 0 0x30330424>; }; /omit-if-no-ref/ iomuxc_sai3_txfs_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI3_TXFS_PDM_BIT_STREAM_PDM_BIT_STREAM3 { pinmux = <0x303301c4 6 0x303304cc 6 0x30330424>; }; /omit-if-no-ref/ iomuxc_sai3_txfs_sai_rx_data_sai5_rx_data1: IOMUXC_SAI3_TXFS_SAI_RX_DATA_SAI5_RX_DATA1 { pinmux = <0x303301c4 2 0x303304fc 2 0x30330424>; }; /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_data_sai2_tx_data1: IOMUXC_SAI3_TXFS_SAI_TX_DATA_SAI2_TX_DATA1 { pinmux = <0x303301c4 1 0x0 0 0x30330424>; }; /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_data_sai3_tx_data1: IOMUXC_SAI3_TXFS_SAI_TX_DATA_SAI3_TX_DATA1 { pinmux = <0x303301c4 3 0x0 0 0x30330424>; }; /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_sync_sai3_tx_sync: IOMUXC_SAI3_TXFS_SAI_TX_SYNC_SAI3_TX_SYNC { pinmux = <0x303301c4 0 0x303304ec 1 0x30330424>; }; /omit-if-no-ref/ iomuxc_sai3_txfs_uart_rx_uart2_rx: IOMUXC_SAI3_TXFS_UART_RX_UART2_RX { pinmux = <0x303301c4 4 0x303305f0 4 0x30330424>; }; /omit-if-no-ref/ iomuxc_sai3_txfs_uart_tx_uart2_rx: IOMUXC_SAI3_TXFS_UART_TX_UART2_RX { pinmux = <0x303301c4 4 0x0 0 0x30330424>; }; /omit-if-no-ref/ iomuxc_sai5_mclk_can_rx_can2_rx: IOMUXC_SAI5_MCLK_CAN_RX_CAN2_RX { pinmux = <0x30330144 6 0x30330550 0 0x303303a4>; }; /omit-if-no-ref/ iomuxc_sai5_mclk_gpio_io_gpio3_io25: IOMUXC_SAI5_MCLK_GPIO_IO_GPIO3_IO25 { pinmux = <0x30330144 5 0x0 0 0x303303a4>; }; /omit-if-no-ref/ iomuxc_sai5_mclk_i2c_sda_i2c5_sda: IOMUXC_SAI5_MCLK_I2C_SDA_I2C5_SDA { pinmux = <0x30330144 3 0x303305c8 1 0x303303a4>; }; /omit-if-no-ref/ iomuxc_sai5_mclk_pwm_out_pwm1_out: IOMUXC_SAI5_MCLK_PWM_OUT_PWM1_OUT { pinmux = <0x30330144 2 0x0 0 0x303303a4>; }; /omit-if-no-ref/ iomuxc_sai5_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI5_MCLK_SAI_MCLK_SAI5_MCLK { pinmux = <0x30330144 0 0x303304f0 0 0x303303a4>; }; /omit-if-no-ref/ iomuxc_sai5_mclk_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI5_MCLK_SAI_TX_BCLK_SAI1_TX_BCLK { pinmux = <0x30330144 1 0x303304d4 0 0x303303a4>; }; /omit-if-no-ref/ iomuxc_sai5_rxc_gpio_io_gpio3_io20: IOMUXC_SAI5_RXC_GPIO_IO_GPIO3_IO20 { pinmux = <0x30330130 5 0x0 0 0x30330390>; }; /omit-if-no-ref/ iomuxc_sai5_rxc_i2c_sda_i2c6_sda: IOMUXC_SAI5_RXC_I2C_SDA_I2C6_SDA { pinmux = <0x30330130 3 0x303305d0 1 0x30330390>; }; /omit-if-no-ref/ iomuxc_sai5_rxc_pdm_clk_pdm_clk: IOMUXC_SAI5_RXC_PDM_CLK_PDM_CLK { pinmux = <0x30330130 4 0x0 0 0x30330390>; }; /omit-if-no-ref/ iomuxc_sai5_rxc_pwm_out_pwm3_out: IOMUXC_SAI5_RXC_PWM_OUT_PWM3_OUT { pinmux = <0x30330130 2 0x0 0 0x30330390>; }; /omit-if-no-ref/ iomuxc_sai5_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI5_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { pinmux = <0x30330130 0 0x303304f4 0 0x30330390>; }; /omit-if-no-ref/ iomuxc_sai5_rxc_sai_tx_data_sai1_tx_data1: IOMUXC_SAI5_RXC_SAI_TX_DATA_SAI1_TX_DATA1 { pinmux = <0x30330130 1 0x0 0 0x30330390>; }; /omit-if-no-ref/ iomuxc_sai5_rxd0_gpio_io_gpio3_io21: IOMUXC_SAI5_RXD0_GPIO_IO_GPIO3_IO21 { pinmux = <0x30330134 5 0x0 0 0x30330394>; }; /omit-if-no-ref/ iomuxc_sai5_rxd0_i2c_scl_i2c5_scl: IOMUXC_SAI5_RXD0_I2C_SCL_I2C5_SCL { pinmux = <0x30330134 3 0x303305c4 1 0x30330394>; }; /omit-if-no-ref/ iomuxc_sai5_rxd0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI5_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { pinmux = <0x30330134 4 0x303304c0 3 0x30330394>; }; /omit-if-no-ref/ iomuxc_sai5_rxd0_pwm_out_pwm2_out: IOMUXC_SAI5_RXD0_PWM_OUT_PWM2_OUT { pinmux = <0x30330134 2 0x0 0 0x30330394>; }; /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_rx_data_sai5_rx_data0: IOMUXC_SAI5_RXD0_SAI_RX_DATA_SAI5_RX_DATA0 { pinmux = <0x30330134 0 0x303304f8 0 0x30330394>; }; /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_tx_data_sai1_tx_data2: IOMUXC_SAI5_RXD0_SAI_TX_DATA_SAI1_TX_DATA2 { pinmux = <0x30330134 1 0x0 0 0x30330394>; }; /omit-if-no-ref/ iomuxc_sai5_rxd1_can_tx_can1_tx: IOMUXC_SAI5_RXD1_CAN_TX_CAN1_TX { pinmux = <0x30330138 6 0x0 0 0x30330398>; }; /omit-if-no-ref/ iomuxc_sai5_rxd1_gpio_io_gpio3_io22: IOMUXC_SAI5_RXD1_GPIO_IO_GPIO3_IO22 { pinmux = <0x30330138 5 0x0 0 0x30330398>; }; /omit-if-no-ref/ iomuxc_sai5_rxd1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI5_RXD1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { pinmux = <0x30330138 4 0x303304c4 3 0x30330398>; }; /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_rx_data_sai5_rx_data1: IOMUXC_SAI5_RXD1_SAI_RX_DATA_SAI5_RX_DATA1 { pinmux = <0x30330138 0 0x303304fc 0 0x30330398>; }; /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_data_sai1_tx_data3: IOMUXC_SAI5_RXD1_SAI_TX_DATA_SAI1_TX_DATA3 { pinmux = <0x30330138 1 0x0 0 0x30330398>; }; /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI1_TX_SYNC { pinmux = <0x30330138 2 0x303304d8 0 0x30330398>; }; /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI5_TX_SYNC { pinmux = <0x30330138 3 0x30330510 0 0x30330398>; }; /omit-if-no-ref/ iomuxc_sai5_rxd2_can_rx_can1_rx: IOMUXC_SAI5_RXD2_CAN_RX_CAN1_RX { pinmux = <0x3033013c 6 0x3033054c 0 0x3033039c>; }; /omit-if-no-ref/ iomuxc_sai5_rxd2_gpio_io_gpio3_io23: IOMUXC_SAI5_RXD2_GPIO_IO_GPIO3_IO23 { pinmux = <0x3033013c 5 0x0 0 0x3033039c>; }; /omit-if-no-ref/ iomuxc_sai5_rxd2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI5_RXD2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { pinmux = <0x3033013c 4 0x303304c8 3 0x3033039c>; }; /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_rx_data_sai5_rx_data2: IOMUXC_SAI5_RXD2_SAI_RX_DATA_SAI5_RX_DATA2 { pinmux = <0x3033013c 0 0x30330500 0 0x3033039c>; }; /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI5_RXD2_SAI_TX_BCLK_SAI5_TX_BCLK { pinmux = <0x3033013c 3 0x3033050c 0 0x3033039c>; }; /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_data_sai1_tx_data4: IOMUXC_SAI5_RXD2_SAI_TX_DATA_SAI1_TX_DATA4 { pinmux = <0x3033013c 1 0x0 0 0x3033039c>; }; /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD2_SAI_TX_SYNC_SAI1_TX_SYNC { pinmux = <0x3033013c 2 0x303304d8 1 0x3033039c>; }; /omit-if-no-ref/ iomuxc_sai5_rxd3_can_tx_can2_tx: IOMUXC_SAI5_RXD3_CAN_TX_CAN2_TX { pinmux = <0x30330140 6 0x0 0 0x303303a0>; }; /omit-if-no-ref/ iomuxc_sai5_rxd3_gpio_io_gpio3_io24: IOMUXC_SAI5_RXD3_GPIO_IO_GPIO3_IO24 { pinmux = <0x30330140 5 0x0 0 0x303303a0>; }; /omit-if-no-ref/ iomuxc_sai5_rxd3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI5_RXD3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { pinmux = <0x30330140 4 0x303304cc 3 0x303303a0>; }; /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_rx_data_sai5_rx_data3: IOMUXC_SAI5_RXD3_SAI_RX_DATA_SAI5_RX_DATA3 { pinmux = <0x30330140 0 0x30330504 0 0x303303a0>; }; /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai1_tx_data5: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI1_TX_DATA5 { pinmux = <0x30330140 1 0x0 0 0x303303a0>; }; /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai5_tx_data0: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI5_TX_DATA0 { pinmux = <0x30330140 3 0x0 0 0x303303a0>; }; /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD3_SAI_TX_SYNC_SAI1_TX_SYNC { pinmux = <0x30330140 2 0x303304d8 2 0x303303a0>; }; /omit-if-no-ref/ iomuxc_sai5_rxfs_gpio_io_gpio3_io19: IOMUXC_SAI5_RXFS_GPIO_IO_GPIO3_IO19 { pinmux = <0x3033012c 5 0x0 0 0x3033038c>; }; /omit-if-no-ref/ iomuxc_sai5_rxfs_i2c_scl_i2c6_scl: IOMUXC_SAI5_RXFS_I2C_SCL_I2C6_SCL { pinmux = <0x3033012c 3 0x303305cc 1 0x3033038c>; }; /omit-if-no-ref/ iomuxc_sai5_rxfs_pwm_out_pwm4_out: IOMUXC_SAI5_RXFS_PWM_OUT_PWM4_OUT { pinmux = <0x3033012c 2 0x0 0 0x3033038c>; }; /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI5_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { pinmux = <0x3033012c 0 0x30330508 0 0x3033038c>; }; /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_tx_data_sai1_tx_data0: IOMUXC_SAI5_RXFS_SAI_TX_DATA_SAI1_TX_DATA0 { pinmux = <0x3033012c 1 0x0 0 0x3033038c>; }; /omit-if-no-ref/ iomuxc_sd1_clk_enet_mdc_enet1_mdc: IOMUXC_SD1_CLK_ENET_MDC_ENET1_MDC { pinmux = <0x3033008c 1 0x0 0 0x303302ec>; }; /omit-if-no-ref/ iomuxc_sd1_clk_gpio_io_gpio2_io0: IOMUXC_SD1_CLK_GPIO_IO_GPIO2_IO0 { pinmux = <0x3033008c 5 0x0 0 0x303302ec>; }; /omit-if-no-ref/ iomuxc_sd1_clk_i2c_scl_i2c5_scl: IOMUXC_SD1_CLK_I2C_SCL_I2C5_SCL { pinmux = <0x3033008c 3 0x303305c4 0 0x303302ec>; }; /omit-if-no-ref/ iomuxc_sd1_clk_uart_rx_uart1_tx: IOMUXC_SD1_CLK_UART_RX_UART1_TX { pinmux = <0x3033008c 4 0x303305e8 0 0x303302ec>; }; /omit-if-no-ref/ iomuxc_sd1_clk_uart_tx_uart1_tx: IOMUXC_SD1_CLK_UART_TX_UART1_TX { pinmux = <0x3033008c 4 0x0 0 0x303302ec>; }; /omit-if-no-ref/ iomuxc_sd1_clk_usdhc_clk_usdhc1_clk: IOMUXC_SD1_CLK_USDHC_CLK_USDHC1_CLK { pinmux = <0x3033008c 0 0x0 0 0x303302ec>; }; /omit-if-no-ref/ iomuxc_sd1_cmd_enet_mdio_enet1_mdio: IOMUXC_SD1_CMD_ENET_MDIO_ENET1_MDIO { pinmux = <0x30330090 1 0x3033057c 0 0x303302f0>; }; /omit-if-no-ref/ iomuxc_sd1_cmd_gpio_io_gpio2_io1: IOMUXC_SD1_CMD_GPIO_IO_GPIO2_IO1 { pinmux = <0x30330090 5 0x0 0 0x303302f0>; }; /omit-if-no-ref/ iomuxc_sd1_cmd_i2c_sda_i2c5_sda: IOMUXC_SD1_CMD_I2C_SDA_I2C5_SDA { pinmux = <0x30330090 3 0x303305c8 0 0x303302f0>; }; /omit-if-no-ref/ iomuxc_sd1_cmd_uart_rx_uart1_rx: IOMUXC_SD1_CMD_UART_RX_UART1_RX { pinmux = <0x30330090 4 0x303305e8 1 0x303302f0>; }; /omit-if-no-ref/ iomuxc_sd1_cmd_uart_tx_uart1_rx: IOMUXC_SD1_CMD_UART_TX_UART1_RX { pinmux = <0x30330090 4 0x0 0 0x303302f0>; }; /omit-if-no-ref/ iomuxc_sd1_cmd_usdhc_cmd_usdhc1_cmd: IOMUXC_SD1_CMD_USDHC_CMD_USDHC1_CMD { pinmux = <0x30330090 0 0x0 0 0x303302f0>; }; /omit-if-no-ref/ iomuxc_sd1_data0_enet_rgmii_td_enet1_rgmii_td1: IOMUXC_SD1_DATA0_ENET_RGMII_TD_ENET1_RGMII_TD1 { pinmux = <0x30330094 1 0x0 0 0x303302f4>; }; /omit-if-no-ref/ iomuxc_sd1_data0_gpio_io_gpio2_io2: IOMUXC_SD1_DATA0_GPIO_IO_GPIO2_IO2 { pinmux = <0x30330094 5 0x0 0 0x303302f4>; }; /omit-if-no-ref/ iomuxc_sd1_data0_i2c_scl_i2c6_scl: IOMUXC_SD1_DATA0_I2C_SCL_I2C6_SCL { pinmux = <0x30330094 3 0x303305cc 0 0x303302f4>; }; /omit-if-no-ref/ iomuxc_sd1_data0_uart_cts_b_uart1_rts_b: IOMUXC_SD1_DATA0_UART_CTS_B_UART1_RTS_B { pinmux = <0x30330094 4 0x0 0 0x303302f4>; }; /omit-if-no-ref/ iomuxc_sd1_data0_uart_rts_b_uart1_rts_b: IOMUXC_SD1_DATA0_UART_RTS_B_UART1_RTS_B { pinmux = <0x30330094 4 0x303305e4 0 0x303302f4>; }; /omit-if-no-ref/ iomuxc_sd1_data0_usdhc_data_usdhc1_data0: IOMUXC_SD1_DATA0_USDHC_DATA_USDHC1_DATA0 { pinmux = <0x30330094 0 0x0 0 0x303302f4>; }; /omit-if-no-ref/ iomuxc_sd1_data1_enet_rgmii_td_enet1_rgmii_td0: IOMUXC_SD1_DATA1_ENET_RGMII_TD_ENET1_RGMII_TD0 { pinmux = <0x30330098 1 0x0 0 0x303302f8>; }; /omit-if-no-ref/ iomuxc_sd1_data1_gpio_io_gpio2_io3: IOMUXC_SD1_DATA1_GPIO_IO_GPIO2_IO3 { pinmux = <0x30330098 5 0x0 0 0x303302f8>; }; /omit-if-no-ref/ iomuxc_sd1_data1_i2c_sda_i2c6_sda: IOMUXC_SD1_DATA1_I2C_SDA_I2C6_SDA { pinmux = <0x30330098 3 0x303305d0 0 0x303302f8>; }; /omit-if-no-ref/ iomuxc_sd1_data1_uart_cts_b_uart1_cts_b: IOMUXC_SD1_DATA1_UART_CTS_B_UART1_CTS_B { pinmux = <0x30330098 4 0x0 0 0x303302f8>; }; /omit-if-no-ref/ iomuxc_sd1_data1_uart_rts_b_uart1_cts_b: IOMUXC_SD1_DATA1_UART_RTS_B_UART1_CTS_B { pinmux = <0x30330098 4 0x303305e4 1 0x303302f8>; }; /omit-if-no-ref/ iomuxc_sd1_data1_usdhc_data_usdhc1_data1: IOMUXC_SD1_DATA1_USDHC_DATA_USDHC1_DATA1 { pinmux = <0x30330098 0 0x0 0 0x303302f8>; }; /omit-if-no-ref/ iomuxc_sd1_data2_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC_SD1_DATA2_ENET_RGMII_RD_ENET1_RGMII_RD0 { pinmux = <0x3033009c 1 0x30330580 0 0x303302fc>; }; /omit-if-no-ref/ iomuxc_sd1_data2_gpio_io_gpio2_io4: IOMUXC_SD1_DATA2_GPIO_IO_GPIO2_IO4 { pinmux = <0x3033009c 5 0x0 0 0x303302fc>; }; /omit-if-no-ref/ iomuxc_sd1_data2_i2c_scl_i2c4_scl: IOMUXC_SD1_DATA2_I2C_SCL_I2C4_SCL { pinmux = <0x3033009c 3 0x303305bc 0 0x303302fc>; }; /omit-if-no-ref/ iomuxc_sd1_data2_uart_rx_uart2_tx: IOMUXC_SD1_DATA2_UART_RX_UART2_TX { pinmux = <0x3033009c 4 0x303305f0 0 0x303302fc>; }; /omit-if-no-ref/ iomuxc_sd1_data2_uart_tx_uart2_tx: IOMUXC_SD1_DATA2_UART_TX_UART2_TX { pinmux = <0x3033009c 4 0x0 0 0x303302fc>; }; /omit-if-no-ref/ iomuxc_sd1_data2_usdhc_data_usdhc1_data2: IOMUXC_SD1_DATA2_USDHC_DATA_USDHC1_DATA2 { pinmux = <0x3033009c 0 0x0 0 0x303302fc>; }; /omit-if-no-ref/ iomuxc_sd1_data3_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC_SD1_DATA3_ENET_RGMII_RD_ENET1_RGMII_RD1 { pinmux = <0x303300a0 1 0x30330584 0 0x30330300>; }; /omit-if-no-ref/ iomuxc_sd1_data3_gpio_io_gpio2_io5: IOMUXC_SD1_DATA3_GPIO_IO_GPIO2_IO5 { pinmux = <0x303300a0 5 0x0 0 0x30330300>; }; /omit-if-no-ref/ iomuxc_sd1_data3_i2c_sda_i2c4_sda: IOMUXC_SD1_DATA3_I2C_SDA_I2C4_SDA { pinmux = <0x303300a0 3 0x303305c0 0 0x30330300>; }; /omit-if-no-ref/ iomuxc_sd1_data3_uart_rx_uart2_rx: IOMUXC_SD1_DATA3_UART_RX_UART2_RX { pinmux = <0x303300a0 4 0x303305f0 1 0x30330300>; }; /omit-if-no-ref/ iomuxc_sd1_data3_uart_tx_uart2_rx: IOMUXC_SD1_DATA3_UART_TX_UART2_RX { pinmux = <0x303300a0 4 0x0 0 0x30330300>; }; /omit-if-no-ref/ iomuxc_sd1_data3_usdhc_data_usdhc1_data3: IOMUXC_SD1_DATA3_USDHC_DATA_USDHC1_DATA3 { pinmux = <0x303300a0 0 0x0 0 0x30330300>; }; /omit-if-no-ref/ iomuxc_sd1_data4_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC_SD1_DATA4_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { pinmux = <0x303300a4 1 0x0 0 0x30330304>; }; /omit-if-no-ref/ iomuxc_sd1_data4_gpio_io_gpio2_io6: IOMUXC_SD1_DATA4_GPIO_IO_GPIO2_IO6 { pinmux = <0x303300a4 5 0x0 0 0x30330304>; }; /omit-if-no-ref/ iomuxc_sd1_data4_i2c_scl_i2c1_scl: IOMUXC_SD1_DATA4_I2C_SCL_I2C1_SCL { pinmux = <0x303300a4 3 0x303305a4 0 0x30330304>; }; /omit-if-no-ref/ iomuxc_sd1_data4_uart_cts_b_uart2_rts_b: IOMUXC_SD1_DATA4_UART_CTS_B_UART2_RTS_B { pinmux = <0x303300a4 4 0x0 0 0x30330304>; }; /omit-if-no-ref/ iomuxc_sd1_data4_uart_rts_b_uart2_rts_b: IOMUXC_SD1_DATA4_UART_RTS_B_UART2_RTS_B { pinmux = <0x303300a4 4 0x303305ec 0 0x30330304>; }; /omit-if-no-ref/ iomuxc_sd1_data4_usdhc_data_usdhc1_data4: IOMUXC_SD1_DATA4_USDHC_DATA_USDHC1_DATA4 { pinmux = <0x303300a4 0 0x0 0 0x30330304>; }; /omit-if-no-ref/ iomuxc_sd1_data5_enet_tx_er_enet1_tx_er: IOMUXC_SD1_DATA5_ENET_TX_ER_ENET1_TX_ER { pinmux = <0x303300a8 1 0x0 0 0x30330308>; }; /omit-if-no-ref/ iomuxc_sd1_data5_gpio_io_gpio2_io7: IOMUXC_SD1_DATA5_GPIO_IO_GPIO2_IO7 { pinmux = <0x303300a8 5 0x0 0 0x30330308>; }; /omit-if-no-ref/ iomuxc_sd1_data5_i2c_sda_i2c1_sda: IOMUXC_SD1_DATA5_I2C_SDA_I2C1_SDA { pinmux = <0x303300a8 3 0x303305a8 0 0x30330308>; }; /omit-if-no-ref/ iomuxc_sd1_data5_uart_cts_b_uart2_cts_b: IOMUXC_SD1_DATA5_UART_CTS_B_UART2_CTS_B { pinmux = <0x303300a8 4 0x0 0 0x30330308>; }; /omit-if-no-ref/ iomuxc_sd1_data5_uart_rts_b_uart2_cts_b: IOMUXC_SD1_DATA5_UART_RTS_B_UART2_CTS_B { pinmux = <0x303300a8 4 0x303305ec 1 0x30330308>; }; /omit-if-no-ref/ iomuxc_sd1_data5_usdhc_data_usdhc1_data5: IOMUXC_SD1_DATA5_USDHC_DATA_USDHC1_DATA5 { pinmux = <0x303300a8 0 0x0 0 0x30330308>; }; /omit-if-no-ref/ iomuxc_sd1_data6_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC_SD1_DATA6_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { pinmux = <0x303300ac 1 0x30330588 0 0x3033030c>; }; /omit-if-no-ref/ iomuxc_sd1_data6_gpio_io_gpio2_io8: IOMUXC_SD1_DATA6_GPIO_IO_GPIO2_IO8 { pinmux = <0x303300ac 5 0x0 0 0x3033030c>; }; /omit-if-no-ref/ iomuxc_sd1_data6_i2c_scl_i2c2_scl: IOMUXC_SD1_DATA6_I2C_SCL_I2C2_SCL { pinmux = <0x303300ac 3 0x303305ac 0 0x3033030c>; }; /omit-if-no-ref/ iomuxc_sd1_data6_uart_rx_uart3_tx: IOMUXC_SD1_DATA6_UART_RX_UART3_TX { pinmux = <0x303300ac 4 0x303305f8 0 0x3033030c>; }; /omit-if-no-ref/ iomuxc_sd1_data6_uart_tx_uart3_tx: IOMUXC_SD1_DATA6_UART_TX_UART3_TX { pinmux = <0x303300ac 4 0x0 0 0x3033030c>; }; /omit-if-no-ref/ iomuxc_sd1_data6_usdhc_data_usdhc1_data6: IOMUXC_SD1_DATA6_USDHC_DATA_USDHC1_DATA6 { pinmux = <0x303300ac 0 0x0 0 0x3033030c>; }; /omit-if-no-ref/ iomuxc_sd1_data7_enet_rx_er_enet1_rx_er: IOMUXC_SD1_DATA7_ENET_RX_ER_ENET1_RX_ER { pinmux = <0x303300b0 1 0x3033058c 0 0x30330310>; }; /omit-if-no-ref/ iomuxc_sd1_data7_gpio_io_gpio2_io9: IOMUXC_SD1_DATA7_GPIO_IO_GPIO2_IO9 { pinmux = <0x303300b0 5 0x0 0 0x30330310>; }; /omit-if-no-ref/ iomuxc_sd1_data7_i2c_sda_i2c2_sda: IOMUXC_SD1_DATA7_I2C_SDA_I2C2_SDA { pinmux = <0x303300b0 3 0x303305b0 0 0x30330310>; }; /omit-if-no-ref/ iomuxc_sd1_data7_uart_rx_uart3_rx: IOMUXC_SD1_DATA7_UART_RX_UART3_RX { pinmux = <0x303300b0 4 0x303305f8 1 0x30330310>; }; /omit-if-no-ref/ iomuxc_sd1_data7_uart_tx_uart3_rx: IOMUXC_SD1_DATA7_UART_TX_UART3_RX { pinmux = <0x303300b0 4 0x0 0 0x30330310>; }; /omit-if-no-ref/ iomuxc_sd1_data7_usdhc_data_usdhc1_data7: IOMUXC_SD1_DATA7_USDHC_DATA_USDHC1_DATA7 { pinmux = <0x303300b0 0 0x0 0 0x30330310>; }; /omit-if-no-ref/ iomuxc_sd1_reset_b_enet_tx_clk_enet1_tx_clk: IOMUXC_SD1_RESET_B_ENET_TX_CLK_ENET1_TX_CLK { pinmux = <0x303300b4 1 0x30330578 0 0x30330314>; }; /omit-if-no-ref/ iomuxc_sd1_reset_b_gpio_io_gpio2_io10: IOMUXC_SD1_RESET_B_GPIO_IO_GPIO2_IO10 { pinmux = <0x303300b4 5 0x0 0 0x30330314>; }; /omit-if-no-ref/ iomuxc_sd1_reset_b_i2c_scl_i2c3_scl: IOMUXC_SD1_RESET_B_I2C_SCL_I2C3_SCL { pinmux = <0x303300b4 3 0x303305b4 0 0x30330314>; }; /omit-if-no-ref/ iomuxc_sd1_reset_b_uart_cts_b_uart3_rts_b: IOMUXC_SD1_RESET_B_UART_CTS_B_UART3_RTS_B { pinmux = <0x303300b4 4 0x0 0 0x30330314>; }; /omit-if-no-ref/ iomuxc_sd1_reset_b_uart_rts_b_uart3_rts_b: IOMUXC_SD1_RESET_B_UART_RTS_B_UART3_RTS_B { pinmux = <0x303300b4 4 0x303305f4 0 0x30330314>; }; /omit-if-no-ref/ iomuxc_sd1_reset_b_usdhc_reset_b_usdhc1_reset_b: IOMUXC_SD1_RESET_B_USDHC_RESET_B_USDHC1_RESET_B { pinmux = <0x303300b4 0 0x0 0 0x30330314>; }; /omit-if-no-ref/ iomuxc_sd1_strobe_gpio_io_gpio2_io11: IOMUXC_SD1_STROBE_GPIO_IO_GPIO2_IO11 { pinmux = <0x303300b8 5 0x0 0 0x30330318>; }; /omit-if-no-ref/ iomuxc_sd1_strobe_i2c_sda_i2c3_sda: IOMUXC_SD1_STROBE_I2C_SDA_I2C3_SDA { pinmux = <0x303300b8 3 0x303305b8 0 0x30330318>; }; /omit-if-no-ref/ iomuxc_sd1_strobe_uart_cts_b_uart3_cts_b: IOMUXC_SD1_STROBE_UART_CTS_B_UART3_CTS_B { pinmux = <0x303300b8 4 0x0 0 0x30330318>; }; /omit-if-no-ref/ iomuxc_sd1_strobe_uart_rts_b_uart3_cts_b: IOMUXC_SD1_STROBE_UART_RTS_B_UART3_CTS_B { pinmux = <0x303300b8 4 0x303305f4 1 0x30330318>; }; /omit-if-no-ref/ iomuxc_sd1_strobe_usdhc_strobe_usdhc1_strobe: IOMUXC_SD1_STROBE_USDHC_STROBE_USDHC1_STROBE { pinmux = <0x303300b8 0 0x0 0 0x30330318>; }; /omit-if-no-ref/ iomuxc_sd2_cd_b_gpio_io_gpio2_io12: IOMUXC_SD2_CD_B_GPIO_IO_GPIO2_IO12 { pinmux = <0x303300bc 5 0x0 0 0x3033031c>; }; /omit-if-no-ref/ iomuxc_sd2_cd_b_usdhc_cd_b_usdhc2_cd_b: IOMUXC_SD2_CD_B_USDHC_CD_B_USDHC2_CD_B { pinmux = <0x303300bc 0 0x0 0 0x3033031c>; }; /omit-if-no-ref/ iomuxc_sd2_clk_ecspi_sclk_ecspi2_sclk: IOMUXC_SD2_CLK_ECSPI_SCLK_ECSPI2_SCLK { pinmux = <0x303300c0 2 0x30330568 0 0x30330320>; }; /omit-if-no-ref/ iomuxc_sd2_clk_gpio_io_gpio2_io13: IOMUXC_SD2_CLK_GPIO_IO_GPIO2_IO13 { pinmux = <0x303300c0 5 0x0 0 0x30330320>; }; /omit-if-no-ref/ iomuxc_sd2_clk_uart_rx_uart4_rx: IOMUXC_SD2_CLK_UART_RX_UART4_RX { pinmux = <0x303300c0 3 0x30330600 0 0x30330320>; }; /omit-if-no-ref/ iomuxc_sd2_clk_uart_tx_uart4_rx: IOMUXC_SD2_CLK_UART_TX_UART4_RX { pinmux = <0x303300c0 3 0x0 0 0x30330320>; }; /omit-if-no-ref/ iomuxc_sd2_clk_usdhc_clk_usdhc2_clk: IOMUXC_SD2_CLK_USDHC_CLK_USDHC2_CLK { pinmux = <0x303300c0 0 0x0 0 0x30330320>; }; /omit-if-no-ref/ iomuxc_sd2_cmd_ecspi_mosi_ecspi2_mosi: IOMUXC_SD2_CMD_ECSPI_MOSI_ECSPI2_MOSI { pinmux = <0x303300c4 2 0x30330570 0 0x30330324>; }; /omit-if-no-ref/ iomuxc_sd2_cmd_gpio_io_gpio2_io14: IOMUXC_SD2_CMD_GPIO_IO_GPIO2_IO14 { pinmux = <0x303300c4 5 0x0 0 0x30330324>; }; /omit-if-no-ref/ iomuxc_sd2_cmd_pdm_clk_pdm_clk: IOMUXC_SD2_CMD_PDM_CLK_PDM_CLK { pinmux = <0x303300c4 4 0x0 0 0x30330324>; }; /omit-if-no-ref/ iomuxc_sd2_cmd_uart_rx_uart4_tx: IOMUXC_SD2_CMD_UART_RX_UART4_TX { pinmux = <0x303300c4 3 0x30330600 1 0x30330324>; }; /omit-if-no-ref/ iomuxc_sd2_cmd_uart_tx_uart4_tx: IOMUXC_SD2_CMD_UART_TX_UART4_TX { pinmux = <0x303300c4 3 0x0 0 0x30330324>; }; /omit-if-no-ref/ iomuxc_sd2_cmd_usdhc_cmd_usdhc2_cmd: IOMUXC_SD2_CMD_USDHC_CMD_USDHC2_CMD { pinmux = <0x303300c4 0 0x0 0 0x30330324>; }; /omit-if-no-ref/ iomuxc_sd2_data0_gpio_io_gpio2_io15: IOMUXC_SD2_DATA0_GPIO_IO_GPIO2_IO15 { pinmux = <0x303300c8 5 0x0 0 0x30330328>; }; /omit-if-no-ref/ iomuxc_sd2_data0_i2c_sda_i2c4_sda: IOMUXC_SD2_DATA0_I2C_SDA_I2C4_SDA { pinmux = <0x303300c8 2 0x303305c0 1 0x30330328>; }; /omit-if-no-ref/ iomuxc_sd2_data0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SD2_DATA0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { pinmux = <0x303300c8 4 0x303304c0 2 0x30330328>; }; /omit-if-no-ref/ iomuxc_sd2_data0_uart_rx_uart2_rx: IOMUXC_SD2_DATA0_UART_RX_UART2_RX { pinmux = <0x303300c8 3 0x303305f0 2 0x30330328>; }; /omit-if-no-ref/ iomuxc_sd2_data0_uart_tx_uart2_rx: IOMUXC_SD2_DATA0_UART_TX_UART2_RX { pinmux = <0x303300c8 3 0x0 0 0x30330328>; }; /omit-if-no-ref/ iomuxc_sd2_data0_usdhc_data_usdhc2_data0: IOMUXC_SD2_DATA0_USDHC_DATA_USDHC2_DATA0 { pinmux = <0x303300c8 0 0x0 0 0x30330328>; }; /omit-if-no-ref/ iomuxc_sd2_data1_gpio_io_gpio2_io16: IOMUXC_SD2_DATA1_GPIO_IO_GPIO2_IO16 { pinmux = <0x303300cc 5 0x0 0 0x3033032c>; }; /omit-if-no-ref/ iomuxc_sd2_data1_i2c_scl_i2c4_scl: IOMUXC_SD2_DATA1_I2C_SCL_I2C4_SCL { pinmux = <0x303300cc 2 0x303305bc 1 0x3033032c>; }; /omit-if-no-ref/ iomuxc_sd2_data1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SD2_DATA1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { pinmux = <0x303300cc 4 0x303304c4 2 0x3033032c>; }; /omit-if-no-ref/ iomuxc_sd2_data1_uart_rx_uart2_tx: IOMUXC_SD2_DATA1_UART_RX_UART2_TX { pinmux = <0x303300cc 3 0x303305f0 3 0x3033032c>; }; /omit-if-no-ref/ iomuxc_sd2_data1_uart_tx_uart2_tx: IOMUXC_SD2_DATA1_UART_TX_UART2_TX { pinmux = <0x303300cc 3 0x0 0 0x3033032c>; }; /omit-if-no-ref/ iomuxc_sd2_data1_usdhc_data_usdhc2_data1: IOMUXC_SD2_DATA1_USDHC_DATA_USDHC2_DATA1 { pinmux = <0x303300cc 0 0x0 0 0x3033032c>; }; /omit-if-no-ref/ iomuxc_sd2_data2_ecspi_ss_ecspi2_ss0: IOMUXC_SD2_DATA2_ECSPI_SS_ECSPI2_SS0 { pinmux = <0x303300d0 2 0x30330574 0 0x30330330>; }; /omit-if-no-ref/ iomuxc_sd2_data2_gpio_io_gpio2_io17: IOMUXC_SD2_DATA2_GPIO_IO_GPIO2_IO17 { pinmux = <0x303300d0 5 0x0 0 0x30330330>; }; /omit-if-no-ref/ iomuxc_sd2_data2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SD2_DATA2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { pinmux = <0x303300d0 4 0x303304c8 2 0x30330330>; }; /omit-if-no-ref/ iomuxc_sd2_data2_spdif_out_spdif1_out: IOMUXC_SD2_DATA2_SPDIF_OUT_SPDIF1_OUT { pinmux = <0x303300d0 3 0x0 0 0x30330330>; }; /omit-if-no-ref/ iomuxc_sd2_data2_usdhc_data_usdhc2_data2: IOMUXC_SD2_DATA2_USDHC_DATA_USDHC2_DATA2 { pinmux = <0x303300d0 0 0x0 0 0x30330330>; }; /omit-if-no-ref/ iomuxc_sd2_data3_ecspi_miso_ecspi2_miso: IOMUXC_SD2_DATA3_ECSPI_MISO_ECSPI2_MISO { pinmux = <0x303300d4 2 0x3033056c 0 0x30330334>; }; /omit-if-no-ref/ iomuxc_sd2_data3_gpio_io_gpio2_io18: IOMUXC_SD2_DATA3_GPIO_IO_GPIO2_IO18 { pinmux = <0x303300d4 5 0x0 0 0x30330334>; }; /omit-if-no-ref/ iomuxc_sd2_data3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SD2_DATA3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { pinmux = <0x303300d4 4 0x303304cc 2 0x30330334>; }; /omit-if-no-ref/ iomuxc_sd2_data3_spdif_in_spdif1_in: IOMUXC_SD2_DATA3_SPDIF_IN_SPDIF1_IN { pinmux = <0x303300d4 3 0x30330544 1 0x30330334>; }; /omit-if-no-ref/ iomuxc_sd2_data3_usdhc_data_usdhc2_data3: IOMUXC_SD2_DATA3_USDHC_DATA_USDHC2_DATA3 { pinmux = <0x303300d4 0 0x0 0 0x30330334>; }; /omit-if-no-ref/ iomuxc_sd2_reset_b_gpio_io_gpio2_io19: IOMUXC_SD2_RESET_B_GPIO_IO_GPIO2_IO19 { pinmux = <0x303300d8 5 0x0 0 0x30330338>; }; /omit-if-no-ref/ iomuxc_sd2_reset_b_usdhc_reset_b_usdhc2_reset_b: IOMUXC_SD2_RESET_B_USDHC_RESET_B_USDHC2_RESET_B { pinmux = <0x303300d8 0 0x0 0 0x30330338>; }; /omit-if-no-ref/ iomuxc_sd2_wp_coresight_eventi_coresight_eventi: IOMUXC_SD2_WP_CORESIGHT_EVENTI_CORESIGHT_EVENTI { pinmux = <0x303300dc 6 0x0 0 0x3033033c>; }; /omit-if-no-ref/ iomuxc_sd2_wp_gpio_io_gpio2_io20: IOMUXC_SD2_WP_GPIO_IO_GPIO2_IO20 { pinmux = <0x303300dc 5 0x0 0 0x3033033c>; }; /omit-if-no-ref/ iomuxc_sd2_wp_usdhc_wp_usdhc2_wp: IOMUXC_SD2_WP_USDHC_WP_USDHC2_WP { pinmux = <0x303300dc 0 0x0 0 0x3033033c>; }; /omit-if-no-ref/ iomuxc_spdif_ext_clk_gpio_io_gpio5_io5: IOMUXC_SPDIF_EXT_CLK_GPIO_IO_GPIO5_IO5 { pinmux = <0x303301dc 5 0x0 0 0x3033043c>; }; /omit-if-no-ref/ iomuxc_spdif_ext_clk_gpt_compare_gpt1_compare3: IOMUXC_SPDIF_EXT_CLK_GPT_COMPARE_GPT1_COMPARE3 { pinmux = <0x303301dc 3 0x0 0 0x3033043c>; }; /omit-if-no-ref/ iomuxc_spdif_ext_clk_pwm_out_pwm1_out: IOMUXC_SPDIF_EXT_CLK_PWM_OUT_PWM1_OUT { pinmux = <0x303301dc 1 0x0 0 0x3033043c>; }; /omit-if-no-ref/ iomuxc_spdif_ext_clk_spdif_ext_clk_spdif1_ext_clk: IOMUXC_SPDIF_EXT_CLK_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { pinmux = <0x303301dc 0 0x30330548 1 0x3033043c>; }; /omit-if-no-ref/ iomuxc_spdif_rx_can_rx_can1_rx: IOMUXC_SPDIF_RX_CAN_RX_CAN1_RX { pinmux = <0x303301d8 4 0x3033054c 2 0x30330438>; }; /omit-if-no-ref/ iomuxc_spdif_rx_gpio_io_gpio5_io4: IOMUXC_SPDIF_RX_GPIO_IO_GPIO5_IO4 { pinmux = <0x303301d8 5 0x0 0 0x30330438>; }; /omit-if-no-ref/ iomuxc_spdif_rx_gpt_compare_gpt1_compare2: IOMUXC_SPDIF_RX_GPT_COMPARE_GPT1_COMPARE2 { pinmux = <0x303301d8 3 0x0 0 0x30330438>; }; /omit-if-no-ref/ iomuxc_spdif_rx_i2c_sda_i2c5_sda: IOMUXC_SPDIF_RX_I2C_SDA_I2C5_SDA { pinmux = <0x303301d8 2 0x303305c8 2 0x30330438>; }; /omit-if-no-ref/ iomuxc_spdif_rx_pwm_out_pwm2_out: IOMUXC_SPDIF_RX_PWM_OUT_PWM2_OUT { pinmux = <0x303301d8 1 0x0 0 0x30330438>; }; /omit-if-no-ref/ iomuxc_spdif_rx_spdif_in_spdif1_in: IOMUXC_SPDIF_RX_SPDIF_IN_SPDIF1_IN { pinmux = <0x303301d8 0 0x30330544 4 0x30330438>; }; /omit-if-no-ref/ iomuxc_spdif_tx_can_tx_can1_tx: IOMUXC_SPDIF_TX_CAN_TX_CAN1_TX { pinmux = <0x303301d4 4 0x0 0 0x30330434>; }; /omit-if-no-ref/ iomuxc_spdif_tx_gpio_io_gpio5_io3: IOMUXC_SPDIF_TX_GPIO_IO_GPIO5_IO3 { pinmux = <0x303301d4 5 0x0 0 0x30330434>; }; /omit-if-no-ref/ iomuxc_spdif_tx_gpt_compare_gpt1_compare1: IOMUXC_SPDIF_TX_GPT_COMPARE_GPT1_COMPARE1 { pinmux = <0x303301d4 3 0x0 0 0x30330434>; }; /omit-if-no-ref/ iomuxc_spdif_tx_i2c_scl_i2c5_scl: IOMUXC_SPDIF_TX_I2C_SCL_I2C5_SCL { pinmux = <0x303301d4 2 0x303305c4 2 0x30330434>; }; /omit-if-no-ref/ iomuxc_spdif_tx_pwm_out_pwm3_out: IOMUXC_SPDIF_TX_PWM_OUT_PWM3_OUT { pinmux = <0x303301d4 1 0x0 0 0x30330434>; }; /omit-if-no-ref/ iomuxc_spdif_tx_spdif_out_spdif1_out: IOMUXC_SPDIF_TX_SPDIF_OUT_SPDIF1_OUT { pinmux = <0x303301d4 0 0x0 0 0x30330434>; }; /omit-if-no-ref/ iomuxc_uart1_rxd_ecspi_sclk_ecspi3_sclk: IOMUXC_UART1_RXD_ECSPI_SCLK_ECSPI3_SCLK { pinmux = <0x30330220 1 0x0 0 0x30330480>; }; /omit-if-no-ref/ iomuxc_uart1_rxd_gpio_io_gpio5_io22: IOMUXC_UART1_RXD_GPIO_IO_GPIO5_IO22 { pinmux = <0x30330220 5 0x0 0 0x30330480>; }; /omit-if-no-ref/ iomuxc_uart1_rxd_uart_rx_uart1_rx: IOMUXC_UART1_RXD_UART_RX_UART1_RX { pinmux = <0x30330220 0 0x303305e8 4 0x30330480>; }; /omit-if-no-ref/ iomuxc_uart1_rxd_uart_tx_uart1_rx: IOMUXC_UART1_RXD_UART_TX_UART1_RX { pinmux = <0x30330220 0 0x0 0 0x30330480>; }; /omit-if-no-ref/ iomuxc_uart1_txd_ecspi_mosi_ecspi3_mosi: IOMUXC_UART1_TXD_ECSPI_MOSI_ECSPI3_MOSI { pinmux = <0x30330224 1 0x0 0 0x30330484>; }; /omit-if-no-ref/ iomuxc_uart1_txd_gpio_io_gpio5_io23: IOMUXC_UART1_TXD_GPIO_IO_GPIO5_IO23 { pinmux = <0x30330224 5 0x0 0 0x30330484>; }; /omit-if-no-ref/ iomuxc_uart1_txd_uart_rx_uart1_tx: IOMUXC_UART1_TXD_UART_RX_UART1_TX { pinmux = <0x30330224 0 0x303305e8 5 0x30330484>; }; /omit-if-no-ref/ iomuxc_uart1_txd_uart_tx_uart1_tx: IOMUXC_UART1_TXD_UART_TX_UART1_TX { pinmux = <0x30330224 0 0x0 0 0x30330484>; }; /omit-if-no-ref/ iomuxc_uart2_rxd_ecspi_miso_ecspi3_miso: IOMUXC_UART2_RXD_ECSPI_MISO_ECSPI3_MISO { pinmux = <0x30330228 1 0x0 0 0x30330488>; }; /omit-if-no-ref/ iomuxc_uart2_rxd_gpio_io_gpio5_io24: IOMUXC_UART2_RXD_GPIO_IO_GPIO5_IO24 { pinmux = <0x30330228 5 0x0 0 0x30330488>; }; /omit-if-no-ref/ iomuxc_uart2_rxd_gpt_compare_gpt1_compare3: IOMUXC_UART2_RXD_GPT_COMPARE_GPT1_COMPARE3 { pinmux = <0x30330228 3 0x0 0 0x30330488>; }; /omit-if-no-ref/ iomuxc_uart2_rxd_uart_rx_uart2_rx: IOMUXC_UART2_RXD_UART_RX_UART2_RX { pinmux = <0x30330228 0 0x303305f0 6 0x30330488>; }; /omit-if-no-ref/ iomuxc_uart2_rxd_uart_tx_uart2_rx: IOMUXC_UART2_RXD_UART_TX_UART2_RX { pinmux = <0x30330228 0 0x0 0 0x30330488>; }; /omit-if-no-ref/ iomuxc_uart2_txd_ecspi_ss_ecspi3_ss0: IOMUXC_UART2_TXD_ECSPI_SS_ECSPI3_SS0 { pinmux = <0x3033022c 1 0x0 0 0x3033048c>; }; /omit-if-no-ref/ iomuxc_uart2_txd_gpio_io_gpio5_io25: IOMUXC_UART2_TXD_GPIO_IO_GPIO5_IO25 { pinmux = <0x3033022c 5 0x0 0 0x3033048c>; }; /omit-if-no-ref/ iomuxc_uart2_txd_gpt_compare_gpt1_compare2: IOMUXC_UART2_TXD_GPT_COMPARE_GPT1_COMPARE2 { pinmux = <0x3033022c 3 0x0 0 0x3033048c>; }; /omit-if-no-ref/ iomuxc_uart2_txd_uart_rx_uart2_tx: IOMUXC_UART2_TXD_UART_RX_UART2_TX { pinmux = <0x3033022c 0 0x303305f0 7 0x3033048c>; }; /omit-if-no-ref/ iomuxc_uart2_txd_uart_tx_uart2_tx: IOMUXC_UART2_TXD_UART_TX_UART2_TX { pinmux = <0x3033022c 0 0x0 0 0x3033048c>; }; /omit-if-no-ref/ iomuxc_uart3_rxd_can_tx_can2_tx: IOMUXC_UART3_RXD_CAN_TX_CAN2_TX { pinmux = <0x30330230 4 0x0 0 0x30330490>; }; /omit-if-no-ref/ iomuxc_uart3_rxd_gpio_io_gpio5_io26: IOMUXC_UART3_RXD_GPIO_IO_GPIO5_IO26 { pinmux = <0x30330230 5 0x0 0 0x30330490>; }; /omit-if-no-ref/ iomuxc_uart3_rxd_gpt_capture_gpt1_capture2: IOMUXC_UART3_RXD_GPT_CAPTURE_GPT1_CAPTURE2 { pinmux = <0x30330230 3 0x30330598 1 0x30330490>; }; /omit-if-no-ref/ iomuxc_uart3_rxd_uart_cts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_CTS_B_UART1_CTS_B { pinmux = <0x30330230 1 0x0 0 0x30330490>; }; /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_RTS_B_UART1_CTS_B { pinmux = <0x30330230 1 0x303305e4 4 0x30330490>; }; /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rx_uart3_rx: IOMUXC_UART3_RXD_UART_RX_UART3_RX { pinmux = <0x30330230 0 0x303305f8 6 0x30330490>; }; /omit-if-no-ref/ iomuxc_uart3_rxd_uart_tx_uart3_rx: IOMUXC_UART3_RXD_UART_TX_UART3_RX { pinmux = <0x30330230 0 0x0 0 0x30330490>; }; /omit-if-no-ref/ iomuxc_uart3_rxd_usdhc_reset_b_usdhc3_reset_b: IOMUXC_UART3_RXD_USDHC_RESET_B_USDHC3_RESET_B { pinmux = <0x30330230 2 0x0 0 0x30330490>; }; /omit-if-no-ref/ iomuxc_uart3_txd_can_rx_can2_rx: IOMUXC_UART3_TXD_CAN_RX_CAN2_RX { pinmux = <0x30330234 4 0x30330550 2 0x30330494>; }; /omit-if-no-ref/ iomuxc_uart3_txd_gpio_io_gpio5_io27: IOMUXC_UART3_TXD_GPIO_IO_GPIO5_IO27 { pinmux = <0x30330234 5 0x0 0 0x30330494>; }; /omit-if-no-ref/ iomuxc_uart3_txd_gpt_clk_gpt1_clk: IOMUXC_UART3_TXD_GPT_CLK_GPT1_CLK { pinmux = <0x30330234 3 0x3033059c 1 0x30330494>; }; /omit-if-no-ref/ iomuxc_uart3_txd_uart_cts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_CTS_B_UART1_RTS_B { pinmux = <0x30330234 1 0x0 0 0x30330494>; }; /omit-if-no-ref/ iomuxc_uart3_txd_uart_rts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_RTS_B_UART1_RTS_B { pinmux = <0x30330234 1 0x303305e4 5 0x30330494>; }; /omit-if-no-ref/ iomuxc_uart3_txd_uart_rx_uart3_tx: IOMUXC_UART3_TXD_UART_RX_UART3_TX { pinmux = <0x30330234 0 0x303305f8 7 0x30330494>; }; /omit-if-no-ref/ iomuxc_uart3_txd_uart_tx_uart3_tx: IOMUXC_UART3_TXD_UART_TX_UART3_TX { pinmux = <0x30330234 0 0x0 0 0x30330494>; }; /omit-if-no-ref/ iomuxc_uart3_txd_usdhc_vselect_usdhc3_vselect: IOMUXC_UART3_TXD_USDHC_VSELECT_USDHC3_VSELECT { pinmux = <0x30330234 2 0x0 0 0x30330494>; }; /omit-if-no-ref/ iomuxc_uart4_rxd_gpio_io_gpio5_io28: IOMUXC_UART4_RXD_GPIO_IO_GPIO5_IO28 { pinmux = <0x30330238 5 0x0 0 0x30330498>; }; /omit-if-no-ref/ iomuxc_uart4_rxd_gpt_compare_gpt1_compare1: IOMUXC_UART4_RXD_GPT_COMPARE_GPT1_COMPARE1 { pinmux = <0x30330238 3 0x0 0 0x30330498>; }; /omit-if-no-ref/ iomuxc_uart4_rxd_i2c_scl_i2c6_scl: IOMUXC_UART4_RXD_I2C_SCL_I2C6_SCL { pinmux = <0x30330238 4 0x303305cc 2 0x30330498>; }; /omit-if-no-ref/ iomuxc_uart4_rxd_pcie_clkreq_b_pcie1_clkreq_b: IOMUXC_UART4_RXD_PCIE_CLKREQ_B_PCIE1_CLKREQ_B { pinmux = <0x30330238 2 0x303305a0 1 0x30330498>; }; /omit-if-no-ref/ iomuxc_uart4_rxd_uart_cts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_CTS_B_UART2_CTS_B { pinmux = <0x30330238 1 0x0 0 0x30330498>; }; /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_RTS_B_UART2_CTS_B { pinmux = <0x30330238 1 0x303305ec 4 0x30330498>; }; /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rx_uart4_rx: IOMUXC_UART4_RXD_UART_RX_UART4_RX { pinmux = <0x30330238 0 0x30330600 8 0x30330498>; }; /omit-if-no-ref/ iomuxc_uart4_rxd_uart_tx_uart4_rx: IOMUXC_UART4_RXD_UART_TX_UART4_RX { pinmux = <0x30330238 0 0x0 0 0x30330498>; }; /omit-if-no-ref/ iomuxc_uart4_txd_gpio_io_gpio5_io29: IOMUXC_UART4_TXD_GPIO_IO_GPIO5_IO29 { pinmux = <0x3033023c 5 0x0 0 0x3033049c>; }; /omit-if-no-ref/ iomuxc_uart4_txd_gpt_capture_gpt1_capture1: IOMUXC_UART4_TXD_GPT_CAPTURE_GPT1_CAPTURE1 { pinmux = <0x3033023c 3 0x30330594 1 0x3033049c>; }; /omit-if-no-ref/ iomuxc_uart4_txd_i2c_sda_i2c6_sda: IOMUXC_UART4_TXD_I2C_SDA_I2C6_SDA { pinmux = <0x3033023c 4 0x303305d0 2 0x3033049c>; }; /omit-if-no-ref/ iomuxc_uart4_txd_uart_cts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_CTS_B_UART2_RTS_B { pinmux = <0x3033023c 1 0x0 0 0x3033049c>; }; /omit-if-no-ref/ iomuxc_uart4_txd_uart_rts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_RTS_B_UART2_RTS_B { pinmux = <0x3033023c 1 0x303305ec 5 0x3033049c>; }; /omit-if-no-ref/ iomuxc_uart4_txd_uart_rx_uart4_tx: IOMUXC_UART4_TXD_UART_RX_UART4_TX { pinmux = <0x3033023c 0 0x30330600 9 0x3033049c>; }; /omit-if-no-ref/ iomuxc_uart4_txd_uart_tx_uart4_tx: IOMUXC_UART4_TXD_UART_TX_UART4_TX { pinmux = <0x3033023c 0 0x0 0 0x3033049c>; }; };