1/*
2 * NOTE: Autogenerated file by kinetis_signal2dts.py
3 *       for MKW24D512VHA5/signal_configuration.xml
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8/*
9 * Pin nodes are of the form:
10 *
11 *	<SIGNAL[0..n]>: <signal[0]> {
12 *		nxp,kinetis-port-pins = < PIN PCR[MUX] >;
13 *	};
14 */
15
16&porta {
17	PTA0: GPIOA_PTA0: gpioa_pta0 {
18		nxp,kinetis-port-pins = < 0 1 >;
19	};
20	UART0_CTS_b_PTA0: UART0_COL_b_PTA0: uart0_cts_b_pta0 {
21		nxp,kinetis-port-pins = < 0 2 >;
22	};
23	FTM0_CH5_PTA0: ftm0_ch5_pta0 {
24		nxp,kinetis-port-pins = < 0 3 >;
25	};
26	JTAG_TCLK_PTA0: SWD_CLK_PTA0: jtag_tclk_pta0 {
27		nxp,kinetis-port-pins = < 0 7 >;
28	};
29	PTA1: GPIOA_PTA1: gpioa_pta1 {
30		nxp,kinetis-port-pins = < 1 1 >;
31	};
32	UART0_RX_PTA1: uart0_rx_pta1 {
33		nxp,kinetis-port-pins = < 1 2 >;
34	};
35	FTM0_CH6_PTA1: ftm0_ch6_pta1 {
36		nxp,kinetis-port-pins = < 1 3 >;
37	};
38	JTAG_TDI_PTA1: jtag_tdi_pta1 {
39		nxp,kinetis-port-pins = < 1 7 >;
40	};
41	PTA2: GPIOA_PTA2: gpioa_pta2 {
42		nxp,kinetis-port-pins = < 2 1 >;
43	};
44	UART0_TX_PTA2: uart0_tx_pta2 {
45		nxp,kinetis-port-pins = < 2 2 >;
46	};
47	FTM0_CH7_PTA2: ftm0_ch7_pta2 {
48		nxp,kinetis-port-pins = < 2 3 >;
49	};
50	JTAG_TDO_PTA2: TRACE_SWO_PTA2: jtag_tdo_pta2 {
51		nxp,kinetis-port-pins = < 2 7 >;
52	};
53	PTA3: GPIOA_PTA3: gpioa_pta3 {
54		nxp,kinetis-port-pins = < 3 1 >;
55	};
56	UART0_RTS_b_PTA3: uart0_rts_b_pta3 {
57		nxp,kinetis-port-pins = < 3 2 >;
58	};
59	FTM0_CH0_PTA3: ftm0_ch0_pta3 {
60		nxp,kinetis-port-pins = < 3 3 >;
61	};
62	JTAG_TMS_PTA3: SWD_DIO_PTA3: jtag_tms_pta3 {
63		nxp,kinetis-port-pins = < 3 7 >;
64	};
65	PTA4: GPIOA_PTA4: LLWU_P3_PTA4: gpioa_pta4 {
66		nxp,kinetis-port-pins = < 4 1 >;
67	};
68	FTM0_CH1_PTA4: ftm0_ch1_pta4 {
69		nxp,kinetis-port-pins = < 4 3 >;
70	};
71	NMI_b_PTA4: nmi_b_pta4 {
72		nxp,kinetis-port-pins = < 4 7 >;
73	};
74	EXTAL0_PTA18: extal0_pta18 {
75		nxp,kinetis-port-pins = < 18 0 >;
76	};
77	PTA18: GPIOA_PTA18: gpioa_pta18 {
78		nxp,kinetis-port-pins = < 18 1 >;
79	};
80	FTM0_FLT2_PTA18: ftm0_flt2_pta18 {
81		nxp,kinetis-port-pins = < 18 3 >;
82	};
83	FTM_CLKIN0_PTA18: ftm_clkin0_pta18 {
84		nxp,kinetis-port-pins = < 18 4 >;
85	};
86	XTAL0_PTA19: xtal0_pta19 {
87		nxp,kinetis-port-pins = < 19 0 >;
88	};
89	PTA19: GPIOA_PTA19: gpioa_pta19 {
90		nxp,kinetis-port-pins = < 19 1 >;
91	};
92	FTM1_FLT0_PTA19: ftm1_flt0_pta19 {
93		nxp,kinetis-port-pins = < 19 3 >;
94	};
95	FTM_CLKIN1_PTA19: ftm_clkin1_pta19 {
96		nxp,kinetis-port-pins = < 19 4 >;
97	};
98	LPTMR0_ALT1_PTA19: lptmr0_alt1_pta19 {
99		nxp,kinetis-port-pins = < 19 6 >;
100	};
101};
102
103&portc {
104	PTC4: GPIOC_PTC4: LLWU_P8_PTC4: gpioc_ptc4 {
105		nxp,kinetis-port-pins = < 4 1 >;
106	};
107	SPI0_PCS0_PTC4: spi0_pcs0_ptc4 {
108		nxp,kinetis-port-pins = < 4 2 >;
109	};
110	UART1_TX_PTC4: uart1_tx_ptc4 {
111		nxp,kinetis-port-pins = < 4 3 >;
112	};
113	FTM0_CH3_PTC4: ftm0_ch3_ptc4 {
114		nxp,kinetis-port-pins = < 4 4 >;
115	};
116	CMP1_OUT_PTC4: cmp1_out_ptc4 {
117		nxp,kinetis-port-pins = < 4 6 >;
118	};
119	PTC5: GPIOC_PTC5: LLWU_P9_PTC5: gpioc_ptc5 {
120		nxp,kinetis-port-pins = < 5 1 >;
121	};
122	SPI0_SCK_PTC5: spi0_sck_ptc5 {
123		nxp,kinetis-port-pins = < 5 2 >;
124	};
125	LPTMR0_ALT2_PTC5: lptmr0_alt2_ptc5 {
126		nxp,kinetis-port-pins = < 5 3 >;
127	};
128	I2S0_RXD0_PTC5: i2s0_rxd0_ptc5 {
129		nxp,kinetis-port-pins = < 5 4 >;
130	};
131	CMP0_OUT_PTC5: cmp0_out_ptc5 {
132		nxp,kinetis-port-pins = < 5 6 >;
133	};
134	CMP0_IN0_PTC6: cmp0_in0_ptc6 {
135		nxp,kinetis-port-pins = < 6 0 >;
136	};
137	PTC6: GPIOC_PTC6: LLWU_P10_PTC6: gpioc_ptc6 {
138		nxp,kinetis-port-pins = < 6 1 >;
139	};
140	SPI0_SOUT_PTC6: spi0_sout_ptc6 {
141		nxp,kinetis-port-pins = < 6 2 >;
142	};
143	PDB0_EXTRG_PTC6: pdb0_extrg_ptc6 {
144		nxp,kinetis-port-pins = < 6 3 >;
145	};
146	I2S0_RX_BCLK_PTC6: i2s0_rx_bclk_ptc6 {
147		nxp,kinetis-port-pins = < 6 4 >;
148	};
149	I2S0_MCLK_PTC6: i2s0_mclk_ptc6 {
150		nxp,kinetis-port-pins = < 6 6 >;
151	};
152	CMP0_IN1_PTC7: cmp0_in1_ptc7 {
153		nxp,kinetis-port-pins = < 7 0 >;
154	};
155	PTC7: GPIOC_PTC7: gpioc_ptc7 {
156		nxp,kinetis-port-pins = < 7 1 >;
157	};
158	SPI0_SIN_PTC7: spi0_sin_ptc7 {
159		nxp,kinetis-port-pins = < 7 2 >;
160	};
161	USB_SOF_OUT_PTC7: usb_sof_out_ptc7 {
162		nxp,kinetis-port-pins = < 7 3 >;
163	};
164	I2S0_RX_FS_PTC7: i2s0_rx_fs_ptc7 {
165		nxp,kinetis-port-pins = < 7 4 >;
166	};
167};
168
169&portd {
170	ADC0_SE5b_PTD1: adc0_se5b_ptd1 {
171		nxp,kinetis-port-pins = < 1 0 >;
172	};
173	PTD1: GPIOD_PTD1: gpiod_ptd1 {
174		nxp,kinetis-port-pins = < 1 1 >;
175	};
176	SPI0_SCK_PTD1: spi0_sck_ptd1 {
177		nxp,kinetis-port-pins = < 1 2 >;
178	};
179	UART2_CTS_b_PTD1: uart2_cts_b_ptd1 {
180		nxp,kinetis-port-pins = < 1 3 >;
181	};
182	PTD2: GPIOD_PTD2: LLWU_P13_PTD2: gpiod_ptd2 {
183		nxp,kinetis-port-pins = < 2 1 >;
184	};
185	SPI0_SOUT_PTD2: spi0_sout_ptd2 {
186		nxp,kinetis-port-pins = < 2 2 >;
187	};
188	UART2_RX_PTD2: uart2_rx_ptd2 {
189		nxp,kinetis-port-pins = < 2 3 >;
190	};
191	I2C0_SCL_PTD2: i2c0_scl_ptd2 {
192		nxp,kinetis-port-pins = < 2 4 >;
193	};
194	PTD3: GPIOD_PTD3: gpiod_ptd3 {
195		nxp,kinetis-port-pins = < 3 1 >;
196	};
197	SPI0_SIN_PTD3: spi0_sin_ptd3 {
198		nxp,kinetis-port-pins = < 3 2 >;
199	};
200	UART2_TX_PTD3: uart2_tx_ptd3 {
201		nxp,kinetis-port-pins = < 3 3 >;
202	};
203	I2C0_SDA_PTD3: i2c0_sda_ptd3 {
204		nxp,kinetis-port-pins = < 3 4 >;
205	};
206	ADC0_SE21_PTD4: adc0_se21_ptd4 {
207		nxp,kinetis-port-pins = < 4 0 >;
208	};
209	PTD4: GPIOD_PTD4: LLWU_P14_PTD4: gpiod_ptd4 {
210		nxp,kinetis-port-pins = < 4 1 >;
211	};
212	SPI0_PCS1_PTD4: spi0_pcs1_ptd4 {
213		nxp,kinetis-port-pins = < 4 2 >;
214	};
215	UART0_RTS_b_PTD4: uart0_rts_b_ptd4 {
216		nxp,kinetis-port-pins = < 4 3 >;
217	};
218	FTM0_CH4_PTD4: ftm0_ch4_ptd4 {
219		nxp,kinetis-port-pins = < 4 4 >;
220	};
221	EWM_IN_PTD4: ewm_in_ptd4 {
222		nxp,kinetis-port-pins = < 4 6 >;
223	};
224	ADC0_SE6b_PTD5: adc0_se6b_ptd5 {
225		nxp,kinetis-port-pins = < 5 0 >;
226	};
227	PTD5: GPIOD_PTD5: gpiod_ptd5 {
228		nxp,kinetis-port-pins = < 5 1 >;
229	};
230	SPI0_PCS2_PTD5: spi0_pcs2_ptd5 {
231		nxp,kinetis-port-pins = < 5 2 >;
232	};
233	UART0_CTS_b_PTD5: UART0_COL_b_PTD5: uart0_cts_b_ptd5 {
234		nxp,kinetis-port-pins = < 5 3 >;
235	};
236	FTM0_CH5_PTD5: ftm0_ch5_ptd5 {
237		nxp,kinetis-port-pins = < 5 4 >;
238	};
239	EWM_OUT_b_PTD5: ewm_out_b_ptd5 {
240		nxp,kinetis-port-pins = < 5 6 >;
241	};
242	ADC0_SE7b_PTD6: adc0_se7b_ptd6 {
243		nxp,kinetis-port-pins = < 6 0 >;
244	};
245	PTD6: GPIOD_PTD6: LLWU_P15_PTD6: gpiod_ptd6 {
246		nxp,kinetis-port-pins = < 6 1 >;
247	};
248	SPI0_PCS3_PTD6: spi0_pcs3_ptd6 {
249		nxp,kinetis-port-pins = < 6 2 >;
250	};
251	UART0_RX_PTD6: uart0_rx_ptd6 {
252		nxp,kinetis-port-pins = < 6 3 >;
253	};
254	FTM0_CH6_PTD6: ftm0_ch6_ptd6 {
255		nxp,kinetis-port-pins = < 6 4 >;
256	};
257	FTM0_FLT0_PTD6: ftm0_flt0_ptd6 {
258		nxp,kinetis-port-pins = < 6 6 >;
259	};
260	ADC0_SE22_PTD7: adc0_se22_ptd7 {
261		nxp,kinetis-port-pins = < 7 0 >;
262	};
263	PTD7: GPIOD_PTD7: gpiod_ptd7 {
264		nxp,kinetis-port-pins = < 7 1 >;
265	};
266	CMT_IRO_PTD7: cmt_iro_ptd7 {
267		nxp,kinetis-port-pins = < 7 2 >;
268	};
269	UART0_TX_PTD7: uart0_tx_ptd7 {
270		nxp,kinetis-port-pins = < 7 3 >;
271	};
272	FTM0_CH7_PTD7: ftm0_ch7_ptd7 {
273		nxp,kinetis-port-pins = < 7 4 >;
274	};
275	FTM0_FLT1_PTD7: ftm0_flt1_ptd7 {
276		nxp,kinetis-port-pins = < 7 6 >;
277	};
278};
279
280&porte {
281	ADC0_SE10_PTE0: adc0_se10_pte0 {
282		nxp,kinetis-port-pins = < 0 0 >;
283	};
284	PTE0: GPIOE_PTE0: gpioe_pte0 {
285		nxp,kinetis-port-pins = < 0 1 >;
286	};
287	SPI1_PCS1_PTE0: spi1_pcs1_pte0 {
288		nxp,kinetis-port-pins = < 0 2 >;
289	};
290	UART1_TX_PTE0: uart1_tx_pte0 {
291		nxp,kinetis-port-pins = < 0 3 >;
292	};
293	TRACE_CLKOUT_PTE0: trace_clkout_pte0 {
294		nxp,kinetis-port-pins = < 0 5 >;
295	};
296	I2C1_SDA_PTE0: i2c1_sda_pte0 {
297		nxp,kinetis-port-pins = < 0 6 >;
298	};
299	RTC_CLKOUT_PTE0: rtc_clkout_pte0 {
300		nxp,kinetis-port-pins = < 0 7 >;
301	};
302	ADC0_SE11_PTE1: adc0_se11_pte1 {
303		nxp,kinetis-port-pins = < 1 0 >;
304	};
305	PTE1: GPIOE_PTE1: LLWU_P0_PTE1: gpioe_pte1 {
306		nxp,kinetis-port-pins = < 1 1 >;
307	};
308	SPI1_SOUT_PTE1: spi1_sout_pte1 {
309		nxp,kinetis-port-pins = < 1 2 >;
310	};
311	UART1_RX_PTE1: uart1_rx_pte1 {
312		nxp,kinetis-port-pins = < 1 3 >;
313	};
314	TRACE_D3_PTE1: trace_d3_pte1 {
315		nxp,kinetis-port-pins = < 1 5 >;
316	};
317	I2C1_SCL_PTE1: i2c1_scl_pte1 {
318		nxp,kinetis-port-pins = < 1 6 >;
319	};
320	SPI1_SIN_PTE1: spi1_sin_pte1 {
321		nxp,kinetis-port-pins = < 1 7 >;
322	};
323	ADC0_DP1_PTE2: adc0_dp1_pte2 {
324		nxp,kinetis-port-pins = < 2 0 >;
325	};
326	PTE2: GPIOE_PTE2: LLWU_P1_PTE2: gpioe_pte2 {
327		nxp,kinetis-port-pins = < 2 1 >;
328	};
329	SPI1_SCK_PTE2: spi1_sck_pte2 {
330		nxp,kinetis-port-pins = < 2 2 >;
331	};
332	UART1_CTS_b_PTE2: uart1_cts_b_pte2 {
333		nxp,kinetis-port-pins = < 2 3 >;
334	};
335	TRACE_D2_PTE2: trace_d2_pte2 {
336		nxp,kinetis-port-pins = < 2 5 >;
337	};
338	ADC0_DM1_PTE3: adc0_dm1_pte3 {
339		nxp,kinetis-port-pins = < 3 0 >;
340	};
341	PTE3: GPIOE_PTE3: gpioe_pte3 {
342		nxp,kinetis-port-pins = < 3 1 >;
343	};
344	SPI1_SIN_PTE3: spi1_sin_pte3 {
345		nxp,kinetis-port-pins = < 3 2 >;
346	};
347	UART1_RTS_b_PTE3: uart1_rts_b_pte3 {
348		nxp,kinetis-port-pins = < 3 3 >;
349	};
350	TRACE_D1_PTE3: trace_d1_pte3 {
351		nxp,kinetis-port-pins = < 3 5 >;
352	};
353	SPI1_SOUT_PTE3: spi1_sout_pte3 {
354		nxp,kinetis-port-pins = < 3 7 >;
355	};
356	PTE4: GPIOE_PTE4: LLWU_P2_PTE4: gpioe_pte4 {
357		nxp,kinetis-port-pins = < 4 1 >;
358	};
359	SPI1_PCS0_PTE4: spi1_pcs0_pte4 {
360		nxp,kinetis-port-pins = < 4 2 >;
361	};
362	TRACE_D0_PTE4: trace_d0_pte4 {
363		nxp,kinetis-port-pins = < 4 5 >;
364	};
365};
366
367