/*
 * NOTE: Autogenerated file by kinetis_signal2dts.py
 *       for MKW24D512VHA5/signal_configuration.xml
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/*
 * Pin nodes are of the form:
 *
 *	<SIGNAL[0..n]>: <signal[0]> {
 *		nxp,kinetis-port-pins = < PIN PCR[MUX] >;
 *	};
 */

&porta {
	PTA0: GPIOA_PTA0: gpioa_pta0 {
		nxp,kinetis-port-pins = < 0 1 >;
	};
	UART0_CTS_b_PTA0: UART0_COL_b_PTA0: uart0_cts_b_pta0 {
		nxp,kinetis-port-pins = < 0 2 >;
	};
	FTM0_CH5_PTA0: ftm0_ch5_pta0 {
		nxp,kinetis-port-pins = < 0 3 >;
	};
	JTAG_TCLK_PTA0: SWD_CLK_PTA0: jtag_tclk_pta0 {
		nxp,kinetis-port-pins = < 0 7 >;
	};
	PTA1: GPIOA_PTA1: gpioa_pta1 {
		nxp,kinetis-port-pins = < 1 1 >;
	};
	UART0_RX_PTA1: uart0_rx_pta1 {
		nxp,kinetis-port-pins = < 1 2 >;
	};
	FTM0_CH6_PTA1: ftm0_ch6_pta1 {
		nxp,kinetis-port-pins = < 1 3 >;
	};
	JTAG_TDI_PTA1: jtag_tdi_pta1 {
		nxp,kinetis-port-pins = < 1 7 >;
	};
	PTA2: GPIOA_PTA2: gpioa_pta2 {
		nxp,kinetis-port-pins = < 2 1 >;
	};
	UART0_TX_PTA2: uart0_tx_pta2 {
		nxp,kinetis-port-pins = < 2 2 >;
	};
	FTM0_CH7_PTA2: ftm0_ch7_pta2 {
		nxp,kinetis-port-pins = < 2 3 >;
	};
	JTAG_TDO_PTA2: TRACE_SWO_PTA2: jtag_tdo_pta2 {
		nxp,kinetis-port-pins = < 2 7 >;
	};
	PTA3: GPIOA_PTA3: gpioa_pta3 {
		nxp,kinetis-port-pins = < 3 1 >;
	};
	UART0_RTS_b_PTA3: uart0_rts_b_pta3 {
		nxp,kinetis-port-pins = < 3 2 >;
	};
	FTM0_CH0_PTA3: ftm0_ch0_pta3 {
		nxp,kinetis-port-pins = < 3 3 >;
	};
	JTAG_TMS_PTA3: SWD_DIO_PTA3: jtag_tms_pta3 {
		nxp,kinetis-port-pins = < 3 7 >;
	};
	PTA4: GPIOA_PTA4: LLWU_P3_PTA4: gpioa_pta4 {
		nxp,kinetis-port-pins = < 4 1 >;
	};
	FTM0_CH1_PTA4: ftm0_ch1_pta4 {
		nxp,kinetis-port-pins = < 4 3 >;
	};
	NMI_b_PTA4: nmi_b_pta4 {
		nxp,kinetis-port-pins = < 4 7 >;
	};
	EXTAL0_PTA18: extal0_pta18 {
		nxp,kinetis-port-pins = < 18 0 >;
	};
	PTA18: GPIOA_PTA18: gpioa_pta18 {
		nxp,kinetis-port-pins = < 18 1 >;
	};
	FTM0_FLT2_PTA18: ftm0_flt2_pta18 {
		nxp,kinetis-port-pins = < 18 3 >;
	};
	FTM_CLKIN0_PTA18: ftm_clkin0_pta18 {
		nxp,kinetis-port-pins = < 18 4 >;
	};
	XTAL0_PTA19: xtal0_pta19 {
		nxp,kinetis-port-pins = < 19 0 >;
	};
	PTA19: GPIOA_PTA19: gpioa_pta19 {
		nxp,kinetis-port-pins = < 19 1 >;
	};
	FTM1_FLT0_PTA19: ftm1_flt0_pta19 {
		nxp,kinetis-port-pins = < 19 3 >;
	};
	FTM_CLKIN1_PTA19: ftm_clkin1_pta19 {
		nxp,kinetis-port-pins = < 19 4 >;
	};
	LPTMR0_ALT1_PTA19: lptmr0_alt1_pta19 {
		nxp,kinetis-port-pins = < 19 6 >;
	};
};

&portc {
	PTC4: GPIOC_PTC4: LLWU_P8_PTC4: gpioc_ptc4 {
		nxp,kinetis-port-pins = < 4 1 >;
	};
	SPI0_PCS0_PTC4: spi0_pcs0_ptc4 {
		nxp,kinetis-port-pins = < 4 2 >;
	};
	UART1_TX_PTC4: uart1_tx_ptc4 {
		nxp,kinetis-port-pins = < 4 3 >;
	};
	FTM0_CH3_PTC4: ftm0_ch3_ptc4 {
		nxp,kinetis-port-pins = < 4 4 >;
	};
	CMP1_OUT_PTC4: cmp1_out_ptc4 {
		nxp,kinetis-port-pins = < 4 6 >;
	};
	PTC5: GPIOC_PTC5: LLWU_P9_PTC5: gpioc_ptc5 {
		nxp,kinetis-port-pins = < 5 1 >;
	};
	SPI0_SCK_PTC5: spi0_sck_ptc5 {
		nxp,kinetis-port-pins = < 5 2 >;
	};
	LPTMR0_ALT2_PTC5: lptmr0_alt2_ptc5 {
		nxp,kinetis-port-pins = < 5 3 >;
	};
	I2S0_RXD0_PTC5: i2s0_rxd0_ptc5 {
		nxp,kinetis-port-pins = < 5 4 >;
	};
	CMP0_OUT_PTC5: cmp0_out_ptc5 {
		nxp,kinetis-port-pins = < 5 6 >;
	};
	CMP0_IN0_PTC6: cmp0_in0_ptc6 {
		nxp,kinetis-port-pins = < 6 0 >;
	};
	PTC6: GPIOC_PTC6: LLWU_P10_PTC6: gpioc_ptc6 {
		nxp,kinetis-port-pins = < 6 1 >;
	};
	SPI0_SOUT_PTC6: spi0_sout_ptc6 {
		nxp,kinetis-port-pins = < 6 2 >;
	};
	PDB0_EXTRG_PTC6: pdb0_extrg_ptc6 {
		nxp,kinetis-port-pins = < 6 3 >;
	};
	I2S0_RX_BCLK_PTC6: i2s0_rx_bclk_ptc6 {
		nxp,kinetis-port-pins = < 6 4 >;
	};
	I2S0_MCLK_PTC6: i2s0_mclk_ptc6 {
		nxp,kinetis-port-pins = < 6 6 >;
	};
	CMP0_IN1_PTC7: cmp0_in1_ptc7 {
		nxp,kinetis-port-pins = < 7 0 >;
	};
	PTC7: GPIOC_PTC7: gpioc_ptc7 {
		nxp,kinetis-port-pins = < 7 1 >;
	};
	SPI0_SIN_PTC7: spi0_sin_ptc7 {
		nxp,kinetis-port-pins = < 7 2 >;
	};
	USB_SOF_OUT_PTC7: usb_sof_out_ptc7 {
		nxp,kinetis-port-pins = < 7 3 >;
	};
	I2S0_RX_FS_PTC7: i2s0_rx_fs_ptc7 {
		nxp,kinetis-port-pins = < 7 4 >;
	};
};

&portd {
	ADC0_SE5b_PTD1: adc0_se5b_ptd1 {
		nxp,kinetis-port-pins = < 1 0 >;
	};
	PTD1: GPIOD_PTD1: gpiod_ptd1 {
		nxp,kinetis-port-pins = < 1 1 >;
	};
	SPI0_SCK_PTD1: spi0_sck_ptd1 {
		nxp,kinetis-port-pins = < 1 2 >;
	};
	UART2_CTS_b_PTD1: uart2_cts_b_ptd1 {
		nxp,kinetis-port-pins = < 1 3 >;
	};
	PTD2: GPIOD_PTD2: LLWU_P13_PTD2: gpiod_ptd2 {
		nxp,kinetis-port-pins = < 2 1 >;
	};
	SPI0_SOUT_PTD2: spi0_sout_ptd2 {
		nxp,kinetis-port-pins = < 2 2 >;
	};
	UART2_RX_PTD2: uart2_rx_ptd2 {
		nxp,kinetis-port-pins = < 2 3 >;
	};
	I2C0_SCL_PTD2: i2c0_scl_ptd2 {
		nxp,kinetis-port-pins = < 2 4 >;
	};
	PTD3: GPIOD_PTD3: gpiod_ptd3 {
		nxp,kinetis-port-pins = < 3 1 >;
	};
	SPI0_SIN_PTD3: spi0_sin_ptd3 {
		nxp,kinetis-port-pins = < 3 2 >;
	};
	UART2_TX_PTD3: uart2_tx_ptd3 {
		nxp,kinetis-port-pins = < 3 3 >;
	};
	I2C0_SDA_PTD3: i2c0_sda_ptd3 {
		nxp,kinetis-port-pins = < 3 4 >;
	};
	ADC0_SE21_PTD4: adc0_se21_ptd4 {
		nxp,kinetis-port-pins = < 4 0 >;
	};
	PTD4: GPIOD_PTD4: LLWU_P14_PTD4: gpiod_ptd4 {
		nxp,kinetis-port-pins = < 4 1 >;
	};
	SPI0_PCS1_PTD4: spi0_pcs1_ptd4 {
		nxp,kinetis-port-pins = < 4 2 >;
	};
	UART0_RTS_b_PTD4: uart0_rts_b_ptd4 {
		nxp,kinetis-port-pins = < 4 3 >;
	};
	FTM0_CH4_PTD4: ftm0_ch4_ptd4 {
		nxp,kinetis-port-pins = < 4 4 >;
	};
	EWM_IN_PTD4: ewm_in_ptd4 {
		nxp,kinetis-port-pins = < 4 6 >;
	};
	ADC0_SE6b_PTD5: adc0_se6b_ptd5 {
		nxp,kinetis-port-pins = < 5 0 >;
	};
	PTD5: GPIOD_PTD5: gpiod_ptd5 {
		nxp,kinetis-port-pins = < 5 1 >;
	};
	SPI0_PCS2_PTD5: spi0_pcs2_ptd5 {
		nxp,kinetis-port-pins = < 5 2 >;
	};
	UART0_CTS_b_PTD5: UART0_COL_b_PTD5: uart0_cts_b_ptd5 {
		nxp,kinetis-port-pins = < 5 3 >;
	};
	FTM0_CH5_PTD5: ftm0_ch5_ptd5 {
		nxp,kinetis-port-pins = < 5 4 >;
	};
	EWM_OUT_b_PTD5: ewm_out_b_ptd5 {
		nxp,kinetis-port-pins = < 5 6 >;
	};
	ADC0_SE7b_PTD6: adc0_se7b_ptd6 {
		nxp,kinetis-port-pins = < 6 0 >;
	};
	PTD6: GPIOD_PTD6: LLWU_P15_PTD6: gpiod_ptd6 {
		nxp,kinetis-port-pins = < 6 1 >;
	};
	SPI0_PCS3_PTD6: spi0_pcs3_ptd6 {
		nxp,kinetis-port-pins = < 6 2 >;
	};
	UART0_RX_PTD6: uart0_rx_ptd6 {
		nxp,kinetis-port-pins = < 6 3 >;
	};
	FTM0_CH6_PTD6: ftm0_ch6_ptd6 {
		nxp,kinetis-port-pins = < 6 4 >;
	};
	FTM0_FLT0_PTD6: ftm0_flt0_ptd6 {
		nxp,kinetis-port-pins = < 6 6 >;
	};
	ADC0_SE22_PTD7: adc0_se22_ptd7 {
		nxp,kinetis-port-pins = < 7 0 >;
	};
	PTD7: GPIOD_PTD7: gpiod_ptd7 {
		nxp,kinetis-port-pins = < 7 1 >;
	};
	CMT_IRO_PTD7: cmt_iro_ptd7 {
		nxp,kinetis-port-pins = < 7 2 >;
	};
	UART0_TX_PTD7: uart0_tx_ptd7 {
		nxp,kinetis-port-pins = < 7 3 >;
	};
	FTM0_CH7_PTD7: ftm0_ch7_ptd7 {
		nxp,kinetis-port-pins = < 7 4 >;
	};
	FTM0_FLT1_PTD7: ftm0_flt1_ptd7 {
		nxp,kinetis-port-pins = < 7 6 >;
	};
};

&porte {
	ADC0_SE10_PTE0: adc0_se10_pte0 {
		nxp,kinetis-port-pins = < 0 0 >;
	};
	PTE0: GPIOE_PTE0: gpioe_pte0 {
		nxp,kinetis-port-pins = < 0 1 >;
	};
	SPI1_PCS1_PTE0: spi1_pcs1_pte0 {
		nxp,kinetis-port-pins = < 0 2 >;
	};
	UART1_TX_PTE0: uart1_tx_pte0 {
		nxp,kinetis-port-pins = < 0 3 >;
	};
	TRACE_CLKOUT_PTE0: trace_clkout_pte0 {
		nxp,kinetis-port-pins = < 0 5 >;
	};
	I2C1_SDA_PTE0: i2c1_sda_pte0 {
		nxp,kinetis-port-pins = < 0 6 >;
	};
	RTC_CLKOUT_PTE0: rtc_clkout_pte0 {
		nxp,kinetis-port-pins = < 0 7 >;
	};
	ADC0_SE11_PTE1: adc0_se11_pte1 {
		nxp,kinetis-port-pins = < 1 0 >;
	};
	PTE1: GPIOE_PTE1: LLWU_P0_PTE1: gpioe_pte1 {
		nxp,kinetis-port-pins = < 1 1 >;
	};
	SPI1_SOUT_PTE1: spi1_sout_pte1 {
		nxp,kinetis-port-pins = < 1 2 >;
	};
	UART1_RX_PTE1: uart1_rx_pte1 {
		nxp,kinetis-port-pins = < 1 3 >;
	};
	TRACE_D3_PTE1: trace_d3_pte1 {
		nxp,kinetis-port-pins = < 1 5 >;
	};
	I2C1_SCL_PTE1: i2c1_scl_pte1 {
		nxp,kinetis-port-pins = < 1 6 >;
	};
	SPI1_SIN_PTE1: spi1_sin_pte1 {
		nxp,kinetis-port-pins = < 1 7 >;
	};
	ADC0_DP1_PTE2: adc0_dp1_pte2 {
		nxp,kinetis-port-pins = < 2 0 >;
	};
	PTE2: GPIOE_PTE2: LLWU_P1_PTE2: gpioe_pte2 {
		nxp,kinetis-port-pins = < 2 1 >;
	};
	SPI1_SCK_PTE2: spi1_sck_pte2 {
		nxp,kinetis-port-pins = < 2 2 >;
	};
	UART1_CTS_b_PTE2: uart1_cts_b_pte2 {
		nxp,kinetis-port-pins = < 2 3 >;
	};
	TRACE_D2_PTE2: trace_d2_pte2 {
		nxp,kinetis-port-pins = < 2 5 >;
	};
	ADC0_DM1_PTE3: adc0_dm1_pte3 {
		nxp,kinetis-port-pins = < 3 0 >;
	};
	PTE3: GPIOE_PTE3: gpioe_pte3 {
		nxp,kinetis-port-pins = < 3 1 >;
	};
	SPI1_SIN_PTE3: spi1_sin_pte3 {
		nxp,kinetis-port-pins = < 3 2 >;
	};
	UART1_RTS_b_PTE3: uart1_rts_b_pte3 {
		nxp,kinetis-port-pins = < 3 3 >;
	};
	TRACE_D1_PTE3: trace_d1_pte3 {
		nxp,kinetis-port-pins = < 3 5 >;
	};
	SPI1_SOUT_PTE3: spi1_sout_pte3 {
		nxp,kinetis-port-pins = < 3 7 >;
	};
	PTE4: GPIOE_PTE4: LLWU_P2_PTE4: gpioe_pte4 {
		nxp,kinetis-port-pins = < 4 1 >;
	};
	SPI1_PCS0_PTE4: spi1_pcs0_pte4 {
		nxp,kinetis-port-pins = < 4 2 >;
	};
	TRACE_D0_PTE4: trace_d0_pte4 {
		nxp,kinetis-port-pins = < 4 5 >;
	};
};