1/*
2 * NOTE: Autogenerated file by kinetis_signal2dts.py
3 *       for MKV58F1M0VLQ24/signal_configuration.xml
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8/*
9 * Pin nodes are of the form:
10 *
11 *	<SIGNAL[0..n]>: <signal[0]> {
12 *		nxp,kinetis-port-pins = < PIN PCR[MUX] >;
13 *	};
14 */
15
16&porta {
17	PTA0: GPIOA_PTA0: gpioa_pta0 {
18		nxp,kinetis-port-pins = < 0 1 >;
19	};
20	UART0_CTS_b_PTA0: UART0_COL_b_PTA0: uart0_cts_b_pta0 {
21		nxp,kinetis-port-pins = < 0 2 >;
22	};
23	FTM0_CH5_PTA0: ftm0_ch5_pta0 {
24		nxp,kinetis-port-pins = < 0 3 >;
25	};
26	XB_IN4_PTA0: xb_in4_pta0 {
27		nxp,kinetis-port-pins = < 0 4 >;
28	};
29	JTAG_TCLK_PTA0: jtag_tclk_pta0 {
30		nxp,kinetis-port-pins = < 0 7 >;
31	};
32	PTA1: GPIOA_PTA1: gpioa_pta1 {
33		nxp,kinetis-port-pins = < 1 1 >;
34	};
35	UART0_RX_PTA1: uart0_rx_pta1 {
36		nxp,kinetis-port-pins = < 1 2 >;
37	};
38	FTM0_CH6_PTA1: ftm0_ch6_pta1 {
39		nxp,kinetis-port-pins = < 1 3 >;
40	};
41	CMP0_OUT_PTA1: cmp0_out_pta1 {
42		nxp,kinetis-port-pins = < 1 4 >;
43	};
44	FTM2_QD_PHA_PTA1: ftm2_qd_pha_pta1 {
45		nxp,kinetis-port-pins = < 1 5 >;
46	};
47	FTM1_CH1_PTA1: ftm1_ch1_pta1 {
48		nxp,kinetis-port-pins = < 1 6 >;
49	};
50	JTAG_TDI_PTA1: jtag_tdi_pta1 {
51		nxp,kinetis-port-pins = < 1 7 >;
52	};
53	PTA2: GPIOA_PTA2: gpioa_pta2 {
54		nxp,kinetis-port-pins = < 2 1 >;
55	};
56	UART0_TX_PTA2: uart0_tx_pta2 {
57		nxp,kinetis-port-pins = < 2 2 >;
58	};
59	FTM0_CH7_PTA2: ftm0_ch7_pta2 {
60		nxp,kinetis-port-pins = < 2 3 >;
61	};
62	CMP1_OUT_PTA2: cmp1_out_pta2 {
63		nxp,kinetis-port-pins = < 2 4 >;
64	};
65	FTM2_QD_PHB_PTA2: ftm2_qd_phb_pta2 {
66		nxp,kinetis-port-pins = < 2 5 >;
67	};
68	FTM1_CH0_PTA2: ftm1_ch0_pta2 {
69		nxp,kinetis-port-pins = < 2 6 >;
70	};
71	JTAG_TDO_PTA2: TRACE_SWO_PTA2: jtag_tdo_pta2 {
72		nxp,kinetis-port-pins = < 2 7 >;
73	};
74	PTA3: GPIOA_PTA3: gpioa_pta3 {
75		nxp,kinetis-port-pins = < 3 1 >;
76	};
77	UART0_RTS_b_PTA3: uart0_rts_b_pta3 {
78		nxp,kinetis-port-pins = < 3 2 >;
79	};
80	FTM0_CH0_PTA3: ftm0_ch0_pta3 {
81		nxp,kinetis-port-pins = < 3 3 >;
82	};
83	XB_IN9_PTA3: xb_in9_pta3 {
84		nxp,kinetis-port-pins = < 3 4 >;
85	};
86	EWM_OUT_b_PTA3: ewm_out_b_pta3 {
87		nxp,kinetis-port-pins = < 3 5 >;
88	};
89	FLEXPWM0_A0_PTA3: flexpwm0_a0_pta3 {
90		nxp,kinetis-port-pins = < 3 6 >;
91	};
92	JTAG_TMS_PTA3: jtag_tms_pta3 {
93		nxp,kinetis-port-pins = < 3 7 >;
94	};
95	PTA4: GPIOA_PTA4: LLWU_P3_PTA4: gpioa_pta4 {
96		nxp,kinetis-port-pins = < 4 1 >;
97	};
98	FTM0_CH1_PTA4: ftm0_ch1_pta4 {
99		nxp,kinetis-port-pins = < 4 3 >;
100	};
101	XB_IN10_PTA4: xb_in10_pta4 {
102		nxp,kinetis-port-pins = < 4 4 >;
103	};
104	FLEXPWM0_B0_PTA4: flexpwm0_b0_pta4 {
105		nxp,kinetis-port-pins = < 4 6 >;
106	};
107	NMI_b_PTA4: nmi_b_pta4 {
108		nxp,kinetis-port-pins = < 4 7 >;
109	};
110	PTA5: GPIOA_PTA5: gpioa_pta5 {
111		nxp,kinetis-port-pins = < 5 1 >;
112	};
113	FTM0_CH2_PTA5: ftm0_ch2_pta5 {
114		nxp,kinetis-port-pins = < 5 3 >;
115	};
116	RMII0_RXER_PTA5: MII0_RXER_PTA5: rmii0_rxer_pta5 {
117		nxp,kinetis-port-pins = < 5 4 >;
118	};
119	CMP2_OUT_PTA5: cmp2_out_pta5 {
120		nxp,kinetis-port-pins = < 5 5 >;
121	};
122	JTAG_TRST_b_PTA5: jtag_trst_b_pta5 {
123		nxp,kinetis-port-pins = < 5 7 >;
124	};
125	PTA6: GPIOA_PTA6: gpioa_pta6 {
126		nxp,kinetis-port-pins = < 6 1 >;
127	};
128	FTM0_CH3_PTA6: ftm0_ch3_pta6 {
129		nxp,kinetis-port-pins = < 6 3 >;
130	};
131	CLKOUT_PTA6: clkout_pta6 {
132		nxp,kinetis-port-pins = < 6 5 >;
133	};
134	TRACE_CLKOUT_PTA6: trace_clkout_pta6 {
135		nxp,kinetis-port-pins = < 6 7 >;
136	};
137	HSADC1B_CH8_PTA7: hsadc1b_ch8_pta7 {
138		nxp,kinetis-port-pins = < 7 0 >;
139	};
140	PTA7: GPIOA_PTA7: gpioa_pta7 {
141		nxp,kinetis-port-pins = < 7 1 >;
142	};
143	FTM0_CH4_PTA7: ftm0_ch4_pta7 {
144		nxp,kinetis-port-pins = < 7 3 >;
145	};
146	RMII0_MDIO_PTA7: MII0_MDIO_PTA7: rmii0_mdio_pta7 {
147		nxp,kinetis-port-pins = < 7 5 >;
148	};
149	TRACE_D3_PTA7: trace_d3_pta7 {
150		nxp,kinetis-port-pins = < 7 7 >;
151	};
152	HSADC1B_CH9_PTA8: hsadc1b_ch9_pta8 {
153		nxp,kinetis-port-pins = < 8 0 >;
154	};
155	PTA8: GPIOA_PTA8: gpioa_pta8 {
156		nxp,kinetis-port-pins = < 8 1 >;
157	};
158	FTM1_CH0_PTA8: ftm1_ch0_pta8 {
159		nxp,kinetis-port-pins = < 8 3 >;
160	};
161	RMII0_MDC_PTA8: MII0_MDC_PTA8: rmii0_mdc_pta8 {
162		nxp,kinetis-port-pins = < 8 5 >;
163	};
164	TRACE_D2_PTA8: trace_d2_pta8 {
165		nxp,kinetis-port-pins = < 8 7 >;
166	};
167	PTA9: GPIOA_PTA9: gpioa_pta9 {
168		nxp,kinetis-port-pins = < 9 1 >;
169	};
170	FTM1_CH1_PTA9: ftm1_ch1_pta9 {
171		nxp,kinetis-port-pins = < 9 3 >;
172	};
173	MII0_RXD3_PTA9: mii0_rxd3_pta9 {
174		nxp,kinetis-port-pins = < 9 5 >;
175	};
176	TRACE_D1_PTA9: trace_d1_pta9 {
177		nxp,kinetis-port-pins = < 9 7 >;
178	};
179	PTA10: GPIOA_PTA10: LLWU_P22_PTA10: gpioa_pta10 {
180		nxp,kinetis-port-pins = < 10 1 >;
181	};
182	FTM2_CH0_PTA10: ftm2_ch0_pta10 {
183		nxp,kinetis-port-pins = < 10 3 >;
184	};
185	MII0_RXD2_PTA10: mii0_rxd2_pta10 {
186		nxp,kinetis-port-pins = < 10 5 >;
187	};
188	FTM2_QD_PHA_PTA10: ftm2_qd_pha_pta10 {
189		nxp,kinetis-port-pins = < 10 6 >;
190	};
191	TRACE_D0_PTA10: trace_d0_pta10 {
192		nxp,kinetis-port-pins = < 10 7 >;
193	};
194	PTA11: GPIOA_PTA11: LLWU_P23_PTA11: gpioa_pta11 {
195		nxp,kinetis-port-pins = < 11 1 >;
196	};
197	FTM2_CH1_PTA11: ftm2_ch1_pta11 {
198		nxp,kinetis-port-pins = < 11 3 >;
199	};
200	MII0_RXCLK_PTA11: mii0_rxclk_pta11 {
201		nxp,kinetis-port-pins = < 11 5 >;
202	};
203	FTM2_QD_PHB_PTA11: ftm2_qd_phb_pta11 {
204		nxp,kinetis-port-pins = < 11 6 >;
205	};
206	I2C0_SDA_PTA11: i2c0_sda_pta11 {
207		nxp,kinetis-port-pins = < 11 8 >;
208	};
209	CMP2_IN0_PTA12: cmp2_in0_pta12 {
210		nxp,kinetis-port-pins = < 12 0 >;
211	};
212	PTA12: GPIOA_PTA12: gpioa_pta12 {
213		nxp,kinetis-port-pins = < 12 1 >;
214	};
215	CAN0_TX_PTA12: can0_tx_pta12 {
216		nxp,kinetis-port-pins = < 12 2 >;
217	};
218	FTM1_CH0_PTA12: ftm1_ch0_pta12 {
219		nxp,kinetis-port-pins = < 12 3 >;
220	};
221	RMII0_RXD1_PTA12: MII0_RXD1_PTA12: rmii0_rxd1_pta12 {
222		nxp,kinetis-port-pins = < 12 5 >;
223	};
224	FTM1_QD_PHA_PTA12: ftm1_qd_pha_pta12 {
225		nxp,kinetis-port-pins = < 12 7 >;
226	};
227	I2C0_SCL_PTA12: i2c0_scl_pta12 {
228		nxp,kinetis-port-pins = < 12 8 >;
229	};
230	CMP2_IN1_PTA13: cmp2_in1_pta13 {
231		nxp,kinetis-port-pins = < 13 0 >;
232	};
233	PTA13: GPIOA_PTA13: LLWU_P4_PTA13: gpioa_pta13 {
234		nxp,kinetis-port-pins = < 13 1 >;
235	};
236	CAN0_RX_PTA13: can0_rx_pta13 {
237		nxp,kinetis-port-pins = < 13 2 >;
238	};
239	FTM1_CH1_PTA13: ftm1_ch1_pta13 {
240		nxp,kinetis-port-pins = < 13 3 >;
241	};
242	RMII0_RXD0_PTA13: MII0_RXD0_PTA13: rmii0_rxd0_pta13 {
243		nxp,kinetis-port-pins = < 13 5 >;
244	};
245	FTM1_QD_PHB_PTA13: ftm1_qd_phb_pta13 {
246		nxp,kinetis-port-pins = < 13 7 >;
247	};
248	I2C1_SDA_PTA13: i2c1_sda_pta13 {
249		nxp,kinetis-port-pins = < 13 8 >;
250	};
251	CMP3_IN0_PTA14: cmp3_in0_pta14 {
252		nxp,kinetis-port-pins = < 14 0 >;
253	};
254	PTA14: GPIOA_PTA14: gpioa_pta14 {
255		nxp,kinetis-port-pins = < 14 1 >;
256	};
257	SPI0_PCS0_PTA14: spi0_pcs0_pta14 {
258		nxp,kinetis-port-pins = < 14 2 >;
259	};
260	UART0_TX_PTA14: uart0_tx_pta14 {
261		nxp,kinetis-port-pins = < 14 3 >;
262	};
263	CAN2_TX_PTA14: can2_tx_pta14 {
264		nxp,kinetis-port-pins = < 14 4 >;
265	};
266	RMII0_CRS_DV_PTA14: MII0_RXDV_PTA14: rmii0_crs_dv_pta14 {
267		nxp,kinetis-port-pins = < 14 5 >;
268	};
269	I2C1_SCL_PTA14: i2c1_scl_pta14 {
270		nxp,kinetis-port-pins = < 14 8 >;
271	};
272	CMP3_IN1_PTA15: cmp3_in1_pta15 {
273		nxp,kinetis-port-pins = < 15 0 >;
274	};
275	PTA15: GPIOA_PTA15: gpioa_pta15 {
276		nxp,kinetis-port-pins = < 15 1 >;
277	};
278	SPI0_SCK_PTA15: spi0_sck_pta15 {
279		nxp,kinetis-port-pins = < 15 2 >;
280	};
281	UART0_RX_PTA15: uart0_rx_pta15 {
282		nxp,kinetis-port-pins = < 15 3 >;
283	};
284	CAN2_RX_PTA15: can2_rx_pta15 {
285		nxp,kinetis-port-pins = < 15 4 >;
286	};
287	RMII0_TXEN_PTA15: MII0_TXEN_PTA15: rmii0_txen_pta15 {
288		nxp,kinetis-port-pins = < 15 5 >;
289	};
290	CMP3_IN2_PTA16: cmp3_in2_pta16 {
291		nxp,kinetis-port-pins = < 16 0 >;
292	};
293	PTA16: GPIOA_PTA16: gpioa_pta16 {
294		nxp,kinetis-port-pins = < 16 1 >;
295	};
296	SPI0_SOUT_PTA16: spi0_sout_pta16 {
297		nxp,kinetis-port-pins = < 16 2 >;
298	};
299	UART0_CTS_b_PTA16: UART0_COL_b_PTA16: uart0_cts_b_pta16 {
300		nxp,kinetis-port-pins = < 16 3 >;
301	};
302	RMII0_TXD0_PTA16: MII0_TXD0_PTA16: rmii0_txd0_pta16 {
303		nxp,kinetis-port-pins = < 16 5 >;
304	};
305	HSADC0A_CH15_PTA17: hsadc0a_ch15_pta17 {
306		nxp,kinetis-port-pins = < 17 0 >;
307	};
308	PTA17: GPIOA_PTA17: gpioa_pta17 {
309		nxp,kinetis-port-pins = < 17 1 >;
310	};
311	SPI0_SIN_PTA17: spi0_sin_pta17 {
312		nxp,kinetis-port-pins = < 17 2 >;
313	};
314	UART0_RTS_b_PTA17: uart0_rts_b_pta17 {
315		nxp,kinetis-port-pins = < 17 3 >;
316	};
317	RMII0_TXD1_PTA17: MII0_TXD1_PTA17: rmii0_txd1_pta17 {
318		nxp,kinetis-port-pins = < 17 5 >;
319	};
320	EXTAL0_PTA18: extal0_pta18 {
321		nxp,kinetis-port-pins = < 18 0 >;
322	};
323	PTA18: GPIOA_PTA18: gpioa_pta18 {
324		nxp,kinetis-port-pins = < 18 1 >;
325	};
326	XB_IN7_PTA18: xb_in7_pta18 {
327		nxp,kinetis-port-pins = < 18 2 >;
328	};
329	FTM0_FLT2_PTA18: ftm0_flt2_pta18 {
330		nxp,kinetis-port-pins = < 18 3 >;
331	};
332	FTM_CLKIN0_PTA18: ftm_clkin0_pta18 {
333		nxp,kinetis-port-pins = < 18 4 >;
334	};
335	XB_OUT8_PTA18: xb_out8_pta18 {
336		nxp,kinetis-port-pins = < 18 5 >;
337	};
338	FTM3_CH2_PTA18: ftm3_ch2_pta18 {
339		nxp,kinetis-port-pins = < 18 6 >;
340	};
341	XTAL0_PTA19: xtal0_pta19 {
342		nxp,kinetis-port-pins = < 19 0 >;
343	};
344	PTA19: GPIOA_PTA19: gpioa_pta19 {
345		nxp,kinetis-port-pins = < 19 1 >;
346	};
347	XB_IN8_PTA19: xb_in8_pta19 {
348		nxp,kinetis-port-pins = < 19 2 >;
349	};
350	FTM1_FLT0_PTA19: ftm1_flt0_pta19 {
351		nxp,kinetis-port-pins = < 19 3 >;
352	};
353	FTM_CLKIN1_PTA19: ftm_clkin1_pta19 {
354		nxp,kinetis-port-pins = < 19 4 >;
355	};
356	XB_OUT9_PTA19: xb_out9_pta19 {
357		nxp,kinetis-port-pins = < 19 5 >;
358	};
359	LPTMR0_ALT1_PTA19: lptmr0_alt1_pta19 {
360		nxp,kinetis-port-pins = < 19 6 >;
361	};
362	PTA24: GPIOA_PTA24: gpioa_pta24 {
363		nxp,kinetis-port-pins = < 24 1 >;
364	};
365	XB_IN4_PTA24: xb_in4_pta24 {
366		nxp,kinetis-port-pins = < 24 2 >;
367	};
368	MII0_TXD2_PTA24: mii0_txd2_pta24 {
369		nxp,kinetis-port-pins = < 24 5 >;
370	};
371	PTA25: GPIOA_PTA25: gpioa_pta25 {
372		nxp,kinetis-port-pins = < 25 1 >;
373	};
374	XB_IN5_PTA25: xb_in5_pta25 {
375		nxp,kinetis-port-pins = < 25 2 >;
376	};
377	MII0_TXCLK_PTA25: mii0_txclk_pta25 {
378		nxp,kinetis-port-pins = < 25 5 >;
379	};
380	PTA26: GPIOA_PTA26: gpioa_pta26 {
381		nxp,kinetis-port-pins = < 26 1 >;
382	};
383	MII0_TXD3_PTA26: mii0_txd3_pta26 {
384		nxp,kinetis-port-pins = < 26 5 >;
385	};
386	PTA27: GPIOA_PTA27: gpioa_pta27 {
387		nxp,kinetis-port-pins = < 27 1 >;
388	};
389	MII0_CRS_PTA27: mii0_crs_pta27 {
390		nxp,kinetis-port-pins = < 27 5 >;
391	};
392	PTA28: GPIOA_PTA28: gpioa_pta28 {
393		nxp,kinetis-port-pins = < 28 1 >;
394	};
395	MII0_TXER_PTA28: mii0_txer_pta28 {
396		nxp,kinetis-port-pins = < 28 5 >;
397	};
398	PTA29: GPIOA_PTA29: gpioa_pta29 {
399		nxp,kinetis-port-pins = < 29 1 >;
400	};
401	MII0_COL_PTA29: mii0_col_pta29 {
402		nxp,kinetis-port-pins = < 29 5 >;
403	};
404};
405
406&portb {
407	HSADC0B_CH2_PTB0: hsadc0b_ch2_ptb0 {
408		nxp,kinetis-port-pins = < 0 0 >;
409	};
410	PTB0: GPIOB_PTB0: LLWU_P5_PTB0: gpiob_ptb0 {
411		nxp,kinetis-port-pins = < 0 1 >;
412	};
413	I2C0_SCL_PTB0: i2c0_scl_ptb0 {
414		nxp,kinetis-port-pins = < 0 2 >;
415	};
416	FTM1_CH0_PTB0: ftm1_ch0_ptb0 {
417		nxp,kinetis-port-pins = < 0 3 >;
418	};
419	FTM1_QD_PHA_PTB0: ftm1_qd_pha_ptb0 {
420		nxp,kinetis-port-pins = < 0 6 >;
421	};
422	UART0_RX_PTB0: uart0_rx_ptb0 {
423		nxp,kinetis-port-pins = < 0 7 >;
424	};
425	RMII0_MDIO_PTB0: MII0_MDIO_PTB0: rmii0_mdio_ptb0 {
426		nxp,kinetis-port-pins = < 0 8 >;
427	};
428	HSADC0B_CH3_PTB1: hsadc0b_ch3_ptb1 {
429		nxp,kinetis-port-pins = < 1 0 >;
430	};
431	PTB1: GPIOB_PTB1: gpiob_ptb1 {
432		nxp,kinetis-port-pins = < 1 1 >;
433	};
434	I2C0_SDA_PTB1: i2c0_sda_ptb1 {
435		nxp,kinetis-port-pins = < 1 2 >;
436	};
437	FTM1_CH1_PTB1: ftm1_ch1_ptb1 {
438		nxp,kinetis-port-pins = < 1 3 >;
439	};
440	FTM0_FLT2_PTB1: ftm0_flt2_ptb1 {
441		nxp,kinetis-port-pins = < 1 4 >;
442	};
443	EWM_IN_PTB1: ewm_in_ptb1 {
444		nxp,kinetis-port-pins = < 1 5 >;
445	};
446	FTM1_QD_PHB_PTB1: ftm1_qd_phb_ptb1 {
447		nxp,kinetis-port-pins = < 1 6 >;
448	};
449	UART0_TX_PTB1: uart0_tx_ptb1 {
450		nxp,kinetis-port-pins = < 1 7 >;
451	};
452	RMII0_MDC_PTB1: MII0_MDC_PTB1: rmii0_mdc_ptb1 {
453		nxp,kinetis-port-pins = < 1 8 >;
454	};
455	HSADC0A_CH14_PTB2: CMP2_IN2_PTB2: hsadc0a_ch14_ptb2 {
456		nxp,kinetis-port-pins = < 2 0 >;
457	};
458	PTB2: GPIOB_PTB2: gpiob_ptb2 {
459		nxp,kinetis-port-pins = < 2 1 >;
460	};
461	I2C0_SCL_PTB2: i2c0_scl_ptb2 {
462		nxp,kinetis-port-pins = < 2 2 >;
463	};
464	UART0_RTS_b_PTB2: uart0_rts_b_ptb2 {
465		nxp,kinetis-port-pins = < 2 3 >;
466	};
467	FTM0_FLT1_PTB2: ftm0_flt1_ptb2 {
468		nxp,kinetis-port-pins = < 2 4 >;
469	};
470	ENET0_1588_TMR0_PTB2: enet0_1588_tmr0_ptb2 {
471		nxp,kinetis-port-pins = < 2 5 >;
472	};
473	FTM0_FLT3_PTB2: ftm0_flt3_ptb2 {
474		nxp,kinetis-port-pins = < 2 6 >;
475	};
476	HSADC0B_CH15_PTB3: CMP3_IN5_PTB3: hsadc0b_ch15_ptb3 {
477		nxp,kinetis-port-pins = < 3 0 >;
478	};
479	PTB3: GPIOB_PTB3: gpiob_ptb3 {
480		nxp,kinetis-port-pins = < 3 1 >;
481	};
482	I2C0_SDA_PTB3: i2c0_sda_ptb3 {
483		nxp,kinetis-port-pins = < 3 2 >;
484	};
485	UART0_CTS_b_PTB3: UART0_COL_b_PTB3: uart0_cts_b_ptb3 {
486		nxp,kinetis-port-pins = < 3 3 >;
487	};
488	ENET0_1588_TMR1_PTB3: enet0_1588_tmr1_ptb3 {
489		nxp,kinetis-port-pins = < 3 5 >;
490	};
491	FTM0_FLT0_PTB3: ftm0_flt0_ptb3 {
492		nxp,kinetis-port-pins = < 3 6 >;
493	};
494	ADC0_SE6b_PTB4: adc0_se6b_ptb4 {
495		nxp,kinetis-port-pins = < 4 0 >;
496	};
497	PTB4: GPIOB_PTB4: gpiob_ptb4 {
498		nxp,kinetis-port-pins = < 4 1 >;
499	};
500	FLEXPWM1_X0_PTB4: flexpwm1_x0_ptb4 {
501		nxp,kinetis-port-pins = < 4 4 >;
502	};
503	ENET0_1588_TMR2_PTB4: enet0_1588_tmr2_ptb4 {
504		nxp,kinetis-port-pins = < 4 5 >;
505	};
506	FTM1_FLT0_PTB4: ftm1_flt0_ptb4 {
507		nxp,kinetis-port-pins = < 4 6 >;
508	};
509	ADC0_SE7b_PTB5: adc0_se7b_ptb5 {
510		nxp,kinetis-port-pins = < 5 0 >;
511	};
512	PTB5: GPIOB_PTB5: gpiob_ptb5 {
513		nxp,kinetis-port-pins = < 5 1 >;
514	};
515	FLEXPWM1_X1_PTB5: flexpwm1_x1_ptb5 {
516		nxp,kinetis-port-pins = < 5 4 >;
517	};
518	ENET0_1588_TMR3_PTB5: enet0_1588_tmr3_ptb5 {
519		nxp,kinetis-port-pins = < 5 5 >;
520	};
521	FTM2_FLT0_PTB5: ftm2_flt0_ptb5 {
522		nxp,kinetis-port-pins = < 5 6 >;
523	};
524	HSADC1A_CH12_PTB6: hsadc1a_ch12_ptb6 {
525		nxp,kinetis-port-pins = < 6 0 >;
526	};
527	PTB6: GPIOB_PTB6: gpiob_ptb6 {
528		nxp,kinetis-port-pins = < 6 1 >;
529	};
530	CAN2_TX_PTB6: can2_tx_ptb6 {
531		nxp,kinetis-port-pins = < 6 2 >;
532	};
533	FLEXPWM1_X2_PTB6: flexpwm1_x2_ptb6 {
534		nxp,kinetis-port-pins = < 6 4 >;
535	};
536	HSADC1A_CH13_PTB7: hsadc1a_ch13_ptb7 {
537		nxp,kinetis-port-pins = < 7 0 >;
538	};
539	PTB7: GPIOB_PTB7: gpiob_ptb7 {
540		nxp,kinetis-port-pins = < 7 1 >;
541	};
542	CAN2_RX_PTB7: can2_rx_ptb7 {
543		nxp,kinetis-port-pins = < 7 2 >;
544	};
545	FLEXPWM1_X3_PTB7: flexpwm1_x3_ptb7 {
546		nxp,kinetis-port-pins = < 7 4 >;
547	};
548	PTB8: GPIOB_PTB8: gpiob_ptb8 {
549		nxp,kinetis-port-pins = < 8 1 >;
550	};
551	UART3_RTS_b_PTB8: uart3_rts_b_ptb8 {
552		nxp,kinetis-port-pins = < 8 3 >;
553	};
554	PTB9: GPIOB_PTB9: gpiob_ptb9 {
555		nxp,kinetis-port-pins = < 9 1 >;
556	};
557	SPI1_PCS1_PTB9: spi1_pcs1_ptb9 {
558		nxp,kinetis-port-pins = < 9 2 >;
559	};
560	UART3_CTS_b_PTB9: uart3_cts_b_ptb9 {
561		nxp,kinetis-port-pins = < 9 3 >;
562	};
563	ENET0_1588_TMR2_PTB9: enet0_1588_tmr2_ptb9 {
564		nxp,kinetis-port-pins = < 9 5 >;
565	};
566	HSADC0B_CH6_PTB10: hsadc0b_ch6_ptb10 {
567		nxp,kinetis-port-pins = < 10 0 >;
568	};
569	PTB10: GPIOB_PTB10: gpiob_ptb10 {
570		nxp,kinetis-port-pins = < 10 1 >;
571	};
572	SPI1_PCS0_PTB10: spi1_pcs0_ptb10 {
573		nxp,kinetis-port-pins = < 10 2 >;
574	};
575	UART3_RX_PTB10: uart3_rx_ptb10 {
576		nxp,kinetis-port-pins = < 10 3 >;
577	};
578	ENET0_1588_TMR3_PTB10: enet0_1588_tmr3_ptb10 {
579		nxp,kinetis-port-pins = < 10 5 >;
580	};
581	FTM0_FLT1_PTB10: ftm0_flt1_ptb10 {
582		nxp,kinetis-port-pins = < 10 6 >;
583	};
584	HSADC0B_CH7_PTB11: hsadc0b_ch7_ptb11 {
585		nxp,kinetis-port-pins = < 11 0 >;
586	};
587	PTB11: GPIOB_PTB11: gpiob_ptb11 {
588		nxp,kinetis-port-pins = < 11 1 >;
589	};
590	SPI1_SCK_PTB11: spi1_sck_ptb11 {
591		nxp,kinetis-port-pins = < 11 2 >;
592	};
593	UART3_TX_PTB11: uart3_tx_ptb11 {
594		nxp,kinetis-port-pins = < 11 3 >;
595	};
596	FTM0_FLT2_PTB11: ftm0_flt2_ptb11 {
597		nxp,kinetis-port-pins = < 11 6 >;
598	};
599	PTB16: GPIOB_PTB16: gpiob_ptb16 {
600		nxp,kinetis-port-pins = < 16 1 >;
601	};
602	SPI1_SOUT_PTB16: spi1_sout_ptb16 {
603		nxp,kinetis-port-pins = < 16 2 >;
604	};
605	UART0_RX_PTB16: uart0_rx_ptb16 {
606		nxp,kinetis-port-pins = < 16 3 >;
607	};
608	FTM_CLKIN2_PTB16: ftm_clkin2_ptb16 {
609		nxp,kinetis-port-pins = < 16 4 >;
610	};
611	CAN0_TX_PTB16: can0_tx_ptb16 {
612		nxp,kinetis-port-pins = < 16 5 >;
613	};
614	EWM_IN_PTB16: ewm_in_ptb16 {
615		nxp,kinetis-port-pins = < 16 6 >;
616	};
617	XB_IN5_PTB16: xb_in5_ptb16 {
618		nxp,kinetis-port-pins = < 16 7 >;
619	};
620	PTB17: GPIOB_PTB17: gpiob_ptb17 {
621		nxp,kinetis-port-pins = < 17 1 >;
622	};
623	SPI1_SIN_PTB17: spi1_sin_ptb17 {
624		nxp,kinetis-port-pins = < 17 2 >;
625	};
626	UART0_TX_PTB17: uart0_tx_ptb17 {
627		nxp,kinetis-port-pins = < 17 3 >;
628	};
629	FTM_CLKIN1_PTB17: ftm_clkin1_ptb17 {
630		nxp,kinetis-port-pins = < 17 4 >;
631	};
632	CAN0_RX_PTB17: can0_rx_ptb17 {
633		nxp,kinetis-port-pins = < 17 5 >;
634	};
635	EWM_OUT_b_PTB17: ewm_out_b_ptb17 {
636		nxp,kinetis-port-pins = < 17 6 >;
637	};
638	PTB18: GPIOB_PTB18: gpiob_ptb18 {
639		nxp,kinetis-port-pins = < 18 1 >;
640	};
641	CAN0_TX_PTB18: can0_tx_ptb18 {
642		nxp,kinetis-port-pins = < 18 2 >;
643	};
644	FTM2_CH0_PTB18: ftm2_ch0_ptb18 {
645		nxp,kinetis-port-pins = < 18 3 >;
646	};
647	FTM3_CH2_PTB18: ftm3_ch2_ptb18 {
648		nxp,kinetis-port-pins = < 18 4 >;
649	};
650	FLEXPWM1_A1_PTB18: flexpwm1_a1_ptb18 {
651		nxp,kinetis-port-pins = < 18 5 >;
652	};
653	FTM2_QD_PHA_PTB18: ftm2_qd_pha_ptb18 {
654		nxp,kinetis-port-pins = < 18 6 >;
655	};
656	PTB19: GPIOB_PTB19: gpiob_ptb19 {
657		nxp,kinetis-port-pins = < 19 1 >;
658	};
659	CAN0_RX_PTB19: can0_rx_ptb19 {
660		nxp,kinetis-port-pins = < 19 2 >;
661	};
662	FTM2_CH1_PTB19: ftm2_ch1_ptb19 {
663		nxp,kinetis-port-pins = < 19 3 >;
664	};
665	FTM3_CH3_PTB19: ftm3_ch3_ptb19 {
666		nxp,kinetis-port-pins = < 19 4 >;
667	};
668	FLEXPWM1_B1_PTB19: flexpwm1_b1_ptb19 {
669		nxp,kinetis-port-pins = < 19 5 >;
670	};
671	FTM2_QD_PHB_PTB19: ftm2_qd_phb_ptb19 {
672		nxp,kinetis-port-pins = < 19 6 >;
673	};
674	PTB20: GPIOB_PTB20: gpiob_ptb20 {
675		nxp,kinetis-port-pins = < 20 1 >;
676	};
677	SPI2_PCS0_PTB20: spi2_pcs0_ptb20 {
678		nxp,kinetis-port-pins = < 20 2 >;
679	};
680	FLEXPWM0_X0_PTB20: flexpwm0_x0_ptb20 {
681		nxp,kinetis-port-pins = < 20 5 >;
682	};
683	CMP0_OUT_PTB20: cmp0_out_ptb20 {
684		nxp,kinetis-port-pins = < 20 6 >;
685	};
686	PTB21: GPIOB_PTB21: gpiob_ptb21 {
687		nxp,kinetis-port-pins = < 21 1 >;
688	};
689	SPI2_SCK_PTB21: spi2_sck_ptb21 {
690		nxp,kinetis-port-pins = < 21 2 >;
691	};
692	FLEXPWM0_X1_PTB21: flexpwm0_x1_ptb21 {
693		nxp,kinetis-port-pins = < 21 5 >;
694	};
695	CMP1_OUT_PTB21: cmp1_out_ptb21 {
696		nxp,kinetis-port-pins = < 21 6 >;
697	};
698	PTB22: GPIOB_PTB22: gpiob_ptb22 {
699		nxp,kinetis-port-pins = < 22 1 >;
700	};
701	SPI2_SOUT_PTB22: spi2_sout_ptb22 {
702		nxp,kinetis-port-pins = < 22 2 >;
703	};
704	FLEXPWM0_X2_PTB22: flexpwm0_x2_ptb22 {
705		nxp,kinetis-port-pins = < 22 5 >;
706	};
707	CMP2_OUT_PTB22: cmp2_out_ptb22 {
708		nxp,kinetis-port-pins = < 22 6 >;
709	};
710	PTB23: GPIOB_PTB23: gpiob_ptb23 {
711		nxp,kinetis-port-pins = < 23 1 >;
712	};
713	SPI2_SIN_PTB23: spi2_sin_ptb23 {
714		nxp,kinetis-port-pins = < 23 2 >;
715	};
716	SPI0_PCS5_PTB23: spi0_pcs5_ptb23 {
717		nxp,kinetis-port-pins = < 23 3 >;
718	};
719	FLEXPWM0_X3_PTB23: flexpwm0_x3_ptb23 {
720		nxp,kinetis-port-pins = < 23 5 >;
721	};
722	CMP3_OUT_PTB23: cmp3_out_ptb23 {
723		nxp,kinetis-port-pins = < 23 6 >;
724	};
725};
726
727&portc {
728	HSADC0B_CH8_PTC0: hsadc0b_ch8_ptc0 {
729		nxp,kinetis-port-pins = < 0 0 >;
730	};
731	PTC0: GPIOC_PTC0: gpioc_ptc0 {
732		nxp,kinetis-port-pins = < 0 1 >;
733	};
734	SPI0_PCS4_PTC0: spi0_pcs4_ptc0 {
735		nxp,kinetis-port-pins = < 0 2 >;
736	};
737	PDB0_EXTRG_PTC0: pdb0_extrg_ptc0 {
738		nxp,kinetis-port-pins = < 0 3 >;
739	};
740	FTM0_FLT1_PTC0: ftm0_flt1_ptc0 {
741		nxp,kinetis-port-pins = < 0 6 >;
742	};
743	SPI0_PCS0_PTC0: spi0_pcs0_ptc0 {
744		nxp,kinetis-port-pins = < 0 7 >;
745	};
746	HSADC0B_CH9_PTC1: hsadc0b_ch9_ptc1 {
747		nxp,kinetis-port-pins = < 1 0 >;
748	};
749	PTC1: GPIOC_PTC1: LLWU_P6_PTC1: gpioc_ptc1 {
750		nxp,kinetis-port-pins = < 1 1 >;
751	};
752	SPI0_PCS3_PTC1: spi0_pcs3_ptc1 {
753		nxp,kinetis-port-pins = < 1 2 >;
754	};
755	UART1_RTS_b_PTC1: uart1_rts_b_ptc1 {
756		nxp,kinetis-port-pins = < 1 3 >;
757	};
758	FTM0_CH0_PTC1: ftm0_ch0_ptc1 {
759		nxp,kinetis-port-pins = < 1 4 >;
760	};
761	FLEXPWM0_A3_PTC1: flexpwm0_a3_ptc1 {
762		nxp,kinetis-port-pins = < 1 5 >;
763	};
764	XB_IN11_PTC1: xb_in11_ptc1 {
765		nxp,kinetis-port-pins = < 1 6 >;
766	};
767	HSADC1B_CH10_PTC2: CMP1_IN0_PTC2: hsadc1b_ch10_ptc2 {
768		nxp,kinetis-port-pins = < 2 0 >;
769	};
770	PTC2: GPIOC_PTC2: gpioc_ptc2 {
771		nxp,kinetis-port-pins = < 2 1 >;
772	};
773	SPI0_PCS2_PTC2: spi0_pcs2_ptc2 {
774		nxp,kinetis-port-pins = < 2 2 >;
775	};
776	UART1_CTS_b_PTC2: uart1_cts_b_ptc2 {
777		nxp,kinetis-port-pins = < 2 3 >;
778	};
779	FTM0_CH1_PTC2: ftm0_ch1_ptc2 {
780		nxp,kinetis-port-pins = < 2 4 >;
781	};
782	FLEXPWM0_B3_PTC2: flexpwm0_b3_ptc2 {
783		nxp,kinetis-port-pins = < 2 5 >;
784	};
785	XB_IN6_PTC2: xb_in6_ptc2 {
786		nxp,kinetis-port-pins = < 2 6 >;
787	};
788	CMP1_IN1_PTC3: cmp1_in1_ptc3 {
789		nxp,kinetis-port-pins = < 3 0 >;
790	};
791	PTC3: GPIOC_PTC3: LLWU_P7_PTC3: gpioc_ptc3 {
792		nxp,kinetis-port-pins = < 3 1 >;
793	};
794	SPI0_PCS1_PTC3: spi0_pcs1_ptc3 {
795		nxp,kinetis-port-pins = < 3 2 >;
796	};
797	UART1_RX_PTC3: uart1_rx_ptc3 {
798		nxp,kinetis-port-pins = < 3 3 >;
799	};
800	FTM0_CH2_PTC3: ftm0_ch2_ptc3 {
801		nxp,kinetis-port-pins = < 3 4 >;
802	};
803	CLKOUT_PTC3: clkout_ptc3 {
804		nxp,kinetis-port-pins = < 3 5 >;
805	};
806	FTM3_FLT0_PTC3: ftm3_flt0_ptc3 {
807		nxp,kinetis-port-pins = < 3 6 >;
808	};
809	PTC4: GPIOC_PTC4: LLWU_P8_PTC4: gpioc_ptc4 {
810		nxp,kinetis-port-pins = < 4 1 >;
811	};
812	SPI0_PCS0_PTC4: spi0_pcs0_ptc4 {
813		nxp,kinetis-port-pins = < 4 2 >;
814	};
815	UART1_TX_PTC4: uart1_tx_ptc4 {
816		nxp,kinetis-port-pins = < 4 3 >;
817	};
818	FTM0_CH3_PTC4: ftm0_ch3_ptc4 {
819		nxp,kinetis-port-pins = < 4 4 >;
820	};
821	CMP1_OUT_PTC4: cmp1_out_ptc4 {
822		nxp,kinetis-port-pins = < 4 6 >;
823	};
824	PTC5: GPIOC_PTC5: LLWU_P9_PTC5: gpioc_ptc5 {
825		nxp,kinetis-port-pins = < 5 1 >;
826	};
827	SPI0_SCK_PTC5: spi0_sck_ptc5 {
828		nxp,kinetis-port-pins = < 5 2 >;
829	};
830	LPTMR0_ALT2_PTC5: lptmr0_alt2_ptc5 {
831		nxp,kinetis-port-pins = < 5 3 >;
832	};
833	XB_IN2_PTC5: xb_in2_ptc5 {
834		nxp,kinetis-port-pins = < 5 4 >;
835	};
836	CMP0_OUT_PTC5: cmp0_out_ptc5 {
837		nxp,kinetis-port-pins = < 5 6 >;
838	};
839	FTM0_CH2_PTC5: ftm0_ch2_ptc5 {
840		nxp,kinetis-port-pins = < 5 7 >;
841	};
842	CMP2_IN4_PTC6: CMP0_IN0_PTC6: cmp2_in4_ptc6 {
843		nxp,kinetis-port-pins = < 6 0 >;
844	};
845	PTC6: GPIOC_PTC6: LLWU_P10_PTC6: gpioc_ptc6 {
846		nxp,kinetis-port-pins = < 6 1 >;
847	};
848	SPI0_SOUT_PTC6: spi0_sout_ptc6 {
849		nxp,kinetis-port-pins = < 6 2 >;
850	};
851	PDB0_EXTRG_PTC6: pdb0_extrg_ptc6 {
852		nxp,kinetis-port-pins = < 6 3 >;
853	};
854	XB_IN3_PTC6: xb_in3_ptc6 {
855		nxp,kinetis-port-pins = < 6 4 >;
856	};
857	UART0_RX_PTC6: uart0_rx_ptc6 {
858		nxp,kinetis-port-pins = < 6 5 >;
859	};
860	XB_OUT6_PTC6: xb_out6_ptc6 {
861		nxp,kinetis-port-pins = < 6 6 >;
862	};
863	I2C0_SCL_PTC6: i2c0_scl_ptc6 {
864		nxp,kinetis-port-pins = < 6 7 >;
865	};
866	CMP3_IN4_PTC7: CMP0_IN1_PTC7: cmp3_in4_ptc7 {
867		nxp,kinetis-port-pins = < 7 0 >;
868	};
869	PTC7: GPIOC_PTC7: gpioc_ptc7 {
870		nxp,kinetis-port-pins = < 7 1 >;
871	};
872	SPI0_SIN_PTC7: spi0_sin_ptc7 {
873		nxp,kinetis-port-pins = < 7 2 >;
874	};
875	XB_IN4_PTC7: xb_in4_ptc7 {
876		nxp,kinetis-port-pins = < 7 4 >;
877	};
878	UART0_TX_PTC7: uart0_tx_ptc7 {
879		nxp,kinetis-port-pins = < 7 5 >;
880	};
881	XB_OUT7_PTC7: xb_out7_ptc7 {
882		nxp,kinetis-port-pins = < 7 6 >;
883	};
884	I2C0_SDA_PTC7: i2c0_sda_ptc7 {
885		nxp,kinetis-port-pins = < 7 7 >;
886	};
887	HSADC1B_CH11_PTC8: CMP0_IN2_PTC8: hsadc1b_ch11_ptc8 {
888		nxp,kinetis-port-pins = < 8 0 >;
889	};
890	PTC8: GPIOC_PTC8: gpioc_ptc8 {
891		nxp,kinetis-port-pins = < 8 1 >;
892	};
893	FTM3_CH4_PTC8: ftm3_ch4_ptc8 {
894		nxp,kinetis-port-pins = < 8 3 >;
895	};
896	FLEXPWM1_A2_PTC8: flexpwm1_a2_ptc8 {
897		nxp,kinetis-port-pins = < 8 4 >;
898	};
899	HSADC1B_CH12_PTC9: CMP0_IN3_PTC9: hsadc1b_ch12_ptc9 {
900		nxp,kinetis-port-pins = < 9 0 >;
901	};
902	PTC9: GPIOC_PTC9: gpioc_ptc9 {
903		nxp,kinetis-port-pins = < 9 1 >;
904	};
905	FTM3_CH5_PTC9: ftm3_ch5_ptc9 {
906		nxp,kinetis-port-pins = < 9 3 >;
907	};
908	FLEXPWM1_B2_PTC9: flexpwm1_b2_ptc9 {
909		nxp,kinetis-port-pins = < 9 4 >;
910	};
911	HSADC1B_CH13_PTC10: hsadc1b_ch13_ptc10 {
912		nxp,kinetis-port-pins = < 10 0 >;
913	};
914	PTC10: GPIOC_PTC10: gpioc_ptc10 {
915		nxp,kinetis-port-pins = < 10 1 >;
916	};
917	I2C1_SCL_PTC10: i2c1_scl_ptc10 {
918		nxp,kinetis-port-pins = < 10 2 >;
919	};
920	FTM3_CH6_PTC10: ftm3_ch6_ptc10 {
921		nxp,kinetis-port-pins = < 10 3 >;
922	};
923	FLEXPWM1_A3_PTC10: flexpwm1_a3_ptc10 {
924		nxp,kinetis-port-pins = < 10 4 >;
925	};
926	HSADC1B_CH14_PTC11: hsadc1b_ch14_ptc11 {
927		nxp,kinetis-port-pins = < 11 0 >;
928	};
929	PTC11: GPIOC_PTC11: LLWU_P11_PTC11: gpioc_ptc11 {
930		nxp,kinetis-port-pins = < 11 1 >;
931	};
932	I2C1_SDA_PTC11: i2c1_sda_ptc11 {
933		nxp,kinetis-port-pins = < 11 2 >;
934	};
935	FTM3_CH7_PTC11: ftm3_ch7_ptc11 {
936		nxp,kinetis-port-pins = < 11 3 >;
937	};
938	FLEXPWM1_B3_PTC11: flexpwm1_b3_ptc11 {
939		nxp,kinetis-port-pins = < 11 4 >;
940	};
941	PTC12: GPIOC_PTC12: gpioc_ptc12 {
942		nxp,kinetis-port-pins = < 12 1 >;
943	};
944	CAN2_TX_PTC12: can2_tx_ptc12 {
945		nxp,kinetis-port-pins = < 12 2 >;
946	};
947	FTM_CLKIN0_PTC12: ftm_clkin0_ptc12 {
948		nxp,kinetis-port-pins = < 12 4 >;
949	};
950	FLEXPWM1_A1_PTC12: flexpwm1_a1_ptc12 {
951		nxp,kinetis-port-pins = < 12 5 >;
952	};
953	FTM3_FLT0_PTC12: ftm3_flt0_ptc12 {
954		nxp,kinetis-port-pins = < 12 6 >;
955	};
956	SPI2_PCS1_PTC12: spi2_pcs1_ptc12 {
957		nxp,kinetis-port-pins = < 12 7 >;
958	};
959	UART4_RTS_b_PTC12: uart4_rts_b_ptc12 {
960		nxp,kinetis-port-pins = < 12 9 >;
961	};
962	PTC13: GPIOC_PTC13: gpioc_ptc13 {
963		nxp,kinetis-port-pins = < 13 1 >;
964	};
965	CAN2_RX_PTC13: can2_rx_ptc13 {
966		nxp,kinetis-port-pins = < 13 2 >;
967	};
968	FTM_CLKIN1_PTC13: ftm_clkin1_ptc13 {
969		nxp,kinetis-port-pins = < 13 4 >;
970	};
971	FLEXPWM1_B1_PTC13: flexpwm1_b1_ptc13 {
972		nxp,kinetis-port-pins = < 13 5 >;
973	};
974	UART4_CTS_b_PTC13: uart4_cts_b_ptc13 {
975		nxp,kinetis-port-pins = < 13 9 >;
976	};
977	PTC14: GPIOC_PTC14: gpioc_ptc14 {
978		nxp,kinetis-port-pins = < 14 1 >;
979	};
980	I2C1_SCL_PTC14: i2c1_scl_ptc14 {
981		nxp,kinetis-port-pins = < 14 2 >;
982	};
983	I2C0_SCL_PTC14: i2c0_scl_ptc14 {
984		nxp,kinetis-port-pins = < 14 3 >;
985	};
986	FLEXPWM1_A0_PTC14: flexpwm1_a0_ptc14 {
987		nxp,kinetis-port-pins = < 14 5 >;
988	};
989	UART4_RX_PTC14: uart4_rx_ptc14 {
990		nxp,kinetis-port-pins = < 14 9 >;
991	};
992	PTC15: GPIOC_PTC15: gpioc_ptc15 {
993		nxp,kinetis-port-pins = < 15 1 >;
994	};
995	I2C1_SDA_PTC15: i2c1_sda_ptc15 {
996		nxp,kinetis-port-pins = < 15 2 >;
997	};
998	I2C0_SDA_PTC15: i2c0_sda_ptc15 {
999		nxp,kinetis-port-pins = < 15 3 >;
1000	};
1001	FLEXPWM1_B0_PTC15: flexpwm1_b0_ptc15 {
1002		nxp,kinetis-port-pins = < 15 5 >;
1003	};
1004	UART4_TX_PTC15: uart4_tx_ptc15 {
1005		nxp,kinetis-port-pins = < 15 9 >;
1006	};
1007	PTC16: GPIOC_PTC16: gpioc_ptc16 {
1008		nxp,kinetis-port-pins = < 16 1 >;
1009	};
1010	CAN1_RX_PTC16: can1_rx_ptc16 {
1011		nxp,kinetis-port-pins = < 16 2 >;
1012	};
1013	UART3_RX_PTC16: uart3_rx_ptc16 {
1014		nxp,kinetis-port-pins = < 16 3 >;
1015	};
1016	ENET0_1588_TMR0_PTC16: enet0_1588_tmr0_ptc16 {
1017		nxp,kinetis-port-pins = < 16 4 >;
1018	};
1019	FLEXPWM1_A2_PTC16: flexpwm1_a2_ptc16 {
1020		nxp,kinetis-port-pins = < 16 5 >;
1021	};
1022	PTC17: GPIOC_PTC17: gpioc_ptc17 {
1023		nxp,kinetis-port-pins = < 17 1 >;
1024	};
1025	CAN1_TX_PTC17: can1_tx_ptc17 {
1026		nxp,kinetis-port-pins = < 17 2 >;
1027	};
1028	UART3_TX_PTC17: uart3_tx_ptc17 {
1029		nxp,kinetis-port-pins = < 17 3 >;
1030	};
1031	ENET0_1588_TMR1_PTC17: enet0_1588_tmr1_ptc17 {
1032		nxp,kinetis-port-pins = < 17 4 >;
1033	};
1034	FLEXPWM1_B2_PTC17: flexpwm1_b2_ptc17 {
1035		nxp,kinetis-port-pins = < 17 5 >;
1036	};
1037	PTC18: GPIOC_PTC18: gpioc_ptc18 {
1038		nxp,kinetis-port-pins = < 18 1 >;
1039	};
1040	UART3_RTS_b_PTC18: uart3_rts_b_ptc18 {
1041		nxp,kinetis-port-pins = < 18 3 >;
1042	};
1043	ENET0_1588_TMR2_PTC18: enet0_1588_tmr2_ptc18 {
1044		nxp,kinetis-port-pins = < 18 4 >;
1045	};
1046	FLEXPWM1_A3_PTC18: flexpwm1_a3_ptc18 {
1047		nxp,kinetis-port-pins = < 18 5 >;
1048	};
1049	PTC19: GPIOC_PTC19: gpioc_ptc19 {
1050		nxp,kinetis-port-pins = < 19 1 >;
1051	};
1052	UART3_CTS_b_PTC19: uart3_cts_b_ptc19 {
1053		nxp,kinetis-port-pins = < 19 3 >;
1054	};
1055	ENET0_1588_TMR3_PTC19: enet0_1588_tmr3_ptc19 {
1056		nxp,kinetis-port-pins = < 19 4 >;
1057	};
1058	FLEXPWM1_B3_PTC19: flexpwm1_b3_ptc19 {
1059		nxp,kinetis-port-pins = < 19 5 >;
1060	};
1061};
1062
1063&portd {
1064	PTD0: GPIOD_PTD0: LLWU_P12_PTD0: gpiod_ptd0 {
1065		nxp,kinetis-port-pins = < 0 1 >;
1066	};
1067	SPI0_PCS0_PTD0: spi0_pcs0_ptd0 {
1068		nxp,kinetis-port-pins = < 0 2 >;
1069	};
1070	UART2_RTS_b_PTD0: uart2_rts_b_ptd0 {
1071		nxp,kinetis-port-pins = < 0 3 >;
1072	};
1073	FTM3_CH0_PTD0: ftm3_ch0_ptd0 {
1074		nxp,kinetis-port-pins = < 0 4 >;
1075	};
1076	FTM0_CH0_PTD0: ftm0_ch0_ptd0 {
1077		nxp,kinetis-port-pins = < 0 5 >;
1078	};
1079	FLEXPWM0_A0_PTD0: flexpwm0_a0_ptd0 {
1080		nxp,kinetis-port-pins = < 0 6 >;
1081	};
1082	FLEXPWM1_A0_PTD0: flexpwm1_a0_ptd0 {
1083		nxp,kinetis-port-pins = < 0 9 >;
1084	};
1085	HSADC1A_CH11_PTD1: hsadc1a_ch11_ptd1 {
1086		nxp,kinetis-port-pins = < 1 0 >;
1087	};
1088	PTD1: GPIOD_PTD1: gpiod_ptd1 {
1089		nxp,kinetis-port-pins = < 1 1 >;
1090	};
1091	SPI0_SCK_PTD1: spi0_sck_ptd1 {
1092		nxp,kinetis-port-pins = < 1 2 >;
1093	};
1094	UART2_CTS_b_PTD1: uart2_cts_b_ptd1 {
1095		nxp,kinetis-port-pins = < 1 3 >;
1096	};
1097	FTM3_CH1_PTD1: ftm3_ch1_ptd1 {
1098		nxp,kinetis-port-pins = < 1 4 >;
1099	};
1100	FTM0_CH1_PTD1: ftm0_ch1_ptd1 {
1101		nxp,kinetis-port-pins = < 1 5 >;
1102	};
1103	FLEXPWM0_B0_PTD1: flexpwm0_b0_ptd1 {
1104		nxp,kinetis-port-pins = < 1 6 >;
1105	};
1106	FLEXPWM1_B0_PTD1: flexpwm1_b0_ptd1 {
1107		nxp,kinetis-port-pins = < 1 9 >;
1108	};
1109	PTD2: GPIOD_PTD2: LLWU_P13_PTD2: gpiod_ptd2 {
1110		nxp,kinetis-port-pins = < 2 1 >;
1111	};
1112	SPI0_SOUT_PTD2: spi0_sout_ptd2 {
1113		nxp,kinetis-port-pins = < 2 2 >;
1114	};
1115	UART2_RX_PTD2: uart2_rx_ptd2 {
1116		nxp,kinetis-port-pins = < 2 3 >;
1117	};
1118	FTM3_CH2_PTD2: ftm3_ch2_ptd2 {
1119		nxp,kinetis-port-pins = < 2 4 >;
1120	};
1121	FTM0_CH2_PTD2: ftm0_ch2_ptd2 {
1122		nxp,kinetis-port-pins = < 2 5 >;
1123	};
1124	FLEXPWM0_A1_PTD2: flexpwm0_a1_ptd2 {
1125		nxp,kinetis-port-pins = < 2 6 >;
1126	};
1127	I2C0_SCL_PTD2: i2c0_scl_ptd2 {
1128		nxp,kinetis-port-pins = < 2 7 >;
1129	};
1130	FLEXPWM1_A1_PTD2: flexpwm1_a1_ptd2 {
1131		nxp,kinetis-port-pins = < 2 9 >;
1132	};
1133	PTD3: GPIOD_PTD3: gpiod_ptd3 {
1134		nxp,kinetis-port-pins = < 3 1 >;
1135	};
1136	SPI0_SIN_PTD3: spi0_sin_ptd3 {
1137		nxp,kinetis-port-pins = < 3 2 >;
1138	};
1139	UART2_TX_PTD3: uart2_tx_ptd3 {
1140		nxp,kinetis-port-pins = < 3 3 >;
1141	};
1142	FTM3_CH3_PTD3: ftm3_ch3_ptd3 {
1143		nxp,kinetis-port-pins = < 3 4 >;
1144	};
1145	FTM0_CH3_PTD3: ftm0_ch3_ptd3 {
1146		nxp,kinetis-port-pins = < 3 5 >;
1147	};
1148	FLEXPWM0_B1_PTD3: flexpwm0_b1_ptd3 {
1149		nxp,kinetis-port-pins = < 3 6 >;
1150	};
1151	I2C0_SDA_PTD3: i2c0_sda_ptd3 {
1152		nxp,kinetis-port-pins = < 3 7 >;
1153	};
1154	FLEXPWM1_B1_PTD3: flexpwm1_b1_ptd3 {
1155		nxp,kinetis-port-pins = < 3 9 >;
1156	};
1157	PTD4: GPIOD_PTD4: LLWU_P14_PTD4: gpiod_ptd4 {
1158		nxp,kinetis-port-pins = < 4 1 >;
1159	};
1160	SPI0_PCS1_PTD4: spi0_pcs1_ptd4 {
1161		nxp,kinetis-port-pins = < 4 2 >;
1162	};
1163	UART0_RTS_b_PTD4: uart0_rts_b_ptd4 {
1164		nxp,kinetis-port-pins = < 4 3 >;
1165	};
1166	FTM0_CH4_PTD4: ftm0_ch4_ptd4 {
1167		nxp,kinetis-port-pins = < 4 4 >;
1168	};
1169	FLEXPWM0_A2_PTD4: flexpwm0_a2_ptd4 {
1170		nxp,kinetis-port-pins = < 4 5 >;
1171	};
1172	EWM_IN_PTD4: ewm_in_ptd4 {
1173		nxp,kinetis-port-pins = < 4 6 >;
1174	};
1175	SPI1_PCS0_PTD4: spi1_pcs0_ptd4 {
1176		nxp,kinetis-port-pins = < 4 7 >;
1177	};
1178	HSADC1A_CH8_PTD5: hsadc1a_ch8_ptd5 {
1179		nxp,kinetis-port-pins = < 5 0 >;
1180	};
1181	PTD5: GPIOD_PTD5: gpiod_ptd5 {
1182		nxp,kinetis-port-pins = < 5 1 >;
1183	};
1184	SPI0_PCS2_PTD5: spi0_pcs2_ptd5 {
1185		nxp,kinetis-port-pins = < 5 2 >;
1186	};
1187	UART0_CTS_b_PTD5: UART0_COL_b_PTD5: uart0_cts_b_ptd5 {
1188		nxp,kinetis-port-pins = < 5 3 >;
1189	};
1190	FTM0_CH5_PTD5: ftm0_ch5_ptd5 {
1191		nxp,kinetis-port-pins = < 5 4 >;
1192	};
1193	FLEXPWM0_B2_PTD5: flexpwm0_b2_ptd5 {
1194		nxp,kinetis-port-pins = < 5 5 >;
1195	};
1196	EWM_OUT_b_PTD5: ewm_out_b_ptd5 {
1197		nxp,kinetis-port-pins = < 5 6 >;
1198	};
1199	SPI1_SCK_PTD5: spi1_sck_ptd5 {
1200		nxp,kinetis-port-pins = < 5 7 >;
1201	};
1202	HSADC1A_CH9_PTD6: hsadc1a_ch9_ptd6 {
1203		nxp,kinetis-port-pins = < 6 0 >;
1204	};
1205	PTD6: GPIOD_PTD6: LLWU_P15_PTD6: gpiod_ptd6 {
1206		nxp,kinetis-port-pins = < 6 1 >;
1207	};
1208	SPI0_PCS3_PTD6: spi0_pcs3_ptd6 {
1209		nxp,kinetis-port-pins = < 6 2 >;
1210	};
1211	UART0_RX_PTD6: uart0_rx_ptd6 {
1212		nxp,kinetis-port-pins = < 6 3 >;
1213	};
1214	FTM0_CH6_PTD6: ftm0_ch6_ptd6 {
1215		nxp,kinetis-port-pins = < 6 4 >;
1216	};
1217	FTM1_CH0_PTD6: ftm1_ch0_ptd6 {
1218		nxp,kinetis-port-pins = < 6 5 >;
1219	};
1220	FTM0_FLT0_PTD6: ftm0_flt0_ptd6 {
1221		nxp,kinetis-port-pins = < 6 6 >;
1222	};
1223	SPI1_SOUT_PTD6: spi1_sout_ptd6 {
1224		nxp,kinetis-port-pins = < 6 7 >;
1225	};
1226	PTD7: GPIOD_PTD7: gpiod_ptd7 {
1227		nxp,kinetis-port-pins = < 7 1 >;
1228	};
1229	UART0_TX_PTD7: uart0_tx_ptd7 {
1230		nxp,kinetis-port-pins = < 7 3 >;
1231	};
1232	FTM0_CH7_PTD7: ftm0_ch7_ptd7 {
1233		nxp,kinetis-port-pins = < 7 4 >;
1234	};
1235	FTM1_CH1_PTD7: ftm1_ch1_ptd7 {
1236		nxp,kinetis-port-pins = < 7 5 >;
1237	};
1238	FTM0_FLT1_PTD7: ftm0_flt1_ptd7 {
1239		nxp,kinetis-port-pins = < 7 6 >;
1240	};
1241	SPI1_SIN_PTD7: spi1_sin_ptd7 {
1242		nxp,kinetis-port-pins = < 7 7 >;
1243	};
1244	PTD8: GPIOD_PTD8: LLWU_P24_PTD8: gpiod_ptd8 {
1245		nxp,kinetis-port-pins = < 8 1 >;
1246	};
1247	I2C1_SCL_PTD8: i2c1_scl_ptd8 {
1248		nxp,kinetis-port-pins = < 8 2 >;
1249	};
1250	UART5_RX_PTD8: uart5_rx_ptd8 {
1251		nxp,kinetis-port-pins = < 8 3 >;
1252	};
1253	FLEXPWM0_A3_PTD8: flexpwm0_a3_ptd8 {
1254		nxp,kinetis-port-pins = < 8 6 >;
1255	};
1256	PTD9: GPIOD_PTD9: gpiod_ptd9 {
1257		nxp,kinetis-port-pins = < 9 1 >;
1258	};
1259	I2C1_SDA_PTD9: i2c1_sda_ptd9 {
1260		nxp,kinetis-port-pins = < 9 2 >;
1261	};
1262	UART5_TX_PTD9: uart5_tx_ptd9 {
1263		nxp,kinetis-port-pins = < 9 3 >;
1264	};
1265	FLEXPWM0_B3_PTD9: flexpwm0_b3_ptd9 {
1266		nxp,kinetis-port-pins = < 9 6 >;
1267	};
1268	PTD10: GPIOD_PTD10: gpiod_ptd10 {
1269		nxp,kinetis-port-pins = < 10 1 >;
1270	};
1271	UART5_RTS_b_PTD10: uart5_rts_b_ptd10 {
1272		nxp,kinetis-port-pins = < 10 3 >;
1273	};
1274	FLEXPWM0_A2_PTD10: flexpwm0_a2_ptd10 {
1275		nxp,kinetis-port-pins = < 10 6 >;
1276	};
1277	PTD11: GPIOD_PTD11: LLWU_P25_PTD11: gpiod_ptd11 {
1278		nxp,kinetis-port-pins = < 11 1 >;
1279	};
1280	SPI2_PCS0_PTD11: spi2_pcs0_ptd11 {
1281		nxp,kinetis-port-pins = < 11 2 >;
1282	};
1283	UART5_CTS_b_PTD11: uart5_cts_b_ptd11 {
1284		nxp,kinetis-port-pins = < 11 3 >;
1285	};
1286	FLEXPWM0_B2_PTD11: flexpwm0_b2_ptd11 {
1287		nxp,kinetis-port-pins = < 11 6 >;
1288	};
1289	PTD12: GPIOD_PTD12: gpiod_ptd12 {
1290		nxp,kinetis-port-pins = < 12 1 >;
1291	};
1292	SPI2_SCK_PTD12: spi2_sck_ptd12 {
1293		nxp,kinetis-port-pins = < 12 2 >;
1294	};
1295	FTM3_FLT0_PTD12: ftm3_flt0_ptd12 {
1296		nxp,kinetis-port-pins = < 12 3 >;
1297	};
1298	XB_IN5_PTD12: xb_in5_ptd12 {
1299		nxp,kinetis-port-pins = < 12 4 >;
1300	};
1301	XB_OUT5_PTD12: xb_out5_ptd12 {
1302		nxp,kinetis-port-pins = < 12 5 >;
1303	};
1304	FLEXPWM0_A1_PTD12: flexpwm0_a1_ptd12 {
1305		nxp,kinetis-port-pins = < 12 6 >;
1306	};
1307	PTD13: GPIOD_PTD13: gpiod_ptd13 {
1308		nxp,kinetis-port-pins = < 13 1 >;
1309	};
1310	SPI2_SOUT_PTD13: spi2_sout_ptd13 {
1311		nxp,kinetis-port-pins = < 13 2 >;
1312	};
1313	XB_IN7_PTD13: xb_in7_ptd13 {
1314		nxp,kinetis-port-pins = < 13 4 >;
1315	};
1316	XB_OUT7_PTD13: xb_out7_ptd13 {
1317		nxp,kinetis-port-pins = < 13 5 >;
1318	};
1319	FLEXPWM0_B1_PTD13: flexpwm0_b1_ptd13 {
1320		nxp,kinetis-port-pins = < 13 6 >;
1321	};
1322	PTD14: GPIOD_PTD14: gpiod_ptd14 {
1323		nxp,kinetis-port-pins = < 14 1 >;
1324	};
1325	SPI2_SIN_PTD14: spi2_sin_ptd14 {
1326		nxp,kinetis-port-pins = < 14 2 >;
1327	};
1328	XB_IN11_PTD14: xb_in11_ptd14 {
1329		nxp,kinetis-port-pins = < 14 4 >;
1330	};
1331	XB_OUT11_PTD14: xb_out11_ptd14 {
1332		nxp,kinetis-port-pins = < 14 5 >;
1333	};
1334	FLEXPWM0_A0_PTD14: flexpwm0_a0_ptd14 {
1335		nxp,kinetis-port-pins = < 14 6 >;
1336	};
1337	PTD15: GPIOD_PTD15: gpiod_ptd15 {
1338		nxp,kinetis-port-pins = < 15 1 >;
1339	};
1340	SPI2_PCS1_PTD15: spi2_pcs1_ptd15 {
1341		nxp,kinetis-port-pins = < 15 2 >;
1342	};
1343	FLEXPWM0_B0_PTD15: flexpwm0_b0_ptd15 {
1344		nxp,kinetis-port-pins = < 15 6 >;
1345	};
1346};
1347
1348&porte {
1349	HSADC0B_CH16_PTE0: HSADC1A_CH0_PTE0: hsadc0b_ch16_pte0 {
1350		nxp,kinetis-port-pins = < 0 0 >;
1351	};
1352	PTE0: GPIOE_PTE0: gpioe_pte0 {
1353		nxp,kinetis-port-pins = < 0 1 >;
1354	};
1355	SPI1_PCS1_PTE0: spi1_pcs1_pte0 {
1356		nxp,kinetis-port-pins = < 0 2 >;
1357	};
1358	UART1_TX_PTE0: uart1_tx_pte0 {
1359		nxp,kinetis-port-pins = < 0 3 >;
1360	};
1361	XB_OUT10_PTE0: xb_out10_pte0 {
1362		nxp,kinetis-port-pins = < 0 4 >;
1363	};
1364	XB_IN11_PTE0: xb_in11_pte0 {
1365		nxp,kinetis-port-pins = < 0 5 >;
1366	};
1367	I2C1_SDA_PTE0: i2c1_sda_pte0 {
1368		nxp,kinetis-port-pins = < 0 6 >;
1369	};
1370	TRACE_CLKOUT_PTE0: trace_clkout_pte0 {
1371		nxp,kinetis-port-pins = < 0 8 >;
1372	};
1373	HSADC0B_CH17_PTE1: HSADC1A_CH1_PTE1: hsadc0b_ch17_pte1 {
1374		nxp,kinetis-port-pins = < 1 0 >;
1375	};
1376	PTE1: GPIOE_PTE1: LLWU_P0_PTE1: gpioe_pte1 {
1377		nxp,kinetis-port-pins = < 1 1 >;
1378	};
1379	SPI1_SOUT_PTE1: spi1_sout_pte1 {
1380		nxp,kinetis-port-pins = < 1 2 >;
1381	};
1382	UART1_RX_PTE1: uart1_rx_pte1 {
1383		nxp,kinetis-port-pins = < 1 3 >;
1384	};
1385	XB_OUT11_PTE1: xb_out11_pte1 {
1386		nxp,kinetis-port-pins = < 1 4 >;
1387	};
1388	XB_IN7_PTE1: xb_in7_pte1 {
1389		nxp,kinetis-port-pins = < 1 5 >;
1390	};
1391	I2C1_SCL_PTE1: i2c1_scl_pte1 {
1392		nxp,kinetis-port-pins = < 1 6 >;
1393	};
1394	TRACE_D3_PTE1: trace_d3_pte1 {
1395		nxp,kinetis-port-pins = < 1 8 >;
1396	};
1397	HSADC0B_CH10_PTE2: HSADC1B_CH0_PTE2: hsadc0b_ch10_pte2 {
1398		nxp,kinetis-port-pins = < 2 0 >;
1399	};
1400	PTE2: GPIOE_PTE2: LLWU_P1_PTE2: gpioe_pte2 {
1401		nxp,kinetis-port-pins = < 2 1 >;
1402	};
1403	SPI1_SCK_PTE2: spi1_sck_pte2 {
1404		nxp,kinetis-port-pins = < 2 2 >;
1405	};
1406	UART1_CTS_b_PTE2: uart1_cts_b_pte2 {
1407		nxp,kinetis-port-pins = < 2 3 >;
1408	};
1409	TRACE_D2_PTE2: trace_d2_pte2 {
1410		nxp,kinetis-port-pins = < 2 8 >;
1411	};
1412	HSADC0B_CH11_PTE3: HSADC1B_CH1_PTE3: hsadc0b_ch11_pte3 {
1413		nxp,kinetis-port-pins = < 3 0 >;
1414	};
1415	PTE3: GPIOE_PTE3: gpioe_pte3 {
1416		nxp,kinetis-port-pins = < 3 1 >;
1417	};
1418	SPI1_SIN_PTE3: spi1_sin_pte3 {
1419		nxp,kinetis-port-pins = < 3 2 >;
1420	};
1421	UART1_RTS_b_PTE3: uart1_rts_b_pte3 {
1422		nxp,kinetis-port-pins = < 3 3 >;
1423	};
1424	TRACE_D1_PTE3: trace_d1_pte3 {
1425		nxp,kinetis-port-pins = < 3 8 >;
1426	};
1427	HSADC1A_CH4_PTE4: ADC0_SE2_PTE4: ADC0_DP2_PTE4: hsadc1a_ch4_pte4 {
1428		nxp,kinetis-port-pins = < 4 0 >;
1429	};
1430	PTE4: GPIOE_PTE4: LLWU_P2_PTE4: gpioe_pte4 {
1431		nxp,kinetis-port-pins = < 4 1 >;
1432	};
1433	SPI1_PCS0_PTE4: spi1_pcs0_pte4 {
1434		nxp,kinetis-port-pins = < 4 2 >;
1435	};
1436	UART3_TX_PTE4: uart3_tx_pte4 {
1437		nxp,kinetis-port-pins = < 4 3 >;
1438	};
1439	TRACE_D0_PTE4: trace_d0_pte4 {
1440		nxp,kinetis-port-pins = < 4 8 >;
1441	};
1442	HSADC1A_CH5_PTE5: ADC0_SE10_PTE5: ADC0_DM2_PTE5: hsadc1a_ch5_pte5 {
1443		nxp,kinetis-port-pins = < 5 0 >;
1444	};
1445	PTE5: GPIOE_PTE5: gpioe_pte5 {
1446		nxp,kinetis-port-pins = < 5 1 >;
1447	};
1448	SPI1_PCS2_PTE5: spi1_pcs2_pte5 {
1449		nxp,kinetis-port-pins = < 5 2 >;
1450	};
1451	UART3_RX_PTE5: uart3_rx_pte5 {
1452		nxp,kinetis-port-pins = < 5 3 >;
1453	};
1454	FLEXPWM1_A0_PTE5: flexpwm1_a0_pte5 {
1455		nxp,kinetis-port-pins = < 5 5 >;
1456	};
1457	FTM3_CH0_PTE5: ftm3_ch0_pte5 {
1458		nxp,kinetis-port-pins = < 5 6 >;
1459	};
1460	HSADC1B_CH7_PTE6: ADC0_SE4a_PTE6: hsadc1b_ch7_pte6 {
1461		nxp,kinetis-port-pins = < 6 0 >;
1462	};
1463	PTE6: GPIOE_PTE6: LLWU_P16_PTE6: gpioe_pte6 {
1464		nxp,kinetis-port-pins = < 6 1 >;
1465	};
1466	SPI1_PCS3_PTE6: spi1_pcs3_pte6 {
1467		nxp,kinetis-port-pins = < 6 2 >;
1468	};
1469	UART3_CTS_b_PTE6: uart3_cts_b_pte6 {
1470		nxp,kinetis-port-pins = < 6 3 >;
1471	};
1472	FLEXPWM1_B0_PTE6: flexpwm1_b0_pte6 {
1473		nxp,kinetis-port-pins = < 6 5 >;
1474	};
1475	FTM3_CH1_PTE6: ftm3_ch1_pte6 {
1476		nxp,kinetis-port-pins = < 6 6 >;
1477	};
1478	PTE7: GPIOE_PTE7: gpioe_pte7 {
1479		nxp,kinetis-port-pins = < 7 1 >;
1480	};
1481	UART3_RTS_b_PTE7: uart3_rts_b_pte7 {
1482		nxp,kinetis-port-pins = < 7 3 >;
1483	};
1484	FLEXPWM1_A1_PTE7: flexpwm1_a1_pte7 {
1485		nxp,kinetis-port-pins = < 7 5 >;
1486	};
1487	FTM3_CH2_PTE7: ftm3_ch2_pte7 {
1488		nxp,kinetis-port-pins = < 7 6 >;
1489	};
1490	PTE8: GPIOE_PTE8: gpioe_pte8 {
1491		nxp,kinetis-port-pins = < 8 1 >;
1492	};
1493	UART5_TX_PTE8: uart5_tx_pte8 {
1494		nxp,kinetis-port-pins = < 8 3 >;
1495	};
1496	FLEXPWM1_B1_PTE8: flexpwm1_b1_pte8 {
1497		nxp,kinetis-port-pins = < 8 5 >;
1498	};
1499	FTM3_CH3_PTE8: ftm3_ch3_pte8 {
1500		nxp,kinetis-port-pins = < 8 6 >;
1501	};
1502	PTE9: GPIOE_PTE9: LLWU_P17_PTE9: gpioe_pte9 {
1503		nxp,kinetis-port-pins = < 9 1 >;
1504	};
1505	UART5_RX_PTE9: uart5_rx_pte9 {
1506		nxp,kinetis-port-pins = < 9 3 >;
1507	};
1508	FLEXPWM1_A2_PTE9: flexpwm1_a2_pte9 {
1509		nxp,kinetis-port-pins = < 9 5 >;
1510	};
1511	FTM3_CH4_PTE9: ftm3_ch4_pte9 {
1512		nxp,kinetis-port-pins = < 9 6 >;
1513	};
1514	PTE10: GPIOE_PTE10: LLWU_P18_PTE10: gpioe_pte10 {
1515		nxp,kinetis-port-pins = < 10 1 >;
1516	};
1517	UART5_CTS_b_PTE10: uart5_cts_b_pte10 {
1518		nxp,kinetis-port-pins = < 10 3 >;
1519	};
1520	FLEXPWM1_B2_PTE10: flexpwm1_b2_pte10 {
1521		nxp,kinetis-port-pins = < 10 5 >;
1522	};
1523	FTM3_CH5_PTE10: ftm3_ch5_pte10 {
1524		nxp,kinetis-port-pins = < 10 6 >;
1525	};
1526	HSADC1A_CH6_PTE11: ADC0_SE3_PTE11: ADC0_DP3_PTE11: hsadc1a_ch6_pte11 {
1527		nxp,kinetis-port-pins = < 11 0 >;
1528	};
1529	PTE11: GPIOE_PTE11: gpioe_pte11 {
1530		nxp,kinetis-port-pins = < 11 1 >;
1531	};
1532	UART5_RTS_b_PTE11: uart5_rts_b_pte11 {
1533		nxp,kinetis-port-pins = < 11 3 >;
1534	};
1535	FLEXPWM1_A3_PTE11: flexpwm1_a3_pte11 {
1536		nxp,kinetis-port-pins = < 11 5 >;
1537	};
1538	FTM3_CH6_PTE11: ftm3_ch6_pte11 {
1539		nxp,kinetis-port-pins = < 11 6 >;
1540	};
1541	HSADC1B_CH6_PTE12: ADC0_SE11_PTE12: ADC0_DM3_PTE12: hsadc1b_ch6_pte12 {
1542		nxp,kinetis-port-pins = < 12 0 >;
1543	};
1544	PTE12: GPIOE_PTE12: gpioe_pte12 {
1545		nxp,kinetis-port-pins = < 12 1 >;
1546	};
1547	FLEXPWM1_B3_PTE12: flexpwm1_b3_pte12 {
1548		nxp,kinetis-port-pins = < 12 5 >;
1549	};
1550	FTM3_CH7_PTE12: ftm3_ch7_pte12 {
1551		nxp,kinetis-port-pins = < 12 6 >;
1552	};
1553	PTE13: GPIOE_PTE13: gpioe_pte13 {
1554		nxp,kinetis-port-pins = < 13 1 >;
1555	};
1556	HSADC0A_CH0_PTE16: ADC0_SE1_PTE16: ADC0_DP1_PTE16: hsadc0a_ch0_pte16 {
1557		nxp,kinetis-port-pins = < 16 0 >;
1558	};
1559	PTE16: GPIOE_PTE16: gpioe_pte16 {
1560		nxp,kinetis-port-pins = < 16 1 >;
1561	};
1562	SPI0_PCS0_PTE16: spi0_pcs0_pte16 {
1563		nxp,kinetis-port-pins = < 16 2 >;
1564	};
1565	UART2_TX_PTE16: uart2_tx_pte16 {
1566		nxp,kinetis-port-pins = < 16 3 >;
1567	};
1568	FTM_CLKIN0_PTE16: ftm_clkin0_pte16 {
1569		nxp,kinetis-port-pins = < 16 4 >;
1570	};
1571	FTM0_FLT3_PTE16: ftm0_flt3_pte16 {
1572		nxp,kinetis-port-pins = < 16 6 >;
1573	};
1574	HSADC0A_CH1_PTE17: ADC0_SE9_PTE17: ADC0_DM1_PTE17: hsadc0a_ch1_pte17 {
1575		nxp,kinetis-port-pins = < 17 0 >;
1576	};
1577	PTE17: GPIOE_PTE17: LLWU_P19_PTE17: gpioe_pte17 {
1578		nxp,kinetis-port-pins = < 17 1 >;
1579	};
1580	SPI0_SCK_PTE17: spi0_sck_pte17 {
1581		nxp,kinetis-port-pins = < 17 2 >;
1582	};
1583	UART2_RX_PTE17: uart2_rx_pte17 {
1584		nxp,kinetis-port-pins = < 17 3 >;
1585	};
1586	FTM_CLKIN1_PTE17: ftm_clkin1_pte17 {
1587		nxp,kinetis-port-pins = < 17 4 >;
1588	};
1589	LPTMR0_ALT3_PTE17: lptmr0_alt3_pte17 {
1590		nxp,kinetis-port-pins = < 17 6 >;
1591	};
1592	HSADC0B_CH0_PTE18: ADC0_SE5a_PTE18: hsadc0b_ch0_pte18 {
1593		nxp,kinetis-port-pins = < 18 0 >;
1594	};
1595	PTE18: GPIOE_PTE18: LLWU_P20_PTE18: gpioe_pte18 {
1596		nxp,kinetis-port-pins = < 18 1 >;
1597	};
1598	SPI0_SOUT_PTE18: spi0_sout_pte18 {
1599		nxp,kinetis-port-pins = < 18 2 >;
1600	};
1601	UART2_CTS_b_PTE18: uart2_cts_b_pte18 {
1602		nxp,kinetis-port-pins = < 18 3 >;
1603	};
1604	I2C0_SDA_PTE18: i2c0_sda_pte18 {
1605		nxp,kinetis-port-pins = < 18 4 >;
1606	};
1607	HSADC0B_CH1_PTE19: ADC0_SE6a_PTE19: hsadc0b_ch1_pte19 {
1608		nxp,kinetis-port-pins = < 19 0 >;
1609	};
1610	PTE19: GPIOE_PTE19: gpioe_pte19 {
1611		nxp,kinetis-port-pins = < 19 1 >;
1612	};
1613	SPI0_SIN_PTE19: spi0_sin_pte19 {
1614		nxp,kinetis-port-pins = < 19 2 >;
1615	};
1616	UART2_RTS_b_PTE19: uart2_rts_b_pte19 {
1617		nxp,kinetis-port-pins = < 19 3 >;
1618	};
1619	I2C0_SCL_PTE19: i2c0_scl_pte19 {
1620		nxp,kinetis-port-pins = < 19 4 >;
1621	};
1622	CMP3_OUT_PTE19: cmp3_out_pte19 {
1623		nxp,kinetis-port-pins = < 19 6 >;
1624	};
1625	HSADC0A_CH8_PTE20: ADC0_SE5b_PTE20: hsadc0a_ch8_pte20 {
1626		nxp,kinetis-port-pins = < 20 0 >;
1627	};
1628	PTE20: GPIOE_PTE20: gpioe_pte20 {
1629		nxp,kinetis-port-pins = < 20 1 >;
1630	};
1631	FTM1_CH0_PTE20: ftm1_ch0_pte20 {
1632		nxp,kinetis-port-pins = < 20 3 >;
1633	};
1634	UART0_TX_PTE20: uart0_tx_pte20 {
1635		nxp,kinetis-port-pins = < 20 4 >;
1636	};
1637	FTM1_QD_PHA_PTE20: ftm1_qd_pha_pte20 {
1638		nxp,kinetis-port-pins = < 20 5 >;
1639	};
1640	HSADC0A_CH9_PTE21: HSADC1A_CH7_PTE21: hsadc0a_ch9_pte21 {
1641		nxp,kinetis-port-pins = < 21 0 >;
1642	};
1643	PTE21: GPIOE_PTE21: gpioe_pte21 {
1644		nxp,kinetis-port-pins = < 21 1 >;
1645	};
1646	XB_IN9_PTE21: xb_in9_pte21 {
1647		nxp,kinetis-port-pins = < 21 2 >;
1648	};
1649	FTM1_CH1_PTE21: ftm1_ch1_pte21 {
1650		nxp,kinetis-port-pins = < 21 3 >;
1651	};
1652	UART0_RX_PTE21: uart0_rx_pte21 {
1653		nxp,kinetis-port-pins = < 21 4 >;
1654	};
1655	FTM1_QD_PHB_PTE21: ftm1_qd_phb_pte21 {
1656		nxp,kinetis-port-pins = < 21 5 >;
1657	};
1658	PTE22: GPIOE_PTE22: gpioe_pte22 {
1659		nxp,kinetis-port-pins = < 22 1 >;
1660	};
1661	FTM2_CH0_PTE22: ftm2_ch0_pte22 {
1662		nxp,kinetis-port-pins = < 22 3 >;
1663	};
1664	XB_IN2_PTE22: xb_in2_pte22 {
1665		nxp,kinetis-port-pins = < 22 4 >;
1666	};
1667	FTM2_QD_PHA_PTE22: ftm2_qd_pha_pte22 {
1668		nxp,kinetis-port-pins = < 22 5 >;
1669	};
1670	PTE23: GPIOE_PTE23: gpioe_pte23 {
1671		nxp,kinetis-port-pins = < 23 1 >;
1672	};
1673	FTM2_CH1_PTE23: ftm2_ch1_pte23 {
1674		nxp,kinetis-port-pins = < 23 3 >;
1675	};
1676	XB_IN3_PTE23: xb_in3_pte23 {
1677		nxp,kinetis-port-pins = < 23 4 >;
1678	};
1679	FTM2_QD_PHB_PTE23: ftm2_qd_phb_pte23 {
1680		nxp,kinetis-port-pins = < 23 5 >;
1681	};
1682	HSADC0B_CH4_PTE24: HSADC1B_CH4_PTE24: hsadc0b_ch4_pte24 {
1683		nxp,kinetis-port-pins = < 24 0 >;
1684	};
1685	PTE24: GPIOE_PTE24: gpioe_pte24 {
1686		nxp,kinetis-port-pins = < 24 1 >;
1687	};
1688	CAN1_TX_PTE24: can1_tx_pte24 {
1689		nxp,kinetis-port-pins = < 24 2 >;
1690	};
1691	FTM0_CH0_PTE24: ftm0_ch0_pte24 {
1692		nxp,kinetis-port-pins = < 24 3 >;
1693	};
1694	XB_IN2_PTE24: xb_in2_pte24 {
1695		nxp,kinetis-port-pins = < 24 4 >;
1696	};
1697	I2C0_SCL_PTE24: i2c0_scl_pte24 {
1698		nxp,kinetis-port-pins = < 24 5 >;
1699	};
1700	EWM_OUT_b_PTE24: ewm_out_b_pte24 {
1701		nxp,kinetis-port-pins = < 24 6 >;
1702	};
1703	XB_OUT4_PTE24: xb_out4_pte24 {
1704		nxp,kinetis-port-pins = < 24 7 >;
1705	};
1706	UART4_TX_PTE24: uart4_tx_pte24 {
1707		nxp,kinetis-port-pins = < 24 8 >;
1708	};
1709	HSADC0B_CH5_PTE25: HSADC1B_CH5_PTE25: hsadc0b_ch5_pte25 {
1710		nxp,kinetis-port-pins = < 25 0 >;
1711	};
1712	PTE25: GPIOE_PTE25: LLWU_P21_PTE25: gpioe_pte25 {
1713		nxp,kinetis-port-pins = < 25 1 >;
1714	};
1715	CAN1_RX_PTE25: can1_rx_pte25 {
1716		nxp,kinetis-port-pins = < 25 2 >;
1717	};
1718	FTM0_CH1_PTE25: ftm0_ch1_pte25 {
1719		nxp,kinetis-port-pins = < 25 3 >;
1720	};
1721	XB_IN3_PTE25: xb_in3_pte25 {
1722		nxp,kinetis-port-pins = < 25 4 >;
1723	};
1724	I2C0_SDA_PTE25: i2c0_sda_pte25 {
1725		nxp,kinetis-port-pins = < 25 5 >;
1726	};
1727	XB_OUT5_PTE25: xb_out5_pte25 {
1728		nxp,kinetis-port-pins = < 25 7 >;
1729	};
1730	UART4_RX_PTE25: uart4_rx_pte25 {
1731		nxp,kinetis-port-pins = < 25 8 >;
1732	};
1733	PTE26: GPIOE_PTE26: gpioe_pte26 {
1734		nxp,kinetis-port-pins = < 26 1 >;
1735	};
1736	ENET_1588_CLKIN_PTE26: enet_1588_clkin_pte26 {
1737		nxp,kinetis-port-pins = < 26 2 >;
1738	};
1739	FTM0_CH4_PTE26: ftm0_ch4_pte26 {
1740		nxp,kinetis-port-pins = < 26 3 >;
1741	};
1742	UART4_CTS_b_PTE26: uart4_cts_b_pte26 {
1743		nxp,kinetis-port-pins = < 26 8 >;
1744	};
1745	PTE27: GPIOE_PTE27: gpioe_pte27 {
1746		nxp,kinetis-port-pins = < 27 1 >;
1747	};
1748	CAN2_TX_PTE27: can2_tx_pte27 {
1749		nxp,kinetis-port-pins = < 27 2 >;
1750	};
1751	UART4_RTS_b_PTE27: uart4_rts_b_pte27 {
1752		nxp,kinetis-port-pins = < 27 8 >;
1753	};
1754	PTE28: GPIOE_PTE28: gpioe_pte28 {
1755		nxp,kinetis-port-pins = < 28 1 >;
1756	};
1757	CAN2_RX_PTE28: can2_rx_pte28 {
1758		nxp,kinetis-port-pins = < 28 2 >;
1759	};
1760	HSADC0A_CH4_PTE29: CMP1_IN5_PTE29: CMP0_IN5_PTE29: hsadc0a_ch4_pte29 {
1761		nxp,kinetis-port-pins = < 29 0 >;
1762	};
1763	PTE29: GPIOE_PTE29: gpioe_pte29 {
1764		nxp,kinetis-port-pins = < 29 1 >;
1765	};
1766	FTM0_CH2_PTE29: ftm0_ch2_pte29 {
1767		nxp,kinetis-port-pins = < 29 3 >;
1768	};
1769	FTM_CLKIN0_PTE29: ftm_clkin0_pte29 {
1770		nxp,kinetis-port-pins = < 29 5 >;
1771	};
1772	DAC0_OUT_PTE30: CMP1_IN3_PTE30: HSADC0A_CH5_PTE30: dac0_out_pte30 {
1773		nxp,kinetis-port-pins = < 30 0 >;
1774	};
1775	PTE30: GPIOE_PTE30: gpioe_pte30 {
1776		nxp,kinetis-port-pins = < 30 1 >;
1777	};
1778	FTM0_CH3_PTE30: ftm0_ch3_pte30 {
1779		nxp,kinetis-port-pins = < 30 3 >;
1780	};
1781	FTM_CLKIN1_PTE30: ftm_clkin1_pte30 {
1782		nxp,kinetis-port-pins = < 30 5 >;
1783	};
1784};
1785
1786