/*
 * NOTE: Autogenerated file by kinetis_signal2dts.py
 *       for MKV58F1M0VLQ24/signal_configuration.xml
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/*
 * Pin nodes are of the form:
 *
 *	<SIGNAL[0..n]>: <signal[0]> {
 *		nxp,kinetis-port-pins = < PIN PCR[MUX] >;
 *	};
 */

&porta {
	PTA0: GPIOA_PTA0: gpioa_pta0 {
		nxp,kinetis-port-pins = < 0 1 >;
	};
	UART0_CTS_b_PTA0: UART0_COL_b_PTA0: uart0_cts_b_pta0 {
		nxp,kinetis-port-pins = < 0 2 >;
	};
	FTM0_CH5_PTA0: ftm0_ch5_pta0 {
		nxp,kinetis-port-pins = < 0 3 >;
	};
	XB_IN4_PTA0: xb_in4_pta0 {
		nxp,kinetis-port-pins = < 0 4 >;
	};
	JTAG_TCLK_PTA0: jtag_tclk_pta0 {
		nxp,kinetis-port-pins = < 0 7 >;
	};
	PTA1: GPIOA_PTA1: gpioa_pta1 {
		nxp,kinetis-port-pins = < 1 1 >;
	};
	UART0_RX_PTA1: uart0_rx_pta1 {
		nxp,kinetis-port-pins = < 1 2 >;
	};
	FTM0_CH6_PTA1: ftm0_ch6_pta1 {
		nxp,kinetis-port-pins = < 1 3 >;
	};
	CMP0_OUT_PTA1: cmp0_out_pta1 {
		nxp,kinetis-port-pins = < 1 4 >;
	};
	FTM2_QD_PHA_PTA1: ftm2_qd_pha_pta1 {
		nxp,kinetis-port-pins = < 1 5 >;
	};
	FTM1_CH1_PTA1: ftm1_ch1_pta1 {
		nxp,kinetis-port-pins = < 1 6 >;
	};
	JTAG_TDI_PTA1: jtag_tdi_pta1 {
		nxp,kinetis-port-pins = < 1 7 >;
	};
	PTA2: GPIOA_PTA2: gpioa_pta2 {
		nxp,kinetis-port-pins = < 2 1 >;
	};
	UART0_TX_PTA2: uart0_tx_pta2 {
		nxp,kinetis-port-pins = < 2 2 >;
	};
	FTM0_CH7_PTA2: ftm0_ch7_pta2 {
		nxp,kinetis-port-pins = < 2 3 >;
	};
	CMP1_OUT_PTA2: cmp1_out_pta2 {
		nxp,kinetis-port-pins = < 2 4 >;
	};
	FTM2_QD_PHB_PTA2: ftm2_qd_phb_pta2 {
		nxp,kinetis-port-pins = < 2 5 >;
	};
	FTM1_CH0_PTA2: ftm1_ch0_pta2 {
		nxp,kinetis-port-pins = < 2 6 >;
	};
	JTAG_TDO_PTA2: TRACE_SWO_PTA2: jtag_tdo_pta2 {
		nxp,kinetis-port-pins = < 2 7 >;
	};
	PTA3: GPIOA_PTA3: gpioa_pta3 {
		nxp,kinetis-port-pins = < 3 1 >;
	};
	UART0_RTS_b_PTA3: uart0_rts_b_pta3 {
		nxp,kinetis-port-pins = < 3 2 >;
	};
	FTM0_CH0_PTA3: ftm0_ch0_pta3 {
		nxp,kinetis-port-pins = < 3 3 >;
	};
	XB_IN9_PTA3: xb_in9_pta3 {
		nxp,kinetis-port-pins = < 3 4 >;
	};
	EWM_OUT_b_PTA3: ewm_out_b_pta3 {
		nxp,kinetis-port-pins = < 3 5 >;
	};
	FLEXPWM0_A0_PTA3: flexpwm0_a0_pta3 {
		nxp,kinetis-port-pins = < 3 6 >;
	};
	JTAG_TMS_PTA3: jtag_tms_pta3 {
		nxp,kinetis-port-pins = < 3 7 >;
	};
	PTA4: GPIOA_PTA4: LLWU_P3_PTA4: gpioa_pta4 {
		nxp,kinetis-port-pins = < 4 1 >;
	};
	FTM0_CH1_PTA4: ftm0_ch1_pta4 {
		nxp,kinetis-port-pins = < 4 3 >;
	};
	XB_IN10_PTA4: xb_in10_pta4 {
		nxp,kinetis-port-pins = < 4 4 >;
	};
	FLEXPWM0_B0_PTA4: flexpwm0_b0_pta4 {
		nxp,kinetis-port-pins = < 4 6 >;
	};
	NMI_b_PTA4: nmi_b_pta4 {
		nxp,kinetis-port-pins = < 4 7 >;
	};
	PTA5: GPIOA_PTA5: gpioa_pta5 {
		nxp,kinetis-port-pins = < 5 1 >;
	};
	FTM0_CH2_PTA5: ftm0_ch2_pta5 {
		nxp,kinetis-port-pins = < 5 3 >;
	};
	RMII0_RXER_PTA5: MII0_RXER_PTA5: rmii0_rxer_pta5 {
		nxp,kinetis-port-pins = < 5 4 >;
	};
	CMP2_OUT_PTA5: cmp2_out_pta5 {
		nxp,kinetis-port-pins = < 5 5 >;
	};
	JTAG_TRST_b_PTA5: jtag_trst_b_pta5 {
		nxp,kinetis-port-pins = < 5 7 >;
	};
	PTA6: GPIOA_PTA6: gpioa_pta6 {
		nxp,kinetis-port-pins = < 6 1 >;
	};
	FTM0_CH3_PTA6: ftm0_ch3_pta6 {
		nxp,kinetis-port-pins = < 6 3 >;
	};
	CLKOUT_PTA6: clkout_pta6 {
		nxp,kinetis-port-pins = < 6 5 >;
	};
	TRACE_CLKOUT_PTA6: trace_clkout_pta6 {
		nxp,kinetis-port-pins = < 6 7 >;
	};
	HSADC1B_CH8_PTA7: hsadc1b_ch8_pta7 {
		nxp,kinetis-port-pins = < 7 0 >;
	};
	PTA7: GPIOA_PTA7: gpioa_pta7 {
		nxp,kinetis-port-pins = < 7 1 >;
	};
	FTM0_CH4_PTA7: ftm0_ch4_pta7 {
		nxp,kinetis-port-pins = < 7 3 >;
	};
	RMII0_MDIO_PTA7: MII0_MDIO_PTA7: rmii0_mdio_pta7 {
		nxp,kinetis-port-pins = < 7 5 >;
	};
	TRACE_D3_PTA7: trace_d3_pta7 {
		nxp,kinetis-port-pins = < 7 7 >;
	};
	HSADC1B_CH9_PTA8: hsadc1b_ch9_pta8 {
		nxp,kinetis-port-pins = < 8 0 >;
	};
	PTA8: GPIOA_PTA8: gpioa_pta8 {
		nxp,kinetis-port-pins = < 8 1 >;
	};
	FTM1_CH0_PTA8: ftm1_ch0_pta8 {
		nxp,kinetis-port-pins = < 8 3 >;
	};
	RMII0_MDC_PTA8: MII0_MDC_PTA8: rmii0_mdc_pta8 {
		nxp,kinetis-port-pins = < 8 5 >;
	};
	TRACE_D2_PTA8: trace_d2_pta8 {
		nxp,kinetis-port-pins = < 8 7 >;
	};
	PTA9: GPIOA_PTA9: gpioa_pta9 {
		nxp,kinetis-port-pins = < 9 1 >;
	};
	FTM1_CH1_PTA9: ftm1_ch1_pta9 {
		nxp,kinetis-port-pins = < 9 3 >;
	};
	MII0_RXD3_PTA9: mii0_rxd3_pta9 {
		nxp,kinetis-port-pins = < 9 5 >;
	};
	TRACE_D1_PTA9: trace_d1_pta9 {
		nxp,kinetis-port-pins = < 9 7 >;
	};
	PTA10: GPIOA_PTA10: LLWU_P22_PTA10: gpioa_pta10 {
		nxp,kinetis-port-pins = < 10 1 >;
	};
	FTM2_CH0_PTA10: ftm2_ch0_pta10 {
		nxp,kinetis-port-pins = < 10 3 >;
	};
	MII0_RXD2_PTA10: mii0_rxd2_pta10 {
		nxp,kinetis-port-pins = < 10 5 >;
	};
	FTM2_QD_PHA_PTA10: ftm2_qd_pha_pta10 {
		nxp,kinetis-port-pins = < 10 6 >;
	};
	TRACE_D0_PTA10: trace_d0_pta10 {
		nxp,kinetis-port-pins = < 10 7 >;
	};
	PTA11: GPIOA_PTA11: LLWU_P23_PTA11: gpioa_pta11 {
		nxp,kinetis-port-pins = < 11 1 >;
	};
	FTM2_CH1_PTA11: ftm2_ch1_pta11 {
		nxp,kinetis-port-pins = < 11 3 >;
	};
	MII0_RXCLK_PTA11: mii0_rxclk_pta11 {
		nxp,kinetis-port-pins = < 11 5 >;
	};
	FTM2_QD_PHB_PTA11: ftm2_qd_phb_pta11 {
		nxp,kinetis-port-pins = < 11 6 >;
	};
	I2C0_SDA_PTA11: i2c0_sda_pta11 {
		nxp,kinetis-port-pins = < 11 8 >;
	};
	CMP2_IN0_PTA12: cmp2_in0_pta12 {
		nxp,kinetis-port-pins = < 12 0 >;
	};
	PTA12: GPIOA_PTA12: gpioa_pta12 {
		nxp,kinetis-port-pins = < 12 1 >;
	};
	CAN0_TX_PTA12: can0_tx_pta12 {
		nxp,kinetis-port-pins = < 12 2 >;
	};
	FTM1_CH0_PTA12: ftm1_ch0_pta12 {
		nxp,kinetis-port-pins = < 12 3 >;
	};
	RMII0_RXD1_PTA12: MII0_RXD1_PTA12: rmii0_rxd1_pta12 {
		nxp,kinetis-port-pins = < 12 5 >;
	};
	FTM1_QD_PHA_PTA12: ftm1_qd_pha_pta12 {
		nxp,kinetis-port-pins = < 12 7 >;
	};
	I2C0_SCL_PTA12: i2c0_scl_pta12 {
		nxp,kinetis-port-pins = < 12 8 >;
	};
	CMP2_IN1_PTA13: cmp2_in1_pta13 {
		nxp,kinetis-port-pins = < 13 0 >;
	};
	PTA13: GPIOA_PTA13: LLWU_P4_PTA13: gpioa_pta13 {
		nxp,kinetis-port-pins = < 13 1 >;
	};
	CAN0_RX_PTA13: can0_rx_pta13 {
		nxp,kinetis-port-pins = < 13 2 >;
	};
	FTM1_CH1_PTA13: ftm1_ch1_pta13 {
		nxp,kinetis-port-pins = < 13 3 >;
	};
	RMII0_RXD0_PTA13: MII0_RXD0_PTA13: rmii0_rxd0_pta13 {
		nxp,kinetis-port-pins = < 13 5 >;
	};
	FTM1_QD_PHB_PTA13: ftm1_qd_phb_pta13 {
		nxp,kinetis-port-pins = < 13 7 >;
	};
	I2C1_SDA_PTA13: i2c1_sda_pta13 {
		nxp,kinetis-port-pins = < 13 8 >;
	};
	CMP3_IN0_PTA14: cmp3_in0_pta14 {
		nxp,kinetis-port-pins = < 14 0 >;
	};
	PTA14: GPIOA_PTA14: gpioa_pta14 {
		nxp,kinetis-port-pins = < 14 1 >;
	};
	SPI0_PCS0_PTA14: spi0_pcs0_pta14 {
		nxp,kinetis-port-pins = < 14 2 >;
	};
	UART0_TX_PTA14: uart0_tx_pta14 {
		nxp,kinetis-port-pins = < 14 3 >;
	};
	CAN2_TX_PTA14: can2_tx_pta14 {
		nxp,kinetis-port-pins = < 14 4 >;
	};
	RMII0_CRS_DV_PTA14: MII0_RXDV_PTA14: rmii0_crs_dv_pta14 {
		nxp,kinetis-port-pins = < 14 5 >;
	};
	I2C1_SCL_PTA14: i2c1_scl_pta14 {
		nxp,kinetis-port-pins = < 14 8 >;
	};
	CMP3_IN1_PTA15: cmp3_in1_pta15 {
		nxp,kinetis-port-pins = < 15 0 >;
	};
	PTA15: GPIOA_PTA15: gpioa_pta15 {
		nxp,kinetis-port-pins = < 15 1 >;
	};
	SPI0_SCK_PTA15: spi0_sck_pta15 {
		nxp,kinetis-port-pins = < 15 2 >;
	};
	UART0_RX_PTA15: uart0_rx_pta15 {
		nxp,kinetis-port-pins = < 15 3 >;
	};
	CAN2_RX_PTA15: can2_rx_pta15 {
		nxp,kinetis-port-pins = < 15 4 >;
	};
	RMII0_TXEN_PTA15: MII0_TXEN_PTA15: rmii0_txen_pta15 {
		nxp,kinetis-port-pins = < 15 5 >;
	};
	CMP3_IN2_PTA16: cmp3_in2_pta16 {
		nxp,kinetis-port-pins = < 16 0 >;
	};
	PTA16: GPIOA_PTA16: gpioa_pta16 {
		nxp,kinetis-port-pins = < 16 1 >;
	};
	SPI0_SOUT_PTA16: spi0_sout_pta16 {
		nxp,kinetis-port-pins = < 16 2 >;
	};
	UART0_CTS_b_PTA16: UART0_COL_b_PTA16: uart0_cts_b_pta16 {
		nxp,kinetis-port-pins = < 16 3 >;
	};
	RMII0_TXD0_PTA16: MII0_TXD0_PTA16: rmii0_txd0_pta16 {
		nxp,kinetis-port-pins = < 16 5 >;
	};
	HSADC0A_CH15_PTA17: hsadc0a_ch15_pta17 {
		nxp,kinetis-port-pins = < 17 0 >;
	};
	PTA17: GPIOA_PTA17: gpioa_pta17 {
		nxp,kinetis-port-pins = < 17 1 >;
	};
	SPI0_SIN_PTA17: spi0_sin_pta17 {
		nxp,kinetis-port-pins = < 17 2 >;
	};
	UART0_RTS_b_PTA17: uart0_rts_b_pta17 {
		nxp,kinetis-port-pins = < 17 3 >;
	};
	RMII0_TXD1_PTA17: MII0_TXD1_PTA17: rmii0_txd1_pta17 {
		nxp,kinetis-port-pins = < 17 5 >;
	};
	EXTAL0_PTA18: extal0_pta18 {
		nxp,kinetis-port-pins = < 18 0 >;
	};
	PTA18: GPIOA_PTA18: gpioa_pta18 {
		nxp,kinetis-port-pins = < 18 1 >;
	};
	XB_IN7_PTA18: xb_in7_pta18 {
		nxp,kinetis-port-pins = < 18 2 >;
	};
	FTM0_FLT2_PTA18: ftm0_flt2_pta18 {
		nxp,kinetis-port-pins = < 18 3 >;
	};
	FTM_CLKIN0_PTA18: ftm_clkin0_pta18 {
		nxp,kinetis-port-pins = < 18 4 >;
	};
	XB_OUT8_PTA18: xb_out8_pta18 {
		nxp,kinetis-port-pins = < 18 5 >;
	};
	FTM3_CH2_PTA18: ftm3_ch2_pta18 {
		nxp,kinetis-port-pins = < 18 6 >;
	};
	XTAL0_PTA19: xtal0_pta19 {
		nxp,kinetis-port-pins = < 19 0 >;
	};
	PTA19: GPIOA_PTA19: gpioa_pta19 {
		nxp,kinetis-port-pins = < 19 1 >;
	};
	XB_IN8_PTA19: xb_in8_pta19 {
		nxp,kinetis-port-pins = < 19 2 >;
	};
	FTM1_FLT0_PTA19: ftm1_flt0_pta19 {
		nxp,kinetis-port-pins = < 19 3 >;
	};
	FTM_CLKIN1_PTA19: ftm_clkin1_pta19 {
		nxp,kinetis-port-pins = < 19 4 >;
	};
	XB_OUT9_PTA19: xb_out9_pta19 {
		nxp,kinetis-port-pins = < 19 5 >;
	};
	LPTMR0_ALT1_PTA19: lptmr0_alt1_pta19 {
		nxp,kinetis-port-pins = < 19 6 >;
	};
	PTA24: GPIOA_PTA24: gpioa_pta24 {
		nxp,kinetis-port-pins = < 24 1 >;
	};
	XB_IN4_PTA24: xb_in4_pta24 {
		nxp,kinetis-port-pins = < 24 2 >;
	};
	MII0_TXD2_PTA24: mii0_txd2_pta24 {
		nxp,kinetis-port-pins = < 24 5 >;
	};
	PTA25: GPIOA_PTA25: gpioa_pta25 {
		nxp,kinetis-port-pins = < 25 1 >;
	};
	XB_IN5_PTA25: xb_in5_pta25 {
		nxp,kinetis-port-pins = < 25 2 >;
	};
	MII0_TXCLK_PTA25: mii0_txclk_pta25 {
		nxp,kinetis-port-pins = < 25 5 >;
	};
	PTA26: GPIOA_PTA26: gpioa_pta26 {
		nxp,kinetis-port-pins = < 26 1 >;
	};
	MII0_TXD3_PTA26: mii0_txd3_pta26 {
		nxp,kinetis-port-pins = < 26 5 >;
	};
	PTA27: GPIOA_PTA27: gpioa_pta27 {
		nxp,kinetis-port-pins = < 27 1 >;
	};
	MII0_CRS_PTA27: mii0_crs_pta27 {
		nxp,kinetis-port-pins = < 27 5 >;
	};
	PTA28: GPIOA_PTA28: gpioa_pta28 {
		nxp,kinetis-port-pins = < 28 1 >;
	};
	MII0_TXER_PTA28: mii0_txer_pta28 {
		nxp,kinetis-port-pins = < 28 5 >;
	};
	PTA29: GPIOA_PTA29: gpioa_pta29 {
		nxp,kinetis-port-pins = < 29 1 >;
	};
	MII0_COL_PTA29: mii0_col_pta29 {
		nxp,kinetis-port-pins = < 29 5 >;
	};
};

&portb {
	HSADC0B_CH2_PTB0: hsadc0b_ch2_ptb0 {
		nxp,kinetis-port-pins = < 0 0 >;
	};
	PTB0: GPIOB_PTB0: LLWU_P5_PTB0: gpiob_ptb0 {
		nxp,kinetis-port-pins = < 0 1 >;
	};
	I2C0_SCL_PTB0: i2c0_scl_ptb0 {
		nxp,kinetis-port-pins = < 0 2 >;
	};
	FTM1_CH0_PTB0: ftm1_ch0_ptb0 {
		nxp,kinetis-port-pins = < 0 3 >;
	};
	FTM1_QD_PHA_PTB0: ftm1_qd_pha_ptb0 {
		nxp,kinetis-port-pins = < 0 6 >;
	};
	UART0_RX_PTB0: uart0_rx_ptb0 {
		nxp,kinetis-port-pins = < 0 7 >;
	};
	RMII0_MDIO_PTB0: MII0_MDIO_PTB0: rmii0_mdio_ptb0 {
		nxp,kinetis-port-pins = < 0 8 >;
	};
	HSADC0B_CH3_PTB1: hsadc0b_ch3_ptb1 {
		nxp,kinetis-port-pins = < 1 0 >;
	};
	PTB1: GPIOB_PTB1: gpiob_ptb1 {
		nxp,kinetis-port-pins = < 1 1 >;
	};
	I2C0_SDA_PTB1: i2c0_sda_ptb1 {
		nxp,kinetis-port-pins = < 1 2 >;
	};
	FTM1_CH1_PTB1: ftm1_ch1_ptb1 {
		nxp,kinetis-port-pins = < 1 3 >;
	};
	FTM0_FLT2_PTB1: ftm0_flt2_ptb1 {
		nxp,kinetis-port-pins = < 1 4 >;
	};
	EWM_IN_PTB1: ewm_in_ptb1 {
		nxp,kinetis-port-pins = < 1 5 >;
	};
	FTM1_QD_PHB_PTB1: ftm1_qd_phb_ptb1 {
		nxp,kinetis-port-pins = < 1 6 >;
	};
	UART0_TX_PTB1: uart0_tx_ptb1 {
		nxp,kinetis-port-pins = < 1 7 >;
	};
	RMII0_MDC_PTB1: MII0_MDC_PTB1: rmii0_mdc_ptb1 {
		nxp,kinetis-port-pins = < 1 8 >;
	};
	HSADC0A_CH14_PTB2: CMP2_IN2_PTB2: hsadc0a_ch14_ptb2 {
		nxp,kinetis-port-pins = < 2 0 >;
	};
	PTB2: GPIOB_PTB2: gpiob_ptb2 {
		nxp,kinetis-port-pins = < 2 1 >;
	};
	I2C0_SCL_PTB2: i2c0_scl_ptb2 {
		nxp,kinetis-port-pins = < 2 2 >;
	};
	UART0_RTS_b_PTB2: uart0_rts_b_ptb2 {
		nxp,kinetis-port-pins = < 2 3 >;
	};
	FTM0_FLT1_PTB2: ftm0_flt1_ptb2 {
		nxp,kinetis-port-pins = < 2 4 >;
	};
	ENET0_1588_TMR0_PTB2: enet0_1588_tmr0_ptb2 {
		nxp,kinetis-port-pins = < 2 5 >;
	};
	FTM0_FLT3_PTB2: ftm0_flt3_ptb2 {
		nxp,kinetis-port-pins = < 2 6 >;
	};
	HSADC0B_CH15_PTB3: CMP3_IN5_PTB3: hsadc0b_ch15_ptb3 {
		nxp,kinetis-port-pins = < 3 0 >;
	};
	PTB3: GPIOB_PTB3: gpiob_ptb3 {
		nxp,kinetis-port-pins = < 3 1 >;
	};
	I2C0_SDA_PTB3: i2c0_sda_ptb3 {
		nxp,kinetis-port-pins = < 3 2 >;
	};
	UART0_CTS_b_PTB3: UART0_COL_b_PTB3: uart0_cts_b_ptb3 {
		nxp,kinetis-port-pins = < 3 3 >;
	};
	ENET0_1588_TMR1_PTB3: enet0_1588_tmr1_ptb3 {
		nxp,kinetis-port-pins = < 3 5 >;
	};
	FTM0_FLT0_PTB3: ftm0_flt0_ptb3 {
		nxp,kinetis-port-pins = < 3 6 >;
	};
	ADC0_SE6b_PTB4: adc0_se6b_ptb4 {
		nxp,kinetis-port-pins = < 4 0 >;
	};
	PTB4: GPIOB_PTB4: gpiob_ptb4 {
		nxp,kinetis-port-pins = < 4 1 >;
	};
	FLEXPWM1_X0_PTB4: flexpwm1_x0_ptb4 {
		nxp,kinetis-port-pins = < 4 4 >;
	};
	ENET0_1588_TMR2_PTB4: enet0_1588_tmr2_ptb4 {
		nxp,kinetis-port-pins = < 4 5 >;
	};
	FTM1_FLT0_PTB4: ftm1_flt0_ptb4 {
		nxp,kinetis-port-pins = < 4 6 >;
	};
	ADC0_SE7b_PTB5: adc0_se7b_ptb5 {
		nxp,kinetis-port-pins = < 5 0 >;
	};
	PTB5: GPIOB_PTB5: gpiob_ptb5 {
		nxp,kinetis-port-pins = < 5 1 >;
	};
	FLEXPWM1_X1_PTB5: flexpwm1_x1_ptb5 {
		nxp,kinetis-port-pins = < 5 4 >;
	};
	ENET0_1588_TMR3_PTB5: enet0_1588_tmr3_ptb5 {
		nxp,kinetis-port-pins = < 5 5 >;
	};
	FTM2_FLT0_PTB5: ftm2_flt0_ptb5 {
		nxp,kinetis-port-pins = < 5 6 >;
	};
	HSADC1A_CH12_PTB6: hsadc1a_ch12_ptb6 {
		nxp,kinetis-port-pins = < 6 0 >;
	};
	PTB6: GPIOB_PTB6: gpiob_ptb6 {
		nxp,kinetis-port-pins = < 6 1 >;
	};
	CAN2_TX_PTB6: can2_tx_ptb6 {
		nxp,kinetis-port-pins = < 6 2 >;
	};
	FLEXPWM1_X2_PTB6: flexpwm1_x2_ptb6 {
		nxp,kinetis-port-pins = < 6 4 >;
	};
	HSADC1A_CH13_PTB7: hsadc1a_ch13_ptb7 {
		nxp,kinetis-port-pins = < 7 0 >;
	};
	PTB7: GPIOB_PTB7: gpiob_ptb7 {
		nxp,kinetis-port-pins = < 7 1 >;
	};
	CAN2_RX_PTB7: can2_rx_ptb7 {
		nxp,kinetis-port-pins = < 7 2 >;
	};
	FLEXPWM1_X3_PTB7: flexpwm1_x3_ptb7 {
		nxp,kinetis-port-pins = < 7 4 >;
	};
	PTB8: GPIOB_PTB8: gpiob_ptb8 {
		nxp,kinetis-port-pins = < 8 1 >;
	};
	UART3_RTS_b_PTB8: uart3_rts_b_ptb8 {
		nxp,kinetis-port-pins = < 8 3 >;
	};
	PTB9: GPIOB_PTB9: gpiob_ptb9 {
		nxp,kinetis-port-pins = < 9 1 >;
	};
	SPI1_PCS1_PTB9: spi1_pcs1_ptb9 {
		nxp,kinetis-port-pins = < 9 2 >;
	};
	UART3_CTS_b_PTB9: uart3_cts_b_ptb9 {
		nxp,kinetis-port-pins = < 9 3 >;
	};
	ENET0_1588_TMR2_PTB9: enet0_1588_tmr2_ptb9 {
		nxp,kinetis-port-pins = < 9 5 >;
	};
	HSADC0B_CH6_PTB10: hsadc0b_ch6_ptb10 {
		nxp,kinetis-port-pins = < 10 0 >;
	};
	PTB10: GPIOB_PTB10: gpiob_ptb10 {
		nxp,kinetis-port-pins = < 10 1 >;
	};
	SPI1_PCS0_PTB10: spi1_pcs0_ptb10 {
		nxp,kinetis-port-pins = < 10 2 >;
	};
	UART3_RX_PTB10: uart3_rx_ptb10 {
		nxp,kinetis-port-pins = < 10 3 >;
	};
	ENET0_1588_TMR3_PTB10: enet0_1588_tmr3_ptb10 {
		nxp,kinetis-port-pins = < 10 5 >;
	};
	FTM0_FLT1_PTB10: ftm0_flt1_ptb10 {
		nxp,kinetis-port-pins = < 10 6 >;
	};
	HSADC0B_CH7_PTB11: hsadc0b_ch7_ptb11 {
		nxp,kinetis-port-pins = < 11 0 >;
	};
	PTB11: GPIOB_PTB11: gpiob_ptb11 {
		nxp,kinetis-port-pins = < 11 1 >;
	};
	SPI1_SCK_PTB11: spi1_sck_ptb11 {
		nxp,kinetis-port-pins = < 11 2 >;
	};
	UART3_TX_PTB11: uart3_tx_ptb11 {
		nxp,kinetis-port-pins = < 11 3 >;
	};
	FTM0_FLT2_PTB11: ftm0_flt2_ptb11 {
		nxp,kinetis-port-pins = < 11 6 >;
	};
	PTB16: GPIOB_PTB16: gpiob_ptb16 {
		nxp,kinetis-port-pins = < 16 1 >;
	};
	SPI1_SOUT_PTB16: spi1_sout_ptb16 {
		nxp,kinetis-port-pins = < 16 2 >;
	};
	UART0_RX_PTB16: uart0_rx_ptb16 {
		nxp,kinetis-port-pins = < 16 3 >;
	};
	FTM_CLKIN2_PTB16: ftm_clkin2_ptb16 {
		nxp,kinetis-port-pins = < 16 4 >;
	};
	CAN0_TX_PTB16: can0_tx_ptb16 {
		nxp,kinetis-port-pins = < 16 5 >;
	};
	EWM_IN_PTB16: ewm_in_ptb16 {
		nxp,kinetis-port-pins = < 16 6 >;
	};
	XB_IN5_PTB16: xb_in5_ptb16 {
		nxp,kinetis-port-pins = < 16 7 >;
	};
	PTB17: GPIOB_PTB17: gpiob_ptb17 {
		nxp,kinetis-port-pins = < 17 1 >;
	};
	SPI1_SIN_PTB17: spi1_sin_ptb17 {
		nxp,kinetis-port-pins = < 17 2 >;
	};
	UART0_TX_PTB17: uart0_tx_ptb17 {
		nxp,kinetis-port-pins = < 17 3 >;
	};
	FTM_CLKIN1_PTB17: ftm_clkin1_ptb17 {
		nxp,kinetis-port-pins = < 17 4 >;
	};
	CAN0_RX_PTB17: can0_rx_ptb17 {
		nxp,kinetis-port-pins = < 17 5 >;
	};
	EWM_OUT_b_PTB17: ewm_out_b_ptb17 {
		nxp,kinetis-port-pins = < 17 6 >;
	};
	PTB18: GPIOB_PTB18: gpiob_ptb18 {
		nxp,kinetis-port-pins = < 18 1 >;
	};
	CAN0_TX_PTB18: can0_tx_ptb18 {
		nxp,kinetis-port-pins = < 18 2 >;
	};
	FTM2_CH0_PTB18: ftm2_ch0_ptb18 {
		nxp,kinetis-port-pins = < 18 3 >;
	};
	FTM3_CH2_PTB18: ftm3_ch2_ptb18 {
		nxp,kinetis-port-pins = < 18 4 >;
	};
	FLEXPWM1_A1_PTB18: flexpwm1_a1_ptb18 {
		nxp,kinetis-port-pins = < 18 5 >;
	};
	FTM2_QD_PHA_PTB18: ftm2_qd_pha_ptb18 {
		nxp,kinetis-port-pins = < 18 6 >;
	};
	PTB19: GPIOB_PTB19: gpiob_ptb19 {
		nxp,kinetis-port-pins = < 19 1 >;
	};
	CAN0_RX_PTB19: can0_rx_ptb19 {
		nxp,kinetis-port-pins = < 19 2 >;
	};
	FTM2_CH1_PTB19: ftm2_ch1_ptb19 {
		nxp,kinetis-port-pins = < 19 3 >;
	};
	FTM3_CH3_PTB19: ftm3_ch3_ptb19 {
		nxp,kinetis-port-pins = < 19 4 >;
	};
	FLEXPWM1_B1_PTB19: flexpwm1_b1_ptb19 {
		nxp,kinetis-port-pins = < 19 5 >;
	};
	FTM2_QD_PHB_PTB19: ftm2_qd_phb_ptb19 {
		nxp,kinetis-port-pins = < 19 6 >;
	};
	PTB20: GPIOB_PTB20: gpiob_ptb20 {
		nxp,kinetis-port-pins = < 20 1 >;
	};
	SPI2_PCS0_PTB20: spi2_pcs0_ptb20 {
		nxp,kinetis-port-pins = < 20 2 >;
	};
	FLEXPWM0_X0_PTB20: flexpwm0_x0_ptb20 {
		nxp,kinetis-port-pins = < 20 5 >;
	};
	CMP0_OUT_PTB20: cmp0_out_ptb20 {
		nxp,kinetis-port-pins = < 20 6 >;
	};
	PTB21: GPIOB_PTB21: gpiob_ptb21 {
		nxp,kinetis-port-pins = < 21 1 >;
	};
	SPI2_SCK_PTB21: spi2_sck_ptb21 {
		nxp,kinetis-port-pins = < 21 2 >;
	};
	FLEXPWM0_X1_PTB21: flexpwm0_x1_ptb21 {
		nxp,kinetis-port-pins = < 21 5 >;
	};
	CMP1_OUT_PTB21: cmp1_out_ptb21 {
		nxp,kinetis-port-pins = < 21 6 >;
	};
	PTB22: GPIOB_PTB22: gpiob_ptb22 {
		nxp,kinetis-port-pins = < 22 1 >;
	};
	SPI2_SOUT_PTB22: spi2_sout_ptb22 {
		nxp,kinetis-port-pins = < 22 2 >;
	};
	FLEXPWM0_X2_PTB22: flexpwm0_x2_ptb22 {
		nxp,kinetis-port-pins = < 22 5 >;
	};
	CMP2_OUT_PTB22: cmp2_out_ptb22 {
		nxp,kinetis-port-pins = < 22 6 >;
	};
	PTB23: GPIOB_PTB23: gpiob_ptb23 {
		nxp,kinetis-port-pins = < 23 1 >;
	};
	SPI2_SIN_PTB23: spi2_sin_ptb23 {
		nxp,kinetis-port-pins = < 23 2 >;
	};
	SPI0_PCS5_PTB23: spi0_pcs5_ptb23 {
		nxp,kinetis-port-pins = < 23 3 >;
	};
	FLEXPWM0_X3_PTB23: flexpwm0_x3_ptb23 {
		nxp,kinetis-port-pins = < 23 5 >;
	};
	CMP3_OUT_PTB23: cmp3_out_ptb23 {
		nxp,kinetis-port-pins = < 23 6 >;
	};
};

&portc {
	HSADC0B_CH8_PTC0: hsadc0b_ch8_ptc0 {
		nxp,kinetis-port-pins = < 0 0 >;
	};
	PTC0: GPIOC_PTC0: gpioc_ptc0 {
		nxp,kinetis-port-pins = < 0 1 >;
	};
	SPI0_PCS4_PTC0: spi0_pcs4_ptc0 {
		nxp,kinetis-port-pins = < 0 2 >;
	};
	PDB0_EXTRG_PTC0: pdb0_extrg_ptc0 {
		nxp,kinetis-port-pins = < 0 3 >;
	};
	FTM0_FLT1_PTC0: ftm0_flt1_ptc0 {
		nxp,kinetis-port-pins = < 0 6 >;
	};
	SPI0_PCS0_PTC0: spi0_pcs0_ptc0 {
		nxp,kinetis-port-pins = < 0 7 >;
	};
	HSADC0B_CH9_PTC1: hsadc0b_ch9_ptc1 {
		nxp,kinetis-port-pins = < 1 0 >;
	};
	PTC1: GPIOC_PTC1: LLWU_P6_PTC1: gpioc_ptc1 {
		nxp,kinetis-port-pins = < 1 1 >;
	};
	SPI0_PCS3_PTC1: spi0_pcs3_ptc1 {
		nxp,kinetis-port-pins = < 1 2 >;
	};
	UART1_RTS_b_PTC1: uart1_rts_b_ptc1 {
		nxp,kinetis-port-pins = < 1 3 >;
	};
	FTM0_CH0_PTC1: ftm0_ch0_ptc1 {
		nxp,kinetis-port-pins = < 1 4 >;
	};
	FLEXPWM0_A3_PTC1: flexpwm0_a3_ptc1 {
		nxp,kinetis-port-pins = < 1 5 >;
	};
	XB_IN11_PTC1: xb_in11_ptc1 {
		nxp,kinetis-port-pins = < 1 6 >;
	};
	HSADC1B_CH10_PTC2: CMP1_IN0_PTC2: hsadc1b_ch10_ptc2 {
		nxp,kinetis-port-pins = < 2 0 >;
	};
	PTC2: GPIOC_PTC2: gpioc_ptc2 {
		nxp,kinetis-port-pins = < 2 1 >;
	};
	SPI0_PCS2_PTC2: spi0_pcs2_ptc2 {
		nxp,kinetis-port-pins = < 2 2 >;
	};
	UART1_CTS_b_PTC2: uart1_cts_b_ptc2 {
		nxp,kinetis-port-pins = < 2 3 >;
	};
	FTM0_CH1_PTC2: ftm0_ch1_ptc2 {
		nxp,kinetis-port-pins = < 2 4 >;
	};
	FLEXPWM0_B3_PTC2: flexpwm0_b3_ptc2 {
		nxp,kinetis-port-pins = < 2 5 >;
	};
	XB_IN6_PTC2: xb_in6_ptc2 {
		nxp,kinetis-port-pins = < 2 6 >;
	};
	CMP1_IN1_PTC3: cmp1_in1_ptc3 {
		nxp,kinetis-port-pins = < 3 0 >;
	};
	PTC3: GPIOC_PTC3: LLWU_P7_PTC3: gpioc_ptc3 {
		nxp,kinetis-port-pins = < 3 1 >;
	};
	SPI0_PCS1_PTC3: spi0_pcs1_ptc3 {
		nxp,kinetis-port-pins = < 3 2 >;
	};
	UART1_RX_PTC3: uart1_rx_ptc3 {
		nxp,kinetis-port-pins = < 3 3 >;
	};
	FTM0_CH2_PTC3: ftm0_ch2_ptc3 {
		nxp,kinetis-port-pins = < 3 4 >;
	};
	CLKOUT_PTC3: clkout_ptc3 {
		nxp,kinetis-port-pins = < 3 5 >;
	};
	FTM3_FLT0_PTC3: ftm3_flt0_ptc3 {
		nxp,kinetis-port-pins = < 3 6 >;
	};
	PTC4: GPIOC_PTC4: LLWU_P8_PTC4: gpioc_ptc4 {
		nxp,kinetis-port-pins = < 4 1 >;
	};
	SPI0_PCS0_PTC4: spi0_pcs0_ptc4 {
		nxp,kinetis-port-pins = < 4 2 >;
	};
	UART1_TX_PTC4: uart1_tx_ptc4 {
		nxp,kinetis-port-pins = < 4 3 >;
	};
	FTM0_CH3_PTC4: ftm0_ch3_ptc4 {
		nxp,kinetis-port-pins = < 4 4 >;
	};
	CMP1_OUT_PTC4: cmp1_out_ptc4 {
		nxp,kinetis-port-pins = < 4 6 >;
	};
	PTC5: GPIOC_PTC5: LLWU_P9_PTC5: gpioc_ptc5 {
		nxp,kinetis-port-pins = < 5 1 >;
	};
	SPI0_SCK_PTC5: spi0_sck_ptc5 {
		nxp,kinetis-port-pins = < 5 2 >;
	};
	LPTMR0_ALT2_PTC5: lptmr0_alt2_ptc5 {
		nxp,kinetis-port-pins = < 5 3 >;
	};
	XB_IN2_PTC5: xb_in2_ptc5 {
		nxp,kinetis-port-pins = < 5 4 >;
	};
	CMP0_OUT_PTC5: cmp0_out_ptc5 {
		nxp,kinetis-port-pins = < 5 6 >;
	};
	FTM0_CH2_PTC5: ftm0_ch2_ptc5 {
		nxp,kinetis-port-pins = < 5 7 >;
	};
	CMP2_IN4_PTC6: CMP0_IN0_PTC6: cmp2_in4_ptc6 {
		nxp,kinetis-port-pins = < 6 0 >;
	};
	PTC6: GPIOC_PTC6: LLWU_P10_PTC6: gpioc_ptc6 {
		nxp,kinetis-port-pins = < 6 1 >;
	};
	SPI0_SOUT_PTC6: spi0_sout_ptc6 {
		nxp,kinetis-port-pins = < 6 2 >;
	};
	PDB0_EXTRG_PTC6: pdb0_extrg_ptc6 {
		nxp,kinetis-port-pins = < 6 3 >;
	};
	XB_IN3_PTC6: xb_in3_ptc6 {
		nxp,kinetis-port-pins = < 6 4 >;
	};
	UART0_RX_PTC6: uart0_rx_ptc6 {
		nxp,kinetis-port-pins = < 6 5 >;
	};
	XB_OUT6_PTC6: xb_out6_ptc6 {
		nxp,kinetis-port-pins = < 6 6 >;
	};
	I2C0_SCL_PTC6: i2c0_scl_ptc6 {
		nxp,kinetis-port-pins = < 6 7 >;
	};
	CMP3_IN4_PTC7: CMP0_IN1_PTC7: cmp3_in4_ptc7 {
		nxp,kinetis-port-pins = < 7 0 >;
	};
	PTC7: GPIOC_PTC7: gpioc_ptc7 {
		nxp,kinetis-port-pins = < 7 1 >;
	};
	SPI0_SIN_PTC7: spi0_sin_ptc7 {
		nxp,kinetis-port-pins = < 7 2 >;
	};
	XB_IN4_PTC7: xb_in4_ptc7 {
		nxp,kinetis-port-pins = < 7 4 >;
	};
	UART0_TX_PTC7: uart0_tx_ptc7 {
		nxp,kinetis-port-pins = < 7 5 >;
	};
	XB_OUT7_PTC7: xb_out7_ptc7 {
		nxp,kinetis-port-pins = < 7 6 >;
	};
	I2C0_SDA_PTC7: i2c0_sda_ptc7 {
		nxp,kinetis-port-pins = < 7 7 >;
	};
	HSADC1B_CH11_PTC8: CMP0_IN2_PTC8: hsadc1b_ch11_ptc8 {
		nxp,kinetis-port-pins = < 8 0 >;
	};
	PTC8: GPIOC_PTC8: gpioc_ptc8 {
		nxp,kinetis-port-pins = < 8 1 >;
	};
	FTM3_CH4_PTC8: ftm3_ch4_ptc8 {
		nxp,kinetis-port-pins = < 8 3 >;
	};
	FLEXPWM1_A2_PTC8: flexpwm1_a2_ptc8 {
		nxp,kinetis-port-pins = < 8 4 >;
	};
	HSADC1B_CH12_PTC9: CMP0_IN3_PTC9: hsadc1b_ch12_ptc9 {
		nxp,kinetis-port-pins = < 9 0 >;
	};
	PTC9: GPIOC_PTC9: gpioc_ptc9 {
		nxp,kinetis-port-pins = < 9 1 >;
	};
	FTM3_CH5_PTC9: ftm3_ch5_ptc9 {
		nxp,kinetis-port-pins = < 9 3 >;
	};
	FLEXPWM1_B2_PTC9: flexpwm1_b2_ptc9 {
		nxp,kinetis-port-pins = < 9 4 >;
	};
	HSADC1B_CH13_PTC10: hsadc1b_ch13_ptc10 {
		nxp,kinetis-port-pins = < 10 0 >;
	};
	PTC10: GPIOC_PTC10: gpioc_ptc10 {
		nxp,kinetis-port-pins = < 10 1 >;
	};
	I2C1_SCL_PTC10: i2c1_scl_ptc10 {
		nxp,kinetis-port-pins = < 10 2 >;
	};
	FTM3_CH6_PTC10: ftm3_ch6_ptc10 {
		nxp,kinetis-port-pins = < 10 3 >;
	};
	FLEXPWM1_A3_PTC10: flexpwm1_a3_ptc10 {
		nxp,kinetis-port-pins = < 10 4 >;
	};
	HSADC1B_CH14_PTC11: hsadc1b_ch14_ptc11 {
		nxp,kinetis-port-pins = < 11 0 >;
	};
	PTC11: GPIOC_PTC11: LLWU_P11_PTC11: gpioc_ptc11 {
		nxp,kinetis-port-pins = < 11 1 >;
	};
	I2C1_SDA_PTC11: i2c1_sda_ptc11 {
		nxp,kinetis-port-pins = < 11 2 >;
	};
	FTM3_CH7_PTC11: ftm3_ch7_ptc11 {
		nxp,kinetis-port-pins = < 11 3 >;
	};
	FLEXPWM1_B3_PTC11: flexpwm1_b3_ptc11 {
		nxp,kinetis-port-pins = < 11 4 >;
	};
	PTC12: GPIOC_PTC12: gpioc_ptc12 {
		nxp,kinetis-port-pins = < 12 1 >;
	};
	CAN2_TX_PTC12: can2_tx_ptc12 {
		nxp,kinetis-port-pins = < 12 2 >;
	};
	FTM_CLKIN0_PTC12: ftm_clkin0_ptc12 {
		nxp,kinetis-port-pins = < 12 4 >;
	};
	FLEXPWM1_A1_PTC12: flexpwm1_a1_ptc12 {
		nxp,kinetis-port-pins = < 12 5 >;
	};
	FTM3_FLT0_PTC12: ftm3_flt0_ptc12 {
		nxp,kinetis-port-pins = < 12 6 >;
	};
	SPI2_PCS1_PTC12: spi2_pcs1_ptc12 {
		nxp,kinetis-port-pins = < 12 7 >;
	};
	UART4_RTS_b_PTC12: uart4_rts_b_ptc12 {
		nxp,kinetis-port-pins = < 12 9 >;
	};
	PTC13: GPIOC_PTC13: gpioc_ptc13 {
		nxp,kinetis-port-pins = < 13 1 >;
	};
	CAN2_RX_PTC13: can2_rx_ptc13 {
		nxp,kinetis-port-pins = < 13 2 >;
	};
	FTM_CLKIN1_PTC13: ftm_clkin1_ptc13 {
		nxp,kinetis-port-pins = < 13 4 >;
	};
	FLEXPWM1_B1_PTC13: flexpwm1_b1_ptc13 {
		nxp,kinetis-port-pins = < 13 5 >;
	};
	UART4_CTS_b_PTC13: uart4_cts_b_ptc13 {
		nxp,kinetis-port-pins = < 13 9 >;
	};
	PTC14: GPIOC_PTC14: gpioc_ptc14 {
		nxp,kinetis-port-pins = < 14 1 >;
	};
	I2C1_SCL_PTC14: i2c1_scl_ptc14 {
		nxp,kinetis-port-pins = < 14 2 >;
	};
	I2C0_SCL_PTC14: i2c0_scl_ptc14 {
		nxp,kinetis-port-pins = < 14 3 >;
	};
	FLEXPWM1_A0_PTC14: flexpwm1_a0_ptc14 {
		nxp,kinetis-port-pins = < 14 5 >;
	};
	UART4_RX_PTC14: uart4_rx_ptc14 {
		nxp,kinetis-port-pins = < 14 9 >;
	};
	PTC15: GPIOC_PTC15: gpioc_ptc15 {
		nxp,kinetis-port-pins = < 15 1 >;
	};
	I2C1_SDA_PTC15: i2c1_sda_ptc15 {
		nxp,kinetis-port-pins = < 15 2 >;
	};
	I2C0_SDA_PTC15: i2c0_sda_ptc15 {
		nxp,kinetis-port-pins = < 15 3 >;
	};
	FLEXPWM1_B0_PTC15: flexpwm1_b0_ptc15 {
		nxp,kinetis-port-pins = < 15 5 >;
	};
	UART4_TX_PTC15: uart4_tx_ptc15 {
		nxp,kinetis-port-pins = < 15 9 >;
	};
	PTC16: GPIOC_PTC16: gpioc_ptc16 {
		nxp,kinetis-port-pins = < 16 1 >;
	};
	CAN1_RX_PTC16: can1_rx_ptc16 {
		nxp,kinetis-port-pins = < 16 2 >;
	};
	UART3_RX_PTC16: uart3_rx_ptc16 {
		nxp,kinetis-port-pins = < 16 3 >;
	};
	ENET0_1588_TMR0_PTC16: enet0_1588_tmr0_ptc16 {
		nxp,kinetis-port-pins = < 16 4 >;
	};
	FLEXPWM1_A2_PTC16: flexpwm1_a2_ptc16 {
		nxp,kinetis-port-pins = < 16 5 >;
	};
	PTC17: GPIOC_PTC17: gpioc_ptc17 {
		nxp,kinetis-port-pins = < 17 1 >;
	};
	CAN1_TX_PTC17: can1_tx_ptc17 {
		nxp,kinetis-port-pins = < 17 2 >;
	};
	UART3_TX_PTC17: uart3_tx_ptc17 {
		nxp,kinetis-port-pins = < 17 3 >;
	};
	ENET0_1588_TMR1_PTC17: enet0_1588_tmr1_ptc17 {
		nxp,kinetis-port-pins = < 17 4 >;
	};
	FLEXPWM1_B2_PTC17: flexpwm1_b2_ptc17 {
		nxp,kinetis-port-pins = < 17 5 >;
	};
	PTC18: GPIOC_PTC18: gpioc_ptc18 {
		nxp,kinetis-port-pins = < 18 1 >;
	};
	UART3_RTS_b_PTC18: uart3_rts_b_ptc18 {
		nxp,kinetis-port-pins = < 18 3 >;
	};
	ENET0_1588_TMR2_PTC18: enet0_1588_tmr2_ptc18 {
		nxp,kinetis-port-pins = < 18 4 >;
	};
	FLEXPWM1_A3_PTC18: flexpwm1_a3_ptc18 {
		nxp,kinetis-port-pins = < 18 5 >;
	};
	PTC19: GPIOC_PTC19: gpioc_ptc19 {
		nxp,kinetis-port-pins = < 19 1 >;
	};
	UART3_CTS_b_PTC19: uart3_cts_b_ptc19 {
		nxp,kinetis-port-pins = < 19 3 >;
	};
	ENET0_1588_TMR3_PTC19: enet0_1588_tmr3_ptc19 {
		nxp,kinetis-port-pins = < 19 4 >;
	};
	FLEXPWM1_B3_PTC19: flexpwm1_b3_ptc19 {
		nxp,kinetis-port-pins = < 19 5 >;
	};
};

&portd {
	PTD0: GPIOD_PTD0: LLWU_P12_PTD0: gpiod_ptd0 {
		nxp,kinetis-port-pins = < 0 1 >;
	};
	SPI0_PCS0_PTD0: spi0_pcs0_ptd0 {
		nxp,kinetis-port-pins = < 0 2 >;
	};
	UART2_RTS_b_PTD0: uart2_rts_b_ptd0 {
		nxp,kinetis-port-pins = < 0 3 >;
	};
	FTM3_CH0_PTD0: ftm3_ch0_ptd0 {
		nxp,kinetis-port-pins = < 0 4 >;
	};
	FTM0_CH0_PTD0: ftm0_ch0_ptd0 {
		nxp,kinetis-port-pins = < 0 5 >;
	};
	FLEXPWM0_A0_PTD0: flexpwm0_a0_ptd0 {
		nxp,kinetis-port-pins = < 0 6 >;
	};
	FLEXPWM1_A0_PTD0: flexpwm1_a0_ptd0 {
		nxp,kinetis-port-pins = < 0 9 >;
	};
	HSADC1A_CH11_PTD1: hsadc1a_ch11_ptd1 {
		nxp,kinetis-port-pins = < 1 0 >;
	};
	PTD1: GPIOD_PTD1: gpiod_ptd1 {
		nxp,kinetis-port-pins = < 1 1 >;
	};
	SPI0_SCK_PTD1: spi0_sck_ptd1 {
		nxp,kinetis-port-pins = < 1 2 >;
	};
	UART2_CTS_b_PTD1: uart2_cts_b_ptd1 {
		nxp,kinetis-port-pins = < 1 3 >;
	};
	FTM3_CH1_PTD1: ftm3_ch1_ptd1 {
		nxp,kinetis-port-pins = < 1 4 >;
	};
	FTM0_CH1_PTD1: ftm0_ch1_ptd1 {
		nxp,kinetis-port-pins = < 1 5 >;
	};
	FLEXPWM0_B0_PTD1: flexpwm0_b0_ptd1 {
		nxp,kinetis-port-pins = < 1 6 >;
	};
	FLEXPWM1_B0_PTD1: flexpwm1_b0_ptd1 {
		nxp,kinetis-port-pins = < 1 9 >;
	};
	PTD2: GPIOD_PTD2: LLWU_P13_PTD2: gpiod_ptd2 {
		nxp,kinetis-port-pins = < 2 1 >;
	};
	SPI0_SOUT_PTD2: spi0_sout_ptd2 {
		nxp,kinetis-port-pins = < 2 2 >;
	};
	UART2_RX_PTD2: uart2_rx_ptd2 {
		nxp,kinetis-port-pins = < 2 3 >;
	};
	FTM3_CH2_PTD2: ftm3_ch2_ptd2 {
		nxp,kinetis-port-pins = < 2 4 >;
	};
	FTM0_CH2_PTD2: ftm0_ch2_ptd2 {
		nxp,kinetis-port-pins = < 2 5 >;
	};
	FLEXPWM0_A1_PTD2: flexpwm0_a1_ptd2 {
		nxp,kinetis-port-pins = < 2 6 >;
	};
	I2C0_SCL_PTD2: i2c0_scl_ptd2 {
		nxp,kinetis-port-pins = < 2 7 >;
	};
	FLEXPWM1_A1_PTD2: flexpwm1_a1_ptd2 {
		nxp,kinetis-port-pins = < 2 9 >;
	};
	PTD3: GPIOD_PTD3: gpiod_ptd3 {
		nxp,kinetis-port-pins = < 3 1 >;
	};
	SPI0_SIN_PTD3: spi0_sin_ptd3 {
		nxp,kinetis-port-pins = < 3 2 >;
	};
	UART2_TX_PTD3: uart2_tx_ptd3 {
		nxp,kinetis-port-pins = < 3 3 >;
	};
	FTM3_CH3_PTD3: ftm3_ch3_ptd3 {
		nxp,kinetis-port-pins = < 3 4 >;
	};
	FTM0_CH3_PTD3: ftm0_ch3_ptd3 {
		nxp,kinetis-port-pins = < 3 5 >;
	};
	FLEXPWM0_B1_PTD3: flexpwm0_b1_ptd3 {
		nxp,kinetis-port-pins = < 3 6 >;
	};
	I2C0_SDA_PTD3: i2c0_sda_ptd3 {
		nxp,kinetis-port-pins = < 3 7 >;
	};
	FLEXPWM1_B1_PTD3: flexpwm1_b1_ptd3 {
		nxp,kinetis-port-pins = < 3 9 >;
	};
	PTD4: GPIOD_PTD4: LLWU_P14_PTD4: gpiod_ptd4 {
		nxp,kinetis-port-pins = < 4 1 >;
	};
	SPI0_PCS1_PTD4: spi0_pcs1_ptd4 {
		nxp,kinetis-port-pins = < 4 2 >;
	};
	UART0_RTS_b_PTD4: uart0_rts_b_ptd4 {
		nxp,kinetis-port-pins = < 4 3 >;
	};
	FTM0_CH4_PTD4: ftm0_ch4_ptd4 {
		nxp,kinetis-port-pins = < 4 4 >;
	};
	FLEXPWM0_A2_PTD4: flexpwm0_a2_ptd4 {
		nxp,kinetis-port-pins = < 4 5 >;
	};
	EWM_IN_PTD4: ewm_in_ptd4 {
		nxp,kinetis-port-pins = < 4 6 >;
	};
	SPI1_PCS0_PTD4: spi1_pcs0_ptd4 {
		nxp,kinetis-port-pins = < 4 7 >;
	};
	HSADC1A_CH8_PTD5: hsadc1a_ch8_ptd5 {
		nxp,kinetis-port-pins = < 5 0 >;
	};
	PTD5: GPIOD_PTD5: gpiod_ptd5 {
		nxp,kinetis-port-pins = < 5 1 >;
	};
	SPI0_PCS2_PTD5: spi0_pcs2_ptd5 {
		nxp,kinetis-port-pins = < 5 2 >;
	};
	UART0_CTS_b_PTD5: UART0_COL_b_PTD5: uart0_cts_b_ptd5 {
		nxp,kinetis-port-pins = < 5 3 >;
	};
	FTM0_CH5_PTD5: ftm0_ch5_ptd5 {
		nxp,kinetis-port-pins = < 5 4 >;
	};
	FLEXPWM0_B2_PTD5: flexpwm0_b2_ptd5 {
		nxp,kinetis-port-pins = < 5 5 >;
	};
	EWM_OUT_b_PTD5: ewm_out_b_ptd5 {
		nxp,kinetis-port-pins = < 5 6 >;
	};
	SPI1_SCK_PTD5: spi1_sck_ptd5 {
		nxp,kinetis-port-pins = < 5 7 >;
	};
	HSADC1A_CH9_PTD6: hsadc1a_ch9_ptd6 {
		nxp,kinetis-port-pins = < 6 0 >;
	};
	PTD6: GPIOD_PTD6: LLWU_P15_PTD6: gpiod_ptd6 {
		nxp,kinetis-port-pins = < 6 1 >;
	};
	SPI0_PCS3_PTD6: spi0_pcs3_ptd6 {
		nxp,kinetis-port-pins = < 6 2 >;
	};
	UART0_RX_PTD6: uart0_rx_ptd6 {
		nxp,kinetis-port-pins = < 6 3 >;
	};
	FTM0_CH6_PTD6: ftm0_ch6_ptd6 {
		nxp,kinetis-port-pins = < 6 4 >;
	};
	FTM1_CH0_PTD6: ftm1_ch0_ptd6 {
		nxp,kinetis-port-pins = < 6 5 >;
	};
	FTM0_FLT0_PTD6: ftm0_flt0_ptd6 {
		nxp,kinetis-port-pins = < 6 6 >;
	};
	SPI1_SOUT_PTD6: spi1_sout_ptd6 {
		nxp,kinetis-port-pins = < 6 7 >;
	};
	PTD7: GPIOD_PTD7: gpiod_ptd7 {
		nxp,kinetis-port-pins = < 7 1 >;
	};
	UART0_TX_PTD7: uart0_tx_ptd7 {
		nxp,kinetis-port-pins = < 7 3 >;
	};
	FTM0_CH7_PTD7: ftm0_ch7_ptd7 {
		nxp,kinetis-port-pins = < 7 4 >;
	};
	FTM1_CH1_PTD7: ftm1_ch1_ptd7 {
		nxp,kinetis-port-pins = < 7 5 >;
	};
	FTM0_FLT1_PTD7: ftm0_flt1_ptd7 {
		nxp,kinetis-port-pins = < 7 6 >;
	};
	SPI1_SIN_PTD7: spi1_sin_ptd7 {
		nxp,kinetis-port-pins = < 7 7 >;
	};
	PTD8: GPIOD_PTD8: LLWU_P24_PTD8: gpiod_ptd8 {
		nxp,kinetis-port-pins = < 8 1 >;
	};
	I2C1_SCL_PTD8: i2c1_scl_ptd8 {
		nxp,kinetis-port-pins = < 8 2 >;
	};
	UART5_RX_PTD8: uart5_rx_ptd8 {
		nxp,kinetis-port-pins = < 8 3 >;
	};
	FLEXPWM0_A3_PTD8: flexpwm0_a3_ptd8 {
		nxp,kinetis-port-pins = < 8 6 >;
	};
	PTD9: GPIOD_PTD9: gpiod_ptd9 {
		nxp,kinetis-port-pins = < 9 1 >;
	};
	I2C1_SDA_PTD9: i2c1_sda_ptd9 {
		nxp,kinetis-port-pins = < 9 2 >;
	};
	UART5_TX_PTD9: uart5_tx_ptd9 {
		nxp,kinetis-port-pins = < 9 3 >;
	};
	FLEXPWM0_B3_PTD9: flexpwm0_b3_ptd9 {
		nxp,kinetis-port-pins = < 9 6 >;
	};
	PTD10: GPIOD_PTD10: gpiod_ptd10 {
		nxp,kinetis-port-pins = < 10 1 >;
	};
	UART5_RTS_b_PTD10: uart5_rts_b_ptd10 {
		nxp,kinetis-port-pins = < 10 3 >;
	};
	FLEXPWM0_A2_PTD10: flexpwm0_a2_ptd10 {
		nxp,kinetis-port-pins = < 10 6 >;
	};
	PTD11: GPIOD_PTD11: LLWU_P25_PTD11: gpiod_ptd11 {
		nxp,kinetis-port-pins = < 11 1 >;
	};
	SPI2_PCS0_PTD11: spi2_pcs0_ptd11 {
		nxp,kinetis-port-pins = < 11 2 >;
	};
	UART5_CTS_b_PTD11: uart5_cts_b_ptd11 {
		nxp,kinetis-port-pins = < 11 3 >;
	};
	FLEXPWM0_B2_PTD11: flexpwm0_b2_ptd11 {
		nxp,kinetis-port-pins = < 11 6 >;
	};
	PTD12: GPIOD_PTD12: gpiod_ptd12 {
		nxp,kinetis-port-pins = < 12 1 >;
	};
	SPI2_SCK_PTD12: spi2_sck_ptd12 {
		nxp,kinetis-port-pins = < 12 2 >;
	};
	FTM3_FLT0_PTD12: ftm3_flt0_ptd12 {
		nxp,kinetis-port-pins = < 12 3 >;
	};
	XB_IN5_PTD12: xb_in5_ptd12 {
		nxp,kinetis-port-pins = < 12 4 >;
	};
	XB_OUT5_PTD12: xb_out5_ptd12 {
		nxp,kinetis-port-pins = < 12 5 >;
	};
	FLEXPWM0_A1_PTD12: flexpwm0_a1_ptd12 {
		nxp,kinetis-port-pins = < 12 6 >;
	};
	PTD13: GPIOD_PTD13: gpiod_ptd13 {
		nxp,kinetis-port-pins = < 13 1 >;
	};
	SPI2_SOUT_PTD13: spi2_sout_ptd13 {
		nxp,kinetis-port-pins = < 13 2 >;
	};
	XB_IN7_PTD13: xb_in7_ptd13 {
		nxp,kinetis-port-pins = < 13 4 >;
	};
	XB_OUT7_PTD13: xb_out7_ptd13 {
		nxp,kinetis-port-pins = < 13 5 >;
	};
	FLEXPWM0_B1_PTD13: flexpwm0_b1_ptd13 {
		nxp,kinetis-port-pins = < 13 6 >;
	};
	PTD14: GPIOD_PTD14: gpiod_ptd14 {
		nxp,kinetis-port-pins = < 14 1 >;
	};
	SPI2_SIN_PTD14: spi2_sin_ptd14 {
		nxp,kinetis-port-pins = < 14 2 >;
	};
	XB_IN11_PTD14: xb_in11_ptd14 {
		nxp,kinetis-port-pins = < 14 4 >;
	};
	XB_OUT11_PTD14: xb_out11_ptd14 {
		nxp,kinetis-port-pins = < 14 5 >;
	};
	FLEXPWM0_A0_PTD14: flexpwm0_a0_ptd14 {
		nxp,kinetis-port-pins = < 14 6 >;
	};
	PTD15: GPIOD_PTD15: gpiod_ptd15 {
		nxp,kinetis-port-pins = < 15 1 >;
	};
	SPI2_PCS1_PTD15: spi2_pcs1_ptd15 {
		nxp,kinetis-port-pins = < 15 2 >;
	};
	FLEXPWM0_B0_PTD15: flexpwm0_b0_ptd15 {
		nxp,kinetis-port-pins = < 15 6 >;
	};
};

&porte {
	HSADC0B_CH16_PTE0: HSADC1A_CH0_PTE0: hsadc0b_ch16_pte0 {
		nxp,kinetis-port-pins = < 0 0 >;
	};
	PTE0: GPIOE_PTE0: gpioe_pte0 {
		nxp,kinetis-port-pins = < 0 1 >;
	};
	SPI1_PCS1_PTE0: spi1_pcs1_pte0 {
		nxp,kinetis-port-pins = < 0 2 >;
	};
	UART1_TX_PTE0: uart1_tx_pte0 {
		nxp,kinetis-port-pins = < 0 3 >;
	};
	XB_OUT10_PTE0: xb_out10_pte0 {
		nxp,kinetis-port-pins = < 0 4 >;
	};
	XB_IN11_PTE0: xb_in11_pte0 {
		nxp,kinetis-port-pins = < 0 5 >;
	};
	I2C1_SDA_PTE0: i2c1_sda_pte0 {
		nxp,kinetis-port-pins = < 0 6 >;
	};
	TRACE_CLKOUT_PTE0: trace_clkout_pte0 {
		nxp,kinetis-port-pins = < 0 8 >;
	};
	HSADC0B_CH17_PTE1: HSADC1A_CH1_PTE1: hsadc0b_ch17_pte1 {
		nxp,kinetis-port-pins = < 1 0 >;
	};
	PTE1: GPIOE_PTE1: LLWU_P0_PTE1: gpioe_pte1 {
		nxp,kinetis-port-pins = < 1 1 >;
	};
	SPI1_SOUT_PTE1: spi1_sout_pte1 {
		nxp,kinetis-port-pins = < 1 2 >;
	};
	UART1_RX_PTE1: uart1_rx_pte1 {
		nxp,kinetis-port-pins = < 1 3 >;
	};
	XB_OUT11_PTE1: xb_out11_pte1 {
		nxp,kinetis-port-pins = < 1 4 >;
	};
	XB_IN7_PTE1: xb_in7_pte1 {
		nxp,kinetis-port-pins = < 1 5 >;
	};
	I2C1_SCL_PTE1: i2c1_scl_pte1 {
		nxp,kinetis-port-pins = < 1 6 >;
	};
	TRACE_D3_PTE1: trace_d3_pte1 {
		nxp,kinetis-port-pins = < 1 8 >;
	};
	HSADC0B_CH10_PTE2: HSADC1B_CH0_PTE2: hsadc0b_ch10_pte2 {
		nxp,kinetis-port-pins = < 2 0 >;
	};
	PTE2: GPIOE_PTE2: LLWU_P1_PTE2: gpioe_pte2 {
		nxp,kinetis-port-pins = < 2 1 >;
	};
	SPI1_SCK_PTE2: spi1_sck_pte2 {
		nxp,kinetis-port-pins = < 2 2 >;
	};
	UART1_CTS_b_PTE2: uart1_cts_b_pte2 {
		nxp,kinetis-port-pins = < 2 3 >;
	};
	TRACE_D2_PTE2: trace_d2_pte2 {
		nxp,kinetis-port-pins = < 2 8 >;
	};
	HSADC0B_CH11_PTE3: HSADC1B_CH1_PTE3: hsadc0b_ch11_pte3 {
		nxp,kinetis-port-pins = < 3 0 >;
	};
	PTE3: GPIOE_PTE3: gpioe_pte3 {
		nxp,kinetis-port-pins = < 3 1 >;
	};
	SPI1_SIN_PTE3: spi1_sin_pte3 {
		nxp,kinetis-port-pins = < 3 2 >;
	};
	UART1_RTS_b_PTE3: uart1_rts_b_pte3 {
		nxp,kinetis-port-pins = < 3 3 >;
	};
	TRACE_D1_PTE3: trace_d1_pte3 {
		nxp,kinetis-port-pins = < 3 8 >;
	};
	HSADC1A_CH4_PTE4: ADC0_SE2_PTE4: ADC0_DP2_PTE4: hsadc1a_ch4_pte4 {
		nxp,kinetis-port-pins = < 4 0 >;
	};
	PTE4: GPIOE_PTE4: LLWU_P2_PTE4: gpioe_pte4 {
		nxp,kinetis-port-pins = < 4 1 >;
	};
	SPI1_PCS0_PTE4: spi1_pcs0_pte4 {
		nxp,kinetis-port-pins = < 4 2 >;
	};
	UART3_TX_PTE4: uart3_tx_pte4 {
		nxp,kinetis-port-pins = < 4 3 >;
	};
	TRACE_D0_PTE4: trace_d0_pte4 {
		nxp,kinetis-port-pins = < 4 8 >;
	};
	HSADC1A_CH5_PTE5: ADC0_SE10_PTE5: ADC0_DM2_PTE5: hsadc1a_ch5_pte5 {
		nxp,kinetis-port-pins = < 5 0 >;
	};
	PTE5: GPIOE_PTE5: gpioe_pte5 {
		nxp,kinetis-port-pins = < 5 1 >;
	};
	SPI1_PCS2_PTE5: spi1_pcs2_pte5 {
		nxp,kinetis-port-pins = < 5 2 >;
	};
	UART3_RX_PTE5: uart3_rx_pte5 {
		nxp,kinetis-port-pins = < 5 3 >;
	};
	FLEXPWM1_A0_PTE5: flexpwm1_a0_pte5 {
		nxp,kinetis-port-pins = < 5 5 >;
	};
	FTM3_CH0_PTE5: ftm3_ch0_pte5 {
		nxp,kinetis-port-pins = < 5 6 >;
	};
	HSADC1B_CH7_PTE6: ADC0_SE4a_PTE6: hsadc1b_ch7_pte6 {
		nxp,kinetis-port-pins = < 6 0 >;
	};
	PTE6: GPIOE_PTE6: LLWU_P16_PTE6: gpioe_pte6 {
		nxp,kinetis-port-pins = < 6 1 >;
	};
	SPI1_PCS3_PTE6: spi1_pcs3_pte6 {
		nxp,kinetis-port-pins = < 6 2 >;
	};
	UART3_CTS_b_PTE6: uart3_cts_b_pte6 {
		nxp,kinetis-port-pins = < 6 3 >;
	};
	FLEXPWM1_B0_PTE6: flexpwm1_b0_pte6 {
		nxp,kinetis-port-pins = < 6 5 >;
	};
	FTM3_CH1_PTE6: ftm3_ch1_pte6 {
		nxp,kinetis-port-pins = < 6 6 >;
	};
	PTE7: GPIOE_PTE7: gpioe_pte7 {
		nxp,kinetis-port-pins = < 7 1 >;
	};
	UART3_RTS_b_PTE7: uart3_rts_b_pte7 {
		nxp,kinetis-port-pins = < 7 3 >;
	};
	FLEXPWM1_A1_PTE7: flexpwm1_a1_pte7 {
		nxp,kinetis-port-pins = < 7 5 >;
	};
	FTM3_CH2_PTE7: ftm3_ch2_pte7 {
		nxp,kinetis-port-pins = < 7 6 >;
	};
	PTE8: GPIOE_PTE8: gpioe_pte8 {
		nxp,kinetis-port-pins = < 8 1 >;
	};
	UART5_TX_PTE8: uart5_tx_pte8 {
		nxp,kinetis-port-pins = < 8 3 >;
	};
	FLEXPWM1_B1_PTE8: flexpwm1_b1_pte8 {
		nxp,kinetis-port-pins = < 8 5 >;
	};
	FTM3_CH3_PTE8: ftm3_ch3_pte8 {
		nxp,kinetis-port-pins = < 8 6 >;
	};
	PTE9: GPIOE_PTE9: LLWU_P17_PTE9: gpioe_pte9 {
		nxp,kinetis-port-pins = < 9 1 >;
	};
	UART5_RX_PTE9: uart5_rx_pte9 {
		nxp,kinetis-port-pins = < 9 3 >;
	};
	FLEXPWM1_A2_PTE9: flexpwm1_a2_pte9 {
		nxp,kinetis-port-pins = < 9 5 >;
	};
	FTM3_CH4_PTE9: ftm3_ch4_pte9 {
		nxp,kinetis-port-pins = < 9 6 >;
	};
	PTE10: GPIOE_PTE10: LLWU_P18_PTE10: gpioe_pte10 {
		nxp,kinetis-port-pins = < 10 1 >;
	};
	UART5_CTS_b_PTE10: uart5_cts_b_pte10 {
		nxp,kinetis-port-pins = < 10 3 >;
	};
	FLEXPWM1_B2_PTE10: flexpwm1_b2_pte10 {
		nxp,kinetis-port-pins = < 10 5 >;
	};
	FTM3_CH5_PTE10: ftm3_ch5_pte10 {
		nxp,kinetis-port-pins = < 10 6 >;
	};
	HSADC1A_CH6_PTE11: ADC0_SE3_PTE11: ADC0_DP3_PTE11: hsadc1a_ch6_pte11 {
		nxp,kinetis-port-pins = < 11 0 >;
	};
	PTE11: GPIOE_PTE11: gpioe_pte11 {
		nxp,kinetis-port-pins = < 11 1 >;
	};
	UART5_RTS_b_PTE11: uart5_rts_b_pte11 {
		nxp,kinetis-port-pins = < 11 3 >;
	};
	FLEXPWM1_A3_PTE11: flexpwm1_a3_pte11 {
		nxp,kinetis-port-pins = < 11 5 >;
	};
	FTM3_CH6_PTE11: ftm3_ch6_pte11 {
		nxp,kinetis-port-pins = < 11 6 >;
	};
	HSADC1B_CH6_PTE12: ADC0_SE11_PTE12: ADC0_DM3_PTE12: hsadc1b_ch6_pte12 {
		nxp,kinetis-port-pins = < 12 0 >;
	};
	PTE12: GPIOE_PTE12: gpioe_pte12 {
		nxp,kinetis-port-pins = < 12 1 >;
	};
	FLEXPWM1_B3_PTE12: flexpwm1_b3_pte12 {
		nxp,kinetis-port-pins = < 12 5 >;
	};
	FTM3_CH7_PTE12: ftm3_ch7_pte12 {
		nxp,kinetis-port-pins = < 12 6 >;
	};
	PTE13: GPIOE_PTE13: gpioe_pte13 {
		nxp,kinetis-port-pins = < 13 1 >;
	};
	HSADC0A_CH0_PTE16: ADC0_SE1_PTE16: ADC0_DP1_PTE16: hsadc0a_ch0_pte16 {
		nxp,kinetis-port-pins = < 16 0 >;
	};
	PTE16: GPIOE_PTE16: gpioe_pte16 {
		nxp,kinetis-port-pins = < 16 1 >;
	};
	SPI0_PCS0_PTE16: spi0_pcs0_pte16 {
		nxp,kinetis-port-pins = < 16 2 >;
	};
	UART2_TX_PTE16: uart2_tx_pte16 {
		nxp,kinetis-port-pins = < 16 3 >;
	};
	FTM_CLKIN0_PTE16: ftm_clkin0_pte16 {
		nxp,kinetis-port-pins = < 16 4 >;
	};
	FTM0_FLT3_PTE16: ftm0_flt3_pte16 {
		nxp,kinetis-port-pins = < 16 6 >;
	};
	HSADC0A_CH1_PTE17: ADC0_SE9_PTE17: ADC0_DM1_PTE17: hsadc0a_ch1_pte17 {
		nxp,kinetis-port-pins = < 17 0 >;
	};
	PTE17: GPIOE_PTE17: LLWU_P19_PTE17: gpioe_pte17 {
		nxp,kinetis-port-pins = < 17 1 >;
	};
	SPI0_SCK_PTE17: spi0_sck_pte17 {
		nxp,kinetis-port-pins = < 17 2 >;
	};
	UART2_RX_PTE17: uart2_rx_pte17 {
		nxp,kinetis-port-pins = < 17 3 >;
	};
	FTM_CLKIN1_PTE17: ftm_clkin1_pte17 {
		nxp,kinetis-port-pins = < 17 4 >;
	};
	LPTMR0_ALT3_PTE17: lptmr0_alt3_pte17 {
		nxp,kinetis-port-pins = < 17 6 >;
	};
	HSADC0B_CH0_PTE18: ADC0_SE5a_PTE18: hsadc0b_ch0_pte18 {
		nxp,kinetis-port-pins = < 18 0 >;
	};
	PTE18: GPIOE_PTE18: LLWU_P20_PTE18: gpioe_pte18 {
		nxp,kinetis-port-pins = < 18 1 >;
	};
	SPI0_SOUT_PTE18: spi0_sout_pte18 {
		nxp,kinetis-port-pins = < 18 2 >;
	};
	UART2_CTS_b_PTE18: uart2_cts_b_pte18 {
		nxp,kinetis-port-pins = < 18 3 >;
	};
	I2C0_SDA_PTE18: i2c0_sda_pte18 {
		nxp,kinetis-port-pins = < 18 4 >;
	};
	HSADC0B_CH1_PTE19: ADC0_SE6a_PTE19: hsadc0b_ch1_pte19 {
		nxp,kinetis-port-pins = < 19 0 >;
	};
	PTE19: GPIOE_PTE19: gpioe_pte19 {
		nxp,kinetis-port-pins = < 19 1 >;
	};
	SPI0_SIN_PTE19: spi0_sin_pte19 {
		nxp,kinetis-port-pins = < 19 2 >;
	};
	UART2_RTS_b_PTE19: uart2_rts_b_pte19 {
		nxp,kinetis-port-pins = < 19 3 >;
	};
	I2C0_SCL_PTE19: i2c0_scl_pte19 {
		nxp,kinetis-port-pins = < 19 4 >;
	};
	CMP3_OUT_PTE19: cmp3_out_pte19 {
		nxp,kinetis-port-pins = < 19 6 >;
	};
	HSADC0A_CH8_PTE20: ADC0_SE5b_PTE20: hsadc0a_ch8_pte20 {
		nxp,kinetis-port-pins = < 20 0 >;
	};
	PTE20: GPIOE_PTE20: gpioe_pte20 {
		nxp,kinetis-port-pins = < 20 1 >;
	};
	FTM1_CH0_PTE20: ftm1_ch0_pte20 {
		nxp,kinetis-port-pins = < 20 3 >;
	};
	UART0_TX_PTE20: uart0_tx_pte20 {
		nxp,kinetis-port-pins = < 20 4 >;
	};
	FTM1_QD_PHA_PTE20: ftm1_qd_pha_pte20 {
		nxp,kinetis-port-pins = < 20 5 >;
	};
	HSADC0A_CH9_PTE21: HSADC1A_CH7_PTE21: hsadc0a_ch9_pte21 {
		nxp,kinetis-port-pins = < 21 0 >;
	};
	PTE21: GPIOE_PTE21: gpioe_pte21 {
		nxp,kinetis-port-pins = < 21 1 >;
	};
	XB_IN9_PTE21: xb_in9_pte21 {
		nxp,kinetis-port-pins = < 21 2 >;
	};
	FTM1_CH1_PTE21: ftm1_ch1_pte21 {
		nxp,kinetis-port-pins = < 21 3 >;
	};
	UART0_RX_PTE21: uart0_rx_pte21 {
		nxp,kinetis-port-pins = < 21 4 >;
	};
	FTM1_QD_PHB_PTE21: ftm1_qd_phb_pte21 {
		nxp,kinetis-port-pins = < 21 5 >;
	};
	PTE22: GPIOE_PTE22: gpioe_pte22 {
		nxp,kinetis-port-pins = < 22 1 >;
	};
	FTM2_CH0_PTE22: ftm2_ch0_pte22 {
		nxp,kinetis-port-pins = < 22 3 >;
	};
	XB_IN2_PTE22: xb_in2_pte22 {
		nxp,kinetis-port-pins = < 22 4 >;
	};
	FTM2_QD_PHA_PTE22: ftm2_qd_pha_pte22 {
		nxp,kinetis-port-pins = < 22 5 >;
	};
	PTE23: GPIOE_PTE23: gpioe_pte23 {
		nxp,kinetis-port-pins = < 23 1 >;
	};
	FTM2_CH1_PTE23: ftm2_ch1_pte23 {
		nxp,kinetis-port-pins = < 23 3 >;
	};
	XB_IN3_PTE23: xb_in3_pte23 {
		nxp,kinetis-port-pins = < 23 4 >;
	};
	FTM2_QD_PHB_PTE23: ftm2_qd_phb_pte23 {
		nxp,kinetis-port-pins = < 23 5 >;
	};
	HSADC0B_CH4_PTE24: HSADC1B_CH4_PTE24: hsadc0b_ch4_pte24 {
		nxp,kinetis-port-pins = < 24 0 >;
	};
	PTE24: GPIOE_PTE24: gpioe_pte24 {
		nxp,kinetis-port-pins = < 24 1 >;
	};
	CAN1_TX_PTE24: can1_tx_pte24 {
		nxp,kinetis-port-pins = < 24 2 >;
	};
	FTM0_CH0_PTE24: ftm0_ch0_pte24 {
		nxp,kinetis-port-pins = < 24 3 >;
	};
	XB_IN2_PTE24: xb_in2_pte24 {
		nxp,kinetis-port-pins = < 24 4 >;
	};
	I2C0_SCL_PTE24: i2c0_scl_pte24 {
		nxp,kinetis-port-pins = < 24 5 >;
	};
	EWM_OUT_b_PTE24: ewm_out_b_pte24 {
		nxp,kinetis-port-pins = < 24 6 >;
	};
	XB_OUT4_PTE24: xb_out4_pte24 {
		nxp,kinetis-port-pins = < 24 7 >;
	};
	UART4_TX_PTE24: uart4_tx_pte24 {
		nxp,kinetis-port-pins = < 24 8 >;
	};
	HSADC0B_CH5_PTE25: HSADC1B_CH5_PTE25: hsadc0b_ch5_pte25 {
		nxp,kinetis-port-pins = < 25 0 >;
	};
	PTE25: GPIOE_PTE25: LLWU_P21_PTE25: gpioe_pte25 {
		nxp,kinetis-port-pins = < 25 1 >;
	};
	CAN1_RX_PTE25: can1_rx_pte25 {
		nxp,kinetis-port-pins = < 25 2 >;
	};
	FTM0_CH1_PTE25: ftm0_ch1_pte25 {
		nxp,kinetis-port-pins = < 25 3 >;
	};
	XB_IN3_PTE25: xb_in3_pte25 {
		nxp,kinetis-port-pins = < 25 4 >;
	};
	I2C0_SDA_PTE25: i2c0_sda_pte25 {
		nxp,kinetis-port-pins = < 25 5 >;
	};
	XB_OUT5_PTE25: xb_out5_pte25 {
		nxp,kinetis-port-pins = < 25 7 >;
	};
	UART4_RX_PTE25: uart4_rx_pte25 {
		nxp,kinetis-port-pins = < 25 8 >;
	};
	PTE26: GPIOE_PTE26: gpioe_pte26 {
		nxp,kinetis-port-pins = < 26 1 >;
	};
	ENET_1588_CLKIN_PTE26: enet_1588_clkin_pte26 {
		nxp,kinetis-port-pins = < 26 2 >;
	};
	FTM0_CH4_PTE26: ftm0_ch4_pte26 {
		nxp,kinetis-port-pins = < 26 3 >;
	};
	UART4_CTS_b_PTE26: uart4_cts_b_pte26 {
		nxp,kinetis-port-pins = < 26 8 >;
	};
	PTE27: GPIOE_PTE27: gpioe_pte27 {
		nxp,kinetis-port-pins = < 27 1 >;
	};
	CAN2_TX_PTE27: can2_tx_pte27 {
		nxp,kinetis-port-pins = < 27 2 >;
	};
	UART4_RTS_b_PTE27: uart4_rts_b_pte27 {
		nxp,kinetis-port-pins = < 27 8 >;
	};
	PTE28: GPIOE_PTE28: gpioe_pte28 {
		nxp,kinetis-port-pins = < 28 1 >;
	};
	CAN2_RX_PTE28: can2_rx_pte28 {
		nxp,kinetis-port-pins = < 28 2 >;
	};
	HSADC0A_CH4_PTE29: CMP1_IN5_PTE29: CMP0_IN5_PTE29: hsadc0a_ch4_pte29 {
		nxp,kinetis-port-pins = < 29 0 >;
	};
	PTE29: GPIOE_PTE29: gpioe_pte29 {
		nxp,kinetis-port-pins = < 29 1 >;
	};
	FTM0_CH2_PTE29: ftm0_ch2_pte29 {
		nxp,kinetis-port-pins = < 29 3 >;
	};
	FTM_CLKIN0_PTE29: ftm_clkin0_pte29 {
		nxp,kinetis-port-pins = < 29 5 >;
	};
	DAC0_OUT_PTE30: CMP1_IN3_PTE30: HSADC0A_CH5_PTE30: dac0_out_pte30 {
		nxp,kinetis-port-pins = < 30 0 >;
	};
	PTE30: GPIOE_PTE30: gpioe_pte30 {
		nxp,kinetis-port-pins = < 30 1 >;
	};
	FTM0_CH3_PTE30: ftm0_ch3_pte30 {
		nxp,kinetis-port-pins = < 30 3 >;
	};
	FTM_CLKIN1_PTE30: ftm_clkin1_pte30 {
		nxp,kinetis-port-pins = < 30 5 >;
	};
};