1/*
2 * NOTE: Autogenerated file by kinetis_signal2dts.py
3 *       for MKL25Z128VLK4/signal_configuration.xml
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8/*
9 * Pin nodes are of the form:
10 *
11 *	<SIGNAL[0..n]>: <signal[0]> {
12 *		nxp,kinetis-port-pins = < PIN PCR[MUX] >;
13 *	};
14 */
15
16&porta {
17	TSI0_CH1_PTA0: tsi0_ch1_pta0 {
18		nxp,kinetis-port-pins = < 0 0 >;
19	};
20	PTA0: GPIOA_PTA0: gpioa_pta0 {
21		nxp,kinetis-port-pins = < 0 1 >;
22	};
23	TPM0_CH5_PTA0: tpm0_ch5_pta0 {
24		nxp,kinetis-port-pins = < 0 3 >;
25	};
26	SWD_CLK_PTA0: swd_clk_pta0 {
27		nxp,kinetis-port-pins = < 0 7 >;
28	};
29	TSI0_CH2_PTA1: tsi0_ch2_pta1 {
30		nxp,kinetis-port-pins = < 1 0 >;
31	};
32	PTA1: GPIOA_PTA1: gpioa_pta1 {
33		nxp,kinetis-port-pins = < 1 1 >;
34	};
35	UART0_RX_PTA1: uart0_rx_pta1 {
36		nxp,kinetis-port-pins = < 1 2 >;
37	};
38	TPM2_CH0_PTA1: tpm2_ch0_pta1 {
39		nxp,kinetis-port-pins = < 1 3 >;
40	};
41	TSI0_CH3_PTA2: tsi0_ch3_pta2 {
42		nxp,kinetis-port-pins = < 2 0 >;
43	};
44	PTA2: GPIOA_PTA2: gpioa_pta2 {
45		nxp,kinetis-port-pins = < 2 1 >;
46	};
47	UART0_TX_PTA2: uart0_tx_pta2 {
48		nxp,kinetis-port-pins = < 2 2 >;
49	};
50	TPM2_CH1_PTA2: tpm2_ch1_pta2 {
51		nxp,kinetis-port-pins = < 2 3 >;
52	};
53	TSI0_CH4_PTA3: tsi0_ch4_pta3 {
54		nxp,kinetis-port-pins = < 3 0 >;
55	};
56	PTA3: GPIOA_PTA3: gpioa_pta3 {
57		nxp,kinetis-port-pins = < 3 1 >;
58	};
59	I2C1_SCL_PTA3: i2c1_scl_pta3 {
60		nxp,kinetis-port-pins = < 3 2 >;
61	};
62	TPM0_CH0_PTA3: tpm0_ch0_pta3 {
63		nxp,kinetis-port-pins = < 3 3 >;
64	};
65	SWD_DIO_PTA3: swd_dio_pta3 {
66		nxp,kinetis-port-pins = < 3 7 >;
67	};
68	TSI0_CH5_PTA4: tsi0_ch5_pta4 {
69		nxp,kinetis-port-pins = < 4 0 >;
70	};
71	PTA4: GPIOA_PTA4: gpioa_pta4 {
72		nxp,kinetis-port-pins = < 4 1 >;
73	};
74	I2C1_SDA_PTA4: i2c1_sda_pta4 {
75		nxp,kinetis-port-pins = < 4 2 >;
76	};
77	TPM0_CH1_PTA4: tpm0_ch1_pta4 {
78		nxp,kinetis-port-pins = < 4 3 >;
79	};
80	NMI_b_PTA4: nmi_b_pta4 {
81		nxp,kinetis-port-pins = < 4 7 >;
82	};
83	PTA5: GPIOA_PTA5: gpioa_pta5 {
84		nxp,kinetis-port-pins = < 5 1 >;
85	};
86	USB_CLKIN_PTA5: usb_clkin_pta5 {
87		nxp,kinetis-port-pins = < 5 2 >;
88	};
89	TPM0_CH2_PTA5: tpm0_ch2_pta5 {
90		nxp,kinetis-port-pins = < 5 3 >;
91	};
92	PTA12: GPIOA_PTA12: gpioa_pta12 {
93		nxp,kinetis-port-pins = < 12 1 >;
94	};
95	TPM1_CH0_PTA12: tpm1_ch0_pta12 {
96		nxp,kinetis-port-pins = < 12 3 >;
97	};
98	PTA13: GPIOA_PTA13: gpioa_pta13 {
99		nxp,kinetis-port-pins = < 13 1 >;
100	};
101	TPM1_CH1_PTA13: tpm1_ch1_pta13 {
102		nxp,kinetis-port-pins = < 13 3 >;
103	};
104	PTA14: GPIOA_PTA14: gpioa_pta14 {
105		nxp,kinetis-port-pins = < 14 1 >;
106	};
107	SPI0_PCS0_PTA14: spi0_pcs0_pta14 {
108		nxp,kinetis-port-pins = < 14 2 >;
109	};
110	UART0_TX_PTA14: uart0_tx_pta14 {
111		nxp,kinetis-port-pins = < 14 3 >;
112	};
113	PTA15: GPIOA_PTA15: gpioa_pta15 {
114		nxp,kinetis-port-pins = < 15 1 >;
115	};
116	SPI0_SCK_PTA15: spi0_sck_pta15 {
117		nxp,kinetis-port-pins = < 15 2 >;
118	};
119	UART0_RX_PTA15: uart0_rx_pta15 {
120		nxp,kinetis-port-pins = < 15 3 >;
121	};
122	PTA16: GPIOA_PTA16: gpioa_pta16 {
123		nxp,kinetis-port-pins = < 16 1 >;
124	};
125	SPI0_MOSI_PTA16: spi0_mosi_pta16 {
126		nxp,kinetis-port-pins = < 16 2 >;
127	};
128	SPI0_MISO_PTA16: spi0_miso_pta16 {
129		nxp,kinetis-port-pins = < 16 5 >;
130	};
131	PTA17: GPIOA_PTA17: gpioa_pta17 {
132		nxp,kinetis-port-pins = < 17 1 >;
133	};
134	SPI0_MISO_PTA17: spi0_miso_pta17 {
135		nxp,kinetis-port-pins = < 17 2 >;
136	};
137	SPI0_MOSI_PTA17: spi0_mosi_pta17 {
138		nxp,kinetis-port-pins = < 17 5 >;
139	};
140	EXTAL0_PTA18: extal0_pta18 {
141		nxp,kinetis-port-pins = < 18 0 >;
142	};
143	PTA18: GPIOA_PTA18: gpioa_pta18 {
144		nxp,kinetis-port-pins = < 18 1 >;
145	};
146	UART1_RX_PTA18: uart1_rx_pta18 {
147		nxp,kinetis-port-pins = < 18 3 >;
148	};
149	TPM_CLKIN0_PTA18: tpm_clkin0_pta18 {
150		nxp,kinetis-port-pins = < 18 4 >;
151	};
152	XTAL0_PTA19: xtal0_pta19 {
153		nxp,kinetis-port-pins = < 19 0 >;
154	};
155	PTA19: GPIOA_PTA19: gpioa_pta19 {
156		nxp,kinetis-port-pins = < 19 1 >;
157	};
158	UART1_TX_PTA19: uart1_tx_pta19 {
159		nxp,kinetis-port-pins = < 19 3 >;
160	};
161	TPM_CLKIN1_PTA19: tpm_clkin1_pta19 {
162		nxp,kinetis-port-pins = < 19 4 >;
163	};
164	LPTMR0_ALT1_PTA19: lptmr0_alt1_pta19 {
165		nxp,kinetis-port-pins = < 19 6 >;
166	};
167	PTA20: GPIOA_PTA20: gpioa_pta20 {
168		nxp,kinetis-port-pins = < 20 1 >;
169	};
170	RESET_b_PTA20: reset_b_pta20 {
171		nxp,kinetis-port-pins = < 20 7 >;
172	};
173};
174
175&portb {
176	ADC0_SE8_PTB0: TSI0_CH0_PTB0: adc0_se8_ptb0 {
177		nxp,kinetis-port-pins = < 0 0 >;
178	};
179	PTB0: GPIOB_PTB0: LLWU_P5_PTB0: gpiob_ptb0 {
180		nxp,kinetis-port-pins = < 0 1 >;
181	};
182	I2C0_SCL_PTB0: i2c0_scl_ptb0 {
183		nxp,kinetis-port-pins = < 0 2 >;
184	};
185	TPM1_CH0_PTB0: tpm1_ch0_ptb0 {
186		nxp,kinetis-port-pins = < 0 3 >;
187	};
188	ADC0_SE9_PTB1: TSI0_CH6_PTB1: adc0_se9_ptb1 {
189		nxp,kinetis-port-pins = < 1 0 >;
190	};
191	PTB1: GPIOB_PTB1: gpiob_ptb1 {
192		nxp,kinetis-port-pins = < 1 1 >;
193	};
194	I2C0_SDA_PTB1: i2c0_sda_ptb1 {
195		nxp,kinetis-port-pins = < 1 2 >;
196	};
197	TPM1_CH1_PTB1: tpm1_ch1_ptb1 {
198		nxp,kinetis-port-pins = < 1 3 >;
199	};
200	ADC0_SE12_PTB2: TSI0_CH7_PTB2: adc0_se12_ptb2 {
201		nxp,kinetis-port-pins = < 2 0 >;
202	};
203	PTB2: GPIOB_PTB2: gpiob_ptb2 {
204		nxp,kinetis-port-pins = < 2 1 >;
205	};
206	I2C0_SCL_PTB2: i2c0_scl_ptb2 {
207		nxp,kinetis-port-pins = < 2 2 >;
208	};
209	TPM2_CH0_PTB2: tpm2_ch0_ptb2 {
210		nxp,kinetis-port-pins = < 2 3 >;
211	};
212	ADC0_SE13_PTB3: TSI0_CH8_PTB3: adc0_se13_ptb3 {
213		nxp,kinetis-port-pins = < 3 0 >;
214	};
215	PTB3: GPIOB_PTB3: gpiob_ptb3 {
216		nxp,kinetis-port-pins = < 3 1 >;
217	};
218	I2C0_SDA_PTB3: i2c0_sda_ptb3 {
219		nxp,kinetis-port-pins = < 3 2 >;
220	};
221	TPM2_CH1_PTB3: tpm2_ch1_ptb3 {
222		nxp,kinetis-port-pins = < 3 3 >;
223	};
224	PTB8: GPIOB_PTB8: gpiob_ptb8 {
225		nxp,kinetis-port-pins = < 8 1 >;
226	};
227	EXTRG_IN_PTB8: extrg_in_ptb8 {
228		nxp,kinetis-port-pins = < 8 3 >;
229	};
230	PTB9: GPIOB_PTB9: gpiob_ptb9 {
231		nxp,kinetis-port-pins = < 9 1 >;
232	};
233	PTB10: GPIOB_PTB10: gpiob_ptb10 {
234		nxp,kinetis-port-pins = < 10 1 >;
235	};
236	SPI1_PCS0_PTB10: spi1_pcs0_ptb10 {
237		nxp,kinetis-port-pins = < 10 2 >;
238	};
239	PTB11: GPIOB_PTB11: gpiob_ptb11 {
240		nxp,kinetis-port-pins = < 11 1 >;
241	};
242	SPI1_SCK_PTB11: spi1_sck_ptb11 {
243		nxp,kinetis-port-pins = < 11 2 >;
244	};
245	TSI0_CH9_PTB16: tsi0_ch9_ptb16 {
246		nxp,kinetis-port-pins = < 16 0 >;
247	};
248	PTB16: GPIOB_PTB16: gpiob_ptb16 {
249		nxp,kinetis-port-pins = < 16 1 >;
250	};
251	SPI1_MOSI_PTB16: spi1_mosi_ptb16 {
252		nxp,kinetis-port-pins = < 16 2 >;
253	};
254	UART0_RX_PTB16: uart0_rx_ptb16 {
255		nxp,kinetis-port-pins = < 16 3 >;
256	};
257	TPM_CLKIN0_PTB16: tpm_clkin0_ptb16 {
258		nxp,kinetis-port-pins = < 16 4 >;
259	};
260	SPI1_MISO_PTB16: spi1_miso_ptb16 {
261		nxp,kinetis-port-pins = < 16 5 >;
262	};
263	TSI0_CH10_PTB17: tsi0_ch10_ptb17 {
264		nxp,kinetis-port-pins = < 17 0 >;
265	};
266	PTB17: GPIOB_PTB17: gpiob_ptb17 {
267		nxp,kinetis-port-pins = < 17 1 >;
268	};
269	SPI1_MISO_PTB17: spi1_miso_ptb17 {
270		nxp,kinetis-port-pins = < 17 2 >;
271	};
272	UART0_TX_PTB17: uart0_tx_ptb17 {
273		nxp,kinetis-port-pins = < 17 3 >;
274	};
275	TPM_CLKIN1_PTB17: tpm_clkin1_ptb17 {
276		nxp,kinetis-port-pins = < 17 4 >;
277	};
278	SPI1_MOSI_PTB17: spi1_mosi_ptb17 {
279		nxp,kinetis-port-pins = < 17 5 >;
280	};
281	TSI0_CH11_PTB18: tsi0_ch11_ptb18 {
282		nxp,kinetis-port-pins = < 18 0 >;
283	};
284	PTB18: GPIOB_PTB18: gpiob_ptb18 {
285		nxp,kinetis-port-pins = < 18 1 >;
286	};
287	TPM2_CH0_PTB18: tpm2_ch0_ptb18 {
288		nxp,kinetis-port-pins = < 18 3 >;
289	};
290	TSI0_CH12_PTB19: tsi0_ch12_ptb19 {
291		nxp,kinetis-port-pins = < 19 0 >;
292	};
293	PTB19: GPIOB_PTB19: gpiob_ptb19 {
294		nxp,kinetis-port-pins = < 19 1 >;
295	};
296	TPM2_CH1_PTB19: tpm2_ch1_ptb19 {
297		nxp,kinetis-port-pins = < 19 3 >;
298	};
299};
300
301&portc {
302	ADC0_SE14_PTC0: TSI0_CH13_PTC0: adc0_se14_ptc0 {
303		nxp,kinetis-port-pins = < 0 0 >;
304	};
305	PTC0: GPIOC_PTC0: gpioc_ptc0 {
306		nxp,kinetis-port-pins = < 0 1 >;
307	};
308	EXTRG_IN_PTC0: extrg_in_ptc0 {
309		nxp,kinetis-port-pins = < 0 3 >;
310	};
311	CMP0_OUT_PTC0: cmp0_out_ptc0 {
312		nxp,kinetis-port-pins = < 0 5 >;
313	};
314	ADC0_SE15_PTC1: TSI0_CH14_PTC1: adc0_se15_ptc1 {
315		nxp,kinetis-port-pins = < 1 0 >;
316	};
317	PTC1: GPIOC_PTC1: LLWU_P6_PTC1: RTC_CLKIN_PTC1: gpioc_ptc1 {
318		nxp,kinetis-port-pins = < 1 1 >;
319	};
320	I2C1_SCL_PTC1: i2c1_scl_ptc1 {
321		nxp,kinetis-port-pins = < 1 2 >;
322	};
323	TPM0_CH0_PTC1: tpm0_ch0_ptc1 {
324		nxp,kinetis-port-pins = < 1 4 >;
325	};
326	ADC0_SE11_PTC2: TSI0_CH15_PTC2: adc0_se11_ptc2 {
327		nxp,kinetis-port-pins = < 2 0 >;
328	};
329	PTC2: GPIOC_PTC2: gpioc_ptc2 {
330		nxp,kinetis-port-pins = < 2 1 >;
331	};
332	I2C1_SDA_PTC2: i2c1_sda_ptc2 {
333		nxp,kinetis-port-pins = < 2 2 >;
334	};
335	TPM0_CH1_PTC2: tpm0_ch1_ptc2 {
336		nxp,kinetis-port-pins = < 2 4 >;
337	};
338	PTC3: GPIOC_PTC3: LLWU_P7_PTC3: gpioc_ptc3 {
339		nxp,kinetis-port-pins = < 3 1 >;
340	};
341	UART1_RX_PTC3: uart1_rx_ptc3 {
342		nxp,kinetis-port-pins = < 3 3 >;
343	};
344	TPM0_CH2_PTC3: tpm0_ch2_ptc3 {
345		nxp,kinetis-port-pins = < 3 4 >;
346	};
347	CLKOUTa_PTC3: clkouta_ptc3 {
348		nxp,kinetis-port-pins = < 3 5 >;
349	};
350	PTC4: GPIOC_PTC4: LLWU_P8_PTC4: gpioc_ptc4 {
351		nxp,kinetis-port-pins = < 4 1 >;
352	};
353	SPI0_PCS0_PTC4: spi0_pcs0_ptc4 {
354		nxp,kinetis-port-pins = < 4 2 >;
355	};
356	UART1_TX_PTC4: uart1_tx_ptc4 {
357		nxp,kinetis-port-pins = < 4 3 >;
358	};
359	TPM0_CH3_PTC4: tpm0_ch3_ptc4 {
360		nxp,kinetis-port-pins = < 4 4 >;
361	};
362	PTC5: GPIOC_PTC5: LLWU_P9_PTC5: gpioc_ptc5 {
363		nxp,kinetis-port-pins = < 5 1 >;
364	};
365	SPI0_SCK_PTC5: spi0_sck_ptc5 {
366		nxp,kinetis-port-pins = < 5 2 >;
367	};
368	LPTMR0_ALT2_PTC5: lptmr0_alt2_ptc5 {
369		nxp,kinetis-port-pins = < 5 3 >;
370	};
371	CMP0_OUT_PTC5: cmp0_out_ptc5 {
372		nxp,kinetis-port-pins = < 5 6 >;
373	};
374	CMP0_IN0_PTC6: cmp0_in0_ptc6 {
375		nxp,kinetis-port-pins = < 6 0 >;
376	};
377	PTC6: GPIOC_PTC6: LLWU_P10_PTC6: gpioc_ptc6 {
378		nxp,kinetis-port-pins = < 6 1 >;
379	};
380	SPI0_MOSI_PTC6: spi0_mosi_ptc6 {
381		nxp,kinetis-port-pins = < 6 2 >;
382	};
383	EXTRG_IN_PTC6: extrg_in_ptc6 {
384		nxp,kinetis-port-pins = < 6 3 >;
385	};
386	SPI0_MISO_PTC6: spi0_miso_ptc6 {
387		nxp,kinetis-port-pins = < 6 5 >;
388	};
389	CMP0_IN1_PTC7: cmp0_in1_ptc7 {
390		nxp,kinetis-port-pins = < 7 0 >;
391	};
392	PTC7: GPIOC_PTC7: gpioc_ptc7 {
393		nxp,kinetis-port-pins = < 7 1 >;
394	};
395	SPI0_MISO_PTC7: spi0_miso_ptc7 {
396		nxp,kinetis-port-pins = < 7 2 >;
397	};
398	SPI0_MOSI_PTC7: spi0_mosi_ptc7 {
399		nxp,kinetis-port-pins = < 7 5 >;
400	};
401	CMP0_IN2_PTC8: cmp0_in2_ptc8 {
402		nxp,kinetis-port-pins = < 8 0 >;
403	};
404	PTC8: GPIOC_PTC8: gpioc_ptc8 {
405		nxp,kinetis-port-pins = < 8 1 >;
406	};
407	I2C0_SCL_PTC8: i2c0_scl_ptc8 {
408		nxp,kinetis-port-pins = < 8 2 >;
409	};
410	TPM0_CH4_PTC8: tpm0_ch4_ptc8 {
411		nxp,kinetis-port-pins = < 8 3 >;
412	};
413	CMP0_IN3_PTC9: cmp0_in3_ptc9 {
414		nxp,kinetis-port-pins = < 9 0 >;
415	};
416	PTC9: GPIOC_PTC9: gpioc_ptc9 {
417		nxp,kinetis-port-pins = < 9 1 >;
418	};
419	I2C0_SDA_PTC9: i2c0_sda_ptc9 {
420		nxp,kinetis-port-pins = < 9 2 >;
421	};
422	TPM0_CH5_PTC9: tpm0_ch5_ptc9 {
423		nxp,kinetis-port-pins = < 9 3 >;
424	};
425	PTC10: GPIOC_PTC10: gpioc_ptc10 {
426		nxp,kinetis-port-pins = < 10 1 >;
427	};
428	I2C1_SCL_PTC10: i2c1_scl_ptc10 {
429		nxp,kinetis-port-pins = < 10 2 >;
430	};
431	PTC11: GPIOC_PTC11: gpioc_ptc11 {
432		nxp,kinetis-port-pins = < 11 1 >;
433	};
434	I2C1_SDA_PTC11: i2c1_sda_ptc11 {
435		nxp,kinetis-port-pins = < 11 2 >;
436	};
437	PTC12: GPIOC_PTC12: gpioc_ptc12 {
438		nxp,kinetis-port-pins = < 12 1 >;
439	};
440	TPM_CLKIN0_PTC12: tpm_clkin0_ptc12 {
441		nxp,kinetis-port-pins = < 12 4 >;
442	};
443	PTC13: GPIOC_PTC13: gpioc_ptc13 {
444		nxp,kinetis-port-pins = < 13 1 >;
445	};
446	TPM_CLKIN1_PTC13: tpm_clkin1_ptc13 {
447		nxp,kinetis-port-pins = < 13 4 >;
448	};
449	PTC16: GPIOC_PTC16: gpioc_ptc16 {
450		nxp,kinetis-port-pins = < 16 1 >;
451	};
452	PTC17: GPIOC_PTC17: gpioc_ptc17 {
453		nxp,kinetis-port-pins = < 17 1 >;
454	};
455};
456
457&portd {
458	PTD0: GPIOD_PTD0: gpiod_ptd0 {
459		nxp,kinetis-port-pins = < 0 1 >;
460	};
461	SPI0_PCS0_PTD0: spi0_pcs0_ptd0 {
462		nxp,kinetis-port-pins = < 0 2 >;
463	};
464	TPM0_CH0_PTD0: tpm0_ch0_ptd0 {
465		nxp,kinetis-port-pins = < 0 4 >;
466	};
467	ADC0_SE5b_PTD1: adc0_se5b_ptd1 {
468		nxp,kinetis-port-pins = < 1 0 >;
469	};
470	PTD1: GPIOD_PTD1: gpiod_ptd1 {
471		nxp,kinetis-port-pins = < 1 1 >;
472	};
473	SPI0_SCK_PTD1: spi0_sck_ptd1 {
474		nxp,kinetis-port-pins = < 1 2 >;
475	};
476	TPM0_CH1_PTD1: tpm0_ch1_ptd1 {
477		nxp,kinetis-port-pins = < 1 4 >;
478	};
479	PTD2: GPIOD_PTD2: gpiod_ptd2 {
480		nxp,kinetis-port-pins = < 2 1 >;
481	};
482	SPI0_MOSI_PTD2: spi0_mosi_ptd2 {
483		nxp,kinetis-port-pins = < 2 2 >;
484	};
485	UART2_RX_PTD2: uart2_rx_ptd2 {
486		nxp,kinetis-port-pins = < 2 3 >;
487	};
488	TPM0_CH2_PTD2: tpm0_ch2_ptd2 {
489		nxp,kinetis-port-pins = < 2 4 >;
490	};
491	SPI0_MISO_PTD2: spi0_miso_ptd2 {
492		nxp,kinetis-port-pins = < 2 5 >;
493	};
494	PTD3: GPIOD_PTD3: gpiod_ptd3 {
495		nxp,kinetis-port-pins = < 3 1 >;
496	};
497	SPI0_MISO_PTD3: spi0_miso_ptd3 {
498		nxp,kinetis-port-pins = < 3 2 >;
499	};
500	UART2_TX_PTD3: uart2_tx_ptd3 {
501		nxp,kinetis-port-pins = < 3 3 >;
502	};
503	TPM0_CH3_PTD3: tpm0_ch3_ptd3 {
504		nxp,kinetis-port-pins = < 3 4 >;
505	};
506	SPI0_MOSI_PTD3: spi0_mosi_ptd3 {
507		nxp,kinetis-port-pins = < 3 5 >;
508	};
509	PTD4: GPIOD_PTD4: LLWU_P14_PTD4: gpiod_ptd4 {
510		nxp,kinetis-port-pins = < 4 1 >;
511	};
512	SPI1_PCS0_PTD4: spi1_pcs0_ptd4 {
513		nxp,kinetis-port-pins = < 4 2 >;
514	};
515	UART2_RX_PTD4: uart2_rx_ptd4 {
516		nxp,kinetis-port-pins = < 4 3 >;
517	};
518	TPM0_CH4_PTD4: tpm0_ch4_ptd4 {
519		nxp,kinetis-port-pins = < 4 4 >;
520	};
521	ADC0_SE6b_PTD5: adc0_se6b_ptd5 {
522		nxp,kinetis-port-pins = < 5 0 >;
523	};
524	PTD5: GPIOD_PTD5: gpiod_ptd5 {
525		nxp,kinetis-port-pins = < 5 1 >;
526	};
527	SPI1_SCK_PTD5: spi1_sck_ptd5 {
528		nxp,kinetis-port-pins = < 5 2 >;
529	};
530	UART2_TX_PTD5: uart2_tx_ptd5 {
531		nxp,kinetis-port-pins = < 5 3 >;
532	};
533	TPM0_CH5_PTD5: tpm0_ch5_ptd5 {
534		nxp,kinetis-port-pins = < 5 4 >;
535	};
536	ADC0_SE7b_PTD6: adc0_se7b_ptd6 {
537		nxp,kinetis-port-pins = < 6 0 >;
538	};
539	PTD6: GPIOD_PTD6: LLWU_P15_PTD6: gpiod_ptd6 {
540		nxp,kinetis-port-pins = < 6 1 >;
541	};
542	SPI1_MOSI_PTD6: spi1_mosi_ptd6 {
543		nxp,kinetis-port-pins = < 6 2 >;
544	};
545	UART0_RX_PTD6: uart0_rx_ptd6 {
546		nxp,kinetis-port-pins = < 6 3 >;
547	};
548	SPI1_MISO_PTD6: spi1_miso_ptd6 {
549		nxp,kinetis-port-pins = < 6 5 >;
550	};
551	PTD7: GPIOD_PTD7: gpiod_ptd7 {
552		nxp,kinetis-port-pins = < 7 1 >;
553	};
554	SPI1_MISO_PTD7: spi1_miso_ptd7 {
555		nxp,kinetis-port-pins = < 7 2 >;
556	};
557	UART0_TX_PTD7: uart0_tx_ptd7 {
558		nxp,kinetis-port-pins = < 7 3 >;
559	};
560	SPI1_MOSI_PTD7: spi1_mosi_ptd7 {
561		nxp,kinetis-port-pins = < 7 5 >;
562	};
563};
564
565&porte {
566	PTE0: GPIOE_PTE0: gpioe_pte0 {
567		nxp,kinetis-port-pins = < 0 1 >;
568	};
569	UART1_TX_PTE0: uart1_tx_pte0 {
570		nxp,kinetis-port-pins = < 0 3 >;
571	};
572	RTC_CLKOUT_PTE0: rtc_clkout_pte0 {
573		nxp,kinetis-port-pins = < 0 4 >;
574	};
575	CMP0_OUT_PTE0: cmp0_out_pte0 {
576		nxp,kinetis-port-pins = < 0 5 >;
577	};
578	I2C1_SDA_PTE0: i2c1_sda_pte0 {
579		nxp,kinetis-port-pins = < 0 6 >;
580	};
581	PTE1: GPIOE_PTE1: gpioe_pte1 {
582		nxp,kinetis-port-pins = < 1 1 >;
583	};
584	SPI1_MOSI_PTE1: spi1_mosi_pte1 {
585		nxp,kinetis-port-pins = < 1 2 >;
586	};
587	UART1_RX_PTE1: uart1_rx_pte1 {
588		nxp,kinetis-port-pins = < 1 3 >;
589	};
590	SPI1_MISO_PTE1: spi1_miso_pte1 {
591		nxp,kinetis-port-pins = < 1 5 >;
592	};
593	I2C1_SCL_PTE1: i2c1_scl_pte1 {
594		nxp,kinetis-port-pins = < 1 6 >;
595	};
596	PTE2: GPIOE_PTE2: gpioe_pte2 {
597		nxp,kinetis-port-pins = < 2 1 >;
598	};
599	SPI1_SCK_PTE2: spi1_sck_pte2 {
600		nxp,kinetis-port-pins = < 2 2 >;
601	};
602	PTE3: GPIOE_PTE3: gpioe_pte3 {
603		nxp,kinetis-port-pins = < 3 1 >;
604	};
605	SPI1_MISO_PTE3: spi1_miso_pte3 {
606		nxp,kinetis-port-pins = < 3 2 >;
607	};
608	SPI1_MOSI_PTE3: spi1_mosi_pte3 {
609		nxp,kinetis-port-pins = < 3 5 >;
610	};
611	PTE4: GPIOE_PTE4: gpioe_pte4 {
612		nxp,kinetis-port-pins = < 4 1 >;
613	};
614	SPI1_PCS0_PTE4: spi1_pcs0_pte4 {
615		nxp,kinetis-port-pins = < 4 2 >;
616	};
617	PTE5: GPIOE_PTE5: gpioe_pte5 {
618		nxp,kinetis-port-pins = < 5 1 >;
619	};
620	ADC0_DP0_PTE20: ADC0_SE0_PTE20: adc0_dp0_pte20 {
621		nxp,kinetis-port-pins = < 20 0 >;
622	};
623	PTE20: GPIOE_PTE20: gpioe_pte20 {
624		nxp,kinetis-port-pins = < 20 1 >;
625	};
626	TPM1_CH0_PTE20: tpm1_ch0_pte20 {
627		nxp,kinetis-port-pins = < 20 3 >;
628	};
629	UART0_TX_PTE20: uart0_tx_pte20 {
630		nxp,kinetis-port-pins = < 20 4 >;
631	};
632	ADC0_DM0_PTE21: ADC0_SE4a_PTE21: adc0_dm0_pte21 {
633		nxp,kinetis-port-pins = < 21 0 >;
634	};
635	PTE21: GPIOE_PTE21: gpioe_pte21 {
636		nxp,kinetis-port-pins = < 21 1 >;
637	};
638	TPM1_CH1_PTE21: tpm1_ch1_pte21 {
639		nxp,kinetis-port-pins = < 21 3 >;
640	};
641	UART0_RX_PTE21: uart0_rx_pte21 {
642		nxp,kinetis-port-pins = < 21 4 >;
643	};
644	ADC0_DP3_PTE22: ADC0_SE3_PTE22: adc0_dp3_pte22 {
645		nxp,kinetis-port-pins = < 22 0 >;
646	};
647	PTE22: GPIOE_PTE22: gpioe_pte22 {
648		nxp,kinetis-port-pins = < 22 1 >;
649	};
650	TPM2_CH0_PTE22: tpm2_ch0_pte22 {
651		nxp,kinetis-port-pins = < 22 3 >;
652	};
653	UART2_TX_PTE22: uart2_tx_pte22 {
654		nxp,kinetis-port-pins = < 22 4 >;
655	};
656	ADC0_DM3_PTE23: ADC0_SE7a_PTE23: adc0_dm3_pte23 {
657		nxp,kinetis-port-pins = < 23 0 >;
658	};
659	PTE23: GPIOE_PTE23: gpioe_pte23 {
660		nxp,kinetis-port-pins = < 23 1 >;
661	};
662	TPM2_CH1_PTE23: tpm2_ch1_pte23 {
663		nxp,kinetis-port-pins = < 23 3 >;
664	};
665	UART2_RX_PTE23: uart2_rx_pte23 {
666		nxp,kinetis-port-pins = < 23 4 >;
667	};
668	PTE24: GPIOE_PTE24: gpioe_pte24 {
669		nxp,kinetis-port-pins = < 24 1 >;
670	};
671	TPM0_CH0_PTE24: tpm0_ch0_pte24 {
672		nxp,kinetis-port-pins = < 24 3 >;
673	};
674	I2C0_SCL_PTE24: i2c0_scl_pte24 {
675		nxp,kinetis-port-pins = < 24 5 >;
676	};
677	PTE25: GPIOE_PTE25: gpioe_pte25 {
678		nxp,kinetis-port-pins = < 25 1 >;
679	};
680	TPM0_CH1_PTE25: tpm0_ch1_pte25 {
681		nxp,kinetis-port-pins = < 25 3 >;
682	};
683	I2C0_SDA_PTE25: i2c0_sda_pte25 {
684		nxp,kinetis-port-pins = < 25 5 >;
685	};
686	CMP0_IN5_PTE29: ADC0_SE4b_PTE29: cmp0_in5_pte29 {
687		nxp,kinetis-port-pins = < 29 0 >;
688	};
689	PTE29: GPIOE_PTE29: gpioe_pte29 {
690		nxp,kinetis-port-pins = < 29 1 >;
691	};
692	TPM0_CH2_PTE29: tpm0_ch2_pte29 {
693		nxp,kinetis-port-pins = < 29 3 >;
694	};
695	TPM_CLKIN0_PTE29: tpm_clkin0_pte29 {
696		nxp,kinetis-port-pins = < 29 4 >;
697	};
698	DAC0_OUT_PTE30: ADC0_SE23_PTE30: CMP0_IN4_PTE30: dac0_out_pte30 {
699		nxp,kinetis-port-pins = < 30 0 >;
700	};
701	PTE30: GPIOE_PTE30: gpioe_pte30 {
702		nxp,kinetis-port-pins = < 30 1 >;
703	};
704	TPM0_CH3_PTE30: tpm0_ch3_pte30 {
705		nxp,kinetis-port-pins = < 30 3 >;
706	};
707	TPM_CLKIN1_PTE30: tpm_clkin1_pte30 {
708		nxp,kinetis-port-pins = < 30 4 >;
709	};
710	PTE31: GPIOE_PTE31: gpioe_pte31 {
711		nxp,kinetis-port-pins = < 31 1 >;
712	};
713	TPM0_CH4_PTE31: tpm0_ch4_pte31 {
714		nxp,kinetis-port-pins = < 31 3 >;
715	};
716};
717
718