/*
 * NOTE: Autogenerated file by kinetis_signal2dts.py
 *       for MKL25Z128VLK4/signal_configuration.xml
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/*
 * Pin nodes are of the form:
 *
 *	<SIGNAL[0..n]>: <signal[0]> {
 *		nxp,kinetis-port-pins = < PIN PCR[MUX] >;
 *	};
 */

&porta {
	TSI0_CH1_PTA0: tsi0_ch1_pta0 {
		nxp,kinetis-port-pins = < 0 0 >;
	};
	PTA0: GPIOA_PTA0: gpioa_pta0 {
		nxp,kinetis-port-pins = < 0 1 >;
	};
	TPM0_CH5_PTA0: tpm0_ch5_pta0 {
		nxp,kinetis-port-pins = < 0 3 >;
	};
	SWD_CLK_PTA0: swd_clk_pta0 {
		nxp,kinetis-port-pins = < 0 7 >;
	};
	TSI0_CH2_PTA1: tsi0_ch2_pta1 {
		nxp,kinetis-port-pins = < 1 0 >;
	};
	PTA1: GPIOA_PTA1: gpioa_pta1 {
		nxp,kinetis-port-pins = < 1 1 >;
	};
	UART0_RX_PTA1: uart0_rx_pta1 {
		nxp,kinetis-port-pins = < 1 2 >;
	};
	TPM2_CH0_PTA1: tpm2_ch0_pta1 {
		nxp,kinetis-port-pins = < 1 3 >;
	};
	TSI0_CH3_PTA2: tsi0_ch3_pta2 {
		nxp,kinetis-port-pins = < 2 0 >;
	};
	PTA2: GPIOA_PTA2: gpioa_pta2 {
		nxp,kinetis-port-pins = < 2 1 >;
	};
	UART0_TX_PTA2: uart0_tx_pta2 {
		nxp,kinetis-port-pins = < 2 2 >;
	};
	TPM2_CH1_PTA2: tpm2_ch1_pta2 {
		nxp,kinetis-port-pins = < 2 3 >;
	};
	TSI0_CH4_PTA3: tsi0_ch4_pta3 {
		nxp,kinetis-port-pins = < 3 0 >;
	};
	PTA3: GPIOA_PTA3: gpioa_pta3 {
		nxp,kinetis-port-pins = < 3 1 >;
	};
	I2C1_SCL_PTA3: i2c1_scl_pta3 {
		nxp,kinetis-port-pins = < 3 2 >;
	};
	TPM0_CH0_PTA3: tpm0_ch0_pta3 {
		nxp,kinetis-port-pins = < 3 3 >;
	};
	SWD_DIO_PTA3: swd_dio_pta3 {
		nxp,kinetis-port-pins = < 3 7 >;
	};
	TSI0_CH5_PTA4: tsi0_ch5_pta4 {
		nxp,kinetis-port-pins = < 4 0 >;
	};
	PTA4: GPIOA_PTA4: gpioa_pta4 {
		nxp,kinetis-port-pins = < 4 1 >;
	};
	I2C1_SDA_PTA4: i2c1_sda_pta4 {
		nxp,kinetis-port-pins = < 4 2 >;
	};
	TPM0_CH1_PTA4: tpm0_ch1_pta4 {
		nxp,kinetis-port-pins = < 4 3 >;
	};
	NMI_b_PTA4: nmi_b_pta4 {
		nxp,kinetis-port-pins = < 4 7 >;
	};
	PTA5: GPIOA_PTA5: gpioa_pta5 {
		nxp,kinetis-port-pins = < 5 1 >;
	};
	USB_CLKIN_PTA5: usb_clkin_pta5 {
		nxp,kinetis-port-pins = < 5 2 >;
	};
	TPM0_CH2_PTA5: tpm0_ch2_pta5 {
		nxp,kinetis-port-pins = < 5 3 >;
	};
	PTA12: GPIOA_PTA12: gpioa_pta12 {
		nxp,kinetis-port-pins = < 12 1 >;
	};
	TPM1_CH0_PTA12: tpm1_ch0_pta12 {
		nxp,kinetis-port-pins = < 12 3 >;
	};
	PTA13: GPIOA_PTA13: gpioa_pta13 {
		nxp,kinetis-port-pins = < 13 1 >;
	};
	TPM1_CH1_PTA13: tpm1_ch1_pta13 {
		nxp,kinetis-port-pins = < 13 3 >;
	};
	PTA14: GPIOA_PTA14: gpioa_pta14 {
		nxp,kinetis-port-pins = < 14 1 >;
	};
	SPI0_PCS0_PTA14: spi0_pcs0_pta14 {
		nxp,kinetis-port-pins = < 14 2 >;
	};
	UART0_TX_PTA14: uart0_tx_pta14 {
		nxp,kinetis-port-pins = < 14 3 >;
	};
	PTA15: GPIOA_PTA15: gpioa_pta15 {
		nxp,kinetis-port-pins = < 15 1 >;
	};
	SPI0_SCK_PTA15: spi0_sck_pta15 {
		nxp,kinetis-port-pins = < 15 2 >;
	};
	UART0_RX_PTA15: uart0_rx_pta15 {
		nxp,kinetis-port-pins = < 15 3 >;
	};
	PTA16: GPIOA_PTA16: gpioa_pta16 {
		nxp,kinetis-port-pins = < 16 1 >;
	};
	SPI0_MOSI_PTA16: spi0_mosi_pta16 {
		nxp,kinetis-port-pins = < 16 2 >;
	};
	SPI0_MISO_PTA16: spi0_miso_pta16 {
		nxp,kinetis-port-pins = < 16 5 >;
	};
	PTA17: GPIOA_PTA17: gpioa_pta17 {
		nxp,kinetis-port-pins = < 17 1 >;
	};
	SPI0_MISO_PTA17: spi0_miso_pta17 {
		nxp,kinetis-port-pins = < 17 2 >;
	};
	SPI0_MOSI_PTA17: spi0_mosi_pta17 {
		nxp,kinetis-port-pins = < 17 5 >;
	};
	EXTAL0_PTA18: extal0_pta18 {
		nxp,kinetis-port-pins = < 18 0 >;
	};
	PTA18: GPIOA_PTA18: gpioa_pta18 {
		nxp,kinetis-port-pins = < 18 1 >;
	};
	UART1_RX_PTA18: uart1_rx_pta18 {
		nxp,kinetis-port-pins = < 18 3 >;
	};
	TPM_CLKIN0_PTA18: tpm_clkin0_pta18 {
		nxp,kinetis-port-pins = < 18 4 >;
	};
	XTAL0_PTA19: xtal0_pta19 {
		nxp,kinetis-port-pins = < 19 0 >;
	};
	PTA19: GPIOA_PTA19: gpioa_pta19 {
		nxp,kinetis-port-pins = < 19 1 >;
	};
	UART1_TX_PTA19: uart1_tx_pta19 {
		nxp,kinetis-port-pins = < 19 3 >;
	};
	TPM_CLKIN1_PTA19: tpm_clkin1_pta19 {
		nxp,kinetis-port-pins = < 19 4 >;
	};
	LPTMR0_ALT1_PTA19: lptmr0_alt1_pta19 {
		nxp,kinetis-port-pins = < 19 6 >;
	};
	PTA20: GPIOA_PTA20: gpioa_pta20 {
		nxp,kinetis-port-pins = < 20 1 >;
	};
	RESET_b_PTA20: reset_b_pta20 {
		nxp,kinetis-port-pins = < 20 7 >;
	};
};

&portb {
	ADC0_SE8_PTB0: TSI0_CH0_PTB0: adc0_se8_ptb0 {
		nxp,kinetis-port-pins = < 0 0 >;
	};
	PTB0: GPIOB_PTB0: LLWU_P5_PTB0: gpiob_ptb0 {
		nxp,kinetis-port-pins = < 0 1 >;
	};
	I2C0_SCL_PTB0: i2c0_scl_ptb0 {
		nxp,kinetis-port-pins = < 0 2 >;
	};
	TPM1_CH0_PTB0: tpm1_ch0_ptb0 {
		nxp,kinetis-port-pins = < 0 3 >;
	};
	ADC0_SE9_PTB1: TSI0_CH6_PTB1: adc0_se9_ptb1 {
		nxp,kinetis-port-pins = < 1 0 >;
	};
	PTB1: GPIOB_PTB1: gpiob_ptb1 {
		nxp,kinetis-port-pins = < 1 1 >;
	};
	I2C0_SDA_PTB1: i2c0_sda_ptb1 {
		nxp,kinetis-port-pins = < 1 2 >;
	};
	TPM1_CH1_PTB1: tpm1_ch1_ptb1 {
		nxp,kinetis-port-pins = < 1 3 >;
	};
	ADC0_SE12_PTB2: TSI0_CH7_PTB2: adc0_se12_ptb2 {
		nxp,kinetis-port-pins = < 2 0 >;
	};
	PTB2: GPIOB_PTB2: gpiob_ptb2 {
		nxp,kinetis-port-pins = < 2 1 >;
	};
	I2C0_SCL_PTB2: i2c0_scl_ptb2 {
		nxp,kinetis-port-pins = < 2 2 >;
	};
	TPM2_CH0_PTB2: tpm2_ch0_ptb2 {
		nxp,kinetis-port-pins = < 2 3 >;
	};
	ADC0_SE13_PTB3: TSI0_CH8_PTB3: adc0_se13_ptb3 {
		nxp,kinetis-port-pins = < 3 0 >;
	};
	PTB3: GPIOB_PTB3: gpiob_ptb3 {
		nxp,kinetis-port-pins = < 3 1 >;
	};
	I2C0_SDA_PTB3: i2c0_sda_ptb3 {
		nxp,kinetis-port-pins = < 3 2 >;
	};
	TPM2_CH1_PTB3: tpm2_ch1_ptb3 {
		nxp,kinetis-port-pins = < 3 3 >;
	};
	PTB8: GPIOB_PTB8: gpiob_ptb8 {
		nxp,kinetis-port-pins = < 8 1 >;
	};
	EXTRG_IN_PTB8: extrg_in_ptb8 {
		nxp,kinetis-port-pins = < 8 3 >;
	};
	PTB9: GPIOB_PTB9: gpiob_ptb9 {
		nxp,kinetis-port-pins = < 9 1 >;
	};
	PTB10: GPIOB_PTB10: gpiob_ptb10 {
		nxp,kinetis-port-pins = < 10 1 >;
	};
	SPI1_PCS0_PTB10: spi1_pcs0_ptb10 {
		nxp,kinetis-port-pins = < 10 2 >;
	};
	PTB11: GPIOB_PTB11: gpiob_ptb11 {
		nxp,kinetis-port-pins = < 11 1 >;
	};
	SPI1_SCK_PTB11: spi1_sck_ptb11 {
		nxp,kinetis-port-pins = < 11 2 >;
	};
	TSI0_CH9_PTB16: tsi0_ch9_ptb16 {
		nxp,kinetis-port-pins = < 16 0 >;
	};
	PTB16: GPIOB_PTB16: gpiob_ptb16 {
		nxp,kinetis-port-pins = < 16 1 >;
	};
	SPI1_MOSI_PTB16: spi1_mosi_ptb16 {
		nxp,kinetis-port-pins = < 16 2 >;
	};
	UART0_RX_PTB16: uart0_rx_ptb16 {
		nxp,kinetis-port-pins = < 16 3 >;
	};
	TPM_CLKIN0_PTB16: tpm_clkin0_ptb16 {
		nxp,kinetis-port-pins = < 16 4 >;
	};
	SPI1_MISO_PTB16: spi1_miso_ptb16 {
		nxp,kinetis-port-pins = < 16 5 >;
	};
	TSI0_CH10_PTB17: tsi0_ch10_ptb17 {
		nxp,kinetis-port-pins = < 17 0 >;
	};
	PTB17: GPIOB_PTB17: gpiob_ptb17 {
		nxp,kinetis-port-pins = < 17 1 >;
	};
	SPI1_MISO_PTB17: spi1_miso_ptb17 {
		nxp,kinetis-port-pins = < 17 2 >;
	};
	UART0_TX_PTB17: uart0_tx_ptb17 {
		nxp,kinetis-port-pins = < 17 3 >;
	};
	TPM_CLKIN1_PTB17: tpm_clkin1_ptb17 {
		nxp,kinetis-port-pins = < 17 4 >;
	};
	SPI1_MOSI_PTB17: spi1_mosi_ptb17 {
		nxp,kinetis-port-pins = < 17 5 >;
	};
	TSI0_CH11_PTB18: tsi0_ch11_ptb18 {
		nxp,kinetis-port-pins = < 18 0 >;
	};
	PTB18: GPIOB_PTB18: gpiob_ptb18 {
		nxp,kinetis-port-pins = < 18 1 >;
	};
	TPM2_CH0_PTB18: tpm2_ch0_ptb18 {
		nxp,kinetis-port-pins = < 18 3 >;
	};
	TSI0_CH12_PTB19: tsi0_ch12_ptb19 {
		nxp,kinetis-port-pins = < 19 0 >;
	};
	PTB19: GPIOB_PTB19: gpiob_ptb19 {
		nxp,kinetis-port-pins = < 19 1 >;
	};
	TPM2_CH1_PTB19: tpm2_ch1_ptb19 {
		nxp,kinetis-port-pins = < 19 3 >;
	};
};

&portc {
	ADC0_SE14_PTC0: TSI0_CH13_PTC0: adc0_se14_ptc0 {
		nxp,kinetis-port-pins = < 0 0 >;
	};
	PTC0: GPIOC_PTC0: gpioc_ptc0 {
		nxp,kinetis-port-pins = < 0 1 >;
	};
	EXTRG_IN_PTC0: extrg_in_ptc0 {
		nxp,kinetis-port-pins = < 0 3 >;
	};
	CMP0_OUT_PTC0: cmp0_out_ptc0 {
		nxp,kinetis-port-pins = < 0 5 >;
	};
	ADC0_SE15_PTC1: TSI0_CH14_PTC1: adc0_se15_ptc1 {
		nxp,kinetis-port-pins = < 1 0 >;
	};
	PTC1: GPIOC_PTC1: LLWU_P6_PTC1: RTC_CLKIN_PTC1: gpioc_ptc1 {
		nxp,kinetis-port-pins = < 1 1 >;
	};
	I2C1_SCL_PTC1: i2c1_scl_ptc1 {
		nxp,kinetis-port-pins = < 1 2 >;
	};
	TPM0_CH0_PTC1: tpm0_ch0_ptc1 {
		nxp,kinetis-port-pins = < 1 4 >;
	};
	ADC0_SE11_PTC2: TSI0_CH15_PTC2: adc0_se11_ptc2 {
		nxp,kinetis-port-pins = < 2 0 >;
	};
	PTC2: GPIOC_PTC2: gpioc_ptc2 {
		nxp,kinetis-port-pins = < 2 1 >;
	};
	I2C1_SDA_PTC2: i2c1_sda_ptc2 {
		nxp,kinetis-port-pins = < 2 2 >;
	};
	TPM0_CH1_PTC2: tpm0_ch1_ptc2 {
		nxp,kinetis-port-pins = < 2 4 >;
	};
	PTC3: GPIOC_PTC3: LLWU_P7_PTC3: gpioc_ptc3 {
		nxp,kinetis-port-pins = < 3 1 >;
	};
	UART1_RX_PTC3: uart1_rx_ptc3 {
		nxp,kinetis-port-pins = < 3 3 >;
	};
	TPM0_CH2_PTC3: tpm0_ch2_ptc3 {
		nxp,kinetis-port-pins = < 3 4 >;
	};
	CLKOUTa_PTC3: clkouta_ptc3 {
		nxp,kinetis-port-pins = < 3 5 >;
	};
	PTC4: GPIOC_PTC4: LLWU_P8_PTC4: gpioc_ptc4 {
		nxp,kinetis-port-pins = < 4 1 >;
	};
	SPI0_PCS0_PTC4: spi0_pcs0_ptc4 {
		nxp,kinetis-port-pins = < 4 2 >;
	};
	UART1_TX_PTC4: uart1_tx_ptc4 {
		nxp,kinetis-port-pins = < 4 3 >;
	};
	TPM0_CH3_PTC4: tpm0_ch3_ptc4 {
		nxp,kinetis-port-pins = < 4 4 >;
	};
	PTC5: GPIOC_PTC5: LLWU_P9_PTC5: gpioc_ptc5 {
		nxp,kinetis-port-pins = < 5 1 >;
	};
	SPI0_SCK_PTC5: spi0_sck_ptc5 {
		nxp,kinetis-port-pins = < 5 2 >;
	};
	LPTMR0_ALT2_PTC5: lptmr0_alt2_ptc5 {
		nxp,kinetis-port-pins = < 5 3 >;
	};
	CMP0_OUT_PTC5: cmp0_out_ptc5 {
		nxp,kinetis-port-pins = < 5 6 >;
	};
	CMP0_IN0_PTC6: cmp0_in0_ptc6 {
		nxp,kinetis-port-pins = < 6 0 >;
	};
	PTC6: GPIOC_PTC6: LLWU_P10_PTC6: gpioc_ptc6 {
		nxp,kinetis-port-pins = < 6 1 >;
	};
	SPI0_MOSI_PTC6: spi0_mosi_ptc6 {
		nxp,kinetis-port-pins = < 6 2 >;
	};
	EXTRG_IN_PTC6: extrg_in_ptc6 {
		nxp,kinetis-port-pins = < 6 3 >;
	};
	SPI0_MISO_PTC6: spi0_miso_ptc6 {
		nxp,kinetis-port-pins = < 6 5 >;
	};
	CMP0_IN1_PTC7: cmp0_in1_ptc7 {
		nxp,kinetis-port-pins = < 7 0 >;
	};
	PTC7: GPIOC_PTC7: gpioc_ptc7 {
		nxp,kinetis-port-pins = < 7 1 >;
	};
	SPI0_MISO_PTC7: spi0_miso_ptc7 {
		nxp,kinetis-port-pins = < 7 2 >;
	};
	SPI0_MOSI_PTC7: spi0_mosi_ptc7 {
		nxp,kinetis-port-pins = < 7 5 >;
	};
	CMP0_IN2_PTC8: cmp0_in2_ptc8 {
		nxp,kinetis-port-pins = < 8 0 >;
	};
	PTC8: GPIOC_PTC8: gpioc_ptc8 {
		nxp,kinetis-port-pins = < 8 1 >;
	};
	I2C0_SCL_PTC8: i2c0_scl_ptc8 {
		nxp,kinetis-port-pins = < 8 2 >;
	};
	TPM0_CH4_PTC8: tpm0_ch4_ptc8 {
		nxp,kinetis-port-pins = < 8 3 >;
	};
	CMP0_IN3_PTC9: cmp0_in3_ptc9 {
		nxp,kinetis-port-pins = < 9 0 >;
	};
	PTC9: GPIOC_PTC9: gpioc_ptc9 {
		nxp,kinetis-port-pins = < 9 1 >;
	};
	I2C0_SDA_PTC9: i2c0_sda_ptc9 {
		nxp,kinetis-port-pins = < 9 2 >;
	};
	TPM0_CH5_PTC9: tpm0_ch5_ptc9 {
		nxp,kinetis-port-pins = < 9 3 >;
	};
	PTC10: GPIOC_PTC10: gpioc_ptc10 {
		nxp,kinetis-port-pins = < 10 1 >;
	};
	I2C1_SCL_PTC10: i2c1_scl_ptc10 {
		nxp,kinetis-port-pins = < 10 2 >;
	};
	PTC11: GPIOC_PTC11: gpioc_ptc11 {
		nxp,kinetis-port-pins = < 11 1 >;
	};
	I2C1_SDA_PTC11: i2c1_sda_ptc11 {
		nxp,kinetis-port-pins = < 11 2 >;
	};
	PTC12: GPIOC_PTC12: gpioc_ptc12 {
		nxp,kinetis-port-pins = < 12 1 >;
	};
	TPM_CLKIN0_PTC12: tpm_clkin0_ptc12 {
		nxp,kinetis-port-pins = < 12 4 >;
	};
	PTC13: GPIOC_PTC13: gpioc_ptc13 {
		nxp,kinetis-port-pins = < 13 1 >;
	};
	TPM_CLKIN1_PTC13: tpm_clkin1_ptc13 {
		nxp,kinetis-port-pins = < 13 4 >;
	};
	PTC16: GPIOC_PTC16: gpioc_ptc16 {
		nxp,kinetis-port-pins = < 16 1 >;
	};
	PTC17: GPIOC_PTC17: gpioc_ptc17 {
		nxp,kinetis-port-pins = < 17 1 >;
	};
};

&portd {
	PTD0: GPIOD_PTD0: gpiod_ptd0 {
		nxp,kinetis-port-pins = < 0 1 >;
	};
	SPI0_PCS0_PTD0: spi0_pcs0_ptd0 {
		nxp,kinetis-port-pins = < 0 2 >;
	};
	TPM0_CH0_PTD0: tpm0_ch0_ptd0 {
		nxp,kinetis-port-pins = < 0 4 >;
	};
	ADC0_SE5b_PTD1: adc0_se5b_ptd1 {
		nxp,kinetis-port-pins = < 1 0 >;
	};
	PTD1: GPIOD_PTD1: gpiod_ptd1 {
		nxp,kinetis-port-pins = < 1 1 >;
	};
	SPI0_SCK_PTD1: spi0_sck_ptd1 {
		nxp,kinetis-port-pins = < 1 2 >;
	};
	TPM0_CH1_PTD1: tpm0_ch1_ptd1 {
		nxp,kinetis-port-pins = < 1 4 >;
	};
	PTD2: GPIOD_PTD2: gpiod_ptd2 {
		nxp,kinetis-port-pins = < 2 1 >;
	};
	SPI0_MOSI_PTD2: spi0_mosi_ptd2 {
		nxp,kinetis-port-pins = < 2 2 >;
	};
	UART2_RX_PTD2: uart2_rx_ptd2 {
		nxp,kinetis-port-pins = < 2 3 >;
	};
	TPM0_CH2_PTD2: tpm0_ch2_ptd2 {
		nxp,kinetis-port-pins = < 2 4 >;
	};
	SPI0_MISO_PTD2: spi0_miso_ptd2 {
		nxp,kinetis-port-pins = < 2 5 >;
	};
	PTD3: GPIOD_PTD3: gpiod_ptd3 {
		nxp,kinetis-port-pins = < 3 1 >;
	};
	SPI0_MISO_PTD3: spi0_miso_ptd3 {
		nxp,kinetis-port-pins = < 3 2 >;
	};
	UART2_TX_PTD3: uart2_tx_ptd3 {
		nxp,kinetis-port-pins = < 3 3 >;
	};
	TPM0_CH3_PTD3: tpm0_ch3_ptd3 {
		nxp,kinetis-port-pins = < 3 4 >;
	};
	SPI0_MOSI_PTD3: spi0_mosi_ptd3 {
		nxp,kinetis-port-pins = < 3 5 >;
	};
	PTD4: GPIOD_PTD4: LLWU_P14_PTD4: gpiod_ptd4 {
		nxp,kinetis-port-pins = < 4 1 >;
	};
	SPI1_PCS0_PTD4: spi1_pcs0_ptd4 {
		nxp,kinetis-port-pins = < 4 2 >;
	};
	UART2_RX_PTD4: uart2_rx_ptd4 {
		nxp,kinetis-port-pins = < 4 3 >;
	};
	TPM0_CH4_PTD4: tpm0_ch4_ptd4 {
		nxp,kinetis-port-pins = < 4 4 >;
	};
	ADC0_SE6b_PTD5: adc0_se6b_ptd5 {
		nxp,kinetis-port-pins = < 5 0 >;
	};
	PTD5: GPIOD_PTD5: gpiod_ptd5 {
		nxp,kinetis-port-pins = < 5 1 >;
	};
	SPI1_SCK_PTD5: spi1_sck_ptd5 {
		nxp,kinetis-port-pins = < 5 2 >;
	};
	UART2_TX_PTD5: uart2_tx_ptd5 {
		nxp,kinetis-port-pins = < 5 3 >;
	};
	TPM0_CH5_PTD5: tpm0_ch5_ptd5 {
		nxp,kinetis-port-pins = < 5 4 >;
	};
	ADC0_SE7b_PTD6: adc0_se7b_ptd6 {
		nxp,kinetis-port-pins = < 6 0 >;
	};
	PTD6: GPIOD_PTD6: LLWU_P15_PTD6: gpiod_ptd6 {
		nxp,kinetis-port-pins = < 6 1 >;
	};
	SPI1_MOSI_PTD6: spi1_mosi_ptd6 {
		nxp,kinetis-port-pins = < 6 2 >;
	};
	UART0_RX_PTD6: uart0_rx_ptd6 {
		nxp,kinetis-port-pins = < 6 3 >;
	};
	SPI1_MISO_PTD6: spi1_miso_ptd6 {
		nxp,kinetis-port-pins = < 6 5 >;
	};
	PTD7: GPIOD_PTD7: gpiod_ptd7 {
		nxp,kinetis-port-pins = < 7 1 >;
	};
	SPI1_MISO_PTD7: spi1_miso_ptd7 {
		nxp,kinetis-port-pins = < 7 2 >;
	};
	UART0_TX_PTD7: uart0_tx_ptd7 {
		nxp,kinetis-port-pins = < 7 3 >;
	};
	SPI1_MOSI_PTD7: spi1_mosi_ptd7 {
		nxp,kinetis-port-pins = < 7 5 >;
	};
};

&porte {
	PTE0: GPIOE_PTE0: gpioe_pte0 {
		nxp,kinetis-port-pins = < 0 1 >;
	};
	UART1_TX_PTE0: uart1_tx_pte0 {
		nxp,kinetis-port-pins = < 0 3 >;
	};
	RTC_CLKOUT_PTE0: rtc_clkout_pte0 {
		nxp,kinetis-port-pins = < 0 4 >;
	};
	CMP0_OUT_PTE0: cmp0_out_pte0 {
		nxp,kinetis-port-pins = < 0 5 >;
	};
	I2C1_SDA_PTE0: i2c1_sda_pte0 {
		nxp,kinetis-port-pins = < 0 6 >;
	};
	PTE1: GPIOE_PTE1: gpioe_pte1 {
		nxp,kinetis-port-pins = < 1 1 >;
	};
	SPI1_MOSI_PTE1: spi1_mosi_pte1 {
		nxp,kinetis-port-pins = < 1 2 >;
	};
	UART1_RX_PTE1: uart1_rx_pte1 {
		nxp,kinetis-port-pins = < 1 3 >;
	};
	SPI1_MISO_PTE1: spi1_miso_pte1 {
		nxp,kinetis-port-pins = < 1 5 >;
	};
	I2C1_SCL_PTE1: i2c1_scl_pte1 {
		nxp,kinetis-port-pins = < 1 6 >;
	};
	PTE2: GPIOE_PTE2: gpioe_pte2 {
		nxp,kinetis-port-pins = < 2 1 >;
	};
	SPI1_SCK_PTE2: spi1_sck_pte2 {
		nxp,kinetis-port-pins = < 2 2 >;
	};
	PTE3: GPIOE_PTE3: gpioe_pte3 {
		nxp,kinetis-port-pins = < 3 1 >;
	};
	SPI1_MISO_PTE3: spi1_miso_pte3 {
		nxp,kinetis-port-pins = < 3 2 >;
	};
	SPI1_MOSI_PTE3: spi1_mosi_pte3 {
		nxp,kinetis-port-pins = < 3 5 >;
	};
	PTE4: GPIOE_PTE4: gpioe_pte4 {
		nxp,kinetis-port-pins = < 4 1 >;
	};
	SPI1_PCS0_PTE4: spi1_pcs0_pte4 {
		nxp,kinetis-port-pins = < 4 2 >;
	};
	PTE5: GPIOE_PTE5: gpioe_pte5 {
		nxp,kinetis-port-pins = < 5 1 >;
	};
	ADC0_DP0_PTE20: ADC0_SE0_PTE20: adc0_dp0_pte20 {
		nxp,kinetis-port-pins = < 20 0 >;
	};
	PTE20: GPIOE_PTE20: gpioe_pte20 {
		nxp,kinetis-port-pins = < 20 1 >;
	};
	TPM1_CH0_PTE20: tpm1_ch0_pte20 {
		nxp,kinetis-port-pins = < 20 3 >;
	};
	UART0_TX_PTE20: uart0_tx_pte20 {
		nxp,kinetis-port-pins = < 20 4 >;
	};
	ADC0_DM0_PTE21: ADC0_SE4a_PTE21: adc0_dm0_pte21 {
		nxp,kinetis-port-pins = < 21 0 >;
	};
	PTE21: GPIOE_PTE21: gpioe_pte21 {
		nxp,kinetis-port-pins = < 21 1 >;
	};
	TPM1_CH1_PTE21: tpm1_ch1_pte21 {
		nxp,kinetis-port-pins = < 21 3 >;
	};
	UART0_RX_PTE21: uart0_rx_pte21 {
		nxp,kinetis-port-pins = < 21 4 >;
	};
	ADC0_DP3_PTE22: ADC0_SE3_PTE22: adc0_dp3_pte22 {
		nxp,kinetis-port-pins = < 22 0 >;
	};
	PTE22: GPIOE_PTE22: gpioe_pte22 {
		nxp,kinetis-port-pins = < 22 1 >;
	};
	TPM2_CH0_PTE22: tpm2_ch0_pte22 {
		nxp,kinetis-port-pins = < 22 3 >;
	};
	UART2_TX_PTE22: uart2_tx_pte22 {
		nxp,kinetis-port-pins = < 22 4 >;
	};
	ADC0_DM3_PTE23: ADC0_SE7a_PTE23: adc0_dm3_pte23 {
		nxp,kinetis-port-pins = < 23 0 >;
	};
	PTE23: GPIOE_PTE23: gpioe_pte23 {
		nxp,kinetis-port-pins = < 23 1 >;
	};
	TPM2_CH1_PTE23: tpm2_ch1_pte23 {
		nxp,kinetis-port-pins = < 23 3 >;
	};
	UART2_RX_PTE23: uart2_rx_pte23 {
		nxp,kinetis-port-pins = < 23 4 >;
	};
	PTE24: GPIOE_PTE24: gpioe_pte24 {
		nxp,kinetis-port-pins = < 24 1 >;
	};
	TPM0_CH0_PTE24: tpm0_ch0_pte24 {
		nxp,kinetis-port-pins = < 24 3 >;
	};
	I2C0_SCL_PTE24: i2c0_scl_pte24 {
		nxp,kinetis-port-pins = < 24 5 >;
	};
	PTE25: GPIOE_PTE25: gpioe_pte25 {
		nxp,kinetis-port-pins = < 25 1 >;
	};
	TPM0_CH1_PTE25: tpm0_ch1_pte25 {
		nxp,kinetis-port-pins = < 25 3 >;
	};
	I2C0_SDA_PTE25: i2c0_sda_pte25 {
		nxp,kinetis-port-pins = < 25 5 >;
	};
	CMP0_IN5_PTE29: ADC0_SE4b_PTE29: cmp0_in5_pte29 {
		nxp,kinetis-port-pins = < 29 0 >;
	};
	PTE29: GPIOE_PTE29: gpioe_pte29 {
		nxp,kinetis-port-pins = < 29 1 >;
	};
	TPM0_CH2_PTE29: tpm0_ch2_pte29 {
		nxp,kinetis-port-pins = < 29 3 >;
	};
	TPM_CLKIN0_PTE29: tpm_clkin0_pte29 {
		nxp,kinetis-port-pins = < 29 4 >;
	};
	DAC0_OUT_PTE30: ADC0_SE23_PTE30: CMP0_IN4_PTE30: dac0_out_pte30 {
		nxp,kinetis-port-pins = < 30 0 >;
	};
	PTE30: GPIOE_PTE30: gpioe_pte30 {
		nxp,kinetis-port-pins = < 30 1 >;
	};
	TPM0_CH3_PTE30: tpm0_ch3_pte30 {
		nxp,kinetis-port-pins = < 30 3 >;
	};
	TPM_CLKIN1_PTE30: tpm_clkin1_pte30 {
		nxp,kinetis-port-pins = < 30 4 >;
	};
	PTE31: GPIOE_PTE31: gpioe_pte31 {
		nxp,kinetis-port-pins = < 31 1 >;
	};
	TPM0_CH4_PTE31: tpm0_ch4_pte31 {
		nxp,kinetis-port-pins = < 31 3 >;
	};
};