1<?xml version="1.0" encoding="utf-8"?>
2<device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd">
3  <vendor>Cypress Semiconductor</vendor>
4  <vendorID>Cypress</vendorID>
5  <name>fx3g2</name>
6  <series>fx3g2</series>
7  <version>1.0</version>
8  <description>FX3G2</description>
9  <licenseText>(c) (2016-2021), Cypress Semiconductor Corporation (an Infineon company)\n
10    or an affiliate of Cypress Semiconductor Corporation.\n
11\n
12    SPDX-License-Identifier: Apache-2.0\n
13\n
14    Licensed under the Apache License, Version 2.0 (the "License");\n
15    you may not use this file except in compliance with the License.\n
16    You may obtain a copy of the License at\n
17\n
18      http://www.apache.org/licenses/LICENSE-2.0\n
19\n
20    Unless required by applicable law or agreed to in writing, software\n
21    distributed under the License is distributed on an "AS IS" BASIS,\n
22    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n
23    See the License for the specific language governing permissions and\n
24    limitations under the License.</licenseText>
25  <cpu>
26    <name>CM4</name>
27    <revision>r0p1</revision>
28    <endian>little</endian>
29    <mpuPresent>true</mpuPresent>
30    <fpuPresent>true</fpuPresent>
31    <vtorPresent>1</vtorPresent>
32    <nvicPrioBits>3</nvicPrioBits>
33    <vendorSystickConfig>0</vendorSystickConfig>
34  </cpu>
35  <addressUnitBits>8</addressUnitBits>
36  <width>32</width>
37  <resetValue>0x00000000</resetValue>
38  <resetMask>0xFFFFFFFF</resetMask>
39  <peripherals>
40    <peripheral>
41      <name>PERI</name>
42      <description>Peripheral interconnect</description>
43      <baseAddress>0x40000000</baseAddress>
44      <addressBlock>
45        <offset>0</offset>
46        <size>65536</size>
47        <usage>registers</usage>
48      </addressBlock>
49      <registers>
50        <register>
51          <name>TIMEOUT_CTL</name>
52          <description>Timeout control</description>
53          <addressOffset>0x200</addressOffset>
54          <size>32</size>
55          <access>read-write</access>
56          <resetValue>0xFFFF</resetValue>
57          <resetMask>0xFFFF</resetMask>
58          <fields>
59            <field>
60              <name>TIMEOUT</name>
61              <description>This field specifies a number of clock cycles (clk_slow). If an AHB-Lite bus transfer takes more than the specified number of cycles (timeout detection), the bus transfer is terminated with an AHB-Lite bus error and a fault is generated (and possibly recorded in the fault report structure(s)).
62'0x0000'-'0xfffe': Number of clock cycles.
63'0xffff': This value is the default/reset value and specifies that no timeout detection is performed: a bus transfer will never be terminated and a fault will never be generated.</description>
64              <bitRange>[15:0]</bitRange>
65              <access>read-write</access>
66            </field>
67          </fields>
68        </register>
69        <register>
70          <name>TR_CMD</name>
71          <description>Trigger command</description>
72          <addressOffset>0x220</addressOffset>
73          <size>32</size>
74          <access>read-write</access>
75          <resetValue>0x0</resetValue>
76          <resetMask>0xE0001FFF</resetMask>
77          <fields>
78            <field>
79              <name>TR_SEL</name>
80              <description>Specifies the activated trigger when ACTIVATE is '1'. If the specified trigger is not present, the trigger activation has no effect.</description>
81              <bitRange>[7:0]</bitRange>
82              <access>read-write</access>
83            </field>
84            <field>
85              <name>GROUP_SEL</name>
86              <description>Specifies the trigger group:
87'0'-'15': trigger multiplexer groups.
88'16'-'31': trigger 1-to-1 groups.</description>
89              <bitRange>[12:8]</bitRange>
90              <access>read-write</access>
91            </field>
92            <field>
93              <name>TR_EDGE</name>
94              <description>Specifies if the activated  trigger is treated as a level sensitive or edge sensitive  trigger.
95'0': level sensitive. The trigger reflects TR_CMD.ACTIVATE.
96'1': edge sensitive trigger. The trigger is activated for two clk_peri cycles.</description>
97              <bitRange>[29:29]</bitRange>
98              <access>read-write</access>
99            </field>
100            <field>
101              <name>OUT_SEL</name>
102              <description>Specifies whether trigger activation is for a specific input or output trigger of the trigger multiplexer. Activation of a specific input trigger, will result in activation of all output triggers that have the specific input trigger selected through their TR_OUT_CTL.TR_SEL  field. Activation of a specific output trigger, will result in activation of the specified TR_SEL output trigger only.
103'0': TR_SEL selection and trigger activation is for an input trigger to the trigger multiplexer.
104'1': TR_SEL selection and trigger activation is for an output trigger from the trigger multiplexer.
105
106Note: this field is not used for trigger 1-to-1 groups.</description>
107              <bitRange>[30:30]</bitRange>
108              <access>read-write</access>
109            </field>
110            <field>
111              <name>ACTIVATE</name>
112              <description>SW sets this field to '1' to activate (set to '1') a trigger as identified by TR_SEL, TR_EDGE and OUT_SEL. HW sets this field to '0' for edge sensitive triggers AFTER the selected trigger is activated for two clk_peri cycles.
113
114Note: when ACTIVATE is '1', SW should not modify the other register fields.
115SW MUST NOT set ACTIVATE bit to '1' while updating the other register bits simultaneously. At first the SW MUST update the other register bits as needed, and then set ACTIVATE to '1' with a new register write.</description>
116              <bitRange>[31:31]</bitRange>
117              <access>read-write</access>
118            </field>
119          </fields>
120        </register>
121        <register>
122          <name>DIV_CMD</name>
123          <description>Divider command</description>
124          <addressOffset>0x400</addressOffset>
125          <size>32</size>
126          <access>read-write</access>
127          <resetValue>0x3FF03FF</resetValue>
128          <resetMask>0xC3FF03FF</resetMask>
129          <fields>
130            <field>
131              <name>DIV_SEL</name>
132              <description>(TYPE_SEL, DIV_SEL) specifies the divider on which the command (DISABLE/ENABLE) is performed.
133
134If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock signal(s) are generated.</description>
135              <bitRange>[7:0]</bitRange>
136              <access>read-write</access>
137            </field>
138            <field>
139              <name>TYPE_SEL</name>
140              <description>Specifies the divider type of the divider on which the command is performed:
1410: 8.0 (integer) clock dividers.
1421: 16.0 (integer) clock dividers.
1432: 16.5 (fractional) clock dividers.
1443: 24.5 (fractional) clock dividers.</description>
145              <bitRange>[9:8]</bitRange>
146              <access>read-write</access>
147            </field>
148            <field>
149              <name>PA_DIV_SEL</name>
150              <description>(PA_TYPE_SEL, PA_DIV_SEL) specifies the divider to which phase alignment is performed for the clock enable command. Any enabled divider can be used as reference. This allows all dividers to be aligned with each other, even when they are enabled at different times.
151
152If PA_DIV_SEL is '255' and PA_TYPE_SEL is '3', 'clk_peri' is used as reference.</description>
153              <bitRange>[23:16]</bitRange>
154              <access>read-write</access>
155            </field>
156            <field>
157              <name>PA_TYPE_SEL</name>
158              <description>Specifies the divider type of the divider to which phase alignment is performed for the clock enable command:
1590: 8.0 (integer) clock dividers.
1601: 16.0 (integer) clock dividers.
1612: 16.5 (fractional) clock dividers.
1623: 24.5 (fractional) clock dividers.</description>
163              <bitRange>[25:24]</bitRange>
164              <access>read-write</access>
165            </field>
166            <field>
167              <name>DISABLE</name>
168              <description>Clock divider disable command (mutually exclusive with ENABLE). SW sets this field to '1' and HW sets this field to '0'.
169
170The DIV_SEL and TYPE_SEL fields specify which divider is to be disabled.
171
172The HW sets the DISABLE field to '0' immediately and the HW sets the DIV_XXX_CTL.EN field of the divider to '0' immediately.</description>
173              <bitRange>[30:30]</bitRange>
174              <access>read-write</access>
175            </field>
176            <field>
177              <name>ENABLE</name>
178              <description>Clock divider enable command (mutually exclusive with DISABLE). Typically, SW sets this field to '1' to enable a divider and HW sets this field to '0' to indicate that divider enabling has completed. When a divider is enabled, its integer and fractional (if present) counters are initialized to '0'. If a divider is to be re-enabled using different integer and fractional divider values, the SW should follow these steps:
1790: Disable the divider using the DIV_CMD.DISABLE field.
1801: Configure the divider's DIV_XXX_CTL register.
1812: Enable the divider using the DIV_CMD_ENABLE field.
182
183The DIV_SEL and TYPE_SEL fields specify which divider is to be enabled. The enabled divider may be phase aligned to either 'clk_peri' (typical usage) or to ANY enabled divider.
184
185The PA_DIV_SEL and PA_TYPE_SEL fields specify the reference divider.
186
187The HW sets the ENABLE field to '0' when the enabling is performed and the HW set the DIV_XXX_CTL.EN field of the divider to '1' when the enabling is performed. Note that enabling with phase alignment to a low frequency divider takes time. E.g. To align to a divider that generates a clock of 'clk_peri'/n (with n being the integer divider value INT_DIV+1), up to n cycles may be required to perform alignment. Phase alignment to 'clk_peri' takes affect immediately. SW can set this field to '0' during phase alignment to abort the enabling process.</description>
188              <bitRange>[31:31]</bitRange>
189              <access>read-write</access>
190            </field>
191          </fields>
192        </register>
193        <register>
194          <dim>256</dim>
195          <dimIncrement>4</dimIncrement>
196          <name>CLOCK_CTL[%s]</name>
197          <description>Clock control</description>
198          <addressOffset>0xC00</addressOffset>
199          <size>32</size>
200          <access>read-write</access>
201          <resetValue>0x3FF</resetValue>
202          <resetMask>0x3FF</resetMask>
203          <fields>
204            <field>
205              <name>DIV_SEL</name>
206              <description>Specifies one of the dividers of the divider type specified by TYPE_SEL.
207
208If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated.
209
210When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.</description>
211              <bitRange>[7:0]</bitRange>
212              <access>read-write</access>
213            </field>
214            <field>
215              <name>TYPE_SEL</name>
216              <description>Specifies divider type:
2170: 8.0 (integer) clock dividers.
2181: 16.0 (integer) clock dividers.
2192: 16.5 (fractional) clock dividers.
2203: 24.5 (fractional) clock dividers.</description>
221              <bitRange>[9:8]</bitRange>
222              <access>read-write</access>
223            </field>
224          </fields>
225        </register>
226        <register>
227          <dim>256</dim>
228          <dimIncrement>4</dimIncrement>
229          <name>DIV_8_CTL[%s]</name>
230          <description>Divider control (for 8.0 divider)</description>
231          <addressOffset>0x1000</addressOffset>
232          <size>32</size>
233          <access>read-write</access>
234          <resetValue>0x0</resetValue>
235          <resetMask>0xFF01</resetMask>
236          <fields>
237            <field>
238              <name>EN</name>
239              <description>Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command.
240
241Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.</description>
242              <bitRange>[0:0]</bitRange>
243              <access>read-only</access>
244            </field>
245            <field>
246              <name>INT8_DIV</name>
247              <description>Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division.
248
249For the generation of a divided clock, the integer division range is restricted to [2, 256].
250
251For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50  percent duty cycle analog divided clock has no restrictions.
252
253Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.</description>
254              <bitRange>[15:8]</bitRange>
255              <access>read-write</access>
256            </field>
257          </fields>
258        </register>
259        <register>
260          <dim>256</dim>
261          <dimIncrement>4</dimIncrement>
262          <name>DIV_16_CTL[%s]</name>
263          <description>Divider control (for 16.0 divider)</description>
264          <addressOffset>0x1400</addressOffset>
265          <size>32</size>
266          <access>read-write</access>
267          <resetValue>0x0</resetValue>
268          <resetMask>0xFFFF01</resetMask>
269          <fields>
270            <field>
271              <name>EN</name>
272              <description>Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command.
273
274Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.</description>
275              <bitRange>[0:0]</bitRange>
276              <access>read-only</access>
277            </field>
278            <field>
279              <name>INT16_DIV</name>
280              <description>Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division.
281
282For the generation of a divided clock, the integer division range is restricted to [2, 65,536].
283
284For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50  percent duty cycle analog divided clock has no restrictions.
285
286Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.</description>
287              <bitRange>[23:8]</bitRange>
288              <access>read-write</access>
289            </field>
290          </fields>
291        </register>
292        <register>
293          <dim>256</dim>
294          <dimIncrement>4</dimIncrement>
295          <name>DIV_16_5_CTL[%s]</name>
296          <description>Divider control (for 16.5 divider)</description>
297          <addressOffset>0x1800</addressOffset>
298          <size>32</size>
299          <access>read-write</access>
300          <resetValue>0x0</resetValue>
301          <resetMask>0xFFFFF9</resetMask>
302          <fields>
303            <field>
304              <name>EN</name>
305              <description>Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command.
306
307Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.</description>
308              <bitRange>[0:0]</bitRange>
309              <access>read-only</access>
310            </field>
311            <field>
312              <name>FRAC5_DIV</name>
313              <description>Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods.
314
315Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.</description>
316              <bitRange>[7:3]</bitRange>
317              <access>read-write</access>
318            </field>
319            <field>
320              <name>INT16_DIV</name>
321              <description>Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments.
322
323For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32].
324
325For the generation of a 50/50 percent duty cycle divided clock, the  division range is restricted to [2, 65,536].
326
327Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.</description>
328              <bitRange>[23:8]</bitRange>
329              <access>read-write</access>
330            </field>
331          </fields>
332        </register>
333        <register>
334          <dim>255</dim>
335          <dimIncrement>4</dimIncrement>
336          <name>DIV_24_5_CTL[%s]</name>
337          <description>Divider control (for 24.5 divider)</description>
338          <addressOffset>0x1C00</addressOffset>
339          <size>32</size>
340          <access>read-write</access>
341          <resetValue>0x0</resetValue>
342          <resetMask>0xFFFFFFF9</resetMask>
343          <fields>
344            <field>
345              <name>EN</name>
346              <description>Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command.
347
348Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.</description>
349              <bitRange>[0:0]</bitRange>
350              <access>read-only</access>
351            </field>
352            <field>
353              <name>FRAC5_DIV</name>
354              <description>Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods.
355
356Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.</description>
357              <bitRange>[7:3]</bitRange>
358              <access>read-write</access>
359            </field>
360            <field>
361              <name>INT24_DIV</name>
362              <description>Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments.
363
364For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32].
365
366For the generation of a 50/50 percent duty cycle divided clock, the  division range is restricted to [2, 16,777,216].
367
368Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.</description>
369              <bitRange>[31:8]</bitRange>
370              <access>read-write</access>
371            </field>
372          </fields>
373        </register>
374        <register>
375          <name>ECC_CTL</name>
376          <description>ECC control</description>
377          <addressOffset>0x2000</addressOffset>
378          <size>32</size>
379          <access>read-write</access>
380          <resetValue>0x10000</resetValue>
381          <resetMask>0xFF0507FF</resetMask>
382          <fields>
383            <field>
384              <name>WORD_ADDR</name>
385              <description>Specifies the word address where the parity is injected.
386- On a 32-bit write access to this SRAM address and when ECC_INJ_EN bit is '1', the parity (PARITY) is injected.</description>
387              <bitRange>[10:0]</bitRange>
388              <access>read-write</access>
389            </field>
390            <field>
391              <name>ECC_EN</name>
392              <description>Enable ECC checking:
393'0': Disabled.
394'1': Enabled.</description>
395              <bitRange>[16:16]</bitRange>
396              <access>read-write</access>
397            </field>
398            <field>
399              <name>ECC_INJ_EN</name>
400              <description>Enable error injection for PERI protection structure SRAM.
401When '1', the parity (PARITY) is used when a write is done to the WORD_ADDR word address of the SRAM.</description>
402              <bitRange>[18:18]</bitRange>
403              <access>read-write</access>
404            </field>
405            <field>
406              <name>PARITY</name>
407              <description>ECC parity to use for ECC error injection at address WORD_ADDR.</description>
408              <bitRange>[31:24]</bitRange>
409              <access>read-write</access>
410            </field>
411          </fields>
412        </register>
413        <cluster>
414          <dim>6</dim>
415          <dimIncrement>32</dimIncrement>
416          <name>GR[%s]</name>
417          <description>Peripheral group structure</description>
418          <addressOffset>0x00004000</addressOffset>
419          <register>
420            <name>CLOCK_CTL</name>
421            <description>Clock control</description>
422            <addressOffset>0x0</addressOffset>
423            <size>32</size>
424            <access>read-write</access>
425            <resetValue>0x0</resetValue>
426            <resetMask>0xFF00</resetMask>
427            <fields>
428              <field>
429                <name>INT8_DIV</name>
430                <description>Specifies a group clock divider (from the peripheral clock 'clk_peri' to the group clock 'clk_group[3/4/5/...15]'). Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256].
431
432Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.</description>
433                <bitRange>[15:8]</bitRange>
434                <access>read-write</access>
435              </field>
436            </fields>
437          </register>
438          <register>
439            <name>SL_CTL</name>
440            <description>Slave control</description>
441            <addressOffset>0x10</addressOffset>
442            <size>32</size>
443            <access>read-write</access>
444            <resetValue>0xFFFF</resetValue>
445            <resetMask>0xFFFFFFFF</resetMask>
446            <fields>
447              <field>
448                <name>ENABLED_0</name>
449                <description>Peripheral group, slave 0 enable. If the slave is disabled, its clock is gated off (constant '0') and its resets are activated.
450
451Note: For peripheral group 0 (the peripheral interconnect MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled.</description>
452                <bitRange>[0:0]</bitRange>
453                <access>read-write</access>
454              </field>
455              <field>
456                <name>ENABLED_1</name>
457                <description>Peripheral group, slave 1 enable. If the slave is disabled, its clock is gated off (constant '0') and its resets are activated.
458
459Note: For peripheral group 0 (the peripheral interconnect, master interface MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled.</description>
460                <bitRange>[1:1]</bitRange>
461                <access>read-write</access>
462              </field>
463              <field>
464                <name>ENABLED_2</name>
465                <description>N/A</description>
466                <bitRange>[2:2]</bitRange>
467                <access>read-write</access>
468              </field>
469              <field>
470                <name>ENABLED_3</name>
471                <description>N/A</description>
472                <bitRange>[3:3]</bitRange>
473                <access>read-write</access>
474              </field>
475              <field>
476                <name>ENABLED_4</name>
477                <description>N/A</description>
478                <bitRange>[4:4]</bitRange>
479                <access>read-write</access>
480              </field>
481              <field>
482                <name>ENABLED_5</name>
483                <description>N/A</description>
484                <bitRange>[5:5]</bitRange>
485                <access>read-write</access>
486              </field>
487              <field>
488                <name>ENABLED_6</name>
489                <description>N/A</description>
490                <bitRange>[6:6]</bitRange>
491                <access>read-write</access>
492              </field>
493              <field>
494                <name>ENABLED_7</name>
495                <description>N/A</description>
496                <bitRange>[7:7]</bitRange>
497                <access>read-write</access>
498              </field>
499              <field>
500                <name>ENABLED_8</name>
501                <description>N/A</description>
502                <bitRange>[8:8]</bitRange>
503                <access>read-write</access>
504              </field>
505              <field>
506                <name>ENABLED_9</name>
507                <description>N/A</description>
508                <bitRange>[9:9]</bitRange>
509                <access>read-write</access>
510              </field>
511              <field>
512                <name>ENABLED_10</name>
513                <description>N/A</description>
514                <bitRange>[10:10]</bitRange>
515                <access>read-write</access>
516              </field>
517              <field>
518                <name>ENABLED_11</name>
519                <description>N/A</description>
520                <bitRange>[11:11]</bitRange>
521                <access>read-write</access>
522              </field>
523              <field>
524                <name>ENABLED_12</name>
525                <description>N/A</description>
526                <bitRange>[12:12]</bitRange>
527                <access>read-write</access>
528              </field>
529              <field>
530                <name>ENABLED_13</name>
531                <description>N/A</description>
532                <bitRange>[13:13]</bitRange>
533                <access>read-write</access>
534              </field>
535              <field>
536                <name>ENABLED_14</name>
537                <description>N/A</description>
538                <bitRange>[14:14]</bitRange>
539                <access>read-write</access>
540              </field>
541              <field>
542                <name>ENABLED_15</name>
543                <description>N/A</description>
544                <bitRange>[15:15]</bitRange>
545                <access>read-write</access>
546              </field>
547              <field>
548                <name>DISABLED_0</name>
549                <description>Peripheral group, slave 0 permanent disable. Setting this bit to 1 has the same effect as setting ENABLED_0 to 0.  However, once set to 1, this bit cannot be changed back to 0 anymore.</description>
550                <bitRange>[16:16]</bitRange>
551                <access>read-write</access>
552              </field>
553              <field>
554                <name>DISABLED_1</name>
555                <description>N/A</description>
556                <bitRange>[17:17]</bitRange>
557                <access>read-write</access>
558              </field>
559              <field>
560                <name>DISABLED_2</name>
561                <description>N/A</description>
562                <bitRange>[18:18]</bitRange>
563                <access>read-write</access>
564              </field>
565              <field>
566                <name>DISABLED_3</name>
567                <description>N/A</description>
568                <bitRange>[19:19]</bitRange>
569                <access>read-write</access>
570              </field>
571              <field>
572                <name>DISABLED_4</name>
573                <description>N/A</description>
574                <bitRange>[20:20]</bitRange>
575                <access>read-write</access>
576              </field>
577              <field>
578                <name>DISABLED_5</name>
579                <description>N/A</description>
580                <bitRange>[21:21]</bitRange>
581                <access>read-write</access>
582              </field>
583              <field>
584                <name>DISABLED_6</name>
585                <description>N/A</description>
586                <bitRange>[22:22]</bitRange>
587                <access>read-write</access>
588              </field>
589              <field>
590                <name>DISABLED_7</name>
591                <description>N/A</description>
592                <bitRange>[23:23]</bitRange>
593                <access>read-write</access>
594              </field>
595              <field>
596                <name>DISABLED_8</name>
597                <description>N/A</description>
598                <bitRange>[24:24]</bitRange>
599                <access>read-write</access>
600              </field>
601              <field>
602                <name>DISABLED_9</name>
603                <description>N/A</description>
604                <bitRange>[25:25]</bitRange>
605                <access>read-write</access>
606              </field>
607              <field>
608                <name>DISABLED_10</name>
609                <description>N/A</description>
610                <bitRange>[26:26]</bitRange>
611                <access>read-write</access>
612              </field>
613              <field>
614                <name>DISABLED_11</name>
615                <description>N/A</description>
616                <bitRange>[27:27]</bitRange>
617                <access>read-write</access>
618              </field>
619              <field>
620                <name>DISABLED_12</name>
621                <description>N/A</description>
622                <bitRange>[28:28]</bitRange>
623                <access>read-write</access>
624              </field>
625              <field>
626                <name>DISABLED_13</name>
627                <description>N/A</description>
628                <bitRange>[29:29]</bitRange>
629                <access>read-write</access>
630              </field>
631              <field>
632                <name>DISABLED_14</name>
633                <description>N/A</description>
634                <bitRange>[30:30]</bitRange>
635                <access>read-write</access>
636              </field>
637              <field>
638                <name>DISABLED_15</name>
639                <description>N/A</description>
640                <bitRange>[31:31]</bitRange>
641                <access>read-write</access>
642              </field>
643            </fields>
644          </register>
645        </cluster>
646        <cluster>
647          <dim>13</dim>
648          <dimIncrement>1024</dimIncrement>
649          <name>TR_GR[%s]</name>
650          <description>Trigger group</description>
651          <addressOffset>0x00008000</addressOffset>
652          <register>
653            <dim>256</dim>
654            <dimIncrement>4</dimIncrement>
655            <name>TR_CTL[%s]</name>
656            <description>Trigger control register</description>
657            <addressOffset>0x0</addressOffset>
658            <size>32</size>
659            <access>read-write</access>
660            <resetValue>0x0</resetValue>
661            <resetMask>0x13FF</resetMask>
662            <fields>
663              <field>
664                <name>TR_SEL</name>
665                <description>Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.</description>
666                <bitRange>[7:0]</bitRange>
667                <access>read-write</access>
668              </field>
669              <field>
670                <name>TR_INV</name>
671                <description>Specifies if the output trigger is inverted.</description>
672                <bitRange>[8:8]</bitRange>
673                <access>read-write</access>
674              </field>
675              <field>
676                <name>TR_EDGE</name>
677                <description>Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive  trigger.
678'0': level sensitive.
679'1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.</description>
680                <bitRange>[9:9]</bitRange>
681                <access>read-write</access>
682              </field>
683              <field>
684                <name>DBG_FREEZE_EN</name>
685                <description>Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation.</description>
686                <bitRange>[12:12]</bitRange>
687                <access>read-write</access>
688              </field>
689            </fields>
690          </register>
691        </cluster>
692        <cluster>
693          <dim>6</dim>
694          <dimIncrement>1024</dimIncrement>
695          <name>TR_1TO1_GR[%s]</name>
696          <description>Trigger 1-to-1 group</description>
697          <addressOffset>0x0000C000</addressOffset>
698          <register>
699            <dim>256</dim>
700            <dimIncrement>4</dimIncrement>
701            <name>TR_CTL[%s]</name>
702            <description>Trigger control register</description>
703            <addressOffset>0x0</addressOffset>
704            <size>32</size>
705            <access>read-write</access>
706            <resetValue>0x0</resetValue>
707            <resetMask>0x1301</resetMask>
708            <fields>
709              <field>
710                <name>TR_SEL</name>
711                <description>Specifies input trigger:
712'0'': constant signal level '0'.
713'1': input trigger.</description>
714                <bitRange>[0:0]</bitRange>
715                <access>read-write</access>
716              </field>
717              <field>
718                <name>TR_INV</name>
719                <description>Specifies if the output trigger is inverted.</description>
720                <bitRange>[8:8]</bitRange>
721                <access>read-write</access>
722              </field>
723              <field>
724                <name>TR_EDGE</name>
725                <description>Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive  trigger.
726'0': level sensitive.
727'1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.</description>
728                <bitRange>[9:9]</bitRange>
729                <access>read-write</access>
730              </field>
731              <field>
732                <name>DBG_FREEZE_EN</name>
733                <description>Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation.</description>
734                <bitRange>[12:12]</bitRange>
735                <access>read-write</access>
736              </field>
737            </fields>
738          </register>
739        </cluster>
740      </registers>
741    </peripheral>
742    <peripheral>
743      <name>PERI_MS</name>
744      <description>Peripheral interconnect, master interface</description>
745      <baseAddress>0x40010000</baseAddress>
746      <addressBlock>
747        <offset>0</offset>
748        <size>65536</size>
749        <usage>registers</usage>
750      </addressBlock>
751      <registers>
752        <cluster>
753          <dim>8</dim>
754          <dimIncrement>64</dimIncrement>
755          <name>PPU_PR[%s]</name>
756          <description>Programmable protection structure pair</description>
757          <addressOffset>0x00000000</addressOffset>
758          <register>
759            <name>SL_ADDR</name>
760            <description>Slave region, base address</description>
761            <addressOffset>0x0</addressOffset>
762            <size>32</size>
763            <access>read-write</access>
764            <resetValue>0x0</resetValue>
765            <resetMask>0x0</resetMask>
766            <fields>
767              <field>
768                <name>ADDR30</name>
769                <description>This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore, some of the lesser significant address bits of ADDR30 must be '0's. E.g., a 64 KB address region (REGION_SIZE is '15') must be 64 KByte aligned, and ADDR30[13:0] must be '0's.</description>
770                <bitRange>[31:2]</bitRange>
771                <access>read-write</access>
772              </field>
773            </fields>
774          </register>
775          <register>
776            <name>SL_SIZE</name>
777            <description>Slave region, size</description>
778            <addressOffset>0x4</addressOffset>
779            <size>32</size>
780            <access>read-write</access>
781            <resetValue>0x0</resetValue>
782            <resetMask>0x80000000</resetMask>
783            <fields>
784              <field>
785                <name>REGION_SIZE</name>
786                <description>This field specifies the size of the slave region:
787'0': Undefined.
788'1': 4 B region (this is the smallest region size).
789'2': 8 B region
790'3': 16 B region
791'4': 32 B region
792'5': 64 B region
793'6': 128 B region
794'7': 256 B region
795'8': 512 B region
796'9': 1 KB region
797'10': 2 KB region
798'11': 4 KB region
799'12': 8 KB region
800'13': 16 KB region
801'14': 32 KB region
802'15': 64 KB region
803'16': 128 KB region
804'17': 256 KB region
805'18': 512 KB region
806'19': 1 MB region
807'20': 2 MB region
808'21': 4 MB region
809'22': 8 MB region
810'23': 16 MB region
811'24': 32 MB region
812'25': 64 MB region
813'26': 128 MB region
814'27': 256 MB region
815'28': 512 MB region
816'29': 1 GB region
817'30': 2 GB region
818'31': 4 GB region</description>
819                <bitRange>[28:24]</bitRange>
820                <access>read-write</access>
821              </field>
822              <field>
823                <name>VALID</name>
824                <description>Slave region enable:
825'0': Disabled. A disabled region will never result in a match on the transfer address.
826'1': Enabled.</description>
827                <bitRange>[31:31]</bitRange>
828                <access>read-write</access>
829              </field>
830            </fields>
831          </register>
832          <register>
833            <name>SL_ATT0</name>
834            <description>Slave attributes 0</description>
835            <addressOffset>0x10</addressOffset>
836            <size>32</size>
837            <access>read-write</access>
838            <resetValue>0x1F1F1F1F</resetValue>
839            <resetMask>0x1F1F1F1F</resetMask>
840            <fields>
841              <field>
842                <name>PC0_UR</name>
843                <description>Protection context 0, user read enable:
844'0': Disabled (user, read accesses are NOT allowed).
845'1': Enabled (user, read accesses are allowed).</description>
846                <bitRange>[0:0]</bitRange>
847                <access>read-only</access>
848              </field>
849              <field>
850                <name>PC0_UW</name>
851                <description>Protection context 0, user write enable:
852'0': Disabled (user, write accesses are NOT allowed).
853'1': Enabled (user, write accesses are allowed).</description>
854                <bitRange>[1:1]</bitRange>
855                <access>read-only</access>
856              </field>
857              <field>
858                <name>PC0_PR</name>
859                <description>Protection context 0, privileged read enable:
860'0': Disabled (privileged, read accesses are NOT allowed).
861'1': Enabled (privileged, read accesses are allowed).</description>
862                <bitRange>[2:2]</bitRange>
863                <access>read-only</access>
864              </field>
865              <field>
866                <name>PC0_PW</name>
867                <description>Protection context 0, privileged write enable:
868'0': Disabled (privileged, write accesses are NOT allowed).
869'1': Enabled (privileged, write accesses are allowed).</description>
870                <bitRange>[3:3]</bitRange>
871                <access>read-only</access>
872              </field>
873              <field>
874                <name>PC0_NS</name>
875                <description>Protection context 0, non-secure:
876'0': Secure (secure accesses allowed, non-secure access NOT allowed).
877'1': Non-secure (both secure and non-secure accesses allowed).</description>
878                <bitRange>[4:4]</bitRange>
879                <access>read-only</access>
880              </field>
881              <field>
882                <name>PC1_UR</name>
883                <description>Protection context 1, user read enable.</description>
884                <bitRange>[8:8]</bitRange>
885                <access>read-write</access>
886              </field>
887              <field>
888                <name>PC1_UW</name>
889                <description>Protection context 1, user write enable.</description>
890                <bitRange>[9:9]</bitRange>
891                <access>read-write</access>
892              </field>
893              <field>
894                <name>PC1_PR</name>
895                <description>Protection context 1, privileged read enable.</description>
896                <bitRange>[10:10]</bitRange>
897                <access>read-write</access>
898              </field>
899              <field>
900                <name>PC1_PW</name>
901                <description>Protection context 1, privileged write enable.</description>
902                <bitRange>[11:11]</bitRange>
903                <access>read-write</access>
904              </field>
905              <field>
906                <name>PC1_NS</name>
907                <description>Protection context 1, non-secure.</description>
908                <bitRange>[12:12]</bitRange>
909                <access>read-write</access>
910              </field>
911              <field>
912                <name>PC2_UR</name>
913                <description>Protection context 2, user read enable.</description>
914                <bitRange>[16:16]</bitRange>
915                <access>read-write</access>
916              </field>
917              <field>
918                <name>PC2_UW</name>
919                <description>Protection context 2, user write enable.</description>
920                <bitRange>[17:17]</bitRange>
921                <access>read-write</access>
922              </field>
923              <field>
924                <name>PC2_PR</name>
925                <description>Protection context 2, privileged read enable.</description>
926                <bitRange>[18:18]</bitRange>
927                <access>read-write</access>
928              </field>
929              <field>
930                <name>PC2_PW</name>
931                <description>Protection context 2, privileged write enable.</description>
932                <bitRange>[19:19]</bitRange>
933                <access>read-write</access>
934              </field>
935              <field>
936                <name>PC2_NS</name>
937                <description>Protection context 2, non-secure.</description>
938                <bitRange>[20:20]</bitRange>
939                <access>read-write</access>
940              </field>
941              <field>
942                <name>PC3_UR</name>
943                <description>Protection context 3, user read enable.</description>
944                <bitRange>[24:24]</bitRange>
945                <access>read-write</access>
946              </field>
947              <field>
948                <name>PC3_UW</name>
949                <description>Protection context 3, user write enable.</description>
950                <bitRange>[25:25]</bitRange>
951                <access>read-write</access>
952              </field>
953              <field>
954                <name>PC3_PR</name>
955                <description>Protection context 3, privileged read enable.</description>
956                <bitRange>[26:26]</bitRange>
957                <access>read-write</access>
958              </field>
959              <field>
960                <name>PC3_PW</name>
961                <description>Protection context 3, privileged write enable.</description>
962                <bitRange>[27:27]</bitRange>
963                <access>read-write</access>
964              </field>
965              <field>
966                <name>PC3_NS</name>
967                <description>Protection context 3, non-secure.</description>
968                <bitRange>[28:28]</bitRange>
969                <access>read-write</access>
970              </field>
971            </fields>
972          </register>
973          <register>
974            <name>SL_ATT1</name>
975            <description>Slave attributes 1</description>
976            <addressOffset>0x14</addressOffset>
977            <size>32</size>
978            <access>read-write</access>
979            <resetValue>0x1F1F1F1F</resetValue>
980            <resetMask>0x1F1F1F1F</resetMask>
981            <fields>
982              <field>
983                <name>PC4_UR</name>
984                <description>Protection context 4, user read enable.</description>
985                <bitRange>[0:0]</bitRange>
986                <access>read-write</access>
987              </field>
988              <field>
989                <name>PC4_UW</name>
990                <description>Protection context 4, user write enable.</description>
991                <bitRange>[1:1]</bitRange>
992                <access>read-write</access>
993              </field>
994              <field>
995                <name>PC4_PR</name>
996                <description>Protection context 4, privileged read enable.</description>
997                <bitRange>[2:2]</bitRange>
998                <access>read-write</access>
999              </field>
1000              <field>
1001                <name>PC4_PW</name>
1002                <description>Protection context 4, privileged write enable.</description>
1003                <bitRange>[3:3]</bitRange>
1004                <access>read-write</access>
1005              </field>
1006              <field>
1007                <name>PC4_NS</name>
1008                <description>Protection context 4, non-secure.</description>
1009                <bitRange>[4:4]</bitRange>
1010                <access>read-write</access>
1011              </field>
1012              <field>
1013                <name>PC5_UR</name>
1014                <description>Protection context 5, user read enable.</description>
1015                <bitRange>[8:8]</bitRange>
1016                <access>read-write</access>
1017              </field>
1018              <field>
1019                <name>PC5_UW</name>
1020                <description>Protection context 5, user write enable.</description>
1021                <bitRange>[9:9]</bitRange>
1022                <access>read-write</access>
1023              </field>
1024              <field>
1025                <name>PC5_PR</name>
1026                <description>Protection context 5, privileged read enable.</description>
1027                <bitRange>[10:10]</bitRange>
1028                <access>read-write</access>
1029              </field>
1030              <field>
1031                <name>PC5_PW</name>
1032                <description>Protection context 5, privileged write enable.</description>
1033                <bitRange>[11:11]</bitRange>
1034                <access>read-write</access>
1035              </field>
1036              <field>
1037                <name>PC5_NS</name>
1038                <description>Protection context 5, non-secure.</description>
1039                <bitRange>[12:12]</bitRange>
1040                <access>read-write</access>
1041              </field>
1042              <field>
1043                <name>PC6_UR</name>
1044                <description>Protection context 6, user read enable.</description>
1045                <bitRange>[16:16]</bitRange>
1046                <access>read-write</access>
1047              </field>
1048              <field>
1049                <name>PC6_UW</name>
1050                <description>Protection context 6, user write enable.</description>
1051                <bitRange>[17:17]</bitRange>
1052                <access>read-write</access>
1053              </field>
1054              <field>
1055                <name>PC6_PR</name>
1056                <description>Protection context 6, privileged read enable.</description>
1057                <bitRange>[18:18]</bitRange>
1058                <access>read-write</access>
1059              </field>
1060              <field>
1061                <name>PC6_PW</name>
1062                <description>Protection context 6, privileged write enable.</description>
1063                <bitRange>[19:19]</bitRange>
1064                <access>read-write</access>
1065              </field>
1066              <field>
1067                <name>PC6_NS</name>
1068                <description>Protection context 6, non-secure.</description>
1069                <bitRange>[20:20]</bitRange>
1070                <access>read-write</access>
1071              </field>
1072              <field>
1073                <name>PC7_UR</name>
1074                <description>Protection context 7, user read enable.</description>
1075                <bitRange>[24:24]</bitRange>
1076                <access>read-write</access>
1077              </field>
1078              <field>
1079                <name>PC7_UW</name>
1080                <description>Protection context 7, user write enable.</description>
1081                <bitRange>[25:25]</bitRange>
1082                <access>read-write</access>
1083              </field>
1084              <field>
1085                <name>PC7_PR</name>
1086                <description>Protection context 7, privileged read enable.</description>
1087                <bitRange>[26:26]</bitRange>
1088                <access>read-write</access>
1089              </field>
1090              <field>
1091                <name>PC7_PW</name>
1092                <description>Protection context 7, privileged write enable.</description>
1093                <bitRange>[27:27]</bitRange>
1094                <access>read-write</access>
1095              </field>
1096              <field>
1097                <name>PC7_NS</name>
1098                <description>Protection context 7, non-secure.</description>
1099                <bitRange>[28:28]</bitRange>
1100                <access>read-write</access>
1101              </field>
1102            </fields>
1103          </register>
1104          <register>
1105            <name>SL_ATT2</name>
1106            <description>Slave attributes 2</description>
1107            <addressOffset>0x18</addressOffset>
1108            <size>32</size>
1109            <access>read-write</access>
1110            <resetValue>0x1F1F1F1F</resetValue>
1111            <resetMask>0x1F1F1F1F</resetMask>
1112            <fields>
1113              <field>
1114                <name>PC8_UR</name>
1115                <description>Protection context 8, user read enable.</description>
1116                <bitRange>[0:0]</bitRange>
1117                <access>read-write</access>
1118              </field>
1119              <field>
1120                <name>PC8_UW</name>
1121                <description>Protection context 8, user write enable.</description>
1122                <bitRange>[1:1]</bitRange>
1123                <access>read-write</access>
1124              </field>
1125              <field>
1126                <name>PC8_PR</name>
1127                <description>Protection context 8, privileged read enable.</description>
1128                <bitRange>[2:2]</bitRange>
1129                <access>read-write</access>
1130              </field>
1131              <field>
1132                <name>PC8_PW</name>
1133                <description>Protection context 8, privileged write enable.</description>
1134                <bitRange>[3:3]</bitRange>
1135                <access>read-write</access>
1136              </field>
1137              <field>
1138                <name>PC8_NS</name>
1139                <description>Protection context 8, non-secure.</description>
1140                <bitRange>[4:4]</bitRange>
1141                <access>read-write</access>
1142              </field>
1143              <field>
1144                <name>PC9_UR</name>
1145                <description>Protection context 9, user read enable.</description>
1146                <bitRange>[8:8]</bitRange>
1147                <access>read-write</access>
1148              </field>
1149              <field>
1150                <name>PC9_UW</name>
1151                <description>Protection context 9, user write enable.</description>
1152                <bitRange>[9:9]</bitRange>
1153                <access>read-write</access>
1154              </field>
1155              <field>
1156                <name>PC9_PR</name>
1157                <description>Protection context 9, privileged read enable.</description>
1158                <bitRange>[10:10]</bitRange>
1159                <access>read-write</access>
1160              </field>
1161              <field>
1162                <name>PC9_PW</name>
1163                <description>Protection context 9, privileged write enable.</description>
1164                <bitRange>[11:11]</bitRange>
1165                <access>read-write</access>
1166              </field>
1167              <field>
1168                <name>PC9_NS</name>
1169                <description>Protection context 9, non-secure.</description>
1170                <bitRange>[12:12]</bitRange>
1171                <access>read-write</access>
1172              </field>
1173              <field>
1174                <name>PC10_UR</name>
1175                <description>Protection context 10, user read enable.</description>
1176                <bitRange>[16:16]</bitRange>
1177                <access>read-write</access>
1178              </field>
1179              <field>
1180                <name>PC10_UW</name>
1181                <description>Protection context 10, user write enable.</description>
1182                <bitRange>[17:17]</bitRange>
1183                <access>read-write</access>
1184              </field>
1185              <field>
1186                <name>PC10_PR</name>
1187                <description>Protection context 10, privileged read enable.</description>
1188                <bitRange>[18:18]</bitRange>
1189                <access>read-write</access>
1190              </field>
1191              <field>
1192                <name>PC10_PW</name>
1193                <description>Protection context 10, privileged write enable.</description>
1194                <bitRange>[19:19]</bitRange>
1195                <access>read-write</access>
1196              </field>
1197              <field>
1198                <name>PC10_NS</name>
1199                <description>Protection context 10, non-secure.</description>
1200                <bitRange>[20:20]</bitRange>
1201                <access>read-write</access>
1202              </field>
1203              <field>
1204                <name>PC11_UR</name>
1205                <description>Protection context 11, user read enable.</description>
1206                <bitRange>[24:24]</bitRange>
1207                <access>read-write</access>
1208              </field>
1209              <field>
1210                <name>PC11_UW</name>
1211                <description>Protection context 11, user write enable.</description>
1212                <bitRange>[25:25]</bitRange>
1213                <access>read-write</access>
1214              </field>
1215              <field>
1216                <name>PC11_PR</name>
1217                <description>Protection context 11, privileged read enable.</description>
1218                <bitRange>[26:26]</bitRange>
1219                <access>read-write</access>
1220              </field>
1221              <field>
1222                <name>PC11_PW</name>
1223                <description>Protection context 11, privileged write enable.</description>
1224                <bitRange>[27:27]</bitRange>
1225                <access>read-write</access>
1226              </field>
1227              <field>
1228                <name>PC11_NS</name>
1229                <description>Protection context 11, non-secure.</description>
1230                <bitRange>[28:28]</bitRange>
1231                <access>read-write</access>
1232              </field>
1233            </fields>
1234          </register>
1235          <register>
1236            <name>SL_ATT3</name>
1237            <description>Slave attributes 3</description>
1238            <addressOffset>0x1C</addressOffset>
1239            <size>32</size>
1240            <access>read-write</access>
1241            <resetValue>0x1F1F1F1F</resetValue>
1242            <resetMask>0x1F1F1F1F</resetMask>
1243            <fields>
1244              <field>
1245                <name>PC12_UR</name>
1246                <description>Protection context 12, user read enable.</description>
1247                <bitRange>[0:0]</bitRange>
1248                <access>read-write</access>
1249              </field>
1250              <field>
1251                <name>PC12_UW</name>
1252                <description>Protection context 12, user write enable.</description>
1253                <bitRange>[1:1]</bitRange>
1254                <access>read-write</access>
1255              </field>
1256              <field>
1257                <name>PC12_PR</name>
1258                <description>Protection context 12, privileged read enable.</description>
1259                <bitRange>[2:2]</bitRange>
1260                <access>read-write</access>
1261              </field>
1262              <field>
1263                <name>PC12_PW</name>
1264                <description>Protection context 12, privileged write enable.</description>
1265                <bitRange>[3:3]</bitRange>
1266                <access>read-write</access>
1267              </field>
1268              <field>
1269                <name>PC12_NS</name>
1270                <description>Protection context 12, non-secure.</description>
1271                <bitRange>[4:4]</bitRange>
1272                <access>read-write</access>
1273              </field>
1274              <field>
1275                <name>PC13_UR</name>
1276                <description>Protection context 13, user read enable.</description>
1277                <bitRange>[8:8]</bitRange>
1278                <access>read-write</access>
1279              </field>
1280              <field>
1281                <name>PC13_UW</name>
1282                <description>Protection context 13, user write enable.</description>
1283                <bitRange>[9:9]</bitRange>
1284                <access>read-write</access>
1285              </field>
1286              <field>
1287                <name>PC13_PR</name>
1288                <description>Protection context 13, privileged read enable.</description>
1289                <bitRange>[10:10]</bitRange>
1290                <access>read-write</access>
1291              </field>
1292              <field>
1293                <name>PC13_PW</name>
1294                <description>Protection context 13, privileged write enable.</description>
1295                <bitRange>[11:11]</bitRange>
1296                <access>read-write</access>
1297              </field>
1298              <field>
1299                <name>PC13_NS</name>
1300                <description>Protection context 13, non-secure.</description>
1301                <bitRange>[12:12]</bitRange>
1302                <access>read-write</access>
1303              </field>
1304              <field>
1305                <name>PC14_UR</name>
1306                <description>Protection context 14, user read enable.</description>
1307                <bitRange>[16:16]</bitRange>
1308                <access>read-write</access>
1309              </field>
1310              <field>
1311                <name>PC14_UW</name>
1312                <description>Protection context 14, user write enable.</description>
1313                <bitRange>[17:17]</bitRange>
1314                <access>read-write</access>
1315              </field>
1316              <field>
1317                <name>PC14_PR</name>
1318                <description>Protection context 14, privileged read enable.</description>
1319                <bitRange>[18:18]</bitRange>
1320                <access>read-write</access>
1321              </field>
1322              <field>
1323                <name>PC14_PW</name>
1324                <description>Protection context 14, privileged write enable.</description>
1325                <bitRange>[19:19]</bitRange>
1326                <access>read-write</access>
1327              </field>
1328              <field>
1329                <name>PC14_NS</name>
1330                <description>Protection context 14, non-secure.</description>
1331                <bitRange>[20:20]</bitRange>
1332                <access>read-write</access>
1333              </field>
1334              <field>
1335                <name>PC15_UR</name>
1336                <description>Protection context 15, user read enable.</description>
1337                <bitRange>[24:24]</bitRange>
1338                <access>read-write</access>
1339              </field>
1340              <field>
1341                <name>PC15_UW</name>
1342                <description>Protection context 15, user write enable.</description>
1343                <bitRange>[25:25]</bitRange>
1344                <access>read-write</access>
1345              </field>
1346              <field>
1347                <name>PC15_PR</name>
1348                <description>Protection context 15, privileged read enable.</description>
1349                <bitRange>[26:26]</bitRange>
1350                <access>read-write</access>
1351              </field>
1352              <field>
1353                <name>PC15_PW</name>
1354                <description>Protection context 15, privileged write enable.</description>
1355                <bitRange>[27:27]</bitRange>
1356                <access>read-write</access>
1357              </field>
1358              <field>
1359                <name>PC15_NS</name>
1360                <description>Protection context 15, non-secure.</description>
1361                <bitRange>[28:28]</bitRange>
1362                <access>read-write</access>
1363              </field>
1364            </fields>
1365          </register>
1366          <register>
1367            <name>MS_ADDR</name>
1368            <description>Master region, base address</description>
1369            <addressOffset>0x20</addressOffset>
1370            <size>32</size>
1371            <access>read-only</access>
1372            <resetValue>0x0</resetValue>
1373            <resetMask>0xFFFFFFC0</resetMask>
1374            <fields>
1375              <field>
1376                <name>ADDR26</name>
1377                <description>This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register.</description>
1378                <bitRange>[31:6]</bitRange>
1379                <access>read-only</access>
1380              </field>
1381            </fields>
1382          </register>
1383          <register>
1384            <name>MS_SIZE</name>
1385            <description>Master region, size</description>
1386            <addressOffset>0x24</addressOffset>
1387            <size>32</size>
1388            <access>read-only</access>
1389            <resetValue>0x85000000</resetValue>
1390            <resetMask>0x9F000000</resetMask>
1391            <fields>
1392              <field>
1393                <name>REGION_SIZE</name>
1394                <description>This field specifies the size of the master region:
1395'5': 64 B region
1396
1397The master region includes the SL_ADDR, SL_SIZE, SL_ATT0, ..., SL_ATT3, MS_ADDR, MS_SIZE, MS_ATT0, ..., MS_ATT3 registers. Therefore, the access privileges for all these registers is determined by MS_ATT0, ..., MS_ATT3.</description>
1398                <bitRange>[28:24]</bitRange>
1399                <access>read-only</access>
1400              </field>
1401              <field>
1402                <name>VALID</name>
1403                <description>Master region enable:
1404'1': Enabled.</description>
1405                <bitRange>[31:31]</bitRange>
1406                <access>read-only</access>
1407              </field>
1408            </fields>
1409          </register>
1410          <register>
1411            <name>MS_ATT0</name>
1412            <description>Master attributes 0</description>
1413            <addressOffset>0x30</addressOffset>
1414            <size>32</size>
1415            <access>read-write</access>
1416            <resetValue>0x1F1F1F1F</resetValue>
1417            <resetMask>0x1F1F1F1F</resetMask>
1418            <fields>
1419              <field>
1420                <name>PC0_UR</name>
1421                <description>Protection context 0, user read enable:
1422'0': Disabled (user, read accesses are NOT allowed).
1423'1': Enabled (user, read accesses are allowed).</description>
1424                <bitRange>[0:0]</bitRange>
1425                <access>read-only</access>
1426              </field>
1427              <field>
1428                <name>PC0_UW</name>
1429                <description>Protection context 0, user write enable:
1430'0': Disabled (user, write accesses are NOT allowed).
1431'1': Enabled (user, write accesses are allowed).</description>
1432                <bitRange>[1:1]</bitRange>
1433                <access>read-only</access>
1434              </field>
1435              <field>
1436                <name>PC0_PR</name>
1437                <description>Protection context 0, privileged read enable:
1438'0': Disabled (privileged, read accesses are NOT allowed).
1439'1': Enabled (privileged, read accesses are allowed).</description>
1440                <bitRange>[2:2]</bitRange>
1441                <access>read-only</access>
1442              </field>
1443              <field>
1444                <name>PC0_PW</name>
1445                <description>Protection context 0, privileged write enable:
1446'0': Disabled (privileged, write accesses are NOT allowed).
1447'1': Enabled (privileged, write accesses are allowed).</description>
1448                <bitRange>[3:3]</bitRange>
1449                <access>read-only</access>
1450              </field>
1451              <field>
1452                <name>PC0_NS</name>
1453                <description>Protection context 0, non-secure:
1454'0': Secure (secure accesses allowed, non-secure access NOT allowed).
1455'1': Non-secure (both secure and non-secure accesses allowed).</description>
1456                <bitRange>[4:4]</bitRange>
1457                <access>read-only</access>
1458              </field>
1459              <field>
1460                <name>PC1_UR</name>
1461                <description>Protection context 1, user read enable.</description>
1462                <bitRange>[8:8]</bitRange>
1463                <access>read-only</access>
1464              </field>
1465              <field>
1466                <name>PC1_UW</name>
1467                <description>Protection context 1, user write enable.</description>
1468                <bitRange>[9:9]</bitRange>
1469                <access>read-write</access>
1470              </field>
1471              <field>
1472                <name>PC1_PR</name>
1473                <description>Protection context 1, privileged read enable.</description>
1474                <bitRange>[10:10]</bitRange>
1475                <access>read-only</access>
1476              </field>
1477              <field>
1478                <name>PC1_PW</name>
1479                <description>Protection context 1, privileged write enable.</description>
1480                <bitRange>[11:11]</bitRange>
1481                <access>read-write</access>
1482              </field>
1483              <field>
1484                <name>PC1_NS</name>
1485                <description>Protection context 1, non-secure.</description>
1486                <bitRange>[12:12]</bitRange>
1487                <access>read-write</access>
1488              </field>
1489              <field>
1490                <name>PC2_UR</name>
1491                <description>Protection context 2, user read enable.</description>
1492                <bitRange>[16:16]</bitRange>
1493                <access>read-only</access>
1494              </field>
1495              <field>
1496                <name>PC2_UW</name>
1497                <description>Protection context 2, user write enable.</description>
1498                <bitRange>[17:17]</bitRange>
1499                <access>read-write</access>
1500              </field>
1501              <field>
1502                <name>PC2_PR</name>
1503                <description>Protection context 2, privileged read enable.</description>
1504                <bitRange>[18:18]</bitRange>
1505                <access>read-only</access>
1506              </field>
1507              <field>
1508                <name>PC2_PW</name>
1509                <description>Protection context 2, privileged write enable.</description>
1510                <bitRange>[19:19]</bitRange>
1511                <access>read-write</access>
1512              </field>
1513              <field>
1514                <name>PC2_NS</name>
1515                <description>Protection context 2, non-secure.</description>
1516                <bitRange>[20:20]</bitRange>
1517                <access>read-write</access>
1518              </field>
1519              <field>
1520                <name>PC3_UR</name>
1521                <description>Protection context 3, user read enable.</description>
1522                <bitRange>[24:24]</bitRange>
1523                <access>read-only</access>
1524              </field>
1525              <field>
1526                <name>PC3_UW</name>
1527                <description>Protection context 3, user write enable.</description>
1528                <bitRange>[25:25]</bitRange>
1529                <access>read-write</access>
1530              </field>
1531              <field>
1532                <name>PC3_PR</name>
1533                <description>Protection context 3, privileged read enable.</description>
1534                <bitRange>[26:26]</bitRange>
1535                <access>read-only</access>
1536              </field>
1537              <field>
1538                <name>PC3_PW</name>
1539                <description>Protection context 3, privileged write enable.</description>
1540                <bitRange>[27:27]</bitRange>
1541                <access>read-write</access>
1542              </field>
1543              <field>
1544                <name>PC3_NS</name>
1545                <description>Protection context 3, non-secure.</description>
1546                <bitRange>[28:28]</bitRange>
1547                <access>read-write</access>
1548              </field>
1549            </fields>
1550          </register>
1551          <register>
1552            <name>MS_ATT1</name>
1553            <description>Master attributes 1</description>
1554            <addressOffset>0x34</addressOffset>
1555            <size>32</size>
1556            <access>read-write</access>
1557            <resetValue>0x1F1F1F1F</resetValue>
1558            <resetMask>0x1F1F1F1F</resetMask>
1559            <fields>
1560              <field>
1561                <name>PC4_UR</name>
1562                <description>Protection context 4, user read enable.</description>
1563                <bitRange>[0:0]</bitRange>
1564                <access>read-only</access>
1565              </field>
1566              <field>
1567                <name>PC4_UW</name>
1568                <description>Protection context 4, user write enable.</description>
1569                <bitRange>[1:1]</bitRange>
1570                <access>read-write</access>
1571              </field>
1572              <field>
1573                <name>PC4_PR</name>
1574                <description>Protection context 4, privileged read enable.</description>
1575                <bitRange>[2:2]</bitRange>
1576                <access>read-only</access>
1577              </field>
1578              <field>
1579                <name>PC4_PW</name>
1580                <description>Protection context 4, privileged write enable.</description>
1581                <bitRange>[3:3]</bitRange>
1582                <access>read-write</access>
1583              </field>
1584              <field>
1585                <name>PC4_NS</name>
1586                <description>Protection context 4, non-secure.</description>
1587                <bitRange>[4:4]</bitRange>
1588                <access>read-write</access>
1589              </field>
1590              <field>
1591                <name>PC5_UR</name>
1592                <description>Protection context 5, user read enable.</description>
1593                <bitRange>[8:8]</bitRange>
1594                <access>read-only</access>
1595              </field>
1596              <field>
1597                <name>PC5_UW</name>
1598                <description>Protection context 5, user write enable.</description>
1599                <bitRange>[9:9]</bitRange>
1600                <access>read-write</access>
1601              </field>
1602              <field>
1603                <name>PC5_PR</name>
1604                <description>Protection context 5, privileged read enable.</description>
1605                <bitRange>[10:10]</bitRange>
1606                <access>read-only</access>
1607              </field>
1608              <field>
1609                <name>PC5_PW</name>
1610                <description>Protection context 5, privileged write enable.</description>
1611                <bitRange>[11:11]</bitRange>
1612                <access>read-write</access>
1613              </field>
1614              <field>
1615                <name>PC5_NS</name>
1616                <description>Protection context 5, non-secure.</description>
1617                <bitRange>[12:12]</bitRange>
1618                <access>read-write</access>
1619              </field>
1620              <field>
1621                <name>PC6_UR</name>
1622                <description>Protection context 6, user read enable.</description>
1623                <bitRange>[16:16]</bitRange>
1624                <access>read-only</access>
1625              </field>
1626              <field>
1627                <name>PC6_UW</name>
1628                <description>Protection context 6, user write enable.</description>
1629                <bitRange>[17:17]</bitRange>
1630                <access>read-write</access>
1631              </field>
1632              <field>
1633                <name>PC6_PR</name>
1634                <description>Protection context 6, privileged read enable.</description>
1635                <bitRange>[18:18]</bitRange>
1636                <access>read-only</access>
1637              </field>
1638              <field>
1639                <name>PC6_PW</name>
1640                <description>Protection context 6, privileged write enable.</description>
1641                <bitRange>[19:19]</bitRange>
1642                <access>read-write</access>
1643              </field>
1644              <field>
1645                <name>PC6_NS</name>
1646                <description>Protection context 6, non-secure.</description>
1647                <bitRange>[20:20]</bitRange>
1648                <access>read-write</access>
1649              </field>
1650              <field>
1651                <name>PC7_UR</name>
1652                <description>Protection context 7, user read enable.</description>
1653                <bitRange>[24:24]</bitRange>
1654                <access>read-only</access>
1655              </field>
1656              <field>
1657                <name>PC7_UW</name>
1658                <description>Protection context 7, user write enable.</description>
1659                <bitRange>[25:25]</bitRange>
1660                <access>read-write</access>
1661              </field>
1662              <field>
1663                <name>PC7_PR</name>
1664                <description>Protection context 7, privileged read enable.</description>
1665                <bitRange>[26:26]</bitRange>
1666                <access>read-only</access>
1667              </field>
1668              <field>
1669                <name>PC7_PW</name>
1670                <description>Protection context 7, privileged write enable.</description>
1671                <bitRange>[27:27]</bitRange>
1672                <access>read-write</access>
1673              </field>
1674              <field>
1675                <name>PC7_NS</name>
1676                <description>Protection context 7, non-secure.</description>
1677                <bitRange>[28:28]</bitRange>
1678                <access>read-write</access>
1679              </field>
1680            </fields>
1681          </register>
1682          <register>
1683            <name>MS_ATT2</name>
1684            <description>Master attributes 2</description>
1685            <addressOffset>0x38</addressOffset>
1686            <size>32</size>
1687            <access>read-write</access>
1688            <resetValue>0x1F1F1F1F</resetValue>
1689            <resetMask>0x1F1F1F1F</resetMask>
1690            <fields>
1691              <field>
1692                <name>PC8_UR</name>
1693                <description>Protection context 8, user read enable.</description>
1694                <bitRange>[0:0]</bitRange>
1695                <access>read-only</access>
1696              </field>
1697              <field>
1698                <name>PC8_UW</name>
1699                <description>Protection context 8, user write enable.</description>
1700                <bitRange>[1:1]</bitRange>
1701                <access>read-write</access>
1702              </field>
1703              <field>
1704                <name>PC8_PR</name>
1705                <description>Protection context 8, privileged read enable.</description>
1706                <bitRange>[2:2]</bitRange>
1707                <access>read-only</access>
1708              </field>
1709              <field>
1710                <name>PC8_PW</name>
1711                <description>Protection context 8, privileged write enable.</description>
1712                <bitRange>[3:3]</bitRange>
1713                <access>read-write</access>
1714              </field>
1715              <field>
1716                <name>PC8_NS</name>
1717                <description>Protection context 8, non-secure.</description>
1718                <bitRange>[4:4]</bitRange>
1719                <access>read-write</access>
1720              </field>
1721              <field>
1722                <name>PC9_UR</name>
1723                <description>Protection context 9, user read enable.</description>
1724                <bitRange>[8:8]</bitRange>
1725                <access>read-only</access>
1726              </field>
1727              <field>
1728                <name>PC9_UW</name>
1729                <description>Protection context 9, user write enable.</description>
1730                <bitRange>[9:9]</bitRange>
1731                <access>read-write</access>
1732              </field>
1733              <field>
1734                <name>PC9_PR</name>
1735                <description>Protection context 9, privileged read enable.</description>
1736                <bitRange>[10:10]</bitRange>
1737                <access>read-only</access>
1738              </field>
1739              <field>
1740                <name>PC9_PW</name>
1741                <description>Protection context 9, privileged write enable.</description>
1742                <bitRange>[11:11]</bitRange>
1743                <access>read-write</access>
1744              </field>
1745              <field>
1746                <name>PC9_NS</name>
1747                <description>Protection context 9, non-secure.</description>
1748                <bitRange>[12:12]</bitRange>
1749                <access>read-write</access>
1750              </field>
1751              <field>
1752                <name>PC10_UR</name>
1753                <description>Protection context 10, user read enable.</description>
1754                <bitRange>[16:16]</bitRange>
1755                <access>read-only</access>
1756              </field>
1757              <field>
1758                <name>PC10_UW</name>
1759                <description>Protection context 10, user write enable.</description>
1760                <bitRange>[17:17]</bitRange>
1761                <access>read-write</access>
1762              </field>
1763              <field>
1764                <name>PC10_PR</name>
1765                <description>Protection context 10, privileged read enable.</description>
1766                <bitRange>[18:18]</bitRange>
1767                <access>read-only</access>
1768              </field>
1769              <field>
1770                <name>PC10_PW</name>
1771                <description>Protection context 10, privileged write enable.</description>
1772                <bitRange>[19:19]</bitRange>
1773                <access>read-write</access>
1774              </field>
1775              <field>
1776                <name>PC10_NS</name>
1777                <description>Protection context 10, non-secure.</description>
1778                <bitRange>[20:20]</bitRange>
1779                <access>read-write</access>
1780              </field>
1781              <field>
1782                <name>PC11_UR</name>
1783                <description>Protection context 11, user read enable.</description>
1784                <bitRange>[24:24]</bitRange>
1785                <access>read-only</access>
1786              </field>
1787              <field>
1788                <name>PC11_UW</name>
1789                <description>Protection context 11, user write enable.</description>
1790                <bitRange>[25:25]</bitRange>
1791                <access>read-write</access>
1792              </field>
1793              <field>
1794                <name>PC11_PR</name>
1795                <description>Protection context 11, privileged read enable.</description>
1796                <bitRange>[26:26]</bitRange>
1797                <access>read-only</access>
1798              </field>
1799              <field>
1800                <name>PC11_PW</name>
1801                <description>Protection context 11, privileged write enable.</description>
1802                <bitRange>[27:27]</bitRange>
1803                <access>read-write</access>
1804              </field>
1805              <field>
1806                <name>PC11_NS</name>
1807                <description>Protection context 11, non-secure.</description>
1808                <bitRange>[28:28]</bitRange>
1809                <access>read-write</access>
1810              </field>
1811            </fields>
1812          </register>
1813          <register>
1814            <name>MS_ATT3</name>
1815            <description>Master attributes 3</description>
1816            <addressOffset>0x3C</addressOffset>
1817            <size>32</size>
1818            <access>read-write</access>
1819            <resetValue>0x1F1F1F1F</resetValue>
1820            <resetMask>0x1F1F1F1F</resetMask>
1821            <fields>
1822              <field>
1823                <name>PC12_UR</name>
1824                <description>Protection context 12, user read enable.</description>
1825                <bitRange>[0:0]</bitRange>
1826                <access>read-only</access>
1827              </field>
1828              <field>
1829                <name>PC12_UW</name>
1830                <description>Protection context 12, user write enable.</description>
1831                <bitRange>[1:1]</bitRange>
1832                <access>read-write</access>
1833              </field>
1834              <field>
1835                <name>PC12_PR</name>
1836                <description>Protection context 12, privileged read enable.</description>
1837                <bitRange>[2:2]</bitRange>
1838                <access>read-only</access>
1839              </field>
1840              <field>
1841                <name>PC12_PW</name>
1842                <description>Protection context 12, privileged write enable.</description>
1843                <bitRange>[3:3]</bitRange>
1844                <access>read-write</access>
1845              </field>
1846              <field>
1847                <name>PC12_NS</name>
1848                <description>Protection context 12, non-secure.</description>
1849                <bitRange>[4:4]</bitRange>
1850                <access>read-write</access>
1851              </field>
1852              <field>
1853                <name>PC13_UR</name>
1854                <description>Protection context 13, user read enable.</description>
1855                <bitRange>[8:8]</bitRange>
1856                <access>read-only</access>
1857              </field>
1858              <field>
1859                <name>PC13_UW</name>
1860                <description>Protection context 13, user write enable.</description>
1861                <bitRange>[9:9]</bitRange>
1862                <access>read-write</access>
1863              </field>
1864              <field>
1865                <name>PC13_PR</name>
1866                <description>Protection context 13, privileged read enable.</description>
1867                <bitRange>[10:10]</bitRange>
1868                <access>read-only</access>
1869              </field>
1870              <field>
1871                <name>PC13_PW</name>
1872                <description>Protection context 13, privileged write enable.</description>
1873                <bitRange>[11:11]</bitRange>
1874                <access>read-write</access>
1875              </field>
1876              <field>
1877                <name>PC13_NS</name>
1878                <description>Protection context 13, non-secure.</description>
1879                <bitRange>[12:12]</bitRange>
1880                <access>read-write</access>
1881              </field>
1882              <field>
1883                <name>PC14_UR</name>
1884                <description>Protection context 14, user read enable.</description>
1885                <bitRange>[16:16]</bitRange>
1886                <access>read-only</access>
1887              </field>
1888              <field>
1889                <name>PC14_UW</name>
1890                <description>Protection context 14, user write enable.</description>
1891                <bitRange>[17:17]</bitRange>
1892                <access>read-write</access>
1893              </field>
1894              <field>
1895                <name>PC14_PR</name>
1896                <description>Protection context 14, privileged read enable.</description>
1897                <bitRange>[18:18]</bitRange>
1898                <access>read-only</access>
1899              </field>
1900              <field>
1901                <name>PC14_PW</name>
1902                <description>Protection context 14, privileged write enable.</description>
1903                <bitRange>[19:19]</bitRange>
1904                <access>read-write</access>
1905              </field>
1906              <field>
1907                <name>PC14_NS</name>
1908                <description>Protection context 14, non-secure.</description>
1909                <bitRange>[20:20]</bitRange>
1910                <access>read-write</access>
1911              </field>
1912              <field>
1913                <name>PC15_UR</name>
1914                <description>Protection context 15, user read enable.</description>
1915                <bitRange>[24:24]</bitRange>
1916                <access>read-only</access>
1917              </field>
1918              <field>
1919                <name>PC15_UW</name>
1920                <description>Protection context 15, user write enable.</description>
1921                <bitRange>[25:25]</bitRange>
1922                <access>read-write</access>
1923              </field>
1924              <field>
1925                <name>PC15_PR</name>
1926                <description>Protection context 15, privileged read enable.</description>
1927                <bitRange>[26:26]</bitRange>
1928                <access>read-only</access>
1929              </field>
1930              <field>
1931                <name>PC15_PW</name>
1932                <description>Protection context 15, privileged write enable.</description>
1933                <bitRange>[27:27]</bitRange>
1934                <access>read-write</access>
1935              </field>
1936              <field>
1937                <name>PC15_NS</name>
1938                <description>Protection context 15, non-secure.</description>
1939                <bitRange>[28:28]</bitRange>
1940                <access>read-write</access>
1941              </field>
1942            </fields>
1943          </register>
1944        </cluster>
1945        <cluster>
1946          <dim>219</dim>
1947          <dimIncrement>64</dimIncrement>
1948          <name>PPU_FX[%s]</name>
1949          <description>Fixed protection structure pair</description>
1950          <addressOffset>0x00000800</addressOffset>
1951          <register>
1952            <name>SL_ADDR</name>
1953            <description>Slave region, base address</description>
1954            <addressOffset>0x0</addressOffset>
1955            <size>32</size>
1956            <access>read-only</access>
1957            <resetValue>0x0</resetValue>
1958            <resetMask>0xFFFFFFFC</resetMask>
1959            <fields>
1960              <field>
1961                <name>ADDR30</name>
1962                <description>This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore, some of the lesser significant address bits of ADDR30 must be '0's. E.g., a 64 KB address region (REGION_SIZE is '15') must be 64 KByte aligned, and ADDR30[13:0] must be '0's.</description>
1963                <bitRange>[31:2]</bitRange>
1964                <access>read-only</access>
1965              </field>
1966            </fields>
1967          </register>
1968          <register>
1969            <name>SL_SIZE</name>
1970            <description>Slave region, size</description>
1971            <addressOffset>0x4</addressOffset>
1972            <size>32</size>
1973            <access>read-only</access>
1974            <resetValue>0x80000000</resetValue>
1975            <resetMask>0x9F000000</resetMask>
1976            <fields>
1977              <field>
1978                <name>REGION_SIZE</name>
1979                <description>This field specifies the size of the slave region:
1980'0': Undefined.
1981'1': 4 B region (this is the smallest region size).
1982'2': 8 B region
1983'3': 16 B region
1984'4': 32 B region
1985'5': 64 B region
1986'6': 128 B region
1987'7': 256 B region
1988'8': 512 B region
1989'9': 1 KB region
1990'10': 2 KB region
1991'11': 4 KB region
1992'12': 8 KB region
1993'13': 16 KB region
1994'14': 32 KB region
1995'15': 64 KB region
1996'16': 128 KB region
1997'17': 256 KB region
1998'18': 512 KB region
1999'19': 1 MB region
2000'20': 2 MB region
2001'21': 4 MB region
2002'22': 8 MB region
2003'23': 16 MB region
2004'24': 32 MB region
2005'25': 64 MB region
2006'26': 128 MB region
2007'27': 256 MB region
2008'28': 512 MB region
2009'29': 1 GB region
2010'30': 2 GB region
2011'31': 4 GB region</description>
2012                <bitRange>[28:24]</bitRange>
2013                <access>read-only</access>
2014              </field>
2015              <field>
2016                <name>VALID</name>
2017                <description>Slave region enable:
2018'0': Disabled. A disabled region will never result in a match on the transfer address.
2019'1': Enabled.</description>
2020                <bitRange>[31:31]</bitRange>
2021                <access>read-only</access>
2022              </field>
2023            </fields>
2024          </register>
2025          <register>
2026            <name>SL_ATT0</name>
2027            <description>Slave attributes 0</description>
2028            <addressOffset>0x10</addressOffset>
2029            <size>32</size>
2030            <access>read-write</access>
2031            <resetValue>0x1F1F1F1F</resetValue>
2032            <resetMask>0x1F1F1F1F</resetMask>
2033            <fields>
2034              <field>
2035                <name>PC0_UR</name>
2036                <description>Protection context 0, user read enable:
2037'0': Disabled (user, read accesses are NOT allowed).
2038'1': Enabled (user, read accesses are allowed).</description>
2039                <bitRange>[0:0]</bitRange>
2040                <access>read-only</access>
2041              </field>
2042              <field>
2043                <name>PC0_UW</name>
2044                <description>Protection context 0, user write enable:
2045'0': Disabled (user, write accesses are NOT allowed).
2046'1': Enabled (user, write accesses are allowed).</description>
2047                <bitRange>[1:1]</bitRange>
2048                <access>read-only</access>
2049              </field>
2050              <field>
2051                <name>PC0_PR</name>
2052                <description>Protection context 0, privileged read enable:
2053'0': Disabled (privileged, read accesses are NOT allowed).
2054'1': Enabled (privileged, read accesses are allowed).</description>
2055                <bitRange>[2:2]</bitRange>
2056                <access>read-only</access>
2057              </field>
2058              <field>
2059                <name>PC0_PW</name>
2060                <description>Protection context 0, privileged write enable:
2061'0': Disabled (privileged, write accesses are NOT allowed).
2062'1': Enabled (privileged, write accesses are allowed).</description>
2063                <bitRange>[3:3]</bitRange>
2064                <access>read-only</access>
2065              </field>
2066              <field>
2067                <name>PC0_NS</name>
2068                <description>Protection context 0, non-secure:
2069'0': Secure (secure accesses allowed, non-secure access NOT allowed).
2070'1': Non-secure (both secure and non-secure accesses allowed).</description>
2071                <bitRange>[4:4]</bitRange>
2072                <access>read-only</access>
2073              </field>
2074              <field>
2075                <name>PC1_UR</name>
2076                <description>Protection context 1, user read enable.</description>
2077                <bitRange>[8:8]</bitRange>
2078                <access>read-write</access>
2079              </field>
2080              <field>
2081                <name>PC1_UW</name>
2082                <description>Protection context 1, user write enable.</description>
2083                <bitRange>[9:9]</bitRange>
2084                <access>read-write</access>
2085              </field>
2086              <field>
2087                <name>PC1_PR</name>
2088                <description>Protection context 1, privileged read enable.</description>
2089                <bitRange>[10:10]</bitRange>
2090                <access>read-write</access>
2091              </field>
2092              <field>
2093                <name>PC1_PW</name>
2094                <description>Protection context 1, privileged write enable.</description>
2095                <bitRange>[11:11]</bitRange>
2096                <access>read-write</access>
2097              </field>
2098              <field>
2099                <name>PC1_NS</name>
2100                <description>Protection context 1, non-secure.</description>
2101                <bitRange>[12:12]</bitRange>
2102                <access>read-write</access>
2103              </field>
2104              <field>
2105                <name>PC2_UR</name>
2106                <description>Protection context 2, user read enable.</description>
2107                <bitRange>[16:16]</bitRange>
2108                <access>read-write</access>
2109              </field>
2110              <field>
2111                <name>PC2_UW</name>
2112                <description>Protection context 2, user write enable.</description>
2113                <bitRange>[17:17]</bitRange>
2114                <access>read-write</access>
2115              </field>
2116              <field>
2117                <name>PC2_PR</name>
2118                <description>Protection context 2, privileged read enable.</description>
2119                <bitRange>[18:18]</bitRange>
2120                <access>read-write</access>
2121              </field>
2122              <field>
2123                <name>PC2_PW</name>
2124                <description>Protection context 2, privileged write enable.</description>
2125                <bitRange>[19:19]</bitRange>
2126                <access>read-write</access>
2127              </field>
2128              <field>
2129                <name>PC2_NS</name>
2130                <description>Protection context 2, non-secure.</description>
2131                <bitRange>[20:20]</bitRange>
2132                <access>read-write</access>
2133              </field>
2134              <field>
2135                <name>PC3_UR</name>
2136                <description>Protection context 3, user read enable.</description>
2137                <bitRange>[24:24]</bitRange>
2138                <access>read-write</access>
2139              </field>
2140              <field>
2141                <name>PC3_UW</name>
2142                <description>Protection context 3, user write enable.</description>
2143                <bitRange>[25:25]</bitRange>
2144                <access>read-write</access>
2145              </field>
2146              <field>
2147                <name>PC3_PR</name>
2148                <description>Protection context 3, privileged read enable.</description>
2149                <bitRange>[26:26]</bitRange>
2150                <access>read-write</access>
2151              </field>
2152              <field>
2153                <name>PC3_PW</name>
2154                <description>Protection context 3, privileged write enable.</description>
2155                <bitRange>[27:27]</bitRange>
2156                <access>read-write</access>
2157              </field>
2158              <field>
2159                <name>PC3_NS</name>
2160                <description>Protection context 3, non-secure.</description>
2161                <bitRange>[28:28]</bitRange>
2162                <access>read-write</access>
2163              </field>
2164            </fields>
2165          </register>
2166          <register>
2167            <name>SL_ATT1</name>
2168            <description>Slave attributes 1</description>
2169            <addressOffset>0x14</addressOffset>
2170            <size>32</size>
2171            <access>read-write</access>
2172            <resetValue>0x1F1F1F1F</resetValue>
2173            <resetMask>0x1F1F1F1F</resetMask>
2174            <fields>
2175              <field>
2176                <name>PC4_UR</name>
2177                <description>Protection context 4, user read enable.</description>
2178                <bitRange>[0:0]</bitRange>
2179                <access>read-write</access>
2180              </field>
2181              <field>
2182                <name>PC4_UW</name>
2183                <description>Protection context 4, user write enable.</description>
2184                <bitRange>[1:1]</bitRange>
2185                <access>read-write</access>
2186              </field>
2187              <field>
2188                <name>PC4_PR</name>
2189                <description>Protection context 4, privileged read enable.</description>
2190                <bitRange>[2:2]</bitRange>
2191                <access>read-write</access>
2192              </field>
2193              <field>
2194                <name>PC4_PW</name>
2195                <description>Protection context 4, privileged write enable.</description>
2196                <bitRange>[3:3]</bitRange>
2197                <access>read-write</access>
2198              </field>
2199              <field>
2200                <name>PC4_NS</name>
2201                <description>Protection context 4, non-secure.</description>
2202                <bitRange>[4:4]</bitRange>
2203                <access>read-write</access>
2204              </field>
2205              <field>
2206                <name>PC5_UR</name>
2207                <description>Protection context 5, user read enable.</description>
2208                <bitRange>[8:8]</bitRange>
2209                <access>read-write</access>
2210              </field>
2211              <field>
2212                <name>PC5_UW</name>
2213                <description>Protection context 5, user write enable.</description>
2214                <bitRange>[9:9]</bitRange>
2215                <access>read-write</access>
2216              </field>
2217              <field>
2218                <name>PC5_PR</name>
2219                <description>Protection context 5, privileged read enable.</description>
2220                <bitRange>[10:10]</bitRange>
2221                <access>read-write</access>
2222              </field>
2223              <field>
2224                <name>PC5_PW</name>
2225                <description>Protection context 5, privileged write enable.</description>
2226                <bitRange>[11:11]</bitRange>
2227                <access>read-write</access>
2228              </field>
2229              <field>
2230                <name>PC5_NS</name>
2231                <description>Protection context 5, non-secure.</description>
2232                <bitRange>[12:12]</bitRange>
2233                <access>read-write</access>
2234              </field>
2235              <field>
2236                <name>PC6_UR</name>
2237                <description>Protection context 6, user read enable.</description>
2238                <bitRange>[16:16]</bitRange>
2239                <access>read-write</access>
2240              </field>
2241              <field>
2242                <name>PC6_UW</name>
2243                <description>Protection context 6, user write enable.</description>
2244                <bitRange>[17:17]</bitRange>
2245                <access>read-write</access>
2246              </field>
2247              <field>
2248                <name>PC6_PR</name>
2249                <description>Protection context 6, privileged read enable.</description>
2250                <bitRange>[18:18]</bitRange>
2251                <access>read-write</access>
2252              </field>
2253              <field>
2254                <name>PC6_PW</name>
2255                <description>Protection context 6, privileged write enable.</description>
2256                <bitRange>[19:19]</bitRange>
2257                <access>read-write</access>
2258              </field>
2259              <field>
2260                <name>PC6_NS</name>
2261                <description>Protection context 6, non-secure.</description>
2262                <bitRange>[20:20]</bitRange>
2263                <access>read-write</access>
2264              </field>
2265              <field>
2266                <name>PC7_UR</name>
2267                <description>Protection context 7, user read enable.</description>
2268                <bitRange>[24:24]</bitRange>
2269                <access>read-write</access>
2270              </field>
2271              <field>
2272                <name>PC7_UW</name>
2273                <description>Protection context 7, user write enable.</description>
2274                <bitRange>[25:25]</bitRange>
2275                <access>read-write</access>
2276              </field>
2277              <field>
2278                <name>PC7_PR</name>
2279                <description>Protection context 7, privileged read enable.</description>
2280                <bitRange>[26:26]</bitRange>
2281                <access>read-write</access>
2282              </field>
2283              <field>
2284                <name>PC7_PW</name>
2285                <description>Protection context 7, privileged write enable.</description>
2286                <bitRange>[27:27]</bitRange>
2287                <access>read-write</access>
2288              </field>
2289              <field>
2290                <name>PC7_NS</name>
2291                <description>Protection context 7, non-secure.</description>
2292                <bitRange>[28:28]</bitRange>
2293                <access>read-write</access>
2294              </field>
2295            </fields>
2296          </register>
2297          <register>
2298            <name>SL_ATT2</name>
2299            <description>Slave attributes 2</description>
2300            <addressOffset>0x18</addressOffset>
2301            <size>32</size>
2302            <access>read-write</access>
2303            <resetValue>0x1F1F1F1F</resetValue>
2304            <resetMask>0x1F1F1F1F</resetMask>
2305            <fields>
2306              <field>
2307                <name>PC8_UR</name>
2308                <description>Protection context 8, user read enable.</description>
2309                <bitRange>[0:0]</bitRange>
2310                <access>read-write</access>
2311              </field>
2312              <field>
2313                <name>PC8_UW</name>
2314                <description>Protection context 8, user write enable.</description>
2315                <bitRange>[1:1]</bitRange>
2316                <access>read-write</access>
2317              </field>
2318              <field>
2319                <name>PC8_PR</name>
2320                <description>Protection context 8, privileged read enable.</description>
2321                <bitRange>[2:2]</bitRange>
2322                <access>read-write</access>
2323              </field>
2324              <field>
2325                <name>PC8_PW</name>
2326                <description>Protection context 8, privileged write enable.</description>
2327                <bitRange>[3:3]</bitRange>
2328                <access>read-write</access>
2329              </field>
2330              <field>
2331                <name>PC8_NS</name>
2332                <description>Protection context 8, non-secure.</description>
2333                <bitRange>[4:4]</bitRange>
2334                <access>read-write</access>
2335              </field>
2336              <field>
2337                <name>PC9_UR</name>
2338                <description>Protection context 9, user read enable.</description>
2339                <bitRange>[8:8]</bitRange>
2340                <access>read-write</access>
2341              </field>
2342              <field>
2343                <name>PC9_UW</name>
2344                <description>Protection context 9, user write enable.</description>
2345                <bitRange>[9:9]</bitRange>
2346                <access>read-write</access>
2347              </field>
2348              <field>
2349                <name>PC9_PR</name>
2350                <description>Protection context 9, privileged read enable.</description>
2351                <bitRange>[10:10]</bitRange>
2352                <access>read-write</access>
2353              </field>
2354              <field>
2355                <name>PC9_PW</name>
2356                <description>Protection context 9, privileged write enable.</description>
2357                <bitRange>[11:11]</bitRange>
2358                <access>read-write</access>
2359              </field>
2360              <field>
2361                <name>PC9_NS</name>
2362                <description>Protection context 9, non-secure.</description>
2363                <bitRange>[12:12]</bitRange>
2364                <access>read-write</access>
2365              </field>
2366              <field>
2367                <name>PC10_UR</name>
2368                <description>Protection context 10, user read enable.</description>
2369                <bitRange>[16:16]</bitRange>
2370                <access>read-write</access>
2371              </field>
2372              <field>
2373                <name>PC10_UW</name>
2374                <description>Protection context 10, user write enable.</description>
2375                <bitRange>[17:17]</bitRange>
2376                <access>read-write</access>
2377              </field>
2378              <field>
2379                <name>PC10_PR</name>
2380                <description>Protection context 10, privileged read enable.</description>
2381                <bitRange>[18:18]</bitRange>
2382                <access>read-write</access>
2383              </field>
2384              <field>
2385                <name>PC10_PW</name>
2386                <description>Protection context 10, privileged write enable.</description>
2387                <bitRange>[19:19]</bitRange>
2388                <access>read-write</access>
2389              </field>
2390              <field>
2391                <name>PC10_NS</name>
2392                <description>Protection context 10, non-secure.</description>
2393                <bitRange>[20:20]</bitRange>
2394                <access>read-write</access>
2395              </field>
2396              <field>
2397                <name>PC11_UR</name>
2398                <description>Protection context 11, user read enable.</description>
2399                <bitRange>[24:24]</bitRange>
2400                <access>read-write</access>
2401              </field>
2402              <field>
2403                <name>PC11_UW</name>
2404                <description>Protection context 11, user write enable.</description>
2405                <bitRange>[25:25]</bitRange>
2406                <access>read-write</access>
2407              </field>
2408              <field>
2409                <name>PC11_PR</name>
2410                <description>Protection context 11, privileged read enable.</description>
2411                <bitRange>[26:26]</bitRange>
2412                <access>read-write</access>
2413              </field>
2414              <field>
2415                <name>PC11_PW</name>
2416                <description>Protection context 11, privileged write enable.</description>
2417                <bitRange>[27:27]</bitRange>
2418                <access>read-write</access>
2419              </field>
2420              <field>
2421                <name>PC11_NS</name>
2422                <description>Protection context 11, non-secure.</description>
2423                <bitRange>[28:28]</bitRange>
2424                <access>read-write</access>
2425              </field>
2426            </fields>
2427          </register>
2428          <register>
2429            <name>SL_ATT3</name>
2430            <description>Slave attributes 3</description>
2431            <addressOffset>0x1C</addressOffset>
2432            <size>32</size>
2433            <access>read-write</access>
2434            <resetValue>0x1F1F1F1F</resetValue>
2435            <resetMask>0x1F1F1F1F</resetMask>
2436            <fields>
2437              <field>
2438                <name>PC12_UR</name>
2439                <description>Protection context 12, user read enable.</description>
2440                <bitRange>[0:0]</bitRange>
2441                <access>read-write</access>
2442              </field>
2443              <field>
2444                <name>PC12_UW</name>
2445                <description>Protection context 12, user write enable.</description>
2446                <bitRange>[1:1]</bitRange>
2447                <access>read-write</access>
2448              </field>
2449              <field>
2450                <name>PC12_PR</name>
2451                <description>Protection context 12, privileged read enable.</description>
2452                <bitRange>[2:2]</bitRange>
2453                <access>read-write</access>
2454              </field>
2455              <field>
2456                <name>PC12_PW</name>
2457                <description>Protection context 12, privileged write enable.</description>
2458                <bitRange>[3:3]</bitRange>
2459                <access>read-write</access>
2460              </field>
2461              <field>
2462                <name>PC12_NS</name>
2463                <description>Protection context 12, non-secure.</description>
2464                <bitRange>[4:4]</bitRange>
2465                <access>read-write</access>
2466              </field>
2467              <field>
2468                <name>PC13_UR</name>
2469                <description>Protection context 13, user read enable.</description>
2470                <bitRange>[8:8]</bitRange>
2471                <access>read-write</access>
2472              </field>
2473              <field>
2474                <name>PC13_UW</name>
2475                <description>Protection context 13, user write enable.</description>
2476                <bitRange>[9:9]</bitRange>
2477                <access>read-write</access>
2478              </field>
2479              <field>
2480                <name>PC13_PR</name>
2481                <description>Protection context 13, privileged read enable.</description>
2482                <bitRange>[10:10]</bitRange>
2483                <access>read-write</access>
2484              </field>
2485              <field>
2486                <name>PC13_PW</name>
2487                <description>Protection context 13, privileged write enable.</description>
2488                <bitRange>[11:11]</bitRange>
2489                <access>read-write</access>
2490              </field>
2491              <field>
2492                <name>PC13_NS</name>
2493                <description>Protection context 13, non-secure.</description>
2494                <bitRange>[12:12]</bitRange>
2495                <access>read-write</access>
2496              </field>
2497              <field>
2498                <name>PC14_UR</name>
2499                <description>Protection context 14, user read enable.</description>
2500                <bitRange>[16:16]</bitRange>
2501                <access>read-write</access>
2502              </field>
2503              <field>
2504                <name>PC14_UW</name>
2505                <description>Protection context 14, user write enable.</description>
2506                <bitRange>[17:17]</bitRange>
2507                <access>read-write</access>
2508              </field>
2509              <field>
2510                <name>PC14_PR</name>
2511                <description>Protection context 14, privileged read enable.</description>
2512                <bitRange>[18:18]</bitRange>
2513                <access>read-write</access>
2514              </field>
2515              <field>
2516                <name>PC14_PW</name>
2517                <description>Protection context 14, privileged write enable.</description>
2518                <bitRange>[19:19]</bitRange>
2519                <access>read-write</access>
2520              </field>
2521              <field>
2522                <name>PC14_NS</name>
2523                <description>Protection context 14, non-secure.</description>
2524                <bitRange>[20:20]</bitRange>
2525                <access>read-write</access>
2526              </field>
2527              <field>
2528                <name>PC15_UR</name>
2529                <description>Protection context 15, user read enable.</description>
2530                <bitRange>[24:24]</bitRange>
2531                <access>read-write</access>
2532              </field>
2533              <field>
2534                <name>PC15_UW</name>
2535                <description>Protection context 15, user write enable.</description>
2536                <bitRange>[25:25]</bitRange>
2537                <access>read-write</access>
2538              </field>
2539              <field>
2540                <name>PC15_PR</name>
2541                <description>Protection context 15, privileged read enable.</description>
2542                <bitRange>[26:26]</bitRange>
2543                <access>read-write</access>
2544              </field>
2545              <field>
2546                <name>PC15_PW</name>
2547                <description>Protection context 15, privileged write enable.</description>
2548                <bitRange>[27:27]</bitRange>
2549                <access>read-write</access>
2550              </field>
2551              <field>
2552                <name>PC15_NS</name>
2553                <description>Protection context 15, non-secure.</description>
2554                <bitRange>[28:28]</bitRange>
2555                <access>read-write</access>
2556              </field>
2557            </fields>
2558          </register>
2559          <register>
2560            <name>MS_ADDR</name>
2561            <description>Master region, base address</description>
2562            <addressOffset>0x20</addressOffset>
2563            <size>32</size>
2564            <access>read-only</access>
2565            <resetValue>0x0</resetValue>
2566            <resetMask>0xFFFFFFC0</resetMask>
2567            <fields>
2568              <field>
2569                <name>ADDR26</name>
2570                <description>This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register.</description>
2571                <bitRange>[31:6]</bitRange>
2572                <access>read-only</access>
2573              </field>
2574            </fields>
2575          </register>
2576          <register>
2577            <name>MS_SIZE</name>
2578            <description>Master region, size</description>
2579            <addressOffset>0x24</addressOffset>
2580            <size>32</size>
2581            <access>read-only</access>
2582            <resetValue>0x85000000</resetValue>
2583            <resetMask>0x9F000000</resetMask>
2584            <fields>
2585              <field>
2586                <name>REGION_SIZE</name>
2587                <description>This field specifies the size of the master region:
2588'5': 64 B region
2589
2590The master region includes the SL_ADDR, SL_SIZE, SL_ATT0, ..., SL_ATT3, MS_ADDR, MS_SIZE, MS_ATT0, ..., MS_ATT3 registers. Therefore, the access privileges for all these registers is determined by MS_ATT0, ..., MS_ATT3.</description>
2591                <bitRange>[28:24]</bitRange>
2592                <access>read-only</access>
2593              </field>
2594              <field>
2595                <name>VALID</name>
2596                <description>Master region enable:
2597'1': Enabled.</description>
2598                <bitRange>[31:31]</bitRange>
2599                <access>read-only</access>
2600              </field>
2601            </fields>
2602          </register>
2603          <register>
2604            <name>MS_ATT0</name>
2605            <description>Master attributes 0</description>
2606            <addressOffset>0x30</addressOffset>
2607            <size>32</size>
2608            <access>read-write</access>
2609            <resetValue>0x1F1F1F1F</resetValue>
2610            <resetMask>0x1F1F1F1F</resetMask>
2611            <fields>
2612              <field>
2613                <name>PC0_UR</name>
2614                <description>Protection context 0, user read enable:
2615'0': Disabled (user, read accesses are NOT allowed).
2616'1': Enabled (user, read accesses are allowed).</description>
2617                <bitRange>[0:0]</bitRange>
2618                <access>read-only</access>
2619              </field>
2620              <field>
2621                <name>PC0_UW</name>
2622                <description>Protection context 0, user write enable:
2623'0': Disabled (user, write accesses are NOT allowed).
2624'1': Enabled (user, write accesses are allowed).</description>
2625                <bitRange>[1:1]</bitRange>
2626                <access>read-only</access>
2627              </field>
2628              <field>
2629                <name>PC0_PR</name>
2630                <description>Protection context 0, privileged read enable:
2631'0': Disabled (privileged, read accesses are NOT allowed).
2632'1': Enabled (privileged, read accesses are allowed).</description>
2633                <bitRange>[2:2]</bitRange>
2634                <access>read-only</access>
2635              </field>
2636              <field>
2637                <name>PC0_PW</name>
2638                <description>Protection context 0, privileged write enable:
2639'0': Disabled (privileged, write accesses are NOT allowed).
2640'1': Enabled (privileged, write accesses are allowed).</description>
2641                <bitRange>[3:3]</bitRange>
2642                <access>read-only</access>
2643              </field>
2644              <field>
2645                <name>PC0_NS</name>
2646                <description>Protection context 0, non-secure:
2647'0': Secure (secure accesses allowed, non-secure access NOT allowed).
2648'1': Non-secure (both secure and non-secure accesses allowed).</description>
2649                <bitRange>[4:4]</bitRange>
2650                <access>read-only</access>
2651              </field>
2652              <field>
2653                <name>PC1_UR</name>
2654                <description>Protection context 1, user read enable.</description>
2655                <bitRange>[8:8]</bitRange>
2656                <access>read-only</access>
2657              </field>
2658              <field>
2659                <name>PC1_UW</name>
2660                <description>Protection context 1, user write enable.</description>
2661                <bitRange>[9:9]</bitRange>
2662                <access>read-write</access>
2663              </field>
2664              <field>
2665                <name>PC1_PR</name>
2666                <description>Protection context 1, privileged read enable.</description>
2667                <bitRange>[10:10]</bitRange>
2668                <access>read-only</access>
2669              </field>
2670              <field>
2671                <name>PC1_PW</name>
2672                <description>Protection context 1, privileged write enable.</description>
2673                <bitRange>[11:11]</bitRange>
2674                <access>read-write</access>
2675              </field>
2676              <field>
2677                <name>PC1_NS</name>
2678                <description>Protection context 1, non-secure.</description>
2679                <bitRange>[12:12]</bitRange>
2680                <access>read-write</access>
2681              </field>
2682              <field>
2683                <name>PC2_UR</name>
2684                <description>Protection context 2, user read enable.</description>
2685                <bitRange>[16:16]</bitRange>
2686                <access>read-only</access>
2687              </field>
2688              <field>
2689                <name>PC2_UW</name>
2690                <description>Protection context 2, user write enable.</description>
2691                <bitRange>[17:17]</bitRange>
2692                <access>read-write</access>
2693              </field>
2694              <field>
2695                <name>PC2_PR</name>
2696                <description>Protection context 2, privileged read enable.</description>
2697                <bitRange>[18:18]</bitRange>
2698                <access>read-only</access>
2699              </field>
2700              <field>
2701                <name>PC2_PW</name>
2702                <description>Protection context 2, privileged write enable.</description>
2703                <bitRange>[19:19]</bitRange>
2704                <access>read-write</access>
2705              </field>
2706              <field>
2707                <name>PC2_NS</name>
2708                <description>Protection context 2, non-secure.</description>
2709                <bitRange>[20:20]</bitRange>
2710                <access>read-write</access>
2711              </field>
2712              <field>
2713                <name>PC3_UR</name>
2714                <description>Protection context 3, user read enable.</description>
2715                <bitRange>[24:24]</bitRange>
2716                <access>read-only</access>
2717              </field>
2718              <field>
2719                <name>PC3_UW</name>
2720                <description>Protection context 3, user write enable.</description>
2721                <bitRange>[25:25]</bitRange>
2722                <access>read-write</access>
2723              </field>
2724              <field>
2725                <name>PC3_PR</name>
2726                <description>Protection context 3, privileged read enable.</description>
2727                <bitRange>[26:26]</bitRange>
2728                <access>read-only</access>
2729              </field>
2730              <field>
2731                <name>PC3_PW</name>
2732                <description>Protection context 3, privileged write enable.</description>
2733                <bitRange>[27:27]</bitRange>
2734                <access>read-write</access>
2735              </field>
2736              <field>
2737                <name>PC3_NS</name>
2738                <description>Protection context 3, non-secure.</description>
2739                <bitRange>[28:28]</bitRange>
2740                <access>read-write</access>
2741              </field>
2742            </fields>
2743          </register>
2744          <register>
2745            <name>MS_ATT1</name>
2746            <description>Master attributes 1</description>
2747            <addressOffset>0x34</addressOffset>
2748            <size>32</size>
2749            <access>read-write</access>
2750            <resetValue>0x1F1F1F1F</resetValue>
2751            <resetMask>0x1F1F1F1F</resetMask>
2752            <fields>
2753              <field>
2754                <name>PC4_UR</name>
2755                <description>Protection context 4, user read enable.</description>
2756                <bitRange>[0:0]</bitRange>
2757                <access>read-only</access>
2758              </field>
2759              <field>
2760                <name>PC4_UW</name>
2761                <description>Protection context 4, user write enable.</description>
2762                <bitRange>[1:1]</bitRange>
2763                <access>read-write</access>
2764              </field>
2765              <field>
2766                <name>PC4_PR</name>
2767                <description>Protection context 4, privileged read enable.</description>
2768                <bitRange>[2:2]</bitRange>
2769                <access>read-only</access>
2770              </field>
2771              <field>
2772                <name>PC4_PW</name>
2773                <description>Protection context 4, privileged write enable.</description>
2774                <bitRange>[3:3]</bitRange>
2775                <access>read-write</access>
2776              </field>
2777              <field>
2778                <name>PC4_NS</name>
2779                <description>Protection context 4, non-secure.</description>
2780                <bitRange>[4:4]</bitRange>
2781                <access>read-write</access>
2782              </field>
2783              <field>
2784                <name>PC5_UR</name>
2785                <description>Protection context 5, user read enable.</description>
2786                <bitRange>[8:8]</bitRange>
2787                <access>read-only</access>
2788              </field>
2789              <field>
2790                <name>PC5_UW</name>
2791                <description>Protection context 5, user write enable.</description>
2792                <bitRange>[9:9]</bitRange>
2793                <access>read-write</access>
2794              </field>
2795              <field>
2796                <name>PC5_PR</name>
2797                <description>Protection context 5, privileged read enable.</description>
2798                <bitRange>[10:10]</bitRange>
2799                <access>read-only</access>
2800              </field>
2801              <field>
2802                <name>PC5_PW</name>
2803                <description>Protection context 5, privileged write enable.</description>
2804                <bitRange>[11:11]</bitRange>
2805                <access>read-write</access>
2806              </field>
2807              <field>
2808                <name>PC5_NS</name>
2809                <description>Protection context 5, non-secure.</description>
2810                <bitRange>[12:12]</bitRange>
2811                <access>read-write</access>
2812              </field>
2813              <field>
2814                <name>PC6_UR</name>
2815                <description>Protection context 6, user read enable.</description>
2816                <bitRange>[16:16]</bitRange>
2817                <access>read-only</access>
2818              </field>
2819              <field>
2820                <name>PC6_UW</name>
2821                <description>Protection context 6, user write enable.</description>
2822                <bitRange>[17:17]</bitRange>
2823                <access>read-write</access>
2824              </field>
2825              <field>
2826                <name>PC6_PR</name>
2827                <description>Protection context 6, privileged read enable.</description>
2828                <bitRange>[18:18]</bitRange>
2829                <access>read-only</access>
2830              </field>
2831              <field>
2832                <name>PC6_PW</name>
2833                <description>Protection context 6, privileged write enable.</description>
2834                <bitRange>[19:19]</bitRange>
2835                <access>read-write</access>
2836              </field>
2837              <field>
2838                <name>PC6_NS</name>
2839                <description>Protection context 6, non-secure.</description>
2840                <bitRange>[20:20]</bitRange>
2841                <access>read-write</access>
2842              </field>
2843              <field>
2844                <name>PC7_UR</name>
2845                <description>Protection context 7, user read enable.</description>
2846                <bitRange>[24:24]</bitRange>
2847                <access>read-only</access>
2848              </field>
2849              <field>
2850                <name>PC7_UW</name>
2851                <description>Protection context 7, user write enable.</description>
2852                <bitRange>[25:25]</bitRange>
2853                <access>read-write</access>
2854              </field>
2855              <field>
2856                <name>PC7_PR</name>
2857                <description>Protection context 7, privileged read enable.</description>
2858                <bitRange>[26:26]</bitRange>
2859                <access>read-only</access>
2860              </field>
2861              <field>
2862                <name>PC7_PW</name>
2863                <description>Protection context 7, privileged write enable.</description>
2864                <bitRange>[27:27]</bitRange>
2865                <access>read-write</access>
2866              </field>
2867              <field>
2868                <name>PC7_NS</name>
2869                <description>Protection context 7, non-secure.</description>
2870                <bitRange>[28:28]</bitRange>
2871                <access>read-write</access>
2872              </field>
2873            </fields>
2874          </register>
2875          <register>
2876            <name>MS_ATT2</name>
2877            <description>Master attributes 2</description>
2878            <addressOffset>0x38</addressOffset>
2879            <size>32</size>
2880            <access>read-write</access>
2881            <resetValue>0x1F1F1F1F</resetValue>
2882            <resetMask>0x1F1F1F1F</resetMask>
2883            <fields>
2884              <field>
2885                <name>PC8_UR</name>
2886                <description>Protection context 8, user read enable.</description>
2887                <bitRange>[0:0]</bitRange>
2888                <access>read-only</access>
2889              </field>
2890              <field>
2891                <name>PC8_UW</name>
2892                <description>Protection context 8, user write enable.</description>
2893                <bitRange>[1:1]</bitRange>
2894                <access>read-write</access>
2895              </field>
2896              <field>
2897                <name>PC8_PR</name>
2898                <description>Protection context 8, privileged read enable.</description>
2899                <bitRange>[2:2]</bitRange>
2900                <access>read-only</access>
2901              </field>
2902              <field>
2903                <name>PC8_PW</name>
2904                <description>Protection context 8, privileged write enable.</description>
2905                <bitRange>[3:3]</bitRange>
2906                <access>read-write</access>
2907              </field>
2908              <field>
2909                <name>PC8_NS</name>
2910                <description>Protection context 8, non-secure.</description>
2911                <bitRange>[4:4]</bitRange>
2912                <access>read-write</access>
2913              </field>
2914              <field>
2915                <name>PC9_UR</name>
2916                <description>Protection context 9, user read enable.</description>
2917                <bitRange>[8:8]</bitRange>
2918                <access>read-only</access>
2919              </field>
2920              <field>
2921                <name>PC9_UW</name>
2922                <description>Protection context 9, user write enable.</description>
2923                <bitRange>[9:9]</bitRange>
2924                <access>read-write</access>
2925              </field>
2926              <field>
2927                <name>PC9_PR</name>
2928                <description>Protection context 9, privileged read enable.</description>
2929                <bitRange>[10:10]</bitRange>
2930                <access>read-only</access>
2931              </field>
2932              <field>
2933                <name>PC9_PW</name>
2934                <description>Protection context 9, privileged write enable.</description>
2935                <bitRange>[11:11]</bitRange>
2936                <access>read-write</access>
2937              </field>
2938              <field>
2939                <name>PC9_NS</name>
2940                <description>Protection context 9, non-secure.</description>
2941                <bitRange>[12:12]</bitRange>
2942                <access>read-write</access>
2943              </field>
2944              <field>
2945                <name>PC10_UR</name>
2946                <description>Protection context 10, user read enable.</description>
2947                <bitRange>[16:16]</bitRange>
2948                <access>read-only</access>
2949              </field>
2950              <field>
2951                <name>PC10_UW</name>
2952                <description>Protection context 10, user write enable.</description>
2953                <bitRange>[17:17]</bitRange>
2954                <access>read-write</access>
2955              </field>
2956              <field>
2957                <name>PC10_PR</name>
2958                <description>Protection context 10, privileged read enable.</description>
2959                <bitRange>[18:18]</bitRange>
2960                <access>read-only</access>
2961              </field>
2962              <field>
2963                <name>PC10_PW</name>
2964                <description>Protection context 10, privileged write enable.</description>
2965                <bitRange>[19:19]</bitRange>
2966                <access>read-write</access>
2967              </field>
2968              <field>
2969                <name>PC10_NS</name>
2970                <description>Protection context 10, non-secure.</description>
2971                <bitRange>[20:20]</bitRange>
2972                <access>read-write</access>
2973              </field>
2974              <field>
2975                <name>PC11_UR</name>
2976                <description>Protection context 11, user read enable.</description>
2977                <bitRange>[24:24]</bitRange>
2978                <access>read-only</access>
2979              </field>
2980              <field>
2981                <name>PC11_UW</name>
2982                <description>Protection context 11, user write enable.</description>
2983                <bitRange>[25:25]</bitRange>
2984                <access>read-write</access>
2985              </field>
2986              <field>
2987                <name>PC11_PR</name>
2988                <description>Protection context 11, privileged read enable.</description>
2989                <bitRange>[26:26]</bitRange>
2990                <access>read-only</access>
2991              </field>
2992              <field>
2993                <name>PC11_PW</name>
2994                <description>Protection context 11, privileged write enable.</description>
2995                <bitRange>[27:27]</bitRange>
2996                <access>read-write</access>
2997              </field>
2998              <field>
2999                <name>PC11_NS</name>
3000                <description>Protection context 11, non-secure.</description>
3001                <bitRange>[28:28]</bitRange>
3002                <access>read-write</access>
3003              </field>
3004            </fields>
3005          </register>
3006          <register>
3007            <name>MS_ATT3</name>
3008            <description>Master attributes 3</description>
3009            <addressOffset>0x3C</addressOffset>
3010            <size>32</size>
3011            <access>read-write</access>
3012            <resetValue>0x1F1F1F1F</resetValue>
3013            <resetMask>0x1F1F1F1F</resetMask>
3014            <fields>
3015              <field>
3016                <name>PC12_UR</name>
3017                <description>Protection context 12, user read enable.</description>
3018                <bitRange>[0:0]</bitRange>
3019                <access>read-only</access>
3020              </field>
3021              <field>
3022                <name>PC12_UW</name>
3023                <description>Protection context 12, user write enable.</description>
3024                <bitRange>[1:1]</bitRange>
3025                <access>read-write</access>
3026              </field>
3027              <field>
3028                <name>PC12_PR</name>
3029                <description>Protection context 12, privileged read enable.</description>
3030                <bitRange>[2:2]</bitRange>
3031                <access>read-only</access>
3032              </field>
3033              <field>
3034                <name>PC12_PW</name>
3035                <description>Protection context 12, privileged write enable.</description>
3036                <bitRange>[3:3]</bitRange>
3037                <access>read-write</access>
3038              </field>
3039              <field>
3040                <name>PC12_NS</name>
3041                <description>Protection context 12, non-secure.</description>
3042                <bitRange>[4:4]</bitRange>
3043                <access>read-write</access>
3044              </field>
3045              <field>
3046                <name>PC13_UR</name>
3047                <description>Protection context 13, user read enable.</description>
3048                <bitRange>[8:8]</bitRange>
3049                <access>read-only</access>
3050              </field>
3051              <field>
3052                <name>PC13_UW</name>
3053                <description>Protection context 13, user write enable.</description>
3054                <bitRange>[9:9]</bitRange>
3055                <access>read-write</access>
3056              </field>
3057              <field>
3058                <name>PC13_PR</name>
3059                <description>Protection context 13, privileged read enable.</description>
3060                <bitRange>[10:10]</bitRange>
3061                <access>read-only</access>
3062              </field>
3063              <field>
3064                <name>PC13_PW</name>
3065                <description>Protection context 13, privileged write enable.</description>
3066                <bitRange>[11:11]</bitRange>
3067                <access>read-write</access>
3068              </field>
3069              <field>
3070                <name>PC13_NS</name>
3071                <description>Protection context 13, non-secure.</description>
3072                <bitRange>[12:12]</bitRange>
3073                <access>read-write</access>
3074              </field>
3075              <field>
3076                <name>PC14_UR</name>
3077                <description>Protection context 14, user read enable.</description>
3078                <bitRange>[16:16]</bitRange>
3079                <access>read-only</access>
3080              </field>
3081              <field>
3082                <name>PC14_UW</name>
3083                <description>Protection context 14, user write enable.</description>
3084                <bitRange>[17:17]</bitRange>
3085                <access>read-write</access>
3086              </field>
3087              <field>
3088                <name>PC14_PR</name>
3089                <description>Protection context 14, privileged read enable.</description>
3090                <bitRange>[18:18]</bitRange>
3091                <access>read-only</access>
3092              </field>
3093              <field>
3094                <name>PC14_PW</name>
3095                <description>Protection context 14, privileged write enable.</description>
3096                <bitRange>[19:19]</bitRange>
3097                <access>read-write</access>
3098              </field>
3099              <field>
3100                <name>PC14_NS</name>
3101                <description>Protection context 14, non-secure.</description>
3102                <bitRange>[20:20]</bitRange>
3103                <access>read-write</access>
3104              </field>
3105              <field>
3106                <name>PC15_UR</name>
3107                <description>Protection context 15, user read enable.</description>
3108                <bitRange>[24:24]</bitRange>
3109                <access>read-only</access>
3110              </field>
3111              <field>
3112                <name>PC15_UW</name>
3113                <description>Protection context 15, user write enable.</description>
3114                <bitRange>[25:25]</bitRange>
3115                <access>read-write</access>
3116              </field>
3117              <field>
3118                <name>PC15_PR</name>
3119                <description>Protection context 15, privileged read enable.</description>
3120                <bitRange>[26:26]</bitRange>
3121                <access>read-only</access>
3122              </field>
3123              <field>
3124                <name>PC15_PW</name>
3125                <description>Protection context 15, privileged write enable.</description>
3126                <bitRange>[27:27]</bitRange>
3127                <access>read-write</access>
3128              </field>
3129              <field>
3130                <name>PC15_NS</name>
3131                <description>Protection context 15, non-secure.</description>
3132                <bitRange>[28:28]</bitRange>
3133                <access>read-write</access>
3134              </field>
3135            </fields>
3136          </register>
3137        </cluster>
3138      </registers>
3139    </peripheral>
3140    <peripheral>
3141      <name>CPUSS</name>
3142      <description>CPU subsystem (CPUSS)</description>
3143      <baseAddress>0x40200000</baseAddress>
3144      <addressBlock>
3145        <offset>0</offset>
3146        <size>65536</size>
3147        <usage>registers</usage>
3148      </addressBlock>
3149      <interrupt>
3150        <name>ioss_interrupts_gpio_dpslp_0</name>
3151        <description>GPIO Port Interrupt #0</description>
3152        <value>0</value>
3153      </interrupt>
3154      <interrupt>
3155        <name>ioss_interrupts_gpio_dpslp_1</name>
3156        <description>GPIO Port Interrupt #1</description>
3157        <value>1</value>
3158      </interrupt>
3159      <interrupt>
3160        <name>ioss_interrupts_gpio_dpslp_4</name>
3161        <description>GPIO Port Interrupt #4</description>
3162        <value>2</value>
3163      </interrupt>
3164      <interrupt>
3165        <name>ioss_interrupts_gpio_dpslp_5</name>
3166        <description>GPIO Port Interrupt #5</description>
3167        <value>3</value>
3168      </interrupt>
3169      <interrupt>
3170        <name>ioss_interrupts_gpio_dpslp_6</name>
3171        <description>GPIO Port Interrupt #6</description>
3172        <value>4</value>
3173      </interrupt>
3174      <interrupt>
3175        <name>ioss_interrupts_gpio_dpslp_7</name>
3176        <description>GPIO Port Interrupt #7</description>
3177        <value>5</value>
3178      </interrupt>
3179      <interrupt>
3180        <name>ioss_interrupts_gpio_dpslp_8</name>
3181        <description>GPIO Port Interrupt #8</description>
3182        <value>6</value>
3183      </interrupt>
3184      <interrupt>
3185        <name>ioss_interrupts_gpio_dpslp_9</name>
3186        <description>GPIO Port Interrupt #9</description>
3187        <value>7</value>
3188      </interrupt>
3189      <interrupt>
3190        <name>ioss_interrupts_gpio_dpslp_10</name>
3191        <description>GPIO Port Interrupt #10</description>
3192        <value>8</value>
3193      </interrupt>
3194      <interrupt>
3195        <name>ioss_interrupts_gpio_dpslp_11</name>
3196        <description>GPIO Port Interrupt #11</description>
3197        <value>9</value>
3198      </interrupt>
3199      <interrupt>
3200        <name>ioss_interrupts_gpio_dpslp_12</name>
3201        <description>GPIO Port Interrupt #12</description>
3202        <value>10</value>
3203      </interrupt>
3204      <interrupt>
3205        <name>ioss_interrupts_gpio_dpslp_13</name>
3206        <description>GPIO Port Interrupt #13</description>
3207        <value>11</value>
3208      </interrupt>
3209      <interrupt>
3210        <name>ioss_interrupt_gpio_dpslp</name>
3211        <description>GPIO All Ports</description>
3212        <value>12</value>
3213      </interrupt>
3214      <interrupt>
3215        <name>ioss_interrupt_vdd</name>
3216        <description>GPIO Supply Detect Interrupt</description>
3217        <value>13</value>
3218      </interrupt>
3219      <interrupt>
3220        <name>scb_0_interrupt</name>
3221        <description>Serial Communication Block #6 (DeepSleep capable)</description>
3222        <value>14</value>
3223      </interrupt>
3224      <interrupt>
3225        <name>srss_interrupt_mcwdt_0</name>
3226        <description>Multi Counter Watchdog Timer interrupt</description>
3227        <value>15</value>
3228      </interrupt>
3229      <interrupt>
3230        <name>srss_interrupt_mcwdt_1</name>
3231        <description>Multi Counter Watchdog Timer interrupt</description>
3232        <value>16</value>
3233      </interrupt>
3234      <interrupt>
3235        <name>usbhsdev_interrupt_u2d_dpslp_o</name>
3236        <description>USBHS DEV interuupt</description>
3237        <value>17</value>
3238      </interrupt>
3239      <interrupt>
3240        <name>srss_interrupt</name>
3241        <description>Other combined Interrupts for SRSS (LVD, WDT, CLKCAL)</description>
3242        <value>18</value>
3243      </interrupt>
3244      <interrupt>
3245        <name>cpuss_interrupts_ipc_0</name>
3246        <description>CPUSS Inter Process Communication Interrupt #0</description>
3247        <value>19</value>
3248      </interrupt>
3249      <interrupt>
3250        <name>cpuss_interrupts_ipc_1</name>
3251        <description>CPUSS Inter Process Communication Interrupt #1</description>
3252        <value>20</value>
3253      </interrupt>
3254      <interrupt>
3255        <name>cpuss_interrupts_ipc_2</name>
3256        <description>CPUSS Inter Process Communication Interrupt #2</description>
3257        <value>21</value>
3258      </interrupt>
3259      <interrupt>
3260        <name>cpuss_interrupts_ipc_3</name>
3261        <description>CPUSS Inter Process Communication Interrupt #3</description>
3262        <value>22</value>
3263      </interrupt>
3264      <interrupt>
3265        <name>cpuss_interrupts_ipc_4</name>
3266        <description>CPUSS Inter Process Communication Interrupt #4</description>
3267        <value>23</value>
3268      </interrupt>
3269      <interrupt>
3270        <name>cpuss_interrupts_ipc_5</name>
3271        <description>CPUSS Inter Process Communication Interrupt #5</description>
3272        <value>24</value>
3273      </interrupt>
3274      <interrupt>
3275        <name>cpuss_interrupts_ipc_6</name>
3276        <description>CPUSS Inter Process Communication Interrupt #6</description>
3277        <value>25</value>
3278      </interrupt>
3279      <interrupt>
3280        <name>cpuss_interrupts_ipc_7</name>
3281        <description>CPUSS Inter Process Communication Interrupt #7</description>
3282        <value>26</value>
3283      </interrupt>
3284      <interrupt>
3285        <name>cpuss_interrupts_ipc_8</name>
3286        <description>CPUSS Inter Process Communication Interrupt #8</description>
3287        <value>27</value>
3288      </interrupt>
3289      <interrupt>
3290        <name>cpuss_interrupts_ipc_9</name>
3291        <description>CPUSS Inter Process Communication Interrupt #9</description>
3292        <value>28</value>
3293      </interrupt>
3294      <interrupt>
3295        <name>cpuss_interrupts_ipc_10</name>
3296        <description>CPUSS Inter Process Communication Interrupt #10</description>
3297        <value>29</value>
3298      </interrupt>
3299      <interrupt>
3300        <name>cpuss_interrupts_ipc_11</name>
3301        <description>CPUSS Inter Process Communication Interrupt #11</description>
3302        <value>30</value>
3303      </interrupt>
3304      <interrupt>
3305        <name>cpuss_interrupts_ipc_12</name>
3306        <description>CPUSS Inter Process Communication Interrupt #12</description>
3307        <value>31</value>
3308      </interrupt>
3309      <interrupt>
3310        <name>cpuss_interrupts_ipc_13</name>
3311        <description>CPUSS Inter Process Communication Interrupt #13</description>
3312        <value>32</value>
3313      </interrupt>
3314      <interrupt>
3315        <name>cpuss_interrupts_ipc_14</name>
3316        <description>CPUSS Inter Process Communication Interrupt #14</description>
3317        <value>33</value>
3318      </interrupt>
3319      <interrupt>
3320        <name>cpuss_interrupts_ipc_15</name>
3321        <description>CPUSS Inter Process Communication Interrupt #15</description>
3322        <value>34</value>
3323      </interrupt>
3324      <interrupt>
3325        <name>scb_1_interrupt</name>
3326        <description>Serial Communication Block #1</description>
3327        <value>46</value>
3328      </interrupt>
3329      <interrupt>
3330        <name>scb_2_interrupt</name>
3331        <description>Serial Communication Block #2</description>
3332        <value>47</value>
3333      </interrupt>
3334      <interrupt>
3335        <name>scb_3_interrupt</name>
3336        <description>Serial Communication Block #3</description>
3337        <value>48</value>
3338      </interrupt>
3339      <interrupt>
3340        <name>scb_4_interrupt</name>
3341        <description>Serial Communication Block #4</description>
3342        <value>49</value>
3343      </interrupt>
3344      <interrupt>
3345        <name>scb_5_interrupt</name>
3346        <description>Serial Communication Block #5</description>
3347        <value>50</value>
3348      </interrupt>
3349      <interrupt>
3350        <name>scb_6_interrupt</name>
3351        <description>Serial Communication Block #6</description>
3352        <value>51</value>
3353      </interrupt>
3354      <interrupt>
3355        <name>cpuss_interrupts_dmac_0</name>
3356        <description>CPUSS DMAC, Channel #0</description>
3357        <value>52</value>
3358      </interrupt>
3359      <interrupt>
3360        <name>cpuss_interrupts_dmac_1</name>
3361        <description>CPUSS DMAC, Channel #1</description>
3362        <value>53</value>
3363      </interrupt>
3364      <interrupt>
3365        <name>cpuss_interrupts_dmac_2</name>
3366        <description>CPUSS DMAC, Channel #2</description>
3367        <value>54</value>
3368      </interrupt>
3369      <interrupt>
3370        <name>cpuss_interrupts_dmac_3</name>
3371        <description>CPUSS DMAC, Channel #3</description>
3372        <value>55</value>
3373      </interrupt>
3374      <interrupt>
3375        <name>cpuss_interrupts_dmac_4</name>
3376        <description>CPUSS DMAC, Channel #4</description>
3377        <value>56</value>
3378      </interrupt>
3379      <interrupt>
3380        <name>cpuss_interrupts_dmac_5</name>
3381        <description>CPUSS DMAC, Channel #5</description>
3382        <value>57</value>
3383      </interrupt>
3384      <interrupt>
3385        <name>cpuss_interrupts_dw0_0</name>
3386        <description>CPUSS DataWire #0, Channel #0</description>
3387        <value>58</value>
3388      </interrupt>
3389      <interrupt>
3390        <name>cpuss_interrupts_dw0_1</name>
3391        <description>CPUSS DataWire #0, Channel #1</description>
3392        <value>59</value>
3393      </interrupt>
3394      <interrupt>
3395        <name>cpuss_interrupts_dw0_2</name>
3396        <description>CPUSS DataWire #0, Channel #2</description>
3397        <value>60</value>
3398      </interrupt>
3399      <interrupt>
3400        <name>cpuss_interrupts_dw0_3</name>
3401        <description>CPUSS DataWire #0, Channel #3</description>
3402        <value>61</value>
3403      </interrupt>
3404      <interrupt>
3405        <name>cpuss_interrupts_dw0_4</name>
3406        <description>CPUSS DataWire #0, Channel #4</description>
3407        <value>62</value>
3408      </interrupt>
3409      <interrupt>
3410        <name>cpuss_interrupts_dw0_5</name>
3411        <description>CPUSS DataWire #0, Channel #5</description>
3412        <value>63</value>
3413      </interrupt>
3414      <interrupt>
3415        <name>cpuss_interrupts_dw0_6</name>
3416        <description>CPUSS DataWire #0, Channel #6</description>
3417        <value>64</value>
3418      </interrupt>
3419      <interrupt>
3420        <name>cpuss_interrupts_dw0_7</name>
3421        <description>CPUSS DataWire #0, Channel #7</description>
3422        <value>65</value>
3423      </interrupt>
3424      <interrupt>
3425        <name>cpuss_interrupts_dw0_8</name>
3426        <description>CPUSS DataWire #0, Channel #8</description>
3427        <value>66</value>
3428      </interrupt>
3429      <interrupt>
3430        <name>cpuss_interrupts_dw0_9</name>
3431        <description>CPUSS DataWire #0, Channel #9</description>
3432        <value>67</value>
3433      </interrupt>
3434      <interrupt>
3435        <name>cpuss_interrupts_dw0_10</name>
3436        <description>CPUSS DataWire #0, Channel #10</description>
3437        <value>68</value>
3438      </interrupt>
3439      <interrupt>
3440        <name>cpuss_interrupts_dw0_11</name>
3441        <description>CPUSS DataWire #0, Channel #11</description>
3442        <value>69</value>
3443      </interrupt>
3444      <interrupt>
3445        <name>cpuss_interrupts_dw0_12</name>
3446        <description>CPUSS DataWire #0, Channel #12</description>
3447        <value>70</value>
3448      </interrupt>
3449      <interrupt>
3450        <name>cpuss_interrupts_dw0_13</name>
3451        <description>CPUSS DataWire #0, Channel #13</description>
3452        <value>71</value>
3453      </interrupt>
3454      <interrupt>
3455        <name>cpuss_interrupts_dw0_14</name>
3456        <description>CPUSS DataWire #0, Channel #14</description>
3457        <value>72</value>
3458      </interrupt>
3459      <interrupt>
3460        <name>cpuss_interrupts_dw0_15</name>
3461        <description>CPUSS DataWire #0, Channel #15</description>
3462        <value>73</value>
3463      </interrupt>
3464      <interrupt>
3465        <name>cpuss_interrupts_dw0_16</name>
3466        <description>CPUSS DataWire #0, Channel #16</description>
3467        <value>74</value>
3468      </interrupt>
3469      <interrupt>
3470        <name>cpuss_interrupts_dw0_17</name>
3471        <description>CPUSS DataWire #0, Channel #17</description>
3472        <value>75</value>
3473      </interrupt>
3474      <interrupt>
3475        <name>cpuss_interrupts_dw0_18</name>
3476        <description>CPUSS DataWire #0, Channel #18</description>
3477        <value>76</value>
3478      </interrupt>
3479      <interrupt>
3480        <name>cpuss_interrupts_dw0_19</name>
3481        <description>CPUSS DataWire #0, Channel #19</description>
3482        <value>77</value>
3483      </interrupt>
3484      <interrupt>
3485        <name>cpuss_interrupts_dw0_20</name>
3486        <description>CPUSS DataWire #0, Channel #20</description>
3487        <value>78</value>
3488      </interrupt>
3489      <interrupt>
3490        <name>cpuss_interrupts_dw0_21</name>
3491        <description>CPUSS DataWire #0, Channel #21</description>
3492        <value>79</value>
3493      </interrupt>
3494      <interrupt>
3495        <name>cpuss_interrupts_dw0_22</name>
3496        <description>CPUSS DataWire #0, Channel #22</description>
3497        <value>80</value>
3498      </interrupt>
3499      <interrupt>
3500        <name>cpuss_interrupts_dw0_23</name>
3501        <description>CPUSS DataWire #0, Channel #23</description>
3502        <value>81</value>
3503      </interrupt>
3504      <interrupt>
3505        <name>cpuss_interrupts_dw1_0</name>
3506        <description>CPUSS DataWire #1, Channel #0</description>
3507        <value>82</value>
3508      </interrupt>
3509      <interrupt>
3510        <name>cpuss_interrupts_dw1_1</name>
3511        <description>CPUSS DataWire #1, Channel #1</description>
3512        <value>83</value>
3513      </interrupt>
3514      <interrupt>
3515        <name>cpuss_interrupts_dw1_2</name>
3516        <description>CPUSS DataWire #1, Channel #2</description>
3517        <value>84</value>
3518      </interrupt>
3519      <interrupt>
3520        <name>cpuss_interrupts_dw1_3</name>
3521        <description>CPUSS DataWire #1, Channel #3</description>
3522        <value>85</value>
3523      </interrupt>
3524      <interrupt>
3525        <name>cpuss_interrupts_dw1_4</name>
3526        <description>CPUSS DataWire #1, Channel #4</description>
3527        <value>86</value>
3528      </interrupt>
3529      <interrupt>
3530        <name>cpuss_interrupts_dw1_5</name>
3531        <description>CPUSS DataWire #1, Channel #5</description>
3532        <value>87</value>
3533      </interrupt>
3534      <interrupt>
3535        <name>cpuss_interrupts_dw1_6</name>
3536        <description>CPUSS DataWire #1, Channel #6</description>
3537        <value>88</value>
3538      </interrupt>
3539      <interrupt>
3540        <name>cpuss_interrupts_dw1_7</name>
3541        <description>CPUSS DataWire #1, Channel #7</description>
3542        <value>89</value>
3543      </interrupt>
3544      <interrupt>
3545        <name>cpuss_interrupts_dw1_8</name>
3546        <description>CPUSS DataWire #1, Channel #8</description>
3547        <value>90</value>
3548      </interrupt>
3549      <interrupt>
3550        <name>cpuss_interrupts_dw1_9</name>
3551        <description>CPUSS DataWire #1, Channel #9</description>
3552        <value>91</value>
3553      </interrupt>
3554      <interrupt>
3555        <name>cpuss_interrupts_dw1_10</name>
3556        <description>CPUSS DataWire #1, Channel #10</description>
3557        <value>92</value>
3558      </interrupt>
3559      <interrupt>
3560        <name>cpuss_interrupts_dw1_11</name>
3561        <description>CPUSS DataWire #1, Channel #11</description>
3562        <value>93</value>
3563      </interrupt>
3564      <interrupt>
3565        <name>cpuss_interrupts_dw1_12</name>
3566        <description>CPUSS DataWire #1, Channel #12</description>
3567        <value>94</value>
3568      </interrupt>
3569      <interrupt>
3570        <name>cpuss_interrupts_dw1_13</name>
3571        <description>CPUSS DataWire #1, Channel #13</description>
3572        <value>95</value>
3573      </interrupt>
3574      <interrupt>
3575        <name>cpuss_interrupts_dw1_14</name>
3576        <description>CPUSS DataWire #1, Channel #14</description>
3577        <value>96</value>
3578      </interrupt>
3579      <interrupt>
3580        <name>cpuss_interrupts_dw1_15</name>
3581        <description>CPUSS DataWire #1, Channel #15</description>
3582        <value>97</value>
3583      </interrupt>
3584      <interrupt>
3585        <name>cpuss_interrupts_dw1_16</name>
3586        <description>CPUSS DataWire #1, Channel #16</description>
3587        <value>98</value>
3588      </interrupt>
3589      <interrupt>
3590        <name>cpuss_interrupts_dw1_17</name>
3591        <description>CPUSS DataWire #1, Channel #17</description>
3592        <value>99</value>
3593      </interrupt>
3594      <interrupt>
3595        <name>cpuss_interrupts_dw1_18</name>
3596        <description>CPUSS DataWire #1, Channel #18</description>
3597        <value>100</value>
3598      </interrupt>
3599      <interrupt>
3600        <name>cpuss_interrupts_dw1_19</name>
3601        <description>CPUSS DataWire #1, Channel #19</description>
3602        <value>101</value>
3603      </interrupt>
3604      <interrupt>
3605        <name>cpuss_interrupts_dw1_20</name>
3606        <description>CPUSS DataWire #1, Channel #20</description>
3607        <value>102</value>
3608      </interrupt>
3609      <interrupt>
3610        <name>cpuss_interrupts_dw1_21</name>
3611        <description>CPUSS DataWire #1, Channel #21</description>
3612        <value>103</value>
3613      </interrupt>
3614      <interrupt>
3615        <name>cpuss_interrupts_dw1_22</name>
3616        <description>CPUSS DataWire #1, Channel #22</description>
3617        <value>104</value>
3618      </interrupt>
3619      <interrupt>
3620        <name>cpuss_interrupts_dw1_23</name>
3621        <description>CPUSS DataWire #1, Channel #23</description>
3622        <value>105</value>
3623      </interrupt>
3624      <interrupt>
3625        <name>cpuss_interrupts_fault_0</name>
3626        <description>CPUSS Fault Structure Interrupt #0</description>
3627        <value>106</value>
3628      </interrupt>
3629      <interrupt>
3630        <name>cpuss_interrupts_fault_1</name>
3631        <description>CPUSS Fault Structure Interrupt #1</description>
3632        <value>107</value>
3633      </interrupt>
3634      <interrupt>
3635        <name>cpuss_interrupt_crypto</name>
3636        <description>CRYPTO Accelerator Interrupt</description>
3637        <value>108</value>
3638      </interrupt>
3639      <interrupt>
3640        <name>cpuss_interrupt_fm</name>
3641        <description>FLASH Macro Interrupt</description>
3642        <value>109</value>
3643      </interrupt>
3644      <interrupt>
3645        <name>cpuss_interrupts_cm4_fp</name>
3646        <description>Floating Point operation fault</description>
3647        <value>110</value>
3648      </interrupt>
3649      <interrupt>
3650        <name>cpuss_interrupts_cm0_cti_0</name>
3651        <description>CM0+ CTI #0</description>
3652        <value>111</value>
3653      </interrupt>
3654      <interrupt>
3655        <name>cpuss_interrupts_cm0_cti_1</name>
3656        <description>CM0+ CTI #1</description>
3657        <value>112</value>
3658      </interrupt>
3659      <interrupt>
3660        <name>cpuss_interrupts_cm4_cti_0</name>
3661        <description>CM4 CTI #0</description>
3662        <value>113</value>
3663      </interrupt>
3664      <interrupt>
3665        <name>cpuss_interrupts_cm4_cti_1</name>
3666        <description>CM4 CTI #1</description>
3667        <value>114</value>
3668      </interrupt>
3669      <interrupt>
3670        <name>tcpwm_0_interrupts_0</name>
3671        <description>TCPWM #0, Counter #0</description>
3672        <value>115</value>
3673      </interrupt>
3674      <interrupt>
3675        <name>tcpwm_0_interrupts_1</name>
3676        <description>TCPWM #0, Counter #1</description>
3677        <value>116</value>
3678      </interrupt>
3679      <interrupt>
3680        <name>tcpwm_0_interrupts_2</name>
3681        <description>TCPWM #0, Counter #2</description>
3682        <value>117</value>
3683      </interrupt>
3684      <interrupt>
3685        <name>tcpwm_0_interrupts_3</name>
3686        <description>TCPWM #0, Counter #3</description>
3687        <value>118</value>
3688      </interrupt>
3689      <interrupt>
3690        <name>tcpwm_0_interrupts_4</name>
3691        <description>TCPWM #0, Counter #4</description>
3692        <value>119</value>
3693      </interrupt>
3694      <interrupt>
3695        <name>tcpwm_0_interrupts_5</name>
3696        <description>TCPWM #0, Counter #5</description>
3697        <value>120</value>
3698      </interrupt>
3699      <interrupt>
3700        <name>tcpwm_0_interrupts_6</name>
3701        <description>TCPWM #0, Counter #6</description>
3702        <value>121</value>
3703      </interrupt>
3704      <interrupt>
3705        <name>tcpwm_0_interrupts_7</name>
3706        <description>TCPWM #0, Counter #7</description>
3707        <value>122</value>
3708      </interrupt>
3709      <interrupt>
3710        <name>tdm_0_interrupts_rx_0</name>
3711        <description>TDM0 Audio interrupt RX</description>
3712        <value>123</value>
3713      </interrupt>
3714      <interrupt>
3715        <name>tdm_0_interrupts_tx_0</name>
3716        <description>TDM0 Audio interrupt TX</description>
3717        <value>124</value>
3718      </interrupt>
3719      <interrupt>
3720        <name>smif_interrupt</name>
3721        <description>Serial Memory Interface interrupt</description>
3722        <value>125</value>
3723      </interrupt>
3724      <interrupt>
3725        <name>usb_interrupt_hi</name>
3726        <description>USB Interrupt</description>
3727        <value>126</value>
3728      </interrupt>
3729      <interrupt>
3730        <name>usb_interrupt_med</name>
3731        <description>USB Interrupt</description>
3732        <value>127</value>
3733      </interrupt>
3734      <interrupt>
3735        <name>usb_interrupt_lo</name>
3736        <description>USB Interrupt</description>
3737        <value>128</value>
3738      </interrupt>
3739      <interrupt>
3740        <name>usbhsdev_interrupt_u2d_active_o</name>
3741        <description>USB HS dev Interrupt</description>
3742        <value>129</value>
3743      </interrupt>
3744      <interrupt>
3745        <name>canfd_0_interrupt0</name>
3746        <description>Can #0, Consolidated interrupt #0</description>
3747        <value>130</value>
3748      </interrupt>
3749      <interrupt>
3750        <name>canfd_0_interrupts0_0</name>
3751        <description>CAN #0, Interrupt #0, Channel #0</description>
3752        <value>131</value>
3753      </interrupt>
3754      <interrupt>
3755        <name>canfd_0_interrupts1_0</name>
3756        <description>CAN #0, Interrupt #1, Channel #0</description>
3757        <value>132</value>
3758      </interrupt>
3759      <interrupt>
3760        <name>pdm_0_interrupts_0</name>
3761        <description>PDM interrupt</description>
3762        <value>133</value>
3763      </interrupt>
3764      <interrupt>
3765        <name>pdm_0_interrupts_1</name>
3766        <description>PDM interrupt</description>
3767        <value>134</value>
3768      </interrupt>
3769      <interrupt>
3770        <name>lvds2usb32ss_lvds_int_o</name>
3771        <description />
3772        <value>135</value>
3773      </interrupt>
3774      <interrupt>
3775        <name>lvds2usb32ss_lvds_pdma_int_o</name>
3776        <description />
3777        <value>136</value>
3778      </interrupt>
3779      <interrupt>
3780        <name>lvds2usb32ss_lvds_wakeup_int_o</name>
3781        <description />
3782        <value>137</value>
3783      </interrupt>
3784      <interrupt>
3785        <name>lvds2usb32ss_usb32_egrs_dma_int_o</name>
3786        <description />
3787        <value>138</value>
3788      </interrupt>
3789      <interrupt>
3790        <name>lvds2usb32ss_usb32_ingrs_dma_int_o</name>
3791        <description />
3792        <value>139</value>
3793      </interrupt>
3794      <interrupt>
3795        <name>lvds2usb32ss_usb32_int_o</name>
3796        <description />
3797        <value>140</value>
3798      </interrupt>
3799      <interrupt>
3800        <name>lvds2usb32ss_usb32_wakeup_int_o</name>
3801        <description />
3802        <value>141</value>
3803      </interrupt>
3804      <registers>
3805        <register>
3806          <name>IDENTITY</name>
3807          <description>Identity</description>
3808          <addressOffset>0x0</addressOffset>
3809          <size>32</size>
3810          <access>read-only</access>
3811          <resetValue>0x0</resetValue>
3812          <resetMask>0x0</resetMask>
3813          <fields>
3814            <field>
3815              <name>P</name>
3816              <description>This field specifies the privileged setting ('0': user mode; '1': privileged mode) of the transfer that reads the register.</description>
3817              <bitRange>[0:0]</bitRange>
3818              <access>read-only</access>
3819            </field>
3820            <field>
3821              <name>NS</name>
3822              <description>This field specifies the security setting ('0': secure mode; '1': non-secure mode) of the transfer that reads the register.</description>
3823              <bitRange>[1:1]</bitRange>
3824              <access>read-only</access>
3825            </field>
3826            <field>
3827              <name>PC</name>
3828              <description>This field specifies the protection context of the transfer that reads the register.</description>
3829              <bitRange>[7:4]</bitRange>
3830              <access>read-only</access>
3831            </field>
3832            <field>
3833              <name>MS</name>
3834              <description>This field specifies the bus master identifier of the transfer that reads the register.</description>
3835              <bitRange>[11:8]</bitRange>
3836              <access>read-only</access>
3837            </field>
3838          </fields>
3839        </register>
3840        <register>
3841          <name>CM4_STATUS</name>
3842          <description>CM4 status</description>
3843          <addressOffset>0x4</addressOffset>
3844          <size>32</size>
3845          <access>read-only</access>
3846          <resetValue>0x13</resetValue>
3847          <resetMask>0x13</resetMask>
3848          <fields>
3849            <field>
3850              <name>SLEEPING</name>
3851              <description>Specifies if the CPU is in Active, Sleep or DeepSleep power mode:
3852- Active power mode: SLEEPING is '0'.
3853- Sleep power mode: SLEEPING is '1' and SLEEPDEEP is '0'.
3854- DeepSleep power mode: SLEEPING is '1' and SLEEPDEEP is '1'.</description>
3855              <bitRange>[0:0]</bitRange>
3856              <access>read-only</access>
3857            </field>
3858            <field>
3859              <name>SLEEPDEEP</name>
3860              <description>Specifies if the CPU is in Sleep or DeepSleep power mode. See SLEEPING field.</description>
3861              <bitRange>[1:1]</bitRange>
3862              <access>read-only</access>
3863            </field>
3864            <field>
3865              <name>PWR_DONE</name>
3866              <description>After a PWR_MODE change this flag indicates if the new power mode has taken effect or not.
3867Note: this flag can also change as a result of  a change in debug power up req</description>
3868              <bitRange>[4:4]</bitRange>
3869              <access>read-only</access>
3870            </field>
3871          </fields>
3872        </register>
3873        <register>
3874          <name>CM4_CLOCK_CTL</name>
3875          <description>CM4 clock control</description>
3876          <addressOffset>0x8</addressOffset>
3877          <size>32</size>
3878          <access>read-write</access>
3879          <resetValue>0x0</resetValue>
3880          <resetMask>0xFF00</resetMask>
3881          <fields>
3882            <field>
3883              <name>FAST_INT_DIV</name>
3884              <description>Specifies the fast clock divider (from the high frequency clock 'clk_hf' to the peripheral clock 'clk_fast'). Integer division by (1+FAST_INT_DIV). Allows for integer divisions in the range [1, 256] (FAST_INT_DIV is in the range [0, 255]).
3885
3886Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.</description>
3887              <bitRange>[15:8]</bitRange>
3888              <access>read-write</access>
3889            </field>
3890          </fields>
3891        </register>
3892        <register>
3893          <name>CM4_CTL</name>
3894          <description>CM4 control</description>
3895          <addressOffset>0xC</addressOffset>
3896          <size>32</size>
3897          <access>read-write</access>
3898          <resetValue>0x0</resetValue>
3899          <resetMask>0x9F000000</resetMask>
3900          <fields>
3901            <field>
3902              <name>IOC_MASK</name>
3903              <description>CPU floating point unit (FPU) exception mask for the CPU's FPCSR.IOC 'invalid operation' exception condition:
3904'0': The CPU's exception condition does NOT activate the CPU's floating point interrupt.
3905'1': the CPU's exception condition activates the CPU's floating point interrupt.
3906
3907Note: the ARM architecture does NOT support FPU exceptions; i.e. there is no precise FPU exception handler. Instead, FPU conditions are captured in the CPU's FPCSR register and the conditions are provided as CPU interface signals. The interface signals are 'masked' with the fields a provide by this register (CM7_0_CTL). The 'masked' signals are reduced/OR-ed into a single CPU floating point interrupt signal. The associated CPU interrupt handler allows for imprecise handling of FPU exception conditions.
3908
3909Note: the CPU's FPCSR exception conditions are 'sticky'. Typically, the CPU FPU interrupt handler will clear the exception condition(s) to '0'.
3910
3911Note: by default, the FPU exception masks are '0'. Therefore, FPU exception conditions will NOT activate the CPU's floating point interrupt.</description>
3912              <bitRange>[24:24]</bitRange>
3913              <access>read-write</access>
3914            </field>
3915            <field>
3916              <name>DZC_MASK</name>
3917              <description>CPU FPU exception mask for the CPU's FPCSR.DZC 'divide by zero' exception condition:
3918'0': The CPU's exception condition does NOT activate the CPU's floating point interrupt.
3919'1': the CPU's exception condition activates the CPU's floating point interrupt.</description>
3920              <bitRange>[25:25]</bitRange>
3921              <access>read-write</access>
3922            </field>
3923            <field>
3924              <name>OFC_MASK</name>
3925              <description>CPU FPU exception mask for the CPU's FPCSR.OFC 'overflow' exception condition:
3926'0': The CPU's exception condition does NOT activate the CPU's floating point interrupt.
3927'1': the CPU's exception condition activates the CPU's floating point interrupt.</description>
3928              <bitRange>[26:26]</bitRange>
3929              <access>read-write</access>
3930            </field>
3931            <field>
3932              <name>UFC_MASK</name>
3933              <description>CPU FPU exception mask for the CPU's FPCSR.UFC 'underflow' exception condition:
3934'0': The CPU's exception condition does NOT activate the CPU's floating point interrupt.
3935'1': the CPU's exception condition activates the CPU's floating point interrupt.</description>
3936              <bitRange>[27:27]</bitRange>
3937              <access>read-write</access>
3938            </field>
3939            <field>
3940              <name>IXC_MASK</name>
3941              <description>CPU FPU exception mask for the CPU's FPCSR.IXC 'inexact' exception condition:
3942'0': The CPU's exception condition does NOT activate the CPU's floating point interrupt.
3943'1': the CPU's exception condition activates the CPU's floating point interrupt.
3944
3945Note: the 'inexact' condition is set as a result of rounding. Rounding may occur frequently and is typically not an error condition. To prevent frequent CPU FPU interrupts as a result of rounding, this field is typically set to '0'.</description>
3946              <bitRange>[28:28]</bitRange>
3947              <access>read-write</access>
3948            </field>
3949            <field>
3950              <name>IDC_MASK</name>
3951              <description>CPU FPU exception mask for the CPU's FPCSR.IDC 'input denormalized' exception condition:
3952'0': The CPU's exception condition does NOT activate the CPU's floating point interrupt.
3953'1': the CPU's exception condition activates the CPU's floating point interrupt.
3954
3955Note: if the CPU FPCSR.FZ field is set to '1', denormalized inputs are 'flushed to zero'. Dependent on the FPU algorithm, this may or may not occur frequently. To prevent frequent CPU FPU interrupts as a result of denormalized inputs, this field may be set to '0'.</description>
3956              <bitRange>[31:31]</bitRange>
3957              <access>read-write</access>
3958            </field>
3959          </fields>
3960        </register>
3961        <register>
3962          <name>CM4_INT0_STATUS</name>
3963          <description>CM4 interrupt 0 status</description>
3964          <addressOffset>0x100</addressOffset>
3965          <size>32</size>
3966          <access>read-only</access>
3967          <resetValue>0x0</resetValue>
3968          <resetMask>0x80000000</resetMask>
3969          <fields>
3970            <field>
3971              <name>SYSTEM_INT_IDX</name>
3972              <description>Lowest CM4 activated system interrupt index for CPU interrupt 0.
3973
3974See description of CM0_INT0_STATUS.</description>
3975              <bitRange>[9:0]</bitRange>
3976              <access>read-only</access>
3977            </field>
3978            <field>
3979              <name>SYSTEM_INT_VALID</name>
3980              <description>See description of CM0_INT0_STATUS.</description>
3981              <bitRange>[31:31]</bitRange>
3982              <access>read-only</access>
3983            </field>
3984          </fields>
3985        </register>
3986        <register>
3987          <name>CM4_INT1_STATUS</name>
3988          <description>CM4 interrupt 1 status</description>
3989          <addressOffset>0x104</addressOffset>
3990          <size>32</size>
3991          <access>read-only</access>
3992          <resetValue>0x0</resetValue>
3993          <resetMask>0x80000000</resetMask>
3994          <fields>
3995            <field>
3996              <name>SYSTEM_INT_IDX</name>
3997              <description>Lowest CM4 activated system interrupt index for CPU interrupt 1.
3998
3999See description of CM0_INT0_STATUS.</description>
4000              <bitRange>[9:0]</bitRange>
4001              <access>read-only</access>
4002            </field>
4003            <field>
4004              <name>SYSTEM_INT_VALID</name>
4005              <description>See description of CM0_INT0_STATUS.</description>
4006              <bitRange>[31:31]</bitRange>
4007              <access>read-only</access>
4008            </field>
4009          </fields>
4010        </register>
4011        <register>
4012          <name>CM4_INT2_STATUS</name>
4013          <description>CM4 interrupt 2 status</description>
4014          <addressOffset>0x108</addressOffset>
4015          <size>32</size>
4016          <access>read-only</access>
4017          <resetValue>0x0</resetValue>
4018          <resetMask>0x80000000</resetMask>
4019          <fields>
4020            <field>
4021              <name>SYSTEM_INT_IDX</name>
4022              <description>Lowest CM4 activated system interrupt index for CPU interrupt 2.
4023
4024See description of CM0_INT0_STATUS.</description>
4025              <bitRange>[9:0]</bitRange>
4026              <access>read-only</access>
4027            </field>
4028            <field>
4029              <name>SYSTEM_INT_VALID</name>
4030              <description>See description of CM0_INT0_STATUS.</description>
4031              <bitRange>[31:31]</bitRange>
4032              <access>read-only</access>
4033            </field>
4034          </fields>
4035        </register>
4036        <register>
4037          <name>CM4_INT3_STATUS</name>
4038          <description>CM4 interrupt 3 status</description>
4039          <addressOffset>0x10C</addressOffset>
4040          <size>32</size>
4041          <access>read-only</access>
4042          <resetValue>0x0</resetValue>
4043          <resetMask>0x80000000</resetMask>
4044          <fields>
4045            <field>
4046              <name>SYSTEM_INT_IDX</name>
4047              <description>Lowest CM4 activated system interrupt index for CPU interrupt 3.
4048
4049See description of CM0_INT0_STATUS.</description>
4050              <bitRange>[9:0]</bitRange>
4051              <access>read-only</access>
4052            </field>
4053            <field>
4054              <name>SYSTEM_INT_VALID</name>
4055              <description>See description of CM0_INT0_STATUS.</description>
4056              <bitRange>[31:31]</bitRange>
4057              <access>read-only</access>
4058            </field>
4059          </fields>
4060        </register>
4061        <register>
4062          <name>CM4_INT4_STATUS</name>
4063          <description>CM4 interrupt 4 status</description>
4064          <addressOffset>0x110</addressOffset>
4065          <size>32</size>
4066          <access>read-only</access>
4067          <resetValue>0x0</resetValue>
4068          <resetMask>0x80000000</resetMask>
4069          <fields>
4070            <field>
4071              <name>SYSTEM_INT_IDX</name>
4072              <description>Lowest CM4 activated system interrupt index for CPU interrupt 4.
4073
4074See description of CM0_INT0_STATUS.</description>
4075              <bitRange>[9:0]</bitRange>
4076              <access>read-only</access>
4077            </field>
4078            <field>
4079              <name>SYSTEM_INT_VALID</name>
4080              <description>See description of CM0_INT0_STATUS.</description>
4081              <bitRange>[31:31]</bitRange>
4082              <access>read-only</access>
4083            </field>
4084          </fields>
4085        </register>
4086        <register>
4087          <name>CM4_INT5_STATUS</name>
4088          <description>CM4 interrupt 5 status</description>
4089          <addressOffset>0x114</addressOffset>
4090          <size>32</size>
4091          <access>read-only</access>
4092          <resetValue>0x0</resetValue>
4093          <resetMask>0x80000000</resetMask>
4094          <fields>
4095            <field>
4096              <name>SYSTEM_INT_IDX</name>
4097              <description>Lowest CM4 activated system interrupt index for CPU interrupt 5.
4098
4099See description of CM0_INT0_STATUS.</description>
4100              <bitRange>[9:0]</bitRange>
4101              <access>read-only</access>
4102            </field>
4103            <field>
4104              <name>SYSTEM_INT_VALID</name>
4105              <description>See description of CM0_INT0_STATUS.</description>
4106              <bitRange>[31:31]</bitRange>
4107              <access>read-only</access>
4108            </field>
4109          </fields>
4110        </register>
4111        <register>
4112          <name>CM4_INT6_STATUS</name>
4113          <description>CM4 interrupt 6 status</description>
4114          <addressOffset>0x118</addressOffset>
4115          <size>32</size>
4116          <access>read-only</access>
4117          <resetValue>0x0</resetValue>
4118          <resetMask>0x80000000</resetMask>
4119          <fields>
4120            <field>
4121              <name>SYSTEM_INT_IDX</name>
4122              <description>Lowest CM4 activated system interrupt index for CPU interrupt 6.
4123
4124See description of CM0_INT0_STATUS.</description>
4125              <bitRange>[9:0]</bitRange>
4126              <access>read-only</access>
4127            </field>
4128            <field>
4129              <name>SYSTEM_INT_VALID</name>
4130              <description>See description of CM0_INT0_STATUS.</description>
4131              <bitRange>[31:31]</bitRange>
4132              <access>read-only</access>
4133            </field>
4134          </fields>
4135        </register>
4136        <register>
4137          <name>CM4_INT7_STATUS</name>
4138          <description>CM4 interrupt 7 status</description>
4139          <addressOffset>0x11C</addressOffset>
4140          <size>32</size>
4141          <access>read-only</access>
4142          <resetValue>0x0</resetValue>
4143          <resetMask>0x80000000</resetMask>
4144          <fields>
4145            <field>
4146              <name>SYSTEM_INT_IDX</name>
4147              <description>Lowest CM4 activated system interrupt index for CPU interrupt 7.
4148
4149See description of CM0_INT0_STATUS.</description>
4150              <bitRange>[9:0]</bitRange>
4151              <access>read-only</access>
4152            </field>
4153            <field>
4154              <name>SYSTEM_INT_VALID</name>
4155              <description>See description of CM0_INT0_STATUS.</description>
4156              <bitRange>[31:31]</bitRange>
4157              <access>read-only</access>
4158            </field>
4159          </fields>
4160        </register>
4161        <register>
4162          <name>CM4_VECTOR_TABLE_BASE</name>
4163          <description>CM4 vector table base</description>
4164          <addressOffset>0x200</addressOffset>
4165          <size>32</size>
4166          <access>read-write</access>
4167          <resetValue>0x0</resetValue>
4168          <resetMask>0xFFFFFC00</resetMask>
4169          <fields>
4170            <field>
4171              <name>ADDR22</name>
4172              <description>Address of CM4 vector table. This register is used for CM4 warm and cold boot purposes: the CM0+ CPU initializes the CM4_VECTOR_TABLE_BASE register and the CM4 boot code uses the register to initialize the CM4 internal VTOR register.
4173
4174Note: the CM4 vector table is at an address that is a 1024 B multiple.</description>
4175              <bitRange>[31:10]</bitRange>
4176              <access>read-write</access>
4177            </field>
4178          </fields>
4179        </register>
4180        <register>
4181          <dim>4</dim>
4182          <dimIncrement>4</dimIncrement>
4183          <name>CM4_NMI_CTL[%s]</name>
4184          <description>CM4 NMI control</description>
4185          <addressOffset>0x240</addressOffset>
4186          <size>32</size>
4187          <access>read-write</access>
4188          <resetValue>0x3FF</resetValue>
4189          <resetMask>0x3FF</resetMask>
4190          <fields>
4191            <field>
4192              <name>SYSTEM_INT_IDX</name>
4193              <description>System interrupt select for CPU NMI. The reset value ('1023') ensures that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset.</description>
4194              <bitRange>[9:0]</bitRange>
4195              <access>read-write</access>
4196            </field>
4197          </fields>
4198        </register>
4199        <register>
4200          <name>UDB_PWR_CTL</name>
4201          <description>UDB power control</description>
4202          <addressOffset>0x300</addressOffset>
4203          <size>32</size>
4204          <access>read-write</access>
4205          <resetValue>0xFA050001</resetValue>
4206          <resetMask>0xFFFF0003</resetMask>
4207          <fields>
4208            <field>
4209              <name>PWR_MODE</name>
4210              <description>Set Power mode for UDBs</description>
4211              <bitRange>[1:0]</bitRange>
4212              <access>read-write</access>
4213              <enumeratedValues>
4214                <enumeratedValue>
4215                  <name>OFF</name>
4216                  <description>See CM4_PWR_CTL</description>
4217                  <value>0</value>
4218                </enumeratedValue>
4219                <enumeratedValue>
4220                  <name>RESET</name>
4221                  <description>See CM4_PWR_CTL</description>
4222                  <value>1</value>
4223                </enumeratedValue>
4224                <enumeratedValue>
4225                  <name>RETAINED</name>
4226                  <description>See CM4_PWR_CTL</description>
4227                  <value>2</value>
4228                </enumeratedValue>
4229                <enumeratedValue>
4230                  <name>ENABLED</name>
4231                  <description>See CM4_PWR_CTL</description>
4232                  <value>3</value>
4233                </enumeratedValue>
4234              </enumeratedValues>
4235            </field>
4236            <field>
4237              <name>VECTKEYSTAT</name>
4238              <description>Register key (to prevent accidental writes).
4239- Should be written with a 0x05fa key value for the write to take effect.
4240- Always reads as 0xfa05.</description>
4241              <bitRange>[31:16]</bitRange>
4242              <access>read-only</access>
4243            </field>
4244          </fields>
4245        </register>
4246        <register>
4247          <name>UDB_PWR_DELAY_CTL</name>
4248          <description>UDB power control</description>
4249          <addressOffset>0x304</addressOffset>
4250          <size>32</size>
4251          <access>read-write</access>
4252          <resetValue>0x12C</resetValue>
4253          <resetMask>0x3FF</resetMask>
4254          <fields>
4255            <field>
4256              <name>UP</name>
4257              <description>Number clock cycles delay needed after power domain power up</description>
4258              <bitRange>[9:0]</bitRange>
4259              <access>read-write</access>
4260            </field>
4261          </fields>
4262        </register>
4263        <register>
4264          <name>CM0_CTL</name>
4265          <description>CM0+ control</description>
4266          <addressOffset>0x1000</addressOffset>
4267          <size>32</size>
4268          <access>read-write</access>
4269          <resetValue>0xFA050002</resetValue>
4270          <resetMask>0xFFFF0003</resetMask>
4271          <fields>
4272            <field>
4273              <name>SLV_STALL</name>
4274              <description>Processor debug access control:
4275'0': Access.
4276'1': Stall access.
4277
4278This field is used to stall/delay debug accesses. This is useful to protect execution of code that needs to be protected from debug accesses.</description>
4279              <bitRange>[0:0]</bitRange>
4280              <access>read-write</access>
4281            </field>
4282            <field>
4283              <name>ENABLED</name>
4284              <description>Processor enable:
4285'0': Disabled. Processor clock is turned off and reset is activated. After SW clears this field to '0', HW automatically sets this field to '1'. This effectively results in a CM0+ reset, followed by a CM0+ warm boot.
4286'1': Enabled.
4287Note: The intent is that this bit is modified only through an external probe or by the CM4 while the CM0+ is in Sleep or DeepSleep power mode. If this field is cleared to '0' by the CM0+ itself, it should be done under controlled conditions (such that undesirable side effects can be prevented).
4288
4289Note: The CM0+ CPU has a AIRCR.SYSRESETREQ register field that allows the CM0+ to reset the complete device (ENABLED only disables/enables the CM0+), resulting in a warm boot. This CPU register field has similar 'built-in protection' as this CM0_CTL register to prevent accidental system writes (the upper 16-bits of the register need to be written with a 0x05fa key value; see CPU user manual for more details).</description>
4290              <bitRange>[1:1]</bitRange>
4291              <access>read-write</access>
4292            </field>
4293            <field>
4294              <name>VECTKEYSTAT</name>
4295              <description>Register key (to prevent accidental writes).
4296- Should be written with a 0x05fa key value for the write to take effect.
4297- Always reads as 0xfa05.</description>
4298              <bitRange>[31:16]</bitRange>
4299              <access>read-only</access>
4300            </field>
4301          </fields>
4302        </register>
4303        <register>
4304          <name>CM0_STATUS</name>
4305          <description>CM0+ status</description>
4306          <addressOffset>0x1004</addressOffset>
4307          <size>32</size>
4308          <access>read-only</access>
4309          <resetValue>0x0</resetValue>
4310          <resetMask>0x3</resetMask>
4311          <fields>
4312            <field>
4313              <name>SLEEPING</name>
4314              <description>Specifies if the CPU is in Active, Sleep or DeepSleep power mode:
4315- Active power mode: SLEEPING is '0'.
4316- Sleep power mode: SLEEPING is '1' and SLEEPDEEP is '0'.
4317- DeepSleep power mode: SLEEPING is '1' and SLEEPDEEP is '1'.</description>
4318              <bitRange>[0:0]</bitRange>
4319              <access>read-only</access>
4320            </field>
4321            <field>
4322              <name>SLEEPDEEP</name>
4323              <description>Specifies if the CPU is in Sleep or DeepSleep power mode. See SLEEPING field.</description>
4324              <bitRange>[1:1]</bitRange>
4325              <access>read-only</access>
4326            </field>
4327          </fields>
4328        </register>
4329        <register>
4330          <name>CM0_CLOCK_CTL</name>
4331          <description>CM0+ clock control</description>
4332          <addressOffset>0x1008</addressOffset>
4333          <size>32</size>
4334          <access>read-write</access>
4335          <resetValue>0x0</resetValue>
4336          <resetMask>0xFF00FF00</resetMask>
4337          <fields>
4338            <field>
4339              <name>SLOW_INT_DIV</name>
4340              <description>Specifies the slow clock divider (from the peripheral clock 'clk_peri' to the slow clock 'clk_slow'). Integer division by (1+SLOW_INT_DIV). Allows for integer divisions in the range [1, 256] (SLOW_INT_DIV is in the range [0, 255]).
4341
4342Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.</description>
4343              <bitRange>[15:8]</bitRange>
4344              <access>read-write</access>
4345            </field>
4346            <field>
4347              <name>PERI_INT_DIV</name>
4348              <description>Specifies the peripheral clock divider (from the high frequency clock 'clk_hf' to the peripheral clock 'clk_peri'). Integer division by (1+PERI_INT_DIV). Allows for integer divisions in the range [1, 256] (PERI_INT_DIV is in the range [0, 255]).
4349
4350Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
4351
4352Note that Fperi &lt;= Fperi_max. Fperi_max is likely to be smaller than Fhf_max. In other words, if Fhf = Fhf_max, PERI_INT_DIV should not be set to '0'.</description>
4353              <bitRange>[31:24]</bitRange>
4354              <access>read-write</access>
4355            </field>
4356          </fields>
4357        </register>
4358        <register>
4359          <name>CM0_INT0_STATUS</name>
4360          <description>CM0+ interrupt 0 status</description>
4361          <addressOffset>0x1100</addressOffset>
4362          <size>32</size>
4363          <access>read-only</access>
4364          <resetValue>0x0</resetValue>
4365          <resetMask>0x80000000</resetMask>
4366          <fields>
4367            <field>
4368              <name>SYSTEM_INT_IDX</name>
4369              <description>Lowest CM0+ activated system interrupt index for CPU interrupt 0.
4370
4371Multiple system interrupts can be mapped on the same CPU interrupt. The selected system interrupt is the system interrupt with the lowest system interrupt index that has an activated interrupt request at the time of the fetch (system_interrupts[SYSTEM_INT_IDX] is '1').
4372
4373The CPU interrupt handler SW can read SYSTEM_INT_IDX to determine the system interrupt that activated the handler.</description>
4374              <bitRange>[9:0]</bitRange>
4375              <access>read-only</access>
4376            </field>
4377            <field>
4378              <name>SYSTEM_INT_VALID</name>
4379              <description>Valid indication for SYSTEM_INT_IDX. When '0', no system interrupt for CPU interrupt 0 is valid/activated.</description>
4380              <bitRange>[31:31]</bitRange>
4381              <access>read-only</access>
4382            </field>
4383          </fields>
4384        </register>
4385        <register>
4386          <name>CM0_INT1_STATUS</name>
4387          <description>CM0+ interrupt 1 status</description>
4388          <addressOffset>0x1104</addressOffset>
4389          <size>32</size>
4390          <access>read-only</access>
4391          <resetValue>0x0</resetValue>
4392          <resetMask>0x80000000</resetMask>
4393          <fields>
4394            <field>
4395              <name>SYSTEM_INT_IDX</name>
4396              <description>Lowest CM0+ activated system interrupt index for CPU interrupt 1.
4397
4398See description of CM0_INT0_STATUS.</description>
4399              <bitRange>[9:0]</bitRange>
4400              <access>read-only</access>
4401            </field>
4402            <field>
4403              <name>SYSTEM_INT_VALID</name>
4404              <description>See description of CM0_INT0_STATUS.</description>
4405              <bitRange>[31:31]</bitRange>
4406              <access>read-only</access>
4407            </field>
4408          </fields>
4409        </register>
4410        <register>
4411          <name>CM0_INT2_STATUS</name>
4412          <description>CM0+ interrupt 2 status</description>
4413          <addressOffset>0x1108</addressOffset>
4414          <size>32</size>
4415          <access>read-only</access>
4416          <resetValue>0x0</resetValue>
4417          <resetMask>0x80000000</resetMask>
4418          <fields>
4419            <field>
4420              <name>SYSTEM_INT_IDX</name>
4421              <description>Lowest CM0+ activated system interrupt index for CPU interrupt 2.
4422
4423See description of CM0_INT0_STATUS.</description>
4424              <bitRange>[9:0]</bitRange>
4425              <access>read-only</access>
4426            </field>
4427            <field>
4428              <name>SYSTEM_INT_VALID</name>
4429              <description>See description of CM0_INT0_STATUS.</description>
4430              <bitRange>[31:31]</bitRange>
4431              <access>read-only</access>
4432            </field>
4433          </fields>
4434        </register>
4435        <register>
4436          <name>CM0_INT3_STATUS</name>
4437          <description>CM0+ interrupt 3 status</description>
4438          <addressOffset>0x110C</addressOffset>
4439          <size>32</size>
4440          <access>read-only</access>
4441          <resetValue>0x0</resetValue>
4442          <resetMask>0x80000000</resetMask>
4443          <fields>
4444            <field>
4445              <name>SYSTEM_INT_IDX</name>
4446              <description>Lowest CM0+ activated system interrupt index for CPU interrupt 3.
4447
4448See description of CM0_INT0_STATUS.</description>
4449              <bitRange>[9:0]</bitRange>
4450              <access>read-only</access>
4451            </field>
4452            <field>
4453              <name>SYSTEM_INT_VALID</name>
4454              <description>See description of CM0_INT0_STATUS.</description>
4455              <bitRange>[31:31]</bitRange>
4456              <access>read-only</access>
4457            </field>
4458          </fields>
4459        </register>
4460        <register>
4461          <name>CM0_INT4_STATUS</name>
4462          <description>CM0+ interrupt 4 status</description>
4463          <addressOffset>0x1110</addressOffset>
4464          <size>32</size>
4465          <access>read-only</access>
4466          <resetValue>0x0</resetValue>
4467          <resetMask>0x80000000</resetMask>
4468          <fields>
4469            <field>
4470              <name>SYSTEM_INT_IDX</name>
4471              <description>Lowest CM0+ activated system interrupt index for CPU interrupt 4.
4472
4473See description of CM0_INT0_STATUS.</description>
4474              <bitRange>[9:0]</bitRange>
4475              <access>read-only</access>
4476            </field>
4477            <field>
4478              <name>SYSTEM_INT_VALID</name>
4479              <description>See description of CM0_INT0_STATUS.</description>
4480              <bitRange>[31:31]</bitRange>
4481              <access>read-only</access>
4482            </field>
4483          </fields>
4484        </register>
4485        <register>
4486          <name>CM0_INT5_STATUS</name>
4487          <description>CM0+ interrupt 5 status</description>
4488          <addressOffset>0x1114</addressOffset>
4489          <size>32</size>
4490          <access>read-only</access>
4491          <resetValue>0x0</resetValue>
4492          <resetMask>0x80000000</resetMask>
4493          <fields>
4494            <field>
4495              <name>SYSTEM_INT_IDX</name>
4496              <description>Lowest CM0+ activated system interrupt index for CPU interrupt 5.
4497
4498See description of CM0_INT0_STATUS.</description>
4499              <bitRange>[9:0]</bitRange>
4500              <access>read-only</access>
4501            </field>
4502            <field>
4503              <name>SYSTEM_INT_VALID</name>
4504              <description>See description of CM0_INT0_STATUS.</description>
4505              <bitRange>[31:31]</bitRange>
4506              <access>read-only</access>
4507            </field>
4508          </fields>
4509        </register>
4510        <register>
4511          <name>CM0_INT6_STATUS</name>
4512          <description>CM0+ interrupt 6 status</description>
4513          <addressOffset>0x1118</addressOffset>
4514          <size>32</size>
4515          <access>read-only</access>
4516          <resetValue>0x0</resetValue>
4517          <resetMask>0x80000000</resetMask>
4518          <fields>
4519            <field>
4520              <name>SYSTEM_INT_IDX</name>
4521              <description>Lowest CM0+ activated system interrupt index for CPU interrupt 6.
4522
4523See description of CM0_INT0_STATUS.</description>
4524              <bitRange>[9:0]</bitRange>
4525              <access>read-only</access>
4526            </field>
4527            <field>
4528              <name>SYSTEM_INT_VALID</name>
4529              <description>See description of CM0_INT0_STATUS.</description>
4530              <bitRange>[31:31]</bitRange>
4531              <access>read-only</access>
4532            </field>
4533          </fields>
4534        </register>
4535        <register>
4536          <name>CM0_INT7_STATUS</name>
4537          <description>CM0+ interrupt 7 status</description>
4538          <addressOffset>0x111C</addressOffset>
4539          <size>32</size>
4540          <access>read-only</access>
4541          <resetValue>0x0</resetValue>
4542          <resetMask>0x80000000</resetMask>
4543          <fields>
4544            <field>
4545              <name>SYSTEM_INT_IDX</name>
4546              <description>Lowest CM0+ activated system interrupt index for CPU interrupt 7.
4547
4548See description of CM0_INT0_STATUS.</description>
4549              <bitRange>[9:0]</bitRange>
4550              <access>read-only</access>
4551            </field>
4552            <field>
4553              <name>SYSTEM_INT_VALID</name>
4554              <description>See description of CM0_INT0_STATUS.</description>
4555              <bitRange>[31:31]</bitRange>
4556              <access>read-only</access>
4557            </field>
4558          </fields>
4559        </register>
4560        <register>
4561          <name>CM0_VECTOR_TABLE_BASE</name>
4562          <description>CM0+ vector table base</description>
4563          <addressOffset>0x1120</addressOffset>
4564          <size>32</size>
4565          <access>read-write</access>
4566          <resetValue>0x0</resetValue>
4567          <resetMask>0xFFFFFF00</resetMask>
4568          <fields>
4569            <field>
4570              <name>ADDR24</name>
4571              <description>Address of CM0+ vector table. This register is used for CM0+ warm boot purposes: the CM0+ warm boot code uses the register to initialize the CM0+ internal VTOR register.
4572
4573Note: the CM0+ vector table is at an address that is a 256 B multiple.</description>
4574              <bitRange>[31:8]</bitRange>
4575              <access>read-write</access>
4576            </field>
4577          </fields>
4578        </register>
4579        <register>
4580          <dim>4</dim>
4581          <dimIncrement>4</dimIncrement>
4582          <name>CM0_NMI_CTL[%s]</name>
4583          <description>CM0+ NMI control</description>
4584          <addressOffset>0x1140</addressOffset>
4585          <size>32</size>
4586          <access>read-write</access>
4587          <resetValue>0x3FF</resetValue>
4588          <resetMask>0x3FF</resetMask>
4589          <fields>
4590            <field>
4591              <name>SYSTEM_INT_IDX</name>
4592              <description>System interrupt select for CPU NMI. The reset value ('1023') ensures that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset.</description>
4593              <bitRange>[9:0]</bitRange>
4594              <access>read-write</access>
4595            </field>
4596          </fields>
4597        </register>
4598        <register>
4599          <name>CM4_PWR_CTL</name>
4600          <description>CM4 power control</description>
4601          <addressOffset>0x1200</addressOffset>
4602          <size>32</size>
4603          <access>read-write</access>
4604          <resetValue>0xFA050001</resetValue>
4605          <resetMask>0xFFFF0003</resetMask>
4606          <fields>
4607            <field>
4608              <name>PWR_MODE</name>
4609              <description>Power mode.</description>
4610              <bitRange>[1:0]</bitRange>
4611              <access>read-write</access>
4612              <enumeratedValues>
4613                <enumeratedValue>
4614                  <name>OFF</name>
4615                  <description>Switch CM4 off
4616Power off, clock off, isolate, reset and no retain.</description>
4617                  <value>0</value>
4618                </enumeratedValue>
4619                <enumeratedValue>
4620                  <name>RESET</name>
4621                  <description>Reset CM4
4622Clock off, no isolated, no retain and reset.
4623
4624Note: The CM4 CPU has a AIRCR.SYSRESETREQ register field that allows the CM4 to reset the complete device (RESET only resets the CM4), resulting in a warm boot.</description>
4625                  <value>1</value>
4626                </enumeratedValue>
4627                <enumeratedValue>
4628                  <name>RETAINED</name>
4629                  <description>Put CM4 in Retained mode
4630This can only become effective if CM4 is in SleepDeep mode. Check PWR_DONE flag to see if CM4 RETAINED state has been reached.
4631Power off, clock off, isolate, no reset and retain.</description>
4632                  <value>2</value>
4633                </enumeratedValue>
4634                <enumeratedValue>
4635                  <name>ENABLED</name>
4636                  <description>Switch CM4 on.
4637Power on, clock on, no isolate, no reset and no retain.</description>
4638                  <value>3</value>
4639                </enumeratedValue>
4640              </enumeratedValues>
4641            </field>
4642            <field>
4643              <name>VECTKEYSTAT</name>
4644              <description>Register key (to prevent accidental writes).
4645- Should be written with a 0x05fa key value for the write to take effect.
4646- Always reads as 0xfa05.</description>
4647              <bitRange>[31:16]</bitRange>
4648              <access>read-only</access>
4649            </field>
4650          </fields>
4651        </register>
4652        <register>
4653          <name>CM4_PWR_DELAY_CTL</name>
4654          <description>CM4 power control</description>
4655          <addressOffset>0x1204</addressOffset>
4656          <size>32</size>
4657          <access>read-write</access>
4658          <resetValue>0x12C</resetValue>
4659          <resetMask>0x3FF</resetMask>
4660          <fields>
4661            <field>
4662              <name>UP</name>
4663              <description>Number clock cycles delay needed after power domain power up</description>
4664              <bitRange>[9:0]</bitRange>
4665              <access>read-write</access>
4666            </field>
4667          </fields>
4668        </register>
4669        <register>
4670          <name>RAM0_CTL0</name>
4671          <description>RAM 0 control</description>
4672          <addressOffset>0x1300</addressOffset>
4673          <size>32</size>
4674          <access>read-write</access>
4675          <resetValue>0x30001</resetValue>
4676          <resetMask>0x70303</resetMask>
4677          <fields>
4678            <field>
4679              <name>SLOW_WS</name>
4680              <description>Memory wait states for the slow clock domain ('clk_slow'). The number of wait states is expressed in 'clk_hf' clock domain cycles.</description>
4681              <bitRange>[1:0]</bitRange>
4682              <access>read-write</access>
4683            </field>
4684            <field>
4685              <name>FAST_WS</name>
4686              <description>Memory wait states for the fast clock domain ('clk_fast'). The number of wait states is expressed in 'clk_hf' clock domain cycles.</description>
4687              <bitRange>[9:8]</bitRange>
4688              <access>read-write</access>
4689            </field>
4690            <field>
4691              <name>ECC_EN</name>
4692              <description>Enable ECC checking:
4693'0': Disabled.
4694'1': Enabled.</description>
4695              <bitRange>[16:16]</bitRange>
4696              <access>read-write</access>
4697            </field>
4698            <field>
4699              <name>ECC_AUTO_CORRECT</name>
4700              <description>HW ECC autocorrect functionality:
4701'0': Disabled.
4702'1': Enabled. HW automatically writes back SRAM with corrected data when a recoverable ECC error is detected.</description>
4703              <bitRange>[17:17]</bitRange>
4704              <access>read-write</access>
4705            </field>
4706            <field>
4707              <name>ECC_INJ_EN</name>
4708              <description>Enable error injection for system SRAM 0.
4709When '1', the parity (ECC_CTL.PARITY) is used when a full 32-bit write is done to the ECC_CTL.WORD_ADDR word address of system SRAM 0.</description>
4710              <bitRange>[18:18]</bitRange>
4711              <access>read-write</access>
4712            </field>
4713          </fields>
4714        </register>
4715        <register>
4716          <name>RAM0_STATUS</name>
4717          <description>RAM 0 status</description>
4718          <addressOffset>0x1304</addressOffset>
4719          <size>32</size>
4720          <access>read-only</access>
4721          <resetValue>0x1</resetValue>
4722          <resetMask>0x1</resetMask>
4723          <fields>
4724            <field>
4725              <name>WB_EMPTY</name>
4726              <description>Write buffer empty. This information is used when entering DeepSleep power mode: WB_EMPTY must be '1' before a transition to system DeepSleep power mode.
4727'0': Write buffer NOT empty.
4728'1': Write buffer empty.
4729
4730Note: the SRAM controller write buffer is only used when ECC checking is enabled. (RAMi_CTL.ECC_EN is '1').</description>
4731              <bitRange>[0:0]</bitRange>
4732              <access>read-only</access>
4733            </field>
4734          </fields>
4735        </register>
4736        <register>
4737          <dim>16</dim>
4738          <dimIncrement>4</dimIncrement>
4739          <name>RAM0_PWR_MACRO_CTL[%s]</name>
4740          <description>RAM 0 power control</description>
4741          <addressOffset>0x1340</addressOffset>
4742          <size>32</size>
4743          <access>read-write</access>
4744          <resetValue>0xFA050003</resetValue>
4745          <resetMask>0xFFFF0003</resetMask>
4746          <fields>
4747            <field>
4748              <name>PWR_MODE</name>
4749              <description>SRAM Power mode.</description>
4750              <bitRange>[1:0]</bitRange>
4751              <access>read-write</access>
4752              <enumeratedValues>
4753                <enumeratedValue>
4754                  <name>OFF</name>
4755                  <description>Turn OFF the SRAM. This will trun OFF both array and periphery power of the SRAM and SRAM memory contents are lost.</description>
4756                  <value>0</value>
4757                </enumeratedValue>
4758                <enumeratedValue>
4759                  <name>RSVD</name>
4760                  <description>undefined</description>
4761                  <value>1</value>
4762                </enumeratedValue>
4763                <enumeratedValue>
4764                  <name>RETAINED</name>
4765                  <description>Keep SRAM in Retained mode. This will turn OFF the SRAM periphery power, but array power is ON to retain memory contents.
4766The SRAM contents will be retained in DeepSleep system power mode.</description>
4767                  <value>2</value>
4768                </enumeratedValue>
4769                <enumeratedValue>
4770                  <name>ENABLED</name>
4771                  <description>Enable SRAM for regular operation.
4772The SRAM contents will be retained in DeepSleep system power mode.</description>
4773                  <value>3</value>
4774                </enumeratedValue>
4775              </enumeratedValues>
4776            </field>
4777            <field>
4778              <name>VECTKEYSTAT</name>
4779              <description>Register key (to prevent accidental writes).
4780- Should be written with a 0x05fa key value for the write to take effect.
4781- Always reads as 0xfa05.</description>
4782              <bitRange>[31:16]</bitRange>
4783              <access>read-only</access>
4784            </field>
4785          </fields>
4786        </register>
4787        <register>
4788          <name>RAM1_CTL0</name>
4789          <description>RAM 1 control</description>
4790          <addressOffset>0x1380</addressOffset>
4791          <size>32</size>
4792          <access>read-write</access>
4793          <resetValue>0x30001</resetValue>
4794          <resetMask>0x70303</resetMask>
4795          <fields>
4796            <field>
4797              <name>SLOW_WS</name>
4798              <description>See RAM0_CTL.</description>
4799              <bitRange>[1:0]</bitRange>
4800              <access>read-write</access>
4801            </field>
4802            <field>
4803              <name>FAST_WS</name>
4804              <description>See RAM0_CTL.</description>
4805              <bitRange>[9:8]</bitRange>
4806              <access>read-write</access>
4807            </field>
4808            <field>
4809              <name>ECC_EN</name>
4810              <description>See RAM0_CTL.</description>
4811              <bitRange>[16:16]</bitRange>
4812              <access>read-write</access>
4813            </field>
4814            <field>
4815              <name>ECC_AUTO_CORRECT</name>
4816              <description>See RAM0_CTL.</description>
4817              <bitRange>[17:17]</bitRange>
4818              <access>read-write</access>
4819            </field>
4820            <field>
4821              <name>ECC_INJ_EN</name>
4822              <description>See RAM0_CTL.</description>
4823              <bitRange>[18:18]</bitRange>
4824              <access>read-write</access>
4825            </field>
4826          </fields>
4827        </register>
4828        <register>
4829          <name>RAM1_STATUS</name>
4830          <description>RAM 1 status</description>
4831          <addressOffset>0x1384</addressOffset>
4832          <size>32</size>
4833          <access>read-only</access>
4834          <resetValue>0x1</resetValue>
4835          <resetMask>0x1</resetMask>
4836          <fields>
4837            <field>
4838              <name>WB_EMPTY</name>
4839              <description>See RAM0_STATUS.</description>
4840              <bitRange>[0:0]</bitRange>
4841              <access>read-only</access>
4842            </field>
4843          </fields>
4844        </register>
4845        <register>
4846          <name>RAM1_PWR_CTL</name>
4847          <description>RAM 1 power control</description>
4848          <addressOffset>0x1388</addressOffset>
4849          <size>32</size>
4850          <access>read-write</access>
4851          <resetValue>0xFA050003</resetValue>
4852          <resetMask>0xFFFF0003</resetMask>
4853          <fields>
4854            <field>
4855              <name>PWR_MODE</name>
4856              <description>Power mode.</description>
4857              <bitRange>[1:0]</bitRange>
4858              <access>read-write</access>
4859              <enumeratedValues>
4860                <enumeratedValue>
4861                  <name>OFF</name>
4862                  <description>See RAM0_PWR_MACRO_CTL.</description>
4863                  <value>0</value>
4864                </enumeratedValue>
4865                <enumeratedValue>
4866                  <name>RSVD</name>
4867                  <description>undefined</description>
4868                  <value>1</value>
4869                </enumeratedValue>
4870                <enumeratedValue>
4871                  <name>RETAINED</name>
4872                  <description>See RAM0_PWR_MACRO_CTL.</description>
4873                  <value>2</value>
4874                </enumeratedValue>
4875                <enumeratedValue>
4876                  <name>ENABLED</name>
4877                  <description>See RAM0_PWR_MACRO_CTL.</description>
4878                  <value>3</value>
4879                </enumeratedValue>
4880              </enumeratedValues>
4881            </field>
4882            <field>
4883              <name>VECTKEYSTAT</name>
4884              <description>See RAM0_PWR_MACRO_CTL.</description>
4885              <bitRange>[31:16]</bitRange>
4886              <access>read-only</access>
4887            </field>
4888          </fields>
4889        </register>
4890        <register>
4891          <name>RAM2_CTL0</name>
4892          <description>RAM 2 control</description>
4893          <addressOffset>0x13A0</addressOffset>
4894          <size>32</size>
4895          <access>read-write</access>
4896          <resetValue>0x30001</resetValue>
4897          <resetMask>0x70303</resetMask>
4898          <fields>
4899            <field>
4900              <name>SLOW_WS</name>
4901              <description>See RAM0_CTL.</description>
4902              <bitRange>[1:0]</bitRange>
4903              <access>read-write</access>
4904            </field>
4905            <field>
4906              <name>FAST_WS</name>
4907              <description>See RAM0_CTL.</description>
4908              <bitRange>[9:8]</bitRange>
4909              <access>read-write</access>
4910            </field>
4911            <field>
4912              <name>ECC_EN</name>
4913              <description>See RAM0_CTL.</description>
4914              <bitRange>[16:16]</bitRange>
4915              <access>read-write</access>
4916            </field>
4917            <field>
4918              <name>ECC_AUTO_CORRECT</name>
4919              <description>See RAM0_CTL.</description>
4920              <bitRange>[17:17]</bitRange>
4921              <access>read-write</access>
4922            </field>
4923            <field>
4924              <name>ECC_INJ_EN</name>
4925              <description>See RAM0_CTL.</description>
4926              <bitRange>[18:18]</bitRange>
4927              <access>read-write</access>
4928            </field>
4929          </fields>
4930        </register>
4931        <register>
4932          <name>RAM2_STATUS</name>
4933          <description>RAM 2 status</description>
4934          <addressOffset>0x13A4</addressOffset>
4935          <size>32</size>
4936          <access>read-only</access>
4937          <resetValue>0x1</resetValue>
4938          <resetMask>0x1</resetMask>
4939          <fields>
4940            <field>
4941              <name>WB_EMPTY</name>
4942              <description>See RAM0_STATUS.</description>
4943              <bitRange>[0:0]</bitRange>
4944              <access>read-only</access>
4945            </field>
4946          </fields>
4947        </register>
4948        <register>
4949          <name>RAM2_PWR_CTL</name>
4950          <description>RAM 2 power control</description>
4951          <addressOffset>0x13A8</addressOffset>
4952          <size>32</size>
4953          <access>read-write</access>
4954          <resetValue>0xFA050003</resetValue>
4955          <resetMask>0xFFFF0003</resetMask>
4956          <fields>
4957            <field>
4958              <name>PWR_MODE</name>
4959              <description>Power mode.</description>
4960              <bitRange>[1:0]</bitRange>
4961              <access>read-write</access>
4962              <enumeratedValues>
4963                <enumeratedValue>
4964                  <name>OFF</name>
4965                  <description>See RAM0_PWR_MACRO_CTL.</description>
4966                  <value>0</value>
4967                </enumeratedValue>
4968                <enumeratedValue>
4969                  <name>RSVD</name>
4970                  <description>undefined</description>
4971                  <value>1</value>
4972                </enumeratedValue>
4973                <enumeratedValue>
4974                  <name>RETAINED</name>
4975                  <description>See RAM0_PWR_MACRO_CTL.</description>
4976                  <value>2</value>
4977                </enumeratedValue>
4978                <enumeratedValue>
4979                  <name>ENABLED</name>
4980                  <description>See RAM0_PWR_MACRO_CTL.</description>
4981                  <value>3</value>
4982                </enumeratedValue>
4983              </enumeratedValues>
4984            </field>
4985            <field>
4986              <name>VECTKEYSTAT</name>
4987              <description>See RAM0_PWR_MACRO_CTL.</description>
4988              <bitRange>[31:16]</bitRange>
4989              <access>read-only</access>
4990            </field>
4991          </fields>
4992        </register>
4993        <register>
4994          <name>RAM_PWR_DELAY_CTL</name>
4995          <description>Power up delay used for all SRAM power domains</description>
4996          <addressOffset>0x13C0</addressOffset>
4997          <size>32</size>
4998          <access>read-write</access>
4999          <resetValue>0x96</resetValue>
5000          <resetMask>0x3FF</resetMask>
5001          <fields>
5002            <field>
5003              <name>UP</name>
5004              <description>Number clock cycles delay needed after power domain power up</description>
5005              <bitRange>[9:0]</bitRange>
5006              <access>read-write</access>
5007            </field>
5008          </fields>
5009        </register>
5010        <register>
5011          <name>ROM_CTL</name>
5012          <description>ROM control</description>
5013          <addressOffset>0x13C4</addressOffset>
5014          <size>32</size>
5015          <access>read-write</access>
5016          <resetValue>0x1</resetValue>
5017          <resetMask>0x303</resetMask>
5018          <fields>
5019            <field>
5020              <name>SLOW_WS</name>
5021              <description>Memory wait states for the slow clock domain ('clk_slow'). The number of wait states is expressed in 'clk_hf' clock domain cycles.
5022
5023Timing paths to and from the memory have a (fixed) minimum duration  that always needs to be considered/met. The 'clk_hf' clock domain frequency determines this field's value such that the timing paths minimum duration is met. A table/formula will be provided for this field's values for different 'clk_hf' frequencies.</description>
5024              <bitRange>[1:0]</bitRange>
5025              <access>read-write</access>
5026            </field>
5027            <field>
5028              <name>FAST_WS</name>
5029              <description>Memory wait states for the fast clock domain ('clk_fast'). The number of wait states is expressed in 'clk_hf' clock domain cycles.</description>
5030              <bitRange>[9:8]</bitRange>
5031              <access>read-write</access>
5032            </field>
5033          </fields>
5034        </register>
5035        <register>
5036          <name>ECC_CTL</name>
5037          <description>ECC control</description>
5038          <addressOffset>0x13C8</addressOffset>
5039          <size>32</size>
5040          <access>read-write</access>
5041          <resetValue>0x0</resetValue>
5042          <resetMask>0xFFFFFFFF</resetMask>
5043          <fields>
5044            <field>
5045              <name>WORD_ADDR</name>
5046              <description>Specifies the word address where an error will be injected.
5047- On a write transfer to this SRAM address and when the corresponding RAM0/RAM1/RAM2_CTL0.ECC_INJ_EN bit is '1', the parity (PARITY) is injected.
5048This field needs to be written with the offset address within the memory, divided by 4.
5049For example, if the RAM1 start address is 0x08010000, and an error is to be injected to address 0x08010040, then this field needs to configured to 0x000010.</description>
5050              <bitRange>[24:0]</bitRange>
5051              <access>read-write</access>
5052            </field>
5053            <field>
5054              <name>PARITY</name>
5055              <description>ECC parity to use for ECC error injection at address WORD_ADDR.</description>
5056              <bitRange>[31:25]</bitRange>
5057              <access>read-write</access>
5058            </field>
5059          </fields>
5060        </register>
5061        <register>
5062          <name>PRODUCT_ID</name>
5063          <description>Product identifier and version (same as CoreSight RomTables)</description>
5064          <addressOffset>0x1400</addressOffset>
5065          <size>32</size>
5066          <access>read-only</access>
5067          <resetValue>0x0</resetValue>
5068          <resetMask>0xFFF</resetMask>
5069          <fields>
5070            <field>
5071              <name>FAMILY_ID</name>
5072              <description>Family ID a.k.a. Partnumber a.k.a. Silicon ID</description>
5073              <bitRange>[11:0]</bitRange>
5074              <access>read-only</access>
5075            </field>
5076            <field>
5077              <name>MAJOR_REV</name>
5078              <description>Major Revision, starts with 1, increments with all layer tape-out (implemented with metal ECO-able  tie-off)</description>
5079              <bitRange>[19:16]</bitRange>
5080              <access>read-only</access>
5081            </field>
5082            <field>
5083              <name>MINOR_REV</name>
5084              <description>Minor Revision, starts with 1, increments with metal layer only tape-out (implemented with metal ECO-able  tie-off)</description>
5085              <bitRange>[23:20]</bitRange>
5086              <access>read-only</access>
5087            </field>
5088          </fields>
5089        </register>
5090        <register>
5091          <name>DP_STATUS</name>
5092          <description>Debug port status</description>
5093          <addressOffset>0x1410</addressOffset>
5094          <size>32</size>
5095          <access>read-only</access>
5096          <resetValue>0x4</resetValue>
5097          <resetMask>0x7</resetMask>
5098          <fields>
5099            <field>
5100              <name>SWJ_CONNECTED</name>
5101              <description>Specifies if the SWJ debug port is connected; i.e. debug host interface is active:
5102'0': Not connected/not active.
5103'1': Connected/active.</description>
5104              <bitRange>[0:0]</bitRange>
5105              <access>read-only</access>
5106            </field>
5107            <field>
5108              <name>SWJ_DEBUG_EN</name>
5109              <description>Specifies if SWJ debug is enabled, i.e. CDBGPWRUPACK is '1' and thus debug clocks are on:
5110'0': Disabled.
5111'1': Enabled.</description>
5112              <bitRange>[1:1]</bitRange>
5113              <access>read-only</access>
5114            </field>
5115            <field>
5116              <name>SWJ_JTAG_SEL</name>
5117              <description>Specifies if the JTAG or SWD interface is selected. This signal is valid when DP_CTL.PTM_SEL is '0' (SWJ mode selected) and SWJ_CONNECTED is '1' (SWJ is connected).
5118'0': SWD selected.
5119'1': JTAG selected.</description>
5120              <bitRange>[2:2]</bitRange>
5121              <access>read-only</access>
5122            </field>
5123          </fields>
5124        </register>
5125        <register>
5126          <name>AP_CTL</name>
5127          <description>Access port control</description>
5128          <addressOffset>0x1414</addressOffset>
5129          <size>32</size>
5130          <access>read-write</access>
5131          <resetValue>0x0</resetValue>
5132          <resetMask>0x70007</resetMask>
5133          <fields>
5134            <field>
5135              <name>CM0_ENABLE</name>
5136              <description>Enables the CM0 AP interface:
5137'0': Disabled.
5138'1': Enabled.</description>
5139              <bitRange>[0:0]</bitRange>
5140              <access>read-write</access>
5141            </field>
5142            <field>
5143              <name>CM4_ENABLE</name>
5144              <description>Enables the CM4 AP interface:
5145'0': Disabled.
5146'1': Enabled.</description>
5147              <bitRange>[1:1]</bitRange>
5148              <access>read-write</access>
5149            </field>
5150            <field>
5151              <name>SYS_ENABLE</name>
5152              <description>Enables the system AP interface:
5153'0': Disabled.
5154'1': Enabled.</description>
5155              <bitRange>[2:2]</bitRange>
5156              <access>read-write</access>
5157            </field>
5158            <field>
5159              <name>CM0_DISABLE</name>
5160              <description>Disables the CM0 AP interface:
5161'0': Enabled.
5162'1': Disabled.
5163
5164Typically, this field is set by the Cypress boot code with information from eFUSE. The access port is only enabled when CM0_DISABLE is '0' and CM0_ENABLE is '1'.</description>
5165              <bitRange>[16:16]</bitRange>
5166              <access>read-write</access>
5167            </field>
5168            <field>
5169              <name>CM4_DISABLE</name>
5170              <description>Disables the CM4 AP interface:
5171'0': Enabled.
5172'1': Disabled.
5173
5174Typically, this field is set by the Cypress boot code with information from eFUSE. The access port is only enabled when CM4_DISABLE is '0' and CM4_ENABLE is '1'.</description>
5175              <bitRange>[17:17]</bitRange>
5176              <access>read-write</access>
5177            </field>
5178            <field>
5179              <name>SYS_DISABLE</name>
5180              <description>Disables the system AP interface:
5181'0': Enabled.
5182'1': Disabled.
5183
5184Typically, this field is set by the Cypress boot code with information from eFUSE. The access port is only enabled when SYS_DISABLE is '0' and SYS_ENABLE is '1'.</description>
5185              <bitRange>[18:18]</bitRange>
5186              <access>read-write</access>
5187            </field>
5188          </fields>
5189        </register>
5190        <register>
5191          <name>BUFF_CTL</name>
5192          <description>Buffer control</description>
5193          <addressOffset>0x1500</addressOffset>
5194          <size>32</size>
5195          <access>read-write</access>
5196          <resetValue>0x1</resetValue>
5197          <resetMask>0x1</resetMask>
5198          <fields>
5199            <field>
5200              <name>WRITE_BUFF</name>
5201              <description>Specifies if write transfer can be buffered in the bus infrastructure bridges:
5202'0': Write transfers are not buffered, independent of the transfer's bufferable attribute.
5203'1': Write transfers can be buffered, if the transfer's bufferable attribute indicates that the transfer is a bufferable/posted write.</description>
5204              <bitRange>[0:0]</bitRange>
5205              <access>read-write</access>
5206            </field>
5207          </fields>
5208        </register>
5209        <register>
5210          <name>SYSTICK_CTL</name>
5211          <description>SysTick timer control</description>
5212          <addressOffset>0x1600</addressOffset>
5213          <size>32</size>
5214          <access>read-write</access>
5215          <resetValue>0x40000147</resetValue>
5216          <resetMask>0xC3FFFFFF</resetMask>
5217          <fields>
5218            <field>
5219              <name>TENMS</name>
5220              <description>Specifies the number of clock source cycles (minus 1) that make up 10 ms. E.g., for a 32,768 Hz reference clock, TENMS is 328 - 1 = 327.</description>
5221              <bitRange>[23:0]</bitRange>
5222              <access>read-write</access>
5223            </field>
5224            <field>
5225              <name>CLOCK_SOURCE</name>
5226              <description>Specifies an external clock source:
5227'0': The low frequency clock 'clk_lf' is selected. The precision of this clock depends on whether the low frequency clock source is a SRSS internal RC oscillator (imprecise) or a device external crystal oscillator (precise).
5228'1': The internal main oscillator (IMO) clock 'clk_imo' is selected. The MXS40 platform uses a fixed frequency IMO clock.
5229o '2': The external crystal oscillator (ECO) clock 'clk_eco' is selected.
5230'3': The SRSS 'clk_timer' is selected ('clk_timer' is a divided/gated version of 'clk_hf' or 'clk_imo').
5231
5232Note: If NOREF is '1', the CLOCK_SOURCE value is NOT used.
5233Note: It is SW's responsibility to provide the correct NOREF, SKEW and TENMS field values for the selected clock source.</description>
5234              <bitRange>[25:24]</bitRange>
5235              <access>read-write</access>
5236            </field>
5237            <field>
5238              <name>SKEW</name>
5239              <description>Specifies the precision of the clock source and if the TENMS field represents exactly 10 ms (clock source frequency is a multiple of 100 Hz). This affects the suitability of the SysTick timer as a SW real-time clock:
5240'0': Precise.
5241'1': Imprecise.</description>
5242              <bitRange>[30:30]</bitRange>
5243              <access>read-write</access>
5244            </field>
5245            <field>
5246              <name>NOREF</name>
5247              <description>Specifies if an external clock source is provided:
5248'0': An external clock source is provided.
5249'1': An external clock source is NOT provided and only the CPU internal clock can be used as SysTick timer clock source.</description>
5250              <bitRange>[31:31]</bitRange>
5251              <access>read-write</access>
5252            </field>
5253          </fields>
5254        </register>
5255        <register>
5256          <name>MBIST_STAT</name>
5257          <description>Memory BIST status</description>
5258          <addressOffset>0x1704</addressOffset>
5259          <size>32</size>
5260          <access>read-only</access>
5261          <resetValue>0x0</resetValue>
5262          <resetMask>0x3</resetMask>
5263          <fields>
5264            <field>
5265              <name>SFP_READY</name>
5266              <description>Flag indicating the BIST run is done. Note that after starting a BIST run this flag must be set before a new run can be started. For the first BIST run this will be 0.</description>
5267              <bitRange>[0:0]</bitRange>
5268              <access>read-only</access>
5269            </field>
5270            <field>
5271              <name>SFP_FAIL</name>
5272              <description>Report status of the BIST run, only valid if SFP_READY=1</description>
5273              <bitRange>[1:1]</bitRange>
5274              <access>read-only</access>
5275            </field>
5276          </fields>
5277        </register>
5278        <register>
5279          <name>CAL_SUP_SET</name>
5280          <description>Calibration support set and read</description>
5281          <addressOffset>0x1800</addressOffset>
5282          <size>32</size>
5283          <access>read-write</access>
5284          <resetValue>0x0</resetValue>
5285          <resetMask>0xFFFFFFFF</resetMask>
5286          <fields>
5287            <field>
5288              <name>DATA</name>
5289              <description>Read without side effect, write 1 to set</description>
5290              <bitRange>[31:0]</bitRange>
5291              <access>read-write</access>
5292            </field>
5293          </fields>
5294        </register>
5295        <register>
5296          <name>CAL_SUP_CLR</name>
5297          <description>Calibration support clear and reset</description>
5298          <addressOffset>0x1804</addressOffset>
5299          <size>32</size>
5300          <access>read-write</access>
5301          <resetValue>0x0</resetValue>
5302          <resetMask>0xFFFFFFFF</resetMask>
5303          <fields>
5304            <field>
5305              <name>DATA</name>
5306              <description>Read side effect: when read all bits are cleared, write 1 to clear a specific bit
5307Note: no exception for the debug host, it also causes the read side effect</description>
5308              <bitRange>[31:0]</bitRange>
5309              <access>read-write</access>
5310            </field>
5311          </fields>
5312        </register>
5313        <register>
5314          <name>CM0_PC_CTL</name>
5315          <description>CM0+ protection context control</description>
5316          <addressOffset>0x2000</addressOffset>
5317          <size>32</size>
5318          <access>read-write</access>
5319          <resetValue>0x0</resetValue>
5320          <resetMask>0xF</resetMask>
5321          <fields>
5322            <field>
5323              <name>VALID</name>
5324              <description>Valid fields for the protection context handler CM0_PCi_HANDLER registers:
5325Bit 0: Valid field for CM0_PC0_HANDLER.
5326Bit 1: Valid field for CM0_PC1_HANDLER.
5327Bit 2: Valid field for CM0_PC2_HANDLER.
5328Bit 3: Valid field for CM0_PC3_HANDLER.</description>
5329              <bitRange>[3:0]</bitRange>
5330              <access>read-write</access>
5331            </field>
5332          </fields>
5333        </register>
5334        <register>
5335          <name>CM0_PC0_HANDLER</name>
5336          <description>CM0+ protection context 0 handler</description>
5337          <addressOffset>0x2040</addressOffset>
5338          <size>32</size>
5339          <access>read-write</access>
5340          <resetValue>0x0</resetValue>
5341          <resetMask>0xFFFFFFFF</resetMask>
5342          <fields>
5343            <field>
5344              <name>ADDR</name>
5345              <description>Address of the protection context 0 handler. This field is used to detect entry to Cypress 'trusted' code through an exception/interrupt.</description>
5346              <bitRange>[31:0]</bitRange>
5347              <access>read-write</access>
5348            </field>
5349          </fields>
5350        </register>
5351        <register>
5352          <name>CM0_PC1_HANDLER</name>
5353          <description>CM0+ protection context 1 handler</description>
5354          <addressOffset>0x2044</addressOffset>
5355          <size>32</size>
5356          <access>read-write</access>
5357          <resetValue>0x0</resetValue>
5358          <resetMask>0xFFFFFFFF</resetMask>
5359          <fields>
5360            <field>
5361              <name>ADDR</name>
5362              <description>Address of the protection context 1 handler.</description>
5363              <bitRange>[31:0]</bitRange>
5364              <access>read-write</access>
5365            </field>
5366          </fields>
5367        </register>
5368        <register>
5369          <name>CM0_PC2_HANDLER</name>
5370          <description>CM0+ protection context 2 handler</description>
5371          <addressOffset>0x2048</addressOffset>
5372          <size>32</size>
5373          <access>read-write</access>
5374          <resetValue>0x0</resetValue>
5375          <resetMask>0xFFFFFFFF</resetMask>
5376          <fields>
5377            <field>
5378              <name>ADDR</name>
5379              <description>Address of the protection context 2 handler.</description>
5380              <bitRange>[31:0]</bitRange>
5381              <access>read-write</access>
5382            </field>
5383          </fields>
5384        </register>
5385        <register>
5386          <name>CM0_PC3_HANDLER</name>
5387          <description>CM0+ protection context 3 handler</description>
5388          <addressOffset>0x204C</addressOffset>
5389          <size>32</size>
5390          <access>read-write</access>
5391          <resetValue>0x0</resetValue>
5392          <resetMask>0xFFFFFFFF</resetMask>
5393          <fields>
5394            <field>
5395              <name>ADDR</name>
5396              <description>Address of the protection context 3 handler.</description>
5397              <bitRange>[31:0]</bitRange>
5398              <access>read-write</access>
5399            </field>
5400          </fields>
5401        </register>
5402        <register>
5403          <name>PROTECTION</name>
5404          <description>Protection status</description>
5405          <addressOffset>0x20C4</addressOffset>
5406          <size>32</size>
5407          <access>read-write</access>
5408          <resetValue>0x0</resetValue>
5409          <resetMask>0x7</resetMask>
5410          <fields>
5411            <field>
5412              <name>STATE</name>
5413              <description>Protection state:
5414'0': UNKNOWN.
5415'1': VIRGIN.
5416'2': NORMAL.
5417'3': SECURE.
5418'4': DEAD.
5419
5420The following state transitions are allowed (and enforced by HW):
5421- UNKNOWN =&gt; VIRGIN/NORMAL/SECURE/DEAD
5422- NORMAL =&gt; DEAD
5423- SECURE =&gt; DEAD
5424An attempt to make a NOT allowed state transition will NOT affect this register field.</description>
5425              <bitRange>[2:0]</bitRange>
5426              <access>read-write</access>
5427            </field>
5428          </fields>
5429        </register>
5430        <register>
5431          <name>TRIM_ROM_CTL</name>
5432          <description>ROM trim control</description>
5433          <addressOffset>0x2100</addressOffset>
5434          <size>32</size>
5435          <access>read-write</access>
5436          <resetValue>0x0</resetValue>
5437          <resetMask>0xFFFFFFFF</resetMask>
5438          <fields>
5439            <field>
5440              <name>TRIM</name>
5441              <description>N/A</description>
5442              <bitRange>[31:0]</bitRange>
5443              <access>read-write</access>
5444            </field>
5445          </fields>
5446        </register>
5447        <register>
5448          <name>TRIM_RAM_CTL</name>
5449          <description>RAM trim control</description>
5450          <addressOffset>0x2104</addressOffset>
5451          <size>32</size>
5452          <access>read-write</access>
5453          <resetValue>0x0</resetValue>
5454          <resetMask>0xFFFFFFFF</resetMask>
5455          <fields>
5456            <field>
5457              <name>TRIM</name>
5458              <description>N/A</description>
5459              <bitRange>[31:0]</bitRange>
5460              <access>read-write</access>
5461            </field>
5462          </fields>
5463        </register>
5464        <register>
5465          <dim>1023</dim>
5466          <dimIncrement>4</dimIncrement>
5467          <name>CM0_SYSTEM_INT_CTL[%s]</name>
5468          <description>CM0+ system interrupt control</description>
5469          <addressOffset>0x8000</addressOffset>
5470          <size>32</size>
5471          <access>read-write</access>
5472          <resetValue>0x0</resetValue>
5473          <resetMask>0x80000000</resetMask>
5474          <fields>
5475            <field>
5476              <name>CPU_INT_IDX</name>
5477              <description>CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'.
5478
5479Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.</description>
5480              <bitRange>[2:0]</bitRange>
5481              <access>read-write</access>
5482            </field>
5483            <field>
5484              <name>CPU_INT_VALID</name>
5485              <description>Interrupt enable:
5486'0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt.
5487'1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX.
5488
5489Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.</description>
5490              <bitRange>[31:31]</bitRange>
5491              <access>read-write</access>
5492            </field>
5493          </fields>
5494        </register>
5495        <register>
5496          <dim>1023</dim>
5497          <dimIncrement>4</dimIncrement>
5498          <name>CM4_SYSTEM_INT_CTL[%s]</name>
5499          <description>CM4 system interrupt control</description>
5500          <addressOffset>0xA000</addressOffset>
5501          <size>32</size>
5502          <access>read-write</access>
5503          <resetValue>0x0</resetValue>
5504          <resetMask>0x80000000</resetMask>
5505          <fields>
5506            <field>
5507              <name>CPU_INT_IDX</name>
5508              <description>N/A</description>
5509              <bitRange>[2:0]</bitRange>
5510              <access>read-write</access>
5511            </field>
5512            <field>
5513              <name>CPU_INT_VALID</name>
5514              <description>N/A</description>
5515              <bitRange>[31:31]</bitRange>
5516              <access>read-write</access>
5517            </field>
5518          </fields>
5519        </register>
5520      </registers>
5521    </peripheral>
5522    <peripheral>
5523      <name>FAULT</name>
5524      <description>Fault structures</description>
5525      <baseAddress>0x40210000</baseAddress>
5526      <addressBlock>
5527        <offset>0</offset>
5528        <size>65536</size>
5529        <usage>registers</usage>
5530      </addressBlock>
5531      <registers>
5532        <cluster>
5533          <dim>2</dim>
5534          <dimIncrement>256</dimIncrement>
5535          <name>STRUCT[%s]</name>
5536          <description>Fault structure</description>
5537          <addressOffset>0x00000000</addressOffset>
5538          <register>
5539            <name>CTL</name>
5540            <description>Fault control</description>
5541            <addressOffset>0x0</addressOffset>
5542            <size>32</size>
5543            <access>read-write</access>
5544            <resetValue>0x0</resetValue>
5545            <resetMask>0x7</resetMask>
5546            <fields>
5547              <field>
5548                <name>TR_EN</name>
5549                <description>Trigger output enable:
5550'0': Disabled. The trigger output 'tr_fault' is '0'.
5551'1': Enabled. The trigger output 'tr_fault' reflects STATUS.VALID. The trigger can be used to initiate a Datawire transfer of the FAULT data (FAULT_DATA0 through FAULT_DATA3).</description>
5552                <bitRange>[0:0]</bitRange>
5553                <access>read-write</access>
5554              </field>
5555              <field>
5556                <name>OUT_EN</name>
5557                <description>IO output signal enable:
5558'0': Disabled. The IO output signal 'fault_out' is '0'. The IO output enable signal 'fault_out_en' is '0'.
5559'1': Enabled. The IO output signal 'fault_out' reflects STATUS.VALID. The IO output enable signal 'fault_out_en' is '1'.</description>
5560                <bitRange>[1:1]</bitRange>
5561                <access>read-write</access>
5562              </field>
5563              <field>
5564                <name>RESET_REQ_EN</name>
5565                <description>Reset request enable:
5566'0': Disabled.
5567'1': Enabled. The output reset request signal 'fault_reset_req' reflects STATUS.VALID. This reset causes a warm/soft/core reset. This warm/soft/core reset does not affect the fault logic STATUS, DATA0, ..., DATA3 registers (allowing for post soft reset failure analysis).
5568
5569The 'fault_reset_req' signals of the individual fault report structures are combined (logically OR'd) into a single SRSS 'fault_reset_req' signal.</description>
5570                <bitRange>[2:2]</bitRange>
5571                <access>read-write</access>
5572              </field>
5573            </fields>
5574          </register>
5575          <register>
5576            <name>STATUS</name>
5577            <description>Fault status</description>
5578            <addressOffset>0xC</addressOffset>
5579            <size>32</size>
5580            <access>read-write</access>
5581            <resetValue>0x0</resetValue>
5582            <resetMask>0x80000000</resetMask>
5583            <fields>
5584              <field>
5585                <name>IDX</name>
5586                <description>The fault source index for which fault information is captured in DATA0 through DATA3. The fault information is fault source specific and described below.
5587
5588Note: this register field (and associated fault source data in DATA0 through DATA3) should only be considered valid, when VALID is '1'.</description>
5589                <bitRange>[6:0]</bitRange>
5590                <access>read-only</access>
5591              </field>
5592              <field>
5593                <name>VALID</name>
5594                <description>Valid indication:
5595'0': Invalid.
5596'1': Valid. HW sets this field to '1' when new fault source data is captured. New fault source data is ONLY captured when VALID is '0'. SW can clear this field to '0' when the fault is handled (by SW).</description>
5597                <bitRange>[31:31]</bitRange>
5598                <access>read-write</access>
5599              </field>
5600            </fields>
5601          </register>
5602          <register>
5603            <dim>4</dim>
5604            <dimIncrement>4</dimIncrement>
5605            <name>DATA[%s]</name>
5606            <description>Fault data</description>
5607            <addressOffset>0x10</addressOffset>
5608            <size>32</size>
5609            <access>read-only</access>
5610            <resetValue>0x0</resetValue>
5611            <resetMask>0x0</resetMask>
5612            <fields>
5613              <field>
5614                <name>DATA</name>
5615                <description>Captured fault source data.
5616
5617Note: the fault source index STATUS.IDX specifies the format of the DATA registers.</description>
5618                <bitRange>[31:0]</bitRange>
5619                <access>read-only</access>
5620              </field>
5621            </fields>
5622          </register>
5623          <register>
5624            <name>PENDING0</name>
5625            <description>Fault pending 0</description>
5626            <addressOffset>0x40</addressOffset>
5627            <size>32</size>
5628            <access>read-only</access>
5629            <resetValue>0x0</resetValue>
5630            <resetMask>0x0</resetMask>
5631            <fields>
5632              <field>
5633                <name>SOURCE</name>
5634                <description>This field specifies the following sources:
5635Bit 0: CM0 MPU.
5636Bit 1: CRYPTO MPU.
5637Bit 2: DW 0 MPU.
5638Bit 3: DW 1 MPU.
5639...
5640Bit 14: CM4 code bus MPU.
5641Bit 15: DAP MPU.
5642Bit 16: CM4 s+G92ystem bus MPU.
5643
5644
5645Bit 28: Peripheral master interface 0 PPU.
5646Bit 29: Peripheral master interface 1 PPU.
5647Bit 30: Peripheral master interface 2 PPU.
5648Bit 31: Peripheral master interface 3 PPU.</description>
5649                <bitRange>[31:0]</bitRange>
5650                <access>read-only</access>
5651              </field>
5652            </fields>
5653          </register>
5654          <register>
5655            <name>PENDING1</name>
5656            <description>Fault pending 1</description>
5657            <addressOffset>0x44</addressOffset>
5658            <size>32</size>
5659            <access>read-only</access>
5660            <resetValue>0x0</resetValue>
5661            <resetMask>0x0</resetMask>
5662            <fields>
5663              <field>
5664                <name>SOURCE</name>
5665                <description>This field specifies the following sources:
5666Bit 0: Peripheral group 0 PPU.
5667Bit 1: Peripheral group 1 PPU.
5668Bit 2: Peripheral group 2 PPU.
5669Bit 3: Peripheral group 3 PPU.
5670Bit 4: Peripheral group 4 PPU.
5671Bit 5: Peripheral group 5 PPU.
5672Bit 6: Peripheral group 6 PPU.
5673Bit 7: Peripheral group 7 PPU.
5674...
5675Bit 15: Peripheral group 15 PPU.
5676
5677Bit 18: Flash controller, main interface, bus error.</description>
5678                <bitRange>[31:0]</bitRange>
5679                <access>read-only</access>
5680              </field>
5681            </fields>
5682          </register>
5683          <register>
5684            <name>PENDING2</name>
5685            <description>Fault pending 2</description>
5686            <addressOffset>0x48</addressOffset>
5687            <size>32</size>
5688            <access>read-only</access>
5689            <resetValue>0x0</resetValue>
5690            <resetMask>0x0</resetMask>
5691            <fields>
5692              <field>
5693                <name>SOURCE</name>
5694                <description>This field specifies the following sources:
5695Bit 0 - 31: TBD.</description>
5696                <bitRange>[31:0]</bitRange>
5697                <access>read-only</access>
5698              </field>
5699            </fields>
5700          </register>
5701          <register>
5702            <name>MASK0</name>
5703            <description>Fault mask 0</description>
5704            <addressOffset>0x50</addressOffset>
5705            <size>32</size>
5706            <access>read-write</access>
5707            <resetValue>0x0</resetValue>
5708            <resetMask>0xFFFFFFFF</resetMask>
5709            <fields>
5710              <field>
5711                <name>SOURCE</name>
5712                <description>Fault source enables:
5713Bits 31-0: Fault sources 31 to 0.</description>
5714                <bitRange>[31:0]</bitRange>
5715                <access>read-write</access>
5716              </field>
5717            </fields>
5718          </register>
5719          <register>
5720            <name>MASK1</name>
5721            <description>Fault mask 1</description>
5722            <addressOffset>0x54</addressOffset>
5723            <size>32</size>
5724            <access>read-write</access>
5725            <resetValue>0x0</resetValue>
5726            <resetMask>0xFFFFFFFF</resetMask>
5727            <fields>
5728              <field>
5729                <name>SOURCE</name>
5730                <description>Fault source enables:
5731Bits 31-0: Fault sources 63 to 32.</description>
5732                <bitRange>[31:0]</bitRange>
5733                <access>read-write</access>
5734              </field>
5735            </fields>
5736          </register>
5737          <register>
5738            <name>MASK2</name>
5739            <description>Fault mask 2</description>
5740            <addressOffset>0x58</addressOffset>
5741            <size>32</size>
5742            <access>read-write</access>
5743            <resetValue>0x0</resetValue>
5744            <resetMask>0xFFFFFFFF</resetMask>
5745            <fields>
5746              <field>
5747                <name>SOURCE</name>
5748                <description>Fault source enables:
5749Bits 31-0: Fault sources 95 to 64.</description>
5750                <bitRange>[31:0]</bitRange>
5751                <access>read-write</access>
5752              </field>
5753            </fields>
5754          </register>
5755          <register>
5756            <name>INTR</name>
5757            <description>Interrupt</description>
5758            <addressOffset>0xC0</addressOffset>
5759            <size>32</size>
5760            <access>read-write</access>
5761            <resetValue>0x0</resetValue>
5762            <resetMask>0x1</resetMask>
5763            <fields>
5764              <field>
5765                <name>FAULT</name>
5766                <description>This interrupt cause field is activated (HW sets the field to '1') when an enabled (MASK0/MASK1/MASK2) pending fault source is captured:
5767- STATUS.VALID is set to '1'.
5768- STATUS.IDX specifies the fault source index.
5769- DATA0 through DATA3 captures the fault source data.
5770
5771SW writes a '1' to these field to clear the interrupt cause to '0'.</description>
5772                <bitRange>[0:0]</bitRange>
5773                <access>read-write</access>
5774              </field>
5775            </fields>
5776          </register>
5777          <register>
5778            <name>INTR_SET</name>
5779            <description>Interrupt set</description>
5780            <addressOffset>0xC4</addressOffset>
5781            <size>32</size>
5782            <access>read-write</access>
5783            <resetValue>0x0</resetValue>
5784            <resetMask>0x1</resetMask>
5785            <fields>
5786              <field>
5787                <name>FAULT</name>
5788                <description>SW writes a '1' to this field to set the corresponding field in the INTR register.</description>
5789                <bitRange>[0:0]</bitRange>
5790                <access>read-write</access>
5791              </field>
5792            </fields>
5793          </register>
5794          <register>
5795            <name>INTR_MASK</name>
5796            <description>Interrupt mask</description>
5797            <addressOffset>0xC8</addressOffset>
5798            <size>32</size>
5799            <access>read-write</access>
5800            <resetValue>0x0</resetValue>
5801            <resetMask>0x1</resetMask>
5802            <fields>
5803              <field>
5804                <name>FAULT</name>
5805                <description>Mask bit for corresponding field in the INTR register.</description>
5806                <bitRange>[0:0]</bitRange>
5807                <access>read-write</access>
5808              </field>
5809            </fields>
5810          </register>
5811          <register>
5812            <name>INTR_MASKED</name>
5813            <description>Interrupt masked</description>
5814            <addressOffset>0xCC</addressOffset>
5815            <size>32</size>
5816            <access>read-only</access>
5817            <resetValue>0x0</resetValue>
5818            <resetMask>0x1</resetMask>
5819            <fields>
5820              <field>
5821                <name>FAULT</name>
5822                <description>Logical and of corresponding INTR and INTR_MASK fields.</description>
5823                <bitRange>[0:0]</bitRange>
5824                <access>read-only</access>
5825              </field>
5826            </fields>
5827          </register>
5828        </cluster>
5829      </registers>
5830    </peripheral>
5831    <peripheral>
5832      <name>IPC</name>
5833      <description>IPC</description>
5834      <baseAddress>0x40220000</baseAddress>
5835      <addressBlock>
5836        <offset>0</offset>
5837        <size>65536</size>
5838        <usage>registers</usage>
5839      </addressBlock>
5840      <registers>
5841        <cluster>
5842          <dim>16</dim>
5843          <dimIncrement>32</dimIncrement>
5844          <name>STRUCT[%s]</name>
5845          <description>IPC structure</description>
5846          <addressOffset>0x00000000</addressOffset>
5847          <register>
5848            <name>ACQUIRE</name>
5849            <description>IPC acquire</description>
5850            <addressOffset>0x0</addressOffset>
5851            <size>32</size>
5852            <access>read-only</access>
5853            <resetValue>0x0</resetValue>
5854            <resetMask>0x80000000</resetMask>
5855            <fields>
5856              <field>
5857                <name>P</name>
5858                <description>User/privileged access control:
5859'0': user mode.
5860'1': privileged mode.
5861
5862This field is set with the user/privileged access control of the access that successfully acquired the lock.</description>
5863                <bitRange>[0:0]</bitRange>
5864                <access>read-only</access>
5865              </field>
5866              <field>
5867                <name>NS</name>
5868                <description>Secure/non-secure access control:
5869'0': secure.
5870'1': non-secure.
5871
5872This field is set with the secure/non-secure access control of the access that successfully acquired the lock.</description>
5873                <bitRange>[1:1]</bitRange>
5874                <access>read-only</access>
5875              </field>
5876              <field>
5877                <name>PC</name>
5878                <description>This field specifies the protection context that successfully acquired the lock.</description>
5879                <bitRange>[7:4]</bitRange>
5880                <access>read-only</access>
5881              </field>
5882              <field>
5883                <name>MS</name>
5884                <description>This field specifies the bus master identifier that successfully acquired the lock.</description>
5885                <bitRange>[11:8]</bitRange>
5886                <access>read-only</access>
5887              </field>
5888              <field>
5889                <name>SUCCESS</name>
5890                <description>Specifies if the lock is successfully acquired or not (reading the ACQUIRE register can have affect on SUCCESS and LOCK_STATUS.ACQUIRED):
5891'0': Not successfully acquired; i.e. the lock was already acquired by another read transaction and not released. The P, NS, PC and MS fields reflect the access attributes of the transaction that previously successfully acuired the lock; the fields are NOT affected by the current access.
5892'1': Successfully acquired. The P, NS, PC and MS fields reflect the access attributes of the current access.
5893
5894Note that this field is NOT SW writable. A lock is released by writing to the associated RELEASE register (irrespective of the write value).</description>
5895                <bitRange>[31:31]</bitRange>
5896                <access>read-only</access>
5897              </field>
5898            </fields>
5899          </register>
5900          <register>
5901            <name>RELEASE</name>
5902            <description>IPC release</description>
5903            <addressOffset>0x4</addressOffset>
5904            <size>32</size>
5905            <access>write-only</access>
5906            <resetValue>0x0</resetValue>
5907            <resetMask>0xFFFF</resetMask>
5908            <fields>
5909              <field>
5910                <name>INTR_RELEASE</name>
5911                <description>Writing this field releases a lock and allows for the generation of release events to the IPC interrupt structures, but only when the lock is acquired (LOCK_STATUS.ACQUIRED is '1'). The IPC release cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_RELEASE[] is set to '1'.
5912
5913SW writes a '1' to the bit fields to generate a release event. Due to the transient nature of this event, SW always reads a '0' from this field.</description>
5914                <bitRange>[15:0]</bitRange>
5915                <access>write-only</access>
5916              </field>
5917            </fields>
5918          </register>
5919          <register>
5920            <name>NOTIFY</name>
5921            <description>IPC notification</description>
5922            <addressOffset>0x8</addressOffset>
5923            <size>32</size>
5924            <access>write-only</access>
5925            <resetValue>0x0</resetValue>
5926            <resetMask>0xFFFF</resetMask>
5927            <fields>
5928              <field>
5929                <name>INTR_NOTIFY</name>
5930                <description>This field allows for the generation of notification events to the IPC interrupt structures. The IPC notification cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_NOTIFY[] is set to '1'.
5931
5932SW writes a '1' to the bit fields to generate a notify event. Due to the transient nature of this event, SW always reads a '0' from this field.</description>
5933                <bitRange>[15:0]</bitRange>
5934                <access>write-only</access>
5935              </field>
5936            </fields>
5937          </register>
5938          <register>
5939            <name>DATA0</name>
5940            <description>IPC data 0</description>
5941            <addressOffset>0xC</addressOffset>
5942            <size>32</size>
5943            <access>read-write</access>
5944            <resetValue>0x0</resetValue>
5945            <resetMask>0x0</resetMask>
5946            <fields>
5947              <field>
5948                <name>DATA</name>
5949                <description>This field holds a 32-bit data element that is associated with the IPC structure.</description>
5950                <bitRange>[31:0]</bitRange>
5951                <access>read-write</access>
5952              </field>
5953            </fields>
5954          </register>
5955          <register>
5956            <name>DATA1</name>
5957            <description>IPC data 1</description>
5958            <addressOffset>0x10</addressOffset>
5959            <size>32</size>
5960            <access>read-write</access>
5961            <resetValue>0x0</resetValue>
5962            <resetMask>0x0</resetMask>
5963            <fields>
5964              <field>
5965                <name>DATA</name>
5966                <description>This field holds a 32-bit data element that is associated with the IPC structure.</description>
5967                <bitRange>[31:0]</bitRange>
5968                <access>read-write</access>
5969              </field>
5970            </fields>
5971          </register>
5972          <register>
5973            <name>LOCK_STATUS</name>
5974            <description>IPC lock status</description>
5975            <addressOffset>0x1C</addressOffset>
5976            <size>32</size>
5977            <access>read-only</access>
5978            <resetValue>0x0</resetValue>
5979            <resetMask>0x80000000</resetMask>
5980            <fields>
5981              <field>
5982                <name>P</name>
5983                <description>This field specifies the user/privileged access control:
5984'0': user mode.
5985'1': privileged mode.</description>
5986                <bitRange>[0:0]</bitRange>
5987                <access>read-only</access>
5988              </field>
5989              <field>
5990                <name>NS</name>
5991                <description>This field specifies the secure/non-secure access control:
5992'0': secure.
5993'1': non-secure.</description>
5994                <bitRange>[1:1]</bitRange>
5995                <access>read-only</access>
5996              </field>
5997              <field>
5998                <name>PC</name>
5999                <description>This field specifies the protection context that successfully acquired the lock.</description>
6000                <bitRange>[7:4]</bitRange>
6001                <access>read-only</access>
6002              </field>
6003              <field>
6004                <name>MS</name>
6005                <description>This field specifies the bus master identifier that successfully acquired the lock.</description>
6006                <bitRange>[11:8]</bitRange>
6007                <access>read-only</access>
6008              </field>
6009              <field>
6010                <name>ACQUIRED</name>
6011                <description>Specifies if the lock is acquired. This field is set to '1', if a ACQUIRE read transfer successfully acquires the lock (the ACQUIRE read transfer returns ACQUIRE.SUCCESS as '1'). If zero, P, NS, PC, and MS are not valid.</description>
6012                <bitRange>[31:31]</bitRange>
6013                <access>read-only</access>
6014              </field>
6015            </fields>
6016          </register>
6017        </cluster>
6018        <cluster>
6019          <dim>16</dim>
6020          <dimIncrement>32</dimIncrement>
6021          <name>INTR_STRUCT[%s]</name>
6022          <description>IPC interrupt structure</description>
6023          <addressOffset>0x00001000</addressOffset>
6024          <register>
6025            <name>INTR</name>
6026            <description>Interrupt</description>
6027            <addressOffset>0x0</addressOffset>
6028            <size>32</size>
6029            <access>read-write</access>
6030            <resetValue>0x0</resetValue>
6031            <resetMask>0xFFFFFFFF</resetMask>
6032            <fields>
6033              <field>
6034                <name>RELEASE</name>
6035                <description>These interrupt cause fields are activated (HW sets the field to '1') when a IPC release event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause.</description>
6036                <bitRange>[15:0]</bitRange>
6037                <access>read-write</access>
6038              </field>
6039              <field>
6040                <name>NOTIFY</name>
6041                <description>These interrupt cause fields are activated (HW sets the field to '1') when a IPC notification event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause.</description>
6042                <bitRange>[31:16]</bitRange>
6043                <access>read-write</access>
6044              </field>
6045            </fields>
6046          </register>
6047          <register>
6048            <name>INTR_SET</name>
6049            <description>Interrupt set</description>
6050            <addressOffset>0x4</addressOffset>
6051            <size>32</size>
6052            <access>read-write</access>
6053            <resetValue>0x0</resetValue>
6054            <resetMask>0xFFFFFFFF</resetMask>
6055            <fields>
6056              <field>
6057                <name>RELEASE</name>
6058                <description>SW writes a '1' to this field to set the corresponding field in the INTR register.</description>
6059                <bitRange>[15:0]</bitRange>
6060                <access>read-write</access>
6061              </field>
6062              <field>
6063                <name>NOTIFY</name>
6064                <description>SW writes a '1' to this field to set the corresponding field in the INTR register.</description>
6065                <bitRange>[31:16]</bitRange>
6066                <access>read-write</access>
6067              </field>
6068            </fields>
6069          </register>
6070          <register>
6071            <name>INTR_MASK</name>
6072            <description>Interrupt mask</description>
6073            <addressOffset>0x8</addressOffset>
6074            <size>32</size>
6075            <access>read-write</access>
6076            <resetValue>0x0</resetValue>
6077            <resetMask>0xFFFFFFFF</resetMask>
6078            <fields>
6079              <field>
6080                <name>RELEASE</name>
6081                <description>Mask bit for corresponding field in the INTR register.</description>
6082                <bitRange>[15:0]</bitRange>
6083                <access>read-write</access>
6084              </field>
6085              <field>
6086                <name>NOTIFY</name>
6087                <description>Mask bit for corresponding field in the INTR register.</description>
6088                <bitRange>[31:16]</bitRange>
6089                <access>read-write</access>
6090              </field>
6091            </fields>
6092          </register>
6093          <register>
6094            <name>INTR_MASKED</name>
6095            <description>Interrupt masked</description>
6096            <addressOffset>0xC</addressOffset>
6097            <size>32</size>
6098            <access>read-only</access>
6099            <resetValue>0x0</resetValue>
6100            <resetMask>0xFFFFFFFF</resetMask>
6101            <fields>
6102              <field>
6103                <name>RELEASE</name>
6104                <description>Logical and of corresponding request and mask bits.</description>
6105                <bitRange>[15:0]</bitRange>
6106                <access>read-only</access>
6107              </field>
6108              <field>
6109                <name>NOTIFY</name>
6110                <description>Logical and of corresponding INTR and INTR_MASK fields.</description>
6111                <bitRange>[31:16]</bitRange>
6112                <access>read-only</access>
6113              </field>
6114            </fields>
6115          </register>
6116        </cluster>
6117      </registers>
6118    </peripheral>
6119    <peripheral>
6120      <name>PROT</name>
6121      <description>Protection</description>
6122      <baseAddress>0x40230000</baseAddress>
6123      <addressBlock>
6124        <offset>0</offset>
6125        <size>65536</size>
6126        <usage>registers</usage>
6127      </addressBlock>
6128      <registers>
6129        <cluster>
6130          <name>SMPU</name>
6131          <description>SMPU</description>
6132          <addressOffset>0x00000000</addressOffset>
6133          <register>
6134            <name>MS0_CTL</name>
6135            <description>Master 0 protection context control</description>
6136            <addressOffset>0x0</addressOffset>
6137            <size>32</size>
6138            <access>read-write</access>
6139            <resetValue>0x303</resetValue>
6140            <resetMask>0xFFFF0303</resetMask>
6141            <fields>
6142              <field>
6143                <name>P</name>
6144                <description>Privileged setting ('0': user mode; '1': privileged mode).
6145
6146Notes:
6147This field is ONLY used for masters that do NOT provide their own user/privileged access control attribute.
6148The default/reset field value provides privileged mode access capabilities.</description>
6149                <bitRange>[0:0]</bitRange>
6150                <access>read-write</access>
6151              </field>
6152              <field>
6153                <name>NS</name>
6154                <description>Security setting ('0': secure mode; '1': non-secure mode).
6155
6156Notes:
6157This field is ONLY used for masters that do NOT provide their own secure/non-secure access control attribute.
6158Note that the default/reset field value provides non-secure mode access capabilities to all masters.</description>
6159                <bitRange>[1:1]</bitRange>
6160                <access>read-write</access>
6161              </field>
6162              <field>
6163                <name>PRIO</name>
6164                <description>Device wide bus arbitration priority setting ('0': highest priority, '3': lowest priority).
6165
6166Notes:
6167The AHB-Lite interconnect performs arbitration on the individual  beats/transfers of a burst (this optimizes latency over locality/bandwidth).
6168The AXI-Lite interconnects performs a single arbitration for the complete burst (this optimizes locality/bandwidth over latency).
6169Masters with the same priority setting form a 'priority group'. Within a 'priority group', round robin arbitration is performed.</description>
6170                <bitRange>[9:8]</bitRange>
6171                <access>read-write</access>
6172              </field>
6173              <field>
6174                <name>PC_MASK_0</name>
6175                <description>Protection context mask for protection context '0'. This field is a constant '0':
6176- PC_MASK_0 is '0': MPU MS_CTL.PC[3:0] can NOT be set to '0' and PC[3:0] is not changed. If the protection context of the write transfer is '0', protection is not applied and PC[3:0] can be changed.</description>
6177                <bitRange>[16:16]</bitRange>
6178                <access>read-only</access>
6179              </field>
6180              <field>
6181                <name>PC_MASK_15_TO_1</name>
6182                <description>Protection context mask for protection contexts '15' down to '1'. Bit PC_MASK_15_TO_1[i] indicates if the MPU MS_CTL.PC[3:0] protection context field can be set to the value 'i+1':
6183- PC_MASK_15_TO_1[i] is '0': MPU MS_CTL.PC[3:0] can NOT be set to 'i+1'; and PC[3:0] is not changed. If the protection context of the write transfer is '0', protection is not applied and PC[3:0] can be changed.
6184- PC_MASK_15_TO_1[i] is '1': MPU MS_CTL.PC[3:0] can be set to 'i+1'.
6185
6186Note: When CPUSS_CM0_PC_CTL.VALID[i] is '1' (the associated protection context handler is valid), write transfers to PC_MASK_15_TO_1[i-1] always write '0', regardless of data written. This ensures that when valid protection context handlers are used to enter protection contexts 1, 2 or 3 through (HW modifies MPU MS_CTL.PC[3:0] on entry of the handler), it is NOT possible for SW to enter those protection contexts (SW modifies MPU MS_CTL.PC[3:0]).</description>
6187                <bitRange>[31:17]</bitRange>
6188                <access>read-write</access>
6189              </field>
6190            </fields>
6191          </register>
6192          <register>
6193            <name>MS1_CTL</name>
6194            <description>Master 1 protection context control</description>
6195            <addressOffset>0x4</addressOffset>
6196            <size>32</size>
6197            <access>read-write</access>
6198            <resetValue>0x303</resetValue>
6199            <resetMask>0xFFFF0303</resetMask>
6200            <fields>
6201              <field>
6202                <name>P</name>
6203                <description>See MS0_CTL.P.</description>
6204                <bitRange>[0:0]</bitRange>
6205                <access>read-write</access>
6206              </field>
6207              <field>
6208                <name>NS</name>
6209                <description>See MS0_CTL.NS.</description>
6210                <bitRange>[1:1]</bitRange>
6211                <access>read-write</access>
6212              </field>
6213              <field>
6214                <name>PRIO</name>
6215                <description>See MS0_CTL.PRIO</description>
6216                <bitRange>[9:8]</bitRange>
6217                <access>read-write</access>
6218              </field>
6219              <field>
6220                <name>PC_MASK_0</name>
6221                <description>See MS0_CTL.PC_MASK_0.</description>
6222                <bitRange>[16:16]</bitRange>
6223                <access>read-only</access>
6224              </field>
6225              <field>
6226                <name>PC_MASK_15_TO_1</name>
6227                <description>See MS0_CTL.PC_MASK_15_TO_1.</description>
6228                <bitRange>[31:17]</bitRange>
6229                <access>read-write</access>
6230              </field>
6231            </fields>
6232          </register>
6233          <register>
6234            <name>MS2_CTL</name>
6235            <description>Master 2 protection context control</description>
6236            <addressOffset>0x8</addressOffset>
6237            <size>32</size>
6238            <access>read-write</access>
6239            <resetValue>0x303</resetValue>
6240            <resetMask>0xFFFF0303</resetMask>
6241            <fields>
6242              <field>
6243                <name>P</name>
6244                <description>See MS0_CTL.P.</description>
6245                <bitRange>[0:0]</bitRange>
6246                <access>read-write</access>
6247              </field>
6248              <field>
6249                <name>NS</name>
6250                <description>See MS0_CTL.NS.</description>
6251                <bitRange>[1:1]</bitRange>
6252                <access>read-write</access>
6253              </field>
6254              <field>
6255                <name>PRIO</name>
6256                <description>See MS0_CTL.PRIO</description>
6257                <bitRange>[9:8]</bitRange>
6258                <access>read-write</access>
6259              </field>
6260              <field>
6261                <name>PC_MASK_0</name>
6262                <description>See MS0_CTL.PC_MASK_0.</description>
6263                <bitRange>[16:16]</bitRange>
6264                <access>read-only</access>
6265              </field>
6266              <field>
6267                <name>PC_MASK_15_TO_1</name>
6268                <description>See MS0_CTL.PC_MASK_15_TO_1.</description>
6269                <bitRange>[31:17]</bitRange>
6270                <access>read-write</access>
6271              </field>
6272            </fields>
6273          </register>
6274          <register>
6275            <name>MS3_CTL</name>
6276            <description>Master 3 protection context control</description>
6277            <addressOffset>0xC</addressOffset>
6278            <size>32</size>
6279            <access>read-write</access>
6280            <resetValue>0x303</resetValue>
6281            <resetMask>0xFFFF0303</resetMask>
6282            <fields>
6283              <field>
6284                <name>P</name>
6285                <description>See MS0_CTL.P.</description>
6286                <bitRange>[0:0]</bitRange>
6287                <access>read-write</access>
6288              </field>
6289              <field>
6290                <name>NS</name>
6291                <description>See MS0_CTL.NS.</description>
6292                <bitRange>[1:1]</bitRange>
6293                <access>read-write</access>
6294              </field>
6295              <field>
6296                <name>PRIO</name>
6297                <description>See MS0_CTL.PRIO</description>
6298                <bitRange>[9:8]</bitRange>
6299                <access>read-write</access>
6300              </field>
6301              <field>
6302                <name>PC_MASK_0</name>
6303                <description>See MS0_CTL.PC_MASK_0.</description>
6304                <bitRange>[16:16]</bitRange>
6305                <access>read-only</access>
6306              </field>
6307              <field>
6308                <name>PC_MASK_15_TO_1</name>
6309                <description>See MS0_CTL.PC_MASK_15_TO_1.</description>
6310                <bitRange>[31:17]</bitRange>
6311                <access>read-write</access>
6312              </field>
6313            </fields>
6314          </register>
6315          <register>
6316            <name>MS4_CTL</name>
6317            <description>Master 4 protection context control</description>
6318            <addressOffset>0x10</addressOffset>
6319            <size>32</size>
6320            <access>read-write</access>
6321            <resetValue>0x303</resetValue>
6322            <resetMask>0xFFFF0303</resetMask>
6323            <fields>
6324              <field>
6325                <name>P</name>
6326                <description>See MS0_CTL.P.</description>
6327                <bitRange>[0:0]</bitRange>
6328                <access>read-write</access>
6329              </field>
6330              <field>
6331                <name>NS</name>
6332                <description>See MS0_CTL.NS.</description>
6333                <bitRange>[1:1]</bitRange>
6334                <access>read-write</access>
6335              </field>
6336              <field>
6337                <name>PRIO</name>
6338                <description>See MS0_CTL.PRIO</description>
6339                <bitRange>[9:8]</bitRange>
6340                <access>read-write</access>
6341              </field>
6342              <field>
6343                <name>PC_MASK_0</name>
6344                <description>See MS0_CTL.PC_MASK_0.</description>
6345                <bitRange>[16:16]</bitRange>
6346                <access>read-only</access>
6347              </field>
6348              <field>
6349                <name>PC_MASK_15_TO_1</name>
6350                <description>See MS0_CTL.PC_MASK_15_TO_1.</description>
6351                <bitRange>[31:17]</bitRange>
6352                <access>read-write</access>
6353              </field>
6354            </fields>
6355          </register>
6356          <register>
6357            <name>MS5_CTL</name>
6358            <description>Master 5 protection context control</description>
6359            <addressOffset>0x14</addressOffset>
6360            <size>32</size>
6361            <access>read-write</access>
6362            <resetValue>0x303</resetValue>
6363            <resetMask>0xFFFF0303</resetMask>
6364            <fields>
6365              <field>
6366                <name>P</name>
6367                <description>See MS0_CTL.P.</description>
6368                <bitRange>[0:0]</bitRange>
6369                <access>read-write</access>
6370              </field>
6371              <field>
6372                <name>NS</name>
6373                <description>See MS0_CTL.NS.</description>
6374                <bitRange>[1:1]</bitRange>
6375                <access>read-write</access>
6376              </field>
6377              <field>
6378                <name>PRIO</name>
6379                <description>See MS0_CTL.PRIO</description>
6380                <bitRange>[9:8]</bitRange>
6381                <access>read-write</access>
6382              </field>
6383              <field>
6384                <name>PC_MASK_0</name>
6385                <description>See MS0_CTL.PC_MASK_0.</description>
6386                <bitRange>[16:16]</bitRange>
6387                <access>read-only</access>
6388              </field>
6389              <field>
6390                <name>PC_MASK_15_TO_1</name>
6391                <description>See MS0_CTL.PC_MASK_15_TO_1.</description>
6392                <bitRange>[31:17]</bitRange>
6393                <access>read-write</access>
6394              </field>
6395            </fields>
6396          </register>
6397          <register>
6398            <name>MS6_CTL</name>
6399            <description>Master 6 protection context control</description>
6400            <addressOffset>0x18</addressOffset>
6401            <size>32</size>
6402            <access>read-write</access>
6403            <resetValue>0x303</resetValue>
6404            <resetMask>0xFFFF0303</resetMask>
6405            <fields>
6406              <field>
6407                <name>P</name>
6408                <description>See MS0_CTL.P.</description>
6409                <bitRange>[0:0]</bitRange>
6410                <access>read-write</access>
6411              </field>
6412              <field>
6413                <name>NS</name>
6414                <description>See MS0_CTL.NS.</description>
6415                <bitRange>[1:1]</bitRange>
6416                <access>read-write</access>
6417              </field>
6418              <field>
6419                <name>PRIO</name>
6420                <description>See MS0_CTL.PRIO</description>
6421                <bitRange>[9:8]</bitRange>
6422                <access>read-write</access>
6423              </field>
6424              <field>
6425                <name>PC_MASK_0</name>
6426                <description>See MS0_CTL.PC_MASK_0.</description>
6427                <bitRange>[16:16]</bitRange>
6428                <access>read-only</access>
6429              </field>
6430              <field>
6431                <name>PC_MASK_15_TO_1</name>
6432                <description>See MS0_CTL.PC_MASK_15_TO_1.</description>
6433                <bitRange>[31:17]</bitRange>
6434                <access>read-write</access>
6435              </field>
6436            </fields>
6437          </register>
6438          <register>
6439            <name>MS7_CTL</name>
6440            <description>Master 7 protection context control</description>
6441            <addressOffset>0x1C</addressOffset>
6442            <size>32</size>
6443            <access>read-write</access>
6444            <resetValue>0x303</resetValue>
6445            <resetMask>0xFFFF0303</resetMask>
6446            <fields>
6447              <field>
6448                <name>P</name>
6449                <description>See MS0_CTL.P.</description>
6450                <bitRange>[0:0]</bitRange>
6451                <access>read-write</access>
6452              </field>
6453              <field>
6454                <name>NS</name>
6455                <description>See MS0_CTL.NS.</description>
6456                <bitRange>[1:1]</bitRange>
6457                <access>read-write</access>
6458              </field>
6459              <field>
6460                <name>PRIO</name>
6461                <description>See MS0_CTL.PRIO</description>
6462                <bitRange>[9:8]</bitRange>
6463                <access>read-write</access>
6464              </field>
6465              <field>
6466                <name>PC_MASK_0</name>
6467                <description>See MS0_CTL.PC_MASK_0.</description>
6468                <bitRange>[16:16]</bitRange>
6469                <access>read-only</access>
6470              </field>
6471              <field>
6472                <name>PC_MASK_15_TO_1</name>
6473                <description>See MS0_CTL.PC_MASK_15_TO_1.</description>
6474                <bitRange>[31:17]</bitRange>
6475                <access>read-write</access>
6476              </field>
6477            </fields>
6478          </register>
6479          <register>
6480            <name>MS8_CTL</name>
6481            <description>Master 8 protection context control</description>
6482            <addressOffset>0x20</addressOffset>
6483            <size>32</size>
6484            <access>read-write</access>
6485            <resetValue>0x303</resetValue>
6486            <resetMask>0xFFFF0303</resetMask>
6487            <fields>
6488              <field>
6489                <name>P</name>
6490                <description>See MS0_CTL.P.</description>
6491                <bitRange>[0:0]</bitRange>
6492                <access>read-write</access>
6493              </field>
6494              <field>
6495                <name>NS</name>
6496                <description>See MS0_CTL.NS.</description>
6497                <bitRange>[1:1]</bitRange>
6498                <access>read-write</access>
6499              </field>
6500              <field>
6501                <name>PRIO</name>
6502                <description>See MS0_CTL.PRIO</description>
6503                <bitRange>[9:8]</bitRange>
6504                <access>read-write</access>
6505              </field>
6506              <field>
6507                <name>PC_MASK_0</name>
6508                <description>See MS0_CTL.PC_MASK_0.</description>
6509                <bitRange>[16:16]</bitRange>
6510                <access>read-only</access>
6511              </field>
6512              <field>
6513                <name>PC_MASK_15_TO_1</name>
6514                <description>See MS0_CTL.PC_MASK_15_TO_1.</description>
6515                <bitRange>[31:17]</bitRange>
6516                <access>read-write</access>
6517              </field>
6518            </fields>
6519          </register>
6520          <register>
6521            <name>MS9_CTL</name>
6522            <description>Master 9 protection context control</description>
6523            <addressOffset>0x24</addressOffset>
6524            <size>32</size>
6525            <access>read-write</access>
6526            <resetValue>0x303</resetValue>
6527            <resetMask>0xFFFF0303</resetMask>
6528            <fields>
6529              <field>
6530                <name>P</name>
6531                <description>See MS0_CTL.P.</description>
6532                <bitRange>[0:0]</bitRange>
6533                <access>read-write</access>
6534              </field>
6535              <field>
6536                <name>NS</name>
6537                <description>See MS0_CTL.NS.</description>
6538                <bitRange>[1:1]</bitRange>
6539                <access>read-write</access>
6540              </field>
6541              <field>
6542                <name>PRIO</name>
6543                <description>See MS0_CTL.PRIO</description>
6544                <bitRange>[9:8]</bitRange>
6545                <access>read-write</access>
6546              </field>
6547              <field>
6548                <name>PC_MASK_0</name>
6549                <description>See MS0_CTL.PC_MASK_0.</description>
6550                <bitRange>[16:16]</bitRange>
6551                <access>read-only</access>
6552              </field>
6553              <field>
6554                <name>PC_MASK_15_TO_1</name>
6555                <description>See MS0_CTL.PC_MASK_15_TO_1.</description>
6556                <bitRange>[31:17]</bitRange>
6557                <access>read-write</access>
6558              </field>
6559            </fields>
6560          </register>
6561          <register>
6562            <name>MS10_CTL</name>
6563            <description>Master 10 protection context control</description>
6564            <addressOffset>0x28</addressOffset>
6565            <size>32</size>
6566            <access>read-write</access>
6567            <resetValue>0x303</resetValue>
6568            <resetMask>0xFFFF0303</resetMask>
6569            <fields>
6570              <field>
6571                <name>P</name>
6572                <description>See MS0_CTL.P.</description>
6573                <bitRange>[0:0]</bitRange>
6574                <access>read-write</access>
6575              </field>
6576              <field>
6577                <name>NS</name>
6578                <description>See MS0_CTL.NS.</description>
6579                <bitRange>[1:1]</bitRange>
6580                <access>read-write</access>
6581              </field>
6582              <field>
6583                <name>PRIO</name>
6584                <description>See MS0_CTL.PRIO</description>
6585                <bitRange>[9:8]</bitRange>
6586                <access>read-write</access>
6587              </field>
6588              <field>
6589                <name>PC_MASK_0</name>
6590                <description>See MS0_CTL.PC_MASK_0.</description>
6591                <bitRange>[16:16]</bitRange>
6592                <access>read-only</access>
6593              </field>
6594              <field>
6595                <name>PC_MASK_15_TO_1</name>
6596                <description>See MS0_CTL.PC_MASK_15_TO_1.</description>
6597                <bitRange>[31:17]</bitRange>
6598                <access>read-write</access>
6599              </field>
6600            </fields>
6601          </register>
6602          <register>
6603            <name>MS11_CTL</name>
6604            <description>Master 11 protection context control</description>
6605            <addressOffset>0x2C</addressOffset>
6606            <size>32</size>
6607            <access>read-write</access>
6608            <resetValue>0x303</resetValue>
6609            <resetMask>0xFFFF0303</resetMask>
6610            <fields>
6611              <field>
6612                <name>P</name>
6613                <description>See MS0_CTL.P.</description>
6614                <bitRange>[0:0]</bitRange>
6615                <access>read-write</access>
6616              </field>
6617              <field>
6618                <name>NS</name>
6619                <description>See MS0_CTL.NS.</description>
6620                <bitRange>[1:1]</bitRange>
6621                <access>read-write</access>
6622              </field>
6623              <field>
6624                <name>PRIO</name>
6625                <description>See MS0_CTL.PRIO</description>
6626                <bitRange>[9:8]</bitRange>
6627                <access>read-write</access>
6628              </field>
6629              <field>
6630                <name>PC_MASK_0</name>
6631                <description>See MS0_CTL.PC_MASK_0.</description>
6632                <bitRange>[16:16]</bitRange>
6633                <access>read-only</access>
6634              </field>
6635              <field>
6636                <name>PC_MASK_15_TO_1</name>
6637                <description>See MS0_CTL.PC_MASK_15_TO_1.</description>
6638                <bitRange>[31:17]</bitRange>
6639                <access>read-write</access>
6640              </field>
6641            </fields>
6642          </register>
6643          <register>
6644            <name>MS12_CTL</name>
6645            <description>Master 12 protection context control</description>
6646            <addressOffset>0x30</addressOffset>
6647            <size>32</size>
6648            <access>read-write</access>
6649            <resetValue>0x303</resetValue>
6650            <resetMask>0xFFFF0303</resetMask>
6651            <fields>
6652              <field>
6653                <name>P</name>
6654                <description>See MS0_CTL.P.</description>
6655                <bitRange>[0:0]</bitRange>
6656                <access>read-write</access>
6657              </field>
6658              <field>
6659                <name>NS</name>
6660                <description>See MS0_CTL.NS.</description>
6661                <bitRange>[1:1]</bitRange>
6662                <access>read-write</access>
6663              </field>
6664              <field>
6665                <name>PRIO</name>
6666                <description>See MS0_CTL.PRIO</description>
6667                <bitRange>[9:8]</bitRange>
6668                <access>read-write</access>
6669              </field>
6670              <field>
6671                <name>PC_MASK_0</name>
6672                <description>See MS0_CTL.PC_MASK_0.</description>
6673                <bitRange>[16:16]</bitRange>
6674                <access>read-only</access>
6675              </field>
6676              <field>
6677                <name>PC_MASK_15_TO_1</name>
6678                <description>See MS0_CTL.PC_MASK_15_TO_1.</description>
6679                <bitRange>[31:17]</bitRange>
6680                <access>read-write</access>
6681              </field>
6682            </fields>
6683          </register>
6684          <register>
6685            <name>MS13_CTL</name>
6686            <description>Master 13 protection context control</description>
6687            <addressOffset>0x34</addressOffset>
6688            <size>32</size>
6689            <access>read-write</access>
6690            <resetValue>0x303</resetValue>
6691            <resetMask>0xFFFF0303</resetMask>
6692            <fields>
6693              <field>
6694                <name>P</name>
6695                <description>See MS0_CTL.P.</description>
6696                <bitRange>[0:0]</bitRange>
6697                <access>read-write</access>
6698              </field>
6699              <field>
6700                <name>NS</name>
6701                <description>See MS0_CTL.NS.</description>
6702                <bitRange>[1:1]</bitRange>
6703                <access>read-write</access>
6704              </field>
6705              <field>
6706                <name>PRIO</name>
6707                <description>See MS0_CTL.PRIO</description>
6708                <bitRange>[9:8]</bitRange>
6709                <access>read-write</access>
6710              </field>
6711              <field>
6712                <name>PC_MASK_0</name>
6713                <description>See MS0_CTL.PC_MASK_0.</description>
6714                <bitRange>[16:16]</bitRange>
6715                <access>read-only</access>
6716              </field>
6717              <field>
6718                <name>PC_MASK_15_TO_1</name>
6719                <description>See MS0_CTL.PC_MASK_15_TO_1.</description>
6720                <bitRange>[31:17]</bitRange>
6721                <access>read-write</access>
6722              </field>
6723            </fields>
6724          </register>
6725          <register>
6726            <name>MS14_CTL</name>
6727            <description>Master 14 protection context control</description>
6728            <addressOffset>0x38</addressOffset>
6729            <size>32</size>
6730            <access>read-write</access>
6731            <resetValue>0x303</resetValue>
6732            <resetMask>0xFFFF0303</resetMask>
6733            <fields>
6734              <field>
6735                <name>P</name>
6736                <description>See MS0_CTL.P.</description>
6737                <bitRange>[0:0]</bitRange>
6738                <access>read-write</access>
6739              </field>
6740              <field>
6741                <name>NS</name>
6742                <description>See MS0_CTL.NS.</description>
6743                <bitRange>[1:1]</bitRange>
6744                <access>read-write</access>
6745              </field>
6746              <field>
6747                <name>PRIO</name>
6748                <description>See MS0_CTL.PRIO</description>
6749                <bitRange>[9:8]</bitRange>
6750                <access>read-write</access>
6751              </field>
6752              <field>
6753                <name>PC_MASK_0</name>
6754                <description>See MS0_CTL.PC_MASK_0.</description>
6755                <bitRange>[16:16]</bitRange>
6756                <access>read-only</access>
6757              </field>
6758              <field>
6759                <name>PC_MASK_15_TO_1</name>
6760                <description>See MS0_CTL.PC_MASK_15_TO_1.</description>
6761                <bitRange>[31:17]</bitRange>
6762                <access>read-write</access>
6763              </field>
6764            </fields>
6765          </register>
6766          <register>
6767            <name>MS15_CTL</name>
6768            <description>Master 15 protection context control</description>
6769            <addressOffset>0x3C</addressOffset>
6770            <size>32</size>
6771            <access>read-write</access>
6772            <resetValue>0x303</resetValue>
6773            <resetMask>0xFFFF0303</resetMask>
6774            <fields>
6775              <field>
6776                <name>P</name>
6777                <description>See MS0_CTL.P.</description>
6778                <bitRange>[0:0]</bitRange>
6779                <access>read-write</access>
6780              </field>
6781              <field>
6782                <name>NS</name>
6783                <description>See MS0_CTL.NS.</description>
6784                <bitRange>[1:1]</bitRange>
6785                <access>read-write</access>
6786              </field>
6787              <field>
6788                <name>PRIO</name>
6789                <description>See MS0_CTL.PRIO</description>
6790                <bitRange>[9:8]</bitRange>
6791                <access>read-write</access>
6792              </field>
6793              <field>
6794                <name>PC_MASK_0</name>
6795                <description>See MS0_CTL.PC_MASK_0.</description>
6796                <bitRange>[16:16]</bitRange>
6797                <access>read-only</access>
6798              </field>
6799              <field>
6800                <name>PC_MASK_15_TO_1</name>
6801                <description>See MS0_CTL.PC_MASK_15_TO_1.</description>
6802                <bitRange>[31:17]</bitRange>
6803                <access>read-write</access>
6804              </field>
6805            </fields>
6806          </register>
6807          <cluster>
6808            <dim>16</dim>
6809            <dimIncrement>64</dimIncrement>
6810            <name>SMPU_STRUCT[%s]</name>
6811            <description>SMPU structure</description>
6812            <addressOffset>0x00002000</addressOffset>
6813            <register>
6814              <name>ADDR0</name>
6815              <description>SMPU region address 0 (slave structure)</description>
6816              <addressOffset>0x0</addressOffset>
6817              <size>32</size>
6818              <access>read-write</access>
6819              <resetValue>0x0</resetValue>
6820              <resetMask>0x0</resetMask>
6821              <fields>
6822                <field>
6823                  <name>SUBREGION_DISABLE</name>
6824                  <description>This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable:
6825Bit 0: subregion 0 disable.
6826Bit 1: subregion 1 disable.
6827Bit 2: subregion 2 disable.
6828Bit 3: subregion 3 disable.
6829Bit 4: subregion 4 disable.
6830Bit 5: subregion 5 disable.
6831Bit 6: subregion 6 disable.
6832Bit 7: subregion 7 disable.
6833E.g., a 64 KByte address region (ATT0.REGION_SIZE is '15') has eight 8 KByte subregions. The access control as defined by ATT0 applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B.</description>
6834                  <bitRange>[7:0]</bitRange>
6835                  <access>read-write</access>
6836                </field>
6837                <field>
6838                  <name>ADDR24</name>
6839                  <description>This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by ATT0.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result, some of the lesser significant address bits of ADDR24 may be ignored in determining whether a bus transfer address is within an address region. E.g., a 64 KByte address region (REGION_SIZE is '15') is 64 KByte aligned, and ADDR24[7:0] are ignored.</description>
6840                  <bitRange>[31:8]</bitRange>
6841                  <access>read-write</access>
6842                </field>
6843              </fields>
6844            </register>
6845            <register>
6846              <name>ATT0</name>
6847              <description>SMPU region attributes 0 (slave structure)</description>
6848              <addressOffset>0x4</addressOffset>
6849              <size>32</size>
6850              <access>read-write</access>
6851              <resetValue>0x100</resetValue>
6852              <resetMask>0x80000100</resetMask>
6853              <fields>
6854                <field>
6855                  <name>UR</name>
6856                  <description>User read enable:
6857'0': Disabled (user, read accesses are NOT allowed).
6858'1': Enabled (user, read accesses are allowed).</description>
6859                  <bitRange>[0:0]</bitRange>
6860                  <access>read-write</access>
6861                </field>
6862                <field>
6863                  <name>UW</name>
6864                  <description>User write enable:
6865'0': Disabled (user, write accesses are NOT allowed).
6866'1': Enabled (user, write accesses are allowed).</description>
6867                  <bitRange>[1:1]</bitRange>
6868                  <access>read-write</access>
6869                </field>
6870                <field>
6871                  <name>UX</name>
6872                  <description>User execute enable:
6873'0': Disabled (user, execute accesses are NOT allowed).
6874'1': Enabled (user, execute accesses are allowed).</description>
6875                  <bitRange>[2:2]</bitRange>
6876                  <access>read-write</access>
6877                </field>
6878                <field>
6879                  <name>PR</name>
6880                  <description>Privileged read enable:
6881'0': Disabled (privileged, read accesses are NOT allowed).
6882'1': Enabled (privileged, read accesses are allowed).</description>
6883                  <bitRange>[3:3]</bitRange>
6884                  <access>read-write</access>
6885                </field>
6886                <field>
6887                  <name>PW</name>
6888                  <description>Privileged write enable:
6889'0': Disabled (privileged, write accesses are NOT allowed).
6890'1': Enabled (privileged, write accesses are allowed).</description>
6891                  <bitRange>[4:4]</bitRange>
6892                  <access>read-write</access>
6893                </field>
6894                <field>
6895                  <name>PX</name>
6896                  <description>Privileged execute enable:
6897'0': Disabled (privileged, execute accesses are NOT allowed).
6898'1': Enabled (privileged, execute accesses are allowed).</description>
6899                  <bitRange>[5:5]</bitRange>
6900                  <access>read-write</access>
6901                </field>
6902                <field>
6903                  <name>NS</name>
6904                  <description>Non-secure:
6905'0': Secure (secure accesses allowed, non-secure access NOT allowed).
6906'1': Non-secure (both secure and non-secure accesses allowed).</description>
6907                  <bitRange>[6:6]</bitRange>
6908                  <access>read-write</access>
6909                </field>
6910                <field>
6911                  <name>PC_MASK_0</name>
6912                  <description>This field specifies protection context identifier based access control for protection context '0'.</description>
6913                  <bitRange>[8:8]</bitRange>
6914                  <access>read-only</access>
6915                </field>
6916                <field>
6917                  <name>PC_MASK_15_TO_1</name>
6918                  <description>This field specifies protection context identifier based access control.
6919Bit i: protection context i+1 enable. If '0', protection context i+1 access is disabled; i.e. not allowed. If '1', protection context i+1 access is enabled; i.e. allowed.</description>
6920                  <bitRange>[23:9]</bitRange>
6921                  <access>read-write</access>
6922                </field>
6923                <field>
6924                  <name>REGION_SIZE</name>
6925                  <description>This field specifies the region size:
6926'0'-'6': Undefined.
6927'7': 256 B region
6928'8': 512 B region
6929'9': 1 KB region
6930'10': 2 KB region
6931'11': 4 KB region
6932'12': 8 KB region
6933'13': 16 KB region
6934'14': 32 KB region
6935'15': 64 KB region
6936'16': 128 KB region
6937'17': 256 KB region
6938'18': 512 KB region
6939'19': 1 MB region
6940'20': 2 MB region
6941'21': 4 MB region
6942'22': 8 MB region
6943'23': 16 MB region
6944'24': 32 MB region
6945'25': 64 MB region
6946'26': 128 MB region
6947'27': 256 MB region
6948'28': 512 MB region
6949'39': 1 GB region
6950'30': 2 GB region
6951'31': 4 GB region</description>
6952                  <bitRange>[28:24]</bitRange>
6953                  <access>read-write</access>
6954                </field>
6955                <field>
6956                  <name>PC_MATCH</name>
6957                  <description>This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process:
6958'0': PC field participates in 'access evaluation'.
6959'1': PC field participates in 'matching'.
6960
6961'Matching' process. For each protection structure, the process identifies if a transfer address is contained within the address range. This identifies the 'matching' regions.
6962'Access evaluation' process. For each protection structure, the process evaluates the bus transfer access attributes against the access control attributes.
6963
6964Note that it is possible to define different access control for multiple protection contexts by using multiple protection structures with the same address region and PC_MATCH set to '1'.</description>
6965                  <bitRange>[30:30]</bitRange>
6966                  <access>read-write</access>
6967                </field>
6968                <field>
6969                  <name>ENABLED</name>
6970                  <description>Region enable:
6971'0': Disabled. A disabled region will never result in a match on the bus transfer address.
6972'1': Enabled.
6973
6974Note: a disabled address region performs logic gating to reduce dynamic power consumption.</description>
6975                  <bitRange>[31:31]</bitRange>
6976                  <access>read-write</access>
6977                </field>
6978              </fields>
6979            </register>
6980            <register>
6981              <name>ADDR1</name>
6982              <description>SMPU region address 1 (master structure)</description>
6983              <addressOffset>0x20</addressOffset>
6984              <size>32</size>
6985              <access>read-only</access>
6986              <resetValue>0x0</resetValue>
6987              <resetMask>0xFFFFFFFF</resetMask>
6988              <fields>
6989                <field>
6990                  <name>SUBREGION_DISABLE</name>
6991                  <description>This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable:
6992Bit 0: subregion 0 disable.
6993Bit 1: subregion 1 disable.
6994Bit 2: subregion 2 disable.
6995Bit 3: subregion 3 disable.
6996Bit 4: subregion 4 disable.
6997Bit 5: subregion 5 disable.
6998Bit 6: subregion 6 disable.
6999Bit 7: subregion 7 disable.
7000
7001Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
7002
7003Note: this field is read-only.</description>
7004                  <bitRange>[7:0]</bitRange>
7005                  <access>read-only</access>
7006                </field>
7007                <field>
7008                  <name>ADDR24</name>
7009                  <description>This field specifies the most significant bits of the 32-bit address of an address region.
7010
7011'ADDR_DEF1': base address of structure.
7012
7013Note: this field is read-only.</description>
7014                  <bitRange>[31:8]</bitRange>
7015                  <access>read-only</access>
7016                </field>
7017              </fields>
7018            </register>
7019            <register>
7020              <name>ATT1</name>
7021              <description>SMPU region attributes 1 (master structure)</description>
7022              <addressOffset>0x24</addressOffset>
7023              <size>32</size>
7024              <access>read-write</access>
7025              <resetValue>0x7000109</resetValue>
7026              <resetMask>0x9F00012D</resetMask>
7027              <fields>
7028                <field>
7029                  <name>UR</name>
7030                  <description>User read enable:
7031'0': Disabled (user, read accesses are NOT allowed).
7032'1': Enabled (user, read accesses are allowed).
7033
7034Note that this register is constant '1'; i.e. user read accesses are ALWAYS allowed.</description>
7035                  <bitRange>[0:0]</bitRange>
7036                  <access>read-only</access>
7037                </field>
7038                <field>
7039                  <name>UW</name>
7040                  <description>User write enable:
7041'0': Disabled (user, write accesses are NOT allowed).
7042'1': Enabled (user, write accesses are allowed).</description>
7043                  <bitRange>[1:1]</bitRange>
7044                  <access>read-write</access>
7045                </field>
7046                <field>
7047                  <name>UX</name>
7048                  <description>User execute enable:
7049'0': Disabled (user, execute accesses are NOT allowed).
7050'1': Enabled (user, execute accesses are allowed).
7051
7052Note that this register is constant '0'; i.e. user execute accesses are NEVER allowed.</description>
7053                  <bitRange>[2:2]</bitRange>
7054                  <access>read-only</access>
7055                </field>
7056                <field>
7057                  <name>PR</name>
7058                  <description>Privileged read enable:
7059'0': Disabled (privileged, read accesses are NOT allowed).
7060'1': Enabled (privileged, read accesses are allowed).
7061
7062Note that this register is constant '1'; i.e. privileged read accesses are ALWAYS allowed.</description>
7063                  <bitRange>[3:3]</bitRange>
7064                  <access>read-only</access>
7065                </field>
7066                <field>
7067                  <name>PW</name>
7068                  <description>Privileged write enable:
7069'0': Disabled (privileged, write accesses are NOT allowed).
7070'1': Enabled (privileged, write accesses are allowed).</description>
7071                  <bitRange>[4:4]</bitRange>
7072                  <access>read-write</access>
7073                </field>
7074                <field>
7075                  <name>PX</name>
7076                  <description>Privileged execute enable:
7077'0': Disabled (privileged, execute accesses are NOT allowed).
7078'1': Enabled (privileged, execute accesses are allowed).
7079
7080Note that this register is constant '0'; i.e. privileged execute accesses are NEVER allowed.</description>
7081                  <bitRange>[5:5]</bitRange>
7082                  <access>read-only</access>
7083                </field>
7084                <field>
7085                  <name>NS</name>
7086                  <description>Non-secure:
7087'0': Secure (secure accesses allowed, non-secure access NOT allowed).
7088'1': Non-secure (both secure and non-secure accesses allowed).</description>
7089                  <bitRange>[6:6]</bitRange>
7090                  <access>read-write</access>
7091                </field>
7092                <field>
7093                  <name>PC_MASK_0</name>
7094                  <description>This field specifies protection context identifier based access control for protection context '0'.</description>
7095                  <bitRange>[8:8]</bitRange>
7096                  <access>read-only</access>
7097                </field>
7098                <field>
7099                  <name>PC_MASK_15_TO_1</name>
7100                  <description>This field specifies protection context identifier based access control.
7101Bit i: protection context i+1 enable. If '0', protection context i+1 access is disabled; i.e. not allowed. If '1', protection context i+1 access is enabled; i.e. allowed.</description>
7102                  <bitRange>[23:9]</bitRange>
7103                  <access>read-write</access>
7104                </field>
7105                <field>
7106                  <name>REGION_SIZE</name>
7107                  <description>This field specifies the region size:
7108'7': 256 B region (8 32 B subregions)
7109
7110Note: this field is read-only.</description>
7111                  <bitRange>[28:24]</bitRange>
7112                  <access>read-only</access>
7113                </field>
7114                <field>
7115                  <name>PC_MATCH</name>
7116                  <description>This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process:
7117'0': PC field participates in 'access evaluation'.
7118'1': PC field participates in 'matching'.
7119
7120'Matching' process. For each protection structure, the process identifies if a transfer address is contained within the address range. This identifies the 'matching' regions.
7121'Access evaluation' process. For each protection structure, the process evaluates the bus transfer access attributes against the access control attributes.
7122
7123Note that it is possible to define different access control for multiple protection contexts by using multiple protection structures with the same address region and PC_MATCH set to '1'.</description>
7124                  <bitRange>[30:30]</bitRange>
7125                  <access>read-write</access>
7126                </field>
7127                <field>
7128                  <name>ENABLED</name>
7129                  <description>Region enable:
7130'0': Disabled. A disabled region will never result in a match on the bus transfer address.
7131'1': Enabled.</description>
7132                  <bitRange>[31:31]</bitRange>
7133                  <access>read-write</access>
7134                </field>
7135              </fields>
7136            </register>
7137          </cluster>
7138        </cluster>
7139        <cluster>
7140          <dim>16</dim>
7141          <dimIncrement>1024</dimIncrement>
7142          <name>MPU[%s]</name>
7143          <description>MPU</description>
7144          <addressOffset>0x00004000</addressOffset>
7145          <register>
7146            <name>MS_CTL</name>
7147            <description>Master control</description>
7148            <addressOffset>0x0</addressOffset>
7149            <size>32</size>
7150            <access>read-write</access>
7151            <resetValue>0x0</resetValue>
7152            <resetMask>0xF000F</resetMask>
7153            <fields>
7154              <field>
7155                <name>PC</name>
7156                <description>Active protection context (PC). Modifications to this field are constrained by the associated SMPU MS_CTL.PC_MASK_0 and MS_CTL.PC_MASK_15_TO_1[] fields. In addition, a write transfer with protection context '0' can change this field (protection context 0 has unrestricted access).
7157
7158The CM0+ MPU MS_CTL register is special: the PC field is modifiable by BOTH HW and SW (for all other masters, the MPU MS_CTL.PC field is modifiable by SW ONLY. For CM0+ PC field HW modifications, the following holds:
7159* On entry of a CM0_PC0/1/2/3_HANDLER exception/interrupt handler:
7160   IF (the new PC is the same as MS_CTL.PC)
7161       PC is not affected; PC_SAVED is not affected.
7162   ELSE IF (CM0_PC_CTL.VALID[MS_CTL.PC])
7163       An AHB-Lite bus error is generated for the exception handler fetch;
7164       PC is not affected; PC_SAVED is not affected.
7165   ELSE
7166       PC = 'new PC'; PC_SAVED = PC (push operation).
7167* On entry of any other exception/interrupt handler:
7168   PC = PC_SAVED; PC_SAVED is not affected (pop operation).
7169
7170Note that the CM0_PC0/1/2/3_HANDLER and CM0_PC_CTL registers are part of repecitve CPUSS MMIO registers.
7171
7172Note: this field is NOT used by the DW controllers, DMA controller, AXI DMA controller, CRYPTO component and VIDEOSS.</description>
7173                <bitRange>[3:0]</bitRange>
7174                <access>read-write</access>
7175              </field>
7176              <field>
7177                <name>PC_SAVED</name>
7178                <description>Saved protection context. Modifications to this field are constrained by the associated SMPU MS_CTL.PC_MASK_0 and MS_CTL.PC_MASK_15_TO_1[] fields.
7179
7180Note: this field is ONLY used by the CM0+.</description>
7181                <bitRange>[19:16]</bitRange>
7182                <access>read-write</access>
7183              </field>
7184            </fields>
7185          </register>
7186          <register>
7187            <dim>127</dim>
7188            <dimIncrement>4</dimIncrement>
7189            <name>MS_CTL_READ_MIR[%s]</name>
7190            <description>Master control read mirror</description>
7191            <addressOffset>0x4</addressOffset>
7192            <size>32</size>
7193            <access>read-only</access>
7194            <resetValue>0x0</resetValue>
7195            <resetMask>0xF000F</resetMask>
7196            <fields>
7197              <field>
7198                <name>PC</name>
7199                <description>Read-only mirror of MS_CTL.PC</description>
7200                <bitRange>[3:0]</bitRange>
7201                <access>read-only</access>
7202              </field>
7203              <field>
7204                <name>PC_SAVED</name>
7205                <description>Read-only mirror of MS_CTL.PC_SAVED</description>
7206                <bitRange>[19:16]</bitRange>
7207                <access>read-only</access>
7208              </field>
7209            </fields>
7210          </register>
7211          <cluster>
7212            <dim>8</dim>
7213            <dimIncrement>32</dimIncrement>
7214            <name>MPU_STRUCT[%s]</name>
7215            <description>MPU structure</description>
7216            <addressOffset>0x00000200</addressOffset>
7217            <register>
7218              <name>ADDR</name>
7219              <description>MPU region address</description>
7220              <addressOffset>0x0</addressOffset>
7221              <size>32</size>
7222              <access>read-write</access>
7223              <resetValue>0x0</resetValue>
7224              <resetMask>0x0</resetMask>
7225              <fields>
7226                <field>
7227                  <name>SUBREGION_DISABLE</name>
7228                  <description>This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable:
7229Bit 0: subregion 0 disable.
7230Bit 1: subregion 1 disable.
7231Bit 2: subregion 2 disable.
7232Bit 3: subregion 3 disable.
7233Bit 4: subregion 4 disable.
7234Bit 5: subregion 5 disable.
7235Bit 6: subregion 6 disable.
7236Bit 7: subregion 7 disable.
7237E.g., a 64 KByte address region (REGION_SIZE is '15') has eight 8 KByte subregions. The access control as defined by MPU_REGION_ATT applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B.</description>
7238                  <bitRange>[7:0]</bitRange>
7239                  <access>read-write</access>
7240                </field>
7241                <field>
7242                  <name>ADDR24</name>
7243                  <description>This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by ATT.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result, some of the lesser significant address bits of ADDR24 may be ignored in determining whether a bus transfer address is within an address region. E.g., a 64 KByte address region (REGION_SIZE is '15') is 64 KByte aligned, and ADDR24[7:0] are ignored.</description>
7244                  <bitRange>[31:8]</bitRange>
7245                  <access>read-write</access>
7246                </field>
7247              </fields>
7248            </register>
7249            <register>
7250              <name>ATT</name>
7251              <description>MPU region attrributes</description>
7252              <addressOffset>0x4</addressOffset>
7253              <size>32</size>
7254              <access>read-write</access>
7255              <resetValue>0x0</resetValue>
7256              <resetMask>0x80000000</resetMask>
7257              <fields>
7258                <field>
7259                  <name>UR</name>
7260                  <description>User read enable:
7261'0': Disabled (user, read accesses are NOT allowed).
7262'1': Enabled (user, read accesses are allowed).</description>
7263                  <bitRange>[0:0]</bitRange>
7264                  <access>read-write</access>
7265                </field>
7266                <field>
7267                  <name>UW</name>
7268                  <description>User write enable:
7269'0': Disabled (user, write accesses are NOT allowed).
7270'1': Enabled (user, write accesses are allowed).</description>
7271                  <bitRange>[1:1]</bitRange>
7272                  <access>read-write</access>
7273                </field>
7274                <field>
7275                  <name>UX</name>
7276                  <description>User execute enable:
7277'0': Disabled (user, execute accesses are NOT allowed).
7278'1': Enabled (user, execute accesses are allowed).</description>
7279                  <bitRange>[2:2]</bitRange>
7280                  <access>read-write</access>
7281                </field>
7282                <field>
7283                  <name>PR</name>
7284                  <description>Privileged read enable:
7285'0': Disabled (privileged, read accesses are NOT allowed).
7286'1': Enabled (privileged, read accesses are allowed).</description>
7287                  <bitRange>[3:3]</bitRange>
7288                  <access>read-write</access>
7289                </field>
7290                <field>
7291                  <name>PW</name>
7292                  <description>Privileged write enable:
7293'0': Disabled (privileged, write accesses are NOT allowed).
7294'1': Enabled (privileged, write accesses are allowed).</description>
7295                  <bitRange>[4:4]</bitRange>
7296                  <access>read-write</access>
7297                </field>
7298                <field>
7299                  <name>PX</name>
7300                  <description>Privileged execute enable:
7301'0': Disabled (privileged, execute accesses are NOT allowed).
7302'1': Enabled (privileged, execute accesses are allowed).</description>
7303                  <bitRange>[5:5]</bitRange>
7304                  <access>read-write</access>
7305                </field>
7306                <field>
7307                  <name>NS</name>
7308                  <description>Non-secure:
7309'0': Secure (secure accesses allowed, non-secure access NOT allowed).
7310'1': Non-secure (both secure and non-secure accesses allowed).</description>
7311                  <bitRange>[6:6]</bitRange>
7312                  <access>read-write</access>
7313                </field>
7314                <field>
7315                  <name>REGION_SIZE</name>
7316                  <description>This field specifies the region size:
7317'0'-'6': Undefined.
7318'7': 256 B region
7319'8': 512 B region
7320'9': 1 KB region
7321'10': 2 KB region
7322'11': 4 KB region
7323'12': 8 KB region
7324'13': 16 KB region
7325'14': 32 KB region
7326'15': 64 KB region
7327'16': 128 KB region
7328'17': 256 KB region
7329'18': 512 KB region
7330'19': 1 MB region
7331'20': 2 MB region
7332'21': 4 MB region
7333'22': 8 MB region
7334'23': 16 MB region
7335'24': 32 MB region
7336'25': 64 MB region
7337'26': 128 MB region
7338'27': 256 MB region
7339'28': 512 MB region
7340'39': 1 GB region
7341'30': 2 GB region
7342'31': 4 GB region</description>
7343                  <bitRange>[28:24]</bitRange>
7344                  <access>read-write</access>
7345                </field>
7346                <field>
7347                  <name>ENABLED</name>
7348                  <description>Region enable:
7349'0': Disabled. A disabled region will never result in a match on the bus transfer address.
7350'1': Enabled.
7351
7352Note: a disabled address region performs logic gating to reduce dynamic power consumption.</description>
7353                  <bitRange>[31:31]</bitRange>
7354                  <access>read-write</access>
7355                </field>
7356              </fields>
7357            </register>
7358          </cluster>
7359        </cluster>
7360      </registers>
7361    </peripheral>
7362    <peripheral>
7363      <name>FLASHC</name>
7364      <description>Flash controller</description>
7365      <baseAddress>0x40240000</baseAddress>
7366      <addressBlock>
7367        <offset>0</offset>
7368        <size>65536</size>
7369        <usage>registers</usage>
7370      </addressBlock>
7371      <registers>
7372        <register>
7373          <name>FLASH_CTL</name>
7374          <description>Control</description>
7375          <addressOffset>0x0</addressOffset>
7376          <size>32</size>
7377          <access>read-write</access>
7378          <resetValue>0x110000</resetValue>
7379          <resetMask>0x77330F</resetMask>
7380          <fields>
7381            <field>
7382              <name>MAIN_WS</name>
7383              <description>FLASH macro main interface wait states:
7384'0': 0 wait states.
7385...
7386'15': 15 wait states</description>
7387              <bitRange>[3:0]</bitRange>
7388              <access>read-write</access>
7389            </field>
7390            <field>
7391              <name>MAIN_MAP</name>
7392              <description>Specifies mapping of FLASH macro main array.
73930: Mapping A.
73941: Mapping B.
7395
7396This field is only used when MAIN_BANK_MODE is '1' (dual bank mode).</description>
7397              <bitRange>[8:8]</bitRange>
7398              <access>read-write</access>
7399            </field>
7400            <field>
7401              <name>WORK_MAP</name>
7402              <description>Specifies mapping of FLASH macro work array.
74030: Mapping A.
74041: Mapping B.
7405
7406This field is only used when WORK_BANK_MODE is '1' (dual bank mode).</description>
7407              <bitRange>[9:9]</bitRange>
7408              <access>read-write</access>
7409            </field>
7410            <field>
7411              <name>MAIN_BANK_MODE</name>
7412              <description>Specifies bank mode of FLASH macro main array.
74130: Single bank mode.
74141: Dual bank mode.</description>
7415              <bitRange>[12:12]</bitRange>
7416              <access>read-write</access>
7417            </field>
7418            <field>
7419              <name>WORK_BANK_MODE</name>
7420              <description>Specifies bank mode of FLASH macro work array.
74210: Single bank mode.
74221: Dual bank mode.</description>
7423              <bitRange>[13:13]</bitRange>
7424              <access>read-write</access>
7425            </field>
7426            <field>
7427              <name>MAIN_ECC_EN</name>
7428              <description>Enable ECC checking for FLASH main interface:
74290: Disabled. ECC checking/reporting on FLASH main interface is disabled. No correctable or non-correctable faults are reported.
74301: Enabled.</description>
7431              <bitRange>[16:16]</bitRange>
7432              <access>read-write</access>
7433            </field>
7434            <field>
7435              <name>MAIN_ECC_INJ_EN</name>
7436              <description>Enable error injection for FLASH main interface.
7437When'1', the parity (ECC_CTL.PARITY[7:0]) is used for a load from the ECC_CTL.WORD_ADDR[23:0] word address.</description>
7438              <bitRange>[17:17]</bitRange>
7439              <access>read-write</access>
7440            </field>
7441            <field>
7442              <name>MAIN_ERR_SILENT</name>
7443              <description>Specifies bus transfer behavior for a non-recoverable error on the FLASH macro main interface (either a non-correctable ECC error, a FLASH macro main interface internal error, a FLASH macro main interface memory hole access):
74440: Bus transfer has a bus error.
74451: Bus transfer does NOT have a bus error; i.e. the error is 'silent'
7446In either case, the erroneous FLASH macro data is returned by the bus master interface. The erroneous data is NOT placed in a bus master interface's cache and/or buffer.
7447
7448This field is ONLY used by CPU (and debug i.e. SYS_AP/CM0_AP/CM4_AP) bus transfers. Non-CPU bus transfers always have a bus transfer with a bus error, in case of a non-recoverable error.
7449
7450Note: All CPU bus masters have dedicated status registers (CM0_STATUS and CM4_STATUS) to register the occurrence of FLASH macro main interface internal errors (non-correctable ECC errors and memory hole errors are NOT registered).
7451
7452Note: fault reporting can be used to identify the error that occurred:
7453- FLASH macro main interface internal error.
7454- FLASH macro main interface non-recoverable ECC error.
7455- FLASH macro main interface recoverable ECC error.
7456- FLASH macro main interface memory hole error.</description>
7457              <bitRange>[18:18]</bitRange>
7458              <access>read-write</access>
7459            </field>
7460            <field>
7461              <name>WORK_ECC_EN</name>
7462              <description>Enable ECC checking for FLASH work interface:
74630: Disabled. ECC checking/reporting on FLASH work interface is disabled. No correctable or non-correctable faults are reported.
74641: Enabled.</description>
7465              <bitRange>[20:20]</bitRange>
7466              <access>read-write</access>
7467            </field>
7468            <field>
7469              <name>WORK_ECC_INJ_EN</name>
7470              <description>Enable error injection for FLASH work interface.
7471When'1', the parity (ECC_CTL.PARITY[6:0]) is used for a load from the ECC_CTL.WORD_ADDR[23:0] word address.</description>
7472              <bitRange>[21:21]</bitRange>
7473              <access>read-write</access>
7474            </field>
7475            <field>
7476              <name>WORK_ERR_SILENT</name>
7477              <description>Specifies bus transfer behavior for a non-recoverable error on the FLASH macro work interface (either a non-correctable ECC error, a FLASH macro work interface internal error, a FLASH macro work interface memory hole access):
74780: Bus transfer has a bus error.
74791: Bus transfer does NOT have a bus error; i.e. the error is 'silent'
7480In either case, the erroneous FLASH macro data is returned by the bus master interface. The erroneous data is NOT placed in a bus master interface's cache and/or buffer.
7481
7482This field is ONLY used by CPU (and debug i.e. SYS_AP/CM0_AP/CM4_AP) bus transfers. Non-CPU bus transfers always have a bus transfer with a bus error, in case of a non-recoverable error.
7483
7484Note: All CPU bus masters have dedicated status registers (CM0_STATUS and CM4_STATUS) to register the occurrence of FLASH macro work interface internal errors (non-correctable ECC errors and memory hole errors are NOT registered).
7485
7486Note: fault reporting can be used to identify the error that occurred:
7487- FLASH macro work interface internal error.
7488- FLASH macro work interface non-recoverable ECC error.
7489- FLASH macro work interface recoverable ECC error.
7490- FLASH macro work interface memory hole error.</description>
7491              <bitRange>[22:22]</bitRange>
7492              <access>read-write</access>
7493            </field>
7494          </fields>
7495        </register>
7496        <register>
7497          <name>FLASH_PWR_CTL</name>
7498          <description>Flash power control</description>
7499          <addressOffset>0x4</addressOffset>
7500          <size>32</size>
7501          <access>read-write</access>
7502          <resetValue>0x3</resetValue>
7503          <resetMask>0x3</resetMask>
7504          <fields>
7505            <field>
7506              <name>ENABLE</name>
7507              <description>Controls 'enable' pin of the Flash memory.</description>
7508              <bitRange>[0:0]</bitRange>
7509              <access>read-write</access>
7510            </field>
7511            <field>
7512              <name>ENABLE_HV</name>
7513              <description>Controls 'enable_hv' pin of the Flash memory.</description>
7514              <bitRange>[1:1]</bitRange>
7515              <access>read-write</access>
7516            </field>
7517          </fields>
7518        </register>
7519        <register>
7520          <name>FLASH_CMD</name>
7521          <description>Command</description>
7522          <addressOffset>0x8</addressOffset>
7523          <size>32</size>
7524          <access>read-write</access>
7525          <resetValue>0x0</resetValue>
7526          <resetMask>0x3</resetMask>
7527          <fields>
7528            <field>
7529              <name>INV</name>
7530              <description>Invalidation of ALL caches (for CM0+ and CM4) and ALL buffers. SW writes a '1' to clear the caches. HW sets this field to '0' when the operation is completed. The operation takes a maximum of three clock cycles on the slowest of the clk_slow and clk_fast clocks. The caches' LRU structures are also reset to their default state.</description>
7531              <bitRange>[0:0]</bitRange>
7532              <access>read-write</access>
7533            </field>
7534            <field>
7535              <name>BUFF_INV</name>
7536              <description>Invalidation of ALL buffers (does not invalidate the caches). SW writes a '1' to clear the buffers. HW sets this field to '0' when the operation is completed. The operation takes a maximum of three clock cycles on the slowest of the clk_slow and clk_fast clocks.
7537
7538Note: the caches only capture FLASH macro main array data. Therefore, invalidating just the buffers (BUFF_INV) does not invalidate captures main array data in the caches.</description>
7539              <bitRange>[1:1]</bitRange>
7540              <access>read-write</access>
7541            </field>
7542          </fields>
7543        </register>
7544        <register>
7545          <name>ECC_CTL</name>
7546          <description>ECC control</description>
7547          <addressOffset>0x2A0</addressOffset>
7548          <size>32</size>
7549          <access>read-write</access>
7550          <resetValue>0x0</resetValue>
7551          <resetMask>0xFFFFFFFF</resetMask>
7552          <fields>
7553            <field>
7554              <name>WORD_ADDR</name>
7555              <description>Specifies the word address where an error will be injected.
7556- For cache SRAM ECC, the word address WORD_ADDR[23:0] is device address A[25:2]. On a FLASH macro refill to this word address and when the corresponding CM0/4_CA_CTL.RAM_ECC_INJ_EN bit is '1', the parity (PARITY[6:0]) is injected and stored in the cache.
7557- For FLASH main interface ECC, the word address WORD_ADDR[23:0] is device address A[26:3]. On a FLASH main interface read and when FLASH_CTL.MAIN_ECC_INJ_EN bit is '1', the parity (PARITY[7:0]) replaces the FLASH macro parity (FLASH main interface read path is manipulated).
7558- For FLASH work interface ECC, the word address WORD_ADDR[23:0] is device address A[24:2]. On a FLASH work interface read and when FLASH_CTL.WORK_ECC_INJ_EN bit is '1', the parity (PARITY[6:0]) replaces the FLASH macro parity (FLASH work interface read path is manipulated).</description>
7559              <bitRange>[23:0]</bitRange>
7560              <access>read-write</access>
7561            </field>
7562            <field>
7563              <name>PARITY</name>
7564              <description>ECC parity to use for ECC error injection at address WORD_ADDR.
7565- For cache SRAM ECC, the 7-bit parity PARITY[6:0] is for a 32-bit word.
7566- For FLASH main interface ECC, the 8-bit parity PARITY[7:0] is for a 64-bit word.
7567- For FLASH work interface ECC, the 7-bit parity PARITY[6:0] is for a 32-bit word.</description>
7568              <bitRange>[31:24]</bitRange>
7569              <access>read-write</access>
7570            </field>
7571          </fields>
7572        </register>
7573        <register>
7574          <name>FM_SRAM_ECC_CTL0</name>
7575          <description>eCT Flash SRAM ECC control 0</description>
7576          <addressOffset>0x2B0</addressOffset>
7577          <size>32</size>
7578          <access>read-write</access>
7579          <resetValue>0x0</resetValue>
7580          <resetMask>0xFFFFFFFF</resetMask>
7581          <fields>
7582            <field>
7583              <name>ECC_INJ_DATA</name>
7584              <description>32-bit data for ECC error injection test of eCT Flash SRAM ECC logic.</description>
7585              <bitRange>[31:0]</bitRange>
7586              <access>read-write</access>
7587            </field>
7588          </fields>
7589        </register>
7590        <register>
7591          <name>FM_SRAM_ECC_CTL1</name>
7592          <description>eCT Flash SRAM ECC control 1</description>
7593          <addressOffset>0x2B4</addressOffset>
7594          <size>32</size>
7595          <access>read-write</access>
7596          <resetValue>0x0</resetValue>
7597          <resetMask>0x7F</resetMask>
7598          <fields>
7599            <field>
7600              <name>ECC_INJ_PARITY</name>
7601              <description>7-bit parity for ECC error injection test of eCT Flash SRAM ECC logic.</description>
7602              <bitRange>[6:0]</bitRange>
7603              <access>read-write</access>
7604            </field>
7605          </fields>
7606        </register>
7607        <register>
7608          <name>FM_SRAM_ECC_CTL2</name>
7609          <description>eCT Flash SRAM ECC control 2</description>
7610          <addressOffset>0x2B8</addressOffset>
7611          <size>32</size>
7612          <access>read-only</access>
7613          <resetValue>0x0</resetValue>
7614          <resetMask>0xFFFFFFFF</resetMask>
7615          <fields>
7616            <field>
7617              <name>CORRECTED_DATA</name>
7618              <description>32-bit corrected data output of the ECC syndrome logic.</description>
7619              <bitRange>[31:0]</bitRange>
7620              <access>read-only</access>
7621            </field>
7622          </fields>
7623        </register>
7624        <register>
7625          <name>FM_SRAM_ECC_CTL3</name>
7626          <description>eCT Flash SRAM ECC control 3</description>
7627          <addressOffset>0x2BC</addressOffset>
7628          <size>32</size>
7629          <access>read-write</access>
7630          <resetValue>0x1</resetValue>
7631          <resetMask>0x111</resetMask>
7632          <fields>
7633            <field>
7634              <name>ECC_ENABLE</name>
7635              <description>ECC generation/check enable for eCT Flash SRAM memory.</description>
7636              <bitRange>[0:0]</bitRange>
7637              <access>read-write</access>
7638            </field>
7639            <field>
7640              <name>ECC_INJ_EN</name>
7641              <description>eCT Flash SRAM ECC error injection test enable. Follow the steps below for ECC logic test:
76421. Write corrupted or uncorrupted 39-bit data to FM_SRAM_ECC_CTL0/1 registers.
76432. Set the ECC_INJ_EN bit to '1'.
76443. Confirm that the bit ECC_TEST_FAIL is '0'. If this is not the case, start over at item 1 because the eCT Flash was not idle.
76454. Check the corrected data in FM_SRAM_ECC_CTL2.
76465. Confirm that fault was reported to fault structure, and check syndrome (only applicable if
7647corrupted data was written in step 1).
76486. If not finished, start over at 1 with different data.</description>
7649              <bitRange>[4:4]</bitRange>
7650              <access>read-write</access>
7651            </field>
7652            <field>
7653              <name>ECC_TEST_FAIL</name>
7654              <description>Status of ECC test.
76551 : ECC test failed because eCT Flash macro is busy and using the SRAM.
76560: ECC was performed.</description>
7657              <bitRange>[8:8]</bitRange>
7658              <access>read-only</access>
7659            </field>
7660          </fields>
7661        </register>
7662        <register>
7663          <name>CM0_CA_CTL0</name>
7664          <description>CM0+ cache control</description>
7665          <addressOffset>0x400</addressOffset>
7666          <size>32</size>
7667          <access>read-write</access>
7668          <resetValue>0xC0000001</resetValue>
7669          <resetMask>0xC7030003</resetMask>
7670          <fields>
7671            <field>
7672              <name>RAM_ECC_EN</name>
7673              <description>Enable ECC checking for cache accesses:
76740: Disabled.
76751: Enabled.</description>
7676              <bitRange>[0:0]</bitRange>
7677              <access>read-write</access>
7678            </field>
7679            <field>
7680              <name>RAM_ECC_INJ_EN</name>
7681              <description>Enable error injection for cache.
7682When '1', the parity (ECC_CTL.PARITY[6:0]) is used when a refill is done from the FLASH macro to the ECC_CTL.WORD_ADDR[23:0] word address.</description>
7683              <bitRange>[1:1]</bitRange>
7684              <access>read-write</access>
7685            </field>
7686            <field>
7687              <name>WAY</name>
7688              <description>Specifies the cache way for which cache information is provided in CM0_CA_STATUS0/1/2.</description>
7689              <bitRange>[17:16]</bitRange>
7690              <access>read-write</access>
7691            </field>
7692            <field>
7693              <name>SET_ADDR</name>
7694              <description>Specifies the cache set for which cache information is provided in CM0_CA_STATUS0/1/2.</description>
7695              <bitRange>[26:24]</bitRange>
7696              <access>read-write</access>
7697            </field>
7698            <field>
7699              <name>PREF_EN</name>
7700              <description>Prefetch enable:
77010: Disabled.
77021: Enabled.
7703
7704Prefetching requires the cache to be enabled; i.e. ENABLED is '1'.</description>
7705              <bitRange>[30:30]</bitRange>
7706              <access>read-write</access>
7707            </field>
7708            <field>
7709              <name>CA_EN</name>
7710              <description>Cache enable:
77110: Disabled. The cache tag valid bits are reset to '0's and the cache LRU information is set to '1's (making way 0 the LRU way and way 3 the MRU way).
77121: Enabled.</description>
7713              <bitRange>[31:31]</bitRange>
7714              <access>read-write</access>
7715            </field>
7716          </fields>
7717        </register>
7718        <register>
7719          <name>CM0_CA_CTL1</name>
7720          <description>CM0+ cache control</description>
7721          <addressOffset>0x404</addressOffset>
7722          <size>32</size>
7723          <access>read-write</access>
7724          <resetValue>0xFA050003</resetValue>
7725          <resetMask>0xFFFF0003</resetMask>
7726          <fields>
7727            <field>
7728              <name>PWR_MODE</name>
7729              <description>Specifies power mode for CM0 cache.
7730The following sequnece should be followed for turning OFF/ON the cache SRAM.
7731Turn OFF sequence:
7732a) Write CM0_CA_CTL0 to disable cache.
7733b) Write CM0_CA_CTL1 to turn OFF cache SRAM.
7734Turn ON sequence:
7735a) Write CM0_CA_CTL1 to turn ON cache SRAM.
7736b) Delay to allow power up of cache SRAM. Delay should be at a minimum of CM0_CA_CTL2.PWRUP_DELAY CLK_SLOW clock cycles.
7737c) Write CM0_CA_CTL0 to enable cache.</description>
7738              <bitRange>[1:0]</bitRange>
7739              <access>read-write</access>
7740              <enumeratedValues>
7741                <enumeratedValue>
7742                  <name>OFF</name>
7743                  <description>Power OFF the CM0 cache SRAM.</description>
7744                  <value>0</value>
7745                </enumeratedValue>
7746                <enumeratedValue>
7747                  <name>RSVD</name>
7748                  <description>Undefined</description>
7749                  <value>1</value>
7750                </enumeratedValue>
7751                <enumeratedValue>
7752                  <name>RETAINED</name>
7753                  <description>Put CM0 cache SRAM in retained mode.</description>
7754                  <value>2</value>
7755                </enumeratedValue>
7756                <enumeratedValue>
7757                  <name>ENABLED</name>
7758                  <description>Enable/Turn ON the CM0 cache SRAM.</description>
7759                  <value>3</value>
7760                </enumeratedValue>
7761              </enumeratedValues>
7762            </field>
7763            <field>
7764              <name>VECTKEYSTAT</name>
7765              <description>Register key (to prevent accidental writes).
7766- Should be written with a 0x05fa key value for the write to take effect.
7767- Always reads as 0xfa05.
7768
7769Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW.</description>
7770              <bitRange>[31:16]</bitRange>
7771              <access>read-only</access>
7772            </field>
7773          </fields>
7774        </register>
7775        <register>
7776          <name>CM0_CA_CTL2</name>
7777          <description>CM0+ cache control</description>
7778          <addressOffset>0x408</addressOffset>
7779          <size>32</size>
7780          <access>read-write</access>
7781          <resetValue>0x12C</resetValue>
7782          <resetMask>0x3FF</resetMask>
7783          <fields>
7784            <field>
7785              <name>PWRUP_DELAY</name>
7786              <description>Number clock cycles delay needed after power domain power up</description>
7787              <bitRange>[9:0]</bitRange>
7788              <access>read-write</access>
7789            </field>
7790          </fields>
7791        </register>
7792        <register>
7793          <name>CM0_CA_STATUS0</name>
7794          <description>CM0+ cache status 0</description>
7795          <addressOffset>0x440</addressOffset>
7796          <size>32</size>
7797          <access>read-only</access>
7798          <resetValue>0x0</resetValue>
7799          <resetMask>0xFFFFFFFF</resetMask>
7800          <fields>
7801            <field>
7802              <name>VALID32</name>
7803              <description>Sixteen valid bits of the cache line specified by CM0_CA_CTL.WAY and CM0_CA_CTL.SET_ADDR.</description>
7804              <bitRange>[31:0]</bitRange>
7805              <access>read-only</access>
7806            </field>
7807          </fields>
7808        </register>
7809        <register>
7810          <name>CM0_CA_STATUS1</name>
7811          <description>CM0+ cache status 1</description>
7812          <addressOffset>0x444</addressOffset>
7813          <size>32</size>
7814          <access>read-only</access>
7815          <resetValue>0x0</resetValue>
7816          <resetMask>0x0</resetMask>
7817          <fields>
7818            <field>
7819              <name>TAG</name>
7820              <description>Cache line address of the cache line specified by CM0_CA_CTL.WAY and CM0_CA_CTL.SET_ADDR.</description>
7821              <bitRange>[31:0]</bitRange>
7822              <access>read-only</access>
7823            </field>
7824          </fields>
7825        </register>
7826        <register>
7827          <name>CM0_CA_STATUS2</name>
7828          <description>CM0+ cache status 2</description>
7829          <addressOffset>0x448</addressOffset>
7830          <size>32</size>
7831          <access>read-only</access>
7832          <resetValue>0x0</resetValue>
7833          <resetMask>0x0</resetMask>
7834          <fields>
7835            <field>
7836              <name>LRU</name>
7837              <description>Six bit LRU representation of the cache set specified by CM0_CA_CTL.SET_ADDR. The encoding of the field is as follows ('X_LRU_Y' indicates that way X is Less Recently Used than way Y):
7838Bit 5: 0_LRU_1: way 0 less recently used than way 1.
7839Bit 4: 0_LRU_2.
7840Bit 3: 0_LRU_3.
7841Bit 2: 1_LRU_2.
7842Bit 1: 1_LRU_3.
7843Bit 0: 2_LRU_3.</description>
7844              <bitRange>[5:0]</bitRange>
7845              <access>read-only</access>
7846            </field>
7847          </fields>
7848        </register>
7849        <register>
7850          <name>CM0_STATUS</name>
7851          <description>CM0+ interface status</description>
7852          <addressOffset>0x460</addressOffset>
7853          <size>32</size>
7854          <access>read-write</access>
7855          <resetValue>0x0</resetValue>
7856          <resetMask>0x3</resetMask>
7857          <fields>
7858            <field>
7859              <name>MAIN_INTERNAL_ERR</name>
7860              <description>Specifies/registers the occurrence of a FLASH macro main interface internal error (typically the result of a read access while a program erase operation is ongoing) as a result of a CM0+ access (or debug access via SYS_AP/CM0_AP).
7861
7862SW clears this field to '0'. HW sets this field to '1' on a FLASH macro main interface internal error. Typically, SW reads this field after a code section to detect the occurrence of an error.
7863
7864Note: this field is independent of FLASH_CTL.MAIN_ERR_SILENT.</description>
7865              <bitRange>[0:0]</bitRange>
7866              <access>read-write</access>
7867            </field>
7868            <field>
7869              <name>WORK_INTERNAL_ERR</name>
7870              <description>See CM0_STATUS.MAIN_INTERNAL_ERROR.</description>
7871              <bitRange>[1:1]</bitRange>
7872              <access>read-write</access>
7873            </field>
7874          </fields>
7875        </register>
7876        <register>
7877          <name>CM4_CA_CTL0</name>
7878          <description>CM4 cache control</description>
7879          <addressOffset>0x480</addressOffset>
7880          <size>32</size>
7881          <access>read-write</access>
7882          <resetValue>0xC0000001</resetValue>
7883          <resetMask>0xC7030003</resetMask>
7884          <fields>
7885            <field>
7886              <name>RAM_ECC_EN</name>
7887              <description>See CM0_CA_CTL.</description>
7888              <bitRange>[0:0]</bitRange>
7889              <access>read-write</access>
7890            </field>
7891            <field>
7892              <name>RAM_ECC_INJ_EN</name>
7893              <description>See CM0_CA_CTL.</description>
7894              <bitRange>[1:1]</bitRange>
7895              <access>read-write</access>
7896            </field>
7897            <field>
7898              <name>WAY</name>
7899              <description>See CM0_CA_CTL.</description>
7900              <bitRange>[17:16]</bitRange>
7901              <access>read-write</access>
7902            </field>
7903            <field>
7904              <name>SET_ADDR</name>
7905              <description>See CM0_CA_CTL.</description>
7906              <bitRange>[26:24]</bitRange>
7907              <access>read-write</access>
7908            </field>
7909            <field>
7910              <name>PREF_EN</name>
7911              <description>See CM0_CA_CTL.</description>
7912              <bitRange>[30:30]</bitRange>
7913              <access>read-write</access>
7914            </field>
7915            <field>
7916              <name>CA_EN</name>
7917              <description>See CM0_CA_CTL.</description>
7918              <bitRange>[31:31]</bitRange>
7919              <access>read-write</access>
7920            </field>
7921          </fields>
7922        </register>
7923        <register>
7924          <name>CM4_CA_CTL1</name>
7925          <description>CM4 cache control</description>
7926          <addressOffset>0x484</addressOffset>
7927          <size>32</size>
7928          <access>read-write</access>
7929          <resetValue>0xFA050003</resetValue>
7930          <resetMask>0xFFFF0003</resetMask>
7931          <fields>
7932            <field>
7933              <name>PWR_MODE</name>
7934              <description>Specifies power mode for CM4 cache. Refer CM0_CA_CTL1 for more details.</description>
7935              <bitRange>[1:0]</bitRange>
7936              <access>read-write</access>
7937              <enumeratedValues>
7938                <enumeratedValue>
7939                  <name>OFF</name>
7940                  <description>See CM0_CA_CTL1</description>
7941                  <value>0</value>
7942                </enumeratedValue>
7943                <enumeratedValue>
7944                  <name>RSVD</name>
7945                  <description>Undefined</description>
7946                  <value>1</value>
7947                </enumeratedValue>
7948                <enumeratedValue>
7949                  <name>RETAINED</name>
7950                  <description>See CM0_CA_CTL1</description>
7951                  <value>2</value>
7952                </enumeratedValue>
7953                <enumeratedValue>
7954                  <name>ENABLED</name>
7955                  <description>See CM0_CA_CTL1</description>
7956                  <value>3</value>
7957                </enumeratedValue>
7958              </enumeratedValues>
7959            </field>
7960            <field>
7961              <name>VECTKEYSTAT</name>
7962              <description>Register key (to prevent accidental writes).
7963- Should be written with a 0x05fa key value for the write to take effect.
7964- Always reads as 0xfa05.
7965
7966Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW.</description>
7967              <bitRange>[31:16]</bitRange>
7968              <access>read-only</access>
7969            </field>
7970          </fields>
7971        </register>
7972        <register>
7973          <name>CM4_CA_CTL2</name>
7974          <description>CM4 cache control</description>
7975          <addressOffset>0x488</addressOffset>
7976          <size>32</size>
7977          <access>read-write</access>
7978          <resetValue>0x12C</resetValue>
7979          <resetMask>0x3FF</resetMask>
7980          <fields>
7981            <field>
7982              <name>PWRUP_DELAY</name>
7983              <description>Number clock cycles delay needed after power domain power up</description>
7984              <bitRange>[9:0]</bitRange>
7985              <access>read-write</access>
7986            </field>
7987          </fields>
7988        </register>
7989        <register>
7990          <name>CM4_CA_STATUS0</name>
7991          <description>CM4 cache status 0</description>
7992          <addressOffset>0x4C0</addressOffset>
7993          <size>32</size>
7994          <access>read-only</access>
7995          <resetValue>0x0</resetValue>
7996          <resetMask>0xFFFFFFFF</resetMask>
7997          <fields>
7998            <field>
7999              <name>VALID32</name>
8000              <description>See CM0_CA_STATUS0.</description>
8001              <bitRange>[31:0]</bitRange>
8002              <access>read-only</access>
8003            </field>
8004          </fields>
8005        </register>
8006        <register>
8007          <name>CM4_CA_STATUS1</name>
8008          <description>CM4 cache status 1</description>
8009          <addressOffset>0x4C4</addressOffset>
8010          <size>32</size>
8011          <access>read-only</access>
8012          <resetValue>0x0</resetValue>
8013          <resetMask>0x0</resetMask>
8014          <fields>
8015            <field>
8016              <name>TAG</name>
8017              <description>See CM0_CA_STATUS1.</description>
8018              <bitRange>[31:0]</bitRange>
8019              <access>read-only</access>
8020            </field>
8021          </fields>
8022        </register>
8023        <register>
8024          <name>CM4_CA_STATUS2</name>
8025          <description>CM4 cache status 2</description>
8026          <addressOffset>0x4C8</addressOffset>
8027          <size>32</size>
8028          <access>read-only</access>
8029          <resetValue>0x0</resetValue>
8030          <resetMask>0x0</resetMask>
8031          <fields>
8032            <field>
8033              <name>LRU</name>
8034              <description>See CM0_CA_STATUS2.</description>
8035              <bitRange>[5:0]</bitRange>
8036              <access>read-only</access>
8037            </field>
8038          </fields>
8039        </register>
8040        <register>
8041          <name>CM4_STATUS</name>
8042          <description>CM4 interface status</description>
8043          <addressOffset>0x4E0</addressOffset>
8044          <size>32</size>
8045          <access>read-write</access>
8046          <resetValue>0x0</resetValue>
8047          <resetMask>0x3</resetMask>
8048          <fields>
8049            <field>
8050              <name>MAIN_INTERNAL_ERR</name>
8051              <description>Specifies/registers the occurrence of a FLASH macro main interface internal error (typically the result of a read access while a program erase operation is ongoing) as a result of a CM4 access (or debug access via SYS_AP/CM4_AP).
8052
8053SW clears this field to '0'. HW sets this field to '1' on a FLASH macro main interface internal error. Typically, SW reads this field after a code section to detect the occurrence of an error.
8054
8055Note: this field is independent of FLASH_CTL.MAIN_ERR_SILENT.</description>
8056              <bitRange>[0:0]</bitRange>
8057              <access>read-write</access>
8058            </field>
8059            <field>
8060              <name>WORK_INTERNAL_ERR</name>
8061              <description>See CM4_STATUS.MAIN_INTERNAL_ERROR.</description>
8062              <bitRange>[1:1]</bitRange>
8063              <access>read-write</access>
8064            </field>
8065          </fields>
8066        </register>
8067        <register>
8068          <name>CRYPTO_BUFF_CTL</name>
8069          <description>Cryptography buffer control</description>
8070          <addressOffset>0x500</addressOffset>
8071          <size>32</size>
8072          <access>read-write</access>
8073          <resetValue>0x40000000</resetValue>
8074          <resetMask>0x40000000</resetMask>
8075          <fields>
8076            <field>
8077              <name>PREF_EN</name>
8078              <description>Prefetch enable:
80790: Disabled.
80801: Enabled.
8081A prefetch will be done when there is read 'hit' on the last 32-bit word of the buffer.
8082For eCT work Flash, prefetch will not be done.</description>
8083              <bitRange>[30:30]</bitRange>
8084              <access>read-write</access>
8085            </field>
8086          </fields>
8087        </register>
8088        <register>
8089          <name>DW0_BUFF_CTL</name>
8090          <description>Datawire 0 buffer control</description>
8091          <addressOffset>0x580</addressOffset>
8092          <size>32</size>
8093          <access>read-write</access>
8094          <resetValue>0x40000000</resetValue>
8095          <resetMask>0x40000000</resetMask>
8096          <fields>
8097            <field>
8098              <name>PREF_EN</name>
8099              <description>See CRYPTO_BUFF_CTL.</description>
8100              <bitRange>[30:30]</bitRange>
8101              <access>read-write</access>
8102            </field>
8103          </fields>
8104        </register>
8105        <register>
8106          <name>DW1_BUFF_CTL</name>
8107          <description>Datawire 1 buffer control</description>
8108          <addressOffset>0x600</addressOffset>
8109          <size>32</size>
8110          <access>read-write</access>
8111          <resetValue>0x40000000</resetValue>
8112          <resetMask>0x40000000</resetMask>
8113          <fields>
8114            <field>
8115              <name>PREF_EN</name>
8116              <description>See CRYPTO_BUFF_CTL.</description>
8117              <bitRange>[30:30]</bitRange>
8118              <access>read-write</access>
8119            </field>
8120          </fields>
8121        </register>
8122        <register>
8123          <name>DMAC_BUFF_CTL</name>
8124          <description>DMA controller buffer control</description>
8125          <addressOffset>0x680</addressOffset>
8126          <size>32</size>
8127          <access>read-write</access>
8128          <resetValue>0x40000000</resetValue>
8129          <resetMask>0x40000000</resetMask>
8130          <fields>
8131            <field>
8132              <name>PREF_EN</name>
8133              <description>See CRYPTO_BUFF_CTL.</description>
8134              <bitRange>[30:30]</bitRange>
8135              <access>read-write</access>
8136            </field>
8137          </fields>
8138        </register>
8139        <register>
8140          <name>EXT_MS0_BUFF_CTL</name>
8141          <description>External master 0 buffer control</description>
8142          <addressOffset>0x700</addressOffset>
8143          <size>32</size>
8144          <access>read-write</access>
8145          <resetValue>0x40000000</resetValue>
8146          <resetMask>0x40000000</resetMask>
8147          <fields>
8148            <field>
8149              <name>PREF_EN</name>
8150              <description>See CRYPTO_BUFF_CTL.</description>
8151              <bitRange>[30:30]</bitRange>
8152              <access>read-write</access>
8153            </field>
8154          </fields>
8155        </register>
8156        <register>
8157          <name>EXT_MS1_BUFF_CTL</name>
8158          <description>External master 1 buffer control</description>
8159          <addressOffset>0x780</addressOffset>
8160          <size>32</size>
8161          <access>read-write</access>
8162          <resetValue>0x40000000</resetValue>
8163          <resetMask>0x40000000</resetMask>
8164          <fields>
8165            <field>
8166              <name>PREF_EN</name>
8167              <description>See CRYPTO_BUFF_CTL.</description>
8168              <bitRange>[30:30]</bitRange>
8169              <access>read-write</access>
8170            </field>
8171          </fields>
8172        </register>
8173        <cluster>
8174          <name>FM_CTL</name>
8175          <description>Flash Macro Registers</description>
8176          <addressOffset>0x0000F000</addressOffset>
8177          <register>
8178            <name>FM_CTL</name>
8179            <description>Flash macro control</description>
8180            <addressOffset>0x0</addressOffset>
8181            <size>32</size>
8182            <access>read-write</access>
8183            <resetValue>0x0</resetValue>
8184            <resetMask>0x37F030F</resetMask>
8185            <fields>
8186              <field>
8187                <name>FM_MODE</name>
8188                <description>Requires (IF_SEL|WR_EN)=1
8189Flash macro mode selection</description>
8190                <bitRange>[3:0]</bitRange>
8191                <access>read-write</access>
8192              </field>
8193              <field>
8194                <name>FM_SEQ</name>
8195                <description>Requires (IF_SEL|WR_EN)=1
8196Flash macro sequence selection</description>
8197                <bitRange>[9:8]</bitRange>
8198                <access>read-write</access>
8199              </field>
8200              <field>
8201                <name>DAA_MUX_SEL</name>
8202                <description>Direct memory cell access address.</description>
8203                <bitRange>[22:16]</bitRange>
8204                <access>read-write</access>
8205              </field>
8206              <field>
8207                <name>IF_SEL</name>
8208                <description>Interface selection. Specifies the interface that is used for flash memory read operations:
82090: R interface is used (default value). In this case, the flash memory address is provided as part of the R signal interface.
82101: C interface is used. In this case, the flash memory address is provided by FM_MEM_ADDR (the page address) and by the C interface access offset in the FM_MEM_DATA structure.
8211Note: IF_SEL and WR_EN cannot be changed at the same time</description>
8212                <bitRange>[24:24]</bitRange>
8213                <access>read-write</access>
8214              </field>
8215              <field>
8216                <name>WR_EN</name>
8217                <description>0: normal mode
82181: Fm Write Enable
8219Note: IF_SEL and WR_EN cannot be changed at the same time</description>
8220                <bitRange>[25:25]</bitRange>
8221                <access>read-write</access>
8222              </field>
8223            </fields>
8224          </register>
8225          <register>
8226            <name>STATUS</name>
8227            <description>Status</description>
8228            <addressOffset>0x4</addressOffset>
8229            <size>32</size>
8230            <access>read-only</access>
8231            <resetValue>0x1800</resetValue>
8232            <resetMask>0xFFFFFFFF</resetMask>
8233            <fields>
8234              <field>
8235                <name>TIMER_ENABLED</name>
8236                <description>This is the timer_en bit set by writing a '1' in the TIMER_CTL bit 31. It is reset by HW when the timer expires
82370: timer not running
82381: Timer is enabled and not expired yet</description>
8239                <bitRange>[0:0]</bitRange>
8240                <access>read-only</access>
8241              </field>
8242              <field>
8243                <name>HV_REGS_ISOLATED</name>
8244                <description>Indicates the isolation status at HV trim and redundancy registers inputs
82450: Not isolated, writing permitted
82461: isolated writing disabled</description>
8247                <bitRange>[1:1]</bitRange>
8248                <access>read-only</access>
8249              </field>
8250              <field>
8251                <name>ILLEGAL_HVOP</name>
8252                <description>Indicates a bulk, sector erase, program has been requested when axa=1
82530: no error
82541: illegal HV operation error</description>
8255                <bitRange>[2:2]</bitRange>
8256                <access>read-only</access>
8257              </field>
8258              <field>
8259                <name>TURBO_N</name>
8260                <description>After FM power up indicates the analog blocks currents are boosted to faster reach their functional state..
8261Used in the testchip boot only as an 'FM READY' flag.
82620: turbo mode
82631: normal mode</description>
8264                <bitRange>[3:3]</bitRange>
8265                <access>read-only</access>
8266              </field>
8267              <field>
8268                <name>WR_EN_MON</name>
8269                <description>FM_CTL.WR_EN bit after being synchronized in clk_r domain</description>
8270                <bitRange>[4:4]</bitRange>
8271                <access>read-only</access>
8272              </field>
8273              <field>
8274                <name>IF_SEL_MON</name>
8275                <description>FM_CTL.IF_SEL bit after being synchronized in clk_r domain</description>
8276                <bitRange>[5:5]</bitRange>
8277                <access>read-only</access>
8278              </field>
8279              <field>
8280                <name>TIMER_STATUS</name>
8281                <description>The actual timer state sync-ed in clk_c domain:
82820: timer is not running:
82831: timer is running;</description>
8284                <bitRange>[6:6]</bitRange>
8285                <access>read-only</access>
8286              </field>
8287              <field>
8288                <name>R_GRANT_DELAY_STATUS</name>
8289                <description>0: R_GRANT_DELAY timer is not running
82901: R_GRANT_DELAY timer is running</description>
8291                <bitRange>[7:7]</bitRange>
8292                <access>read-only</access>
8293              </field>
8294              <field>
8295                <name>FM_BUSY</name>
8296                <description>0': FM not busy
82971: FM BUSY : R_GRANT is 0 as result of a busy request from FM ready, or from HV operations.</description>
8298                <bitRange>[8:8]</bitRange>
8299                <access>read-only</access>
8300              </field>
8301              <field>
8302                <name>FM_READY</name>
8303                <description>0: FM not ready
83041: FM ready</description>
8305                <bitRange>[9:9]</bitRange>
8306                <access>read-only</access>
8307              </field>
8308              <field>
8309                <name>POS_PUMP_VLO</name>
8310                <description>POS pump VLO</description>
8311                <bitRange>[10:10]</bitRange>
8312                <access>read-only</access>
8313              </field>
8314              <field>
8315                <name>NEG_PUMP_VHI</name>
8316                <description>NEG pump VHI</description>
8317                <bitRange>[11:11]</bitRange>
8318                <access>read-only</access>
8319              </field>
8320              <field>
8321                <name>RWW</name>
8322                <description>FM Type  (Read While Write or Not Read While Write):
83230: Non RWW FM Type
83241:  RWW FM Type</description>
8325                <bitRange>[12:12]</bitRange>
8326                <access>read-only</access>
8327              </field>
8328              <field>
8329                <name>MAX_DOUT_WIDTH</name>
8330                <description>Internal memory core max data out size
8331(number of data out bits per column):
83320: x128 bits
83331: x256 bits</description>
8334                <bitRange>[13:13]</bitRange>
8335                <access>read-only</access>
8336              </field>
8337              <field>
8338                <name>SECTOR0_SR</name>
8339                <description>0:  Sector 0 does not contain special rows. The special rows are located in separate special sectors.
83401:  Sector 0 contains special rows</description>
8341                <bitRange>[14:14]</bitRange>
8342                <access>read-only</access>
8343              </field>
8344              <field>
8345                <name>RESET_MM</name>
8346                <description>Test_only, internal node: mpcon  reset_mm</description>
8347                <bitRange>[15:15]</bitRange>
8348                <access>read-only</access>
8349              </field>
8350              <field>
8351                <name>ROW_ODD</name>
8352                <description>Test_only, internal node: mpcon  row_odd</description>
8353                <bitRange>[16:16]</bitRange>
8354                <access>read-only</access>
8355              </field>
8356              <field>
8357                <name>ROW_EVEN</name>
8358                <description>Test_only, internal node: mpcon  row_even</description>
8359                <bitRange>[17:17]</bitRange>
8360                <access>read-only</access>
8361              </field>
8362              <field>
8363                <name>HVOP_SUB_SECTOR_N</name>
8364                <description>Test_only, internal node: mpcon  bk_subb</description>
8365                <bitRange>[18:18]</bitRange>
8366                <access>read-only</access>
8367              </field>
8368              <field>
8369                <name>HVOP_SECTOR</name>
8370                <description>Test_only, internal node: mpcon  bk_sec</description>
8371                <bitRange>[19:19]</bitRange>
8372                <access>read-only</access>
8373              </field>
8374              <field>
8375                <name>HVOP_BULK_ALL</name>
8376                <description>Test_only, internal node: mpcon  bk_all</description>
8377                <bitRange>[20:20]</bitRange>
8378                <access>read-only</access>
8379              </field>
8380              <field>
8381                <name>CBUS_RA_MATCH</name>
8382                <description>Test_only, internal node: mpcon  ra match</description>
8383                <bitRange>[21:21]</bitRange>
8384                <access>read-only</access>
8385              </field>
8386              <field>
8387                <name>CBUS_RED_ROW_EN</name>
8388                <description>Test_only, internal node: mpcon  red_row_en</description>
8389                <bitRange>[22:22]</bitRange>
8390                <access>read-only</access>
8391              </field>
8392              <field>
8393                <name>RQ_ERROR</name>
8394                <description>Test_only, internal node:  rq_error  sync-de in clk_c domain</description>
8395                <bitRange>[23:23]</bitRange>
8396                <access>read-only</access>
8397              </field>
8398              <field>
8399                <name>PUMP_PDAC</name>
8400                <description>Test_only, internal node: regif pdac outputs to pos pump</description>
8401                <bitRange>[27:24]</bitRange>
8402                <access>read-only</access>
8403              </field>
8404              <field>
8405                <name>PUMP_NDAC</name>
8406                <description>Test_only, internal node: regif ndac outputs to pos pump</description>
8407                <bitRange>[31:28]</bitRange>
8408                <access>read-only</access>
8409              </field>
8410            </fields>
8411          </register>
8412          <register>
8413            <name>FM_ADDR</name>
8414            <description>Flash macro address</description>
8415            <addressOffset>0x8</addressOffset>
8416            <size>32</size>
8417            <access>read-write</access>
8418            <resetValue>0x0</resetValue>
8419            <resetMask>0x1FFFFFF</resetMask>
8420            <fields>
8421              <field>
8422                <name>RA</name>
8423                <description>Row address.</description>
8424                <bitRange>[15:0]</bitRange>
8425                <access>read-write</access>
8426              </field>
8427              <field>
8428                <name>BA</name>
8429                <description>Bank address.</description>
8430                <bitRange>[23:16]</bitRange>
8431                <access>read-write</access>
8432              </field>
8433              <field>
8434                <name>AXA</name>
8435                <description>Auxiliary address field:
84360: regular flash memory.
84371: supervisory flash memory.</description>
8438                <bitRange>[24:24]</bitRange>
8439                <access>read-write</access>
8440              </field>
8441            </fields>
8442          </register>
8443          <register>
8444            <name>BOOKMARK</name>
8445            <description>Bookmark register - keeps the current FW HV seq</description>
8446            <addressOffset>0xC</addressOffset>
8447            <size>32</size>
8448            <access>read-write</access>
8449            <resetValue>0x0</resetValue>
8450            <resetMask>0xFFFFFFFF</resetMask>
8451            <fields>
8452              <field>
8453                <name>BOOKMARK</name>
8454                <description>Used by FW. Keeps the Current HV cycle sequence</description>
8455                <bitRange>[31:0]</bitRange>
8456                <access>read-write</access>
8457              </field>
8458            </fields>
8459          </register>
8460          <register>
8461            <name>GEOMETRY</name>
8462            <description>Regular flash geometry</description>
8463            <addressOffset>0x10</addressOffset>
8464            <size>32</size>
8465            <access>read-only</access>
8466            <resetValue>0x0</resetValue>
8467            <resetMask>0xFFFFFFFF</resetMask>
8468            <fields>
8469              <field>
8470                <name>ROW_COUNT</name>
8471                <description>Number of rows (minus 1):
84720: 1 row
84731: 2 rows
84742: 3 rows
8475...
8476'65535': 65536 rows</description>
8477                <bitRange>[15:0]</bitRange>
8478                <access>read-only</access>
8479              </field>
8480              <field>
8481                <name>BANK_COUNT</name>
8482                <description>Number of banks (minus 1):
84830: 1 bank
84841: 2 banks
8485...
8486'255': 256 banks</description>
8487                <bitRange>[23:16]</bitRange>
8488                <access>read-only</access>
8489              </field>
8490              <field>
8491                <name>WORD_SIZE_LOG2</name>
8492                <description>Number of Bytes per word (log 2). A word is defined as the data that is read from the flash macro over the R interface with a single read access:
84930: 1 Byte
84941: 2 Bytes
84952: 4 Bytes
8496...
84973: 128 Bytes
8498
8499The currently planned flash macros have a word size of either 32-bit, 64-bit or 128-bit, resulting in WORD_SIZE_LOG2 settings of 2, 3 and 4 respectively.</description>
8500                <bitRange>[27:24]</bitRange>
8501                <access>read-only</access>
8502              </field>
8503              <field>
8504                <name>PAGE_SIZE_LOG2</name>
8505                <description>Number of Bytes per page (log 2):
85060: 1 Byte
85071: 2 Bytes
85082: 4 Bytes
8509...
851015: 32768 Bytes
8511
8512The currently planned flash macros have a page size of either 256 Byte or 512 Byte, resulting in PAGE_SIZE_LOG2 settings of 8 and 9 respectively.</description>
8513                <bitRange>[31:28]</bitRange>
8514                <access>read-only</access>
8515              </field>
8516            </fields>
8517          </register>
8518          <register>
8519            <name>GEOMETRY_SUPERVISORY</name>
8520            <description>Supervisory flash geometry</description>
8521            <addressOffset>0x14</addressOffset>
8522            <size>32</size>
8523            <access>read-only</access>
8524            <resetValue>0x0</resetValue>
8525            <resetMask>0xFFFFFFFF</resetMask>
8526            <fields>
8527              <field>
8528                <name>ROW_COUNT</name>
8529                <description>Number of rows (minus 1). ROW_COUNT is typically less than GEOMETRY.ROW_COUNT</description>
8530                <bitRange>[15:0]</bitRange>
8531                <access>read-only</access>
8532              </field>
8533              <field>
8534                <name>BANK_COUNT</name>
8535                <description>Number of banks (minus 1). BANK_COUNT is less or equal to GEOMETRY.BANK_COUNT.</description>
8536                <bitRange>[23:16]</bitRange>
8537                <access>read-only</access>
8538              </field>
8539              <field>
8540                <name>WORD_SIZE_LOG2</name>
8541                <description>Number of Bytes per word (log 2). See GEOMETRY.WORD_SIZE_LOG2. Typically, WORD_SIZE_LOG2 equals GEOMETRY.WORD_SIZE_LOG2.</description>
8542                <bitRange>[27:24]</bitRange>
8543                <access>read-only</access>
8544              </field>
8545              <field>
8546                <name>PAGE_SIZE_LOG2</name>
8547                <description>Number of Bytes per page (log 2). See GEOMETRY.PAGE_SIZE_LOG2. Typically, PAGE_SIZE_LOG2 equals GEOMETRY.PAGE_SIZE_LOG2.</description>
8548                <bitRange>[31:28]</bitRange>
8549                <access>read-only</access>
8550              </field>
8551            </fields>
8552          </register>
8553          <register>
8554            <name>ANA_CTL0</name>
8555            <description>Analog control 0</description>
8556            <addressOffset>0x18</addressOffset>
8557            <size>32</size>
8558            <access>read-write</access>
8559            <resetValue>0x400</resetValue>
8560            <resetMask>0xFFFFFFFF</resetMask>
8561            <fields>
8562              <field>
8563                <name>MDAC</name>
8564                <description>Trimming of the output margin Voltage as a function of Vpos and Vneg.</description>
8565                <bitRange>[7:0]</bitRange>
8566                <access>read-write</access>
8567              </field>
8568              <field>
8569                <name>CSLDAC</name>
8570                <description>Trimming of common source line DAC.</description>
8571                <bitRange>[10:8]</bitRange>
8572                <access>read-write</access>
8573              </field>
8574              <field>
8575                <name>FLIP_AMUXBUS_AB</name>
8576                <description>Flips amuxbusa and amuxbusb
85770: amuxbusa, amuxbusb
85781:  amuxbusb, amuxbusb</description>
8579                <bitRange>[11:11]</bitRange>
8580                <access>read-write</access>
8581              </field>
8582              <field>
8583                <name>NDAC_MIN</name>
8584                <description>NDAC staircase min value</description>
8585                <bitRange>[15:12]</bitRange>
8586                <access>read-write</access>
8587              </field>
8588              <field>
8589                <name>PDAC_MIN</name>
8590                <description>PDAC staircase min value</description>
8591                <bitRange>[19:16]</bitRange>
8592                <access>read-write</access>
8593              </field>
8594              <field>
8595                <name>SCALE_PRG_SEQ01</name>
8596                <description>PROG&amp;PRE_PROG: Scale for R_GRANT_DELAY on seq0-seq1 transition:
859700: 0.125uS
859801: 1uS
859910: 10uS
860011: 100uS</description>
8601                <bitRange>[21:20]</bitRange>
8602                <access>read-write</access>
8603              </field>
8604              <field>
8605                <name>SCALE_PRG_SEQ12</name>
8606                <description>PROG&amp;PRE_PROG: Scale for R_GRANT_DELAY on seq1-seq2 transition:
860700: 0.125uS
860801: 1uS
860910: 10uS
861011: 100uS</description>
8611                <bitRange>[23:22]</bitRange>
8612                <access>read-write</access>
8613              </field>
8614              <field>
8615                <name>SCALE_PRG_SEQ23</name>
8616                <description>PROG&amp;PRE_PROG: Scale for R_GRANT_DELAY on seq2-seq3 transition:
861700: 0.125uS
861801: 1uS
861910: 10uS
862011: 100uS</description>
8621                <bitRange>[25:24]</bitRange>
8622                <access>read-write</access>
8623              </field>
8624              <field>
8625                <name>SCALE_SEQ30</name>
8626                <description>PROG&amp;PRE_PROG&amp; ERASE: Scale for R_GRANT_DELAY on seq3-seq0 transition:
862700: 0.125uS
862801: 1uS
862910: 10uS
863011: 100uS</description>
8631                <bitRange>[27:26]</bitRange>
8632                <access>read-write</access>
8633              </field>
8634              <field>
8635                <name>SCALE_PRG_PEON</name>
8636                <description>PROG&amp;PRE_PROG: Scale for R_GRANT_DELAY on PE On transition:
863700: 0.125uS
863801: 1uS
863910: 10uS
864011: 100uS</description>
8641                <bitRange>[29:28]</bitRange>
8642                <access>read-write</access>
8643              </field>
8644              <field>
8645                <name>SCALE_PRG_PEOFF</name>
8646                <description>PROG&amp;PRE_PROG: Scale for R_GRANT_DELAY on PE OFF transition:
864700: 0.125uS
864801: 1uS
864910: 10uS
865011: 100uS</description>
8651                <bitRange>[31:30]</bitRange>
8652                <access>read-write</access>
8653              </field>
8654            </fields>
8655          </register>
8656          <register>
8657            <name>ANA_CTL1</name>
8658            <description>Analog control 1</description>
8659            <addressOffset>0x1C</addressOffset>
8660            <size>32</size>
8661            <access>read-write</access>
8662            <resetValue>0xD32FAFA</resetValue>
8663            <resetMask>0xFFFFFFFF</resetMask>
8664            <fields>
8665              <field>
8666                <name>NDAC_MAX</name>
8667                <description>Ndac Max Value.Trimming of negative pump output Voltage.</description>
8668                <bitRange>[3:0]</bitRange>
8669                <access>read-write</access>
8670              </field>
8671              <field>
8672                <name>NDAC_STEP</name>
8673                <description>Ndac step increment</description>
8674                <bitRange>[7:4]</bitRange>
8675                <access>read-write</access>
8676              </field>
8677              <field>
8678                <name>PDAC_MAX</name>
8679                <description>Pdac Max Value.Trimming of positive pump output Voltage:</description>
8680                <bitRange>[11:8]</bitRange>
8681                <access>read-write</access>
8682              </field>
8683              <field>
8684                <name>PDAC_STEP</name>
8685                <description>Pdac step increment</description>
8686                <bitRange>[15:12]</bitRange>
8687                <access>read-write</access>
8688              </field>
8689              <field>
8690                <name>NPDAC_STEP_TIME</name>
8691                <description>Ndac/Pdac step duration: (1uS .. 255uS) * 8
8692When = 0 N/PDAC_MAX control the pumps</description>
8693                <bitRange>[23:16]</bitRange>
8694                <access>read-write</access>
8695              </field>
8696              <field>
8697                <name>NPDAC_ZERO_TIME</name>
8698                <description>Ndac/Pdac LO duration: (1uS .. 255uS) * 8
8699When 0, N/PDAC don't return to 0</description>
8700                <bitRange>[31:24]</bitRange>
8701                <access>read-write</access>
8702              </field>
8703            </fields>
8704          </register>
8705          <register>
8706            <name>WAIT_CTL</name>
8707            <description>Wait State control</description>
8708            <addressOffset>0x28</addressOffset>
8709            <size>32</size>
8710            <access>read-write</access>
8711            <resetValue>0x30B09</resetValue>
8712            <resetMask>0x3F070F0F</resetMask>
8713            <fields>
8714              <field>
8715                <name>WAIT_FM_MEM_RD</name>
8716                <description>Number of C interface wait cycles (on 'clk_c') for a read from the memory</description>
8717                <bitRange>[3:0]</bitRange>
8718                <access>read-write</access>
8719              </field>
8720              <field>
8721                <name>WAIT_FM_HV_RD</name>
8722                <description>Number of C interface wait cycles (on 'clk_c') for a read from the high Voltage page latches.
8723Common for reading HV Page Latches and the DATA_COMP_RESULT bit</description>
8724                <bitRange>[11:8]</bitRange>
8725                <access>read-write</access>
8726              </field>
8727              <field>
8728                <name>WAIT_FM_HV_WR</name>
8729                <description>Number of C interface wait cycles (on 'clk_c') for a write to the high Voltage page latches.</description>
8730                <bitRange>[18:16]</bitRange>
8731                <access>read-write</access>
8732              </field>
8733              <field>
8734                <name>FM_RWW_MODE</name>
8735                <description>00: Full CBUS MODE
873601: RWW
873710: RWW. R_GRANT is stalling r_bus for the whole program/erase duration</description>
8738                <bitRange>[25:24]</bitRange>
8739                <access>read-write</access>
8740              </field>
8741              <field>
8742                <name>LV_SPARE_1</name>
8743                <description>Spare register</description>
8744                <bitRange>[26:26]</bitRange>
8745                <access>read-write</access>
8746              </field>
8747              <field>
8748                <name>DRMM</name>
8749                <description>0: Normal
87501: Test mode to enable Margin mode for 2 rows at a time</description>
8751                <bitRange>[27:27]</bitRange>
8752                <access>read-write</access>
8753              </field>
8754              <field>
8755                <name>MBA</name>
8756                <description>0: Normal
87571: Test mode to enable Master Bulk Access which allows both normal rows and redundant rows to be erased / programmed in one HV cycle (Bulk / Sector Erase and Sector Program).</description>
8758                <bitRange>[28:28]</bitRange>
8759                <access>read-write</access>
8760              </field>
8761              <field>
8762                <name>PL_SOFT_SET_EN</name>
8763                <description>Page latch soft set enable, 0 = disabled, 1 = enabled (at end of seq_2), taken care in API</description>
8764                <bitRange>[29:29]</bitRange>
8765                <access>read-write</access>
8766              </field>
8767            </fields>
8768          </register>
8769          <register>
8770            <name>TIMER_CLK_CTL</name>
8771            <description>Timer prescaler (clk_t to timer clock frequency divider)</description>
8772            <addressOffset>0x34</addressOffset>
8773            <size>32</size>
8774            <access>read-write</access>
8775            <resetValue>0x8</resetValue>
8776            <resetMask>0xFFFFFFFF</resetMask>
8777            <fields>
8778              <field>
8779                <name>TIMER_CLOCK_FREQ</name>
8780                <description>Clk_t frequency divider to provide the 1MHz reference clock for the Regif Timer.
8781Equal to the frequency in MHz of the timer clock 'clk_t'.
8782Example: if 'clk_t' has a frequency of 4 MHz then this field value is '4'
8783Max clk_t frequency = 100MHz.
8784This field is updated at runtime with the  'SW_TIMER_CLOCK_FREQ ' value from the HV parameters table</description>
8785                <bitRange>[7:0]</bitRange>
8786                <access>read-write</access>
8787              </field>
8788              <field>
8789                <name>RGRANT_DELAY_PRG_PEON</name>
8790                <description>PROG&amp;PRE_PROG: R-grant blocking delay on PE ON. Scale = ANA_CTL0.SCALE_PEON
8791When = 0  R_GRANT_DELAY control is disabled
8792when IF_SEL=1  R_GRANT_DELAY control is disabled</description>
8793                <bitRange>[15:8]</bitRange>
8794                <access>read-write</access>
8795              </field>
8796              <field>
8797                <name>RGRANT_DELAY_PRG_PEOFF</name>
8798                <description>PROG&amp;PRE_PROG: R-grant blocking delay on PE OFF. Scale = ANA_CTL0.SCALE_PEOFF
8799When = 0  R_GRANT_DELAY control is disabled
8800when IF_SEL=1  R_GRANT_DELAY control is disabled</description>
8801                <bitRange>[23:16]</bitRange>
8802                <access>read-write</access>
8803              </field>
8804              <field>
8805                <name>RGRANT_DELAY_PRG_SEQ01</name>
8806                <description>PROG&amp;PRE_PROG: R-grant blocking delay on seq0-seq1 transition. Scale = ANA_CTL0.SCALE_SEQ01
8807When = 0  R_GRANT_DELAY control is disabled
8808when IF_SEL=1  R_GRANT_DELAY control is disabled</description>
8809                <bitRange>[31:24]</bitRange>
8810                <access>read-write</access>
8811              </field>
8812            </fields>
8813          </register>
8814          <register>
8815            <name>TIMER_CTL</name>
8816            <description>Timer control</description>
8817            <addressOffset>0x38</addressOffset>
8818            <size>32</size>
8819            <access>read-write</access>
8820            <resetValue>0x4000001</resetValue>
8821            <resetMask>0xE700FFFF</resetMask>
8822            <fields>
8823              <field>
8824                <name>PERIOD</name>
8825                <description>Timer period in either microseconds (SCALE is '0') or 100's of microseconds (SCALE is '1') multiples.</description>
8826                <bitRange>[14:0]</bitRange>
8827                <access>read-write</access>
8828              </field>
8829              <field>
8830                <name>SCALE</name>
8831                <description>Timer tick scale:
88320: 1 microsecond.
88331: 100 microseconds.</description>
8834                <bitRange>[15:15]</bitRange>
8835                <access>read-write</access>
8836              </field>
8837              <field>
8838                <name>AUTO_SEQUENCE</name>
8839                <description>1': Starts1 the HV automatic sequencing
8840Cleared by HW</description>
8841                <bitRange>[24:24]</bitRange>
8842                <access>read-write</access>
8843              </field>
8844              <field>
8845                <name>PRE_PROG</name>
8846                <description>1 during pre-program operation</description>
8847                <bitRange>[25:25]</bitRange>
8848                <access>read-write</access>
8849              </field>
8850              <field>
8851                <name>PRE_PROG_CSL</name>
8852                <description>0: CSL lines driven by CSL_DAC
88531: CSL lines driven by VNEG_G</description>
8854                <bitRange>[26:26]</bitRange>
8855                <access>read-write</access>
8856              </field>
8857              <field>
8858                <name>PUMP_EN</name>
8859                <description>Pump enable:
88600: disabled
88611: enabled (also requires FM_CTL.IF_SEL to be'1', this additional restriction is required to prevent non intentional clearing of the FM).
8862SW sets this field to '1' to generate a single PE pulse.
8863HW clears this field when timer is expired.</description>
8864                <bitRange>[29:29]</bitRange>
8865                <access>read-write</access>
8866              </field>
8867              <field>
8868                <name>ACLK_EN</name>
8869                <description>ACLK enable (generates a single cycle pulse for the FM):
88700: disabled
88711: enabled. SW set this field to '1' to generate a single cycle pulse. HW sets this field to '0' when the pulse is generated.</description>
8872                <bitRange>[30:30]</bitRange>
8873                <access>read-write</access>
8874              </field>
8875              <field>
8876                <name>TIMER_EN</name>
8877                <description>Timer enable:
88780: disabled
88791: enabled. SW sets this field to '1' to start the timer. HW sets this field to '0' when the timer is expired.</description>
8880                <bitRange>[31:31]</bitRange>
8881                <access>read-write</access>
8882              </field>
8883            </fields>
8884          </register>
8885          <register>
8886            <name>ACLK_CTL</name>
8887            <description>MPCON clock</description>
8888            <addressOffset>0x3C</addressOffset>
8889            <size>32</size>
8890            <access>write-only</access>
8891            <resetValue>0x0</resetValue>
8892            <resetMask>0x1</resetMask>
8893            <fields>
8894              <field>
8895                <name>ACLK_GEN</name>
8896                <description>A write to this register generates the clock pulse for HV control registers (mpcon outputs)</description>
8897                <bitRange>[0:0]</bitRange>
8898                <access>write-only</access>
8899              </field>
8900            </fields>
8901          </register>
8902          <register>
8903            <name>INTR</name>
8904            <description>Interrupt</description>
8905            <addressOffset>0x40</addressOffset>
8906            <size>32</size>
8907            <access>read-write</access>
8908            <resetValue>0x0</resetValue>
8909            <resetMask>0x1</resetMask>
8910            <fields>
8911              <field>
8912                <name>TIMER_EXPIRED</name>
8913                <description>Set to '1', when event is detected. Write INTR field with '1', to clear bit. Write INTR_SET field with '1', to set bit.</description>
8914                <bitRange>[0:0]</bitRange>
8915                <access>read-write</access>
8916              </field>
8917            </fields>
8918          </register>
8919          <register>
8920            <name>INTR_SET</name>
8921            <description>Interrupt set</description>
8922            <addressOffset>0x44</addressOffset>
8923            <size>32</size>
8924            <access>read-write</access>
8925            <resetValue>0x0</resetValue>
8926            <resetMask>0x1</resetMask>
8927            <fields>
8928              <field>
8929                <name>TIMER_EXPIRED</name>
8930                <description>Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect).</description>
8931                <bitRange>[0:0]</bitRange>
8932                <access>read-write</access>
8933              </field>
8934            </fields>
8935          </register>
8936          <register>
8937            <name>INTR_MASK</name>
8938            <description>Interrupt mask</description>
8939            <addressOffset>0x48</addressOffset>
8940            <size>32</size>
8941            <access>read-write</access>
8942            <resetValue>0x0</resetValue>
8943            <resetMask>0x1</resetMask>
8944            <fields>
8945              <field>
8946                <name>TIMER_EXPIRED</name>
8947                <description>Mask for corresponding field in INTR register.</description>
8948                <bitRange>[0:0]</bitRange>
8949                <access>read-write</access>
8950              </field>
8951            </fields>
8952          </register>
8953          <register>
8954            <name>INTR_MASKED</name>
8955            <description>Interrupt masked</description>
8956            <addressOffset>0x4C</addressOffset>
8957            <size>32</size>
8958            <access>read-only</access>
8959            <resetValue>0x0</resetValue>
8960            <resetMask>0x1</resetMask>
8961            <fields>
8962              <field>
8963                <name>TIMER_EXPIRED</name>
8964                <description>Logical and of corresponding request and mask fields.</description>
8965                <bitRange>[0:0]</bitRange>
8966                <access>read-only</access>
8967              </field>
8968            </fields>
8969          </register>
8970          <register>
8971            <name>CAL_CTL0</name>
8972            <description>Cal control BG LO trim bits</description>
8973            <addressOffset>0x50</addressOffset>
8974            <size>32</size>
8975            <access>read-write</access>
8976            <resetValue>0x38F8F</resetValue>
8977            <resetMask>0xFFFFF</resetMask>
8978            <fields>
8979              <field>
8980                <name>VCT_TRIM_LO_HV</name>
8981                <description>LO Bandgap Voltage Temperature Compensation trim control.</description>
8982                <bitRange>[4:0]</bitRange>
8983                <access>read-write</access>
8984              </field>
8985              <field>
8986                <name>CDAC_LO_HV</name>
8987                <description>LO Temperature compensated trim DAC. To control Vcstat slope for Vpos.</description>
8988                <bitRange>[7:5]</bitRange>
8989                <access>read-write</access>
8990              </field>
8991              <field>
8992                <name>VBG_TRIM_LO_HV</name>
8993                <description>LO Bandgap Voltage trim control.</description>
8994                <bitRange>[12:8]</bitRange>
8995                <access>read-write</access>
8996              </field>
8997              <field>
8998                <name>VBG_TC_TRIM_LO_HV</name>
8999                <description>LO Bandgap Voltage Temperature Compensation trim control</description>
9000                <bitRange>[15:13]</bitRange>
9001                <access>read-write</access>
9002              </field>
9003              <field>
9004                <name>ICREF_TC_TRIM_LO_HV</name>
9005                <description>LO Bandgap Current Temperature Compensation trim control</description>
9006                <bitRange>[18:16]</bitRange>
9007                <access>read-write</access>
9008              </field>
9009              <field>
9010                <name>IPREF_TRIMA_LO_HV</name>
9011                <description>Adds 100-150nA boost on IPREF_LO</description>
9012                <bitRange>[19:19]</bitRange>
9013                <access>read-write</access>
9014              </field>
9015            </fields>
9016          </register>
9017          <register>
9018            <name>CAL_CTL1</name>
9019            <description>Cal control BG HI trim bits</description>
9020            <addressOffset>0x54</addressOffset>
9021            <size>32</size>
9022            <access>read-write</access>
9023            <resetValue>0x38F8F</resetValue>
9024            <resetMask>0xFFFFF</resetMask>
9025            <fields>
9026              <field>
9027                <name>VCT_TRIM_HI_HV</name>
9028                <description>HI Bandgap Voltage Temperature Compensation trim control.</description>
9029                <bitRange>[4:0]</bitRange>
9030                <access>read-write</access>
9031              </field>
9032              <field>
9033                <name>CDAC_HI_HV</name>
9034                <description>HI Temperature compensated trim DAC. To control Vcstat slope for Vpos.</description>
9035                <bitRange>[7:5]</bitRange>
9036                <access>read-write</access>
9037              </field>
9038              <field>
9039                <name>VBG_TRIM_HI_HV</name>
9040                <description>HI Bandgap Voltage trim control.</description>
9041                <bitRange>[12:8]</bitRange>
9042                <access>read-write</access>
9043              </field>
9044              <field>
9045                <name>VBG_TC_TRIM_HI_HV</name>
9046                <description>HI Bandgap Voltage Temperature Compensation trim control.</description>
9047                <bitRange>[15:13]</bitRange>
9048                <access>read-write</access>
9049              </field>
9050              <field>
9051                <name>ICREF_TC_TRIM_HI_HV</name>
9052                <description>HI Bandgap Current Temperature Compensation trim control.</description>
9053                <bitRange>[18:16]</bitRange>
9054                <access>read-write</access>
9055              </field>
9056              <field>
9057                <name>IPREF_TRIMA_HI_HV</name>
9058                <description>Adds 100-150nA boost on IPREF_HI</description>
9059                <bitRange>[19:19]</bitRange>
9060                <access>read-write</access>
9061              </field>
9062            </fields>
9063          </register>
9064          <register>
9065            <name>CAL_CTL2</name>
9066            <description>Cal control BG LO&amp;HI trim bits</description>
9067            <addressOffset>0x58</addressOffset>
9068            <size>32</size>
9069            <access>read-write</access>
9070            <resetValue>0x7BE10</resetValue>
9071            <resetMask>0xFFFFF</resetMask>
9072            <fields>
9073              <field>
9074                <name>ICREF_TRIM_LO_HV</name>
9075                <description>LO Bandgap Current  trim control.</description>
9076                <bitRange>[4:0]</bitRange>
9077                <access>read-write</access>
9078              </field>
9079              <field>
9080                <name>ICREF_TRIM_HI_HV</name>
9081                <description>HI Bandgap Current  trim control.</description>
9082                <bitRange>[9:5]</bitRange>
9083                <access>read-write</access>
9084              </field>
9085              <field>
9086                <name>IPREF_TRIM_LO_HV</name>
9087                <description>LO Bandgap IPTAT trim control.</description>
9088                <bitRange>[14:10]</bitRange>
9089                <access>read-write</access>
9090              </field>
9091              <field>
9092                <name>IPREF_TRIM_HI_HV</name>
9093                <description>HI  Bandgap IPTAT trim control.</description>
9094                <bitRange>[19:15]</bitRange>
9095                <access>read-write</access>
9096              </field>
9097            </fields>
9098          </register>
9099          <register>
9100            <name>CAL_CTL3</name>
9101            <description>Cal control osc trim bits, idac, sdac, itim</description>
9102            <addressOffset>0x5C</addressOffset>
9103            <size>32</size>
9104            <access>read-write</access>
9105            <resetValue>0x2004</resetValue>
9106            <resetMask>0xFFFFF</resetMask>
9107            <fields>
9108              <field>
9109                <name>OSC_TRIM_HV</name>
9110                <description>Flash macro pump clock trim control.</description>
9111                <bitRange>[3:0]</bitRange>
9112                <access>read-write</access>
9113              </field>
9114              <field>
9115                <name>OSC_RANGE_TRIM_HV</name>
9116                <description>0: Oscillator High Frequency Range
91171: Oscillator Low Frequency range</description>
9118                <bitRange>[4:4]</bitRange>
9119                <access>read-write</access>
9120              </field>
9121              <field>
9122                <name>VPROT_ACT_HV</name>
9123                <description>Forces VPROT in active mode all the time</description>
9124                <bitRange>[5:5]</bitRange>
9125                <access>read-write</access>
9126              </field>
9127              <field>
9128                <name>IPREF_TC_HV</name>
9129                <description>0: Increases the IPREF Tempco by subtracting ICREF from IPREF - IPREF internal will be 0.5uA
91301: Reduces the IPREF Tempco without subtracting ICREF from IPREF - IPREF internal will be 1uA</description>
9131                <bitRange>[6:6]</bitRange>
9132                <access>read-write</access>
9133              </field>
9134              <field>
9135                <name>VREF_SEL_HV</name>
9136                <description>Voltage reference:
91370: internal bandgap reference
91381: external voltage reference</description>
9139                <bitRange>[7:7]</bitRange>
9140                <access>read-write</access>
9141              </field>
9142              <field>
9143                <name>IREF_SEL_HV</name>
9144                <description>Current reference:
91450: internal current reference
91461: external current reference</description>
9147                <bitRange>[8:8]</bitRange>
9148                <access>read-write</access>
9149              </field>
9150              <field>
9151                <name>REG_ACT_HV</name>
9152                <description>0: VBST regulator will operate in active/standby mode based on control signal.
91531: Forces the VBST regulator in active mode all the time</description>
9154                <bitRange>[9:9]</bitRange>
9155                <access>read-write</access>
9156              </field>
9157              <field>
9158                <name>FDIV_TRIM_HV</name>
9159                <description>FDIV_TRIM_HV[1:0]: Assuming oscillator frequency of 8MHz in standby.
9160Following are the clock frequencies seen by doubler
916100: F = 1MHz
916201: F = 0.5MHz
916310: F = 2MHz
916411: F = 4MHz</description>
9165                <bitRange>[11:10]</bitRange>
9166                <access>read-write</access>
9167              </field>
9168              <field>
9169                <name>VDDHI_HV</name>
9170                <description>0: vdd &lt; 2.3V
91711: vdd &gt;= 2.3V
9172'0' setting can used for vdd &gt; 2.3V also, but with a current penalty.</description>
9173                <bitRange>[12:12]</bitRange>
9174                <access>read-write</access>
9175              </field>
9176              <field>
9177                <name>TURBO_PULSEW_HV</name>
9178                <description>Turbo pulse width trim (Typical)
917900: 40 us
918001: 20 us
918110: 15 us
918211: 8 us</description>
9183                <bitRange>[14:13]</bitRange>
9184                <access>read-write</access>
9185              </field>
9186              <field>
9187                <name>BGLO_EN_HV</name>
9188                <description>0: Normal (Automatic change over from HI to LO)
91891: Force enable LO Bandgap</description>
9190                <bitRange>[15:15]</bitRange>
9191                <access>read-write</access>
9192              </field>
9193              <field>
9194                <name>BGHI_EN_HV</name>
9195                <description>0: Normal (Automatic change over from HI to LO)
91961: Force enable HI Bandgap
9197When both BGLO_EN_HV and BGHI_EN_HV are HIGH, only BGHI output is used and turbo_hv_n pulse is active</description>
9198                <bitRange>[16:16]</bitRange>
9199                <access>read-write</access>
9200              </field>
9201              <field>
9202                <name>CL_ISO_DIS_HV</name>
9203                <description>0: The internal logic controls the CL isolation
92041: Forces CL bypass</description>
9205                <bitRange>[17:17]</bitRange>
9206                <access>read-write</access>
9207              </field>
9208              <field>
9209                <name>R_GRANT_EN_HV</name>
9210                <description>0: r_grant handshake disabled, r_grant always 1.
92111: r_grand handshake  enabled</description>
9212                <bitRange>[18:18]</bitRange>
9213                <access>read-write</access>
9214              </field>
9215              <field>
9216                <name>LP_ULP_SW_HV</name>
9217                <description>LP&lt;--&gt;ULP switch for trim signals:
92180: LP
92191: ULP</description>
9220                <bitRange>[19:19]</bitRange>
9221                <access>read-write</access>
9222              </field>
9223            </fields>
9224          </register>
9225          <register>
9226            <name>CAL_CTL4</name>
9227            <description>Cal Control Vlim, SA, fdiv, reg_act</description>
9228            <addressOffset>0x60</addressOffset>
9229            <size>32</size>
9230            <access>read-write</access>
9231            <resetValue>0x12AE0</resetValue>
9232            <resetMask>0xFFFFF</resetMask>
9233            <fields>
9234              <field>
9235                <name>VLIM_TRIM_ULP_HV</name>
9236                <description>VLIM_TRIM[1:0]:
923700: V2 = 650mV
923801: V2 = 600mV
923910: V2 = 750mV
924011: V2 = 700mV</description>
9241                <bitRange>[1:0]</bitRange>
9242                <access>read-write</access>
9243              </field>
9244              <field>
9245                <name>IDAC_ULP_HV</name>
9246                <description>Sets the sense current reference offset value. Refer to trim tables for details.</description>
9247                <bitRange>[5:2]</bitRange>
9248                <access>read-write</access>
9249              </field>
9250              <field>
9251                <name>SDAC_ULP_HV</name>
9252                <description>Sets the sense current reference temp slope. Refer to trim tables for details.</description>
9253                <bitRange>[7:6]</bitRange>
9254                <access>read-write</access>
9255              </field>
9256              <field>
9257                <name>ITIM_ULP_HV</name>
9258                <description>Trimming of timing current</description>
9259                <bitRange>[12:8]</bitRange>
9260                <access>read-write</access>
9261              </field>
9262              <field>
9263                <name>FM_READY_DEL_ULP_HV</name>
9264                <description>00: Default : delay 1ns
926501: Delayed by 1.5us
926610: Delayed by 2.0us
926711: Delayed by 2.5us</description>
9268                <bitRange>[14:13]</bitRange>
9269                <access>read-write</access>
9270              </field>
9271              <field>
9272                <name>SPARE451_ULP_HV</name>
9273                <description>N/A</description>
9274                <bitRange>[15:15]</bitRange>
9275                <access>read-write</access>
9276              </field>
9277              <field>
9278                <name>READY_RESTART_N_HV</name>
9279                <description>Toggle: 1--&gt;0, ready goes low, ready will remain low as long as the bit is low. Toggle the bit back to 1 to activate the ready logic. To be used by API only.</description>
9280                <bitRange>[16:16]</bitRange>
9281                <access>read-write</access>
9282              </field>
9283              <field>
9284                <name>VBST_S_DIS_HV</name>
9285                <description>0: VBST_S voltage for each sector to allow VBST level to be dropped to VCC during Erase in the selected sector, reducing coupling to GBL.
92861: VBST_S voltage for each sector stays at VBST level during Erase in the selected sector.</description>
9287                <bitRange>[17:17]</bitRange>
9288                <access>read-write</access>
9289              </field>
9290              <field>
9291                <name>AUTO_HVPULSE_HV</name>
9292                <description>0: HV Pulse controlled by FW
92931: HV Pulse controlled by Hardware</description>
9294                <bitRange>[18:18]</bitRange>
9295                <access>read-write</access>
9296              </field>
9297              <field>
9298                <name>UGB_EN_HV</name>
9299                <description>UGB enable in TM control</description>
9300                <bitRange>[19:19]</bitRange>
9301                <access>read-write</access>
9302              </field>
9303            </fields>
9304          </register>
9305          <register>
9306            <name>CAL_CTL5</name>
9307            <description>Cal control</description>
9308            <addressOffset>0x64</addressOffset>
9309            <size>32</size>
9310            <access>read-write</access>
9311            <resetValue>0x2AE0</resetValue>
9312            <resetMask>0xFFFFF</resetMask>
9313            <fields>
9314              <field>
9315                <name>VLIM_TRIM_LP_HV</name>
9316                <description>VLIM_TRIM[1:0]:
931700: V2 = 650mV
931801: V2 = 600mV
931910: V2 = 750mV
932011: V2 = 700mV</description>
9321                <bitRange>[1:0]</bitRange>
9322                <access>read-write</access>
9323              </field>
9324              <field>
9325                <name>IDAC_LP_HV</name>
9326                <description>Sets the sense current reference offset value. Refer to trim tables for details.</description>
9327                <bitRange>[5:2]</bitRange>
9328                <access>read-write</access>
9329              </field>
9330              <field>
9331                <name>SDAC_LP_HV</name>
9332                <description>Sets the sense current reference temp slope. Refer to trim tables for details.</description>
9333                <bitRange>[7:6]</bitRange>
9334                <access>read-write</access>
9335              </field>
9336              <field>
9337                <name>ITIM_LP_HV</name>
9338                <description>Trimming of timing current</description>
9339                <bitRange>[12:8]</bitRange>
9340                <access>read-write</access>
9341              </field>
9342              <field>
9343                <name>FM_READY_DEL_LP_HV</name>
9344                <description>00: Delayed by 1us
934501: Delayed by 1.5us
934610: Delayed by 2.0us
934711: Delayed by 2.5us</description>
9348                <bitRange>[14:13]</bitRange>
9349                <access>read-write</access>
9350              </field>
9351              <field>
9352                <name>SPARE451_LP_HV</name>
9353                <description>N/A</description>
9354                <bitRange>[15:15]</bitRange>
9355                <access>read-write</access>
9356              </field>
9357              <field>
9358                <name>SPARE52_HV</name>
9359                <description>N/A</description>
9360                <bitRange>[17:16]</bitRange>
9361                <access>read-write</access>
9362              </field>
9363              <field>
9364                <name>AMUX_SEL_HV</name>
9365                <description>Amux Select in AMUX_UGB
936600: Bypass UGB for both amuxbusa and amuxbusb
936701: Bypass UGB for amuxbusb while passing amuxbusa through UGB.
936810: Bypass UGB for amuxbusa while passing amuxbusb through UGB.
936911: UGB Calibrate mode</description>
9370                <bitRange>[19:18]</bitRange>
9371                <access>read-write</access>
9372              </field>
9373            </fields>
9374          </register>
9375          <register>
9376            <name>CAL_CTL6</name>
9377            <description>SA trim LP/ULP</description>
9378            <addressOffset>0x68</addressOffset>
9379            <size>32</size>
9380            <access>read-write</access>
9381            <resetValue>0x36F7F</resetValue>
9382            <resetMask>0xFFFFF</resetMask>
9383            <fields>
9384              <field>
9385                <name>SA_CTL_TRIM_T1_ULP_HV</name>
9386                <description>clk_trk delay</description>
9387                <bitRange>[0:0]</bitRange>
9388                <access>read-write</access>
9389              </field>
9390              <field>
9391                <name>SA_CTL_TRIM_T4_ULP_HV</name>
9392                <description>SA_CTL_TRIM_T4_ULP_HV&lt;2&gt;= eqi (eq current trim)
9393SA_CTL_TRIM_T4_ULP_HV&lt;1:0&gt; = eqc (eq cap trim)</description>
9394                <bitRange>[3:1]</bitRange>
9395                <access>read-write</access>
9396              </field>
9397              <field>
9398                <name>SA_CTL_TRIM_T5_ULP_HV</name>
9399                <description>SA_CTL_TRIM_T5_ULP_HV&lt;2&gt;= evi (integration current trim)
9400SA_CTL_TRIM_T5_ULP_HV&lt;1:0&gt; = evc (integration cap trim)</description>
9401                <bitRange>[6:4]</bitRange>
9402                <access>read-write</access>
9403              </field>
9404              <field>
9405                <name>SA_CTL_TRIM_T6_ULP_HV</name>
9406                <description>SA_CTL_TRIM_T6_ULP_HV&lt;1&gt;= eni (enable current trim)
9407SA_CTL_TRIM_T6_ULP_HV&lt;0&gt; = ecn (enable cap trim)</description>
9408                <bitRange>[8:7]</bitRange>
9409                <access>read-write</access>
9410              </field>
9411              <field>
9412                <name>SA_CTL_TRIM_T8_ULP_HV</name>
9413                <description>saen3 pulse width trim (Current trim)</description>
9414                <bitRange>[9:9]</bitRange>
9415                <access>read-write</access>
9416              </field>
9417              <field>
9418                <name>SA_CTL_TRIM_T1_LP_HV</name>
9419                <description>clk_trk delay</description>
9420                <bitRange>[10:10]</bitRange>
9421                <access>read-write</access>
9422              </field>
9423              <field>
9424                <name>SA_CTL_TRIM_T4_LP_HV</name>
9425                <description>SA_CTL_TRIM_T4_LP_HV&lt;2&gt;= eqi (eq current trim)
9426SA_CTL_TRIM_T4_LP_HV&lt;1:0&gt; = eqc (eq cap trim)</description>
9427                <bitRange>[13:11]</bitRange>
9428                <access>read-write</access>
9429              </field>
9430              <field>
9431                <name>SA_CTL_TRIM_T5_LP_HV</name>
9432                <description>SA_CTL_TRIM_T5_LP_HV&lt;2&gt;= evi (integration current trim)
9433SA_CTL_TRIM_T5_LP_HV&lt;1:0&gt; = evc (integration cap trim)</description>
9434                <bitRange>[16:14]</bitRange>
9435                <access>read-write</access>
9436              </field>
9437              <field>
9438                <name>SA_CTL_TRIM_T6_LP_HV</name>
9439                <description>SA_CTL_TRIM_T6_LP_HV&lt;1&gt;= eni (enable current trim)
9440SA_CTL_TRIM_T6_LP_HV&lt;0&gt; = ecn (enable cap trim)</description>
9441                <bitRange>[18:17]</bitRange>
9442                <access>read-write</access>
9443              </field>
9444              <field>
9445                <name>SA_CTL_TRIM_T8_LP_HV</name>
9446                <description>saen3 pulse width trim (Current trim)</description>
9447                <bitRange>[19:19]</bitRange>
9448                <access>read-write</access>
9449              </field>
9450            </fields>
9451          </register>
9452          <register>
9453            <name>CAL_CTL7</name>
9454            <description>Cal control</description>
9455            <addressOffset>0x6C</addressOffset>
9456            <size>32</size>
9457            <access>read-write</access>
9458            <resetValue>0x0</resetValue>
9459            <resetMask>0xFFFFF</resetMask>
9460            <fields>
9461              <field>
9462                <name>ERSX8_CLK_SEL_HV</name>
9463                <description>Clock frequency into the ersx8 shift register block
946400: Oscillator clock
946501: Oscillator clock / 2
946610: Oscillator clock / 4
946711: Oscillator clock</description>
9468                <bitRange>[1:0]</bitRange>
9469                <access>read-write</access>
9470              </field>
9471              <field>
9472                <name>FM_ACTIVE_HV</name>
9473                <description>0: Normal operation
94741: Forces FM SYS in active mode</description>
9475                <bitRange>[2:2]</bitRange>
9476                <access>read-write</access>
9477              </field>
9478              <field>
9479                <name>TURBO_EXT_HV</name>
9480                <description>0: Normal operation
94811: Uses external turbo pulse</description>
9482                <bitRange>[3:3]</bitRange>
9483                <access>read-write</access>
9484              </field>
9485              <field>
9486                <name>NPDAC_HWCTL_DIS_HV</name>
9487                <description>0': ndac, pdac staircase hardware controlled
94881: ndac, pdac staircase disabled. Enables FW control.</description>
9489                <bitRange>[4:4]</bitRange>
9490                <access>read-write</access>
9491              </field>
9492              <field>
9493                <name>FM_READY_DIS_HV</name>
9494                <description>0': fm ready is enabled
94951: fm ready is disabled (fm_ready is always '1')</description>
9496                <bitRange>[5:5]</bitRange>
9497                <access>read-write</access>
9498              </field>
9499              <field>
9500                <name>ERSX8_EN_ALL_HV</name>
9501                <description>0': Staggered turn on/off of GWL
95021: GWL are turned on/off at the same time (old FM legacy)</description>
9503                <bitRange>[6:6]</bitRange>
9504                <access>read-write</access>
9505              </field>
9506              <field>
9507                <name>DISABLE_LOAD_ONCE_HV</name>
9508                <description>0: Load common HV params during API HV operations depends on the HV_PARAMS_LOADED bit in RGRANT_DELAY_PRG register.
95091: All HV params are loaded during every API HV operation irrespective of HV_PARAMS_LOADED bit in the RGRANT_DELAY_PRG register.</description>
9510                <bitRange>[7:7]</bitRange>
9511                <access>read-write</access>
9512              </field>
9513              <field>
9514                <name>SPARE7_HV</name>
9515                <description>N/A</description>
9516                <bitRange>[9:8]</bitRange>
9517                <access>read-write</access>
9518              </field>
9519              <field>
9520                <name>SPARE7_ULP_HV</name>
9521                <description>N/A</description>
9522                <bitRange>[14:10]</bitRange>
9523                <access>read-write</access>
9524              </field>
9525              <field>
9526                <name>SPARE7_LP_HV</name>
9527                <description>N/A</description>
9528                <bitRange>[19:15]</bitRange>
9529                <access>read-write</access>
9530              </field>
9531            </fields>
9532          </register>
9533          <register>
9534            <name>RED_CTL01</name>
9535            <description>Redundancy Control normal sectors 0,1</description>
9536            <addressOffset>0x80</addressOffset>
9537            <size>32</size>
9538            <access>read-write</access>
9539            <resetValue>0x0</resetValue>
9540            <resetMask>0x1FF01FF</resetMask>
9541            <fields>
9542              <field>
9543                <name>RED_ADDR_0</name>
9544                <description>Bad Row Pair Address for Sector 0</description>
9545                <bitRange>[7:0]</bitRange>
9546                <access>read-write</access>
9547              </field>
9548              <field>
9549                <name>RED_EN_0</name>
9550                <description>1: Redundancy Enable for Sector 0</description>
9551                <bitRange>[8:8]</bitRange>
9552                <access>read-write</access>
9553              </field>
9554              <field>
9555                <name>RED_ADDR_1</name>
9556                <description>Bad Row Pair Address for Sector 1</description>
9557                <bitRange>[23:16]</bitRange>
9558                <access>read-write</access>
9559              </field>
9560              <field>
9561                <name>RED_EN_1</name>
9562                <description>1: Redundancy Enable for Sector 1</description>
9563                <bitRange>[24:24]</bitRange>
9564                <access>read-write</access>
9565              </field>
9566            </fields>
9567          </register>
9568          <register>
9569            <name>RED_CTL23</name>
9570            <description>Redundancy Control normal sectors 2,3</description>
9571            <addressOffset>0x84</addressOffset>
9572            <size>32</size>
9573            <access>read-write</access>
9574            <resetValue>0x0</resetValue>
9575            <resetMask>0x1FF01FF</resetMask>
9576            <fields>
9577              <field>
9578                <name>RED_ADDR_2</name>
9579                <description>Bad Row Pair Address for Sector 2</description>
9580                <bitRange>[7:0]</bitRange>
9581                <access>read-write</access>
9582              </field>
9583              <field>
9584                <name>RED_EN_2</name>
9585                <description>1: Redundancy Enable for Sector 2</description>
9586                <bitRange>[8:8]</bitRange>
9587                <access>read-write</access>
9588              </field>
9589              <field>
9590                <name>RED_ADDR_3</name>
9591                <description>Bad Row Pair Address for Sector 3</description>
9592                <bitRange>[23:16]</bitRange>
9593                <access>read-write</access>
9594              </field>
9595              <field>
9596                <name>RED_EN_3</name>
9597                <description>1: Redundancy Enable for Sector 3</description>
9598                <bitRange>[24:24]</bitRange>
9599                <access>read-write</access>
9600              </field>
9601            </fields>
9602          </register>
9603          <register>
9604            <name>RED_CTL45</name>
9605            <description>Redundancy Control normal sectors 4,5</description>
9606            <addressOffset>0x88</addressOffset>
9607            <size>32</size>
9608            <access>read-write</access>
9609            <resetValue>0x0</resetValue>
9610            <resetMask>0x1FF01FF</resetMask>
9611            <fields>
9612              <field>
9613                <name>RED_ADDR_4</name>
9614                <description>Bad Row Pair Address for Sector 4</description>
9615                <bitRange>[7:0]</bitRange>
9616                <access>read-write</access>
9617              </field>
9618              <field>
9619                <name>RED_EN_4</name>
9620                <description>1: Redundancy Enable for Sector 4</description>
9621                <bitRange>[8:8]</bitRange>
9622                <access>read-write</access>
9623              </field>
9624              <field>
9625                <name>RED_ADDR_5</name>
9626                <description>Bad Row Pair Address for Sector 5</description>
9627                <bitRange>[23:16]</bitRange>
9628                <access>read-write</access>
9629              </field>
9630              <field>
9631                <name>RED_EN_5</name>
9632                <description>1: Redundancy Enable for Sector 5</description>
9633                <bitRange>[24:24]</bitRange>
9634                <access>read-write</access>
9635              </field>
9636            </fields>
9637          </register>
9638          <register>
9639            <name>RED_CTL67</name>
9640            <description>Redundancy Control normal sectors 6,7</description>
9641            <addressOffset>0x8C</addressOffset>
9642            <size>32</size>
9643            <access>read-write</access>
9644            <resetValue>0x0</resetValue>
9645            <resetMask>0x1FF01FF</resetMask>
9646            <fields>
9647              <field>
9648                <name>RED_ADDR_6</name>
9649                <description>Bad Row Pair Address for Sector 6</description>
9650                <bitRange>[7:0]</bitRange>
9651                <access>read-write</access>
9652              </field>
9653              <field>
9654                <name>RED_EN_6</name>
9655                <description>1: Redundancy Enable for Sector 6</description>
9656                <bitRange>[8:8]</bitRange>
9657                <access>read-write</access>
9658              </field>
9659              <field>
9660                <name>RED_ADDR_7</name>
9661                <description>Bad Row Pair Address for Sector 7</description>
9662                <bitRange>[23:16]</bitRange>
9663                <access>read-write</access>
9664              </field>
9665              <field>
9666                <name>RED_EN_7</name>
9667                <description>1: Redundancy Enable for Sector 7</description>
9668                <bitRange>[24:24]</bitRange>
9669                <access>read-write</access>
9670              </field>
9671            </fields>
9672          </register>
9673          <register>
9674            <name>RED_CTL_SM01</name>
9675            <description>Redundancy Control special sectors 0,1</description>
9676            <addressOffset>0x90</addressOffset>
9677            <size>32</size>
9678            <access>read-write</access>
9679            <resetValue>0x0</resetValue>
9680            <resetMask>0x1FF01FF</resetMask>
9681            <fields>
9682              <field>
9683                <name>RED_ADDR_SM0</name>
9684                <description>Bad Row Pair Address for Special Sector 0</description>
9685                <bitRange>[7:0]</bitRange>
9686                <access>read-write</access>
9687              </field>
9688              <field>
9689                <name>RED_EN_SM0</name>
9690                <description>Redundancy Enable for Special Sector 0</description>
9691                <bitRange>[8:8]</bitRange>
9692                <access>read-write</access>
9693              </field>
9694              <field>
9695                <name>RED_ADDR_SM1</name>
9696                <description>Bad Row Pair Address for Special Sector 1</description>
9697                <bitRange>[23:16]</bitRange>
9698                <access>read-write</access>
9699              </field>
9700              <field>
9701                <name>RED_EN_SM1</name>
9702                <description>Redundancy Enable for Special Sector 1</description>
9703                <bitRange>[24:24]</bitRange>
9704                <access>read-write</access>
9705              </field>
9706            </fields>
9707          </register>
9708          <register>
9709            <name>RGRANT_DELAY_PRG</name>
9710            <description>R-grant delay for program</description>
9711            <addressOffset>0x98</addressOffset>
9712            <size>32</size>
9713            <access>read-write</access>
9714            <resetValue>0x1000000</resetValue>
9715            <resetMask>0x8FFFFFFF</resetMask>
9716            <fields>
9717              <field>
9718                <name>RGRANT_DELAY_PRG_SEQ12</name>
9719                <description>PROG&amp;PRE_PROG: R-grant blocking delay on seq1-seq2 transition. Scale = ANA_CTL0.SCALE_SEQ12
9720When = 0  R_GRANT_DELAY control is disabled
9721when IF_SEL=1  R_GRANT_DELAY control is disabled</description>
9722                <bitRange>[7:0]</bitRange>
9723                <access>read-write</access>
9724              </field>
9725              <field>
9726                <name>RGRANT_DELAY_PRG_SEQ23</name>
9727                <description>PROG&amp;PRE_PROG: R-grant blocking delay on seq2-seq3 transition. Scale = ANA_CTL0.SCALE_SEQ23
9728When = 0  R_GRANT_DELAY control is disabled
9729when IF_SEL=1  R_GRANT_DELAY control is disabled</description>
9730                <bitRange>[15:8]</bitRange>
9731                <access>read-write</access>
9732              </field>
9733              <field>
9734                <name>RGRANT_DELAY_SEQ30</name>
9735                <description>PROG&amp;PRE_PROG &amp; ERASE: R-grant blocking delay on seq3-seq0 transition. Scale = ANA_CTL0.SCALE_SEQ30
9736When = 0  R_GRANT_DELAY control is disabled
9737when IF_SEL=1  R_GRANT_DELAY control is disabled</description>
9738                <bitRange>[23:16]</bitRange>
9739                <access>read-write</access>
9740              </field>
9741              <field>
9742                <name>RGRANT_DELAY_CLK</name>
9743                <description>Frequency divider from clk_t  to create the 8MHz reference clock for R_grant delay
9744The value of this field is the integer result of 'clk_t frequency / 8'.
9745Example: for clk_t=100 this field is INT(100/8) =12.
9746This field is updated at runtime with the  'SW_RGRANT_DELAY_CLK ' value from the HV parameters table</description>
9747                <bitRange>[27:24]</bitRange>
9748                <access>read-write</access>
9749              </field>
9750              <field>
9751                <name>HV_PARAMS_LOADED</name>
9752                <description>0: HV Pulse common params not loaded
97531: HV Pulse common params  loaded: r-grant delays, r-grant scale, prescaler, timer values for seq1,seq2_pre, seq2_post, seq3</description>
9754                <bitRange>[31:31]</bitRange>
9755                <access>read-write</access>
9756              </field>
9757            </fields>
9758          </register>
9759          <register>
9760            <name>PW_SEQ12</name>
9761            <description>HV Pulse Delay for seq 1&amp;2 pre</description>
9762            <addressOffset>0xA0</addressOffset>
9763            <size>32</size>
9764            <access>read-write</access>
9765            <resetValue>0x0</resetValue>
9766            <resetMask>0xFFFFFFFF</resetMask>
9767            <fields>
9768              <field>
9769                <name>PW_SEQ1</name>
9770                <description>Seq1 delay</description>
9771                <bitRange>[15:0]</bitRange>
9772                <access>read-write</access>
9773              </field>
9774              <field>
9775                <name>PW_SEQ2_PRE</name>
9776                <description>Seq2 pre delay</description>
9777                <bitRange>[31:16]</bitRange>
9778                <access>read-write</access>
9779              </field>
9780            </fields>
9781          </register>
9782          <register>
9783            <name>PW_SEQ23</name>
9784            <description>HV Pulse Delay for seq2 post &amp; seq3</description>
9785            <addressOffset>0xA4</addressOffset>
9786            <size>32</size>
9787            <access>read-write</access>
9788            <resetValue>0x0</resetValue>
9789            <resetMask>0xFFFFFFFF</resetMask>
9790            <fields>
9791              <field>
9792                <name>PW_SEQ2_POST</name>
9793                <description>Seq2 post  delay</description>
9794                <bitRange>[15:0]</bitRange>
9795                <access>read-write</access>
9796              </field>
9797              <field>
9798                <name>PW_SEQ3</name>
9799                <description>Seq3 delay</description>
9800                <bitRange>[31:16]</bitRange>
9801                <access>read-write</access>
9802              </field>
9803            </fields>
9804          </register>
9805          <register>
9806            <name>RGRANT_SCALE_ERS</name>
9807            <description>R-grant delay scale for erase</description>
9808            <addressOffset>0xA8</addressOffset>
9809            <size>32</size>
9810            <access>read-write</access>
9811            <resetValue>0x0</resetValue>
9812            <resetMask>0xFFFF03FF</resetMask>
9813            <fields>
9814              <field>
9815                <name>SCALE_ERS_SEQ01</name>
9816                <description>ERASE: Scale for R_GRANT_DELAY on seq0-seq1 transition:
981700: 0.125uS
981801: 1uS
981910: 10uS
982011: 100uS</description>
9821                <bitRange>[1:0]</bitRange>
9822                <access>read-write</access>
9823              </field>
9824              <field>
9825                <name>SCALE_ERS_SEQ12</name>
9826                <description>ERASE: Scale for R_GRANT_DELAY on seq1-seq2 transition:
982700: 0.125uS
982801: 1uS
982910: 10uS
983011: 100uS</description>
9831                <bitRange>[3:2]</bitRange>
9832                <access>read-write</access>
9833              </field>
9834              <field>
9835                <name>SCALE_ERS_SEQ23</name>
9836                <description>ERASE: Scale for R_GRANT_DELAY on seq2-seq3 transition:
983700: 0.125uS
983801: 1uS
983910: 10uS
984011: 100uS</description>
9841                <bitRange>[5:4]</bitRange>
9842                <access>read-write</access>
9843              </field>
9844              <field>
9845                <name>SCALE_ERS_PEON</name>
9846                <description>ERASE: Scale for R_GRANT_DELAY on PE On transition:
984700: 0.125uS
984801: 1uS
984910: 10uS
985011: 100uS</description>
9851                <bitRange>[7:6]</bitRange>
9852                <access>read-write</access>
9853              </field>
9854              <field>
9855                <name>SCALE_ERS_PEOFF</name>
9856                <description>ERASE: Scale for R_GRANT_DELAY on PE OFF transition:
985700: 0.125uS
985801: 1uS
985910: 10uS
986011: 100uS</description>
9861                <bitRange>[9:8]</bitRange>
9862                <access>read-write</access>
9863              </field>
9864              <field>
9865                <name>RGRANT_DELAY_ERS_PEON</name>
9866                <description>ERASE: R-grant blocking delay on PE ON. Scale = ANA_CTL0.SCALE_PEON
9867When = 0  R_GRANT_DELAY control is disabled
9868when IF_SEL=1  R_GRANT_DELAY control is disabled</description>
9869                <bitRange>[23:16]</bitRange>
9870                <access>read-write</access>
9871              </field>
9872              <field>
9873                <name>RGRANT_DELAY_ERS_PEOFF</name>
9874                <description>ERASE: R-grant blocking delay on PE OFF. Scale = ANA_CTL0.SCALE_PEOFF
9875When = 0  R_GRANT_DELAY control is disabled
9876when IF_SEL=1  R_GRANT_DELAY control is disabled</description>
9877                <bitRange>[31:24]</bitRange>
9878                <access>read-write</access>
9879              </field>
9880            </fields>
9881          </register>
9882          <register>
9883            <name>RGRANT_DELAY_ERS</name>
9884            <description>R-grant delay for erase</description>
9885            <addressOffset>0xAC</addressOffset>
9886            <size>32</size>
9887            <access>read-write</access>
9888            <resetValue>0x0</resetValue>
9889            <resetMask>0xFFFFFF</resetMask>
9890            <fields>
9891              <field>
9892                <name>RGRANT_DELAY_ERS_SEQ01</name>
9893                <description>ERASE: R-grant blocking delay on seq0-seq1 transition. Scale = ANA_CTL0.SCALE_SEQ01
9894When = 0  R_GRANT_DELAY control is disabled
9895when IF_SEL=1  R_GRANT_DELAY control is disabled</description>
9896                <bitRange>[7:0]</bitRange>
9897                <access>read-write</access>
9898              </field>
9899              <field>
9900                <name>RGRANT_DELAY_ERS_SEQ12</name>
9901                <description>ERASE: R-grant blocking delay on seq1-seq2 transition. Scale = ANA_CTL0.SCALE_SEQ12
9902When = 0  R_GRANT_DELAY control is disabled
9903when IF_SEL=1  R_GRANT_DELAY control is disabled</description>
9904                <bitRange>[15:8]</bitRange>
9905                <access>read-write</access>
9906              </field>
9907              <field>
9908                <name>RGRANT_DELAY_ERS_SEQ23</name>
9909                <description>ERASE: R-grant blocking delay on seq2-seq3 transition. Scale = ANA_CTL0.SCALE_SEQ23
9910When = 0  R_GRANT_DELAY control is disabled
9911when IF_SEL=1  R_GRANT_DELAY control is disabled</description>
9912                <bitRange>[23:16]</bitRange>
9913                <access>read-write</access>
9914              </field>
9915            </fields>
9916          </register>
9917          <register>
9918            <name>FM_PL_WRDATA_ALL</name>
9919            <description>Flash macro write page latches all</description>
9920            <addressOffset>0x7FC</addressOffset>
9921            <size>32</size>
9922            <access>read-write</access>
9923            <resetValue>0x0</resetValue>
9924            <resetMask>0xFFFFFFFF</resetMask>
9925            <fields>
9926              <field>
9927                <name>DATA32</name>
9928                <description>Write all high Voltage page latches with the same 32-bit data in a single write cycle
9929Read always returns 0.</description>
9930                <bitRange>[31:0]</bitRange>
9931                <access>read-write</access>
9932              </field>
9933            </fields>
9934          </register>
9935          <register>
9936            <dim>256</dim>
9937            <dimIncrement>4</dimIncrement>
9938            <name>FM_PL_DATA[%s]</name>
9939            <description>Flash macro Page Latches data</description>
9940            <addressOffset>0x800</addressOffset>
9941            <size>32</size>
9942            <access>read-write</access>
9943            <resetValue>0x0</resetValue>
9944            <resetMask>0xFFFFFFFF</resetMask>
9945            <fields>
9946              <field>
9947                <name>DATA32</name>
9948                <description>Four page latch Bytes
9949When reading the page latches it requires FM_CTL.IF_SEL to be '1'
9950Note: the high Voltage page latches are readable for test mode functionality.</description>
9951                <bitRange>[31:0]</bitRange>
9952                <access>read-write</access>
9953              </field>
9954            </fields>
9955          </register>
9956          <register>
9957            <dim>256</dim>
9958            <dimIncrement>4</dimIncrement>
9959            <name>FM_MEM_DATA[%s]</name>
9960            <description>Flash macro memory sense amplifier and column decoder data</description>
9961            <addressOffset>0xC00</addressOffset>
9962            <size>32</size>
9963            <access>read-only</access>
9964            <resetValue>0x0</resetValue>
9965            <resetMask>0xFFFFFFFF</resetMask>
9966            <fields>
9967              <field>
9968                <name>DATA32</name>
9969                <description>Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL:
9970- IF_SEL is 0: data as specified by the R interface address
9971- IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.</description>
9972                <bitRange>[31:0]</bitRange>
9973                <access>read-only</access>
9974              </field>
9975            </fields>
9976          </register>
9977        </cluster>
9978      </registers>
9979    </peripheral>
9980    <peripheral>
9981      <name>SRSS</name>
9982      <description>SRSS Core Registers</description>
9983      <baseAddress>0x40260000</baseAddress>
9984      <addressBlock>
9985        <offset>0</offset>
9986        <size>65536</size>
9987        <usage>registers</usage>
9988      </addressBlock>
9989      <registers>
9990        <register>
9991          <name>PWR_CTL</name>
9992          <description>Power Mode Control</description>
9993          <addressOffset>0x0</addressOffset>
9994          <size>32</size>
9995          <access>read-write</access>
9996          <resetValue>0x0</resetValue>
9997          <resetMask>0xFFFC0033</resetMask>
9998          <fields>
9999            <field>
10000              <name>POWER_MODE</name>
10001              <description>Current power mode of the device.  Note that this field cannot be read in all power modes on actual silicon.</description>
10002              <bitRange>[1:0]</bitRange>
10003              <access>read-only</access>
10004              <enumeratedValues>
10005                <enumeratedValue>
10006                  <name>RESET</name>
10007                  <description>System is resetting.</description>
10008                  <value>0</value>
10009                </enumeratedValue>
10010                <enumeratedValue>
10011                  <name>ACTIVE</name>
10012                  <description>At least one CPU is running.</description>
10013                  <value>1</value>
10014                </enumeratedValue>
10015                <enumeratedValue>
10016                  <name>SLEEP</name>
10017                  <description>No CPUs are running.  Peripherals may be running.</description>
10018                  <value>2</value>
10019                </enumeratedValue>
10020                <enumeratedValue>
10021                  <name>DEEPSLEEP</name>
10022                  <description>Main high-frequency clock is off; low speed clocks are available.  Communication interface clocks may be present.</description>
10023                  <value>3</value>
10024                </enumeratedValue>
10025              </enumeratedValues>
10026            </field>
10027            <field>
10028              <name>DEBUG_SESSION</name>
10029              <description>Indicates whether a debug session is active (CDBGPWRUPREQ signal is 1)</description>
10030              <bitRange>[4:4]</bitRange>
10031              <access>read-only</access>
10032              <enumeratedValues>
10033                <enumeratedValue>
10034                  <name>NO_SESSION</name>
10035                  <description>No debug session active</description>
10036                  <value>0</value>
10037                </enumeratedValue>
10038                <enumeratedValue>
10039                  <name>SESSION_ACTIVE</name>
10040                  <description>Debug session is active.  Power modes behave differently to keep the debug session active, and current consumption may be higher than datasheet specification.</description>
10041                  <value>1</value>
10042                </enumeratedValue>
10043              </enumeratedValues>
10044            </field>
10045            <field>
10046              <name>LPM_READY</name>
10047              <description>Indicates whether certain low power functions are ready.  The low current circuits take longer to startup after XRES/POR/BOD/HIBERNATE wakeup than the normal mode circuits.  HIBERNATE mode may be entered regardless of this bit.  This register is only reset by XRES/POR/BOD/HIBERNATE.
100480: If a low power circuit operation is requested, it will stay in its normal operating mode until it is ready.  If DEEPSLEEP is requested by all processors WFI/WFE, the device will instead enter SLEEP.  When low power circuits are ready, device will automatically enter the originally requested mode.
100491: Normal operation.  DEEPSLEEP and low power circuits operate as requested in other registers.</description>
10050              <bitRange>[5:5]</bitRange>
10051              <access>read-only</access>
10052            </field>
10053            <field>
10054              <name>IREF_LPMODE</name>
10055              <description>Control the power mode of the reference current generator.  The value in this register is ignored and normal mode is used until LPM_READY==1.  This register is only reset by XRES/POR/BOD/HIBERNATE.
100560: Current reference generator operates in normal mode.
100571: Current reference generator operates in low power mode.  Response time is reduced to save current.</description>
10058              <bitRange>[18:18]</bitRange>
10059              <access>read-write</access>
10060            </field>
10061            <field>
10062              <name>VREFBUF_OK</name>
10063              <description>Indicates that the voltage reference buffer is ready.  Due to synchronization delays, it may take two IMO clock cycles for hardware to clear this bit after asserting VREFBUF_DIS=1.</description>
10064              <bitRange>[19:19]</bitRange>
10065              <access>read-only</access>
10066            </field>
10067            <field>
10068              <name>DPSLP_REG_DIS</name>
10069              <description>Disable the DeepSleep regulator.  This is only legal when the on-chip buck regulator supplies vccd, but there is no hardware protection for this case.  This register is only reset by XRES/POR/BOD/HIBERNATE.
100700: DeepSleep Regulator is on.
100711: DeepSleep Regulator is off.</description>
10072              <bitRange>[20:20]</bitRange>
10073              <access>read-write</access>
10074            </field>
10075            <field>
10076              <name>RET_REG_DIS</name>
10077              <description>Disable the Retention regulator.  This is only legal when the on-chip buck regulator supplies vccd, but there is no hardware protection for this case.  This register is only reset by XRES/POR/BOD/HIBERNATE.
100780: Retention Regulator is on.
100791: Retention Regulator is off.</description>
10080              <bitRange>[21:21]</bitRange>
10081              <access>read-write</access>
10082            </field>
10083            <field>
10084              <name>NWELL_REG_DIS</name>
10085              <description>Disable the Nwell regulator.  This is only legal when the on-chip buck regulator supplies vccd, but there is no hardware protection for this case.  This register is only reset by XRES/POR/BOD/HIBERNATE.
100860: Nwell Regulator is on.
100871: Nwell Regulator is off.</description>
10088              <bitRange>[22:22]</bitRange>
10089              <access>read-write</access>
10090            </field>
10091            <field>
10092              <name>LINREG_DIS</name>
10093              <description>Disable the linear Core Regulator.  This is only legal when the on-chip buck regulator supplies vccd, but there is no hardware protection for this case.  This register is only reset by XRES/POR/BOD/HIBERNATE.
100940: Linear regulator is on.
100951: Linear regulator is off.</description>
10096              <bitRange>[23:23]</bitRange>
10097              <access>read-write</access>
10098            </field>
10099            <field>
10100              <name>LINREG_LPMODE</name>
10101              <description>Control the power mode of the Linear Regulator.  The value in this register is ignored and normal mode is used until LPM_READY==1.  This register is only reset by XRES/POR/BOD/HIBERNATE.
101020: Linear Regulator operates in normal mode.
101031: Linear Regulator operates in low power mode.  Load current capability is reduced, and firmware must ensure the current is kept within the limit for this operating mode.</description>
10104              <bitRange>[24:24]</bitRange>
10105              <access>read-write</access>
10106            </field>
10107            <field>
10108              <name>PORBOD_LPMODE</name>
10109              <description>Control the power mode of the POR/BOD circuits.  The value in this register is ignored and normal mode is used until LPM_READY==1.  This register is only reset by XRES/POR/BOD/HIBERNATE.
101100: POR/BOD circuits operate in normal mode.
101111: POR/BOD circuits operate in low power mode.  Response time is reduced to save current.</description>
10112              <bitRange>[25:25]</bitRange>
10113              <access>read-write</access>
10114            </field>
10115            <field>
10116              <name>BGREF_LPMODE</name>
10117              <description>Control the power mode of the Bandgap Voltage and Current References.  This applies to voltage and current generation and is different than the reference voltage buffer.  The value in this register is ignored and normal mode is used until LPM_READY==1.  When lower power mode is used, the Active Reference circuit can be disabled to reduce current.  Firmware is responsible to ensure ACT_REF_OK==1 before changing back to normal mode.  This register is only reset by XRES/POR/BOD/HIBERNATE.
101180: Active Bandgap Voltage and Current Reference operates in normal mode.
101191: Active Bandgap Voltage and Current Reference operates in low power mode.  Power supply rejection is reduced to save current.  The Active Reference may be disabled using ACT_REF_DIS=0.</description>
10120              <bitRange>[26:26]</bitRange>
10121              <access>read-write</access>
10122            </field>
10123            <field>
10124              <name>PLL_LS_BYPASS</name>
10125              <description>Bypass level shifter inside the PLL.
101260: Do not bypass the level shifter.  This setting is ok for all operational modes and vccd target voltage.
101271: Bypass the level shifter.  This may reduce jitter on the PLL output clock, but can only be used when vccd is targeted to 1.1V nominal.  Otherwise, it can result in clock degradation and static current.</description>
10128              <bitRange>[27:27]</bitRange>
10129              <access>read-write</access>
10130            </field>
10131            <field>
10132              <name>VREFBUF_LPMODE</name>
10133              <description>Control the power mode of the 800mV voltage reference buffer.  The value in this register is ignored and normal mode is used until LPM_READY==1.
101340: Voltage Reference Buffer operates in normal mode. This register is only reset by XRES/POR/BOD/HIBERNATE.
101351: Voltage Reference Buffer operates in low power mode.  Power supply rejection is reduced to save current.</description>
10136              <bitRange>[28:28]</bitRange>
10137              <access>read-write</access>
10138            </field>
10139            <field>
10140              <name>VREFBUF_DIS</name>
10141              <description>Disable the 800mV voltage reference buffer.  Firmware should only disable the buffer when there is no connected circuit that is using it.  SRSS circuits that require it are the PLL and ECO.  A particular product may have circuits outside the SRSS that use the buffer.  This register is only reset by XRES/POR/BOD/HIBERNATE.</description>
10142              <bitRange>[29:29]</bitRange>
10143              <access>read-write</access>
10144            </field>
10145            <field>
10146              <name>ACT_REF_DIS</name>
10147              <description>Disables the Active Reference.  Firmware must ensure that LPM_READY==1 and BGREF_LPMODE==1 for at least 1us before disabling the Active Reference.  When enabling the Active Reference, use ACT_REF_OK indicator to know when it is ready.  This register is only reset by XRES/POR/BOD/HIBERNATE.
101480: Active Reference is enabled
101491: Active Reference is disabled</description>
10150              <bitRange>[30:30]</bitRange>
10151              <access>read-write</access>
10152            </field>
10153            <field>
10154              <name>ACT_REF_OK</name>
10155              <description>Indicates that the normal mode of the Active Reference is ready.</description>
10156              <bitRange>[31:31]</bitRange>
10157              <access>read-only</access>
10158            </field>
10159          </fields>
10160        </register>
10161        <register>
10162          <name>PWR_HIBERNATE</name>
10163          <description>HIBERNATE Mode Register</description>
10164          <addressOffset>0x4</addressOffset>
10165          <size>32</size>
10166          <access>read-write</access>
10167          <resetValue>0x0</resetValue>
10168          <resetMask>0xCFFEFFFF</resetMask>
10169          <fields>
10170            <field>
10171              <name>TOKEN</name>
10172              <description>Contains a 8-bit token that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware to differentiate WAKEUP from a general RESET event.  Note that waking up from HIBERNATE using XRES will reset this register.</description>
10173              <bitRange>[7:0]</bitRange>
10174              <access>read-write</access>
10175            </field>
10176            <field>
10177              <name>UNLOCK</name>
10178              <description>This byte must be set to 0x3A for FREEZE or HIBERNATE fields to operate.  Any other value in this register will cause FREEZE/HIBERNATE to have no effect, except as noted in the FREEZE description.</description>
10179              <bitRange>[15:8]</bitRange>
10180              <access>read-write</access>
10181            </field>
10182            <field>
10183              <name>FREEZE</name>
10184              <description>Controls whether mode and state of GPIOs and SIOs in the system are frozen.  This is intended to be used as part of the HIBERNATE entry and exit sequences.  When entering HIBERNATE mode, the first write instructs DEEPSLEEP peripherals that they cannot ignore the upcoming freeze command.  This occurs even in the illegal condition where UNLOCK is not set.  If UNLOCK and HIBERNATE are properly set, the IOs actually freeze on the second write.</description>
10185              <bitRange>[17:17]</bitRange>
10186              <access>read-write</access>
10187            </field>
10188            <field>
10189              <name>MASK_HIBALARM</name>
10190              <description>When set, HIBERNATE will wakeup for a RTC interrupt</description>
10191              <bitRange>[18:18]</bitRange>
10192              <access>read-write</access>
10193            </field>
10194            <field>
10195              <name>MASK_HIBWDT</name>
10196              <description>When set, HIBERNATE will wakeup if WDT matches</description>
10197              <bitRange>[19:19]</bitRange>
10198              <access>read-write</access>
10199            </field>
10200            <field>
10201              <name>POLARITY_HIBPIN</name>
10202              <description>Each bit sets the active polarity of the corresponding wakeup pin.
102030: Pin input of 0 will wakeup the part from HIBERNATE
102041: Pin input of 1 will wakeup the part from HIBERNATE</description>
10205              <bitRange>[23:20]</bitRange>
10206              <access>read-write</access>
10207            </field>
10208            <field>
10209              <name>MASK_HIBPIN</name>
10210              <description>When set, HIBERNATE will wakeup if the corresponding pin input matches the POLARITY_HIBPIN setting.  Each bit corresponds to one of the HIBERNATE wakeup pins.</description>
10211              <bitRange>[27:24]</bitRange>
10212              <access>read-write</access>
10213            </field>
10214            <field>
10215              <name>HIBERNATE_DISABLE</name>
10216              <description>Hibernate disable bit.
102170: Normal operation, HIBERNATE works as described
102181: Further writes to this register are ignored
10219Note: This bit is a write-once bit until the next reset.  Avoid changing any other bits in this register while disabling HIBERNATE mode.  Also, it is recommended to clear the UNLOCK code, if it was previously written..</description>
10220              <bitRange>[30:30]</bitRange>
10221              <access>read-write</access>
10222            </field>
10223            <field>
10224              <name>HIBERNATE</name>
10225              <description>Firmware sets this bit to enter HIBERNATE mode.  The system will enter HIBERNATE mode immediately after writing to this bit and will wakeup only in response to XRES or WAKEUP event.  Both UNLOCK and FREEZE must have been set correctly in a previous write operations.  Otherwise, it will not enter HIBERNATE.  External supplies must have been stable for 250us before entering HIBERNATE mode.</description>
10226              <bitRange>[31:31]</bitRange>
10227              <access>read-write</access>
10228            </field>
10229          </fields>
10230        </register>
10231        <register>
10232          <name>PWR_LVD_CTL</name>
10233          <description>Low Voltage Detector (LVD) Configuration Register</description>
10234          <addressOffset>0x8</addressOffset>
10235          <size>32</size>
10236          <access>read-write</access>
10237          <resetValue>0x0</resetValue>
10238          <resetMask>0xFF</resetMask>
10239          <fields>
10240            <field>
10241              <name>HVLVD1_TRIPSEL</name>
10242              <description>Threshold selection for HVLVD1.  Disable the LVD (HVLVD1_EN=0) before changing the threshold.
102430: rise=1.225V (nom), fall=1.2V (nom)
102441: rise=1.425V (nom), fall=1.4V (nom)
102452: rise=1.625V (nom), fall=1.6V (nom)
102463: rise=1.825V (nom), fall=1.8V (nom)
102474: rise=2.025V (nom), fall=2V (nom)
102485: rise=2.125V (nom), fall=2.1V (nom)
102496: rise=2.225V (nom), fall=2.2V (nom)
102507: rise=2.325V (nom), fall=2.3V (nom)
102518: rise=2.425V (nom), fall=2.4V (nom)
102529: rise=2.525V (nom), fall=2.5V (nom)
1025310: rise=2.625V (nom), fall=2.6V (nom)
1025411: rise=2.725V (nom), fall=2.7V (nom)
1025512: rise=2.825V (nom), fall=2.8V (nom)
1025613: rise=2.925V (nom), fall=2.9V (nom)
1025714: rise=3.025V (nom), fall=3.0V (nom)
1025815: rise=3.125V (nom), fall=3.1V (nom)</description>
10259              <bitRange>[3:0]</bitRange>
10260              <access>read-write</access>
10261            </field>
10262            <field>
10263              <name>HVLVD1_SRCSEL</name>
10264              <description>Source selection for HVLVD1</description>
10265              <bitRange>[6:4]</bitRange>
10266              <access>read-write</access>
10267              <enumeratedValues>
10268                <enumeratedValue>
10269                  <name>VDDD</name>
10270                  <description>Select VDDD</description>
10271                  <value>0</value>
10272                </enumeratedValue>
10273                <enumeratedValue>
10274                  <name>AMUXBUSA</name>
10275                  <description>Select AMUXBUSA (VDDD branch)</description>
10276                  <value>1</value>
10277                </enumeratedValue>
10278                <enumeratedValue>
10279                  <name>RSVD</name>
10280                  <description>N/A</description>
10281                  <value>2</value>
10282                </enumeratedValue>
10283                <enumeratedValue>
10284                  <name>VDDIO</name>
10285                  <description>N/A</description>
10286                  <value>3</value>
10287                </enumeratedValue>
10288                <enumeratedValue>
10289                  <name>AMUXBUSB</name>
10290                  <description>Select AMUXBUSB (VDDD branch)</description>
10291                  <value>4</value>
10292                </enumeratedValue>
10293              </enumeratedValues>
10294            </field>
10295            <field>
10296              <name>HVLVD1_EN</name>
10297              <description>Enable HVLVD1 voltage monitor.  When the LVD is enabled, it takes 20us for it to settle.  There is no hardware stabilization counter, and it may falsely trigger during settling.  It is recommended that firmware keep the interrupt masked for at least 8us, write a 1'b1 to the corresponding SRSS_INTR field to any falsely pended interrupt, and then optionally unmask the interrupt.  After enabling, it is further recommended to read the related PWR_LVD_STATUS field, since the interrupt only triggers on edges.  This bit is cleared (LVD is disabled) when entering DEEPSLEEP to prevent false interrupts during wakeup.</description>
10298              <bitRange>[7:7]</bitRange>
10299              <access>read-write</access>
10300            </field>
10301          </fields>
10302        </register>
10303        <register>
10304          <name>PWR_BUCK_CTL</name>
10305          <description>Buck Control Register</description>
10306          <addressOffset>0x14</addressOffset>
10307          <size>32</size>
10308          <access>read-write</access>
10309          <resetValue>0x5</resetValue>
10310          <resetMask>0xC0000007</resetMask>
10311          <fields>
10312            <field>
10313              <name>BUCK_OUT1_SEL</name>
10314              <description>Voltage output selection for vccbuck1 output.  This register is only reset by XRES/POR/BOD/HIBERNATE.  When increasing the voltage, it can take up to 200us for the output voltage to settle.  When decreasing the voltage, the settling time depends on the load current.
103150: 0.85V
103161: 0.875V
103172: 0.90V
103183: 0.95V
103194: 1.05V
103205: 1.10V
103216: 1.15V
103227: 1.20V</description>
10323              <bitRange>[2:0]</bitRange>
10324              <access>read-write</access>
10325            </field>
10326            <field>
10327              <name>BUCK_EN</name>
10328              <description>Master enable for buck converter.    This register is only reset by XRES/POR/BOD/HIBERNATE.</description>
10329              <bitRange>[30:30]</bitRange>
10330              <access>read-write</access>
10331            </field>
10332            <field>
10333              <name>BUCK_OUT1_EN</name>
10334              <description>Enable for vccbuck1 output.  The value in this register is ignored unless PWR_BUCK_CTL.BUCK_EN==1.    This register is only reset by XRES/POR/BOD/HIBERNATE.  The regulator takes up to 600us to charge the external capacitor.  If there is additional load current while charging, this will increase the startup time.  The TRM specifies the required sequence when transitioning vccd from the LDO to SIMO Buck output #1.</description>
10335              <bitRange>[31:31]</bitRange>
10336              <access>read-write</access>
10337            </field>
10338          </fields>
10339        </register>
10340        <register>
10341          <name>PWR_BUCK_CTL2</name>
10342          <description>Buck Control Register 2</description>
10343          <addressOffset>0x18</addressOffset>
10344          <size>32</size>
10345          <access>read-write</access>
10346          <resetValue>0x0</resetValue>
10347          <resetMask>0xC0000007</resetMask>
10348          <fields>
10349            <field>
10350              <name>BUCK_OUT2_SEL</name>
10351              <description>Voltage output selection for vccbuck2 output.  When increasing the voltage, it can take up to 200us for the output voltage to settle.  When decreasing the voltage, the settling time depends on the load current.
103520: 1.15V
103531: 1.20V
103542: 1.25V
103553: 1.30V
103564: 1.35V
103575: 1.40V
103586: 1.45V
103597: 1.50V</description>
10360              <bitRange>[2:0]</bitRange>
10361              <access>read-write</access>
10362            </field>
10363            <field>
10364              <name>BUCK_OUT2_HW_SEL</name>
10365              <description>Hardware control for vccbuck2 output.  When this bit is set, the value in BUCK_OUT2_EN is ignored and a hardware signal is used instead.  If the product has supporting hardware, it can directly control the enable signal for vccbuck2.  The same charging time in BUCK_OUT2_EN applies.</description>
10366              <bitRange>[30:30]</bitRange>
10367              <access>read-write</access>
10368            </field>
10369            <field>
10370              <name>BUCK_OUT2_EN</name>
10371              <description>Enable for vccbuck2 output.  The value in this register is ignored unless PWR_BUCK_CTL.BUCK_EN==1.  The regulator takes up to 600us to charge the external capacitor.  If there is additional load current while charging, this will increase the startup time.</description>
10372              <bitRange>[31:31]</bitRange>
10373              <access>read-write</access>
10374            </field>
10375          </fields>
10376        </register>
10377        <register>
10378          <name>PWR_LVD_STATUS</name>
10379          <description>Low Voltage Detector (LVD) Status Register</description>
10380          <addressOffset>0x1C</addressOffset>
10381          <size>32</size>
10382          <access>read-only</access>
10383          <resetValue>0x0</resetValue>
10384          <resetMask>0x1</resetMask>
10385          <fields>
10386            <field>
10387              <name>HVLVD1_OK</name>
10388              <description>HVLVD1 output.
103890: below voltage threshold
103901: above voltage threshold</description>
10391              <bitRange>[0:0]</bitRange>
10392              <access>read-only</access>
10393            </field>
10394          </fields>
10395        </register>
10396        <register>
10397          <dim>16</dim>
10398          <dimIncrement>4</dimIncrement>
10399          <name>PWR_HIB_DATA[%s]</name>
10400          <description>HIBERNATE Data Register</description>
10401          <addressOffset>0x80</addressOffset>
10402          <size>32</size>
10403          <access>read-write</access>
10404          <resetValue>0x0</resetValue>
10405          <resetMask>0xFFFFFFFF</resetMask>
10406          <fields>
10407            <field>
10408              <name>HIB_DATA</name>
10409              <description>Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose.  Note that waking up from HIBERNATE using XRES will reset this register.</description>
10410              <bitRange>[31:0]</bitRange>
10411              <access>read-write</access>
10412            </field>
10413          </fields>
10414        </register>
10415        <register>
10416          <name>WDT_CTL</name>
10417          <description>Watchdog Counter Control Register</description>
10418          <addressOffset>0x180</addressOffset>
10419          <size>32</size>
10420          <access>read-write</access>
10421          <resetValue>0xC0000001</resetValue>
10422          <resetMask>0xC0000001</resetMask>
10423          <fields>
10424            <field>
10425              <name>WDT_EN</name>
10426              <description>Enable this watchdog timer.  This field is retained during DEEPSLEEP and HIBERNATE modes.</description>
10427              <bitRange>[0:0]</bitRange>
10428              <access>read-write</access>
10429            </field>
10430            <field>
10431              <name>WDT_LOCK</name>
10432              <description>Prohibits writing to WDT_*, CLK_ILO_CONFIG, CLK_SELECT.LFCLK_SEL, and CLK_TRIM_ILO_CTL registers when not equal 0.  Requires at least two different writes to unlock.  A change in WDT_LOCK takes effect beginning with the next write cycle.
10433Note that this field is 2 bits to force multiple writes only.  It represents only a single write protect signal protecting all those registers at the same time.  WDT will lock on any reset.  This field is not retained during DEEPSLEEP or HIBERNATE mode, so the WDT will be locked after wakeup from these modes.</description>
10434              <bitRange>[31:30]</bitRange>
10435              <access>read-write</access>
10436              <enumeratedValues>
10437                <enumeratedValue>
10438                  <name>NO_CHG</name>
10439                  <description>No effect</description>
10440                  <value>0</value>
10441                </enumeratedValue>
10442                <enumeratedValue>
10443                  <name>CLR0</name>
10444                  <description>Clears bit 0</description>
10445                  <value>1</value>
10446                </enumeratedValue>
10447                <enumeratedValue>
10448                  <name>CLR1</name>
10449                  <description>Clears bit 1</description>
10450                  <value>2</value>
10451                </enumeratedValue>
10452                <enumeratedValue>
10453                  <name>SET01</name>
10454                  <description>Sets both bits 0 and 1</description>
10455                  <value>3</value>
10456                </enumeratedValue>
10457              </enumeratedValues>
10458            </field>
10459          </fields>
10460        </register>
10461        <register>
10462          <name>WDT_CNT</name>
10463          <description>Watchdog Counter Count Register</description>
10464          <addressOffset>0x184</addressOffset>
10465          <size>32</size>
10466          <access>read-write</access>
10467          <resetValue>0x0</resetValue>
10468          <resetMask>0xFFFF</resetMask>
10469          <fields>
10470            <field>
10471              <name>COUNTER</name>
10472              <description>Current value of WDT Counter.  The write feature of this register is for engineering use (DfV), have no synchronization, and can only be applied when the WDT is fully off.  When writing, the value is updated immediately in the WDT counter, but it will read back as the old value until this register resynchronizes just after the negedge of ILO.  Writes will be ignored if they occur when the WDT is enabled.</description>
10473              <bitRange>[15:0]</bitRange>
10474              <access>read-write</access>
10475            </field>
10476          </fields>
10477        </register>
10478        <register>
10479          <name>WDT_MATCH</name>
10480          <description>Watchdog Counter Match Register</description>
10481          <addressOffset>0x188</addressOffset>
10482          <size>32</size>
10483          <access>read-write</access>
10484          <resetValue>0x1000</resetValue>
10485          <resetMask>0xFFFFF</resetMask>
10486          <fields>
10487            <field>
10488              <name>MATCH</name>
10489              <description>Match value for Watchdog counter.  Every time WDT_COUNTER reaches MATCH an interrupt is generated.  Two unserviced interrupts will lead to a system reset (i.e. at the third match).</description>
10490              <bitRange>[15:0]</bitRange>
10491              <access>read-write</access>
10492            </field>
10493            <field>
10494              <name>IGNORE_BITS</name>
10495              <description>The number of MSB bits of the watchdog timer that are NOT checked against MATCH.  This value provides control over the time-to-reset of the watchdog (which happens after 3 successive matches).  Up to 12 MSB can be ignored.  Settings &gt;12 behave like a setting of 12.</description>
10496              <bitRange>[19:16]</bitRange>
10497              <access>read-write</access>
10498            </field>
10499          </fields>
10500        </register>
10501        <cluster>
10502          <dim>2</dim>
10503          <dimIncrement>64</dimIncrement>
10504          <name>MCWDT_STRUCT[%s]</name>
10505          <description>Multi-Counter Watchdog Timer</description>
10506          <headerStructName>MCWDT_STRUCT</headerStructName>
10507          <addressOffset>0x00000200</addressOffset>
10508          <register>
10509            <name>MCWDT_CNTLOW</name>
10510            <description>Multi-Counter Watchdog Sub-counters 0/1</description>
10511            <addressOffset>0x4</addressOffset>
10512            <size>32</size>
10513            <access>read-write</access>
10514            <resetValue>0x0</resetValue>
10515            <resetMask>0xFFFFFFFF</resetMask>
10516            <fields>
10517              <field>
10518                <name>WDT_CTR0</name>
10519                <description>Current value of sub-counter 0 for this MCWDT.  Software writes are ignored when the sub-counter is enabled.</description>
10520                <bitRange>[15:0]</bitRange>
10521                <access>read-write</access>
10522              </field>
10523              <field>
10524                <name>WDT_CTR1</name>
10525                <description>Current value of sub-counter 1 for this MCWDT.  Software writes are ignored when the sub-counter is enabled</description>
10526                <bitRange>[31:16]</bitRange>
10527                <access>read-write</access>
10528              </field>
10529            </fields>
10530          </register>
10531          <register>
10532            <name>MCWDT_CNTHIGH</name>
10533            <description>Multi-Counter Watchdog Sub-counter 2</description>
10534            <addressOffset>0x8</addressOffset>
10535            <size>32</size>
10536            <access>read-write</access>
10537            <resetValue>0x0</resetValue>
10538            <resetMask>0xFFFFFFFF</resetMask>
10539            <fields>
10540              <field>
10541                <name>WDT_CTR2</name>
10542                <description>Current value of sub-counter 2 for this MCWDT.  Software writes are ignored when the sub-counter is enabled</description>
10543                <bitRange>[31:0]</bitRange>
10544                <access>read-write</access>
10545              </field>
10546            </fields>
10547          </register>
10548          <register>
10549            <name>MCWDT_MATCH</name>
10550            <description>Multi-Counter Watchdog Counter Match Register</description>
10551            <addressOffset>0xC</addressOffset>
10552            <size>32</size>
10553            <access>read-write</access>
10554            <resetValue>0x0</resetValue>
10555            <resetMask>0xFFFFFFFF</resetMask>
10556            <fields>
10557              <field>
10558                <name>WDT_MATCH0</name>
10559                <description>Match value for sub-counter 0 of this MCWDT</description>
10560                <bitRange>[15:0]</bitRange>
10561                <access>read-write</access>
10562              </field>
10563              <field>
10564                <name>WDT_MATCH1</name>
10565                <description>Match value for sub-counter 1 of this MCWDT</description>
10566                <bitRange>[31:16]</bitRange>
10567                <access>read-write</access>
10568              </field>
10569            </fields>
10570          </register>
10571          <register>
10572            <name>MCWDT_CONFIG</name>
10573            <description>Multi-Counter Watchdog Counter Configuration</description>
10574            <addressOffset>0x10</addressOffset>
10575            <size>32</size>
10576            <access>read-write</access>
10577            <resetValue>0x0</resetValue>
10578            <resetMask>0x1F010F0F</resetMask>
10579            <fields>
10580              <field>
10581                <name>WDT_MODE0</name>
10582                <description>Watchdog Counter Action on Match.  Action is taken on the next increment after the values match (WDT_CTR0=WDT_MATCH0).</description>
10583                <bitRange>[1:0]</bitRange>
10584                <access>read-write</access>
10585                <enumeratedValues>
10586                  <enumeratedValue>
10587                    <name>NOTHING</name>
10588                    <description>Do nothing</description>
10589                    <value>0</value>
10590                  </enumeratedValue>
10591                  <enumeratedValue>
10592                    <name>INT</name>
10593                    <description>Assert WDT_INTx</description>
10594                    <value>1</value>
10595                  </enumeratedValue>
10596                  <enumeratedValue>
10597                    <name>RESET</name>
10598                    <description>Assert WDT Reset</description>
10599                    <value>2</value>
10600                  </enumeratedValue>
10601                  <enumeratedValue>
10602                    <name>INT_THEN_RESET</name>
10603                    <description>Assert WDT_INTx, assert WDT Reset after 3rd unhandled interrupt</description>
10604                    <value>3</value>
10605                  </enumeratedValue>
10606                </enumeratedValues>
10607              </field>
10608              <field>
10609                <name>WDT_CLEAR0</name>
10610                <description>Clear Watchdog Counter when WDT_CTR0=WDT_MATCH0. In other words WDT_CTR0 divides LFCLK by (WDT_MATCH0+1).
106110: Free running counter
106121: Clear on match.  In this mode, the minimum legal setting of WDT_MATCH0 is 1.</description>
10613                <bitRange>[2:2]</bitRange>
10614                <access>read-write</access>
10615              </field>
10616              <field>
10617                <name>WDT_CASCADE0_1</name>
10618                <description>Cascade Watchdog Counters 0,1.  Counter 1 increments the cycle after WDT_CTR0=WDT_MATCH0.
106190: Independent counters
106201: Cascaded counters</description>
10621                <bitRange>[3:3]</bitRange>
10622                <access>read-write</access>
10623              </field>
10624              <field>
10625                <name>WDT_MODE1</name>
10626                <description>Watchdog Counter Action on Match.  Action is taken on the next increment after the values match (WDT_CTR1=WDT_MATCH1).</description>
10627                <bitRange>[9:8]</bitRange>
10628                <access>read-write</access>
10629                <enumeratedValues>
10630                  <enumeratedValue>
10631                    <name>NOTHING</name>
10632                    <description>Do nothing</description>
10633                    <value>0</value>
10634                  </enumeratedValue>
10635                  <enumeratedValue>
10636                    <name>INT</name>
10637                    <description>Assert WDT_INTx</description>
10638                    <value>1</value>
10639                  </enumeratedValue>
10640                  <enumeratedValue>
10641                    <name>RESET</name>
10642                    <description>Assert WDT Reset</description>
10643                    <value>2</value>
10644                  </enumeratedValue>
10645                  <enumeratedValue>
10646                    <name>INT_THEN_RESET</name>
10647                    <description>Assert WDT_INTx, assert WDT Reset after 3rd unhandled interrupt</description>
10648                    <value>3</value>
10649                  </enumeratedValue>
10650                </enumeratedValues>
10651              </field>
10652              <field>
10653                <name>WDT_CLEAR1</name>
10654                <description>Clear Watchdog Counter when WDT_CTR1==WDT_MATCH1. In other words WDT_CTR1 divides LFCLK by (WDT_MATCH1+1).
106550: Free running counter
106561: Clear on match.  In this mode, the minimum legal setting of WDT_MATCH1 is 1.</description>
10657                <bitRange>[10:10]</bitRange>
10658                <access>read-write</access>
10659              </field>
10660              <field>
10661                <name>WDT_CASCADE1_2</name>
10662                <description>Cascade Watchdog Counters 1,2.  Counter 2 increments the cycle after WDT_CTR1=WDT_MATCH1.  It is allowed to cascade all three WDT counters.
106630: Independent counters
106641: Cascaded counters.  When cascading all three counters, WDT_CLEAR1 must be 1.</description>
10665                <bitRange>[11:11]</bitRange>
10666                <access>read-write</access>
10667              </field>
10668              <field>
10669                <name>WDT_MODE2</name>
10670                <description>Watchdog Counter 2 Mode.</description>
10671                <bitRange>[16:16]</bitRange>
10672                <access>read-write</access>
10673                <enumeratedValues>
10674                  <enumeratedValue>
10675                    <name>NOTHING</name>
10676                    <description>Free running counter with no interrupt requests</description>
10677                    <value>0</value>
10678                  </enumeratedValue>
10679                  <enumeratedValue>
10680                    <name>INT</name>
10681                    <description>Free running counter with interrupt request that occurs one LFCLK cycle after the specified bit in CTR2 toggles (see WDT_BITS2).</description>
10682                    <value>1</value>
10683                  </enumeratedValue>
10684                </enumeratedValues>
10685              </field>
10686              <field>
10687                <name>WDT_BITS2</name>
10688                <description>Bit to observe for WDT_INT2:
106890: Assert after bit0 of WDT_CTR2 toggles (one int every tick)
10690...
1069131: Assert after bit31 of WDT_CTR2 toggles (one int every 2^31 ticks)</description>
10692                <bitRange>[28:24]</bitRange>
10693                <access>read-write</access>
10694              </field>
10695            </fields>
10696          </register>
10697          <register>
10698            <name>MCWDT_CTL</name>
10699            <description>Multi-Counter Watchdog Counter Control</description>
10700            <addressOffset>0x14</addressOffset>
10701            <size>32</size>
10702            <access>read-write</access>
10703            <resetValue>0x0</resetValue>
10704            <resetMask>0xB0B0B</resetMask>
10705            <fields>
10706              <field>
10707                <name>WDT_ENABLE0</name>
10708                <description>Enable subcounter 0.  May take up to 2 LFCLK cycles to take effect.
107090: Counter is disabled (not clocked)
107101: Counter is enabled (counting up)</description>
10711                <bitRange>[0:0]</bitRange>
10712                <access>read-write</access>
10713              </field>
10714              <field>
10715                <name>WDT_ENABLED0</name>
10716                <description>Indicates actual state of counter.  May lag WDT_ENABLE0 by up to two LFCLK cycles.</description>
10717                <bitRange>[1:1]</bitRange>
10718                <access>read-only</access>
10719              </field>
10720              <field>
10721                <name>WDT_RESET0</name>
10722                <description>Resets counter 0 back to 0000.  Hardware will reset this bit after counter was reset.  This will take up to one LFCLK cycle to take effect.</description>
10723                <bitRange>[3:3]</bitRange>
10724                <access>read-write</access>
10725              </field>
10726              <field>
10727                <name>WDT_ENABLE1</name>
10728                <description>Enable subcounter 1.  May take up to 2 LFCLK cycles to take effect.
107290: Counter is disabled (not clocked)
107301: Counter is enabled (counting up)</description>
10731                <bitRange>[8:8]</bitRange>
10732                <access>read-write</access>
10733              </field>
10734              <field>
10735                <name>WDT_ENABLED1</name>
10736                <description>Indicates actual state of counter.  May lag WDT_ENABLE1 by up to two LFCLK cycles.</description>
10737                <bitRange>[9:9]</bitRange>
10738                <access>read-only</access>
10739              </field>
10740              <field>
10741                <name>WDT_RESET1</name>
10742                <description>Resets counter 1 back to 0000.  Hardware will reset this bit after counter was reset.  This will take up to one LFCLK cycle to take effect.</description>
10743                <bitRange>[11:11]</bitRange>
10744                <access>read-write</access>
10745              </field>
10746              <field>
10747                <name>WDT_ENABLE2</name>
10748                <description>Enable subcounter 2.  May take up to 2 LFCLK cycles to take effect.
107490: Counter is disabled (not clocked)
107501: Counter is enabled (counting up)</description>
10751                <bitRange>[16:16]</bitRange>
10752                <access>read-write</access>
10753              </field>
10754              <field>
10755                <name>WDT_ENABLED2</name>
10756                <description>Indicates actual state of counter.  May lag WDT_ENABLE2 by up to two LFCLK cycles.</description>
10757                <bitRange>[17:17]</bitRange>
10758                <access>read-only</access>
10759              </field>
10760              <field>
10761                <name>WDT_RESET2</name>
10762                <description>Resets counter 2 back to 0000.  Hardware will reset this bit after counter was reset.  This will take up to one LFCLK cycle to take effect.</description>
10763                <bitRange>[19:19]</bitRange>
10764                <access>read-write</access>
10765              </field>
10766            </fields>
10767          </register>
10768          <register>
10769            <name>MCWDT_INTR</name>
10770            <description>Multi-Counter Watchdog Counter Interrupt Register</description>
10771            <addressOffset>0x18</addressOffset>
10772            <size>32</size>
10773            <access>read-write</access>
10774            <resetValue>0x0</resetValue>
10775            <resetMask>0x7</resetMask>
10776            <fields>
10777              <field>
10778                <name>MCWDT_INT0</name>
10779                <description>MCWDT Interrupt Request for sub-counter 0.  This bit is set by hardware as configured by this registers.  This bit must be cleared by firmware.  Clearing this bit also prevents Reset from happening when WDT_MODE0=3.</description>
10780                <bitRange>[0:0]</bitRange>
10781                <access>read-write</access>
10782              </field>
10783              <field>
10784                <name>MCWDT_INT1</name>
10785                <description>MCWDT Interrupt Request for sub-counter 1.  This bit is set by hardware as configured by this registers.  This bit must be cleared by firmware.  Clearing this bit also prevents Reset from happening when WDT_MODE1=3.</description>
10786                <bitRange>[1:1]</bitRange>
10787                <access>read-write</access>
10788              </field>
10789              <field>
10790                <name>MCWDT_INT2</name>
10791                <description>MCWDT Interrupt Request for sub-counter 2.  This bit is set by hardware as configured by this registers.  This bit must be cleared by firmware.  Clearing this bit also prevents Reset from happening when WDT_MODE2=3.</description>
10792                <bitRange>[2:2]</bitRange>
10793                <access>read-write</access>
10794              </field>
10795            </fields>
10796          </register>
10797          <register>
10798            <name>MCWDT_INTR_SET</name>
10799            <description>Multi-Counter Watchdog Counter Interrupt Set Register</description>
10800            <addressOffset>0x1C</addressOffset>
10801            <size>32</size>
10802            <access>read-write</access>
10803            <resetValue>0x0</resetValue>
10804            <resetMask>0x7</resetMask>
10805            <fields>
10806              <field>
10807                <name>MCWDT_INT0</name>
10808                <description>Set interrupt for MCWDT_INT0</description>
10809                <bitRange>[0:0]</bitRange>
10810                <access>read-write</access>
10811              </field>
10812              <field>
10813                <name>MCWDT_INT1</name>
10814                <description>Set interrupt for MCWDT_INT1</description>
10815                <bitRange>[1:1]</bitRange>
10816                <access>read-write</access>
10817              </field>
10818              <field>
10819                <name>MCWDT_INT2</name>
10820                <description>Set interrupt for MCWDT_INT2</description>
10821                <bitRange>[2:2]</bitRange>
10822                <access>read-write</access>
10823              </field>
10824            </fields>
10825          </register>
10826          <register>
10827            <name>MCWDT_INTR_MASK</name>
10828            <description>Multi-Counter Watchdog Counter Interrupt Mask Register</description>
10829            <addressOffset>0x20</addressOffset>
10830            <size>32</size>
10831            <access>read-write</access>
10832            <resetValue>0x0</resetValue>
10833            <resetMask>0x7</resetMask>
10834            <fields>
10835              <field>
10836                <name>MCWDT_INT0</name>
10837                <description>Mask for sub-counter 0</description>
10838                <bitRange>[0:0]</bitRange>
10839                <access>read-write</access>
10840              </field>
10841              <field>
10842                <name>MCWDT_INT1</name>
10843                <description>Mask for sub-counter 1</description>
10844                <bitRange>[1:1]</bitRange>
10845                <access>read-write</access>
10846              </field>
10847              <field>
10848                <name>MCWDT_INT2</name>
10849                <description>Mask for sub-counter 2</description>
10850                <bitRange>[2:2]</bitRange>
10851                <access>read-write</access>
10852              </field>
10853            </fields>
10854          </register>
10855          <register>
10856            <name>MCWDT_INTR_MASKED</name>
10857            <description>Multi-Counter Watchdog Counter Interrupt Masked Register</description>
10858            <addressOffset>0x24</addressOffset>
10859            <size>32</size>
10860            <access>read-only</access>
10861            <resetValue>0x0</resetValue>
10862            <resetMask>0x7</resetMask>
10863            <fields>
10864              <field>
10865                <name>MCWDT_INT0</name>
10866                <description>Logical and of corresponding request and mask bits.</description>
10867                <bitRange>[0:0]</bitRange>
10868                <access>read-only</access>
10869              </field>
10870              <field>
10871                <name>MCWDT_INT1</name>
10872                <description>Logical and of corresponding request and mask bits.</description>
10873                <bitRange>[1:1]</bitRange>
10874                <access>read-only</access>
10875              </field>
10876              <field>
10877                <name>MCWDT_INT2</name>
10878                <description>Logical and of corresponding request and mask bits.</description>
10879                <bitRange>[2:2]</bitRange>
10880                <access>read-only</access>
10881              </field>
10882            </fields>
10883          </register>
10884          <register>
10885            <name>MCWDT_LOCK</name>
10886            <description>Multi-Counter Watchdog Counter Lock Register</description>
10887            <addressOffset>0x28</addressOffset>
10888            <size>32</size>
10889            <access>read-write</access>
10890            <resetValue>0x0</resetValue>
10891            <resetMask>0xC0000000</resetMask>
10892            <fields>
10893              <field>
10894                <name>MCWDT_LOCK</name>
10895                <description>Prohibits writing control and configuration registers related to this MCWDT when not equal 0 (as specified in the other register descriptions).  Requires at least two different writes to unlock.
10896Note that this field is 2 bits to force multiple writes only.  Each MCWDT has a separate local lock.  LFCLK settings are locked by the global WDT_LOCK register, and this register has no effect on that.</description>
10897                <bitRange>[31:30]</bitRange>
10898                <access>read-write</access>
10899                <enumeratedValues>
10900                  <enumeratedValue>
10901                    <name>NO_CHG</name>
10902                    <description>No effect</description>
10903                    <value>0</value>
10904                  </enumeratedValue>
10905                  <enumeratedValue>
10906                    <name>CLR0</name>
10907                    <description>Clears bit 0</description>
10908                    <value>1</value>
10909                  </enumeratedValue>
10910                  <enumeratedValue>
10911                    <name>CLR1</name>
10912                    <description>Clears bit 1</description>
10913                    <value>2</value>
10914                  </enumeratedValue>
10915                  <enumeratedValue>
10916                    <name>SET01</name>
10917                    <description>Sets both bits 0 and 1</description>
10918                    <value>3</value>
10919                  </enumeratedValue>
10920                </enumeratedValues>
10921              </field>
10922            </fields>
10923          </register>
10924        </cluster>
10925        <register>
10926          <dim>16</dim>
10927          <dimIncrement>4</dimIncrement>
10928          <name>CLK_DSI_SELECT[%s]</name>
10929          <description>Clock DSI Select Register</description>
10930          <addressOffset>0x300</addressOffset>
10931          <size>32</size>
10932          <access>read-write</access>
10933          <resetValue>0x0</resetValue>
10934          <resetMask>0x1F</resetMask>
10935          <fields>
10936            <field>
10937              <name>DSI_MUX</name>
10938              <description>Selects a DSI source or low frequency clock for use in a clock path.  The output of this mux can be selected for clock PATH&lt;i&gt; using CLK_PATH_SELECT register.  Using the output of this mux as HFCLK source will result in undefined behavior.  It can be used to clocks to DSI or to the reference inputs of FLL/PLL, subject to the frequency limits of those circuits.  This mux is not glitch free, so do not change the selection while it is an actively selected clock.</description>
10939              <bitRange>[4:0]</bitRange>
10940              <access>read-write</access>
10941              <enumeratedValues>
10942                <enumeratedValue>
10943                  <name>DSI_OUT0</name>
10944                  <description>DSI0 - dsi_out[0]</description>
10945                  <value>0</value>
10946                </enumeratedValue>
10947                <enumeratedValue>
10948                  <name>DSI_OUT1</name>
10949                  <description>DSI1 - dsi_out[1]</description>
10950                  <value>1</value>
10951                </enumeratedValue>
10952                <enumeratedValue>
10953                  <name>DSI_OUT2</name>
10954                  <description>DSI2 - dsi_out[2]</description>
10955                  <value>2</value>
10956                </enumeratedValue>
10957                <enumeratedValue>
10958                  <name>DSI_OUT3</name>
10959                  <description>DSI3 - dsi_out[3]</description>
10960                  <value>3</value>
10961                </enumeratedValue>
10962                <enumeratedValue>
10963                  <name>DSI_OUT4</name>
10964                  <description>DSI4 - dsi_out[4]</description>
10965                  <value>4</value>
10966                </enumeratedValue>
10967                <enumeratedValue>
10968                  <name>DSI_OUT5</name>
10969                  <description>DSI5 - dsi_out[5]</description>
10970                  <value>5</value>
10971                </enumeratedValue>
10972                <enumeratedValue>
10973                  <name>DSI_OUT6</name>
10974                  <description>DSI6 - dsi_out[6]</description>
10975                  <value>6</value>
10976                </enumeratedValue>
10977                <enumeratedValue>
10978                  <name>DSI_OUT7</name>
10979                  <description>DSI7 - dsi_out[7]</description>
10980                  <value>7</value>
10981                </enumeratedValue>
10982                <enumeratedValue>
10983                  <name>DSI_OUT8</name>
10984                  <description>DSI8 - dsi_out[8]</description>
10985                  <value>8</value>
10986                </enumeratedValue>
10987                <enumeratedValue>
10988                  <name>DSI_OUT9</name>
10989                  <description>DSI9 - dsi_out[9]</description>
10990                  <value>9</value>
10991                </enumeratedValue>
10992                <enumeratedValue>
10993                  <name>DSI_OUT10</name>
10994                  <description>DSI10 - dsi_out[10]</description>
10995                  <value>10</value>
10996                </enumeratedValue>
10997                <enumeratedValue>
10998                  <name>DSI_OUT11</name>
10999                  <description>DSI11 - dsi_out[11]</description>
11000                  <value>11</value>
11001                </enumeratedValue>
11002                <enumeratedValue>
11003                  <name>DSI_OUT12</name>
11004                  <description>DSI12 - dsi_out[12]</description>
11005                  <value>12</value>
11006                </enumeratedValue>
11007                <enumeratedValue>
11008                  <name>DSI_OUT13</name>
11009                  <description>DSI13 - dsi_out[13]</description>
11010                  <value>13</value>
11011                </enumeratedValue>
11012                <enumeratedValue>
11013                  <name>DSI_OUT14</name>
11014                  <description>DSI14 - dsi_out[14]</description>
11015                  <value>14</value>
11016                </enumeratedValue>
11017                <enumeratedValue>
11018                  <name>DSI_OUT15</name>
11019                  <description>DSI15 - dsi_out[15]</description>
11020                  <value>15</value>
11021                </enumeratedValue>
11022                <enumeratedValue>
11023                  <name>ILO</name>
11024                  <description>ILO - Internal Low-speed Oscillator</description>
11025                  <value>16</value>
11026                </enumeratedValue>
11027                <enumeratedValue>
11028                  <name>WCO</name>
11029                  <description>WCO - Watch-Crystal Oscillator</description>
11030                  <value>17</value>
11031                </enumeratedValue>
11032                <enumeratedValue>
11033                  <name>ALTLF</name>
11034                  <description>ALTLF - Alternate Low-Frequency Clock</description>
11035                  <value>18</value>
11036                </enumeratedValue>
11037                <enumeratedValue>
11038                  <name>PILO</name>
11039                  <description>PILO - Precision Internal Low-speed Oscillator</description>
11040                  <value>19</value>
11041                </enumeratedValue>
11042              </enumeratedValues>
11043            </field>
11044          </fields>
11045        </register>
11046        <register>
11047          <dim>16</dim>
11048          <dimIncrement>4</dimIncrement>
11049          <name>CLK_PATH_SELECT[%s]</name>
11050          <description>Clock Path Select Register</description>
11051          <addressOffset>0x340</addressOffset>
11052          <size>32</size>
11053          <access>read-write</access>
11054          <resetValue>0x0</resetValue>
11055          <resetMask>0x7</resetMask>
11056          <fields>
11057            <field>
11058              <name>PATH_MUX</name>
11059              <description>Selects a source for clock PATH&lt;i&gt;.  Note that not all products support all clock sources.  Selecting a clock source that is not supported will result in undefined behavior.</description>
11060              <bitRange>[2:0]</bitRange>
11061              <access>read-write</access>
11062              <enumeratedValues>
11063                <enumeratedValue>
11064                  <name>IMO</name>
11065                  <description>IMO - Internal R/C Oscillator</description>
11066                  <value>0</value>
11067                </enumeratedValue>
11068                <enumeratedValue>
11069                  <name>EXTCLK</name>
11070                  <description>EXTCLK - External Clock Pin</description>
11071                  <value>1</value>
11072                </enumeratedValue>
11073                <enumeratedValue>
11074                  <name>ECO</name>
11075                  <description>ECO - External-Crystal Oscillator</description>
11076                  <value>2</value>
11077                </enumeratedValue>
11078                <enumeratedValue>
11079                  <name>ALTHF</name>
11080                  <description>ALTHF - Alternate High-Frequency clock input (product-specific clock)</description>
11081                  <value>3</value>
11082                </enumeratedValue>
11083                <enumeratedValue>
11084                  <name>DSI_MUX</name>
11085                  <description>DSI_MUX - Output of DSI mux for this path.  Using a DSI source directly as root of HFCLK will result in undefined behavior.</description>
11086                  <value>4</value>
11087                </enumeratedValue>
11088              </enumeratedValues>
11089            </field>
11090          </fields>
11091        </register>
11092        <register>
11093          <dim>16</dim>
11094          <dimIncrement>4</dimIncrement>
11095          <name>CLK_ROOT_SELECT[%s]</name>
11096          <description>Clock Root Select Register</description>
11097          <addressOffset>0x380</addressOffset>
11098          <size>32</size>
11099          <access>read-write</access>
11100          <resetValue>0x0</resetValue>
11101          <resetMask>0x8000003F</resetMask>
11102          <fields>
11103            <field>
11104              <name>ROOT_MUX</name>
11105              <description>Selects a clock path as the root of HFCLK&lt;k&gt; and for SRSS DSI input &lt;k&gt;.  Use CLK_PATH_SELECT[i] to configure the desired path.  Some paths may have FLL or PLL available (product-specific), and the control and bypass mux selections of these are in other registers.  Configure the FLL using CLK_FLL_CONFIG register.  Configure a PLL using the related CLK_PLL_CONFIG[k] register.  Note that not all products support all clock sources.  Selecting a clock source that is not supported will result in undefined behavior.</description>
11106              <bitRange>[3:0]</bitRange>
11107              <access>read-write</access>
11108              <enumeratedValues>
11109                <enumeratedValue>
11110                  <name>PATH0</name>
11111                  <description>Select PATH0 (can be configured for FLL)</description>
11112                  <value>0</value>
11113                </enumeratedValue>
11114                <enumeratedValue>
11115                  <name>PATH1</name>
11116                  <description>Select PATH1 (can be configured for PLL0, if available in the product)</description>
11117                  <value>1</value>
11118                </enumeratedValue>
11119                <enumeratedValue>
11120                  <name>PATH2</name>
11121                  <description>Select PATH2 (can be configured for PLL1, if available in the product)</description>
11122                  <value>2</value>
11123                </enumeratedValue>
11124                <enumeratedValue>
11125                  <name>PATH3</name>
11126                  <description>Select PATH3 (can be configured for PLL2, if available in the product)</description>
11127                  <value>3</value>
11128                </enumeratedValue>
11129                <enumeratedValue>
11130                  <name>PATH4</name>
11131                  <description>Select PATH4 (can be configured for PLL3, if available in the product)</description>
11132                  <value>4</value>
11133                </enumeratedValue>
11134                <enumeratedValue>
11135                  <name>PATH5</name>
11136                  <description>Select PATH5 (can be configured for PLL4, if available in the product)</description>
11137                  <value>5</value>
11138                </enumeratedValue>
11139                <enumeratedValue>
11140                  <name>PATH6</name>
11141                  <description>Select PATH6 (can be configured for PLL5, if available in the product)</description>
11142                  <value>6</value>
11143                </enumeratedValue>
11144                <enumeratedValue>
11145                  <name>PATH7</name>
11146                  <description>Select PATH7 (can be configured for PLL6, if available in the product)</description>
11147                  <value>7</value>
11148                </enumeratedValue>
11149                <enumeratedValue>
11150                  <name>PATH8</name>
11151                  <description>Select PATH8 (can be configured for PLL7, if available in the product)</description>
11152                  <value>8</value>
11153                </enumeratedValue>
11154                <enumeratedValue>
11155                  <name>PATH9</name>
11156                  <description>Select PATH9 (can be configured for PLL8, if available in the product)</description>
11157                  <value>9</value>
11158                </enumeratedValue>
11159                <enumeratedValue>
11160                  <name>PATH10</name>
11161                  <description>Select PATH10 (can be configured for PLL9, if available in the product)</description>
11162                  <value>10</value>
11163                </enumeratedValue>
11164                <enumeratedValue>
11165                  <name>PATH11</name>
11166                  <description>Select PATH11 (can be configured for PLL10, if available in the product)</description>
11167                  <value>11</value>
11168                </enumeratedValue>
11169                <enumeratedValue>
11170                  <name>PATH12</name>
11171                  <description>Select PATH12 (can be configured for PLL11, if available in the product)</description>
11172                  <value>12</value>
11173                </enumeratedValue>
11174                <enumeratedValue>
11175                  <name>PATH13</name>
11176                  <description>Select PATH13 (can be configured for PLL12, if available in the product)</description>
11177                  <value>13</value>
11178                </enumeratedValue>
11179                <enumeratedValue>
11180                  <name>PATH14</name>
11181                  <description>Select PATH14 (can be configured for PLL13, if available in the product)</description>
11182                  <value>14</value>
11183                </enumeratedValue>
11184                <enumeratedValue>
11185                  <name>PATH15</name>
11186                  <description>Select PATH15 (can be configured for PLL14, if available in the product)</description>
11187                  <value>15</value>
11188                </enumeratedValue>
11189              </enumeratedValues>
11190            </field>
11191            <field>
11192              <name>ROOT_DIV</name>
11193              <description>Selects predivider value for this clock root and DSI input.</description>
11194              <bitRange>[5:4]</bitRange>
11195              <access>read-write</access>
11196              <enumeratedValues>
11197                <enumeratedValue>
11198                  <name>NO_DIV</name>
11199                  <description>Transparent mode, feed through selected clock source w/o dividing.</description>
11200                  <value>0</value>
11201                </enumeratedValue>
11202                <enumeratedValue>
11203                  <name>DIV_BY_2</name>
11204                  <description>Divide selected clock source by 2</description>
11205                  <value>1</value>
11206                </enumeratedValue>
11207                <enumeratedValue>
11208                  <name>DIV_BY_4</name>
11209                  <description>Divide selected clock source by 4</description>
11210                  <value>2</value>
11211                </enumeratedValue>
11212                <enumeratedValue>
11213                  <name>DIV_BY_8</name>
11214                  <description>Divide selected clock source by 8</description>
11215                  <value>3</value>
11216                </enumeratedValue>
11217              </enumeratedValues>
11218            </field>
11219            <field>
11220              <name>ENABLE</name>
11221              <description>Enable for this clock root.  All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled.</description>
11222              <bitRange>[31:31]</bitRange>
11223              <access>read-write</access>
11224            </field>
11225          </fields>
11226        </register>
11227        <register>
11228          <name>CLK_SELECT</name>
11229          <description>Clock selection register</description>
11230          <addressOffset>0x500</addressOffset>
11231          <size>32</size>
11232          <access>read-write</access>
11233          <resetValue>0x0</resetValue>
11234          <resetMask>0xFF03</resetMask>
11235          <fields>
11236            <field>
11237              <name>LFCLK_SEL</name>
11238              <description>Select source for LFCLK.  Note that not all products support all clock sources.  Selecting a clock source that is not supported will result in undefined behavior.  Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register.</description>
11239              <bitRange>[1:0]</bitRange>
11240              <access>read-write</access>
11241              <enumeratedValues>
11242                <enumeratedValue>
11243                  <name>ILO</name>
11244                  <description>ILO - Internal Low-speed Oscillator</description>
11245                  <value>0</value>
11246                </enumeratedValue>
11247                <enumeratedValue>
11248                  <name>WCO</name>
11249                  <description>WCO - Watch-Crystal Oscillator.  Requires Backup domain to be present and properly configured (including external watch crystal, if used).</description>
11250                  <value>1</value>
11251                </enumeratedValue>
11252                <enumeratedValue>
11253                  <name>ALTLF</name>
11254                  <description>ALTLF - Alternate Low-Frequency Clock.  Capability is product-specific</description>
11255                  <value>2</value>
11256                </enumeratedValue>
11257                <enumeratedValue>
11258                  <name>PILO</name>
11259                  <description>PILO - Precision ILO. If present, it works in DEEPSLEEP and higher modes.  Does not work in HIBERNATE mode.</description>
11260                  <value>3</value>
11261                </enumeratedValue>
11262              </enumeratedValues>
11263            </field>
11264            <field>
11265              <name>PUMP_SEL</name>
11266              <description>Selects clock PATH&lt;k&gt;, where k=PUMP_SEL.  The output of this mux goes to the PUMP_DIV to make PUMPCLK  Each product has a specific number of available clock paths.  Selecting a path that is not implemented on a product will result in undefined behavior.  Note that this is not a glitch free mux.</description>
11267              <bitRange>[11:8]</bitRange>
11268              <access>read-write</access>
11269            </field>
11270            <field>
11271              <name>PUMP_DIV</name>
11272              <description>Division ratio for PUMPCLK.  Uses selected PUMP_SEL clock as the source.</description>
11273              <bitRange>[14:12]</bitRange>
11274              <access>read-write</access>
11275              <enumeratedValues>
11276                <enumeratedValue>
11277                  <name>NO_DIV</name>
11278                  <description>Transparent mode, feed through selected clock source w/o dividing.</description>
11279                  <value>0</value>
11280                </enumeratedValue>
11281                <enumeratedValue>
11282                  <name>DIV_BY_2</name>
11283                  <description>Divide selected clock source by 2</description>
11284                  <value>1</value>
11285                </enumeratedValue>
11286                <enumeratedValue>
11287                  <name>DIV_BY_4</name>
11288                  <description>Divide selected clock source by 4</description>
11289                  <value>2</value>
11290                </enumeratedValue>
11291                <enumeratedValue>
11292                  <name>DIV_BY_8</name>
11293                  <description>Divide selected clock source by 8</description>
11294                  <value>3</value>
11295                </enumeratedValue>
11296                <enumeratedValue>
11297                  <name>DIV_BY_16</name>
11298                  <description>Divide selected clock source by 16</description>
11299                  <value>4</value>
11300                </enumeratedValue>
11301              </enumeratedValues>
11302            </field>
11303            <field>
11304              <name>PUMP_ENABLE</name>
11305              <description>Enable the pump clock.  PUMP_ENABLE and the PUMP_SEL mux are not glitch-free to minimize side-effects, avoid changing the PUMP_SEL and PUMP_DIV while changing PUMP_ENABLE.  To change the settings, do the following:
113061) If the pump clock is enabled, write PUMP_ENABLE=0 without changing PUMP_SEL and PUMP_DIV.
113072) Change PUMP_SEL and PUMP_DIV to desired settings with PUMP_ENABLE=0.
113083) Write PUMP_ENABLE=1 without changing PUMP_SEL and PUMP_DIV.</description>
11309              <bitRange>[15:15]</bitRange>
11310              <access>read-write</access>
11311            </field>
11312          </fields>
11313        </register>
11314        <register>
11315          <name>CLK_TIMER_CTL</name>
11316          <description>Timer Clock Control Register</description>
11317          <addressOffset>0x504</addressOffset>
11318          <size>32</size>
11319          <access>read-write</access>
11320          <resetValue>0x70000</resetValue>
11321          <resetMask>0x80FF0301</resetMask>
11322          <fields>
11323            <field>
11324              <name>TIMER_SEL</name>
11325              <description>Select source for TIMERCLK.  The output of this mux can be further divided using TIMER_DIV.</description>
11326              <bitRange>[0:0]</bitRange>
11327              <access>read-write</access>
11328              <enumeratedValues>
11329                <enumeratedValue>
11330                  <name>IMO</name>
11331                  <description>IMO - Internal Main Oscillator</description>
11332                  <value>0</value>
11333                </enumeratedValue>
11334                <enumeratedValue>
11335                  <name>HF0_DIV</name>
11336                  <description>Select the output of the predivider configured by TIMER_HF0_DIV.</description>
11337                  <value>1</value>
11338                </enumeratedValue>
11339              </enumeratedValues>
11340            </field>
11341            <field>
11342              <name>TIMER_HF0_DIV</name>
11343              <description>Predivider used when HF0_DIV is selected in TIMER_SEL.  If HFCLK0 frequency is less than 100MHz and has approximately 50 percent duty cycle, then no division is required (NO_DIV).  Otherwise, select a divide ratio of 2, 4, or 8 before selected HF0_DIV as the timer clock.</description>
11344              <bitRange>[9:8]</bitRange>
11345              <access>read-write</access>
11346              <enumeratedValues>
11347                <enumeratedValue>
11348                  <name>NO_DIV</name>
11349                  <description>Transparent mode, feed through selected clock source w/o dividing or correcting duty cycle.</description>
11350                  <value>0</value>
11351                </enumeratedValue>
11352                <enumeratedValue>
11353                  <name>DIV_BY_2</name>
11354                  <description>Divide HFCLK0 by 2.</description>
11355                  <value>1</value>
11356                </enumeratedValue>
11357                <enumeratedValue>
11358                  <name>DIV_BY_4</name>
11359                  <description>Divide HFCLK0 by 4.</description>
11360                  <value>2</value>
11361                </enumeratedValue>
11362                <enumeratedValue>
11363                  <name>DIV_BY_8</name>
11364                  <description>Divide HFCLK0 by 8.</description>
11365                  <value>3</value>
11366                </enumeratedValue>
11367              </enumeratedValues>
11368            </field>
11369            <field>
11370              <name>TIMER_DIV</name>
11371              <description>Divide selected timer clock source by (1+TIMER_DIV).  The output of this divider is TIMERCLK  Allows for integer divisions in the range [1, 256].  Do not change this setting while the timer is enabled.</description>
11372              <bitRange>[23:16]</bitRange>
11373              <access>read-write</access>
11374            </field>
11375            <field>
11376              <name>ENABLE</name>
11377              <description>Enable for TIMERCLK.
113780: TIMERCLK is off
113791: TIMERCLK is enabled</description>
11380              <bitRange>[31:31]</bitRange>
11381              <access>read-write</access>
11382            </field>
11383          </fields>
11384        </register>
11385        <register>
11386          <name>CLK_ILO_CONFIG</name>
11387          <description>ILO Configuration</description>
11388          <addressOffset>0x50C</addressOffset>
11389          <size>32</size>
11390          <access>read-write</access>
11391          <resetValue>0x80000000</resetValue>
11392          <resetMask>0x80000001</resetMask>
11393          <fields>
11394            <field>
11395              <name>ILO_BACKUP</name>
11396              <description>If backup domain is present on this product, this register indicates that ILO should stay enabled for use by backup domain during XRES, HIBERNATE mode, and through power-related resets like BOD on VDDD/VCCD.  Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register.
113970: ILO turns off at XRES/BOD event or HIBERNATE entry.
113981: ILO remains on if backup domain is present and powered even for XRES/BOD or HIBERNATE entry.</description>
11399              <bitRange>[0:0]</bitRange>
11400              <access>read-write</access>
11401            </field>
11402            <field>
11403              <name>ENABLE</name>
11404              <description>Master enable for ILO.  Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register.  After enabling, it takes at most two cycles to reach the accuracy spec.</description>
11405              <bitRange>[31:31]</bitRange>
11406              <access>read-write</access>
11407            </field>
11408          </fields>
11409        </register>
11410        <register>
11411          <name>CLK_IMO_CONFIG</name>
11412          <description>IMO Configuration</description>
11413          <addressOffset>0x510</addressOffset>
11414          <size>32</size>
11415          <access>read-write</access>
11416          <resetValue>0x80000000</resetValue>
11417          <resetMask>0x80000000</resetMask>
11418          <fields>
11419            <field>
11420              <name>ENABLE</name>
11421              <description>Master enable for IMO oscillator.  This bit must be high at all times for all functions to work properly.  Hardware will automatically disable the IMO during HIBERNATE and XRES.  It will automatically disable during DEEPSLEEP if CLK_MFO_CONFIG.DPSLP_ENABLE==0.</description>
11422              <bitRange>[31:31]</bitRange>
11423              <access>read-write</access>
11424            </field>
11425          </fields>
11426        </register>
11427        <register>
11428          <name>CLK_OUTPUT_FAST</name>
11429          <description>Fast Clock Output Select Register</description>
11430          <addressOffset>0x514</addressOffset>
11431          <size>32</size>
11432          <access>read-write</access>
11433          <resetValue>0x0</resetValue>
11434          <resetMask>0xFFF0FFF</resetMask>
11435          <fields>
11436            <field>
11437              <name>FAST_SEL0</name>
11438              <description>Select signal for fast clock output #0</description>
11439              <bitRange>[3:0]</bitRange>
11440              <access>read-write</access>
11441              <enumeratedValues>
11442                <enumeratedValue>
11443                  <name>NC</name>
11444                  <description>Disabled - output is 0.  For power savings, clocks are blocked before entering any muxes, including PATH_SEL0 and HFCLK_SEL0.</description>
11445                  <value>0</value>
11446                </enumeratedValue>
11447                <enumeratedValue>
11448                  <name>ECO</name>
11449                  <description>External Crystal Oscillator (ECO)</description>
11450                  <value>1</value>
11451                </enumeratedValue>
11452                <enumeratedValue>
11453                  <name>EXTCLK</name>
11454                  <description>External clock input (EXTCLK)</description>
11455                  <value>2</value>
11456                </enumeratedValue>
11457                <enumeratedValue>
11458                  <name>ALTHF</name>
11459                  <description>Alternate High-Frequency (ALTHF) clock input to SRSS</description>
11460                  <value>3</value>
11461                </enumeratedValue>
11462                <enumeratedValue>
11463                  <name>TIMERCLK</name>
11464                  <description>Timer clock.  It is grouped with the fast clocks because it may be a gated version of a fast clock, and therefore may have a short high pulse.</description>
11465                  <value>4</value>
11466                </enumeratedValue>
11467                <enumeratedValue>
11468                  <name>PATH_SEL0</name>
11469                  <description>Selects the clock path chosen by PATH_SEL0 field</description>
11470                  <value>5</value>
11471                </enumeratedValue>
11472                <enumeratedValue>
11473                  <name>HFCLK_SEL0</name>
11474                  <description>Selects the output of the HFCLK_SEL0 mux</description>
11475                  <value>6</value>
11476                </enumeratedValue>
11477                <enumeratedValue>
11478                  <name>SLOW_SEL0</name>
11479                  <description>Selects the output of CLK_OUTPUT_SLOW.SLOW_SEL0</description>
11480                  <value>7</value>
11481                </enumeratedValue>
11482              </enumeratedValues>
11483            </field>
11484            <field>
11485              <name>PATH_SEL0</name>
11486              <description>Selects a clock path to use in fast clock output #0 logic.  0: FLL output
114871-15: PLL output on path1-path15 (if available)</description>
11488              <bitRange>[7:4]</bitRange>
11489              <access>read-write</access>
11490            </field>
11491            <field>
11492              <name>HFCLK_SEL0</name>
11493              <description>Selects a HFCLK tree for use in fast clock output #0</description>
11494              <bitRange>[11:8]</bitRange>
11495              <access>read-write</access>
11496            </field>
11497            <field>
11498              <name>FAST_SEL1</name>
11499              <description>Select signal for fast clock output #1</description>
11500              <bitRange>[19:16]</bitRange>
11501              <access>read-write</access>
11502              <enumeratedValues>
11503                <enumeratedValue>
11504                  <name>NC</name>
11505                  <description>Disabled - output is 0.  For power savings, clocks are blocked before entering any muxes, including PATH_SEL1 and HFCLK_SEL1.</description>
11506                  <value>0</value>
11507                </enumeratedValue>
11508                <enumeratedValue>
11509                  <name>ECO</name>
11510                  <description>External Crystal Oscillator (ECO)</description>
11511                  <value>1</value>
11512                </enumeratedValue>
11513                <enumeratedValue>
11514                  <name>EXTCLK</name>
11515                  <description>External clock input (EXTCLK)</description>
11516                  <value>2</value>
11517                </enumeratedValue>
11518                <enumeratedValue>
11519                  <name>ALTHF</name>
11520                  <description>Alternate High-Frequency (ALTHF) clock input to SRSS</description>
11521                  <value>3</value>
11522                </enumeratedValue>
11523                <enumeratedValue>
11524                  <name>TIMERCLK</name>
11525                  <description>Timer clock.  It is grouped with the fast clocks because it may be a gated version of a fast clock, and therefore may have a short high pulse.</description>
11526                  <value>4</value>
11527                </enumeratedValue>
11528                <enumeratedValue>
11529                  <name>PATH_SEL1</name>
11530                  <description>Selects the clock path chosen by PATH_SEL1 field</description>
11531                  <value>5</value>
11532                </enumeratedValue>
11533                <enumeratedValue>
11534                  <name>HFCLK_SEL1</name>
11535                  <description>Selects the output of the HFCLK_SEL1 mux</description>
11536                  <value>6</value>
11537                </enumeratedValue>
11538                <enumeratedValue>
11539                  <name>SLOW_SEL1</name>
11540                  <description>Selects the output of CLK_OUTPUT_SLOW.SLOW_SEL1</description>
11541                  <value>7</value>
11542                </enumeratedValue>
11543              </enumeratedValues>
11544            </field>
11545            <field>
11546              <name>PATH_SEL1</name>
11547              <description>Selects a clock path to use in fast clock output #1 logic.  0: FLL output
115481-15: PLL output on path1-path15 (if available)</description>
11549              <bitRange>[23:20]</bitRange>
11550              <access>read-write</access>
11551            </field>
11552            <field>
11553              <name>HFCLK_SEL1</name>
11554              <description>Selects a HFCLK tree for use in fast clock output #1 logic</description>
11555              <bitRange>[27:24]</bitRange>
11556              <access>read-write</access>
11557            </field>
11558          </fields>
11559        </register>
11560        <register>
11561          <name>CLK_OUTPUT_SLOW</name>
11562          <description>Slow Clock Output Select Register</description>
11563          <addressOffset>0x518</addressOffset>
11564          <size>32</size>
11565          <access>read-write</access>
11566          <resetValue>0x0</resetValue>
11567          <resetMask>0xFF</resetMask>
11568          <fields>
11569            <field>
11570              <name>SLOW_SEL0</name>
11571              <description>Select signal for slow clock output #0</description>
11572              <bitRange>[3:0]</bitRange>
11573              <access>read-write</access>
11574              <enumeratedValues>
11575                <enumeratedValue>
11576                  <name>NC</name>
11577                  <description>Disabled - output is 0.  For power savings, clocks are blocked before entering any muxes.</description>
11578                  <value>0</value>
11579                </enumeratedValue>
11580                <enumeratedValue>
11581                  <name>ILO</name>
11582                  <description>Internal Low Speed Oscillator (ILO)</description>
11583                  <value>1</value>
11584                </enumeratedValue>
11585                <enumeratedValue>
11586                  <name>WCO</name>
11587                  <description>Watch-Crystal Oscillator (WCO)</description>
11588                  <value>2</value>
11589                </enumeratedValue>
11590                <enumeratedValue>
11591                  <name>BAK</name>
11592                  <description>Root of the Backup domain clock tree (BAK)</description>
11593                  <value>3</value>
11594                </enumeratedValue>
11595                <enumeratedValue>
11596                  <name>ALTLF</name>
11597                  <description>Alternate low-frequency clock input to SRSS (ALTLF)</description>
11598                  <value>4</value>
11599                </enumeratedValue>
11600                <enumeratedValue>
11601                  <name>LFCLK</name>
11602                  <description>Root of the low-speed clock tree (LFCLK)</description>
11603                  <value>5</value>
11604                </enumeratedValue>
11605                <enumeratedValue>
11606                  <name>IMO</name>
11607                  <description>Internal Main Oscillator (IMO).  This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit.</description>
11608                  <value>6</value>
11609                </enumeratedValue>
11610                <enumeratedValue>
11611                  <name>SLPCTRL</name>
11612                  <description>Sleep Controller clock (SLPCTRL).  This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit.</description>
11613                  <value>7</value>
11614                </enumeratedValue>
11615                <enumeratedValue>
11616                  <name>PILO</name>
11617                  <description>Precision Internal Low Speed Oscillator (PILO)</description>
11618                  <value>8</value>
11619                </enumeratedValue>
11620              </enumeratedValues>
11621            </field>
11622            <field>
11623              <name>SLOW_SEL1</name>
11624              <description>Select signal for slow clock output #1</description>
11625              <bitRange>[7:4]</bitRange>
11626              <access>read-write</access>
11627              <enumeratedValues>
11628                <enumeratedValue>
11629                  <name>NC</name>
11630                  <description>Disabled - output is 0.  For power savings, clocks are blocked before entering any muxes.</description>
11631                  <value>0</value>
11632                </enumeratedValue>
11633                <enumeratedValue>
11634                  <name>ILO</name>
11635                  <description>Internal Low Speed Oscillator (ILO)</description>
11636                  <value>1</value>
11637                </enumeratedValue>
11638                <enumeratedValue>
11639                  <name>WCO</name>
11640                  <description>Watch-Crystal Oscillator (WCO)</description>
11641                  <value>2</value>
11642                </enumeratedValue>
11643                <enumeratedValue>
11644                  <name>BAK</name>
11645                  <description>Root of the Backup domain clock tree (BAK)</description>
11646                  <value>3</value>
11647                </enumeratedValue>
11648                <enumeratedValue>
11649                  <name>ALTLF</name>
11650                  <description>Alternate low-frequency clock input to SRSS (ALTLF)</description>
11651                  <value>4</value>
11652                </enumeratedValue>
11653                <enumeratedValue>
11654                  <name>LFCLK</name>
11655                  <description>Root of the low-speed clock tree (LFCLK)</description>
11656                  <value>5</value>
11657                </enumeratedValue>
11658                <enumeratedValue>
11659                  <name>IMO</name>
11660                  <description>Internal Main Oscillator (IMO).  This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit.</description>
11661                  <value>6</value>
11662                </enumeratedValue>
11663                <enumeratedValue>
11664                  <name>SLPCTRL</name>
11665                  <description>Sleep Controller clock (SLPCTRL).  This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit.</description>
11666                  <value>7</value>
11667                </enumeratedValue>
11668                <enumeratedValue>
11669                  <name>PILO</name>
11670                  <description>Precision Internal Low Speed Oscillator (PILO)</description>
11671                  <value>8</value>
11672                </enumeratedValue>
11673              </enumeratedValues>
11674            </field>
11675          </fields>
11676        </register>
11677        <register>
11678          <name>CLK_CAL_CNT1</name>
11679          <description>Clock Calibration Counter 1</description>
11680          <addressOffset>0x51C</addressOffset>
11681          <size>32</size>
11682          <access>read-write</access>
11683          <resetValue>0x80000000</resetValue>
11684          <resetMask>0x80FFFFFF</resetMask>
11685          <fields>
11686            <field>
11687              <name>CAL_COUNTER1</name>
11688              <description>Down-counter clocked on fast clock output #0 (see CLK_OUTPUT_FAST). This register always reads as zero.  Counting starts internally when this register is written with a nonzero value.  CAL_COUNTER_DONE goes immediately low to indicate that the counter has started and will be asserted when the counters are done.  Do not write this field unless CAL_COUNTER_DONE==1.  Both clocks must be running or the measurement will not complete.  A stalled counter can be recovered by selecting valid clocks, waiting until the measurement completes, and discarding the first result.</description>
11689              <bitRange>[23:0]</bitRange>
11690              <access>read-write</access>
11691            </field>
11692            <field>
11693              <name>CAL_COUNTER_DONE</name>
11694              <description>Status bit indicating that the internal counter #1 is finished counting and CLK_CAL_CNT2.COUNTER stopped counting up</description>
11695              <bitRange>[31:31]</bitRange>
11696              <access>read-only</access>
11697            </field>
11698          </fields>
11699        </register>
11700        <register>
11701          <name>CLK_CAL_CNT2</name>
11702          <description>Clock Calibration Counter 2</description>
11703          <addressOffset>0x520</addressOffset>
11704          <size>32</size>
11705          <access>read-only</access>
11706          <resetValue>0x0</resetValue>
11707          <resetMask>0xFFFFFF</resetMask>
11708          <fields>
11709            <field>
11710              <name>CAL_COUNTER2</name>
11711              <description>Up-counter clocked on fast clock output  #1 (see CLK_OUTPUT_FAST). When CLK_CAL_CNT1.CAL_COUNTER_DONE==1, the counter is stopped and can be read by SW.  Do not read this value unless CAL_COUNTER_DONE==1.  The expected final value is related to the ratio of clock frequencies used for the two counters and the value loaded into counter 1: CLK_CAL_CNT2.COUNTER=(F_cnt2/F_cnt1)*(CLK_CAL_CNT1.COUNTER)</description>
11712              <bitRange>[23:0]</bitRange>
11713              <access>read-only</access>
11714            </field>
11715          </fields>
11716        </register>
11717        <register>
11718          <name>CLK_ECO_CONFIG</name>
11719          <description>ECO Configuration Register</description>
11720          <addressOffset>0x52C</addressOffset>
11721          <size>32</size>
11722          <access>read-write</access>
11723          <resetValue>0x2</resetValue>
11724          <resetMask>0x80000002</resetMask>
11725          <fields>
11726            <field>
11727              <name>AGC_EN</name>
11728              <description>Automatic Gain Control (AGC) enable.  When set, the oscillation amplitude is controlled to the level selected by ECO_TRIM0.ATRIM.  When low, the amplitude is not explicitly controlled and can be as high as the vddd supply.  WARNING: use care when disabling AGC because driving a crystal beyond its rated limit can permanently damage the crystal.</description>
11729              <bitRange>[1:1]</bitRange>
11730              <access>read-write</access>
11731            </field>
11732            <field>
11733              <name>ECO_EN</name>
11734              <description>Master enable for ECO oscillator.</description>
11735              <bitRange>[31:31]</bitRange>
11736              <access>read-write</access>
11737            </field>
11738          </fields>
11739        </register>
11740        <register>
11741          <name>CLK_ECO_STATUS</name>
11742          <description>ECO Status Register</description>
11743          <addressOffset>0x530</addressOffset>
11744          <size>32</size>
11745          <access>read-only</access>
11746          <resetValue>0x0</resetValue>
11747          <resetMask>0x3</resetMask>
11748          <fields>
11749            <field>
11750              <name>ECO_OK</name>
11751              <description>Indicates the ECO internal oscillator circuit has sufficient amplitude.  It may not meet the PPM accuracy or duty cycle spec.</description>
11752              <bitRange>[0:0]</bitRange>
11753              <access>read-only</access>
11754            </field>
11755            <field>
11756              <name>ECO_READY</name>
11757              <description>Indicates the ECO internal oscillator circuit has had enough time to fully stabilize.  This is the output of a counter since ECO was enabled, and it does not check the ECO output.  It is recommended to also confirm ECO_OK==1.</description>
11758              <bitRange>[1:1]</bitRange>
11759              <access>read-only</access>
11760            </field>
11761          </fields>
11762        </register>
11763        <register>
11764          <name>CLK_PILO_CONFIG</name>
11765          <description>Precision ILO Configuration Register</description>
11766          <addressOffset>0x53C</addressOffset>
11767          <size>32</size>
11768          <access>read-write</access>
11769          <resetValue>0x80</resetValue>
11770          <resetMask>0xE00003FF</resetMask>
11771          <fields>
11772            <field>
11773              <name>PILO_FFREQ</name>
11774              <description>Fine frequency trim allowing +/-250ppm accuracy with periodic calibration.  The nominal step size of the LSB is 8Hz.</description>
11775              <bitRange>[9:0]</bitRange>
11776              <access>read-write</access>
11777            </field>
11778            <field>
11779              <name>PILO_CLK_EN</name>
11780              <description>Enable the PILO clock output.  See PILO_EN field for required sequencing.</description>
11781              <bitRange>[29:29]</bitRange>
11782              <access>read-write</access>
11783            </field>
11784            <field>
11785              <name>PILO_RESET_N</name>
11786              <description>Reset the PILO.  See PILO_EN field for required sequencing.</description>
11787              <bitRange>[30:30]</bitRange>
11788              <access>read-write</access>
11789            </field>
11790            <field>
11791              <name>PILO_EN</name>
11792              <description>Enable PILO.  When enabling PILO, set PILO_EN=1, wait 1ms, then PILO_RESET_N=1 and PILO_CLK_EN=1.  When disabling PILO, clear PILO_EN=0, PILO_RESET_N=0, and PLO_CLK_EN=0 in the same write cycle.</description>
11793              <bitRange>[31:31]</bitRange>
11794              <access>read-write</access>
11795            </field>
11796          </fields>
11797        </register>
11798        <register>
11799          <name>CLK_MF_SELECT</name>
11800          <description>Medium Frequency Clock Select Register</description>
11801          <addressOffset>0x544</addressOffset>
11802          <size>32</size>
11803          <access>read-write</access>
11804          <resetValue>0x0</resetValue>
11805          <resetMask>0x8000FF07</resetMask>
11806          <fields>
11807            <field>
11808              <name>MFCLK_SEL</name>
11809              <description>Select source for MFCLK (clk_mf).  Note that not all products support all clock sources.  Selecting a clock source that is not supported results in undefined behavior.</description>
11810              <bitRange>[2:0]</bitRange>
11811              <access>read-write</access>
11812              <enumeratedValues>
11813                <enumeratedValue>
11814                  <name>MFO</name>
11815                  <description>MFO - medium frequency oscillator</description>
11816                  <value>0</value>
11817                </enumeratedValue>
11818              </enumeratedValues>
11819            </field>
11820            <field>
11821              <name>MFCLK_DIV</name>
11822              <description>Divide selected clock source by (1+MFCLK_DIV).  The output of this divider is MFCLK (clk_mf).  Allows for integer divisions in the range [1, 256].  Do not change this setting while ENABLE==1.</description>
11823              <bitRange>[15:8]</bitRange>
11824              <access>read-write</access>
11825            </field>
11826            <field>
11827              <name>ENABLE</name>
11828              <description>Enable for MFCLK (clk_mf).</description>
11829              <bitRange>[31:31]</bitRange>
11830              <access>read-write</access>
11831            </field>
11832          </fields>
11833        </register>
11834        <register>
11835          <name>CLK_MFO_CONFIG</name>
11836          <description>MFO Configuration Register</description>
11837          <addressOffset>0x548</addressOffset>
11838          <size>32</size>
11839          <access>read-write</access>
11840          <resetValue>0x80000000</resetValue>
11841          <resetMask>0xC0000000</resetMask>
11842          <fields>
11843            <field>
11844              <name>DPSLP_ENABLE</name>
11845              <description>Enable for MFO during DEEPSLEEP.  This bit is ignored when ENABLE==0.  When ENABLE==1:
118460: MFO is automatically disabled during DEEPSLEEP and enables upon wakeup;
118471: MFO is kept enabled throughout DEEPSLEEP</description>
11848              <bitRange>[30:30]</bitRange>
11849              <access>read-write</access>
11850            </field>
11851            <field>
11852              <name>ENABLE</name>
11853              <description>Enable for MFO.</description>
11854              <bitRange>[31:31]</bitRange>
11855              <access>read-write</access>
11856            </field>
11857          </fields>
11858        </register>
11859        <register>
11860          <name>CLK_FLL_CONFIG</name>
11861          <description>FLL Configuration Register</description>
11862          <addressOffset>0x580</addressOffset>
11863          <size>32</size>
11864          <access>read-write</access>
11865          <resetValue>0x1000000</resetValue>
11866          <resetMask>0x8103FFFF</resetMask>
11867          <fields>
11868            <field>
11869              <name>FLL_MULT</name>
11870              <description>Multiplier to determine CCO frequency in multiples of the frequency of the selected reference clock (Fref).
11871
11872Ffll = (FLL_MULT)  * (Fref / REFERENCE_DIV) / (OUTPUT_DIV+1)</description>
11873              <bitRange>[17:0]</bitRange>
11874              <access>read-write</access>
11875            </field>
11876            <field>
11877              <name>FLL_OUTPUT_DIV</name>
11878              <description>Control bits for Output divider.  Set the divide value before enabling the FLL, and do not change it while FLL is enabled.
118790: no division
118801: divide by 2</description>
11881              <bitRange>[24:24]</bitRange>
11882              <access>read-write</access>
11883            </field>
11884            <field>
11885              <name>FLL_ENABLE</name>
11886              <description>Master enable for FLL.  The FLL requires firmware sequencing when enabling, disabling, and entering/exiting DEEPSLEEP.
11887
11888To enable the FLL, first enable the CCO by writing CLK_FLL_CONFIG4.CCO_ENABLE=1 and wait until CLK_FLL_STATUS.CCO_READY==1.  Next, ensure the reference clock has stabilized and CLK_FLL_CONFIG3.BYPASS_SEL=FLL_REF.  Next, write FLL_ENABLE=1 and wait until CLK_FLL_STATUS.LOCKED==1.  Finally, write CLK_FLL_CONFIG3.BYPASS_SEL=FLL_OUT to switch to the FLL output.  It takes seven reference clock cycles plus four FLL output cycles to switch to the FLL output.  Do not disable the FLL before this time completes.
11889
11890To disable the FLL, write CLK_FLL_CONFIG3.BYPASS_SEL=FLL_REF and (optionally) read the same register to ensure the write completes.  Then, wait at least seven FLL reference clock cycles before disabling it with FLL_ENABLE=0.  Lastly, disable the CCO by writing CLK_FLL_CONFIG4.CCO_ENABLE=0.
11891
11892Before entering DEEPSLEEP, either disable the FLL using above sequence or use the following procedure to deselect/select it before/after DEEPSLEEP.  Before entering DEEPSLEEP, write CLK_FLL_CONFIG3.BYPASS_SEL=FLL_REF to change the FLL to use its reference clock.  After DEEPSLEEP wakeup, wait until CLK_FLL_STATUS.LOCKED==1 and then write CLK_FLL_CONFIG3.BYPASS_SEL=FLL_OUT to switch to the FLL output.
11893
118940: Block is powered off
118951: Block is powered on</description>
11896              <bitRange>[31:31]</bitRange>
11897              <access>read-write</access>
11898            </field>
11899          </fields>
11900        </register>
11901        <register>
11902          <name>CLK_FLL_CONFIG2</name>
11903          <description>FLL Configuration Register 2</description>
11904          <addressOffset>0x584</addressOffset>
11905          <size>32</size>
11906          <access>read-write</access>
11907          <resetValue>0x20001</resetValue>
11908          <resetMask>0x1FF1FFF</resetMask>
11909          <fields>
11910            <field>
11911              <name>FLL_REF_DIV</name>
11912              <description>Control bits for reference divider.  Set the divide value before enabling the FLL, and do not change it while FLL is enabled.
119130: illegal (undefined behavior)
119141: divide by 1
11915...
119168191: divide by 8191</description>
11917              <bitRange>[12:0]</bitRange>
11918              <access>read-write</access>
11919            </field>
11920            <field>
11921              <name>LOCK_TOL</name>
11922              <description>Lock tolerance sets the error threshold for when the FLL output is considered locked to the reference input.  A high tolerance can be used to lock more quickly or to track a less accurate source.  The tolerance should be set so that the FLL does not unlock under normal conditions.  The tolerance is the allowed difference between the count value for the ideal formula and the measured value.
119230: tolerate error of 1 count value
119241: tolerate error of 2 count values
11925...
11926511: tolerate error of 512 count values</description>
11927              <bitRange>[24:16]</bitRange>
11928              <access>read-write</access>
11929            </field>
11930          </fields>
11931        </register>
11932        <register>
11933          <name>CLK_FLL_CONFIG3</name>
11934          <description>FLL Configuration Register 3</description>
11935          <addressOffset>0x588</addressOffset>
11936          <size>32</size>
11937          <access>read-write</access>
11938          <resetValue>0x2800</resetValue>
11939          <resetMask>0x301FFFFF</resetMask>
11940          <fields>
11941            <field>
11942              <name>FLL_LF_IGAIN</name>
11943              <description>FLL Loop Filter Gain Setting #1.  The proportional gain is the sum of FLL_LF_IGAIN and FLL_LF_PGAIN.
119440: 1/256
119451: 1/128
119462: 1/64
119473: 1/32
119484: 1/16
119495: 1/8
119506: 1/4
119517: 1/2
119528: 1.0
119539: 2.0
1195410: 4.0
1195511: 8.0
11956&gt;=12: illegal</description>
11957              <bitRange>[3:0]</bitRange>
11958              <access>read-write</access>
11959            </field>
11960            <field>
11961              <name>FLL_LF_PGAIN</name>
11962              <description>FLL Loop Filter Gain Setting #2.  The proportional gain is the sum of FLL_LF_IGAIN and FLL_LF_PGAIN.
119630: 1/256
119641: 1/128
119652: 1/64
119663: 1/32
119674: 1/16
119685: 1/8
119696: 1/4
119707: 1/2
119718: 1.0
119729: 2.0
1197310: 4.0
1197411: 8.0
11975&gt;=12: illegal</description>
11976              <bitRange>[7:4]</bitRange>
11977              <access>read-write</access>
11978            </field>
11979            <field>
11980              <name>SETTLING_COUNT</name>
11981              <description>Number of undivided reference clock cycles to wait after changing the CCO trim until the loop measurement restarts.  A delay allows the CCO output to settle and gives a more accurate measurement.  The default is tuned to an 8MHz reference clock since the IMO is expected to be the most common use case.
119820: no settling time
119831: wait one reference clock cycle
11984...
119858191: wait 8191 reference clock cycles</description>
11986              <bitRange>[20:8]</bitRange>
11987              <access>read-write</access>
11988            </field>
11989            <field>
11990              <name>BYPASS_SEL</name>
11991              <description>Bypass mux located just after FLL output.  See FLL_ENABLE description for instructions on how to use this field when enabling/disabling the FLL.</description>
11992              <bitRange>[29:28]</bitRange>
11993              <access>read-write</access>
11994              <enumeratedValues>
11995                <enumeratedValue>
11996                  <name>AUTO</name>
11997                  <description>N/A</description>
11998                  <value>0</value>
11999                </enumeratedValue>
12000                <enumeratedValue>
12001                  <name>AUTO1</name>
12002                  <description>N/A</description>
12003                  <value>1</value>
12004                </enumeratedValue>
12005                <enumeratedValue>
12006                  <name>FLL_REF</name>
12007                  <description>Select FLL reference input (bypass mode).  Ignores lock indicator</description>
12008                  <value>2</value>
12009                </enumeratedValue>
12010                <enumeratedValue>
12011                  <name>FLL_OUT</name>
12012                  <description>Select FLL output.  Ignores lock indicator.</description>
12013                  <value>3</value>
12014                </enumeratedValue>
12015              </enumeratedValues>
12016            </field>
12017          </fields>
12018        </register>
12019        <register>
12020          <name>CLK_FLL_CONFIG4</name>
12021          <description>FLL Configuration Register 4</description>
12022          <addressOffset>0x58C</addressOffset>
12023          <size>32</size>
12024          <access>read-write</access>
12025          <resetValue>0xFF</resetValue>
12026          <resetMask>0xC1FF07FF</resetMask>
12027          <fields>
12028            <field>
12029              <name>CCO_LIMIT</name>
12030              <description>Maximum CCO offset allowed (used to prevent FLL dynamics from selecting an CCO frequency that the logic cannot support)</description>
12031              <bitRange>[7:0]</bitRange>
12032              <access>read-write</access>
12033            </field>
12034            <field>
12035              <name>CCO_RANGE</name>
12036              <description>Frequency range of CCO</description>
12037              <bitRange>[10:8]</bitRange>
12038              <access>read-write</access>
12039              <enumeratedValues>
12040                <enumeratedValue>
12041                  <name>RANGE0</name>
12042                  <description>Target frequency is in range [48, 64) MHz</description>
12043                  <value>0</value>
12044                </enumeratedValue>
12045                <enumeratedValue>
12046                  <name>RANGE1</name>
12047                  <description>Target frequency is in range [64, 85) MHz</description>
12048                  <value>1</value>
12049                </enumeratedValue>
12050                <enumeratedValue>
12051                  <name>RANGE2</name>
12052                  <description>Target frequency is in range [85, 113) MHz</description>
12053                  <value>2</value>
12054                </enumeratedValue>
12055                <enumeratedValue>
12056                  <name>RANGE3</name>
12057                  <description>Target frequency is in range [113, 150) MHz</description>
12058                  <value>3</value>
12059                </enumeratedValue>
12060                <enumeratedValue>
12061                  <name>RANGE4</name>
12062                  <description>Target frequency is in range [150, 200] MHz</description>
12063                  <value>4</value>
12064                </enumeratedValue>
12065              </enumeratedValues>
12066            </field>
12067            <field>
12068              <name>CCO_FREQ</name>
12069              <description>CCO frequency code.  This is updated by HW when the FLL is enabled.  It can be manually updated to use the CCO in an open loop configuration.  The meaning of each frequency code depends on the range.</description>
12070              <bitRange>[24:16]</bitRange>
12071              <access>read-write</access>
12072            </field>
12073            <field>
12074              <name>CCO_HW_UPDATE_DIS</name>
12075              <description>Disable CCO frequency update by FLL hardware
120760: Hardware update of CCO settings is allowed.  Use this setting for normal FLL operation.
120771: Hardware update of CCO settings is disabled.  Use this setting for open-loop FLL operation.</description>
12078              <bitRange>[30:30]</bitRange>
12079              <access>read-write</access>
12080            </field>
12081            <field>
12082              <name>CCO_ENABLE</name>
12083              <description>Enable the CCO.  It is required to enable the CCO before using the FLL.
120840: Block is powered off
120851: Block is powered on</description>
12086              <bitRange>[31:31]</bitRange>
12087              <access>read-write</access>
12088            </field>
12089          </fields>
12090        </register>
12091        <register>
12092          <name>CLK_FLL_STATUS</name>
12093          <description>FLL Status Register</description>
12094          <addressOffset>0x590</addressOffset>
12095          <size>32</size>
12096          <access>read-write</access>
12097          <resetValue>0x0</resetValue>
12098          <resetMask>0x7</resetMask>
12099          <fields>
12100            <field>
12101              <name>LOCKED</name>
12102              <description>FLL Lock Indicator.  LOCKED is high when FLL is within CLK_FLL_CONFIG2.LOCK_TOL.  If FLL is outside LOCK_TOL, LOCKED goes low.  Note that this can happen during normal operation, if FLL needs to recalculate due to a change in the reference clock, change in voltage, or change in temperature.</description>
12103              <bitRange>[0:0]</bitRange>
12104              <access>read-only</access>
12105            </field>
12106            <field>
12107              <name>UNLOCK_OCCURRED</name>
12108              <description>N/A</description>
12109              <bitRange>[1:1]</bitRange>
12110              <access>read-write</access>
12111            </field>
12112            <field>
12113              <name>CCO_READY</name>
12114              <description>This indicates that the CCO is internally settled and ready to use.</description>
12115              <bitRange>[2:2]</bitRange>
12116              <access>read-only</access>
12117            </field>
12118          </fields>
12119        </register>
12120        <register>
12121          <dim>15</dim>
12122          <dimIncrement>4</dimIncrement>
12123          <name>CLK_PLL_CONFIG[%s]</name>
12124          <description>PLL Configuration Register</description>
12125          <addressOffset>0x600</addressOffset>
12126          <size>32</size>
12127          <access>read-write</access>
12128          <resetValue>0x20116</resetValue>
12129          <resetMask>0xB81F1F7F</resetMask>
12130          <fields>
12131            <field>
12132              <name>FEEDBACK_DIV</name>
12133              <description>Control bits for feedback divider.  Set the divide value before enabling the PLL, and do not change it while PLL is enabled.
121340-21: illegal (undefined behavior)
1213522: divide by 22
12136...
12137112: divide by 112
12138&gt;112: illegal (undefined behavior)</description>
12139              <bitRange>[6:0]</bitRange>
12140              <access>read-write</access>
12141            </field>
12142            <field>
12143              <name>REFERENCE_DIV</name>
12144              <description>Control bits for reference divider.  Set the divide value before enabling the PLL, and do not change it while PLL is enabled.
121450: illegal (undefined behavior)
121461: divide by 1
12147...
1214820: divide by 20
12149others: illegal (undefined behavior)</description>
12150              <bitRange>[12:8]</bitRange>
12151              <access>read-write</access>
12152            </field>
12153            <field>
12154              <name>OUTPUT_DIV</name>
12155              <description>Control bits for Output divider.  Set the divide value before enabling the PLL, and do not change it while PLL is enabled.
121560: illegal (undefined behavior)
121571: illegal (undefined behavior)
121582: divide by 2.  Suitable for direct usage as HFCLK source.
12159...
1216016: divide by 16.  Suitable for direct usage as HFCLK source.
12161&gt;16: illegal (undefined behavior)</description>
12162              <bitRange>[20:16]</bitRange>
12163              <access>read-write</access>
12164            </field>
12165            <field>
12166              <name>PLL_LF_MODE</name>
12167              <description>VCO frequency range selection.  Configure this bit according to the targeted VCO frequency.  Do not change this setting while the PLL is enabled.
121680: VCO frequency is [200MHz, 400MHz]
121691: VCO frequency is [170MHz, 200MHz)</description>
12170              <bitRange>[27:27]</bitRange>
12171              <access>read-write</access>
12172            </field>
12173            <field>
12174              <name>BYPASS_SEL</name>
12175              <description>Bypass mux located just after PLL output.  This selection is glitch-free and can be changed while the PLL is running.</description>
12176              <bitRange>[29:28]</bitRange>
12177              <access>read-write</access>
12178              <enumeratedValues>
12179                <enumeratedValue>
12180                  <name>AUTO</name>
12181                  <description>Automatic using lock indicator.  When unlocked, automatically selects PLL reference input (bypass mode).  When locked, automatically selects PLL output.</description>
12182                  <value>0</value>
12183                </enumeratedValue>
12184                <enumeratedValue>
12185                  <name>AUTO1</name>
12186                  <description>Same as AUTO</description>
12187                  <value>1</value>
12188                </enumeratedValue>
12189                <enumeratedValue>
12190                  <name>PLL_REF</name>
12191                  <description>Select PLL reference input (bypass mode).  Ignores lock indicator</description>
12192                  <value>2</value>
12193                </enumeratedValue>
12194                <enumeratedValue>
12195                  <name>PLL_OUT</name>
12196                  <description>Select PLL output.  Ignores lock indicator.</description>
12197                  <value>3</value>
12198                </enumeratedValue>
12199              </enumeratedValues>
12200            </field>
12201            <field>
12202              <name>ENABLE</name>
12203              <description>Master enable for PLL.  Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1.  To disable the PLL, first deselect it using .BYPASS_SEL=PLL_REF, wait at least six PLL clock cycles, and then disable it with .ENABLE=0.
12204
12205Fpll = (FEEDBACK_DIV)  * (Fref / REFERENCE_DIV) / (OUTPUT_DIV)
12206
122070: Block is disabled
122081: Block is enabled</description>
12209              <bitRange>[31:31]</bitRange>
12210              <access>read-write</access>
12211            </field>
12212          </fields>
12213        </register>
12214        <register>
12215          <dim>15</dim>
12216          <dimIncrement>4</dimIncrement>
12217          <name>CLK_PLL_STATUS[%s]</name>
12218          <description>PLL Status Register</description>
12219          <addressOffset>0x640</addressOffset>
12220          <size>32</size>
12221          <access>read-write</access>
12222          <resetValue>0x0</resetValue>
12223          <resetMask>0x3</resetMask>
12224          <fields>
12225            <field>
12226              <name>LOCKED</name>
12227              <description>PLL Lock Indicator</description>
12228              <bitRange>[0:0]</bitRange>
12229              <access>read-only</access>
12230            </field>
12231            <field>
12232              <name>UNLOCK_OCCURRED</name>
12233              <description>This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware.</description>
12234              <bitRange>[1:1]</bitRange>
12235              <access>read-write</access>
12236            </field>
12237          </fields>
12238        </register>
12239        <register>
12240          <name>SRSS_INTR</name>
12241          <description>SRSS Interrupt Register</description>
12242          <addressOffset>0x700</addressOffset>
12243          <size>32</size>
12244          <access>read-write</access>
12245          <resetValue>0x0</resetValue>
12246          <resetMask>0x23</resetMask>
12247          <fields>
12248            <field>
12249              <name>WDT_MATCH</name>
12250              <description>WDT Interrupt Request.  This bit is set each time WDT_COUNTR==WDT_MATCH.  W1C also feeds the watch dog.  Missing 2 interrupts in a row will generate a reset.  Due to internal synchronization, it takes 2 SYSCLK cycles to update after a W1C.</description>
12251              <bitRange>[0:0]</bitRange>
12252              <access>read-write</access>
12253            </field>
12254            <field>
12255              <name>HVLVD1</name>
12256              <description>Interrupt for low voltage detector HVLVD1</description>
12257              <bitRange>[1:1]</bitRange>
12258              <access>read-write</access>
12259            </field>
12260            <field>
12261              <name>CLK_CAL</name>
12262              <description>Clock calibration counter is done.  This field is reset during DEEPSLEEP mode.</description>
12263              <bitRange>[5:5]</bitRange>
12264              <access>read-write</access>
12265            </field>
12266          </fields>
12267        </register>
12268        <register>
12269          <name>SRSS_INTR_SET</name>
12270          <description>SRSS Interrupt Set Register</description>
12271          <addressOffset>0x704</addressOffset>
12272          <size>32</size>
12273          <access>read-write</access>
12274          <resetValue>0x0</resetValue>
12275          <resetMask>0x23</resetMask>
12276          <fields>
12277            <field>
12278              <name>WDT_MATCH</name>
12279              <description>Set interrupt for low voltage detector WDT_MATCH</description>
12280              <bitRange>[0:0]</bitRange>
12281              <access>read-write</access>
12282            </field>
12283            <field>
12284              <name>HVLVD1</name>
12285              <description>Set interrupt for low voltage detector HVLVD1</description>
12286              <bitRange>[1:1]</bitRange>
12287              <access>read-write</access>
12288            </field>
12289            <field>
12290              <name>CLK_CAL</name>
12291              <description>Set interrupt for clock calibration counter done.  This field is reset during DEEPSLEEP mode.</description>
12292              <bitRange>[5:5]</bitRange>
12293              <access>read-write</access>
12294            </field>
12295          </fields>
12296        </register>
12297        <register>
12298          <name>SRSS_INTR_MASK</name>
12299          <description>SRSS Interrupt Mask Register</description>
12300          <addressOffset>0x708</addressOffset>
12301          <size>32</size>
12302          <access>read-write</access>
12303          <resetValue>0x0</resetValue>
12304          <resetMask>0x23</resetMask>
12305          <fields>
12306            <field>
12307              <name>WDT_MATCH</name>
12308              <description>Mask for watchdog timer.  Clearing this bit will not forward the interrupt to the CPU.  It will not, however, disable the WDT reset generation on 2 missed interrupts.  When WDT resets the chip, it also internally pends an interrupt that survives the reset.  To prevent unintended ISR execution, clear SRSS_INTR.WDT_MATCH before setting this bit.</description>
12309              <bitRange>[0:0]</bitRange>
12310              <access>read-write</access>
12311            </field>
12312            <field>
12313              <name>HVLVD1</name>
12314              <description>Mask for low voltage detector HVLVD1</description>
12315              <bitRange>[1:1]</bitRange>
12316              <access>read-write</access>
12317            </field>
12318            <field>
12319              <name>CLK_CAL</name>
12320              <description>Mask for clock calibration done</description>
12321              <bitRange>[5:5]</bitRange>
12322              <access>read-write</access>
12323            </field>
12324          </fields>
12325        </register>
12326        <register>
12327          <name>SRSS_INTR_MASKED</name>
12328          <description>SRSS Interrupt Masked Register</description>
12329          <addressOffset>0x70C</addressOffset>
12330          <size>32</size>
12331          <access>read-only</access>
12332          <resetValue>0x0</resetValue>
12333          <resetMask>0x23</resetMask>
12334          <fields>
12335            <field>
12336              <name>WDT_MATCH</name>
12337              <description>Logical and of corresponding request and mask bits.</description>
12338              <bitRange>[0:0]</bitRange>
12339              <access>read-only</access>
12340            </field>
12341            <field>
12342              <name>HVLVD1</name>
12343              <description>Logical and of corresponding request and mask bits.</description>
12344              <bitRange>[1:1]</bitRange>
12345              <access>read-only</access>
12346            </field>
12347            <field>
12348              <name>CLK_CAL</name>
12349              <description>Logical and of corresponding request and mask bits.</description>
12350              <bitRange>[5:5]</bitRange>
12351              <access>read-only</access>
12352            </field>
12353          </fields>
12354        </register>
12355        <register>
12356          <name>SRSS_INTR_CFG</name>
12357          <description>SRSS Interrupt Configuration Register</description>
12358          <addressOffset>0x710</addressOffset>
12359          <size>32</size>
12360          <access>read-write</access>
12361          <resetValue>0x0</resetValue>
12362          <resetMask>0x3</resetMask>
12363          <fields>
12364            <field>
12365              <name>HVLVD1_EDGE_SEL</name>
12366              <description>Sets which edge(s) will trigger an IRQ for HVLVD1</description>
12367              <bitRange>[1:0]</bitRange>
12368              <access>read-write</access>
12369              <enumeratedValues>
12370                <enumeratedValue>
12371                  <name>DISABLE</name>
12372                  <description>Disabled</description>
12373                  <value>0</value>
12374                </enumeratedValue>
12375                <enumeratedValue>
12376                  <name>RISING</name>
12377                  <description>Rising edge</description>
12378                  <value>1</value>
12379                </enumeratedValue>
12380                <enumeratedValue>
12381                  <name>FALLING</name>
12382                  <description>Falling edge</description>
12383                  <value>2</value>
12384                </enumeratedValue>
12385                <enumeratedValue>
12386                  <name>BOTH</name>
12387                  <description>Both rising and falling edges</description>
12388                  <value>3</value>
12389                </enumeratedValue>
12390              </enumeratedValues>
12391            </field>
12392          </fields>
12393        </register>
12394        <register>
12395          <name>RES_CAUSE</name>
12396          <description>Reset Cause Observation Register</description>
12397          <addressOffset>0x800</addressOffset>
12398          <size>32</size>
12399          <access>read-write</access>
12400          <resetValue>0x0</resetValue>
12401          <resetMask>0x1FF</resetMask>
12402          <fields>
12403            <field>
12404              <name>RESET_WDT</name>
12405              <description>A basic WatchDog Timer (WDT) reset has occurred since last power cycle.</description>
12406              <bitRange>[0:0]</bitRange>
12407              <access>read-write</access>
12408            </field>
12409            <field>
12410              <name>RESET_ACT_FAULT</name>
12411              <description>Fault logging system requested a reset from its Active logic.</description>
12412              <bitRange>[1:1]</bitRange>
12413              <access>read-write</access>
12414            </field>
12415            <field>
12416              <name>RESET_DPSLP_FAULT</name>
12417              <description>Fault logging system requested a reset from its DeepSleep logic.</description>
12418              <bitRange>[2:2]</bitRange>
12419              <access>read-write</access>
12420            </field>
12421            <field>
12422              <name>RESET_CSV_WCO_LOSS</name>
12423              <description>Clock supervision logic requested a reset due to loss of a watch-crystal clock.</description>
12424              <bitRange>[3:3]</bitRange>
12425              <access>read-write</access>
12426            </field>
12427            <field>
12428              <name>RESET_SOFT</name>
12429              <description>A CPU requested a system reset through it's SYSRESETREQ.  This can be done via a debugger probe or in firmware.</description>
12430              <bitRange>[4:4]</bitRange>
12431              <access>read-write</access>
12432            </field>
12433            <field>
12434              <name>RESET_MCWDT0</name>
12435              <description>Multi-Counter Watchdog timer reset #0 has occurred since last power cycle.</description>
12436              <bitRange>[5:5]</bitRange>
12437              <access>read-write</access>
12438            </field>
12439            <field>
12440              <name>RESET_MCWDT1</name>
12441              <description>Multi-Counter Watchdog timer reset #1 has occurred since last power cycle.</description>
12442              <bitRange>[6:6]</bitRange>
12443              <access>read-write</access>
12444            </field>
12445            <field>
12446              <name>RESET_MCWDT2</name>
12447              <description>Multi-Counter Watchdog timer reset #2 has occurred since last power cycle.</description>
12448              <bitRange>[7:7]</bitRange>
12449              <access>read-write</access>
12450            </field>
12451            <field>
12452              <name>RESET_MCWDT3</name>
12453              <description>Multi-Counter Watchdog timer reset #3 has occurred since last power cycle.</description>
12454              <bitRange>[8:8]</bitRange>
12455              <access>read-write</access>
12456            </field>
12457          </fields>
12458        </register>
12459        <register>
12460          <name>RES_CAUSE2</name>
12461          <description>Reset Cause Observation Register 2</description>
12462          <addressOffset>0x804</addressOffset>
12463          <size>32</size>
12464          <access>read-write</access>
12465          <resetValue>0x0</resetValue>
12466          <resetMask>0xFFFFFFFF</resetMask>
12467          <fields>
12468            <field>
12469              <name>RESET_CSV_HF_LOSS</name>
12470              <description>Clock supervision logic requested a reset due to loss of a high-frequency clock.  Each bit index K corresponds to a HFCLK&lt;K&gt;.  Unimplemented clock bits return zero.</description>
12471              <bitRange>[15:0]</bitRange>
12472              <access>read-write</access>
12473            </field>
12474            <field>
12475              <name>RESET_CSV_HF_FREQ</name>
12476              <description>Clock supervision logic requested a reset due to frequency error of high-frequency clock.  Each bit index K corresponds to a HFCLK&lt;K&gt;.  Unimplemented clock bits return zero.</description>
12477              <bitRange>[31:16]</bitRange>
12478              <access>read-write</access>
12479            </field>
12480          </fields>
12481        </register>
12482        <register>
12483          <name>PWR_TRIM_REF_CTL</name>
12484          <description>Reference Trim Register</description>
12485          <addressOffset>0x7F00</addressOffset>
12486          <size>32</size>
12487          <access>read-write</access>
12488          <resetValue>0x70F00000</resetValue>
12489          <resetMask>0xF1FF5FFF</resetMask>
12490          <fields>
12491            <field>
12492              <name>ACT_REF_TCTRIM</name>
12493              <description>Active-Reference temperature trim.  This register is only reset by XRES/POR/BOD/HIBERNATE.
124940 -&gt; default setting at POR; not for trimming use
12495others -&gt; normal trim range</description>
12496              <bitRange>[3:0]</bitRange>
12497              <access>read-write</access>
12498            </field>
12499            <field>
12500              <name>ACT_REF_ITRIM</name>
12501              <description>Active-Reference current trim.   This register is only reset by XRES/POR/BOD/HIBERNATE.
125020 -&gt; default setting at POR; not for trimming use
12503others -&gt; normal trim range</description>
12504              <bitRange>[7:4]</bitRange>
12505              <access>read-write</access>
12506            </field>
12507            <field>
12508              <name>ACT_REF_ABSTRIM</name>
12509              <description>Active-Reference absolute voltage trim.  This register is only reset by XRES/POR/BOD/HIBERNATE.
125100 -&gt; default setting at POR; not for trimming use
12511others -&gt; normal trim range</description>
12512              <bitRange>[12:8]</bitRange>
12513              <access>read-write</access>
12514            </field>
12515            <field>
12516              <name>ACT_REF_IBOOST</name>
12517              <description>Active-Reference current boost.   This register is only reset by XRES/POR/BOD/HIBERNATE.
125180: normal operation
12519others: risk mitigation</description>
12520              <bitRange>[14:14]</bitRange>
12521              <access>read-write</access>
12522            </field>
12523            <field>
12524              <name>DPSLP_REF_TCTRIM</name>
12525              <description>DeepSleep-Reference temperature trim.  This register is only reset by XRES/POR/BOD/HIBERNATE.
125260 -&gt; default setting at POR; not for trimming use
12527others -&gt; normal trim range</description>
12528              <bitRange>[19:16]</bitRange>
12529              <access>read-write</access>
12530            </field>
12531            <field>
12532              <name>DPSLP_REF_ABSTRIM</name>
12533              <description>DeepSleep-Reference absolute voltage trim.  This register is only reset by XRES/POR/BOD/HIBERNATE.</description>
12534              <bitRange>[24:20]</bitRange>
12535              <access>read-write</access>
12536            </field>
12537            <field>
12538              <name>DPSLP_REF_ITRIM</name>
12539              <description>DeepSleep current reference trim.   This register is only reset by XRES/POR/BOD/HIBERNATE.</description>
12540              <bitRange>[31:28]</bitRange>
12541              <access>read-write</access>
12542            </field>
12543          </fields>
12544        </register>
12545        <register>
12546          <name>PWR_TRIM_BODOVP_CTL</name>
12547          <description>BOD/OVP Trim Register</description>
12548          <addressOffset>0x7F04</addressOffset>
12549          <size>32</size>
12550          <access>read-write</access>
12551          <resetValue>0x40D04</resetValue>
12552          <resetMask>0xFDFF7</resetMask>
12553          <fields>
12554            <field>
12555              <name>HVPORBOD_TRIPSEL</name>
12556              <description>HVPORBOD trip point selection.  Monitors vddd.  This register is only reset by XRES/POR/BOD/HIBERNATE.</description>
12557              <bitRange>[2:0]</bitRange>
12558              <access>read-write</access>
12559            </field>
12560            <field>
12561              <name>HVPORBOD_OFSTRIM</name>
12562              <description>HVPORBOD offset trim.  This register is only reset by XRES/POR/BOD/HIBERNATE.</description>
12563              <bitRange>[6:4]</bitRange>
12564              <access>read-write</access>
12565            </field>
12566            <field>
12567              <name>HVPORBOD_ITRIM</name>
12568              <description>HVPORBOD current trim.  This register is only reset by XRES/POR/BOD/HIBERNATE.</description>
12569              <bitRange>[9:7]</bitRange>
12570              <access>read-write</access>
12571            </field>
12572            <field>
12573              <name>LVPORBOD_TRIPSEL</name>
12574              <description>LVPORBOD trip point selection.  Monitors vccd.  This register is only reset by XRES/POR/BOD/HIBERNATE.</description>
12575              <bitRange>[12:10]</bitRange>
12576              <access>read-write</access>
12577            </field>
12578            <field>
12579              <name>LVPORBOD_OFSTRIM</name>
12580              <description>LVPORBOD offset trim.  This register is only reset by XRES/POR/BOD/HIBERNATE.</description>
12581              <bitRange>[16:14]</bitRange>
12582              <access>read-write</access>
12583            </field>
12584            <field>
12585              <name>LVPORBOD_ITRIM</name>
12586              <description>LVPORBOD current trim.  This register is only reset by XRES/POR/BOD/HIBERNATE.</description>
12587              <bitRange>[19:17]</bitRange>
12588              <access>read-write</access>
12589            </field>
12590          </fields>
12591        </register>
12592        <register>
12593          <name>CLK_TRIM_CCO_CTL</name>
12594          <description>CCO Trim Register</description>
12595          <addressOffset>0x7F08</addressOffset>
12596          <size>32</size>
12597          <access>read-write</access>
12598          <resetValue>0xA7000020</resetValue>
12599          <resetMask>0xBF00003F</resetMask>
12600          <fields>
12601            <field>
12602              <name>CCO_RCSTRIM</name>
12603              <description>CCO reference current source trim.</description>
12604              <bitRange>[5:0]</bitRange>
12605              <access>read-write</access>
12606            </field>
12607            <field>
12608              <name>CCO_STABLE_CNT</name>
12609              <description>Terminal count for the stabilization counter from CCO_ENABLE until stable.</description>
12610              <bitRange>[29:24]</bitRange>
12611              <access>read-write</access>
12612            </field>
12613            <field>
12614              <name>ENABLE_CNT</name>
12615              <description>Enables the automatic stabilization counter.</description>
12616              <bitRange>[31:31]</bitRange>
12617              <access>read-write</access>
12618            </field>
12619          </fields>
12620        </register>
12621        <register>
12622          <name>CLK_TRIM_CCO_CTL2</name>
12623          <description>CCO Trim Register 2</description>
12624          <addressOffset>0x7F0C</addressOffset>
12625          <size>32</size>
12626          <access>read-write</access>
12627          <resetValue>0x884110</resetValue>
12628          <resetMask>0x1FFFFFF</resetMask>
12629          <fields>
12630            <field>
12631              <name>CCO_FCTRIM1</name>
12632              <description>CCO frequency 1st range calibration</description>
12633              <bitRange>[4:0]</bitRange>
12634              <access>read-write</access>
12635            </field>
12636            <field>
12637              <name>CCO_FCTRIM2</name>
12638              <description>CCO frequency 2nd range calibration</description>
12639              <bitRange>[9:5]</bitRange>
12640              <access>read-write</access>
12641            </field>
12642            <field>
12643              <name>CCO_FCTRIM3</name>
12644              <description>CCO frequency 3rd range calibration</description>
12645              <bitRange>[14:10]</bitRange>
12646              <access>read-write</access>
12647            </field>
12648            <field>
12649              <name>CCO_FCTRIM4</name>
12650              <description>CCO frequency 4th range calibration</description>
12651              <bitRange>[19:15]</bitRange>
12652              <access>read-write</access>
12653            </field>
12654            <field>
12655              <name>CCO_FCTRIM5</name>
12656              <description>CCO frequency 5th range calibration</description>
12657              <bitRange>[24:20]</bitRange>
12658              <access>read-write</access>
12659            </field>
12660          </fields>
12661        </register>
12662        <register>
12663          <name>PWR_TRIM_WAKE_CTL</name>
12664          <description>Wakeup Trim Register</description>
12665          <addressOffset>0x7F30</addressOffset>
12666          <size>32</size>
12667          <access>read-write</access>
12668          <resetValue>0x0</resetValue>
12669          <resetMask>0xFF</resetMask>
12670          <fields>
12671            <field>
12672              <name>WAKE_DELAY</name>
12673              <description>Wakeup holdoff.  Spec (fastest) wake time is achieved with a setting of 0.  Additional delay can be added for debugging or workaround.  The delay is counted by the IMO.</description>
12674              <bitRange>[7:0]</bitRange>
12675              <access>read-write</access>
12676            </field>
12677          </fields>
12678        </register>
12679        <register>
12680          <name>PWR_TRIM_LVD_CTL</name>
12681          <description>LVD Trim Register</description>
12682          <addressOffset>0xFF10</addressOffset>
12683          <size>32</size>
12684          <access>read-write</access>
12685          <resetValue>0x20</resetValue>
12686          <resetMask>0x77</resetMask>
12687          <fields>
12688            <field>
12689              <name>HVLVD1_OFSTRIM</name>
12690              <description>HVLVD1 offset trim</description>
12691              <bitRange>[2:0]</bitRange>
12692              <access>read-write</access>
12693            </field>
12694            <field>
12695              <name>HVLVD1_ITRIM</name>
12696              <description>HVLVD1 current trim</description>
12697              <bitRange>[6:4]</bitRange>
12698              <access>read-write</access>
12699            </field>
12700          </fields>
12701        </register>
12702        <register>
12703          <name>CLK_TRIM_ILO_CTL</name>
12704          <description>ILO Trim Register</description>
12705          <addressOffset>0xFF18</addressOffset>
12706          <size>32</size>
12707          <access>read-write</access>
12708          <resetValue>0x2C</resetValue>
12709          <resetMask>0x3F</resetMask>
12710          <fields>
12711            <field>
12712              <name>ILO_FTRIM</name>
12713              <description>ILO frequency trims.  LSB step size is 1.5 percent (typical) of the frequency.</description>
12714              <bitRange>[5:0]</bitRange>
12715              <access>read-write</access>
12716            </field>
12717          </fields>
12718        </register>
12719        <register>
12720          <name>PWR_TRIM_PWRSYS_CTL</name>
12721          <description>Power System Trim Register</description>
12722          <addressOffset>0xFF1C</addressOffset>
12723          <size>32</size>
12724          <access>read-write</access>
12725          <resetValue>0x17</resetValue>
12726          <resetMask>0x1F</resetMask>
12727          <fields>
12728            <field>
12729              <name>ACT_REG_TRIM</name>
12730              <description>Trim for the Active-Regulator.  This sets the output voltage level.  This register is only reset by XRES/POR/BOD/HIBERNATE.  The nominal output voltage is vccd=812.5mV + ACT_REG_TRIM*12.5mV.  The actual output voltage will vary depending on conditions and load.  The following settings are explicitly shown for convenience, and other values may be calculated using the formula:
127315'h07: 900mV (nominal)
127325'h17: 1100mV (nominal)</description>
12733              <bitRange>[4:0]</bitRange>
12734              <access>read-write</access>
12735            </field>
12736            <field>
12737              <name>ACT_REG_BOOST</name>
12738              <description>Controls the tradeoff between output current and internal operating current for the Active Regulator.  The maximum output current depends on the silicon implementation, but an application may limit its maximum current to less than that.  This may allow a reduction in the internal operating current of the regulator.  The regulator internal operating current depends on the boost setting:
127392'b00: 50uA
127402'b01: 100uA
127412'b10: 150uA
127422'b11: 200uA
12743
12744The allowed setting is a lookup table based on the chip-specific maximum (set in factory) and an application-specific maximum (set by customer).  The defaults are set assuming the application consumes the maximum allowed by the chip.
1274550mA chip: 2'b00 (default);
12746100mA chip: 2'b00 (default);
12747150mA chip: 50..100mA app =&gt; 2'b00, 150mA app =&gt; 2'b01 (default);
12748200mA chip: 50mA app =&gt; 2'b00, 100..150mA app =&gt; 2'b01,  200mA app =&gt; 2'b10 (default);
12749250mA chip: 50mA app =&gt; 2'b00, 100..150mA app =&gt; 2'b01,  200..250mA app =&gt; 2'b10 (default);
12750300mA chip: 50mA app =&gt; 2'b00, 100..150mA app =&gt; 2'b01, 200..250mA app =&gt; 2'b10, 300mA app =&gt; 2'b11 (default);
12751
12752This register is only reset by XRES/POR/BOD/HIBERNATE.</description>
12753              <bitRange>[31:30]</bitRange>
12754              <access>read-write</access>
12755            </field>
12756          </fields>
12757        </register>
12758        <register>
12759          <name>CLK_TRIM_ECO_CTL</name>
12760          <description>ECO Trim Register</description>
12761          <addressOffset>0xFF20</addressOffset>
12762          <size>32</size>
12763          <access>read-write</access>
12764          <resetValue>0x1F0003</resetValue>
12765          <resetMask>0x3F3FF7</resetMask>
12766          <fields>
12767            <field>
12768              <name>WDTRIM</name>
12769              <description>Watch Dog Trim -  Delta voltage below steady state level
127700x0 - 50mV
127710x1 - 75mV
127720x2 - 100mV
127730x3 - 125mV
127740x4 - 150mV
127750x5 - 175mV
127760x6 - 200mV
127770x7 - 225mV</description>
12778              <bitRange>[2:0]</bitRange>
12779              <access>read-write</access>
12780            </field>
12781            <field>
12782              <name>ATRIM</name>
12783              <description>Amplitude trim to set the crystal drive level when ECO_CONFIG.AGC_EN=1.  WARNING: use care when setting this field because driving a crystal beyond its rated limit can permanently damage the crystal.
127840x0 - 150mV
127850x1 - 175mV
127860x2 - 200mV
127870x3 - 225mV
127880x4 - 250mV
127890x5 - 275mV
127900x6 - 300mV
127910x7 - 325mV
127920x8 - 350mV
127930x9 - 375mV
127940xA - 400mV
127950xB - 425mV
127960xC - 450mV
127970xD - 475mV
127980xE - 500mV
127990xF - 525mV</description>
12800              <bitRange>[7:4]</bitRange>
12801              <access>read-write</access>
12802            </field>
12803            <field>
12804              <name>FTRIM</name>
12805              <description>Filter Trim - 3rd harmonic oscillation</description>
12806              <bitRange>[9:8]</bitRange>
12807              <access>read-write</access>
12808            </field>
12809            <field>
12810              <name>RTRIM</name>
12811              <description>Feedback resistor Trim</description>
12812              <bitRange>[11:10]</bitRange>
12813              <access>read-write</access>
12814            </field>
12815            <field>
12816              <name>GTRIM</name>
12817              <description>Gain Trim - Startup time</description>
12818              <bitRange>[13:12]</bitRange>
12819              <access>read-write</access>
12820            </field>
12821            <field>
12822              <name>ITRIM</name>
12823              <description>Current Trim</description>
12824              <bitRange>[21:16]</bitRange>
12825              <access>read-write</access>
12826            </field>
12827          </fields>
12828        </register>
12829        <register>
12830          <name>CLK_TRIM_PILO_CTL</name>
12831          <description>PILO Trim Register</description>
12832          <addressOffset>0xFF24</addressOffset>
12833          <size>32</size>
12834          <access>read-write</access>
12835          <resetValue>0x108500F</resetValue>
12836          <resetMask>0x7DFF703F</resetMask>
12837          <fields>
12838            <field>
12839              <name>PILO_CFREQ</name>
12840              <description>Coarse frequency trim to meet 32.768kHz +/-2 percent across PVT without calibration.  The nominal step size of the LSB is 1kHz.</description>
12841              <bitRange>[5:0]</bitRange>
12842              <access>read-write</access>
12843            </field>
12844            <field>
12845              <name>PILO_OSC_TRIM</name>
12846              <description>Trim for current in oscillator block.</description>
12847              <bitRange>[14:12]</bitRange>
12848              <access>read-write</access>
12849            </field>
12850            <field>
12851              <name>PILO_COMP_TRIM</name>
12852              <description>Trim for comparator bias current.</description>
12853              <bitRange>[17:16]</bitRange>
12854              <access>read-write</access>
12855            </field>
12856            <field>
12857              <name>PILO_NBIAS_TRIM</name>
12858              <description>Trim for biasn by trimming sub-Vth NMOS width in beta-multiplier</description>
12859              <bitRange>[19:18]</bitRange>
12860              <access>read-write</access>
12861            </field>
12862            <field>
12863              <name>PILO_RES_TRIM</name>
12864              <description>Trim for beta-multiplier branch current</description>
12865              <bitRange>[24:20]</bitRange>
12866              <access>read-write</access>
12867            </field>
12868            <field>
12869              <name>PILO_ISLOPE_TRIM</name>
12870              <description>Trim for beta-multiplier current slope</description>
12871              <bitRange>[27:26]</bitRange>
12872              <access>read-write</access>
12873            </field>
12874            <field>
12875              <name>PILO_VTDIFF_TRIM</name>
12876              <description>Trim for VT-DIFF output (internal power supply)</description>
12877              <bitRange>[30:28]</bitRange>
12878              <access>read-write</access>
12879            </field>
12880          </fields>
12881        </register>
12882        <register>
12883          <name>CLK_TRIM_PILO_CTL2</name>
12884          <description>PILO Trim Register 2</description>
12885          <addressOffset>0xFF28</addressOffset>
12886          <size>32</size>
12887          <access>read-write</access>
12888          <resetValue>0xDA10E0</resetValue>
12889          <resetMask>0xFF1FFF</resetMask>
12890          <fields>
12891            <field>
12892              <name>PILO_VREF_TRIM</name>
12893              <description>Trim for voltage reference</description>
12894              <bitRange>[7:0]</bitRange>
12895              <access>read-write</access>
12896            </field>
12897            <field>
12898              <name>PILO_IREFBM_TRIM</name>
12899              <description>Trim for beta-multiplier current reference</description>
12900              <bitRange>[12:8]</bitRange>
12901              <access>read-write</access>
12902            </field>
12903            <field>
12904              <name>PILO_IREF_TRIM</name>
12905              <description>Trim for current reference</description>
12906              <bitRange>[23:16]</bitRange>
12907              <access>read-write</access>
12908            </field>
12909          </fields>
12910        </register>
12911        <register>
12912          <name>CLK_TRIM_PILO_CTL3</name>
12913          <description>PILO Trim Register 3</description>
12914          <addressOffset>0xFF2C</addressOffset>
12915          <size>32</size>
12916          <access>read-write</access>
12917          <resetValue>0x4800</resetValue>
12918          <resetMask>0xFFFF</resetMask>
12919          <fields>
12920            <field>
12921              <name>PILO_ENGOPT</name>
12922              <description>Engineering options for PILO circuits
129230: Short vdda to vpwr
129241: Beta:mult current change
129252: Iref generation Ptat current addition
129263: Disable current path in secondary Beta:mult startup circuit
129274: Double oscillator current
129285: Switch between deep:sub:threshold and sub:threshold stacks in Vref generation block
129296: Spare
129307: Ptat component increase in Iref
129318: vpwr_rc and vpwr_dig_rc shorting testmode
129329: Switch b/w psub connection for cascode nfet for vref generation
1293310: Switch between sub:threshold and deep:sub:threshold stacks in comparator.
1293415-11: Frequency fine trim.  See AKK-444 for an overview of the trim strategy.</description>
12935              <bitRange>[15:0]</bitRange>
12936              <access>read-write</access>
12937            </field>
12938          </fields>
12939        </register>
12940      </registers>
12941    </peripheral>
12942    <peripheral>
12943      <name>DW0</name>
12944      <description>Datawire Controller</description>
12945      <headerStructName>DW</headerStructName>
12946      <baseAddress>0x40280000</baseAddress>
12947      <addressBlock>
12948        <offset>0</offset>
12949        <size>65536</size>
12950        <usage>registers</usage>
12951      </addressBlock>
12952      <registers>
12953        <register>
12954          <name>CTL</name>
12955          <description>Control</description>
12956          <addressOffset>0x0</addressOffset>
12957          <size>32</size>
12958          <access>read-write</access>
12959          <resetValue>0x1</resetValue>
12960          <resetMask>0x80000003</resetMask>
12961          <fields>
12962            <field>
12963              <name>ECC_EN</name>
12964              <description>Enable ECC checking:
12965'0': Disabled.
12966'1': Enabled.</description>
12967              <bitRange>[0:0]</bitRange>
12968              <access>read-write</access>
12969            </field>
12970            <field>
12971              <name>ECC_INJ_EN</name>
12972              <description>Enable parity injection for SRAM.
12973When '1', the parity (ECC_CTL.PARITY) is used when a full 32-bit write is done to the ECC_CTL.WORD_ADDR word address of the SRAM.</description>
12974              <bitRange>[1:1]</bitRange>
12975              <access>read-write</access>
12976            </field>
12977            <field>
12978              <name>ENABLED</name>
12979              <description>IP enable:
12980'0': Disabled. Disabling the IP activates the IP's Active logic reset: Active logic and non-retention MMIO registers are reset (retention MMIO registers are not affected).
12981'1': Enabled.</description>
12982              <bitRange>[31:31]</bitRange>
12983              <access>read-write</access>
12984            </field>
12985          </fields>
12986        </register>
12987        <register>
12988          <name>STATUS</name>
12989          <description>Status</description>
12990          <addressOffset>0x4</addressOffset>
12991          <size>32</size>
12992          <access>read-only</access>
12993          <resetValue>0x0</resetValue>
12994          <resetMask>0xF0000000</resetMask>
12995          <fields>
12996            <field>
12997              <name>P</name>
12998              <description>Active channel, user/privileged access control:
12999'0': user mode.
13000'1': privileged mode.</description>
13001              <bitRange>[0:0]</bitRange>
13002              <access>read-only</access>
13003            </field>
13004            <field>
13005              <name>NS</name>
13006              <description>Active channel, secure/non-secure access control:
13007'0': secure.
13008'1': non-secure.</description>
13009              <bitRange>[1:1]</bitRange>
13010              <access>read-only</access>
13011            </field>
13012            <field>
13013              <name>B</name>
13014              <description>Active channel, non-bufferable/bufferable access control:
13015'0': non-bufferable
13016'1': bufferable.</description>
13017              <bitRange>[2:2]</bitRange>
13018              <access>read-only</access>
13019            </field>
13020            <field>
13021              <name>PC</name>
13022              <description>Active channel protection context.</description>
13023              <bitRange>[7:4]</bitRange>
13024              <access>read-only</access>
13025            </field>
13026            <field>
13027              <name>PRIO</name>
13028              <description>Active channel priority.</description>
13029              <bitRange>[9:8]</bitRange>
13030              <access>read-only</access>
13031            </field>
13032            <field>
13033              <name>PREEMPTABLE</name>
13034              <description>Active channel preemptable.</description>
13035              <bitRange>[11:11]</bitRange>
13036              <access>read-only</access>
13037            </field>
13038            <field>
13039              <name>CH_IDX</name>
13040              <description>Active channel index.</description>
13041              <bitRange>[24:16]</bitRange>
13042              <access>read-only</access>
13043            </field>
13044            <field>
13045              <name>STATE</name>
13046              <description>State of the DW controller.
13047'0': Default/inactive state.
13048'1': Loading descriptor.
13049'2': Loading data element from source location.
13050'3': Storing data element to destination location.
13051'4': CRC functionality (only used for CRC transfer descriptor type).
13052'5': Update of active control information (e.g. source and destination addresses) and wait for trigger de-activation.
13053'6': Error.</description>
13054              <bitRange>[30:28]</bitRange>
13055              <access>read-only</access>
13056            </field>
13057            <field>
13058              <name>ACTIVE</name>
13059              <description>Active channel present:
13060'0': No.
13061'1': Yes.</description>
13062              <bitRange>[31:31]</bitRange>
13063              <access>read-only</access>
13064            </field>
13065          </fields>
13066        </register>
13067        <register>
13068          <name>ACT_DESCR_CTL</name>
13069          <description>Active descriptor control</description>
13070          <addressOffset>0x20</addressOffset>
13071          <size>32</size>
13072          <access>read-only</access>
13073          <resetValue>0x0</resetValue>
13074          <resetMask>0x0</resetMask>
13075          <fields>
13076            <field>
13077              <name>DATA</name>
13078              <description>N/A</description>
13079              <bitRange>[31:0]</bitRange>
13080              <access>read-only</access>
13081            </field>
13082          </fields>
13083        </register>
13084        <register>
13085          <name>ACT_DESCR_SRC</name>
13086          <description>Active descriptor source</description>
13087          <addressOffset>0x24</addressOffset>
13088          <size>32</size>
13089          <access>read-only</access>
13090          <resetValue>0x0</resetValue>
13091          <resetMask>0x0</resetMask>
13092          <fields>
13093            <field>
13094              <name>DATA</name>
13095              <description>Copy of DESCR_SRC of the currently active descriptor.
13096
13097Base address of source location.</description>
13098              <bitRange>[31:0]</bitRange>
13099              <access>read-only</access>
13100            </field>
13101          </fields>
13102        </register>
13103        <register>
13104          <name>ACT_DESCR_DST</name>
13105          <description>Active descriptor destination</description>
13106          <addressOffset>0x28</addressOffset>
13107          <size>32</size>
13108          <access>read-only</access>
13109          <resetValue>0x0</resetValue>
13110          <resetMask>0x0</resetMask>
13111          <fields>
13112            <field>
13113              <name>DATA</name>
13114              <description>Copy of DESCR_DST of the currently active descriptor.
13115
13116Base address of destination location.
13117
13118Note: For a CRC transfer descriptor, this field should be programmed with the address of the CRC_LFSR_CTL register. The calculated CRC LFSR state is written to this address (through the CRYPTO AHB-Lite master interface) when the input trigger is processed. The write transfer will be submitted to the CPUSS and PERI protection schemes.</description>
13119              <bitRange>[31:0]</bitRange>
13120              <access>read-only</access>
13121            </field>
13122          </fields>
13123        </register>
13124        <register>
13125          <name>ACT_DESCR_X_CTL</name>
13126          <description>Active descriptor X loop control</description>
13127          <addressOffset>0x30</addressOffset>
13128          <size>32</size>
13129          <access>read-only</access>
13130          <resetValue>0x0</resetValue>
13131          <resetMask>0x0</resetMask>
13132          <fields>
13133            <field>
13134              <name>DATA</name>
13135              <description>Copy of DESCR_X_CTL of the currently active descriptor.
13136
13137[11:0] SRC_X_INCR
13138Specifies increment of source address for each X loop iteration (in multiples of SRC_TRANSFER_SIZE). This field is a signed number in the range [-2048, 2047]. If this field is '0', the source address is not incremented. This is useful for reading from RX FIFO structures.
13139
13140[23:12] DST_X_INCR
13141Specifies increment of destination address for each X loop iteration (in multiples of DST_TRANSFER_SIZE). This field is a signed number in the range [-2048, 2047]. If this field is '0', the destination address is not incremented. This is useful for writing to TX FIFO structures.
13142
13143Note: this field is not used for CRC transfer descriptors and must be set to '0'.
13144
13145[31:24] X_COUNT
13146Number of iterations (minus 1) of the 'X loop' (X_COUNT+1 is the number of single transfers in a 1D transfer). This field is an unsigned number in the range [0, 255], representing 1 through 256 iterations.
13147
13148For a single transfer descriptor type, descriptor will not have X_CTL.</description>
13149              <bitRange>[31:0]</bitRange>
13150              <access>read-only</access>
13151            </field>
13152          </fields>
13153        </register>
13154        <register>
13155          <name>ACT_DESCR_Y_CTL</name>
13156          <description>Active descriptor Y loop control</description>
13157          <addressOffset>0x34</addressOffset>
13158          <size>32</size>
13159          <access>read-only</access>
13160          <resetValue>0x0</resetValue>
13161          <resetMask>0x0</resetMask>
13162          <fields>
13163            <field>
13164              <name>DATA</name>
13165              <description>Copy of DESCR_Y_CTL of the currently active descriptor.
13166
13167[11:0] SRC_Y_INCR
13168Specifies increment of source address for each Y loop iteration (in multiples of SRC_TRANSFER_SIZE). This field is a signed number in the range [-2048, 2047].
13169
13170[23:12] DST_Y_INCR
13171Specifies increment of destination address for each Y loop iteration (in multiples of DST_TRANSFER_SIZE). This field is a signed number in the range [-2048, 2047].
13172
13173[31:24] Y_COUNT
13174Number of iterations (minus 1) of the 'Y loop' (X_COUNT+1)*(Y_COUNT+1) is the number of single transfers in a 2D transfer). This field is an unsigned number in the range [0, 255], representing 1 through 256 iterations.
13175
13176For single, 1D and CRC transfer descriptor types, descriptor will not have Y_CTL.</description>
13177              <bitRange>[31:0]</bitRange>
13178              <access>read-only</access>
13179            </field>
13180          </fields>
13181        </register>
13182        <register>
13183          <name>ACT_DESCR_NEXT_PTR</name>
13184          <description>Active descriptor next pointer</description>
13185          <addressOffset>0x38</addressOffset>
13186          <size>32</size>
13187          <access>read-only</access>
13188          <resetValue>0x0</resetValue>
13189          <resetMask>0x0</resetMask>
13190          <fields>
13191            <field>
13192              <name>ADDR</name>
13193              <description>Copy of DESCR_NEXT_PTR of the currently active descriptor.
13194
13195[31:2] ADDR
13196Address of next descriptor in descriptor list. When this field is '0', this is the last descriptor in the descriptor list.</description>
13197              <bitRange>[31:2]</bitRange>
13198              <access>read-only</access>
13199            </field>
13200          </fields>
13201        </register>
13202        <register>
13203          <name>ACT_SRC</name>
13204          <description>Active source</description>
13205          <addressOffset>0x40</addressOffset>
13206          <size>32</size>
13207          <access>read-only</access>
13208          <resetValue>0x0</resetValue>
13209          <resetMask>0x0</resetMask>
13210          <fields>
13211            <field>
13212              <name>SRC_ADDR</name>
13213              <description>Current address of source location.</description>
13214              <bitRange>[31:0]</bitRange>
13215              <access>read-only</access>
13216            </field>
13217          </fields>
13218        </register>
13219        <register>
13220          <name>ACT_DST</name>
13221          <description>Active destination</description>
13222          <addressOffset>0x44</addressOffset>
13223          <size>32</size>
13224          <access>read-only</access>
13225          <resetValue>0x0</resetValue>
13226          <resetMask>0x0</resetMask>
13227          <fields>
13228            <field>
13229              <name>DST_ADDR</name>
13230              <description>Current address of destination location.</description>
13231              <bitRange>[31:0]</bitRange>
13232              <access>read-only</access>
13233            </field>
13234          </fields>
13235        </register>
13236        <register>
13237          <name>ECC_CTL</name>
13238          <description>ECC control</description>
13239          <addressOffset>0x80</addressOffset>
13240          <size>32</size>
13241          <access>read-write</access>
13242          <resetValue>0x0</resetValue>
13243          <resetMask>0xFE0003FF</resetMask>
13244          <fields>
13245            <field>
13246              <name>WORD_ADDR</name>
13247              <description>Specifies the word address where an error will be injected.
13248- On a write transfer to this SRAM word address and when CTL.ECC_INJ_EN bit is '1', the parity (PARITY) is injected.</description>
13249              <bitRange>[9:0]</bitRange>
13250              <access>read-write</access>
13251            </field>
13252            <field>
13253              <name>PARITY</name>
13254              <description>ECC parity to use for ECC error injection at address WORD_ADDR.</description>
13255              <bitRange>[31:25]</bitRange>
13256              <access>read-write</access>
13257            </field>
13258          </fields>
13259        </register>
13260        <register>
13261          <name>CRC_CTL</name>
13262          <description>CRC control</description>
13263          <addressOffset>0x100</addressOffset>
13264          <size>32</size>
13265          <access>read-write</access>
13266          <resetValue>0x0</resetValue>
13267          <resetMask>0x101</resetMask>
13268          <fields>
13269            <field>
13270              <name>DATA_REVERSE</name>
13271              <description>Specifies the bit order in which a data Byte is processed (reversal is performed after XORing):
13272'0': Most significant bit (bit 1) first.
13273'1': Least significant bit (bit 0) first.</description>
13274              <bitRange>[0:0]</bitRange>
13275              <access>read-write</access>
13276            </field>
13277            <field>
13278              <name>REM_REVERSE</name>
13279              <description>Specifies whether the remainder is bit reversed (reversal is performed after XORing):
13280'0': No.
13281'1': Yes.</description>
13282              <bitRange>[8:8]</bitRange>
13283              <access>read-write</access>
13284            </field>
13285          </fields>
13286        </register>
13287        <register>
13288          <name>CRC_DATA_CTL</name>
13289          <description>CRC data control</description>
13290          <addressOffset>0x110</addressOffset>
13291          <size>32</size>
13292          <access>read-write</access>
13293          <resetValue>0x0</resetValue>
13294          <resetMask>0xFF</resetMask>
13295          <fields>
13296            <field>
13297              <name>DATA_XOR</name>
13298              <description>Specifies a byte mask with which each data byte is XOR'd. The XOR is performed before data reversal.</description>
13299              <bitRange>[7:0]</bitRange>
13300              <access>read-write</access>
13301            </field>
13302          </fields>
13303        </register>
13304        <register>
13305          <name>CRC_POL_CTL</name>
13306          <description>CRC polynomial control</description>
13307          <addressOffset>0x120</addressOffset>
13308          <size>32</size>
13309          <access>read-write</access>
13310          <resetValue>0x0</resetValue>
13311          <resetMask>0xFFFFFFFF</resetMask>
13312          <fields>
13313            <field>
13314              <name>POLYNOMIAL</name>
13315              <description>CRC polynomial. The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1'). The polynomial should be aligned/shifted such that the more significant bits (bit 31 and down) contain the polynomial and the less significant bits (bit 0 and up) contain padding '0's. Some frequently used polynomials:
13316- CRC32: POLYNOMIAL is 0x04c11db7 (x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1).
13317- CRC16: POLYNOMIAL is 0x80050000 (x^16 + x^15 + x^2 + 1, shifted by 16 bit positions).
13318- CRC16 CCITT: POLYNOMIAL is 0x10210000 (x^16 + x^12 + x^5 + 1, shifted by 16 bit positions).</description>
13319              <bitRange>[31:0]</bitRange>
13320              <access>read-write</access>
13321            </field>
13322          </fields>
13323        </register>
13324        <register>
13325          <name>CRC_LFSR_CTL</name>
13326          <description>CRC LFSR control</description>
13327          <addressOffset>0x130</addressOffset>
13328          <size>32</size>
13329          <access>read-write</access>
13330          <resetValue>0x0</resetValue>
13331          <resetMask>0xFFFFFFFF</resetMask>
13332          <fields>
13333            <field>
13334              <name>LFSR32</name>
13335              <description>State of a 32-bit Linear Feedback Shift Registers (LFSR) that is used to implement CRC. This register needs to be initialized by SW to provide the CRC seed value.
13336
13337The seed value should be aligned such that the more significant bits (bit 31 and down) contain the seed value and the less significant bits (bit 0 and up) contain padding '0's.
13338
13339Note that SW can write this field. This functionality can be used prevent information leakage (through either CRC_LFSR_CTL or CRC_REM_RESULT).</description>
13340              <bitRange>[31:0]</bitRange>
13341              <access>read-write</access>
13342            </field>
13343          </fields>
13344        </register>
13345        <register>
13346          <name>CRC_REM_CTL</name>
13347          <description>CRC remainder control</description>
13348          <addressOffset>0x140</addressOffset>
13349          <size>32</size>
13350          <access>read-write</access>
13351          <resetValue>0x0</resetValue>
13352          <resetMask>0xFFFFFFFF</resetMask>
13353          <fields>
13354            <field>
13355              <name>REM_XOR</name>
13356              <description>Specifies a mask with which the CRC_LFSR_CTL.LFSR32 register is XOR'd to produce a remainder. The XOR is performed before remainder reversal.</description>
13357              <bitRange>[31:0]</bitRange>
13358              <access>read-write</access>
13359            </field>
13360          </fields>
13361        </register>
13362        <register>
13363          <name>CRC_REM_RESULT</name>
13364          <description>CRC remainder result</description>
13365          <addressOffset>0x148</addressOffset>
13366          <size>32</size>
13367          <access>read-only</access>
13368          <resetValue>0x0</resetValue>
13369          <resetMask>0xFFFFFFFF</resetMask>
13370          <fields>
13371            <field>
13372              <name>REM</name>
13373              <description>Remainder value. The alignment of the remainder depends on CRC_REM_CTL0.REM_REVERSE:
13374'0': the more significant bits (bit 31 and down) contain the remainder.
13375'1': the less significant bits (bit 0 and up) contain the remainder.
13376
13377Note: This field is combinatorially derived from CRC_LFSR_CTL.LFSR32, CRC_CTL.REM_REVERSE and CRC_REM_CTL.REM_XOR.</description>
13378              <bitRange>[31:0]</bitRange>
13379              <access>read-only</access>
13380            </field>
13381          </fields>
13382        </register>
13383        <cluster>
13384          <dim>32</dim>
13385          <dimIncrement>64</dimIncrement>
13386          <name>CH_STRUCT[%s]</name>
13387          <description>DW channel structure</description>
13388          <addressOffset>0x00008000</addressOffset>
13389          <register>
13390            <name>CH_CTL</name>
13391            <description>Channel control</description>
13392            <addressOffset>0x0</addressOffset>
13393            <size>32</size>
13394            <access>read-write</access>
13395            <resetValue>0x0</resetValue>
13396            <resetMask>0x80000300</resetMask>
13397            <fields>
13398              <field>
13399                <name>P</name>
13400                <description>User/privileged access control:
13401'0': user mode.
13402'1': privileged mode.
13403
13404This field is set with the user/privileged access control of the transaction that writes this register; i.e.  the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R).
13405
13406All transactions for this channel use the P field for the user/privileged access control ('hprot[1]').</description>
13407                <bitRange>[0:0]</bitRange>
13408                <access>read-write</access>
13409              </field>
13410              <field>
13411                <name>NS</name>
13412                <description>Secure/on-secure access control:
13413'0': secure.
13414'1': non-secure.
13415
13416This field is set with the secure/non-secure access control of the transaction that writes this register; i.e.  the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R).
13417
13418All transactions for this channel use the NS field for the secure/non-secure access control ('hprot[4]').</description>
13419                <bitRange>[1:1]</bitRange>
13420                <access>read-write</access>
13421              </field>
13422              <field>
13423                <name>B</name>
13424                <description>Non-bufferable/bufferable access control:
13425'0': non-bufferable.
13426'1': bufferable.
13427
13428This field is used to indicate to an AMBA bridge that a write transaction can complete without waiting for the destination to accept the write transaction data.
13429
13430All transactions for this channel uses the B field for the non-bufferable/bufferable access control ('hprot[2]').</description>
13431                <bitRange>[2:2]</bitRange>
13432                <access>read-write</access>
13433              </field>
13434              <field>
13435                <name>PC</name>
13436                <description>Protection context.
13437
13438This field is set with the protection context of the transaction that writes this register;  i.e.  the 'write data' is ignored and instead the context is inherited from the write transaction (note the field attributes should be HW:RW, SW:R).
13439
13440All transactions for this channel uses the PC field for the protection context.</description>
13441                <bitRange>[7:4]</bitRange>
13442                <access>read-write</access>
13443              </field>
13444              <field>
13445                <name>PRIO</name>
13446                <description>Channel priority:
13447'0': highest priority.
13448'1'
13449'2'
13450'3': lowest priority.
13451
13452Channels with the same priority constitute a priority group. Priority decoding determines the highest priority pending channel. This channel is determined as follows. First, the highest priority group with pending channels is identified. Second, within this priority group, round robin arbitration is applied. Round robin arbitration (within a priority group) gives the highest priority to the lower channel indices (within the priority group).</description>
13453                <bitRange>[9:8]</bitRange>
13454                <access>read-write</access>
13455              </field>
13456              <field>
13457                <name>PREEMPTABLE</name>
13458                <description>Specifies if the channel is preemptable.
13459'0': Not preemptable.
13460'1': Preemptable. This field allows higher priority pending channels (from a higher priority group; i.e. an active channel can NOT be preempted by a pending channel in the same priority group) to preempt the active channel in between 'single transfers' (a 1D transfer consists out of X_COUNT single transfers; a 2D transfer consists out of X_COUNT*Y_COUNT single transfers). Preemption will NOT affect the pending status of channel. As a result, after completion of a higher priority activated channel, the current channel may be reactivated.</description>
13461                <bitRange>[11:11]</bitRange>
13462                <access>read-write</access>
13463              </field>
13464              <field>
13465                <name>ENABLED</name>
13466                <description>Channel enable:
13467'0': Disabled. The channel's trigger is ignored and the channel cannot be made pending and therefore cannot be made active. If a pending channel is disabled, the channel is made non pending. If the activate channel is disabled, the channel is de-activated (bus transactions are completed).
13468'1': Enabled.
13469
13470SW sets this field to '1' to enable a specific channel.
13471
13472HW sets this field to '0' on an error interrupt cause (the specific error is specified by CH_STATUS.INTR_CAUSE).</description>
13473                <bitRange>[31:31]</bitRange>
13474                <access>read-write</access>
13475              </field>
13476            </fields>
13477          </register>
13478          <register>
13479            <name>CH_STATUS</name>
13480            <description>Channel status</description>
13481            <addressOffset>0x4</addressOffset>
13482            <size>32</size>
13483            <access>read-only</access>
13484            <resetValue>0x0</resetValue>
13485            <resetMask>0x80000000</resetMask>
13486            <fields>
13487              <field>
13488                <name>INTR_CAUSE</name>
13489                <description>Specifies the source of the interrupt cause:
13490'0': No interrupt generated
13491'1': Interrupt based on transfer complettion configuration based on INTR_TYPE
13492'2': Source transfer bus error
13493'3': Destination transfer bus error
13494'4': Source address misalignment
13495'5': Destination address misalignment
13496'6': Current descriptor pointer is null
13497'7': Active channel is disabled
13498'8': Descriptor bus error
13499'9'-'15': Not used.
13500
13501For error related interrupt causes (INTR_CAUSE is '2', '3', ..., '8'), the channel is disabled (HW sets CH_CTL.ENABLED to '0').</description>
13502                <bitRange>[3:0]</bitRange>
13503                <access>read-only</access>
13504              </field>
13505              <field>
13506                <name>PENDING</name>
13507                <description>Specifies pending DW channels; i.e. enabled channels whose trigger got activated. This field includes all channels that are in the pending state (not scheduled) or active state (scheduled and performing data transfer(s)).</description>
13508                <bitRange>[31:31]</bitRange>
13509                <access>read-only</access>
13510              </field>
13511            </fields>
13512          </register>
13513          <register>
13514            <name>CH_IDX</name>
13515            <description>Channel current indices</description>
13516            <addressOffset>0x8</addressOffset>
13517            <size>32</size>
13518            <access>read-write</access>
13519            <resetValue>0x0</resetValue>
13520            <resetMask>0x0</resetMask>
13521            <fields>
13522              <field>
13523                <name>X_IDX</name>
13524                <description>Specifies the X loop index. In the range of [0, X_COUNT], with X_COUNT taken from the current descriptor.
13525
13526Note: HW sets this field to '0' when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor.
13527
13528Note: SW should set this field to '0' when it updates CH_CURR_PTR.</description>
13529                <bitRange>[7:0]</bitRange>
13530                <access>read-write</access>
13531              </field>
13532              <field>
13533                <name>Y_IDX</name>
13534                <description>Specifies the Y loop index, with X_COUNT taken from the current descriptor.
13535
13536Note: HW sets this field to '0' when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor.
13537
13538Note: SW should set this field to '0' when it updates CH_CURR_PTR.</description>
13539                <bitRange>[15:8]</bitRange>
13540                <access>read-write</access>
13541              </field>
13542            </fields>
13543          </register>
13544          <register>
13545            <name>CH_CURR_PTR</name>
13546            <description>Channel current descriptor pointer</description>
13547            <addressOffset>0xC</addressOffset>
13548            <size>32</size>
13549            <access>read-write</access>
13550            <resetValue>0x0</resetValue>
13551            <resetMask>0x0</resetMask>
13552            <fields>
13553              <field>
13554                <name>ADDR</name>
13555                <description>Address of current descriptor. When this field is '0', there is no valid descriptor.
13556
13557Note: HW updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor.
13558
13559Note: Typically, when SW updates the current descriptor pointer CH_CURR_PTR, it also sets CH_IDX.X_IDX and CH_IDX.Y_IDX to '0'.</description>
13560                <bitRange>[31:2]</bitRange>
13561                <access>read-write</access>
13562              </field>
13563            </fields>
13564          </register>
13565          <register>
13566            <name>INTR</name>
13567            <description>Interrupt</description>
13568            <addressOffset>0x10</addressOffset>
13569            <size>32</size>
13570            <access>read-write</access>
13571            <resetValue>0x0</resetValue>
13572            <resetMask>0x1</resetMask>
13573            <fields>
13574              <field>
13575                <name>CH</name>
13576                <description>Set to '1', when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1', to clear bit. Write INTR_SET.CH field with '1', to set bit.</description>
13577                <bitRange>[0:0]</bitRange>
13578                <access>read-write</access>
13579              </field>
13580            </fields>
13581          </register>
13582          <register>
13583            <name>INTR_SET</name>
13584            <description>Interrupt set</description>
13585            <addressOffset>0x14</addressOffset>
13586            <size>32</size>
13587            <access>read-write</access>
13588            <resetValue>0x0</resetValue>
13589            <resetMask>0x1</resetMask>
13590            <fields>
13591              <field>
13592                <name>CH</name>
13593                <description>Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect).</description>
13594                <bitRange>[0:0]</bitRange>
13595                <access>read-write</access>
13596              </field>
13597            </fields>
13598          </register>
13599          <register>
13600            <name>INTR_MASK</name>
13601            <description>Interrupt mask</description>
13602            <addressOffset>0x18</addressOffset>
13603            <size>32</size>
13604            <access>read-write</access>
13605            <resetValue>0x0</resetValue>
13606            <resetMask>0x1</resetMask>
13607            <fields>
13608              <field>
13609                <name>CH</name>
13610                <description>Mask for corresponding field in INTR register.</description>
13611                <bitRange>[0:0]</bitRange>
13612                <access>read-write</access>
13613              </field>
13614            </fields>
13615          </register>
13616          <register>
13617            <name>INTR_MASKED</name>
13618            <description>Interrupt masked</description>
13619            <addressOffset>0x1C</addressOffset>
13620            <size>32</size>
13621            <access>read-only</access>
13622            <resetValue>0x0</resetValue>
13623            <resetMask>0x1</resetMask>
13624            <fields>
13625              <field>
13626                <name>CH</name>
13627                <description>Logical and of corresponding INTR and INTR_MASK fields.</description>
13628                <bitRange>[0:0]</bitRange>
13629                <access>read-only</access>
13630              </field>
13631            </fields>
13632          </register>
13633          <register>
13634            <name>SRAM_DATA0</name>
13635            <description>SRAM data 0</description>
13636            <addressOffset>0x20</addressOffset>
13637            <size>32</size>
13638            <access>read-write</access>
13639            <resetValue>0x0</resetValue>
13640            <resetMask>0x0</resetMask>
13641            <fields>
13642              <field>
13643                <name>DATA</name>
13644                <description>N/A</description>
13645                <bitRange>[31:0]</bitRange>
13646                <access>read-write</access>
13647              </field>
13648            </fields>
13649          </register>
13650          <register>
13651            <name>SRAM_DATA1</name>
13652            <description>SRAM data 1</description>
13653            <addressOffset>0x24</addressOffset>
13654            <size>32</size>
13655            <access>read-write</access>
13656            <resetValue>0x0</resetValue>
13657            <resetMask>0x0</resetMask>
13658            <fields>
13659              <field>
13660                <name>DATA</name>
13661                <description>N/A</description>
13662                <bitRange>[31:0]</bitRange>
13663                <access>read-write</access>
13664              </field>
13665            </fields>
13666          </register>
13667          <register>
13668            <name>TR_CMD</name>
13669            <description>Channel software trigger</description>
13670            <addressOffset>0x28</addressOffset>
13671            <size>32</size>
13672            <access>read-write</access>
13673            <resetValue>0x0</resetValue>
13674            <resetMask>0x1</resetMask>
13675            <fields>
13676              <field>
13677                <name>ACTIVATE</name>
13678                <description>Software trigger. When written with '1', a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0.</description>
13679                <bitRange>[0:0]</bitRange>
13680                <access>read-write</access>
13681              </field>
13682            </fields>
13683          </register>
13684        </cluster>
13685      </registers>
13686    </peripheral>
13687    <peripheral derivedFrom="DW0">
13688      <name>DW1</name>
13689      <baseAddress>0x40290000</baseAddress>
13690    </peripheral>
13691    <peripheral>
13692      <name>DMAC</name>
13693      <description>DMAC</description>
13694      <baseAddress>0x402A0000</baseAddress>
13695      <addressBlock>
13696        <offset>0</offset>
13697        <size>65536</size>
13698        <usage>registers</usage>
13699      </addressBlock>
13700      <registers>
13701        <register>
13702          <name>CTL</name>
13703          <description>Control</description>
13704          <addressOffset>0x0</addressOffset>
13705          <size>32</size>
13706          <access>read-write</access>
13707          <resetValue>0x0</resetValue>
13708          <resetMask>0x80000000</resetMask>
13709          <fields>
13710            <field>
13711              <name>ENABLED</name>
13712              <description>IP enable:
13713'0': Disabled. All non-retention registers (command and status registers) are reset to their default value when the IP is disabled. All retention registers retain their value when the IP is disabled.
13714'1': Enabled.</description>
13715              <bitRange>[31:31]</bitRange>
13716              <access>read-write</access>
13717              <enumeratedValues>
13718                <enumeratedValue>
13719                  <name>DISABLED</name>
13720                  <description>N/A</description>
13721                  <value>0</value>
13722                </enumeratedValue>
13723                <enumeratedValue>
13724                  <name>ENABLED</name>
13725                  <description>N/A</description>
13726                  <value>1</value>
13727                </enumeratedValue>
13728              </enumeratedValues>
13729            </field>
13730          </fields>
13731        </register>
13732        <register>
13733          <name>ACTIVE</name>
13734          <description>Active channels</description>
13735          <addressOffset>0x8</addressOffset>
13736          <size>32</size>
13737          <access>read-only</access>
13738          <resetValue>0x0</resetValue>
13739          <resetMask>0xFF</resetMask>
13740          <fields>
13741            <field>
13742              <name>ACTIVE</name>
13743              <description>Specifies active channels; i.e. enabled channels whose trigger got activated.</description>
13744              <bitRange>[7:0]</bitRange>
13745              <access>read-only</access>
13746            </field>
13747          </fields>
13748        </register>
13749        <cluster>
13750          <dim>6</dim>
13751          <dimIncrement>256</dimIncrement>
13752          <name>CH[%s]</name>
13753          <description>DMA controller channel</description>
13754          <addressOffset>0x00001000</addressOffset>
13755          <register>
13756            <name>CTL</name>
13757            <description>Channel control</description>
13758            <addressOffset>0x0</addressOffset>
13759            <size>32</size>
13760            <access>read-write</access>
13761            <resetValue>0x2</resetValue>
13762            <resetMask>0x800003F7</resetMask>
13763            <fields>
13764              <field>
13765                <name>P</name>
13766                <description>User/privileged access control:
13767'0': user mode.
13768'1': privileged mode.
13769
13770This field is set with the user/privileged access control of the transaction that writes this register; i.e. the access control is inherited from the write transaction and not specified by the transaction write data.
13771
13772All transactions for this channel use the P field for the user/privileged access control ('hprot[1]').</description>
13773                <bitRange>[0:0]</bitRange>
13774                <access>read-write</access>
13775              </field>
13776              <field>
13777                <name>NS</name>
13778                <description>Secure/on-secure access control:
13779'0': secure.
13780'1': non-secure.
13781
13782This field is set with the secure/non-secure access control of the transaction that writes this register; i.e. the access control is inherited from the write transaction and not specified by the transaction write data.
13783
13784All transactions for this channel use the NS field for the secure/non-secure access control ('hprot[4]').</description>
13785                <bitRange>[1:1]</bitRange>
13786                <access>read-write</access>
13787              </field>
13788              <field>
13789                <name>B</name>
13790                <description>Non-bufferable/bufferable access control:
13791'0': non-bufferable.
13792'1': bufferable.
13793
13794This field is used to indicate to an AMBA bridge that a write transaction can complete without waiting for the destination to accept the write transaction data.
13795
13796All transactions for this channel uses the B field for the non-bufferable/bufferable access control ('hprot[2]').</description>
13797                <bitRange>[2:2]</bitRange>
13798                <access>read-write</access>
13799              </field>
13800              <field>
13801                <name>PC</name>
13802                <description>Protection context.
13803
13804This field is set with the protection context of the transaction that writes this register; i.e. the context is inherited from the write transaction and not specified by the transaction write data.
13805
13806All transactions for this channel uses the PC field for the protection context.</description>
13807                <bitRange>[7:4]</bitRange>
13808                <access>read-write</access>
13809              </field>
13810              <field>
13811                <name>PRIO</name>
13812                <description>Channel priority:
13813'0': highest priority.
13814'1'
13815'2'
13816'3': lowest priority.
13817
13818Channels with the same priority constitute a priority group and within this priority group, the following 'roundrobin' arbitration is applied.
13819A 'round' consists of a contiguous sequence of channel activations, within this priority group, without any repetition. Within a round, higher priority is given to the lower channel indices. The notion of a round guarantees that within a group, higher channel indices do not yield to lower indices indefinitely.</description>
13820                <bitRange>[9:8]</bitRange>
13821                <access>read-write</access>
13822              </field>
13823              <field>
13824                <name>ENABLED</name>
13825                <description>Channel enable:
13826'0': Disabled. The channel's trigger is ignored and the channel cannot be made pending and therefore cannot be made active. If a pending channel is disabled, the channel is made non pending. If the activate channel is disabled, the channel is de-activated (bus transactions are completed).
13827'1': Enabled.
13828
13829SW sets this field to '1' to enable a specific channel.
13830
13831HW sets this field to '0' when an error interrupt cause is activated.</description>
13832                <bitRange>[31:31]</bitRange>
13833                <access>read-write</access>
13834              </field>
13835            </fields>
13836          </register>
13837          <register>
13838            <name>IDX</name>
13839            <description>Channel current indices</description>
13840            <addressOffset>0x10</addressOffset>
13841            <size>32</size>
13842            <access>read-only</access>
13843            <resetValue>0x0</resetValue>
13844            <resetMask>0x0</resetMask>
13845            <fields>
13846              <field>
13847                <name>X</name>
13848                <description>Specifies the X loop index. In the range of [0, X_COUNT], with X_COUNT taken from the current descriptor.
13849
13850Note: HW sets this field to '0' when it loads a descriptor.</description>
13851                <bitRange>[15:0]</bitRange>
13852                <access>read-only</access>
13853              </field>
13854              <field>
13855                <name>Y</name>
13856                <description>Specifies the Y loop index, with Y_COUNT taken from the current descriptor.
13857
13858Note: HW sets this field to '0' when it loads a descriptor..</description>
13859                <bitRange>[31:16]</bitRange>
13860                <access>read-only</access>
13861              </field>
13862            </fields>
13863          </register>
13864          <register>
13865            <name>SRC</name>
13866            <description>Channel current source address</description>
13867            <addressOffset>0x14</addressOffset>
13868            <size>32</size>
13869            <access>read-only</access>
13870            <resetValue>0x0</resetValue>
13871            <resetMask>0x0</resetMask>
13872            <fields>
13873              <field>
13874                <name>ADDR</name>
13875                <description>Current address of source location.</description>
13876                <bitRange>[31:0]</bitRange>
13877                <access>read-only</access>
13878              </field>
13879            </fields>
13880          </register>
13881          <register>
13882            <name>DST</name>
13883            <description>Channel current destination address</description>
13884            <addressOffset>0x18</addressOffset>
13885            <size>32</size>
13886            <access>read-only</access>
13887            <resetValue>0x0</resetValue>
13888            <resetMask>0x0</resetMask>
13889            <fields>
13890              <field>
13891                <name>ADDR</name>
13892                <description>Current address of destination location.</description>
13893                <bitRange>[31:0]</bitRange>
13894                <access>read-only</access>
13895              </field>
13896            </fields>
13897          </register>
13898          <register>
13899            <name>CURR</name>
13900            <description>Channel current descriptor pointer</description>
13901            <addressOffset>0x20</addressOffset>
13902            <size>32</size>
13903            <access>read-write</access>
13904            <resetValue>0x0</resetValue>
13905            <resetMask>0x0</resetMask>
13906            <fields>
13907              <field>
13908                <name>PTR</name>
13909                <description>Address of current descriptor. When this field is '0', there is no valid descriptor.
13910
13911Note: HW updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor.</description>
13912                <bitRange>[31:2]</bitRange>
13913                <access>read-write</access>
13914              </field>
13915            </fields>
13916          </register>
13917          <register>
13918            <name>TR_CMD</name>
13919            <description>Channle software trigger</description>
13920            <addressOffset>0x28</addressOffset>
13921            <size>32</size>
13922            <access>read-write</access>
13923            <resetValue>0x0</resetValue>
13924            <resetMask>0x1</resetMask>
13925            <fields>
13926              <field>
13927                <name>ACTIVATE</name>
13928                <description>Software trigger. When written with '1', a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0.</description>
13929                <bitRange>[0:0]</bitRange>
13930                <access>read-write</access>
13931              </field>
13932            </fields>
13933          </register>
13934          <register>
13935            <name>DESCR_STATUS</name>
13936            <description>Channel descriptor status</description>
13937            <addressOffset>0x40</addressOffset>
13938            <size>32</size>
13939            <access>read-only</access>
13940            <resetValue>0x0</resetValue>
13941            <resetMask>0x80000000</resetMask>
13942            <fields>
13943              <field>
13944                <name>VALID</name>
13945                <description>Indicates whether the descriptor information present in DESCR_CTL, DESCR_SRC, DESCR_DST, DESCR_X_SIZE, DESCR_X_INCR, DESCR_Y_SIZE, DESCR_Y_INCR, DESCR_NEXT status registers is valid or not.</description>
13946                <bitRange>[31:31]</bitRange>
13947                <access>read-only</access>
13948              </field>
13949            </fields>
13950          </register>
13951          <register>
13952            <name>DESCR_CTL</name>
13953            <description>Channel descriptor control</description>
13954            <addressOffset>0x60</addressOffset>
13955            <size>32</size>
13956            <access>read-only</access>
13957            <resetValue>0x0</resetValue>
13958            <resetMask>0x0</resetMask>
13959            <fields>
13960              <field>
13961                <name>WAIT_FOR_DEACT</name>
13962                <description>Specifies whether the controller should wait for the input trigger to be deactivated; i.e. the selected system trigger is not active. This field is used to synchronize the controller with the agent that generated the trigger. This field is ONLY used at the completion of the transfer as specified by TR_IN. E.g., a TX FIFO indicates that it is empty and it needs a new data sample. The agent removes the trigger ONLY when the data sample has been written by the controller AND received by the agent.  Furthermore, the agent's trigger may be delayed by a few cycles before it reaches the controller. This field is used for level sensitive trigger, which reflect state (pulse sensitive triggers should have this field set to '0'). The wait cycles incurred by this field reduce DW controller performance.
13963'0': Do not wait for trigger de-activation (for pulse sensitive triggers).
13964'1': Wait for up to 4 cycles.
13965'2': Wait for up to 16 cycles.
13966'3': Wait indefinitely. This option may result in controller lockup if the trigger is not de-activated.</description>
13967                <bitRange>[1:0]</bitRange>
13968                <access>read-only</access>
13969              </field>
13970              <field>
13971                <name>INTR_TYPE</name>
13972                <description>Specifies when a completion interrupt is generated (CH_STATUS.INTR_CAUSE is set to COMPLETION):
13973'0': An interrupt is generated after a single transfer.
13974'1': An interrupt is generated after a single 1D transfer or a memory copy transfer
13975- If the descriptor type is 'single', the interrupt is generated after a single transfer.
13976- If the descriptor type is '1D' or '2D', the interrupt is generated after the execution of a 1D transfer.
13977- If the descriptor type is 'memory copy', the interrupt is generated after the execution of a memory copy transfer.
13978- If the descriptor type is 'scatter' the interrupt is generated after the execution of a scatter transfer.
13979'2': An interrupt is generated after the execution of the current descriptor (independent of the value of DESCR_NEXT_PTR.ADDR of the current descriptor).
13980'3': An interrupt is generated after the execution of the current descriptor and the current descriptor's DESCR_NEXT_PTR.ADDR is '0'.</description>
13981                <bitRange>[3:2]</bitRange>
13982                <access>read-only</access>
13983              </field>
13984              <field>
13985                <name>TR_OUT_TYPE</name>
13986                <description>Specifies when an output trigger is generated:
13987'0': An output trigger is generated after a single transfer.
13988'1': An output trigger is generated after a single 1D transfer or a memory copy transfer.
13989- If the descriptor type is 'single', the output trigger is generated after a single transfer.
13990- If the descriptor type is '1D' or '2D', the output trigger is generated after the execution of a 1D transfer.
13991- If the descriptor type is 'memory copy', the output trigger is generated after the execution of a memory copy transfer.
13992- If the descriptor type is 'scatter', the output trigger is generated after the execution of a scatter transfer.
13993'2': An output trigger is generated after the execution of the current descriptor.
13994'3': An output trigger is generated after the execution of a descriptor list: after the execution of the current descriptor AND the current descriptor's DESCR_NEXT_PTR.ADDR is '0'.</description>
13995                <bitRange>[5:4]</bitRange>
13996                <access>read-only</access>
13997              </field>
13998              <field>
13999                <name>TR_IN_TYPE</name>
14000                <description>Specifies the input trigger type (not to be confused with the descriptor type):
14001'0': A trigger results in the execution of a single transfer. The descriptor type can be single, 1D or 2D.
14002'1': A trigger results in the execution of a single 1D transfer.
14003- If the descriptor type is 'single', the trigger results in the execution of a single transfer.
14004- If the descriptor type is '1D' or '2D', the trigger results in the execution of a 1D transfer.
14005- If the descriptor type is 'memory copy', the trigger results in the execution of a memory copy transfer.
14006- If the descriptor type is 'scatter', the trigger results in the execution of an scatter transfer.
14007'2': A trigger results in the execution of the current descriptor.
14008'3': A trigger results in the execution of the current descriptor and continues (without requiring another input trigger) with the execution of the next descriptor using the next descriptor's information.</description>
14009                <bitRange>[7:6]</bitRange>
14010                <access>read-only</access>
14011              </field>
14012              <field>
14013                <name>DATA_PREFETCH</name>
14014                <description>Source data prefetch:
14015'0': No source data prefetch. Source data transfers are only initiated AFTER the input trigger is activated.
14016'1': Source data prefetch. Source data transfers are initiated as soon as the channel is enabled, the current descriptor pointer is NOT '0' and there is space available in the channel's data FIFO. When the input trigger is activated, the trigger can initiate destination data transfers with data that is already in the channel's data FIFO. This effectively shortens the initial delay of the data transfer.
14017
14018Note: data prefetch should be used with care, to ensure that data coherency is guaranteed and that prefetches do not cause undesired side effects.</description>
14019                <bitRange>[8:8]</bitRange>
14020                <access>read-only</access>
14021              </field>
14022              <field>
14023                <name>DATA_SIZE</name>
14024                <description>Specifies the data element size:
14025'0': Byte (8 bits).
14026'1': Halfword (16 bits).
14027'2': Word (32 bits).
14028DATA_SIZE, SRC_TRANSFER_SIZE and DST_TRANSFER_SIZE together determine how data elements are transferred. The following are the 9 legal settings:
14029- DATA is 8 bit, SRC is 8 bit, DST is 8 bit.
14030- DATA is 8 bit, SRC is 32 bit (higher 24 bits are dropped), DST is 8 bit.
14031- DATA is 8 bit, SRC is 8 bit, DST is 32 bit (higher 24 bits are made '0').
14032- DATA is 8 bit, SRC is 32 bit (higher 24 bits are dropped), DST is 32 bit (higher 24 bits are made '0').
14033- DATA is 16 bit, SRC is 16 bit, DST is 16 bit.
14034- DATA is 16 bit, SRC is 32 bit (higher 16 bits are dropped), DST is 16 bit.
14035- DATA is 16 bit, SRC is 16 bit, DST is 32 bit (higher 16 bits are made '0').
14036- DATA is 16 bit, SRC is 32 bit (higher 16 bits are dropped), DST is 32 bit (higher 16 bits are made '0').
14037- DATA is 32 bit, SRC is 32 bit, DST is 32 bit.
14038
14039Note: this field is not used for a 'memory copy' descriptor type. Note: this field must be set to '2' for a 'initialization' descriptor type.</description>
14040                <bitRange>[17:16]</bitRange>
14041                <access>read-only</access>
14042              </field>
14043              <field>
14044                <name>CH_DISABLE</name>
14045                <description>Specifies whether the channel is disabled or not after completion of the current descriptor (independent of the value of the DESCR_NEXT_PTR value):
14046'0': Channel is not disabled.
14047'1': Channel is disabled.</description>
14048                <bitRange>[24:24]</bitRange>
14049                <access>read-only</access>
14050              </field>
14051              <field>
14052                <name>SRC_TRANSFER_SIZE</name>
14053                <description>Specifies the bus transfer size to the source location:
14054'0': As specified by DATA_SIZE.
14055'1': Word (32 bits).
14056Distinguishing bus transfer size from data element size allows for source components with data elements that are smaller than their 32-bit bus interface width. E.g., an ADC source has a 32-bit bus transfer size, but only provides a 16-bit data element.
14057
14058Note: this field is not used for a 'memory copy' descriptor type. Note: this field must be set to '1' for a 'scatter' descriptor type.</description>
14059                <bitRange>[26:26]</bitRange>
14060                <access>read-only</access>
14061              </field>
14062              <field>
14063                <name>DST_TRANSFER_SIZE</name>
14064                <description>Specifies the bus transfer size to the destination location:
14065'0': As specified by DATA_SIZE.
14066'1': Word (32 bits).
14067Distinguishing bus transfer size from data element size allows for destination components with data elements that are smaller than their 32-bit bus interface width. E.g., a DAC destination has a 32-bit bus transfer size, but only requires a 16-bit data element.
14068
14069Note: this field is not used for a 'memory copy' descriptor type. Note: this field must be set to '1' for a 'scatter' descriptor type.</description>
14070                <bitRange>[27:27]</bitRange>
14071                <access>read-only</access>
14072              </field>
14073              <field>
14074                <name>DESCR_TYPE</name>
14075                <description>Specifies the descriptor type (not to be confused with the trigger type):
14076'0': Single transfer.
14077The DESCR_X_SIZE, DESCR_X_INCR, DESCR_Y_SIZE and DESCR_Y_INCR registers are NOT present. The DESCR_NEXT_PTR is at offset 0x0c.
14078'1': 1D transfer.
14079The DESCR_X_SIZE and DESCR_X_INCR registers are present, the DESCR_Y_SIZE and DESCR_Y_INCR are NOT present. A 1D transfer consists out of DESCR_X_SIZE.X_COUNT+1 single transfers. The DESCR_NEXT_PTR is at offset 0x14.
14080'2': 2D transfer.
14081The DESCR_X_SIZE, DESCR_X_INCR, DESCR_Y_SIZE and DESCR_Y_INCR registers are present. A 2D transfer consists of (DESCR_X_SIZE.X_COUNT+1)*(DESCR_Y_SIZE.Y_COUNT+1) single transfers. The DESCR_NEXT_PTR is at offset 0x1c.
14082'3': Memory copy.
14083The DESCR_X_SIZE register is present, the DESCR_X_INCR, DESCR_Y_SIZE and DESCR_Y_INCR are NOT present. A memory copy transfer copies DESCR_X_SIZE.X_COUNT+1 Bytes and may use Byte, halfword and word transfers. The DESCR_NEXT_PTR is at offset 0x10.
14084'4': Scatter transfer. The DESCR_X_SIZE register is present, the DESCR_DST, DESCR_X_INCR, DESCR_Y_SIZE and DESCR_Y_INCR are NOT present.
14085'5'-'7': Undefined.
14086
14087After the execution of the current descriptor, the DESCR_NEXT_PTR address is copied to the channel's CH_CURR_PTR address and CH_STATUS.X_IDX and CH_STATUS.Y_IDX are set to '0'.</description>
14088                <bitRange>[30:28]</bitRange>
14089                <access>read-only</access>
14090              </field>
14091            </fields>
14092          </register>
14093          <register>
14094            <name>DESCR_SRC</name>
14095            <description>Channel descriptor source</description>
14096            <addressOffset>0x64</addressOffset>
14097            <size>32</size>
14098            <access>read-only</access>
14099            <resetValue>0x0</resetValue>
14100            <resetMask>0x0</resetMask>
14101            <fields>
14102              <field>
14103                <name>ADDR</name>
14104                <description>Base address of source location.</description>
14105                <bitRange>[31:0]</bitRange>
14106                <access>read-only</access>
14107              </field>
14108            </fields>
14109          </register>
14110          <register>
14111            <name>DESCR_DST</name>
14112            <description>Channel descriptor destination</description>
14113            <addressOffset>0x68</addressOffset>
14114            <size>32</size>
14115            <access>read-only</access>
14116            <resetValue>0x0</resetValue>
14117            <resetMask>0x0</resetMask>
14118            <fields>
14119              <field>
14120                <name>ADDR</name>
14121                <description>Base address of destination location.</description>
14122                <bitRange>[31:0]</bitRange>
14123                <access>read-only</access>
14124              </field>
14125            </fields>
14126          </register>
14127          <register>
14128            <name>DESCR_X_SIZE</name>
14129            <description>Channel descriptor X size</description>
14130            <addressOffset>0x6C</addressOffset>
14131            <size>32</size>
14132            <access>read-only</access>
14133            <resetValue>0x0</resetValue>
14134            <resetMask>0x0</resetMask>
14135            <fields>
14136              <field>
14137                <name>X_COUNT</name>
14138                <description>Number of iterations (minus 1) of the 'X loop' (X_COUNT+1 is the number of single transfers in a 1D transfer). This field is an unsigned number in the range [0, 65535], representing 1 through 65536 iterations.
14139
14140For the 'memory copy' descriptor type, (X_COUNT + 1) is the number of transferred Bytes. For the 'scatter' descriptor type, ceiling(X_COUNT/2) is the number of (address, write data) initialization pairs processed.</description>
14141                <bitRange>[15:0]</bitRange>
14142                <access>read-only</access>
14143              </field>
14144            </fields>
14145          </register>
14146          <register>
14147            <name>DESCR_X_INCR</name>
14148            <description>Channel descriptor X increment</description>
14149            <addressOffset>0x70</addressOffset>
14150            <size>32</size>
14151            <access>read-only</access>
14152            <resetValue>0x0</resetValue>
14153            <resetMask>0x0</resetMask>
14154            <fields>
14155              <field>
14156                <name>SRC_X</name>
14157                <description>Specifies increment of source address for each X loop iteration (in multiples of SRC_TRANSFER_SIZE). This field is a signed number (sign-magnitude format) in the range [-32768, 32767]. If this field is '0', the source address is not incremented. This is useful for reading from RX FIFO structures.</description>
14158                <bitRange>[15:0]</bitRange>
14159                <access>read-only</access>
14160              </field>
14161              <field>
14162                <name>DST_X</name>
14163                <description>Specifies increment of destination address for each X loop iteration (in multiples of DST_TRANSFER_SIZE). This field is a signed number (sign-magnitude format) in the range [-32768, 32767]. If this field is '0', the destination address is not incremented. This is useful for writing to TX FIFO structures.</description>
14164                <bitRange>[31:16]</bitRange>
14165                <access>read-only</access>
14166              </field>
14167            </fields>
14168          </register>
14169          <register>
14170            <name>DESCR_Y_SIZE</name>
14171            <description>Channel descriptor Y size</description>
14172            <addressOffset>0x74</addressOffset>
14173            <size>32</size>
14174            <access>read-only</access>
14175            <resetValue>0x0</resetValue>
14176            <resetMask>0x0</resetMask>
14177            <fields>
14178              <field>
14179                <name>Y_COUNT</name>
14180                <description>Number of iterations (minus 1) of the 'Y loop' (X_COUNT+1)*(Y_COUNT+1) is the number of single transfers in a 2D transfer). This field is an unsigned number in the range [0, 65535], representing 1 through 65536 iterations.</description>
14181                <bitRange>[15:0]</bitRange>
14182                <access>read-only</access>
14183              </field>
14184            </fields>
14185          </register>
14186          <register>
14187            <name>DESCR_Y_INCR</name>
14188            <description>Channel descriptor Y increment</description>
14189            <addressOffset>0x78</addressOffset>
14190            <size>32</size>
14191            <access>read-only</access>
14192            <resetValue>0x0</resetValue>
14193            <resetMask>0x0</resetMask>
14194            <fields>
14195              <field>
14196                <name>SRC_Y</name>
14197                <description>Specifies increment of source address for each Y loop iteration (in multiples of SRC_TRANSFER_SIZE). This field is a signed number in the range [-32768, 32767].</description>
14198                <bitRange>[15:0]</bitRange>
14199                <access>read-only</access>
14200              </field>
14201              <field>
14202                <name>DST_Y</name>
14203                <description>Specifies increment of destination address for each Y loop iteration (in multiples of DST_TRANSFER_SIZE). This field is a signed number in the range [-32768, 32767].</description>
14204                <bitRange>[31:16]</bitRange>
14205                <access>read-only</access>
14206              </field>
14207            </fields>
14208          </register>
14209          <register>
14210            <name>DESCR_NEXT</name>
14211            <description>Channel descriptor next pointer</description>
14212            <addressOffset>0x7C</addressOffset>
14213            <size>32</size>
14214            <access>read-only</access>
14215            <resetValue>0x0</resetValue>
14216            <resetMask>0x0</resetMask>
14217            <fields>
14218              <field>
14219                <name>PTR</name>
14220                <description>Address of next descriptor in descriptor list. When this field is '0', this is the last descriptor in the descriptor list.</description>
14221                <bitRange>[31:2]</bitRange>
14222                <access>read-only</access>
14223              </field>
14224            </fields>
14225          </register>
14226          <register>
14227            <name>INTR</name>
14228            <description>Interrupt</description>
14229            <addressOffset>0x80</addressOffset>
14230            <size>32</size>
14231            <access>read-write</access>
14232            <resetValue>0x0</resetValue>
14233            <resetMask>0xFF</resetMask>
14234            <fields>
14235              <field>
14236                <name>COMPLETION</name>
14237                <description>Activated (set to '1') on completion of data transfer(s) as specified by the descriptor's CH_DESCR_CTL.INTR_TYPE.</description>
14238                <bitRange>[0:0]</bitRange>
14239                <access>read-write</access>
14240              </field>
14241              <field>
14242                <name>SRC_BUS_ERROR</name>
14243                <description>Activated (set to '1') on a bus error for a load from the source.</description>
14244                <bitRange>[1:1]</bitRange>
14245                <access>read-write</access>
14246              </field>
14247              <field>
14248                <name>DST_BUS_ERROR</name>
14249                <description>Activated (set to '1') on a bus error for a store to the destination.</description>
14250                <bitRange>[2:2]</bitRange>
14251                <access>read-write</access>
14252              </field>
14253              <field>
14254                <name>SRC_MISAL</name>
14255                <description>Activated (set to '1') on a misalignment of the source address.</description>
14256                <bitRange>[3:3]</bitRange>
14257                <access>read-write</access>
14258              </field>
14259              <field>
14260                <name>DST_MISAL</name>
14261                <description>Activated (set to '1') on a misalignment of the destination address.</description>
14262                <bitRange>[4:4]</bitRange>
14263                <access>read-write</access>
14264              </field>
14265              <field>
14266                <name>CURR_PTR_NULL</name>
14267                <description>Activated (set to '1') when the channel is enabled (CH_CTL.ENABLED is '1') and CH_CURR_PTR is '0'.</description>
14268                <bitRange>[5:5]</bitRange>
14269                <access>read-write</access>
14270              </field>
14271              <field>
14272                <name>ACTIVE_CH_DISABLED</name>
14273                <description>Activated (set to '1') if the channel is disabled by SW (accidentally/incorrectly) when the data transfer engine is busy.</description>
14274                <bitRange>[6:6]</bitRange>
14275                <access>read-write</access>
14276              </field>
14277              <field>
14278                <name>DESCR_BUS_ERROR</name>
14279                <description>Activated (set to '1') on a bus error for a load of the descriptor.</description>
14280                <bitRange>[7:7]</bitRange>
14281                <access>read-write</access>
14282              </field>
14283            </fields>
14284          </register>
14285          <register>
14286            <name>INTR_SET</name>
14287            <description>Interrupt set</description>
14288            <addressOffset>0x84</addressOffset>
14289            <size>32</size>
14290            <access>read-write</access>
14291            <resetValue>0x0</resetValue>
14292            <resetMask>0xFF</resetMask>
14293            <fields>
14294              <field>
14295                <name>COMPLETION</name>
14296                <description>Write this field with '1' to set INTR.COMPLETION field to '1' (a write of '0' has no effect).</description>
14297                <bitRange>[0:0]</bitRange>
14298                <access>read-write</access>
14299              </field>
14300              <field>
14301                <name>SRC_BUS_ERROR</name>
14302                <description>Write this field with '1' to set INTR.SRC_BUS_ERROR field to '1' (a write of '0' has no effect).</description>
14303                <bitRange>[1:1]</bitRange>
14304                <access>read-write</access>
14305              </field>
14306              <field>
14307                <name>DST_BUS_ERROR</name>
14308                <description>Write this field with '1' to set INTR.DST_BUS_ERROR field to '1' (a write of '0' has no effect).</description>
14309                <bitRange>[2:2]</bitRange>
14310                <access>read-write</access>
14311              </field>
14312              <field>
14313                <name>SRC_MISAL</name>
14314                <description>Write this field with '1' to set INTR.SRC_MISAL field to '1' (a write of '0' has no effect).</description>
14315                <bitRange>[3:3]</bitRange>
14316                <access>read-write</access>
14317              </field>
14318              <field>
14319                <name>DST_MISAL</name>
14320                <description>Write this field with '1' to set INTR.DST_MISAL field to '1' (a write of '0' has no effect).</description>
14321                <bitRange>[4:4]</bitRange>
14322                <access>read-write</access>
14323              </field>
14324              <field>
14325                <name>CURR_PTR_NULL</name>
14326                <description>Write this field with '1' to set INTR.CURR_PTR_NULL field to '1' (a write of '0' has no effect).</description>
14327                <bitRange>[5:5]</bitRange>
14328                <access>read-write</access>
14329              </field>
14330              <field>
14331                <name>ACTIVE_CH_DISABLED</name>
14332                <description>Write this field with '1' to set INTR.ACT_CH_DISABLED field to '1' (a write of '0' has no effect).</description>
14333                <bitRange>[6:6]</bitRange>
14334                <access>read-write</access>
14335              </field>
14336              <field>
14337                <name>DESCR_BUS_ERROR</name>
14338                <description>Write this field with '1' to set INTR.DESCR_BUS_ERROR field to '1' (a write of '0' has no effect).</description>
14339                <bitRange>[7:7]</bitRange>
14340                <access>read-write</access>
14341              </field>
14342            </fields>
14343          </register>
14344          <register>
14345            <name>INTR_MASK</name>
14346            <description>Interrupt mask</description>
14347            <addressOffset>0x88</addressOffset>
14348            <size>32</size>
14349            <access>read-write</access>
14350            <resetValue>0x0</resetValue>
14351            <resetMask>0xFF</resetMask>
14352            <fields>
14353              <field>
14354                <name>COMPLETION</name>
14355                <description>Mask for INTR.COMPLETION interrupt.</description>
14356                <bitRange>[0:0]</bitRange>
14357                <access>read-write</access>
14358              </field>
14359              <field>
14360                <name>SRC_BUS_ERROR</name>
14361                <description>Mask for INTR.SRC_BUS_ERROR interrupt.</description>
14362                <bitRange>[1:1]</bitRange>
14363                <access>read-write</access>
14364              </field>
14365              <field>
14366                <name>DST_BUS_ERROR</name>
14367                <description>Mask for INTR.DST_BUS_ERROR interrupt.</description>
14368                <bitRange>[2:2]</bitRange>
14369                <access>read-write</access>
14370              </field>
14371              <field>
14372                <name>SRC_MISAL</name>
14373                <description>Mask for INTR.SRC_MISAL interrupt.</description>
14374                <bitRange>[3:3]</bitRange>
14375                <access>read-write</access>
14376              </field>
14377              <field>
14378                <name>DST_MISAL</name>
14379                <description>Mask for INTR.DST_MISAL interrupt.</description>
14380                <bitRange>[4:4]</bitRange>
14381                <access>read-write</access>
14382              </field>
14383              <field>
14384                <name>CURR_PTR_NULL</name>
14385                <description>Mask for INTR.CURR_PTR_NULL interrupt.</description>
14386                <bitRange>[5:5]</bitRange>
14387                <access>read-write</access>
14388              </field>
14389              <field>
14390                <name>ACTIVE_CH_DISABLED</name>
14391                <description>Mask for INTR.ACTIVE_CH_DISABLED interrupt.</description>
14392                <bitRange>[6:6]</bitRange>
14393                <access>read-write</access>
14394              </field>
14395              <field>
14396                <name>DESCR_BUS_ERROR</name>
14397                <description>Mask for INTR.DESCR_BUS_ERROR interrupt.</description>
14398                <bitRange>[7:7]</bitRange>
14399                <access>read-write</access>
14400              </field>
14401            </fields>
14402          </register>
14403          <register>
14404            <name>INTR_MASKED</name>
14405            <description>Interrupt masked</description>
14406            <addressOffset>0x8C</addressOffset>
14407            <size>32</size>
14408            <access>read-only</access>
14409            <resetValue>0x0</resetValue>
14410            <resetMask>0xFF</resetMask>
14411            <fields>
14412              <field>
14413                <name>COMPLETION</name>
14414                <description>Logical and of corresponding INTR.COMPLETION and INTR_MASK.COMPLETION fields.</description>
14415                <bitRange>[0:0]</bitRange>
14416                <access>read-only</access>
14417              </field>
14418              <field>
14419                <name>SRC_BUS_ERROR</name>
14420                <description>Logical and of corresponding INTR.SRC_BUS_ERROR and INTR_MASK.SRC_BUS_ERROR fields.</description>
14421                <bitRange>[1:1]</bitRange>
14422                <access>read-only</access>
14423              </field>
14424              <field>
14425                <name>DST_BUS_ERROR</name>
14426                <description>Logical and of corresponding INTR.DST_BUS_ERROR and INTR_MASK.DST_BUS_ERROR fields.</description>
14427                <bitRange>[2:2]</bitRange>
14428                <access>read-only</access>
14429              </field>
14430              <field>
14431                <name>SRC_MISAL</name>
14432                <description>Logical and of corresponding INTR.SRC_MISAL and INTR_MASK.SRC_MISAL fields.</description>
14433                <bitRange>[3:3]</bitRange>
14434                <access>read-only</access>
14435              </field>
14436              <field>
14437                <name>DST_MISAL</name>
14438                <description>Logical and of corresponding INTR.DST_MISAL and INTR_MASK.DST_MISAL fields.</description>
14439                <bitRange>[4:4]</bitRange>
14440                <access>read-only</access>
14441              </field>
14442              <field>
14443                <name>CURR_PTR_NULL</name>
14444                <description>Logical and of corresponding INTR.CURR_PTR_NULL and INTR_MASK.CURR_PTR_NULL fields.</description>
14445                <bitRange>[5:5]</bitRange>
14446                <access>read-only</access>
14447              </field>
14448              <field>
14449                <name>ACTIVE_CH_DISABLED</name>
14450                <description>Logical and of corresponding INTR.ACTIVE_CH_DISABLED and INTR_MASK.ACTIVE_CH_DISABLED fields.</description>
14451                <bitRange>[6:6]</bitRange>
14452                <access>read-only</access>
14453              </field>
14454              <field>
14455                <name>DESCR_BUS_ERROR</name>
14456                <description>Logical and of corresponding INTR.DESCR_BUS_ERROR and INTR_MASK.DESCR_BUS_ERROR fields.</description>
14457                <bitRange>[7:7]</bitRange>
14458                <access>read-only</access>
14459              </field>
14460            </fields>
14461          </register>
14462        </cluster>
14463      </registers>
14464    </peripheral>
14465    <peripheral>
14466      <name>EFUSE</name>
14467      <description>EFUSE MXS40 registers</description>
14468      <baseAddress>0x402C0000</baseAddress>
14469      <addressBlock>
14470        <offset>0</offset>
14471        <size>128</size>
14472        <usage>registers</usage>
14473      </addressBlock>
14474      <registers>
14475        <register>
14476          <name>CTL</name>
14477          <description>Control</description>
14478          <addressOffset>0x0</addressOffset>
14479          <size>32</size>
14480          <access>read-write</access>
14481          <resetValue>0x0</resetValue>
14482          <resetMask>0x80000000</resetMask>
14483          <fields>
14484            <field>
14485              <name>ENABLED</name>
14486              <description>IP enable:
14487'0': Disabled. All non-retention registers (command and status registers) are reset to their default value when the IP is disabled. All retention registers retain their value when the IP is disabled.
14488'1': Enabled.</description>
14489              <bitRange>[31:31]</bitRange>
14490              <access>read-write</access>
14491            </field>
14492          </fields>
14493        </register>
14494        <register>
14495          <name>CMD</name>
14496          <description>Command</description>
14497          <addressOffset>0x10</addressOffset>
14498          <size>32</size>
14499          <access>read-write</access>
14500          <resetValue>0x1</resetValue>
14501          <resetMask>0x800F1F71</resetMask>
14502          <fields>
14503            <field>
14504              <name>BIT_DATA</name>
14505              <description>Bit data. This field specifies the bit value that is to be programmed into the eFUSE macro array. The address of the bit is specified by the BIT_ADDR, BYTE_ADDR, and MACRO_ADDR fields. This bit is a don't care for the MXS40 Macro.</description>
14506              <bitRange>[0:0]</bitRange>
14507              <access>read-write</access>
14508            </field>
14509            <field>
14510              <name>BIT_ADDR</name>
14511              <description>Bit address. This field specifies a bit within a Byte.</description>
14512              <bitRange>[6:4]</bitRange>
14513              <access>read-write</access>
14514            </field>
14515            <field>
14516              <name>BYTE_ADDR</name>
14517              <description>Byte address. This field specifies a Byte within a eFUSE macro (each macro has 32 B).</description>
14518              <bitRange>[12:8]</bitRange>
14519              <access>read-write</access>
14520            </field>
14521            <field>
14522              <name>MACRO_ADDR</name>
14523              <description>Macro address. This field specifies an eFUSE macro.</description>
14524              <bitRange>[19:16]</bitRange>
14525              <access>read-write</access>
14526            </field>
14527            <field>
14528              <name>START</name>
14529              <description>FW sets this field to '1' to start a program operation. HW sets this field to '0' to indicate that the operation has completed.
14530
14531Note: it is good practice to verify the result of a program operation by reading back a programmed eFUSE memory location. Programming can only change an eFUSE memory bit from '0' to '1'; i.e. a programming operation is a 'one-off' operation for each eFUSE memory bit: once a bit is changed to '1', it can NEVER be changed back to '0' as a hardware fuse is blown.
14532
14533Programming a memory bit to '1' requires blowing a fuse and requires an eFUSE macro operation. Therefore, this programmiong operation takes time (as specified by the SEQ_PROGRAM_CTL reguisters). Programming amemory bit to '0' does not require an eFUSE macro operation (it is the default eFUSE macro state). Therefore, this programming operation is almost instantaneous.
14534
14535Note: during a program operation, a read operation can not be performed. An AHB-Lite read transfer to the eFUSE memory during a program operation results in an AHB-Lite bus error.</description>
14536              <bitRange>[31:31]</bitRange>
14537              <access>read-write</access>
14538            </field>
14539          </fields>
14540        </register>
14541        <register>
14542          <name>SEQ_DEFAULT</name>
14543          <description>Sequencer Default value</description>
14544          <addressOffset>0x20</addressOffset>
14545          <size>32</size>
14546          <access>read-write</access>
14547          <resetValue>0x1D0000</resetValue>
14548          <resetMask>0x7F0000</resetMask>
14549          <fields>
14550            <field>
14551              <name>STROBE_A</name>
14552              <description>Specifies value of eFUSE control signal strobe_f</description>
14553              <bitRange>[16:16]</bitRange>
14554              <access>read-write</access>
14555            </field>
14556            <field>
14557              <name>STROBE_B</name>
14558              <description>Specifies value of eFUSEcontrol signal strobe_b</description>
14559              <bitRange>[17:17]</bitRange>
14560              <access>read-write</access>
14561            </field>
14562            <field>
14563              <name>STROBE_C</name>
14564              <description>Specifies value of eFUSE control signal strobe_c</description>
14565              <bitRange>[18:18]</bitRange>
14566              <access>read-write</access>
14567            </field>
14568            <field>
14569              <name>STROBE_D</name>
14570              <description>Specifies value of eFUSE control signal strobe_d</description>
14571              <bitRange>[19:19]</bitRange>
14572              <access>read-write</access>
14573            </field>
14574            <field>
14575              <name>STROBE_E</name>
14576              <description>Specifies value of eFUSE control signal strobe_e</description>
14577              <bitRange>[20:20]</bitRange>
14578              <access>read-write</access>
14579            </field>
14580            <field>
14581              <name>STROBE_F</name>
14582              <description>Specifies value of eFUSE control signal strobe_f</description>
14583              <bitRange>[21:21]</bitRange>
14584              <access>read-write</access>
14585            </field>
14586            <field>
14587              <name>STROBE_G</name>
14588              <description>Specifies value of eFUSE control signal strobe_g</description>
14589              <bitRange>[22:22]</bitRange>
14590              <access>read-write</access>
14591            </field>
14592          </fields>
14593        </register>
14594        <register>
14595          <name>SEQ_READ_CTL_0</name>
14596          <description>Sequencer read control 0</description>
14597          <addressOffset>0x40</addressOffset>
14598          <size>32</size>
14599          <access>read-write</access>
14600          <resetValue>0x80560001</resetValue>
14601          <resetMask>0x807F03FF</resetMask>
14602          <fields>
14603            <field>
14604              <name>CYCLES</name>
14605              <description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.</description>
14606              <bitRange>[9:0]</bitRange>
14607              <access>read-write</access>
14608            </field>
14609            <field>
14610              <name>STROBE_A</name>
14611              <description>Specifies value of eFUSE control signal strobe_f</description>
14612              <bitRange>[16:16]</bitRange>
14613              <access>read-write</access>
14614            </field>
14615            <field>
14616              <name>STROBE_B</name>
14617              <description>Specifies value of eFUSEcontrol signal strobe_b</description>
14618              <bitRange>[17:17]</bitRange>
14619              <access>read-write</access>
14620            </field>
14621            <field>
14622              <name>STROBE_C</name>
14623              <description>Specifies value of eFUSE control signal strobe_c</description>
14624              <bitRange>[18:18]</bitRange>
14625              <access>read-write</access>
14626            </field>
14627            <field>
14628              <name>STROBE_D</name>
14629              <description>Specifies value of eFUSE control signal strobe_d</description>
14630              <bitRange>[19:19]</bitRange>
14631              <access>read-write</access>
14632            </field>
14633            <field>
14634              <name>STROBE_E</name>
14635              <description>Specifies value of eFUSE control signal strobe_e</description>
14636              <bitRange>[20:20]</bitRange>
14637              <access>read-write</access>
14638            </field>
14639            <field>
14640              <name>STROBE_F</name>
14641              <description>Specifies value of eFUSE control signal strobe_f</description>
14642              <bitRange>[21:21]</bitRange>
14643              <access>read-write</access>
14644            </field>
14645            <field>
14646              <name>STROBE_G</name>
14647              <description>Specifies value of eFUSE control signal strobe_g</description>
14648              <bitRange>[22:22]</bitRange>
14649              <access>read-write</access>
14650            </field>
14651            <field>
14652              <name>DONE</name>
14653              <description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0.</description>
14654              <bitRange>[31:31]</bitRange>
14655              <access>read-write</access>
14656            </field>
14657          </fields>
14658        </register>
14659        <register>
14660          <name>SEQ_READ_CTL_1</name>
14661          <description>Sequencer read control 1</description>
14662          <addressOffset>0x44</addressOffset>
14663          <size>32</size>
14664          <access>read-write</access>
14665          <resetValue>0x540004</resetValue>
14666          <resetMask>0x807F03FF</resetMask>
14667          <fields>
14668            <field>
14669              <name>CYCLES</name>
14670              <description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.</description>
14671              <bitRange>[9:0]</bitRange>
14672              <access>read-write</access>
14673            </field>
14674            <field>
14675              <name>STROBE_A</name>
14676              <description>Specifies value of eFUSE control signal strobe_f</description>
14677              <bitRange>[16:16]</bitRange>
14678              <access>read-write</access>
14679            </field>
14680            <field>
14681              <name>STROBE_B</name>
14682              <description>Specifies value of eFUSEcontrol signal strobe_b</description>
14683              <bitRange>[17:17]</bitRange>
14684              <access>read-write</access>
14685            </field>
14686            <field>
14687              <name>STROBE_C</name>
14688              <description>Specifies value of eFUSE control signal strobe_c</description>
14689              <bitRange>[18:18]</bitRange>
14690              <access>read-write</access>
14691            </field>
14692            <field>
14693              <name>STROBE_D</name>
14694              <description>Specifies value of eFUSE control signal strobe_d</description>
14695              <bitRange>[19:19]</bitRange>
14696              <access>read-write</access>
14697            </field>
14698            <field>
14699              <name>STROBE_E</name>
14700              <description>Specifies value of eFUSE control signal strobe_e</description>
14701              <bitRange>[20:20]</bitRange>
14702              <access>read-write</access>
14703            </field>
14704            <field>
14705              <name>STROBE_F</name>
14706              <description>Specifies value of eFUSE control signal strobe_f</description>
14707              <bitRange>[21:21]</bitRange>
14708              <access>read-write</access>
14709            </field>
14710            <field>
14711              <name>STROBE_G</name>
14712              <description>Specifies value of eFUSE control signal strobe_g</description>
14713              <bitRange>[22:22]</bitRange>
14714              <access>read-write</access>
14715            </field>
14716            <field>
14717              <name>DONE</name>
14718              <description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0.</description>
14719              <bitRange>[31:31]</bitRange>
14720              <access>read-write</access>
14721            </field>
14722          </fields>
14723        </register>
14724        <register>
14725          <name>SEQ_READ_CTL_2</name>
14726          <description>Sequencer read control 2</description>
14727          <addressOffset>0x48</addressOffset>
14728          <size>32</size>
14729          <access>read-write</access>
14730          <resetValue>0x560001</resetValue>
14731          <resetMask>0x807F03FF</resetMask>
14732          <fields>
14733            <field>
14734              <name>CYCLES</name>
14735              <description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.</description>
14736              <bitRange>[9:0]</bitRange>
14737              <access>read-write</access>
14738            </field>
14739            <field>
14740              <name>STROBE_A</name>
14741              <description>Specifies value of eFUSE control signal strobe_f</description>
14742              <bitRange>[16:16]</bitRange>
14743              <access>read-write</access>
14744            </field>
14745            <field>
14746              <name>STROBE_B</name>
14747              <description>Specifies value of eFUSEcontrol signal strobe_b</description>
14748              <bitRange>[17:17]</bitRange>
14749              <access>read-write</access>
14750            </field>
14751            <field>
14752              <name>STROBE_C</name>
14753              <description>Specifies value of eFUSE control signal strobe_c</description>
14754              <bitRange>[18:18]</bitRange>
14755              <access>read-write</access>
14756            </field>
14757            <field>
14758              <name>STROBE_D</name>
14759              <description>Specifies value of eFUSE control signal strobe_d</description>
14760              <bitRange>[19:19]</bitRange>
14761              <access>read-write</access>
14762            </field>
14763            <field>
14764              <name>STROBE_E</name>
14765              <description>Specifies value of eFUSE control signal strobe_e</description>
14766              <bitRange>[20:20]</bitRange>
14767              <access>read-write</access>
14768            </field>
14769            <field>
14770              <name>STROBE_F</name>
14771              <description>Specifies value of eFUSE control signal strobe_f</description>
14772              <bitRange>[21:21]</bitRange>
14773              <access>read-write</access>
14774            </field>
14775            <field>
14776              <name>STROBE_G</name>
14777              <description>Specifies value of eFUSE control signal strobe_g</description>
14778              <bitRange>[22:22]</bitRange>
14779              <access>read-write</access>
14780            </field>
14781            <field>
14782              <name>DONE</name>
14783              <description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0.</description>
14784              <bitRange>[31:31]</bitRange>
14785              <access>read-write</access>
14786            </field>
14787          </fields>
14788        </register>
14789        <register>
14790          <name>SEQ_READ_CTL_3</name>
14791          <description>Sequencer read control 3</description>
14792          <addressOffset>0x4C</addressOffset>
14793          <size>32</size>
14794          <access>read-write</access>
14795          <resetValue>0x540003</resetValue>
14796          <resetMask>0x807F03FF</resetMask>
14797          <fields>
14798            <field>
14799              <name>CYCLES</name>
14800              <description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.</description>
14801              <bitRange>[9:0]</bitRange>
14802              <access>read-write</access>
14803            </field>
14804            <field>
14805              <name>STROBE_A</name>
14806              <description>Specifies value of eFUSE control signal strobe_f</description>
14807              <bitRange>[16:16]</bitRange>
14808              <access>read-write</access>
14809            </field>
14810            <field>
14811              <name>STROBE_B</name>
14812              <description>Specifies value of eFUSEcontrol signal strobe_b</description>
14813              <bitRange>[17:17]</bitRange>
14814              <access>read-write</access>
14815            </field>
14816            <field>
14817              <name>STROBE_C</name>
14818              <description>Specifies value of eFUSE control signal strobe_c</description>
14819              <bitRange>[18:18]</bitRange>
14820              <access>read-write</access>
14821            </field>
14822            <field>
14823              <name>STROBE_D</name>
14824              <description>Specifies value of eFUSE control signal strobe_d</description>
14825              <bitRange>[19:19]</bitRange>
14826              <access>read-write</access>
14827            </field>
14828            <field>
14829              <name>STROBE_E</name>
14830              <description>Specifies value of eFUSE control signal strobe_e</description>
14831              <bitRange>[20:20]</bitRange>
14832              <access>read-write</access>
14833            </field>
14834            <field>
14835              <name>STROBE_F</name>
14836              <description>Specifies value of eFUSE control signal strobe_f</description>
14837              <bitRange>[21:21]</bitRange>
14838              <access>read-write</access>
14839            </field>
14840            <field>
14841              <name>STROBE_G</name>
14842              <description>Specifies value of eFUSE control signal strobe_g</description>
14843              <bitRange>[22:22]</bitRange>
14844              <access>read-write</access>
14845            </field>
14846            <field>
14847              <name>DONE</name>
14848              <description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0.</description>
14849              <bitRange>[31:31]</bitRange>
14850              <access>read-write</access>
14851            </field>
14852          </fields>
14853        </register>
14854        <register>
14855          <name>SEQ_READ_CTL_4</name>
14856          <description>Sequencer read control 4</description>
14857          <addressOffset>0x50</addressOffset>
14858          <size>32</size>
14859          <access>read-write</access>
14860          <resetValue>0x80150001</resetValue>
14861          <resetMask>0x807F03FF</resetMask>
14862          <fields>
14863            <field>
14864              <name>CYCLES</name>
14865              <description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.</description>
14866              <bitRange>[9:0]</bitRange>
14867              <access>read-write</access>
14868            </field>
14869            <field>
14870              <name>STROBE_A</name>
14871              <description>Specifies value of eFUSE control signal strobe_f</description>
14872              <bitRange>[16:16]</bitRange>
14873              <access>read-write</access>
14874            </field>
14875            <field>
14876              <name>STROBE_B</name>
14877              <description>Specifies value of eFUSEcontrol signal strobe_b</description>
14878              <bitRange>[17:17]</bitRange>
14879              <access>read-write</access>
14880            </field>
14881            <field>
14882              <name>STROBE_C</name>
14883              <description>Specifies value of eFUSE control signal strobe_c</description>
14884              <bitRange>[18:18]</bitRange>
14885              <access>read-write</access>
14886            </field>
14887            <field>
14888              <name>STROBE_D</name>
14889              <description>Specifies value of eFUSE control signal strobe_d</description>
14890              <bitRange>[19:19]</bitRange>
14891              <access>read-write</access>
14892            </field>
14893            <field>
14894              <name>STROBE_E</name>
14895              <description>Specifies value of eFUSE control signal strobe_e</description>
14896              <bitRange>[20:20]</bitRange>
14897              <access>read-write</access>
14898            </field>
14899            <field>
14900              <name>STROBE_F</name>
14901              <description>Specifies value of eFUSE control signal strobe_f</description>
14902              <bitRange>[21:21]</bitRange>
14903              <access>read-write</access>
14904            </field>
14905            <field>
14906              <name>STROBE_G</name>
14907              <description>Specifies value of eFUSE control signal strobe_g</description>
14908              <bitRange>[22:22]</bitRange>
14909              <access>read-write</access>
14910            </field>
14911            <field>
14912              <name>DONE</name>
14913              <description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0.</description>
14914              <bitRange>[31:31]</bitRange>
14915              <access>read-write</access>
14916            </field>
14917          </fields>
14918        </register>
14919        <register>
14920          <name>SEQ_READ_CTL_5</name>
14921          <description>Sequencer read control 5</description>
14922          <addressOffset>0x54</addressOffset>
14923          <size>32</size>
14924          <access>read-write</access>
14925          <resetValue>0x310004</resetValue>
14926          <resetMask>0x807F03FF</resetMask>
14927          <fields>
14928            <field>
14929              <name>CYCLES</name>
14930              <description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.</description>
14931              <bitRange>[9:0]</bitRange>
14932              <access>read-write</access>
14933            </field>
14934            <field>
14935              <name>STROBE_A</name>
14936              <description>Specifies value of eFUSE control signal strobe_f</description>
14937              <bitRange>[16:16]</bitRange>
14938              <access>read-write</access>
14939            </field>
14940            <field>
14941              <name>STROBE_B</name>
14942              <description>Specifies value of eFUSEcontrol signal strobe_b</description>
14943              <bitRange>[17:17]</bitRange>
14944              <access>read-write</access>
14945            </field>
14946            <field>
14947              <name>STROBE_C</name>
14948              <description>Specifies value of eFUSE control signal strobe_c</description>
14949              <bitRange>[18:18]</bitRange>
14950              <access>read-write</access>
14951            </field>
14952            <field>
14953              <name>STROBE_D</name>
14954              <description>Specifies value of eFUSE control signal strobe_d</description>
14955              <bitRange>[19:19]</bitRange>
14956              <access>read-write</access>
14957            </field>
14958            <field>
14959              <name>STROBE_E</name>
14960              <description>Specifies value of eFUSE control signal strobe_e</description>
14961              <bitRange>[20:20]</bitRange>
14962              <access>read-write</access>
14963            </field>
14964            <field>
14965              <name>STROBE_F</name>
14966              <description>Specifies value of eFUSE control signal strobe_f</description>
14967              <bitRange>[21:21]</bitRange>
14968              <access>read-write</access>
14969            </field>
14970            <field>
14971              <name>STROBE_G</name>
14972              <description>Specifies value of eFUSE control signal strobe_g</description>
14973              <bitRange>[22:22]</bitRange>
14974              <access>read-write</access>
14975            </field>
14976            <field>
14977              <name>DONE</name>
14978              <description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0.</description>
14979              <bitRange>[31:31]</bitRange>
14980              <access>read-write</access>
14981            </field>
14982          </fields>
14983        </register>
14984        <register>
14985          <name>SEQ_PROGRAM_CTL_0</name>
14986          <description>Sequencer program control 0</description>
14987          <addressOffset>0x60</addressOffset>
14988          <size>32</size>
14989          <access>read-write</access>
14990          <resetValue>0x200001</resetValue>
14991          <resetMask>0x807F03FF</resetMask>
14992          <fields>
14993            <field>
14994              <name>CYCLES</name>
14995              <description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.</description>
14996              <bitRange>[9:0]</bitRange>
14997              <access>read-write</access>
14998            </field>
14999            <field>
15000              <name>STROBE_A</name>
15001              <description>Specifies value of eFUSE control signal strobe_a</description>
15002              <bitRange>[16:16]</bitRange>
15003              <access>read-write</access>
15004            </field>
15005            <field>
15006              <name>STROBE_B</name>
15007              <description>Specifies value of eFUSEcontrol signal strobe_b</description>
15008              <bitRange>[17:17]</bitRange>
15009              <access>read-write</access>
15010            </field>
15011            <field>
15012              <name>STROBE_C</name>
15013              <description>Specifies value of eFUSE control signal strobe_c</description>
15014              <bitRange>[18:18]</bitRange>
15015              <access>read-write</access>
15016            </field>
15017            <field>
15018              <name>STROBE_D</name>
15019              <description>Specifies value of eFUSE control signal strobe_d</description>
15020              <bitRange>[19:19]</bitRange>
15021              <access>read-write</access>
15022            </field>
15023            <field>
15024              <name>STROBE_E</name>
15025              <description>Specifies value of eFUSE control signal strobe_e</description>
15026              <bitRange>[20:20]</bitRange>
15027              <access>read-write</access>
15028            </field>
15029            <field>
15030              <name>STROBE_F</name>
15031              <description>Specifies value of eFUSE control signal strobe_f</description>
15032              <bitRange>[21:21]</bitRange>
15033              <access>read-write</access>
15034            </field>
15035            <field>
15036              <name>STROBE_G</name>
15037              <description>Specifies value of eFUSE control signal strobe_g</description>
15038              <bitRange>[22:22]</bitRange>
15039              <access>read-write</access>
15040            </field>
15041            <field>
15042              <name>DONE</name>
15043              <description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0.</description>
15044              <bitRange>[31:31]</bitRange>
15045              <access>read-write</access>
15046            </field>
15047          </fields>
15048        </register>
15049        <register>
15050          <name>SEQ_PROGRAM_CTL_1</name>
15051          <description>Sequencer program control 1</description>
15052          <addressOffset>0x64</addressOffset>
15053          <size>32</size>
15054          <access>read-write</access>
15055          <resetValue>0x220020</resetValue>
15056          <resetMask>0x807F03FF</resetMask>
15057          <fields>
15058            <field>
15059              <name>CYCLES</name>
15060              <description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.</description>
15061              <bitRange>[9:0]</bitRange>
15062              <access>read-write</access>
15063            </field>
15064            <field>
15065              <name>STROBE_A</name>
15066              <description>Specifies value of eFUSE control signal strobe_a</description>
15067              <bitRange>[16:16]</bitRange>
15068              <access>read-write</access>
15069            </field>
15070            <field>
15071              <name>STROBE_B</name>
15072              <description>Specifies value of eFUSEcontrol signal strobe_b</description>
15073              <bitRange>[17:17]</bitRange>
15074              <access>read-write</access>
15075            </field>
15076            <field>
15077              <name>STROBE_C</name>
15078              <description>Specifies value of eFUSE control signal strobe_c</description>
15079              <bitRange>[18:18]</bitRange>
15080              <access>read-write</access>
15081            </field>
15082            <field>
15083              <name>STROBE_D</name>
15084              <description>Specifies value of eFUSE control signal strobe_d</description>
15085              <bitRange>[19:19]</bitRange>
15086              <access>read-write</access>
15087            </field>
15088            <field>
15089              <name>STROBE_E</name>
15090              <description>Specifies value of eFUSE control signal strobe_e</description>
15091              <bitRange>[20:20]</bitRange>
15092              <access>read-write</access>
15093            </field>
15094            <field>
15095              <name>STROBE_F</name>
15096              <description>Specifies value of eFUSE control signal strobe_f</description>
15097              <bitRange>[21:21]</bitRange>
15098              <access>read-write</access>
15099            </field>
15100            <field>
15101              <name>STROBE_G</name>
15102              <description>Specifies value of eFUSE control signal strobe_g</description>
15103              <bitRange>[22:22]</bitRange>
15104              <access>read-write</access>
15105            </field>
15106            <field>
15107              <name>DONE</name>
15108              <description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0.</description>
15109              <bitRange>[31:31]</bitRange>
15110              <access>read-write</access>
15111            </field>
15112          </fields>
15113        </register>
15114        <register>
15115          <name>SEQ_PROGRAM_CTL_2</name>
15116          <description>Sequencer program control 2</description>
15117          <addressOffset>0x68</addressOffset>
15118          <size>32</size>
15119          <access>read-write</access>
15120          <resetValue>0x200001</resetValue>
15121          <resetMask>0x807F03FF</resetMask>
15122          <fields>
15123            <field>
15124              <name>CYCLES</name>
15125              <description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.</description>
15126              <bitRange>[9:0]</bitRange>
15127              <access>read-write</access>
15128            </field>
15129            <field>
15130              <name>STROBE_A</name>
15131              <description>Specifies value of eFUSE control signal strobe_a</description>
15132              <bitRange>[16:16]</bitRange>
15133              <access>read-write</access>
15134            </field>
15135            <field>
15136              <name>STROBE_B</name>
15137              <description>Specifies value of eFUSEcontrol signal strobe_b</description>
15138              <bitRange>[17:17]</bitRange>
15139              <access>read-write</access>
15140            </field>
15141            <field>
15142              <name>STROBE_C</name>
15143              <description>Specifies value of eFUSE control signal strobe_c</description>
15144              <bitRange>[18:18]</bitRange>
15145              <access>read-write</access>
15146            </field>
15147            <field>
15148              <name>STROBE_D</name>
15149              <description>Specifies value of eFUSE control signal strobe_d</description>
15150              <bitRange>[19:19]</bitRange>
15151              <access>read-write</access>
15152            </field>
15153            <field>
15154              <name>STROBE_E</name>
15155              <description>Specifies value of eFUSE control signal strobe_e</description>
15156              <bitRange>[20:20]</bitRange>
15157              <access>read-write</access>
15158            </field>
15159            <field>
15160              <name>STROBE_F</name>
15161              <description>Specifies value of eFUSE control signal strobe_f</description>
15162              <bitRange>[21:21]</bitRange>
15163              <access>read-write</access>
15164            </field>
15165            <field>
15166              <name>STROBE_G</name>
15167              <description>Specifies value of eFUSE control signal strobe_g</description>
15168              <bitRange>[22:22]</bitRange>
15169              <access>read-write</access>
15170            </field>
15171            <field>
15172              <name>DONE</name>
15173              <description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0.</description>
15174              <bitRange>[31:31]</bitRange>
15175              <access>read-write</access>
15176            </field>
15177          </fields>
15178        </register>
15179        <register>
15180          <name>SEQ_PROGRAM_CTL_3</name>
15181          <description>Sequencer program control 3</description>
15182          <addressOffset>0x6C</addressOffset>
15183          <size>32</size>
15184          <access>read-write</access>
15185          <resetValue>0x310005</resetValue>
15186          <resetMask>0x807F03FF</resetMask>
15187          <fields>
15188            <field>
15189              <name>CYCLES</name>
15190              <description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.</description>
15191              <bitRange>[9:0]</bitRange>
15192              <access>read-write</access>
15193            </field>
15194            <field>
15195              <name>STROBE_A</name>
15196              <description>Specifies value of eFUSE control signal strobe_a</description>
15197              <bitRange>[16:16]</bitRange>
15198              <access>read-write</access>
15199            </field>
15200            <field>
15201              <name>STROBE_B</name>
15202              <description>Specifies value of eFUSEcontrol signal strobe_b</description>
15203              <bitRange>[17:17]</bitRange>
15204              <access>read-write</access>
15205            </field>
15206            <field>
15207              <name>STROBE_C</name>
15208              <description>Specifies value of eFUSE control signal strobe_c</description>
15209              <bitRange>[18:18]</bitRange>
15210              <access>read-write</access>
15211            </field>
15212            <field>
15213              <name>STROBE_D</name>
15214              <description>Specifies value of eFUSE control signal strobe_d</description>
15215              <bitRange>[19:19]</bitRange>
15216              <access>read-write</access>
15217            </field>
15218            <field>
15219              <name>STROBE_E</name>
15220              <description>Specifies value of eFUSE control signal strobe_e</description>
15221              <bitRange>[20:20]</bitRange>
15222              <access>read-write</access>
15223            </field>
15224            <field>
15225              <name>STROBE_F</name>
15226              <description>Specifies value of eFUSE control signal strobe_f</description>
15227              <bitRange>[21:21]</bitRange>
15228              <access>read-write</access>
15229            </field>
15230            <field>
15231              <name>STROBE_G</name>
15232              <description>Specifies value of eFUSE control signal strobe_g</description>
15233              <bitRange>[22:22]</bitRange>
15234              <access>read-write</access>
15235            </field>
15236            <field>
15237              <name>DONE</name>
15238              <description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0.</description>
15239              <bitRange>[31:31]</bitRange>
15240              <access>read-write</access>
15241            </field>
15242          </fields>
15243        </register>
15244        <register>
15245          <name>SEQ_PROGRAM_CTL_4</name>
15246          <description>Sequencer program control 4</description>
15247          <addressOffset>0x70</addressOffset>
15248          <size>32</size>
15249          <access>read-write</access>
15250          <resetValue>0x80350006</resetValue>
15251          <resetMask>0x807F03FF</resetMask>
15252          <fields>
15253            <field>
15254              <name>CYCLES</name>
15255              <description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.</description>
15256              <bitRange>[9:0]</bitRange>
15257              <access>read-write</access>
15258            </field>
15259            <field>
15260              <name>STROBE_A</name>
15261              <description>Specifies value of eFUSE control signal strobe_a</description>
15262              <bitRange>[16:16]</bitRange>
15263              <access>read-write</access>
15264            </field>
15265            <field>
15266              <name>STROBE_B</name>
15267              <description>Specifies value of eFUSEcontrol signal strobe_b</description>
15268              <bitRange>[17:17]</bitRange>
15269              <access>read-write</access>
15270            </field>
15271            <field>
15272              <name>STROBE_C</name>
15273              <description>Specifies value of eFUSE control signal strobe_c</description>
15274              <bitRange>[18:18]</bitRange>
15275              <access>read-write</access>
15276            </field>
15277            <field>
15278              <name>STROBE_D</name>
15279              <description>Specifies value of eFUSE control signal strobe_d</description>
15280              <bitRange>[19:19]</bitRange>
15281              <access>read-write</access>
15282            </field>
15283            <field>
15284              <name>STROBE_E</name>
15285              <description>Specifies value of eFUSE control signal strobe_e</description>
15286              <bitRange>[20:20]</bitRange>
15287              <access>read-write</access>
15288            </field>
15289            <field>
15290              <name>STROBE_F</name>
15291              <description>Specifies value of eFUSE control signal strobe_f</description>
15292              <bitRange>[21:21]</bitRange>
15293              <access>read-write</access>
15294            </field>
15295            <field>
15296              <name>STROBE_G</name>
15297              <description>Specifies value of eFUSE control signal strobe_g</description>
15298              <bitRange>[22:22]</bitRange>
15299              <access>read-write</access>
15300            </field>
15301            <field>
15302              <name>DONE</name>
15303              <description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0.</description>
15304              <bitRange>[31:31]</bitRange>
15305              <access>read-write</access>
15306            </field>
15307          </fields>
15308        </register>
15309        <register>
15310          <name>SEQ_PROGRAM_CTL_5</name>
15311          <description>Sequencer program control 5</description>
15312          <addressOffset>0x74</addressOffset>
15313          <size>32</size>
15314          <access>read-write</access>
15315          <resetValue>0x803D0019</resetValue>
15316          <resetMask>0x807F03FF</resetMask>
15317          <fields>
15318            <field>
15319              <name>CYCLES</name>
15320              <description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.</description>
15321              <bitRange>[9:0]</bitRange>
15322              <access>read-write</access>
15323            </field>
15324            <field>
15325              <name>STROBE_A</name>
15326              <description>Specifies value of eFUSE control signal strobe_a</description>
15327              <bitRange>[16:16]</bitRange>
15328              <access>read-write</access>
15329            </field>
15330            <field>
15331              <name>STROBE_B</name>
15332              <description>Specifies value of eFUSEcontrol signal strobe_b</description>
15333              <bitRange>[17:17]</bitRange>
15334              <access>read-write</access>
15335            </field>
15336            <field>
15337              <name>STROBE_C</name>
15338              <description>Specifies value of eFUSE control signal strobe_c</description>
15339              <bitRange>[18:18]</bitRange>
15340              <access>read-write</access>
15341            </field>
15342            <field>
15343              <name>STROBE_D</name>
15344              <description>Specifies value of eFUSE control signal strobe_d</description>
15345              <bitRange>[19:19]</bitRange>
15346              <access>read-write</access>
15347            </field>
15348            <field>
15349              <name>STROBE_E</name>
15350              <description>Specifies value of eFUSE control signal strobe_e</description>
15351              <bitRange>[20:20]</bitRange>
15352              <access>read-write</access>
15353            </field>
15354            <field>
15355              <name>STROBE_F</name>
15356              <description>Specifies value of eFUSE control signal strobe_f</description>
15357              <bitRange>[21:21]</bitRange>
15358              <access>read-write</access>
15359            </field>
15360            <field>
15361              <name>STROBE_G</name>
15362              <description>Specifies value of eFUSE control signal strobe_g</description>
15363              <bitRange>[22:22]</bitRange>
15364              <access>read-write</access>
15365            </field>
15366            <field>
15367              <name>DONE</name>
15368              <description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0.</description>
15369              <bitRange>[31:31]</bitRange>
15370              <access>read-write</access>
15371            </field>
15372          </fields>
15373        </register>
15374      </registers>
15375    </peripheral>
15376    <peripheral>
15377      <name>HSIOM</name>
15378      <description>High Speed IO Matrix (HSIOM)</description>
15379      <baseAddress>0x40300000</baseAddress>
15380      <addressBlock>
15381        <offset>0</offset>
15382        <size>16384</size>
15383        <usage>registers</usage>
15384      </addressBlock>
15385      <registers>
15386        <cluster>
15387          <dim>14</dim>
15388          <dimIncrement>16</dimIncrement>
15389          <name>PRT[%s]</name>
15390          <description>HSIOM port registers</description>
15391          <addressOffset>0x00000000</addressOffset>
15392          <register>
15393            <name>PORT_SEL0</name>
15394            <description>Port selection 0</description>
15395            <addressOffset>0x0</addressOffset>
15396            <size>32</size>
15397            <access>read-write</access>
15398            <resetValue>0x0</resetValue>
15399            <resetMask>0x1F1F1F1F</resetMask>
15400            <fields>
15401              <field>
15402                <name>IO0_SEL</name>
15403                <description>Selects connection for IO pin 0 route.</description>
15404                <bitRange>[4:0]</bitRange>
15405                <access>read-write</access>
15406                <enumeratedValues>
15407                  <enumeratedValue>
15408                    <name>GPIO</name>
15409                    <description>GPIO controls 'out'</description>
15410                    <value>0</value>
15411                  </enumeratedValue>
15412                  <enumeratedValue>
15413                    <name>GPIO_DSI</name>
15414                    <description>GPIO controls 'out', DSI controls 'output enable'</description>
15415                    <value>1</value>
15416                  </enumeratedValue>
15417                  <enumeratedValue>
15418                    <name>DSI_DSI</name>
15419                    <description>DSI controls 'out' and 'output enable'</description>
15420                    <value>2</value>
15421                  </enumeratedValue>
15422                  <enumeratedValue>
15423                    <name>DSI_GPIO</name>
15424                    <description>DSI controls 'out', GPIO controls 'output enable'</description>
15425                    <value>3</value>
15426                  </enumeratedValue>
15427                  <enumeratedValue>
15428                    <name>AMUXA</name>
15429                    <description>Analog mux bus A</description>
15430                    <value>4</value>
15431                  </enumeratedValue>
15432                  <enumeratedValue>
15433                    <name>AMUXB</name>
15434                    <description>Analog mux bus B</description>
15435                    <value>5</value>
15436                  </enumeratedValue>
15437                  <enumeratedValue>
15438                    <name>AMUXA_DSI</name>
15439                    <description>Analog mux bus A, DSI control</description>
15440                    <value>6</value>
15441                  </enumeratedValue>
15442                  <enumeratedValue>
15443                    <name>AMUXB_DSI</name>
15444                    <description>Analog mux bus B, DSI control</description>
15445                    <value>7</value>
15446                  </enumeratedValue>
15447                  <enumeratedValue>
15448                    <name>ACT_0</name>
15449                    <description>Active functionality 0</description>
15450                    <value>8</value>
15451                  </enumeratedValue>
15452                  <enumeratedValue>
15453                    <name>ACT_1</name>
15454                    <description>Active functionality 1</description>
15455                    <value>9</value>
15456                  </enumeratedValue>
15457                  <enumeratedValue>
15458                    <name>ACT_2</name>
15459                    <description>Active functionality 2</description>
15460                    <value>10</value>
15461                  </enumeratedValue>
15462                  <enumeratedValue>
15463                    <name>ACT_3</name>
15464                    <description>Active functionality 3</description>
15465                    <value>11</value>
15466                  </enumeratedValue>
15467                  <enumeratedValue>
15468                    <name>DS_0</name>
15469                    <description>DeepSleep functionality 0</description>
15470                    <value>12</value>
15471                  </enumeratedValue>
15472                  <enumeratedValue>
15473                    <name>DS_1</name>
15474                    <description>DeepSleep functionality 1</description>
15475                    <value>13</value>
15476                  </enumeratedValue>
15477                  <enumeratedValue>
15478                    <name>DS_2</name>
15479                    <description>DeepSleep functionality 2</description>
15480                    <value>14</value>
15481                  </enumeratedValue>
15482                  <enumeratedValue>
15483                    <name>DS_3</name>
15484                    <description>DeepSleep functionality 3</description>
15485                    <value>15</value>
15486                  </enumeratedValue>
15487                  <enumeratedValue>
15488                    <name>ACT_4</name>
15489                    <description>Active functionality 4</description>
15490                    <value>16</value>
15491                  </enumeratedValue>
15492                  <enumeratedValue>
15493                    <name>ACT_5</name>
15494                    <description>Active functionality 5</description>
15495                    <value>17</value>
15496                  </enumeratedValue>
15497                  <enumeratedValue>
15498                    <name>ACT_6</name>
15499                    <description>Active functionality 6</description>
15500                    <value>18</value>
15501                  </enumeratedValue>
15502                  <enumeratedValue>
15503                    <name>ACT_7</name>
15504                    <description>Active functionality 7</description>
15505                    <value>19</value>
15506                  </enumeratedValue>
15507                  <enumeratedValue>
15508                    <name>ACT_8</name>
15509                    <description>Active functionality 8</description>
15510                    <value>20</value>
15511                  </enumeratedValue>
15512                  <enumeratedValue>
15513                    <name>ACT_9</name>
15514                    <description>Active functionality 9</description>
15515                    <value>21</value>
15516                  </enumeratedValue>
15517                  <enumeratedValue>
15518                    <name>ACT_10</name>
15519                    <description>Active functionality 10</description>
15520                    <value>22</value>
15521                  </enumeratedValue>
15522                  <enumeratedValue>
15523                    <name>ACT_11</name>
15524                    <description>Active functionality 11</description>
15525                    <value>23</value>
15526                  </enumeratedValue>
15527                  <enumeratedValue>
15528                    <name>ACT_12</name>
15529                    <description>Active functionality 12</description>
15530                    <value>24</value>
15531                  </enumeratedValue>
15532                  <enumeratedValue>
15533                    <name>ACT_13</name>
15534                    <description>Active functionality 13</description>
15535                    <value>25</value>
15536                  </enumeratedValue>
15537                  <enumeratedValue>
15538                    <name>ACT_14</name>
15539                    <description>Active functionality 14</description>
15540                    <value>26</value>
15541                  </enumeratedValue>
15542                  <enumeratedValue>
15543                    <name>ACT_15</name>
15544                    <description>Active functionality 15</description>
15545                    <value>27</value>
15546                  </enumeratedValue>
15547                  <enumeratedValue>
15548                    <name>DS_4</name>
15549                    <description>DeepSleep functionality 4</description>
15550                    <value>28</value>
15551                  </enumeratedValue>
15552                  <enumeratedValue>
15553                    <name>DS_5</name>
15554                    <description>DeepSleep functionality 5</description>
15555                    <value>29</value>
15556                  </enumeratedValue>
15557                  <enumeratedValue>
15558                    <name>DS_6</name>
15559                    <description>DeepSleep functionality 6</description>
15560                    <value>30</value>
15561                  </enumeratedValue>
15562                  <enumeratedValue>
15563                    <name>DS_7</name>
15564                    <description>DeepSleep functionality 7</description>
15565                    <value>31</value>
15566                  </enumeratedValue>
15567                </enumeratedValues>
15568              </field>
15569              <field>
15570                <name>IO1_SEL</name>
15571                <description>Selects connection for IO pin 1 route.</description>
15572                <bitRange>[12:8]</bitRange>
15573                <access>read-write</access>
15574              </field>
15575              <field>
15576                <name>IO2_SEL</name>
15577                <description>Selects connection for IO pin 2 route.</description>
15578                <bitRange>[20:16]</bitRange>
15579                <access>read-write</access>
15580              </field>
15581              <field>
15582                <name>IO3_SEL</name>
15583                <description>Selects connection for IO pin 3 route.</description>
15584                <bitRange>[28:24]</bitRange>
15585                <access>read-write</access>
15586              </field>
15587            </fields>
15588          </register>
15589          <register>
15590            <name>PORT_SEL1</name>
15591            <description>Port selection 1</description>
15592            <addressOffset>0x4</addressOffset>
15593            <size>32</size>
15594            <access>read-write</access>
15595            <resetValue>0x0</resetValue>
15596            <resetMask>0x1F1F1F1F</resetMask>
15597            <fields>
15598              <field>
15599                <name>IO4_SEL</name>
15600                <description>Selects connection for IO pin 4 route.
15601See PORT_SEL0 for connection details.</description>
15602                <bitRange>[4:0]</bitRange>
15603                <access>read-write</access>
15604              </field>
15605              <field>
15606                <name>IO5_SEL</name>
15607                <description>Selects connection for IO pin 5 route.</description>
15608                <bitRange>[12:8]</bitRange>
15609                <access>read-write</access>
15610              </field>
15611              <field>
15612                <name>IO6_SEL</name>
15613                <description>Selects connection for IO pin 6 route.</description>
15614                <bitRange>[20:16]</bitRange>
15615                <access>read-write</access>
15616              </field>
15617              <field>
15618                <name>IO7_SEL</name>
15619                <description>Selects connection for IO pin 7 route.</description>
15620                <bitRange>[28:24]</bitRange>
15621                <access>read-write</access>
15622              </field>
15623            </fields>
15624          </register>
15625        </cluster>
15626        <register>
15627          <dim>64</dim>
15628          <dimIncrement>4</dimIncrement>
15629          <name>AMUX_SPLIT_CTL[%s]</name>
15630          <description>AMUX splitter cell control</description>
15631          <addressOffset>0x2000</addressOffset>
15632          <size>32</size>
15633          <access>read-write</access>
15634          <resetValue>0x0</resetValue>
15635          <resetMask>0x77</resetMask>
15636          <fields>
15637            <field>
15638              <name>SWITCH_AA_SL</name>
15639              <description>T-switch control for Left AMUXBUSA switch:
15640'0': switch open.
15641'1': switch closed.</description>
15642              <bitRange>[0:0]</bitRange>
15643              <access>read-write</access>
15644            </field>
15645            <field>
15646              <name>SWITCH_AA_SR</name>
15647              <description>T-switch control for Right AMUXBUSA switch:
15648'0': switch open.
15649'1': switch closed.</description>
15650              <bitRange>[1:1]</bitRange>
15651              <access>read-write</access>
15652            </field>
15653            <field>
15654              <name>SWITCH_AA_S0</name>
15655              <description>T-switch control for AMUXBUSA vssa/ground switch:
15656'0': switch open.
15657'1': switch closed.</description>
15658              <bitRange>[2:2]</bitRange>
15659              <access>read-write</access>
15660            </field>
15661            <field>
15662              <name>SWITCH_BB_SL</name>
15663              <description>T-switch control for Left AMUXBUSB switch.</description>
15664              <bitRange>[4:4]</bitRange>
15665              <access>read-write</access>
15666            </field>
15667            <field>
15668              <name>SWITCH_BB_SR</name>
15669              <description>T-switch control for Right AMUXBUSB switch.</description>
15670              <bitRange>[5:5]</bitRange>
15671              <access>read-write</access>
15672            </field>
15673            <field>
15674              <name>SWITCH_BB_S0</name>
15675              <description>T-switch control for AMUXBUSB vssa/ground switch.</description>
15676              <bitRange>[6:6]</bitRange>
15677              <access>read-write</access>
15678            </field>
15679          </fields>
15680        </register>
15681        <register>
15682          <name>MONITOR_CTL_0</name>
15683          <description>Power/Ground Monitor cell control 0</description>
15684          <addressOffset>0x2200</addressOffset>
15685          <size>32</size>
15686          <access>read-write</access>
15687          <resetValue>0x0</resetValue>
15688          <resetMask>0xFFFFFFFF</resetMask>
15689          <fields>
15690            <field>
15691              <name>MONITOR_EN</name>
15692              <description>control for switch, which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed:
15693'0': switch open.
15694'1': switch closed.</description>
15695              <bitRange>[31:0]</bitRange>
15696              <access>read-write</access>
15697            </field>
15698          </fields>
15699        </register>
15700        <register>
15701          <name>MONITOR_CTL_1</name>
15702          <description>Power/Ground Monitor cell control 1</description>
15703          <addressOffset>0x2204</addressOffset>
15704          <size>32</size>
15705          <access>read-write</access>
15706          <resetValue>0x0</resetValue>
15707          <resetMask>0xFFFFFFFF</resetMask>
15708          <fields>
15709            <field>
15710              <name>MONITOR_EN</name>
15711              <description>control for switch, which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed:
15712'0': switch open.
15713'1': switch closed.</description>
15714              <bitRange>[31:0]</bitRange>
15715              <access>read-write</access>
15716            </field>
15717          </fields>
15718        </register>
15719        <register>
15720          <name>MONITOR_CTL_2</name>
15721          <description>Power/Ground Monitor cell control 2</description>
15722          <addressOffset>0x2208</addressOffset>
15723          <size>32</size>
15724          <access>read-write</access>
15725          <resetValue>0x0</resetValue>
15726          <resetMask>0xFFFFFFFF</resetMask>
15727          <fields>
15728            <field>
15729              <name>MONITOR_EN</name>
15730              <description>control for switch, which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed:
15731'0': switch open.
15732'1': switch closed.</description>
15733              <bitRange>[31:0]</bitRange>
15734              <access>read-write</access>
15735            </field>
15736          </fields>
15737        </register>
15738        <register>
15739          <name>MONITOR_CTL_3</name>
15740          <description>Power/Ground Monitor cell control 3</description>
15741          <addressOffset>0x220C</addressOffset>
15742          <size>32</size>
15743          <access>read-write</access>
15744          <resetValue>0x0</resetValue>
15745          <resetMask>0xFFFFFFFF</resetMask>
15746          <fields>
15747            <field>
15748              <name>MONITOR_EN</name>
15749              <description>control for switch, which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed:
15750'0': switch open.
15751'1': switch closed.</description>
15752              <bitRange>[31:0]</bitRange>
15753              <access>read-write</access>
15754            </field>
15755          </fields>
15756        </register>
15757        <register>
15758          <name>ALT_JTAG_EN</name>
15759          <description>Alternate JTAG IF selection register</description>
15760          <addressOffset>0x2240</addressOffset>
15761          <size>32</size>
15762          <access>read-write</access>
15763          <resetValue>0x0</resetValue>
15764          <resetMask>0x80000000</resetMask>
15765          <fields>
15766            <field>
15767              <name>ENABLE</name>
15768              <description>Provides the selection for alternate JTAG IF connectivity.
157690: Primary JTAG interface is selected
157701: Secondary (alternate) JTAG interface is selected.
15771
15772This connectivity works ONLY in ACTIVE mode.</description>
15773              <bitRange>[31:31]</bitRange>
15774              <access>read-write</access>
15775            </field>
15776          </fields>
15777        </register>
15778      </registers>
15779    </peripheral>
15780    <peripheral>
15781      <name>GPIO</name>
15782      <description>GPIO port control/configuration</description>
15783      <baseAddress>0x40310000</baseAddress>
15784      <addressBlock>
15785        <offset>0</offset>
15786        <size>65536</size>
15787        <usage>registers</usage>
15788      </addressBlock>
15789      <registers>
15790        <cluster>
15791          <dim>14</dim>
15792          <dimIncrement>128</dimIncrement>
15793          <name>PRT[%s]</name>
15794          <description>GPIO port registers</description>
15795          <addressOffset>0x00000000</addressOffset>
15796          <register>
15797            <name>OUT</name>
15798            <description>Port output data register</description>
15799            <addressOffset>0x0</addressOffset>
15800            <size>32</size>
15801            <access>read-write</access>
15802            <resetValue>0x0</resetValue>
15803            <resetMask>0xFF</resetMask>
15804            <fields>
15805              <field>
15806                <name>OUT0</name>
15807                <description>IO output data for pin 0
15808'0': Output state set to '0'
15809'1': Output state set to '1'</description>
15810                <bitRange>[0:0]</bitRange>
15811                <access>read-write</access>
15812              </field>
15813              <field>
15814                <name>OUT1</name>
15815                <description>IO output data for pin 1</description>
15816                <bitRange>[1:1]</bitRange>
15817                <access>read-write</access>
15818              </field>
15819              <field>
15820                <name>OUT2</name>
15821                <description>IO output data for pin 2</description>
15822                <bitRange>[2:2]</bitRange>
15823                <access>read-write</access>
15824              </field>
15825              <field>
15826                <name>OUT3</name>
15827                <description>IO output data for pin 3</description>
15828                <bitRange>[3:3]</bitRange>
15829                <access>read-write</access>
15830              </field>
15831              <field>
15832                <name>OUT4</name>
15833                <description>IO output data for pin 4</description>
15834                <bitRange>[4:4]</bitRange>
15835                <access>read-write</access>
15836              </field>
15837              <field>
15838                <name>OUT5</name>
15839                <description>IO output data for pin 5</description>
15840                <bitRange>[5:5]</bitRange>
15841                <access>read-write</access>
15842              </field>
15843              <field>
15844                <name>OUT6</name>
15845                <description>IO output data for pin 6</description>
15846                <bitRange>[6:6]</bitRange>
15847                <access>read-write</access>
15848              </field>
15849              <field>
15850                <name>OUT7</name>
15851                <description>IO output data for pin 7</description>
15852                <bitRange>[7:7]</bitRange>
15853                <access>read-write</access>
15854              </field>
15855            </fields>
15856          </register>
15857          <register>
15858            <name>OUT_CLR</name>
15859            <description>Port output data clear register</description>
15860            <addressOffset>0x4</addressOffset>
15861            <size>32</size>
15862            <access>read-write</access>
15863            <resetValue>0x0</resetValue>
15864            <resetMask>0xFF</resetMask>
15865            <fields>
15866              <field>
15867                <name>OUT0</name>
15868                <description>IO clear output for pin 0:
15869'0': Output state not affected.
15870'1': Output state set to '0'.</description>
15871                <bitRange>[0:0]</bitRange>
15872                <access>read-write</access>
15873              </field>
15874              <field>
15875                <name>OUT1</name>
15876                <description>IO clear output for pin 1</description>
15877                <bitRange>[1:1]</bitRange>
15878                <access>read-write</access>
15879              </field>
15880              <field>
15881                <name>OUT2</name>
15882                <description>IO clear output for pin 2</description>
15883                <bitRange>[2:2]</bitRange>
15884                <access>read-write</access>
15885              </field>
15886              <field>
15887                <name>OUT3</name>
15888                <description>IO clear output for pin 3</description>
15889                <bitRange>[3:3]</bitRange>
15890                <access>read-write</access>
15891              </field>
15892              <field>
15893                <name>OUT4</name>
15894                <description>IO clear output for pin 4</description>
15895                <bitRange>[4:4]</bitRange>
15896                <access>read-write</access>
15897              </field>
15898              <field>
15899                <name>OUT5</name>
15900                <description>IO clear output for pin 5</description>
15901                <bitRange>[5:5]</bitRange>
15902                <access>read-write</access>
15903              </field>
15904              <field>
15905                <name>OUT6</name>
15906                <description>IO clear output for pin 6</description>
15907                <bitRange>[6:6]</bitRange>
15908                <access>read-write</access>
15909              </field>
15910              <field>
15911                <name>OUT7</name>
15912                <description>IO clear output for pin 7</description>
15913                <bitRange>[7:7]</bitRange>
15914                <access>read-write</access>
15915              </field>
15916            </fields>
15917          </register>
15918          <register>
15919            <name>OUT_SET</name>
15920            <description>Port output data set register</description>
15921            <addressOffset>0x8</addressOffset>
15922            <size>32</size>
15923            <access>read-write</access>
15924            <resetValue>0x0</resetValue>
15925            <resetMask>0xFF</resetMask>
15926            <fields>
15927              <field>
15928                <name>OUT0</name>
15929                <description>IO set output for pin 0:
15930'0': Output state not affected.
15931'1': Output state set to '1'.</description>
15932                <bitRange>[0:0]</bitRange>
15933                <access>read-write</access>
15934              </field>
15935              <field>
15936                <name>OUT1</name>
15937                <description>IO set output for pin 1</description>
15938                <bitRange>[1:1]</bitRange>
15939                <access>read-write</access>
15940              </field>
15941              <field>
15942                <name>OUT2</name>
15943                <description>IO set output for pin 2</description>
15944                <bitRange>[2:2]</bitRange>
15945                <access>read-write</access>
15946              </field>
15947              <field>
15948                <name>OUT3</name>
15949                <description>IO set output for pin 3</description>
15950                <bitRange>[3:3]</bitRange>
15951                <access>read-write</access>
15952              </field>
15953              <field>
15954                <name>OUT4</name>
15955                <description>IO set output for pin 4</description>
15956                <bitRange>[4:4]</bitRange>
15957                <access>read-write</access>
15958              </field>
15959              <field>
15960                <name>OUT5</name>
15961                <description>IO set output for pin 5</description>
15962                <bitRange>[5:5]</bitRange>
15963                <access>read-write</access>
15964              </field>
15965              <field>
15966                <name>OUT6</name>
15967                <description>IO set output for pin 6</description>
15968                <bitRange>[6:6]</bitRange>
15969                <access>read-write</access>
15970              </field>
15971              <field>
15972                <name>OUT7</name>
15973                <description>IO set output for pin 7</description>
15974                <bitRange>[7:7]</bitRange>
15975                <access>read-write</access>
15976              </field>
15977            </fields>
15978          </register>
15979          <register>
15980            <name>OUT_INV</name>
15981            <description>Port output data invert register</description>
15982            <addressOffset>0xC</addressOffset>
15983            <size>32</size>
15984            <access>read-write</access>
15985            <resetValue>0x0</resetValue>
15986            <resetMask>0xFF</resetMask>
15987            <fields>
15988              <field>
15989                <name>OUT0</name>
15990                <description>IO invert output for pin 0:
15991'0': Output state not affected.
15992'1': Output state inverted ('0' =&gt; '1', '1' =&gt; '0').</description>
15993                <bitRange>[0:0]</bitRange>
15994                <access>read-write</access>
15995              </field>
15996              <field>
15997                <name>OUT1</name>
15998                <description>IO invert output for pin 1</description>
15999                <bitRange>[1:1]</bitRange>
16000                <access>read-write</access>
16001              </field>
16002              <field>
16003                <name>OUT2</name>
16004                <description>IO invert output for pin 2</description>
16005                <bitRange>[2:2]</bitRange>
16006                <access>read-write</access>
16007              </field>
16008              <field>
16009                <name>OUT3</name>
16010                <description>IO invert output for pin 3</description>
16011                <bitRange>[3:3]</bitRange>
16012                <access>read-write</access>
16013              </field>
16014              <field>
16015                <name>OUT4</name>
16016                <description>IO invert output for pin 4</description>
16017                <bitRange>[4:4]</bitRange>
16018                <access>read-write</access>
16019              </field>
16020              <field>
16021                <name>OUT5</name>
16022                <description>IO invert output for pin 5</description>
16023                <bitRange>[5:5]</bitRange>
16024                <access>read-write</access>
16025              </field>
16026              <field>
16027                <name>OUT6</name>
16028                <description>IO invert output for pin 6</description>
16029                <bitRange>[6:6]</bitRange>
16030                <access>read-write</access>
16031              </field>
16032              <field>
16033                <name>OUT7</name>
16034                <description>IO invert output for pin 7</description>
16035                <bitRange>[7:7]</bitRange>
16036                <access>read-write</access>
16037              </field>
16038            </fields>
16039          </register>
16040          <register>
16041            <name>IN</name>
16042            <description>Port input state register</description>
16043            <addressOffset>0x10</addressOffset>
16044            <size>32</size>
16045            <access>read-only</access>
16046            <resetValue>0x0</resetValue>
16047            <resetMask>0x1FF</resetMask>
16048            <fields>
16049              <field>
16050                <name>IN0</name>
16051                <description>IO pin state for pin 0
16052'0': Low logic level present on pin.
16053'1': High logic level present on pin.
16054On reset assertion , IN register will get reset. The Pad value takes 2 clock cycles to be reflected into IN Register.  It's value then depends on the external pin value.</description>
16055                <bitRange>[0:0]</bitRange>
16056                <access>read-only</access>
16057              </field>
16058              <field>
16059                <name>IN1</name>
16060                <description>IO pin state for pin 1</description>
16061                <bitRange>[1:1]</bitRange>
16062                <access>read-only</access>
16063              </field>
16064              <field>
16065                <name>IN2</name>
16066                <description>IO pin state for pin 2</description>
16067                <bitRange>[2:2]</bitRange>
16068                <access>read-only</access>
16069              </field>
16070              <field>
16071                <name>IN3</name>
16072                <description>IO pin state for pin 3</description>
16073                <bitRange>[3:3]</bitRange>
16074                <access>read-only</access>
16075              </field>
16076              <field>
16077                <name>IN4</name>
16078                <description>IO pin state for pin 4</description>
16079                <bitRange>[4:4]</bitRange>
16080                <access>read-only</access>
16081              </field>
16082              <field>
16083                <name>IN5</name>
16084                <description>IO pin state for pin 5</description>
16085                <bitRange>[5:5]</bitRange>
16086                <access>read-only</access>
16087              </field>
16088              <field>
16089                <name>IN6</name>
16090                <description>IO pin state for pin 6</description>
16091                <bitRange>[6:6]</bitRange>
16092                <access>read-only</access>
16093              </field>
16094              <field>
16095                <name>IN7</name>
16096                <description>IO pin state for pin 7</description>
16097                <bitRange>[7:7]</bitRange>
16098                <access>read-only</access>
16099              </field>
16100              <field>
16101                <name>FLT_IN</name>
16102                <description>Reads of this register return the logical state of the filtered pin as selected in the INTR_CFG.FLT_SEL register.</description>
16103                <bitRange>[8:8]</bitRange>
16104                <access>read-only</access>
16105              </field>
16106            </fields>
16107          </register>
16108          <register>
16109            <name>INTR</name>
16110            <description>Port interrupt status register</description>
16111            <addressOffset>0x14</addressOffset>
16112            <size>32</size>
16113            <access>read-write</access>
16114            <resetValue>0x0</resetValue>
16115            <resetMask>0x1FF01FF</resetMask>
16116            <fields>
16117              <field>
16118                <name>EDGE0</name>
16119                <description>Edge detect for IO pin 0
16120'0': No edge was detected on pin.
16121'1': An edge was detected on pin.</description>
16122                <bitRange>[0:0]</bitRange>
16123                <access>read-write</access>
16124              </field>
16125              <field>
16126                <name>EDGE1</name>
16127                <description>Edge detect for IO pin 1</description>
16128                <bitRange>[1:1]</bitRange>
16129                <access>read-write</access>
16130              </field>
16131              <field>
16132                <name>EDGE2</name>
16133                <description>Edge detect for IO pin 2</description>
16134                <bitRange>[2:2]</bitRange>
16135                <access>read-write</access>
16136              </field>
16137              <field>
16138                <name>EDGE3</name>
16139                <description>Edge detect for IO pin 3</description>
16140                <bitRange>[3:3]</bitRange>
16141                <access>read-write</access>
16142              </field>
16143              <field>
16144                <name>EDGE4</name>
16145                <description>Edge detect for IO pin 4</description>
16146                <bitRange>[4:4]</bitRange>
16147                <access>read-write</access>
16148              </field>
16149              <field>
16150                <name>EDGE5</name>
16151                <description>Edge detect for IO pin 5</description>
16152                <bitRange>[5:5]</bitRange>
16153                <access>read-write</access>
16154              </field>
16155              <field>
16156                <name>EDGE6</name>
16157                <description>Edge detect for IO pin 6</description>
16158                <bitRange>[6:6]</bitRange>
16159                <access>read-write</access>
16160              </field>
16161              <field>
16162                <name>EDGE7</name>
16163                <description>Edge detect for IO pin 7</description>
16164                <bitRange>[7:7]</bitRange>
16165                <access>read-write</access>
16166              </field>
16167              <field>
16168                <name>FLT_EDGE</name>
16169                <description>Edge detected on filtered pin selected by INTR_CFG.FLT_SEL</description>
16170                <bitRange>[8:8]</bitRange>
16171                <access>read-write</access>
16172              </field>
16173              <field>
16174                <name>IN_IN0</name>
16175                <description>IO pin state for pin 0</description>
16176                <bitRange>[16:16]</bitRange>
16177                <access>read-only</access>
16178              </field>
16179              <field>
16180                <name>IN_IN1</name>
16181                <description>IO pin state for pin 1</description>
16182                <bitRange>[17:17]</bitRange>
16183                <access>read-only</access>
16184              </field>
16185              <field>
16186                <name>IN_IN2</name>
16187                <description>IO pin state for pin 2</description>
16188                <bitRange>[18:18]</bitRange>
16189                <access>read-only</access>
16190              </field>
16191              <field>
16192                <name>IN_IN3</name>
16193                <description>IO pin state for pin 3</description>
16194                <bitRange>[19:19]</bitRange>
16195                <access>read-only</access>
16196              </field>
16197              <field>
16198                <name>IN_IN4</name>
16199                <description>IO pin state for pin 4</description>
16200                <bitRange>[20:20]</bitRange>
16201                <access>read-only</access>
16202              </field>
16203              <field>
16204                <name>IN_IN5</name>
16205                <description>IO pin state for pin 5</description>
16206                <bitRange>[21:21]</bitRange>
16207                <access>read-only</access>
16208              </field>
16209              <field>
16210                <name>IN_IN6</name>
16211                <description>IO pin state for pin 6</description>
16212                <bitRange>[22:22]</bitRange>
16213                <access>read-only</access>
16214              </field>
16215              <field>
16216                <name>IN_IN7</name>
16217                <description>IO pin state for pin 7</description>
16218                <bitRange>[23:23]</bitRange>
16219                <access>read-only</access>
16220              </field>
16221              <field>
16222                <name>FLT_IN_IN</name>
16223                <description>Filtered pin state for pin selected by INTR_CFG.FLT_SEL</description>
16224                <bitRange>[24:24]</bitRange>
16225                <access>read-only</access>
16226              </field>
16227            </fields>
16228          </register>
16229          <register>
16230            <name>INTR_MASK</name>
16231            <description>Port interrupt mask register</description>
16232            <addressOffset>0x18</addressOffset>
16233            <size>32</size>
16234            <access>read-write</access>
16235            <resetValue>0x0</resetValue>
16236            <resetMask>0x1FF</resetMask>
16237            <fields>
16238              <field>
16239                <name>EDGE0</name>
16240                <description>Masks edge interrupt on IO pin 0
16241'0': Pin interrupt forwarding disabled
16242'1': Pin interrupt forwarding enabled</description>
16243                <bitRange>[0:0]</bitRange>
16244                <access>read-write</access>
16245              </field>
16246              <field>
16247                <name>EDGE1</name>
16248                <description>Masks edge interrupt on IO pin 1</description>
16249                <bitRange>[1:1]</bitRange>
16250                <access>read-write</access>
16251              </field>
16252              <field>
16253                <name>EDGE2</name>
16254                <description>Masks edge interrupt on IO pin 2</description>
16255                <bitRange>[2:2]</bitRange>
16256                <access>read-write</access>
16257              </field>
16258              <field>
16259                <name>EDGE3</name>
16260                <description>Masks edge interrupt on IO pin 3</description>
16261                <bitRange>[3:3]</bitRange>
16262                <access>read-write</access>
16263              </field>
16264              <field>
16265                <name>EDGE4</name>
16266                <description>Masks edge interrupt on IO pin 4</description>
16267                <bitRange>[4:4]</bitRange>
16268                <access>read-write</access>
16269              </field>
16270              <field>
16271                <name>EDGE5</name>
16272                <description>Masks edge interrupt on IO pin 5</description>
16273                <bitRange>[5:5]</bitRange>
16274                <access>read-write</access>
16275              </field>
16276              <field>
16277                <name>EDGE6</name>
16278                <description>Masks edge interrupt on IO pin 6</description>
16279                <bitRange>[6:6]</bitRange>
16280                <access>read-write</access>
16281              </field>
16282              <field>
16283                <name>EDGE7</name>
16284                <description>Masks edge interrupt on IO pin 7</description>
16285                <bitRange>[7:7]</bitRange>
16286                <access>read-write</access>
16287              </field>
16288              <field>
16289                <name>FLT_EDGE</name>
16290                <description>Masks edge interrupt on filtered pin selected by INTR_CFG.FLT_SEL</description>
16291                <bitRange>[8:8]</bitRange>
16292                <access>read-write</access>
16293              </field>
16294            </fields>
16295          </register>
16296          <register>
16297            <name>INTR_MASKED</name>
16298            <description>Port interrupt masked status register</description>
16299            <addressOffset>0x1C</addressOffset>
16300            <size>32</size>
16301            <access>read-only</access>
16302            <resetValue>0x0</resetValue>
16303            <resetMask>0x1FF</resetMask>
16304            <fields>
16305              <field>
16306                <name>EDGE0</name>
16307                <description>Edge detected AND masked on IO pin 0
16308'0': Interrupt was not forwarded to CPU
16309'1': Interrupt occurred and was forwarded to CPU</description>
16310                <bitRange>[0:0]</bitRange>
16311                <access>read-only</access>
16312              </field>
16313              <field>
16314                <name>EDGE1</name>
16315                <description>Edge detected and masked on IO pin 1</description>
16316                <bitRange>[1:1]</bitRange>
16317                <access>read-only</access>
16318              </field>
16319              <field>
16320                <name>EDGE2</name>
16321                <description>Edge detected and masked on IO pin 2</description>
16322                <bitRange>[2:2]</bitRange>
16323                <access>read-only</access>
16324              </field>
16325              <field>
16326                <name>EDGE3</name>
16327                <description>Edge detected and masked on IO pin 3</description>
16328                <bitRange>[3:3]</bitRange>
16329                <access>read-only</access>
16330              </field>
16331              <field>
16332                <name>EDGE4</name>
16333                <description>Edge detected and masked on IO pin 4</description>
16334                <bitRange>[4:4]</bitRange>
16335                <access>read-only</access>
16336              </field>
16337              <field>
16338                <name>EDGE5</name>
16339                <description>Edge detected and masked on IO pin 5</description>
16340                <bitRange>[5:5]</bitRange>
16341                <access>read-only</access>
16342              </field>
16343              <field>
16344                <name>EDGE6</name>
16345                <description>Edge detected and masked on IO pin 6</description>
16346                <bitRange>[6:6]</bitRange>
16347                <access>read-only</access>
16348              </field>
16349              <field>
16350                <name>EDGE7</name>
16351                <description>Edge detected and masked on IO pin 7</description>
16352                <bitRange>[7:7]</bitRange>
16353                <access>read-only</access>
16354              </field>
16355              <field>
16356                <name>FLT_EDGE</name>
16357                <description>Edge detected and masked on filtered pin selected by INTR_CFG.FLT_SEL</description>
16358                <bitRange>[8:8]</bitRange>
16359                <access>read-only</access>
16360              </field>
16361            </fields>
16362          </register>
16363          <register>
16364            <name>INTR_SET</name>
16365            <description>Port interrupt set register</description>
16366            <addressOffset>0x20</addressOffset>
16367            <size>32</size>
16368            <access>read-write</access>
16369            <resetValue>0x0</resetValue>
16370            <resetMask>0x1FF</resetMask>
16371            <fields>
16372              <field>
16373                <name>EDGE0</name>
16374                <description>Sets edge detect interrupt for IO pin 0
16375'0': Interrupt state not affected
16376'1': Interrupt set</description>
16377                <bitRange>[0:0]</bitRange>
16378                <access>read-write</access>
16379              </field>
16380              <field>
16381                <name>EDGE1</name>
16382                <description>Sets edge detect interrupt for IO pin 1</description>
16383                <bitRange>[1:1]</bitRange>
16384                <access>read-write</access>
16385              </field>
16386              <field>
16387                <name>EDGE2</name>
16388                <description>Sets edge detect interrupt for IO pin 2</description>
16389                <bitRange>[2:2]</bitRange>
16390                <access>read-write</access>
16391              </field>
16392              <field>
16393                <name>EDGE3</name>
16394                <description>Sets edge detect interrupt for IO pin 3</description>
16395                <bitRange>[3:3]</bitRange>
16396                <access>read-write</access>
16397              </field>
16398              <field>
16399                <name>EDGE4</name>
16400                <description>Sets edge detect interrupt for IO pin 4</description>
16401                <bitRange>[4:4]</bitRange>
16402                <access>read-write</access>
16403              </field>
16404              <field>
16405                <name>EDGE5</name>
16406                <description>Sets edge detect interrupt for IO pin 5</description>
16407                <bitRange>[5:5]</bitRange>
16408                <access>read-write</access>
16409              </field>
16410              <field>
16411                <name>EDGE6</name>
16412                <description>Sets edge detect interrupt for IO pin 6</description>
16413                <bitRange>[6:6]</bitRange>
16414                <access>read-write</access>
16415              </field>
16416              <field>
16417                <name>EDGE7</name>
16418                <description>Sets edge detect interrupt for IO pin 7</description>
16419                <bitRange>[7:7]</bitRange>
16420                <access>read-write</access>
16421              </field>
16422              <field>
16423                <name>FLT_EDGE</name>
16424                <description>Sets edge detect interrupt for filtered pin selected by INTR_CFG.FLT_SEL</description>
16425                <bitRange>[8:8]</bitRange>
16426                <access>read-write</access>
16427              </field>
16428            </fields>
16429          </register>
16430          <register>
16431            <name>INTR_CFG</name>
16432            <description>Port interrupt configuration register</description>
16433            <addressOffset>0x40</addressOffset>
16434            <size>32</size>
16435            <access>read-write</access>
16436            <resetValue>0x0</resetValue>
16437            <resetMask>0x1FFFFF</resetMask>
16438            <fields>
16439              <field>
16440                <name>EDGE0_SEL</name>
16441                <description>Sets which edge will trigger an IRQ for IO pin 0</description>
16442                <bitRange>[1:0]</bitRange>
16443                <access>read-write</access>
16444                <enumeratedValues>
16445                  <enumeratedValue>
16446                    <name>DISABLE</name>
16447                    <description>Disabled</description>
16448                    <value>0</value>
16449                  </enumeratedValue>
16450                  <enumeratedValue>
16451                    <name>RISING</name>
16452                    <description>Rising edge</description>
16453                    <value>1</value>
16454                  </enumeratedValue>
16455                  <enumeratedValue>
16456                    <name>FALLING</name>
16457                    <description>Falling edge</description>
16458                    <value>2</value>
16459                  </enumeratedValue>
16460                  <enumeratedValue>
16461                    <name>BOTH</name>
16462                    <description>Both rising and falling edges</description>
16463                    <value>3</value>
16464                  </enumeratedValue>
16465                </enumeratedValues>
16466              </field>
16467              <field>
16468                <name>EDGE1_SEL</name>
16469                <description>Sets which edge will trigger an IRQ for IO pin 1</description>
16470                <bitRange>[3:2]</bitRange>
16471                <access>read-write</access>
16472              </field>
16473              <field>
16474                <name>EDGE2_SEL</name>
16475                <description>Sets which edge will trigger an IRQ for IO pin 2</description>
16476                <bitRange>[5:4]</bitRange>
16477                <access>read-write</access>
16478              </field>
16479              <field>
16480                <name>EDGE3_SEL</name>
16481                <description>Sets which edge will trigger an IRQ for IO pin 3</description>
16482                <bitRange>[7:6]</bitRange>
16483                <access>read-write</access>
16484              </field>
16485              <field>
16486                <name>EDGE4_SEL</name>
16487                <description>Sets which edge will trigger an IRQ for IO pin 4</description>
16488                <bitRange>[9:8]</bitRange>
16489                <access>read-write</access>
16490              </field>
16491              <field>
16492                <name>EDGE5_SEL</name>
16493                <description>Sets which edge will trigger an IRQ for IO pin 5</description>
16494                <bitRange>[11:10]</bitRange>
16495                <access>read-write</access>
16496              </field>
16497              <field>
16498                <name>EDGE6_SEL</name>
16499                <description>Sets which edge will trigger an IRQ for IO pin 6</description>
16500                <bitRange>[13:12]</bitRange>
16501                <access>read-write</access>
16502              </field>
16503              <field>
16504                <name>EDGE7_SEL</name>
16505                <description>Sets which edge will trigger an IRQ for IO pin 7</description>
16506                <bitRange>[15:14]</bitRange>
16507                <access>read-write</access>
16508              </field>
16509              <field>
16510                <name>FLT_EDGE_SEL</name>
16511                <description>Sets which edge will trigger an IRQ for the glitch filtered pin (selected by INTR_CFG.FLT_SEL</description>
16512                <bitRange>[17:16]</bitRange>
16513                <access>read-write</access>
16514                <enumeratedValues>
16515                  <enumeratedValue>
16516                    <name>DISABLE</name>
16517                    <description>Disabled</description>
16518                    <value>0</value>
16519                  </enumeratedValue>
16520                  <enumeratedValue>
16521                    <name>RISING</name>
16522                    <description>Rising edge</description>
16523                    <value>1</value>
16524                  </enumeratedValue>
16525                  <enumeratedValue>
16526                    <name>FALLING</name>
16527                    <description>Falling edge</description>
16528                    <value>2</value>
16529                  </enumeratedValue>
16530                  <enumeratedValue>
16531                    <name>BOTH</name>
16532                    <description>Both rising and falling edges</description>
16533                    <value>3</value>
16534                  </enumeratedValue>
16535                </enumeratedValues>
16536              </field>
16537              <field>
16538                <name>FLT_SEL</name>
16539                <description>Selects which pin is routed through the 50ns glitch filter to provide a glitch-safe interrupt.</description>
16540                <bitRange>[20:18]</bitRange>
16541                <access>read-write</access>
16542              </field>
16543            </fields>
16544          </register>
16545          <register>
16546            <name>CFG</name>
16547            <description>Port configuration register</description>
16548            <addressOffset>0x44</addressOffset>
16549            <size>32</size>
16550            <access>read-write</access>
16551            <resetValue>0x0</resetValue>
16552            <resetMask>0xFFFFFFFF</resetMask>
16553            <fields>
16554              <field>
16555                <name>DRIVE_MODE0</name>
16556                <description>The GPIO drive mode for IO pin 0. Resistive pull-up and pull-down is selected in the drive mode.
16557Note: when initializing IO's that are connected to a live bus (such as I2C), make sure the peripheral and HSIOM (HSIOM_PRT_SELx) is properly configured  before turning the IO on here to avoid producing glitches on the bus.
16558Note: that peripherals other than GPIO &amp; UDB/DSI directly control both the output and output-enable of the output buffer (peripherals can drive strong 0 or strong 1 in any mode except OFF='0').
16559Note: D_OUT, D_OUT_EN are pins of GPIO cell.</description>
16560                <bitRange>[2:0]</bitRange>
16561                <access>read-write</access>
16562                <enumeratedValues>
16563                  <enumeratedValue>
16564                    <name>HIGHZ</name>
16565                    <description>Output buffer is off creating a high impedance input
16566D_OUT = '0': High Impedance
16567D_OUT = '1': High Impedance</description>
16568                    <value>0</value>
16569                  </enumeratedValue>
16570                  <enumeratedValue>
16571                    <name>RSVD</name>
16572                    <description>N/A</description>
16573                    <value>1</value>
16574                  </enumeratedValue>
16575                  <enumeratedValue>
16576                    <name>PULLUP</name>
16577                    <description>Resistive pull up
16578
16579For GPIO &amp; UDB/DSI peripherals:
16580When D_OUT_EN = 1:
16581   D_OUT = '0': Strong pull down
16582   D_OUT = '1': Weak/resistive pull up
16583When D_OUT_EN = 0:
16584   D_OUT = '0': High impedance
16585   D_OUT = '1': High impedance
16586
16587For peripherals other than GPIO &amp; UDB/DSI:
16588When D_OUT_EN = 1:
16589   D_OUT = '0': Strong pull down
16590   D_OUT = '1': Strong pull up
16591When D_OUT_EN = 0:
16592   D_OUT = '0': Weak/resistive pull up
16593   D_OUT = '1': Weak/resistive pull up</description>
16594                    <value>2</value>
16595                  </enumeratedValue>
16596                  <enumeratedValue>
16597                    <name>PULLDOWN</name>
16598                    <description>Resistive pull down
16599
16600For GPIO &amp; UDB/DSI peripherals:
16601When D_OUT_EN = 1:
16602   D_OUT = '0': Weak/resistive pull down
16603   D_OUT = '1': Strong pull up
16604When D_OUT_EN = 0:
16605   D_OUT = '0': High impedance
16606   D_OUT = '1': High impedance
16607
16608For peripherals other than GPIO &amp; UDB/DSI:
16609When D_OUT_EN = 1:
16610   D_OUT = '0': Strong pull down
16611   D_OUT = '1': Strong pull up
16612When D_OUT_EN = 0:
16613   D_OUT = '0': Weak/resistive pull down
16614   D_OUT = '1': Weak/resistive pull down</description>
16615                    <value>3</value>
16616                  </enumeratedValue>
16617                  <enumeratedValue>
16618                    <name>OD_DRIVESLOW</name>
16619                    <description>Open drain, drives low
16620
16621For GPIO &amp; UDB/DSI peripherals:
16622When D_OUT_EN = 1:
16623   D_OUT = '0': Strong pull down
16624   D_OUT = '1': High Impedance
16625When D_OUT_EN = 0:
16626   D_OUT = '0': High impedance
16627   D_OUT = '1': High impedance
16628
16629For peripherals other than GPIO &amp; UDB/DSI:
16630When D_OUT_EN = 1:
16631   D_OUT = '0': Strong pull down
16632   D_OUT = '1': Strong pull up
16633When D_OUT_EN = 0:
16634   D_OUT = '0': High Impedance
16635   D_OUT = '1': High Impedance</description>
16636                    <value>4</value>
16637                  </enumeratedValue>
16638                  <enumeratedValue>
16639                    <name>OD_DRIVESHIGH</name>
16640                    <description>Open drain, drives high
16641
16642For GPIO &amp; UDB/DSI peripherals:
16643When D_OUT_EN = 1:
16644   D_OUT = '0': High Impedance
16645   D_OUT = '1': Strong pull up
16646When D_OUT_EN = 0:
16647   D_OUT = '0': High impedance
16648   D_OUT = '1': High impedance
16649
16650For peripherals other than GPIO &amp; UDB/DSI:
16651When D_OUT_EN = 1:
16652   D_OUT = '0': Strong pull down
16653   D_OUT = '1': Strong pull up
16654When D_OUT_EN = 0:
16655   D_OUT = '0': High Impedance
16656   D_OUT = '1': High Impedance</description>
16657                    <value>5</value>
16658                  </enumeratedValue>
16659                  <enumeratedValue>
16660                    <name>STRONG</name>
16661                    <description>Strong D_OUTput buffer
16662
16663For GPIO &amp; UDB/DSI peripherals:
16664When D_OUT_EN = 1:
16665   D_OUT = '0': Strong pull down
16666   D_OUT = '1': Strong pull up
16667When D_OUT_EN = 0:
16668   D_OUT = '0': High impedance
16669   D_OUT = '1': High impedance
16670
16671For peripherals other than GPIO &amp; UDB/DSI:
16672When D_OUT_EN = 1:
16673   D_OUT = '0': Strong pull down
16674   D_OUT = '1': Strong pull up
16675When D_OUT_EN = 0:
16676   D_OUT = '0': High Impedance
16677   D_OUT = '1': High Impedance</description>
16678                    <value>6</value>
16679                  </enumeratedValue>
16680                  <enumeratedValue>
16681                    <name>PULLUP_DOWN</name>
16682                    <description>Pull up or pull down
16683
16684For GPIO &amp; UDB/DSI peripherals:
16685When D_OUT_EN = '0':
16686    GPIO_DSI_OUT = '0': Weak/resistive pull down
16687    GPIO_DSI_OUT = '1': Weak/resistive pull up
16688where 'GPIO_DSI_OUT' is a function of PORT_SEL, OUT &amp; DSI_DATA_OUT.
16689
16690For peripherals other than GPIO &amp; UDB/DSI:
16691When D_OUT_EN = 1:
16692   D_OUT = '0': Strong pull down
16693   D_OUT = '1': Strong pull up
16694When D_OUT_EN = 0:
16695    D_OUT = '0': Weak/resistive pull down
16696    D_OUT = '1': Weak/resistive pull up</description>
16697                    <value>7</value>
16698                  </enumeratedValue>
16699                </enumeratedValues>
16700              </field>
16701              <field>
16702                <name>IN_EN0</name>
16703                <description>Enables the input buffer for IO pin 0.  This bit should be cleared when analog signals are present on the pin to avoid crowbar currents.  The output buffer can be used to drive analog signals high or low without issue.
16704'0': Input buffer disabled
16705'1': Input buffer enabled</description>
16706                <bitRange>[3:3]</bitRange>
16707                <access>read-write</access>
16708              </field>
16709              <field>
16710                <name>DRIVE_MODE1</name>
16711                <description>The GPIO drive mode for IO pin 1</description>
16712                <bitRange>[6:4]</bitRange>
16713                <access>read-write</access>
16714              </field>
16715              <field>
16716                <name>IN_EN1</name>
16717                <description>Enables the input buffer for IO pin 1</description>
16718                <bitRange>[7:7]</bitRange>
16719                <access>read-write</access>
16720              </field>
16721              <field>
16722                <name>DRIVE_MODE2</name>
16723                <description>The GPIO drive mode for IO pin 2</description>
16724                <bitRange>[10:8]</bitRange>
16725                <access>read-write</access>
16726              </field>
16727              <field>
16728                <name>IN_EN2</name>
16729                <description>Enables the input buffer for IO pin 2</description>
16730                <bitRange>[11:11]</bitRange>
16731                <access>read-write</access>
16732              </field>
16733              <field>
16734                <name>DRIVE_MODE3</name>
16735                <description>The GPIO drive mode for IO pin 3</description>
16736                <bitRange>[14:12]</bitRange>
16737                <access>read-write</access>
16738              </field>
16739              <field>
16740                <name>IN_EN3</name>
16741                <description>Enables the input buffer for IO pin 3</description>
16742                <bitRange>[15:15]</bitRange>
16743                <access>read-write</access>
16744              </field>
16745              <field>
16746                <name>DRIVE_MODE4</name>
16747                <description>The GPIO drive mode for IO pin4</description>
16748                <bitRange>[18:16]</bitRange>
16749                <access>read-write</access>
16750              </field>
16751              <field>
16752                <name>IN_EN4</name>
16753                <description>Enables the input buffer for IO pin 4</description>
16754                <bitRange>[19:19]</bitRange>
16755                <access>read-write</access>
16756              </field>
16757              <field>
16758                <name>DRIVE_MODE5</name>
16759                <description>The GPIO drive mode for IO pin 5</description>
16760                <bitRange>[22:20]</bitRange>
16761                <access>read-write</access>
16762              </field>
16763              <field>
16764                <name>IN_EN5</name>
16765                <description>Enables the input buffer for IO pin 5</description>
16766                <bitRange>[23:23]</bitRange>
16767                <access>read-write</access>
16768              </field>
16769              <field>
16770                <name>DRIVE_MODE6</name>
16771                <description>The GPIO drive mode for IO pin 6</description>
16772                <bitRange>[26:24]</bitRange>
16773                <access>read-write</access>
16774              </field>
16775              <field>
16776                <name>IN_EN6</name>
16777                <description>Enables the input buffer for IO pin 6</description>
16778                <bitRange>[27:27]</bitRange>
16779                <access>read-write</access>
16780              </field>
16781              <field>
16782                <name>DRIVE_MODE7</name>
16783                <description>The GPIO drive mode for IO pin 7</description>
16784                <bitRange>[30:28]</bitRange>
16785                <access>read-write</access>
16786              </field>
16787              <field>
16788                <name>IN_EN7</name>
16789                <description>Enables the input buffer for IO pin 7</description>
16790                <bitRange>[31:31]</bitRange>
16791                <access>read-write</access>
16792              </field>
16793            </fields>
16794          </register>
16795          <register>
16796            <name>CFG_IN</name>
16797            <description>Port input buffer configuration register</description>
16798            <addressOffset>0x48</addressOffset>
16799            <size>32</size>
16800            <access>read-write</access>
16801            <resetValue>0x0</resetValue>
16802            <resetMask>0xFF</resetMask>
16803            <fields>
16804              <field>
16805                <name>VTRIP_SEL0_0</name>
16806                <description>Configures the pin 0 input buffer mode (trip points and hysteresis)</description>
16807                <bitRange>[0:0]</bitRange>
16808                <access>read-write</access>
16809                <enumeratedValues>
16810                  <enumeratedValue>
16811                    <name>CMOS</name>
16812                    <description>S40S: Input buffer compatible with CMOS and I2C interfaces</description>
16813                    <value>0</value>
16814                  </enumeratedValue>
16815                  <enumeratedValue>
16816                    <name>TTL</name>
16817                    <description>S40S: Input buffer compatible with TTL and MediaLB interfaces</description>
16818                    <value>1</value>
16819                  </enumeratedValue>
16820                </enumeratedValues>
16821              </field>
16822              <field>
16823                <name>VTRIP_SEL1_0</name>
16824                <description>Configures the pin 1 input buffer mode (trip points and hysteresis)</description>
16825                <bitRange>[1:1]</bitRange>
16826                <access>read-write</access>
16827              </field>
16828              <field>
16829                <name>VTRIP_SEL2_0</name>
16830                <description>Configures the pin 2 input buffer mode (trip points and hysteresis)</description>
16831                <bitRange>[2:2]</bitRange>
16832                <access>read-write</access>
16833              </field>
16834              <field>
16835                <name>VTRIP_SEL3_0</name>
16836                <description>Configures the pin 3 input buffer mode (trip points and hysteresis)</description>
16837                <bitRange>[3:3]</bitRange>
16838                <access>read-write</access>
16839              </field>
16840              <field>
16841                <name>VTRIP_SEL4_0</name>
16842                <description>Configures the pin 4 input buffer mode (trip points and hysteresis)</description>
16843                <bitRange>[4:4]</bitRange>
16844                <access>read-write</access>
16845              </field>
16846              <field>
16847                <name>VTRIP_SEL5_0</name>
16848                <description>Configures the pin 5 input buffer mode (trip points and hysteresis)</description>
16849                <bitRange>[5:5]</bitRange>
16850                <access>read-write</access>
16851              </field>
16852              <field>
16853                <name>VTRIP_SEL6_0</name>
16854                <description>Configures the pin 6 input buffer mode (trip points and hysteresis)</description>
16855                <bitRange>[6:6]</bitRange>
16856                <access>read-write</access>
16857              </field>
16858              <field>
16859                <name>VTRIP_SEL7_0</name>
16860                <description>Configures the pin 7 input buffer mode (trip points and hysteresis)</description>
16861                <bitRange>[7:7]</bitRange>
16862                <access>read-write</access>
16863              </field>
16864            </fields>
16865          </register>
16866          <register>
16867            <name>CFG_OUT</name>
16868            <description>Port output buffer configuration register</description>
16869            <addressOffset>0x4C</addressOffset>
16870            <size>32</size>
16871            <access>read-write</access>
16872            <resetValue>0x0</resetValue>
16873            <resetMask>0xFFFF00FF</resetMask>
16874            <fields>
16875              <field>
16876                <name>SLOW0</name>
16877                <description>Enables slow slew rate for IO pin 0
16878'0': Fast slew rate
16879'1': Slow slew rate</description>
16880                <bitRange>[0:0]</bitRange>
16881                <access>read-write</access>
16882              </field>
16883              <field>
16884                <name>SLOW1</name>
16885                <description>Enables slow slew rate for IO pin 1</description>
16886                <bitRange>[1:1]</bitRange>
16887                <access>read-write</access>
16888              </field>
16889              <field>
16890                <name>SLOW2</name>
16891                <description>Enables slow slew rate for IO pin 2</description>
16892                <bitRange>[2:2]</bitRange>
16893                <access>read-write</access>
16894              </field>
16895              <field>
16896                <name>SLOW3</name>
16897                <description>Enables slow slew rate for IO pin 3</description>
16898                <bitRange>[3:3]</bitRange>
16899                <access>read-write</access>
16900              </field>
16901              <field>
16902                <name>SLOW4</name>
16903                <description>Enables slow slew rate for IO pin 4</description>
16904                <bitRange>[4:4]</bitRange>
16905                <access>read-write</access>
16906              </field>
16907              <field>
16908                <name>SLOW5</name>
16909                <description>Enables slow slew rate for IO pin 5</description>
16910                <bitRange>[5:5]</bitRange>
16911                <access>read-write</access>
16912              </field>
16913              <field>
16914                <name>SLOW6</name>
16915                <description>Enables slow slew rate for IO pin 6</description>
16916                <bitRange>[6:6]</bitRange>
16917                <access>read-write</access>
16918              </field>
16919              <field>
16920                <name>SLOW7</name>
16921                <description>Enables slow slew rate for IO pin 7</description>
16922                <bitRange>[7:7]</bitRange>
16923                <access>read-write</access>
16924              </field>
16925              <field>
16926                <name>DRIVE_SEL0</name>
16927                <description>Sets the GPIO drive strength for IO pin 0</description>
16928                <bitRange>[17:16]</bitRange>
16929                <access>read-write</access>
16930                <enumeratedValues>
16931                  <enumeratedValue>
16932                    <name>DRIVE_SEL_ZERO</name>
16933                    <description>N/A</description>
16934                    <value>0</value>
16935                  </enumeratedValue>
16936                  <enumeratedValue>
16937                    <name>DRIVE_SEL_ONE</name>
16938                    <description>N/A</description>
16939                    <value>1</value>
16940                  </enumeratedValue>
16941                  <enumeratedValue>
16942                    <name>DRIVE_SEL_TWO</name>
16943                    <description>N/A</description>
16944                    <value>2</value>
16945                  </enumeratedValue>
16946                  <enumeratedValue>
16947                    <name>DRIVE_SEL_THREE</name>
16948                    <description>N/A</description>
16949                    <value>3</value>
16950                  </enumeratedValue>
16951                </enumeratedValues>
16952              </field>
16953              <field>
16954                <name>DRIVE_SEL1</name>
16955                <description>Sets the GPIO drive strength for IO pin 1</description>
16956                <bitRange>[19:18]</bitRange>
16957                <access>read-write</access>
16958              </field>
16959              <field>
16960                <name>DRIVE_SEL2</name>
16961                <description>Sets the GPIO drive strength for IO pin 2</description>
16962                <bitRange>[21:20]</bitRange>
16963                <access>read-write</access>
16964              </field>
16965              <field>
16966                <name>DRIVE_SEL3</name>
16967                <description>Sets the GPIO drive strength for IO pin 3</description>
16968                <bitRange>[23:22]</bitRange>
16969                <access>read-write</access>
16970              </field>
16971              <field>
16972                <name>DRIVE_SEL4</name>
16973                <description>Sets the GPIO drive strength for IO pin 4</description>
16974                <bitRange>[25:24]</bitRange>
16975                <access>read-write</access>
16976              </field>
16977              <field>
16978                <name>DRIVE_SEL5</name>
16979                <description>Sets the GPIO drive strength for IO pin 5</description>
16980                <bitRange>[27:26]</bitRange>
16981                <access>read-write</access>
16982              </field>
16983              <field>
16984                <name>DRIVE_SEL6</name>
16985                <description>Sets the GPIO drive strength for IO pin 6</description>
16986                <bitRange>[29:28]</bitRange>
16987                <access>read-write</access>
16988              </field>
16989              <field>
16990                <name>DRIVE_SEL7</name>
16991                <description>Sets the GPIO drive strength for IO pin 7</description>
16992                <bitRange>[31:30]</bitRange>
16993                <access>read-write</access>
16994              </field>
16995            </fields>
16996          </register>
16997          <register>
16998            <name>CFG_SIO</name>
16999            <description>Port SIO configuration register</description>
17000            <addressOffset>0x50</addressOffset>
17001            <size>32</size>
17002            <access>read-write</access>
17003            <resetValue>0x0</resetValue>
17004            <resetMask>0xFFFFFFFF</resetMask>
17005            <fields>
17006              <field>
17007                <name>VREG_EN01</name>
17008                <description>Selects the output buffer mode:
17009'0': Unregulated output buffer
17010'1': Regulated output buffer
17011The regulated output mode is selected ONLY if the CFG.DRIVE_MODE bits are set to the strong pull up (Z_1 = '5') mode. If the CFG.DRIVE_MODE bits are set to any other mode the regulated output buffer will be disabled and the standard CMOS output buffer is used.</description>
17012                <bitRange>[0:0]</bitRange>
17013                <access>read-write</access>
17014              </field>
17015              <field>
17016                <name>IBUF_SEL01</name>
17017                <description>Selects the input buffer mode:
170180: Singled ended input buffer
170191: Differential input buffer</description>
17020                <bitRange>[1:1]</bitRange>
17021                <access>read-write</access>
17022              </field>
17023              <field>
17024                <name>VTRIP_SEL01</name>
17025                <description>Selects the input buffer trip-point in single ended input buffer mode (IBUF_SEL = '0'):
17026'0': Input buffer functions as a CMOS input buffer.
17027'1': Input buffer functions as a TTL input buffer.
17028In differential input buffer mode (IBUF_SEL = '1')
17029'0': Trip-point is 0.5*Vddio or 0.5*Voh (depends on VREF_SEL/VOH_SEL)
17030'1': Trip-point is 0.4*Vddio or 1.0*Vref  (depends on VREF_SEL)</description>
17031                <bitRange>[2:2]</bitRange>
17032                <access>read-write</access>
17033              </field>
17034              <field>
17035                <name>VREF_SEL01</name>
17036                <description>Selects reference voltage (Vref) trip-point of the input buffer:
17037'0': Trip-point reference from pin_ref
17038'1': Trip-point reference of SRSS internal reference Vref (1.2 V)
17039'2': Trip-point reference of AMUXBUS_A
17040'3': Trip-point reference of AMUXBUS_B</description>
17041                <bitRange>[4:3]</bitRange>
17042                <access>read-write</access>
17043              </field>
17044              <field>
17045                <name>VOH_SEL01</name>
17046                <description>Selects the regulated Voh output level and trip point of the input buffer for a specific SIO pin pair. Voh depends on the selected reference voltage (VREF_SEL).
17047'0': Voh = 1*reference; e.g. reference at 1.2V -&gt; Voh = 1.2V
17048'1': Voh = 1.25*reference; e.g. reference at 1.2V -&gt; Voh = 1.5V
17049'2': Voh = 1.49*reference; e.g. reference at 1.2V -&gt; Voh = ~1.8V
17050'3': Voh = 1.67*reference; e.g. reference at 1.2V -&gt; Voh = 2V
17051'4': Voh = 2.08*reference; e.g. reference at 1.2V -&gt; Voh = 2.5V
17052'5': Voh = 2.5*reference; e.g. reference at 1.2V -&gt; Voh = 3V
17053'6': Voh = 2.78*reference; e.g. reference at 1.2V -&gt; Voh = ~3.3V
17054'7': Voh = 4.16*reference; e.g. reference at 1.2V -&gt; Voh = 5.0V
17055Note: The upper value on Voh is limited to Vddio - 400mV</description>
17056                <bitRange>[7:5]</bitRange>
17057                <access>read-write</access>
17058              </field>
17059              <field>
17060                <name>VREG_EN23</name>
17061                <description>See corresponding definition for IO pins 0 and 1</description>
17062                <bitRange>[8:8]</bitRange>
17063                <access>read-write</access>
17064              </field>
17065              <field>
17066                <name>IBUF_SEL23</name>
17067                <description>See corresponding definition for IO pins 0 and 1</description>
17068                <bitRange>[9:9]</bitRange>
17069                <access>read-write</access>
17070              </field>
17071              <field>
17072                <name>VTRIP_SEL23</name>
17073                <description>See corresponding definition for IO pins 0 and 1</description>
17074                <bitRange>[10:10]</bitRange>
17075                <access>read-write</access>
17076              </field>
17077              <field>
17078                <name>VREF_SEL23</name>
17079                <description>See corresponding definition for IO pins 0 and 1</description>
17080                <bitRange>[12:11]</bitRange>
17081                <access>read-write</access>
17082              </field>
17083              <field>
17084                <name>VOH_SEL23</name>
17085                <description>See corresponding definition for IO pins 0 and 1</description>
17086                <bitRange>[15:13]</bitRange>
17087                <access>read-write</access>
17088              </field>
17089              <field>
17090                <name>VREG_EN45</name>
17091                <description>See corresponding definition for IO pins 0 and 1</description>
17092                <bitRange>[16:16]</bitRange>
17093                <access>read-write</access>
17094              </field>
17095              <field>
17096                <name>IBUF_SEL45</name>
17097                <description>See corresponding definition for IO pins 0 and 1</description>
17098                <bitRange>[17:17]</bitRange>
17099                <access>read-write</access>
17100              </field>
17101              <field>
17102                <name>VTRIP_SEL45</name>
17103                <description>See corresponding definition for IO pins 0 and 1</description>
17104                <bitRange>[18:18]</bitRange>
17105                <access>read-write</access>
17106              </field>
17107              <field>
17108                <name>VREF_SEL45</name>
17109                <description>See corresponding definition for IO pins 0 and 1</description>
17110                <bitRange>[20:19]</bitRange>
17111                <access>read-write</access>
17112              </field>
17113              <field>
17114                <name>VOH_SEL45</name>
17115                <description>See corresponding definition for IO pins 0 and 1</description>
17116                <bitRange>[23:21]</bitRange>
17117                <access>read-write</access>
17118              </field>
17119              <field>
17120                <name>VREG_EN67</name>
17121                <description>See corresponding definition for IO pins 0 and 1</description>
17122                <bitRange>[24:24]</bitRange>
17123                <access>read-write</access>
17124              </field>
17125              <field>
17126                <name>IBUF_SEL67</name>
17127                <description>See corresponding definition for IO pins 0 and 1</description>
17128                <bitRange>[25:25]</bitRange>
17129                <access>read-write</access>
17130              </field>
17131              <field>
17132                <name>VTRIP_SEL67</name>
17133                <description>See corresponding definition for IO pins 0 and 1</description>
17134                <bitRange>[26:26]</bitRange>
17135                <access>read-write</access>
17136              </field>
17137              <field>
17138                <name>VREF_SEL67</name>
17139                <description>See corresponding definition for IO pins 0 and 1</description>
17140                <bitRange>[28:27]</bitRange>
17141                <access>read-write</access>
17142              </field>
17143              <field>
17144                <name>VOH_SEL67</name>
17145                <description>See corresponding definition for IO pins 0 and 1</description>
17146                <bitRange>[31:29]</bitRange>
17147                <access>read-write</access>
17148              </field>
17149            </fields>
17150          </register>
17151          <register>
17152            <name>CFG_IN_AUTOLVL</name>
17153            <description>Port input buffer AUTOLVL configuration register</description>
17154            <addressOffset>0x58</addressOffset>
17155            <size>32</size>
17156            <access>read-write</access>
17157            <resetValue>0x0</resetValue>
17158            <resetMask>0xFF</resetMask>
17159            <fields>
17160              <field>
17161                <name>VTRIP_SEL0_1</name>
17162                <description>Configures the input buffer mode (trip points and hysteresis) for GPIO upper bit.  Lower bit is still selected by CFG_IN.VTRIP_SEL0_0 field.  This field is used along with CFG_IN.VTRIP_SEL0_0 field as below:
17163{CFG_IN_AUTOLVL.VTRIP_SEL0_1,CFG_IN.VTRIP_SEL0_0}:
171640,0: CMOS
171650,1: TTL
171661,0: input buffer is compatible with automotive.
171671,1: input buffer is compatible with automotive.</description>
17168                <bitRange>[0:0]</bitRange>
17169                <access>read-write</access>
17170                <enumeratedValues>
17171                  <enumeratedValue>
17172                    <name>CMOS_OR_TTL</name>
17173                    <description>Input buffer compatible with CMOS/TTL interfaces as described in CFG_IN.VTRIP_SEL0_0.</description>
17174                    <value>0</value>
17175                  </enumeratedValue>
17176                  <enumeratedValue>
17177                    <name>AUTO</name>
17178                    <description>Input buffer compatible with AUTO (elevated Vil) interfaces when used along with CFG_IN.VTRIP_SEL0_0.</description>
17179                    <value>1</value>
17180                  </enumeratedValue>
17181                </enumeratedValues>
17182              </field>
17183              <field>
17184                <name>VTRIP_SEL1_1</name>
17185                <description>Input buffer compatible with automotive (elevated Vil) interfaces.</description>
17186                <bitRange>[1:1]</bitRange>
17187                <access>read-write</access>
17188              </field>
17189              <field>
17190                <name>VTRIP_SEL2_1</name>
17191                <description>Input buffer compatible with automotive (elevated Vil) interfaces.</description>
17192                <bitRange>[2:2]</bitRange>
17193                <access>read-write</access>
17194              </field>
17195              <field>
17196                <name>VTRIP_SEL3_1</name>
17197                <description>Input buffer compatible with automotive (elevated Vil) interfaces.</description>
17198                <bitRange>[3:3]</bitRange>
17199                <access>read-write</access>
17200              </field>
17201              <field>
17202                <name>VTRIP_SEL4_1</name>
17203                <description>Input buffer compatible with automotive (elevated Vil) interfaces.</description>
17204                <bitRange>[4:4]</bitRange>
17205                <access>read-write</access>
17206              </field>
17207              <field>
17208                <name>VTRIP_SEL5_1</name>
17209                <description>Input buffer compatible with automotive (elevated Vil) interfaces.</description>
17210                <bitRange>[5:5]</bitRange>
17211                <access>read-write</access>
17212              </field>
17213              <field>
17214                <name>VTRIP_SEL6_1</name>
17215                <description>Input buffer compatible with automotive (elevated Vil) interfaces.</description>
17216                <bitRange>[6:6]</bitRange>
17217                <access>read-write</access>
17218              </field>
17219              <field>
17220                <name>VTRIP_SEL7_1</name>
17221                <description>Input buffer compatible with automotive (elevated Vil) interfaces.</description>
17222                <bitRange>[7:7]</bitRange>
17223                <access>read-write</access>
17224              </field>
17225            </fields>
17226          </register>
17227          <register>
17228            <name>CFG_OUT2</name>
17229            <description>Port output buffer configuration register 2</description>
17230            <addressOffset>0x60</addressOffset>
17231            <size>32</size>
17232            <access>read-write</access>
17233            <resetValue>0x0</resetValue>
17234            <resetMask>0xFFFFFF</resetMask>
17235            <fields>
17236              <field>
17237                <name>DS_TRIM0</name>
17238                <description>Sets the Drive Select Trim for  IO pin 0
172390 - Default (50ohms)
172401 - 120ohms
172412 - 90ohms
172423 - 60ohms
172434 - 50ohms
172445 - 30ohms
172456 - 20ohms
172467 - 15ohms</description>
17247                <bitRange>[2:0]</bitRange>
17248                <access>read-write</access>
17249                <enumeratedValues>
17250                  <enumeratedValue>
17251                    <name>DEFAULT</name>
17252                    <description>N/A</description>
17253                    <value>0</value>
17254                  </enumeratedValue>
17255                  <enumeratedValue>
17256                    <name>DS_120OHM</name>
17257                    <description>N/A</description>
17258                    <value>1</value>
17259                  </enumeratedValue>
17260                  <enumeratedValue>
17261                    <name>DS_90OHM</name>
17262                    <description>N/A</description>
17263                    <value>2</value>
17264                  </enumeratedValue>
17265                  <enumeratedValue>
17266                    <name>DS_60OHM</name>
17267                    <description>N/A</description>
17268                    <value>3</value>
17269                  </enumeratedValue>
17270                  <enumeratedValue>
17271                    <name>DS_50OHM</name>
17272                    <description>N/A</description>
17273                    <value>4</value>
17274                  </enumeratedValue>
17275                  <enumeratedValue>
17276                    <name>DS_30OHM</name>
17277                    <description>N/A</description>
17278                    <value>5</value>
17279                  </enumeratedValue>
17280                  <enumeratedValue>
17281                    <name>DS_20OHM</name>
17282                    <description>N/A</description>
17283                    <value>6</value>
17284                  </enumeratedValue>
17285                  <enumeratedValue>
17286                    <name>DS_15OHM</name>
17287                    <description>N/A</description>
17288                    <value>7</value>
17289                  </enumeratedValue>
17290                </enumeratedValues>
17291              </field>
17292              <field>
17293                <name>DS_TRIM1</name>
17294                <description>Sets the Drive Select Trim for IO pin 1</description>
17295                <bitRange>[5:3]</bitRange>
17296                <access>read-write</access>
17297              </field>
17298              <field>
17299                <name>DS_TRIM2</name>
17300                <description>Sets the Drive Select Trim for IO pin 2</description>
17301                <bitRange>[8:6]</bitRange>
17302                <access>read-write</access>
17303              </field>
17304              <field>
17305                <name>DS_TRIM3</name>
17306                <description>Sets the Drive Select Trim for IO pin 3</description>
17307                <bitRange>[11:9]</bitRange>
17308                <access>read-write</access>
17309              </field>
17310              <field>
17311                <name>DS_TRIM4</name>
17312                <description>Sets the Drive Select Trim for IO pin 4</description>
17313                <bitRange>[14:12]</bitRange>
17314                <access>read-write</access>
17315              </field>
17316              <field>
17317                <name>DS_TRIM5</name>
17318                <description>Sets the Drive Select Trim for IO pin 5</description>
17319                <bitRange>[17:15]</bitRange>
17320                <access>read-write</access>
17321              </field>
17322              <field>
17323                <name>DS_TRIM6</name>
17324                <description>Sets the Drive Select Trim for IO pin 6</description>
17325                <bitRange>[20:18]</bitRange>
17326                <access>read-write</access>
17327              </field>
17328              <field>
17329                <name>DS_TRIM7</name>
17330                <description>Sets the Drive Select Trim for IO pin 7</description>
17331                <bitRange>[23:21]</bitRange>
17332                <access>read-write</access>
17333              </field>
17334            </fields>
17335          </register>
17336          <register>
17337            <name>CFG_SLEW_EXT</name>
17338            <description>Port output buffer slew extension configuration register</description>
17339            <addressOffset>0x64</addressOffset>
17340            <size>32</size>
17341            <access>read-write</access>
17342            <resetValue>0x0</resetValue>
17343            <resetMask>0x77777777</resetMask>
17344            <fields>
17345              <field>
17346                <name>SLEW0</name>
17347                <description>Enables slow slew rate for IO pin 0
17348HSIO_STDLIN:
17349slew_ctl[SLEW_WIDTH] = All 0s: Fastest slew rate
17350slew_ctl[SLEW_WIDTH] = All 1s: Slowest slew rate
17351HSIO_ENH:
17352slew_sel[SLEW_WIDTH] = All 0s: Fastest slew rate
17353slew_sel[SLEW_WIDTH] = All 1s: Slowest slew rate</description>
17354                <bitRange>[2:0]</bitRange>
17355                <access>read-write</access>
17356              </field>
17357              <field>
17358                <name>SLEW1</name>
17359                <description>Slew rate for IO pin 1</description>
17360                <bitRange>[6:4]</bitRange>
17361                <access>read-write</access>
17362              </field>
17363              <field>
17364                <name>SLEW2</name>
17365                <description>Slew rate for IO pin 2</description>
17366                <bitRange>[10:8]</bitRange>
17367                <access>read-write</access>
17368              </field>
17369              <field>
17370                <name>SLEW3</name>
17371                <description>Slew rate for IO pin 3</description>
17372                <bitRange>[14:12]</bitRange>
17373                <access>read-write</access>
17374              </field>
17375              <field>
17376                <name>SLEW4</name>
17377                <description>Slew rate for IO pin 4</description>
17378                <bitRange>[18:16]</bitRange>
17379                <access>read-write</access>
17380              </field>
17381              <field>
17382                <name>SLEW5</name>
17383                <description>Slew rate for IO pin 5</description>
17384                <bitRange>[22:20]</bitRange>
17385                <access>read-write</access>
17386              </field>
17387              <field>
17388                <name>SLEW6</name>
17389                <description>Slew rate for IO pin 6</description>
17390                <bitRange>[26:24]</bitRange>
17391                <access>read-write</access>
17392              </field>
17393              <field>
17394                <name>SLEW7</name>
17395                <description>Slew rate for IO pin 7</description>
17396                <bitRange>[30:28]</bitRange>
17397                <access>read-write</access>
17398              </field>
17399            </fields>
17400          </register>
17401          <register>
17402            <name>CFG_DRIVE_EXT0</name>
17403            <description>Port output buffer drive sel extension configuration register</description>
17404            <addressOffset>0x68</addressOffset>
17405            <size>32</size>
17406            <access>read-write</access>
17407            <resetValue>0x0</resetValue>
17408            <resetMask>0x1F1F1F1F</resetMask>
17409            <fields>
17410              <field>
17411                <name>DRIVE_SEL_EXT0</name>
17412                <description>Sets the GPIO drive strength for IO pin 0</description>
17413                <bitRange>[4:0]</bitRange>
17414                <access>read-write</access>
17415              </field>
17416              <field>
17417                <name>DRIVE_SEL_EXT1</name>
17418                <description>Sets the GPIO drive strength for IO pin 1</description>
17419                <bitRange>[12:8]</bitRange>
17420                <access>read-write</access>
17421              </field>
17422              <field>
17423                <name>DRIVE_SEL_EXT2</name>
17424                <description>Sets the GPIO drive strength for IO pin 2</description>
17425                <bitRange>[20:16]</bitRange>
17426                <access>read-write</access>
17427              </field>
17428              <field>
17429                <name>DRIVE_SEL_EXT3</name>
17430                <description>Sets the GPIO drive strength for IO pin 3</description>
17431                <bitRange>[28:24]</bitRange>
17432                <access>read-write</access>
17433              </field>
17434            </fields>
17435          </register>
17436          <register>
17437            <name>CFG_DRIVE_EXT1</name>
17438            <description>Port output buffer drive sel extension configuration register</description>
17439            <addressOffset>0x6C</addressOffset>
17440            <size>32</size>
17441            <access>read-write</access>
17442            <resetValue>0x0</resetValue>
17443            <resetMask>0x1F1F1F1F</resetMask>
17444            <fields>
17445              <field>
17446                <name>DRIVE_SEL_EXT4</name>
17447                <description>Sets the GPIO drive strength for IO pin 4</description>
17448                <bitRange>[4:0]</bitRange>
17449                <access>read-write</access>
17450              </field>
17451              <field>
17452                <name>DRIVE_SEL_EXT5</name>
17453                <description>Sets the GPIO drive strength for IO pin 5</description>
17454                <bitRange>[12:8]</bitRange>
17455                <access>read-write</access>
17456              </field>
17457              <field>
17458                <name>DRIVE_SEL_EXT6</name>
17459                <description>Sets the GPIO drive strength for IO pin 6</description>
17460                <bitRange>[20:16]</bitRange>
17461                <access>read-write</access>
17462              </field>
17463              <field>
17464                <name>DRIVE_SEL_EXT7</name>
17465                <description>Sets the GPIO drive strength for IO pin 7</description>
17466                <bitRange>[28:24]</bitRange>
17467                <access>read-write</access>
17468              </field>
17469            </fields>
17470          </register>
17471        </cluster>
17472        <register>
17473          <name>INTR_CAUSE0</name>
17474          <description>Interrupt port cause register 0</description>
17475          <addressOffset>0x4000</addressOffset>
17476          <size>32</size>
17477          <access>read-only</access>
17478          <resetValue>0x0</resetValue>
17479          <resetMask>0xFFFFFFFF</resetMask>
17480          <fields>
17481            <field>
17482              <name>PORT_INT</name>
17483              <description>Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to determine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PRT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt.
17484'0': Port has no pending interrupt
17485'1': Port has pending interrupt</description>
17486              <bitRange>[31:0]</bitRange>
17487              <access>read-only</access>
17488            </field>
17489          </fields>
17490        </register>
17491        <register>
17492          <name>INTR_CAUSE1</name>
17493          <description>Interrupt port cause register 1</description>
17494          <addressOffset>0x4004</addressOffset>
17495          <size>32</size>
17496          <access>read-only</access>
17497          <resetValue>0x0</resetValue>
17498          <resetMask>0xFFFFFFFF</resetMask>
17499          <fields>
17500            <field>
17501              <name>PORT_INT</name>
17502              <description>Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to determine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PORT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt.
17503'0': Port has no pending interrupt
17504'1': Port has pending interrupt</description>
17505              <bitRange>[31:0]</bitRange>
17506              <access>read-only</access>
17507            </field>
17508          </fields>
17509        </register>
17510        <register>
17511          <name>INTR_CAUSE2</name>
17512          <description>Interrupt port cause register 2</description>
17513          <addressOffset>0x4008</addressOffset>
17514          <size>32</size>
17515          <access>read-only</access>
17516          <resetValue>0x0</resetValue>
17517          <resetMask>0xFFFFFFFF</resetMask>
17518          <fields>
17519            <field>
17520              <name>PORT_INT</name>
17521              <description>Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to determine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PORT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt.
17522'0': Port has no pending interrupt
17523'1': Port has pending interrupt</description>
17524              <bitRange>[31:0]</bitRange>
17525              <access>read-only</access>
17526            </field>
17527          </fields>
17528        </register>
17529        <register>
17530          <name>INTR_CAUSE3</name>
17531          <description>Interrupt port cause register 3</description>
17532          <addressOffset>0x400C</addressOffset>
17533          <size>32</size>
17534          <access>read-only</access>
17535          <resetValue>0x0</resetValue>
17536          <resetMask>0xFFFFFFFF</resetMask>
17537          <fields>
17538            <field>
17539              <name>PORT_INT</name>
17540              <description>Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to determine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PORT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt.
17541'0': Port has no pending interrupt
17542'1': Port has pending interrupt</description>
17543              <bitRange>[31:0]</bitRange>
17544              <access>read-only</access>
17545            </field>
17546          </fields>
17547        </register>
17548        <register>
17549          <name>VDD_ACTIVE</name>
17550          <description>Extern power supply detection register</description>
17551          <addressOffset>0x4010</addressOffset>
17552          <size>32</size>
17553          <access>read-only</access>
17554          <resetValue>0x0</resetValue>
17555          <resetMask>0xC000FFFF</resetMask>
17556          <fields>
17557            <field>
17558              <name>VDDIO_ACTIVE</name>
17559              <description>Indicates presence or absence of VDDIO supplies (i.e. other than VDDD, VDDA) on the device (supplies are numbered 0..n-1).  Note that VDDIO supplies have basic (crude) supply detectors only.  If separate, robust, brown-out detection is desired on IO supplies, on-chip or off-chip analog resources need to provide it.  For these bits to work reliable, the supply must be within valid spec range (per datasheet) or held at ground.  Any in-between voltage has an undefined result.
17560'0': Supply is not present
17561'1': Supply is present
17562
17563When multiple VDDIO supplies are present, they will be assigned in alphanumeric ascending order to these bits during implementation.
17564For example 'vddusb, vddio_0, vddio_a, vbackup, vddio_r, vddio_1' are present then they will be assigned to these bits as below:
175650: vbackup,
175661: vddio_0,
175672: vddio_1,
175683: vddio_a,
175694: vddio_r,
175705: vddusb'</description>
17571              <bitRange>[15:0]</bitRange>
17572              <access>read-only</access>
17573            </field>
17574            <field>
17575              <name>VDDA_ACTIVE</name>
17576              <description>Same as VDDIO_ACTIVE for the analog supply VDDA.</description>
17577              <bitRange>[30:30]</bitRange>
17578              <access>read-only</access>
17579            </field>
17580            <field>
17581              <name>VDDD_ACTIVE</name>
17582              <description>This bit indicates presence of the VDDD supply.  This bit will always read-back 1.  The VDDD supply has robust brown-out protection monitoring and it is not possible to read back this register without a valid supply. (This bit is used in certain test-modes to observe the brown-out detector status.)</description>
17583              <bitRange>[31:31]</bitRange>
17584              <access>read-only</access>
17585            </field>
17586          </fields>
17587        </register>
17588        <register>
17589          <name>VDD_INTR</name>
17590          <description>Supply detection interrupt register</description>
17591          <addressOffset>0x4014</addressOffset>
17592          <size>32</size>
17593          <access>read-write</access>
17594          <resetValue>0x0</resetValue>
17595          <resetMask>0xC000FFFF</resetMask>
17596          <fields>
17597            <field>
17598              <name>VDDIO_ACTIVE</name>
17599              <description>Supply state change detected.
17600'0': No change to supply detected
17601'1': Change to supply detected</description>
17602              <bitRange>[15:0]</bitRange>
17603              <access>read-write</access>
17604            </field>
17605            <field>
17606              <name>VDDA_ACTIVE</name>
17607              <description>Same as VDDIO_ACTIVE for the analog supply VDDA.</description>
17608              <bitRange>[30:30]</bitRange>
17609              <access>read-write</access>
17610            </field>
17611            <field>
17612              <name>VDDD_ACTIVE</name>
17613              <description>The VDDD supply is always present during operation so a supply transition can not occur. This bit will always read back '1'.</description>
17614              <bitRange>[31:31]</bitRange>
17615              <access>read-write</access>
17616            </field>
17617          </fields>
17618        </register>
17619        <register>
17620          <name>VDD_INTR_MASK</name>
17621          <description>Supply detection interrupt mask register</description>
17622          <addressOffset>0x4018</addressOffset>
17623          <size>32</size>
17624          <access>read-write</access>
17625          <resetValue>0x0</resetValue>
17626          <resetMask>0xC000FFFF</resetMask>
17627          <fields>
17628            <field>
17629              <name>VDDIO_ACTIVE</name>
17630              <description>Masks supply interrupt on VDDIO.
17631'0': VDDIO interrupt forwarding disabled
17632'1': VDDIO interrupt forwarding enabled</description>
17633              <bitRange>[15:0]</bitRange>
17634              <access>read-write</access>
17635            </field>
17636            <field>
17637              <name>VDDA_ACTIVE</name>
17638              <description>Same as VDDIO_ACTIVE for the analog supply VDDA.</description>
17639              <bitRange>[30:30]</bitRange>
17640              <access>read-write</access>
17641            </field>
17642            <field>
17643              <name>VDDD_ACTIVE</name>
17644              <description>Same as VDDIO_ACTIVE for the digital supply VDDD.</description>
17645              <bitRange>[31:31]</bitRange>
17646              <access>read-write</access>
17647            </field>
17648          </fields>
17649        </register>
17650        <register>
17651          <name>VDD_INTR_MASKED</name>
17652          <description>Supply detection interrupt masked register</description>
17653          <addressOffset>0x401C</addressOffset>
17654          <size>32</size>
17655          <access>read-only</access>
17656          <resetValue>0x0</resetValue>
17657          <resetMask>0xC000FFFF</resetMask>
17658          <fields>
17659            <field>
17660              <name>VDDIO_ACTIVE</name>
17661              <description>Supply transition detected AND masked
17662'0': Interrupt was not forwarded to CPU
17663'1': Interrupt occurred and was forwarded to CPU</description>
17664              <bitRange>[15:0]</bitRange>
17665              <access>read-only</access>
17666            </field>
17667            <field>
17668              <name>VDDA_ACTIVE</name>
17669              <description>Same as VDDIO_ACTIVE for the analog supply VDDA.</description>
17670              <bitRange>[30:30]</bitRange>
17671              <access>read-only</access>
17672            </field>
17673            <field>
17674              <name>VDDD_ACTIVE</name>
17675              <description>Same as VDDIO_ACTIVE for the digital supply VDDD.</description>
17676              <bitRange>[31:31]</bitRange>
17677              <access>read-only</access>
17678            </field>
17679          </fields>
17680        </register>
17681        <register>
17682          <name>VDD_INTR_SET</name>
17683          <description>Supply detection interrupt set register</description>
17684          <addressOffset>0x4020</addressOffset>
17685          <size>32</size>
17686          <access>read-write</access>
17687          <resetValue>0x0</resetValue>
17688          <resetMask>0xC000FFFF</resetMask>
17689          <fields>
17690            <field>
17691              <name>VDDIO_ACTIVE</name>
17692              <description>Sets supply interrupt.
17693'0': Interrupt state not affected
17694'1': Interrupt set</description>
17695              <bitRange>[15:0]</bitRange>
17696              <access>read-write</access>
17697            </field>
17698            <field>
17699              <name>VDDA_ACTIVE</name>
17700              <description>Same as VDDIO_ACTIVE for the analog supply VDDA.</description>
17701              <bitRange>[30:30]</bitRange>
17702              <access>read-write</access>
17703            </field>
17704            <field>
17705              <name>VDDD_ACTIVE</name>
17706              <description>Same as VDDIO_ACTIVE for the digital supply VDDD.</description>
17707              <bitRange>[31:31]</bitRange>
17708              <access>read-write</access>
17709            </field>
17710          </fields>
17711        </register>
17712        <register>
17713          <name>VDD_LVL</name>
17714          <description>External power supply level register</description>
17715          <addressOffset>0x4024</addressOffset>
17716          <size>32</size>
17717          <access>read-only</access>
17718          <resetValue>0x0</resetValue>
17719          <resetMask>0xFFFF</resetMask>
17720          <fields>
17721            <field>
17722              <name>VDDIO_LVL</name>
17723              <description>The VDD_LVL circuit detects the VDDIO supply level and writes the detected value in this register. '0' indicates the VDDIO supply is at 1.2V and '1' indicates VDDIO supply is at 1.8V.</description>
17724              <bitRange>[15:0]</bitRange>
17725              <access>read-only</access>
17726            </field>
17727          </fields>
17728        </register>
17729      </registers>
17730    </peripheral>
17731    <peripheral>
17732      <name>PDM0</name>
17733      <description>PDM</description>
17734      <headerStructName>PDM</headerStructName>
17735      <baseAddress>0x40320000</baseAddress>
17736      <addressBlock>
17737        <offset>0</offset>
17738        <size>65536</size>
17739        <usage>registers</usage>
17740      </addressBlock>
17741      <registers>
17742        <register>
17743          <name>CTL</name>
17744          <description>Control</description>
17745          <addressOffset>0x0</addressOffset>
17746          <size>32</size>
17747          <access>read-write</access>
17748          <resetValue>0x0</resetValue>
17749          <resetMask>0xFF</resetMask>
17750          <fields>
17751            <field>
17752              <name>ACTIVE</name>
17753              <description>Activate functionality (1 bit for each channel):
17754'0': Reception disabled. The FIFO_OVERFLOW interrupt cause will not be activated.
17755'1': Reception enabled. The FIFO_OVERFLOW interrupt may be activated (when an overflow event occurs).
17756
17757Note: This functionality is intended for startup purposes. Typically, the startup sequence is as follows:
17758- global registers CLOCK_CTL, ROUTE_CTL, TEST_CTL, FIR*_COEFF* are initialized
17759- One or more structures are enabled (structure specific CTL.ENABLED register field is set to '1').
17760- The structures are initialized (structure specific MMIO registers are written).
17761- The structures are activated. This last step is performed by writing the CTL or CTL_SET MMIO registers, or on a rising edge ('0' to '1' transition) of a receiver's 'tr_activate' input trigger.
17762
17763Note: on a rising edge ('0' to '1' transition) of a receiver's 'tr_activate' input trigger, its associated CTL.ACTIVE field is set to '1'. This allows HW based synchronization of PDM receiver activation based on system triggers. Implementation note: the trigger is synchronized on the receiver clock with the receiver reset (this requires the receiver to be enabled; i.e. CTL.ENABLED is '1').
17764
17765Note: if CTL_CLR.ACTIVE[i] is written to '1' at the same time a rising edge of 'tr_activate[i]' occurs, CTL.ACTIVE[i] is set to '1' (i.e. trigger takes precedence).</description>
17766              <bitRange>[7:0]</bitRange>
17767              <access>read-write</access>
17768            </field>
17769          </fields>
17770        </register>
17771        <register>
17772          <name>CTL_CLR</name>
17773          <description>Control clear</description>
17774          <addressOffset>0x4</addressOffset>
17775          <size>32</size>
17776          <access>read-write</access>
17777          <resetValue>0x0</resetValue>
17778          <resetMask>0xFF</resetMask>
17779          <fields>
17780            <field>
17781              <name>ACTIVE</name>
17782              <description>Activate functionality:
17783'0': No effect.
17784'1': Bit is set to '0'.</description>
17785              <bitRange>[7:0]</bitRange>
17786              <access>read-write</access>
17787            </field>
17788          </fields>
17789        </register>
17790        <register>
17791          <name>CTL_SET</name>
17792          <description>Control set</description>
17793          <addressOffset>0x8</addressOffset>
17794          <size>32</size>
17795          <access>read-write</access>
17796          <resetValue>0x0</resetValue>
17797          <resetMask>0xFF</resetMask>
17798          <fields>
17799            <field>
17800              <name>ACTIVE</name>
17801              <description>Activate functionality:
17802'0': No effect.
17803'1': Bit is set to '1'.</description>
17804              <bitRange>[7:0]</bitRange>
17805              <access>read-write</access>
17806            </field>
17807          </fields>
17808        </register>
17809        <register>
17810          <name>CLOCK_CTL</name>
17811          <description>Clock control</description>
17812          <addressOffset>0x10</addressOffset>
17813          <size>32</size>
17814          <access>read-write</access>
17815          <resetValue>0x307</resetValue>
17816          <resetMask>0x103FF</resetMask>
17817          <fields>
17818            <field>
17819              <name>CLOCK_DIV</name>
17820              <description>PDM interface clock divider (legal range [3, 255]). The PDM interface clock clk_pdm ('pdm_clk[]' output signals) is defined as pdm_clk = clk_if / (CLOCK_DIV + 1); i.e. each PDM interface clock cycle equals CLOCK_DIV + 1 clk_if clock cycles. CLOCK_DIV should be set to an odd value ([3, 5, ..., 255]), to ensure a 50/50 percent duty cycle PDM interface clock pdm_clk.
17821'0-2': Illegal value.
17822'3': pdm_clk frequency is 1/4 clk_if frequency (1 pdm_clk cycle consists of 4 clk_if cycles).
17823'4': pdm_clk frequency is 1/5 clk_if frequency. Note: results in a non 50/50 percent duty cycle pdm_clk).
17824...
17825'255': pdm_clk frequency is 1/256 clk_if frequency.</description>
17826              <bitRange>[7:0]</bitRange>
17827              <access>read-write</access>
17828            </field>
17829            <field>
17830              <name>CLOCK_SEL</name>
17831              <description>Interface clock clk_if selection:
17832'0': SRSS clock clk_if_srss.
17833'1': IOSS data input signal 'pdm_data[0]'.
17834'2': IOSS data input signal 'pdm_data[1]'.
17835'3': undefined.
17836
17837Note: when a data input signal is used as a clock source, it cannot be used as a data line.
17838
17839Note: the application is always required to program this field to a value different from the default.</description>
17840              <bitRange>[9:8]</bitRange>
17841              <access>read-write</access>
17842              <enumeratedValues>
17843                <enumeratedValue>
17844                  <name>SEL_SRSS_CLOCK</name>
17845                  <description>N/A</description>
17846                  <value>0</value>
17847                </enumeratedValue>
17848                <enumeratedValue>
17849                  <name>SEL_PDM_DATA0</name>
17850                  <description>N/A</description>
17851                  <value>1</value>
17852                </enumeratedValue>
17853                <enumeratedValue>
17854                  <name>SEL_PDM_DATA1</name>
17855                  <description>N/A</description>
17856                  <value>2</value>
17857                </enumeratedValue>
17858                <enumeratedValue>
17859                  <name>SEL_OR</name>
17860                  <description>N/A</description>
17861                  <value>3</value>
17862                </enumeratedValue>
17863              </enumeratedValues>
17864            </field>
17865            <field>
17866              <name>HALVE</name>
17867              <description>Halve rate sampling:
17868'0': Full rate sampling. The PDM interface clock pdm_clk is as specified by CLOCK_DIV[]. Each captured PDM value is provided once to the CIC filter.
17869'1': Halve rate sampling. The PDM interface clock clk_pdm is as specified by CLOCK_DIV[] divided by two (halve the frequency). Each PDM value is captured twice and provided twice to the CIC filter; i.e. the PDM value is repeated.
17870
17871Note: this field is provided to dynamically change the digital microphone's clock (pdm_clk) without affecting the PDM sample frequency towards the CIC filter. Halving the microphone clock results in lower system power consumption, but does lower audio quality.</description>
17872              <bitRange>[16:16]</bitRange>
17873              <access>read-write</access>
17874              <enumeratedValues>
17875                <enumeratedValue>
17876                  <name>FULL</name>
17877                  <description>N/A</description>
17878                  <value>0</value>
17879                </enumeratedValue>
17880                <enumeratedValue>
17881                  <name>HALVE</name>
17882                  <description>N/A</description>
17883                  <value>1</value>
17884                </enumeratedValue>
17885              </enumeratedValues>
17886            </field>
17887          </fields>
17888        </register>
17889        <register>
17890          <name>ROUTE_CTL</name>
17891          <description>Route control</description>
17892          <addressOffset>0x20</addressOffset>
17893          <size>32</size>
17894          <access>read-write</access>
17895          <resetValue>0x0</resetValue>
17896          <resetMask>0xFF</resetMask>
17897          <fields>
17898            <field>
17899              <name>DATA_SEL</name>
17900              <description>Specifies what IOSS data input signal 'pdm_data[]' is routed to a specific PDM receiver. Each PDM receiver j has a dedicated 1-bit control field: PDM receiver j uses DATA_SEL[j]. The 1-bit field DATA_SEL[j] specification is as follows:
17901'0': PDM receiver j uses data input signal 'pdm_data[j]'.
17902'1': PDM receiver j uses data input signal 'pdm_data[j ^ 1]' (the lower bit of the index is inverted).
17903
17904Routing the same data input signal to two PDM receivers allows for:
17905- A single stereo digital microphone.
17906- Two (mono) digital microphones that share a data line.
17907
17908E.g., if DATA_SEL is 0b00000010, PDM receivers 0 and 1 BOTH use 'pdm_data[0]'.</description>
17909              <bitRange>[7:0]</bitRange>
17910              <access>read-write</access>
17911            </field>
17912          </fields>
17913        </register>
17914        <register>
17915          <name>TEST_CTL</name>
17916          <description>Test control</description>
17917          <addressOffset>0x30</addressOffset>
17918          <size>32</size>
17919          <access>read-write</access>
17920          <resetValue>0x7F0400</resetValue>
17921          <resetMask>0xFFFFFFFF</resetMask>
17922          <fields>
17923            <field>
17924              <name>DRIVE_DELAY_HI</name>
17925              <description>Interface drive delay on the high phase of the PDM interface clock. This field specifies when a PDM value is driven expressed in clk_if clock cycles. DRIVE_DELAY should be set in the range [0, IF_CTL.CLOCK_DIV]:
17926'0': Drive PDM value 1 clk_if cycle after the rising edge of clk_pdm.
17927'1': Drive PDM value 2 clk_if cycles after the rising edge of clk_pdm.
17928...
17929'255': Drive PDM value 256 clk_if cycles after the rising edge of clk_pdm.
17930
17931Note: To drive on the falling edge of the PDM interface clock clk_pdm, DRIVE_DELAY should be set to IF_CTL.CLOCK_DIV/2. To drive on the rising edge of clk_pdm, DRIVE_DELAY should be set to IF_CTL.CLOCK_DIV.</description>
17932              <bitRange>[7:0]</bitRange>
17933              <access>read-write</access>
17934            </field>
17935            <field>
17936              <name>DRIVE_DELAY_LO</name>
17937              <description>Interface drive delay on the low phase of the PDM interface clock. This field specifies when a PDM value is driven expressed in clk_if clock cycles. DRIVE_DELAY should be set in the range [0, IF_CTL.CLOCK_DIV]:
17938'0': Drive PDM value 1 clk_if cycle after the rising edge of clk_pdm.
17939'1': Drive PDM value 2 clk_if cycles after the rising edge of clk_pdm.
17940...
17941'255': Drive PDM value 256 clk_if cycles after the rising edge of clk_pdm.
17942
17943Note: To drive on the falling edge of the PDM interface clock clk_pdm, DRIVE_DELAY should be set to IF_CTL.CLOCK_DIV/2. To drive on the rising edge of clk_pdm, DRIVE_DELAY should be set to IF_CTL.CLOCK_DIV.</description>
17944              <bitRange>[15:8]</bitRange>
17945              <access>read-write</access>
17946            </field>
17947            <field>
17948              <name>MODE_HI</name>
17949              <description>Pattern generator mode on the high phase of the PDM interface clock. This field specifies the type of PDM pattern driven by the generator:
17950'0': constant 0's
17951'1': constant 1's
17952'2': alternating 0's and 1's (clock pattern)
17953'3': sinusoid</description>
17954              <bitRange>[17:16]</bitRange>
17955              <access>read-write</access>
17956              <enumeratedValues>
17957                <enumeratedValue>
17958                  <name>CONSTANT_0</name>
17959                  <description>N/A</description>
17960                  <value>0</value>
17961                </enumeratedValue>
17962                <enumeratedValue>
17963                  <name>CONSTANT_1</name>
17964                  <description>N/A</description>
17965                  <value>1</value>
17966                </enumeratedValue>
17967                <enumeratedValue>
17968                  <name>ALTERNATING</name>
17969                  <description>N/A</description>
17970                  <value>2</value>
17971                </enumeratedValue>
17972                <enumeratedValue>
17973                  <name>SINUSOID</name>
17974                  <description>N/A</description>
17975                  <value>3</value>
17976                </enumeratedValue>
17977              </enumeratedValues>
17978            </field>
17979            <field>
17980              <name>MODE_LO</name>
17981              <description>Pattern generator mode on the low phase of the PDM interface clock. This field specifies the type of pattern driven by the generator:
17982'0': constant 0's
17983'1': constant 1's
17984'2': alternating 0's and 1's (clock pattern)
17985'3': sine wave</description>
17986              <bitRange>[19:18]</bitRange>
17987              <access>read-write</access>
17988              <enumeratedValues>
17989                <enumeratedValue>
17990                  <name>CONSTANT_0</name>
17991                  <description>N/A</description>
17992                  <value>0</value>
17993                </enumeratedValue>
17994                <enumeratedValue>
17995                  <name>CONSTANT_1</name>
17996                  <description>N/A</description>
17997                  <value>1</value>
17998                </enumeratedValue>
17999                <enumeratedValue>
18000                  <name>ALTERNATING</name>
18001                  <description>N/A</description>
18002                  <value>2</value>
18003                </enumeratedValue>
18004                <enumeratedValue>
18005                  <name>SINUSOID</name>
18006                  <description>N/A</description>
18007                  <value>3</value>
18008                </enumeratedValue>
18009              </enumeratedValues>
18010            </field>
18011            <field>
18012              <name>AUDIO_FREQ_DIV</name>
18013              <description>Frequency division factor (legal range [3, 13]) to obtain audio frequency from the PDM clock frequency. This field determines the frequency of the sine wave generated by the pattern generator when MODE=3. The formula is below:
18014
18015Sine wave Frequency = PDM clock frequency / 2p*2^(AUDIO_FREQ_DIV)
18016
18017Example: when PDM clock frequency = 3.072 MHz the audio frequencies obtained for the various values of AUDIO_FREQ_DIV are shown below:
18018
18019'3' : 61.115 kHz
18020'4' : 30.558 kHz
18021'5' : 15.279 kHz
18022'6' : 7.639 kHz
18023'7' : 3.820 kHz
18024'8' : 1.910 kHz
18025'9' : 955 Hz
18026'10' : 477 Hz
18027'11' : 239 Hz
18028'12' : 119 Hz
18029'13' : 60 Hz</description>
18030              <bitRange>[23:20]</bitRange>
18031              <access>read-write</access>
18032              <enumeratedValues>
18033                <enumeratedValue>
18034                  <name>DIV_PDM_FREQ_BY_2PI_x_8</name>
18035                  <description>Example: 3.072 MHz/(2p*8) = 61.115 kHz</description>
18036                  <value>3</value>
18037                </enumeratedValue>
18038                <enumeratedValue>
18039                  <name>DIV_PDM_FREQ_BY_2PI_x_16</name>
18040                  <description>Example: 3.072 MHz/(2p*16) = 30.558 kHz</description>
18041                  <value>4</value>
18042                </enumeratedValue>
18043                <enumeratedValue>
18044                  <name>DIV_PDM_FREQ_BY_2PI_x_8192</name>
18045                  <description>Example: 3.072 MHz/(2p*8192) = 60 Hz</description>
18046                  <value>13</value>
18047                </enumeratedValue>
18048              </enumeratedValues>
18049            </field>
18050            <field>
18051              <name>CH_ENABLED</name>
18052              <description>Pattern generator enable (1 bit for each channel):
18053'0' : disabled, the channel input is taken as normal from external pin pdm_data_in
18054'1' : enabled, the channel input is taken from the pattern generator
18055
18056Note: the pattern generator output is routed to pdm_data_out for testing purposes
18057
18058Note: when all channels are disabled the pattern generator is switched off</description>
18059              <bitRange>[31:24]</bitRange>
18060              <access>read-write</access>
18061            </field>
18062          </fields>
18063        </register>
18064        <register>
18065          <name>FIR0_COEFF0</name>
18066          <description>FIR 0 coefficients 0</description>
18067          <addressOffset>0x100</addressOffset>
18068          <size>32</size>
18069          <access>read-write</access>
18070          <resetValue>0x0</resetValue>
18071          <resetMask>0x0</resetMask>
18072          <fields>
18073            <field>
18074              <name>DATA0</name>
18075              <description>Filter taps 0 and 29 coefficient.</description>
18076              <bitRange>[13:0]</bitRange>
18077              <access>read-write</access>
18078            </field>
18079            <field>
18080              <name>DATA1</name>
18081              <description>Filter taps 1 and 28 coefficient.</description>
18082              <bitRange>[29:16]</bitRange>
18083              <access>read-write</access>
18084            </field>
18085          </fields>
18086        </register>
18087        <register>
18088          <name>FIR0_COEFF1</name>
18089          <description>FIR 0 coefficients 1</description>
18090          <addressOffset>0x104</addressOffset>
18091          <size>32</size>
18092          <access>read-write</access>
18093          <resetValue>0x0</resetValue>
18094          <resetMask>0x0</resetMask>
18095          <fields>
18096            <field>
18097              <name>DATA0</name>
18098              <description>Filter taps 2 and 27 coefficient.</description>
18099              <bitRange>[13:0]</bitRange>
18100              <access>read-write</access>
18101            </field>
18102            <field>
18103              <name>DATA1</name>
18104              <description>Filter taps 3 and 26 coefficient.</description>
18105              <bitRange>[29:16]</bitRange>
18106              <access>read-write</access>
18107            </field>
18108          </fields>
18109        </register>
18110        <register>
18111          <name>FIR0_COEFF2</name>
18112          <description>FIR 0 coefficients 2</description>
18113          <addressOffset>0x108</addressOffset>
18114          <size>32</size>
18115          <access>read-write</access>
18116          <resetValue>0x0</resetValue>
18117          <resetMask>0x0</resetMask>
18118          <fields>
18119            <field>
18120              <name>DATA0</name>
18121              <description>Filter taps 4 and 25 coefficient.</description>
18122              <bitRange>[13:0]</bitRange>
18123              <access>read-write</access>
18124            </field>
18125            <field>
18126              <name>DATA1</name>
18127              <description>Filter taps 5 and 24 coefficient.</description>
18128              <bitRange>[29:16]</bitRange>
18129              <access>read-write</access>
18130            </field>
18131          </fields>
18132        </register>
18133        <register>
18134          <name>FIR0_COEFF3</name>
18135          <description>FIR 0 coefficients 3</description>
18136          <addressOffset>0x10C</addressOffset>
18137          <size>32</size>
18138          <access>read-write</access>
18139          <resetValue>0x0</resetValue>
18140          <resetMask>0x0</resetMask>
18141          <fields>
18142            <field>
18143              <name>DATA0</name>
18144              <description>Filter taps 6 and 23 coefficient.</description>
18145              <bitRange>[13:0]</bitRange>
18146              <access>read-write</access>
18147            </field>
18148            <field>
18149              <name>DATA1</name>
18150              <description>Filter taps 7 and 22 coefficient.</description>
18151              <bitRange>[29:16]</bitRange>
18152              <access>read-write</access>
18153            </field>
18154          </fields>
18155        </register>
18156        <register>
18157          <name>FIR0_COEFF4</name>
18158          <description>FIR 0 coefficients 4</description>
18159          <addressOffset>0x110</addressOffset>
18160          <size>32</size>
18161          <access>read-write</access>
18162          <resetValue>0x0</resetValue>
18163          <resetMask>0x0</resetMask>
18164          <fields>
18165            <field>
18166              <name>DATA0</name>
18167              <description>Filter taps 8 and 21 coefficient.</description>
18168              <bitRange>[13:0]</bitRange>
18169              <access>read-write</access>
18170            </field>
18171            <field>
18172              <name>DATA1</name>
18173              <description>Filter taps 9 and 20 coefficient.</description>
18174              <bitRange>[29:16]</bitRange>
18175              <access>read-write</access>
18176            </field>
18177          </fields>
18178        </register>
18179        <register>
18180          <name>FIR0_COEFF5</name>
18181          <description>FIR 0 coefficients 5</description>
18182          <addressOffset>0x114</addressOffset>
18183          <size>32</size>
18184          <access>read-write</access>
18185          <resetValue>0x0</resetValue>
18186          <resetMask>0x0</resetMask>
18187          <fields>
18188            <field>
18189              <name>DATA0</name>
18190              <description>Filter taps 10 and 19 coefficient.</description>
18191              <bitRange>[13:0]</bitRange>
18192              <access>read-write</access>
18193            </field>
18194            <field>
18195              <name>DATA1</name>
18196              <description>Filter taps 11 and 18 coefficient.</description>
18197              <bitRange>[29:16]</bitRange>
18198              <access>read-write</access>
18199            </field>
18200          </fields>
18201        </register>
18202        <register>
18203          <name>FIR0_COEFF6</name>
18204          <description>FIR 0 coefficients 6</description>
18205          <addressOffset>0x118</addressOffset>
18206          <size>32</size>
18207          <access>read-write</access>
18208          <resetValue>0x0</resetValue>
18209          <resetMask>0x0</resetMask>
18210          <fields>
18211            <field>
18212              <name>DATA0</name>
18213              <description>Filter taps 12 and 17 coefficient.</description>
18214              <bitRange>[13:0]</bitRange>
18215              <access>read-write</access>
18216            </field>
18217            <field>
18218              <name>DATA1</name>
18219              <description>Filter taps 13 and 16 coefficient.</description>
18220              <bitRange>[29:16]</bitRange>
18221              <access>read-write</access>
18222            </field>
18223          </fields>
18224        </register>
18225        <register>
18226          <name>FIR0_COEFF7</name>
18227          <description>FIR 0 coefficients 7</description>
18228          <addressOffset>0x11C</addressOffset>
18229          <size>32</size>
18230          <access>read-write</access>
18231          <resetValue>0x0</resetValue>
18232          <resetMask>0x0</resetMask>
18233          <fields>
18234            <field>
18235              <name>DATA0</name>
18236              <description>Filter tap 14 coefficient.</description>
18237              <bitRange>[13:0]</bitRange>
18238              <access>read-write</access>
18239            </field>
18240            <field>
18241              <name>DATA1</name>
18242              <description>Filter tap 15 coefficient.</description>
18243              <bitRange>[29:16]</bitRange>
18244              <access>read-write</access>
18245            </field>
18246          </fields>
18247        </register>
18248        <register>
18249          <name>FIR1_COEFF0</name>
18250          <description>FIR 1 coefficients 0</description>
18251          <addressOffset>0x140</addressOffset>
18252          <size>32</size>
18253          <access>read-write</access>
18254          <resetValue>0x153FFE</resetValue>
18255          <resetMask>0x3FFF3FFF</resetMask>
18256          <fields>
18257            <field>
18258              <name>DATA0</name>
18259              <description>Filter taps 0 and 54 coefficient (default value -2).</description>
18260              <bitRange>[13:0]</bitRange>
18261              <access>read-write</access>
18262            </field>
18263            <field>
18264              <name>DATA1</name>
18265              <description>Filter taps 1 and 53 coefficient (default value 21).</description>
18266              <bitRange>[29:16]</bitRange>
18267              <access>read-write</access>
18268            </field>
18269          </fields>
18270        </register>
18271        <register>
18272          <name>FIR1_COEFF1</name>
18273          <description>FIR 1 coefficients 1</description>
18274          <addressOffset>0x144</addressOffset>
18275          <size>32</size>
18276          <access>read-write</access>
18277          <resetValue>0x3FEF001A</resetValue>
18278          <resetMask>0x3FFF3FFF</resetMask>
18279          <fields>
18280            <field>
18281              <name>DATA0</name>
18282              <description>Filter taps 2 and 52 coefficient (default value 26).</description>
18283              <bitRange>[13:0]</bitRange>
18284              <access>read-write</access>
18285            </field>
18286            <field>
18287              <name>DATA1</name>
18288              <description>Filter taps 3 and 51 coefficient (default value -17).</description>
18289              <bitRange>[29:16]</bitRange>
18290              <access>read-write</access>
18291            </field>
18292          </fields>
18293        </register>
18294        <register>
18295          <name>FIR1_COEFF2</name>
18296          <description>FIR 1 coefficients 2</description>
18297          <addressOffset>0x148</addressOffset>
18298          <size>32</size>
18299          <access>read-write</access>
18300          <resetValue>0x193FD7</resetValue>
18301          <resetMask>0x3FFF3FFF</resetMask>
18302          <fields>
18303            <field>
18304              <name>DATA0</name>
18305              <description>Filter taps 4 and 50 coefficient (default value -41).</description>
18306              <bitRange>[13:0]</bitRange>
18307              <access>read-write</access>
18308            </field>
18309            <field>
18310              <name>DATA1</name>
18311              <description>Filter taps 5 and 49 coefficient (default value 25).</description>
18312              <bitRange>[29:16]</bitRange>
18313              <access>read-write</access>
18314            </field>
18315          </fields>
18316        </register>
18317        <register>
18318          <name>FIR1_COEFF3</name>
18319          <description>FIR 1 coefficients 3</description>
18320          <addressOffset>0x14C</addressOffset>
18321          <size>32</size>
18322          <access>read-write</access>
18323          <resetValue>0x3FDF0044</resetValue>
18324          <resetMask>0x3FFF3FFF</resetMask>
18325          <fields>
18326            <field>
18327              <name>DATA0</name>
18328              <description>Filter taps 6 and 48 coefficient (default value 68).</description>
18329              <bitRange>[13:0]</bitRange>
18330              <access>read-write</access>
18331            </field>
18332            <field>
18333              <name>DATA1</name>
18334              <description>Filter taps 7 and 47 coefficient (default value -33).</description>
18335              <bitRange>[29:16]</bitRange>
18336              <access>read-write</access>
18337            </field>
18338          </fields>
18339        </register>
18340        <register>
18341          <name>FIR1_COEFF4</name>
18342          <description>FIR 1 coefficients 4</description>
18343          <addressOffset>0x150</addressOffset>
18344          <size>32</size>
18345          <access>read-write</access>
18346          <resetValue>0x293F95</resetValue>
18347          <resetMask>0x3FFF3FFF</resetMask>
18348          <fields>
18349            <field>
18350              <name>DATA0</name>
18351              <description>Filter taps 8 and 46 coefficient (default value -107).</description>
18352              <bitRange>[13:0]</bitRange>
18353              <access>read-write</access>
18354            </field>
18355            <field>
18356              <name>DATA1</name>
18357              <description>Filter taps 9 and 45 coefficient (default value 41).</description>
18358              <bitRange>[29:16]</bitRange>
18359              <access>read-write</access>
18360            </field>
18361          </fields>
18362        </register>
18363        <register>
18364          <name>FIR1_COEFF5</name>
18365          <description>FIR 1 coefficients 5</description>
18366          <addressOffset>0x154</addressOffset>
18367          <size>32</size>
18368          <access>read-write</access>
18369          <resetValue>0x3FD000A0</resetValue>
18370          <resetMask>0x3FFF3FFF</resetMask>
18371          <fields>
18372            <field>
18373              <name>DATA0</name>
18374              <description>Filter taps 10 and 44 coefficient (default value 160).</description>
18375              <bitRange>[13:0]</bitRange>
18376              <access>read-write</access>
18377            </field>
18378            <field>
18379              <name>DATA1</name>
18380              <description>Filter taps 11 and 43 coefficient (default value -48).</description>
18381              <bitRange>[29:16]</bitRange>
18382              <access>read-write</access>
18383            </field>
18384          </fields>
18385        </register>
18386        <register>
18387          <name>FIR1_COEFF6</name>
18388          <description>FIR 1 coefficients 6</description>
18389          <addressOffset>0x158</addressOffset>
18390          <size>32</size>
18391          <access>read-write</access>
18392          <resetValue>0x363F1A</resetValue>
18393          <resetMask>0x3FFF3FFF</resetMask>
18394          <fields>
18395            <field>
18396              <name>DATA0</name>
18397              <description>Filter taps 12 and 42 coefficient (default value -230).</description>
18398              <bitRange>[13:0]</bitRange>
18399              <access>read-write</access>
18400            </field>
18401            <field>
18402              <name>DATA1</name>
18403              <description>Filter taps 13 and 41 coefficient (default value 54).</description>
18404              <bitRange>[29:16]</bitRange>
18405              <access>read-write</access>
18406            </field>
18407          </fields>
18408        </register>
18409        <register>
18410          <name>FIR1_COEFF7</name>
18411          <description>FIR 1 coefficients 7</description>
18412          <addressOffset>0x15C</addressOffset>
18413          <size>32</size>
18414          <access>read-write</access>
18415          <resetValue>0x3FC80145</resetValue>
18416          <resetMask>0x3FFF3FFF</resetMask>
18417          <fields>
18418            <field>
18419              <name>DATA0</name>
18420              <description>Filter taps 14 and 40 coefficient (default value 325).</description>
18421              <bitRange>[13:0]</bitRange>
18422              <access>read-write</access>
18423            </field>
18424            <field>
18425              <name>DATA1</name>
18426              <description>Filter taps 15 and 39 coefficient (default value -56).</description>
18427              <bitRange>[29:16]</bitRange>
18428              <access>read-write</access>
18429            </field>
18430          </fields>
18431        </register>
18432        <register>
18433          <name>FIR1_COEFF8</name>
18434          <description>FIR 1 coefficients 8</description>
18435          <addressOffset>0x160</addressOffset>
18436          <size>32</size>
18437          <access>read-write</access>
18438          <resetValue>0x333E3B</resetValue>
18439          <resetMask>0x3FFF3FFF</resetMask>
18440          <fields>
18441            <field>
18442              <name>DATA0</name>
18443              <description>Filter taps 16 and 38 coefficient (default value -453).</description>
18444              <bitRange>[13:0]</bitRange>
18445              <access>read-write</access>
18446            </field>
18447            <field>
18448              <name>DATA1</name>
18449              <description>Filter taps 17 and 37 coefficient (default value 51).</description>
18450              <bitRange>[29:16]</bitRange>
18451              <access>read-write</access>
18452            </field>
18453          </fields>
18454        </register>
18455        <register>
18456          <name>FIR1_COEFF9</name>
18457          <description>FIR 1 coefficients 9</description>
18458          <addressOffset>0x164</addressOffset>
18459          <size>32</size>
18460          <access>read-write</access>
18461          <resetValue>0x3FE10277</resetValue>
18462          <resetMask>0x3FFF3FFF</resetMask>
18463          <fields>
18464            <field>
18465              <name>DATA0</name>
18466              <description>Filter taps 18 and 36 coefficient (default value 631).</description>
18467              <bitRange>[13:0]</bitRange>
18468              <access>read-write</access>
18469            </field>
18470            <field>
18471              <name>DATA1</name>
18472              <description>Filter taps 19 and 35 coefficient (default value -31).</description>
18473              <bitRange>[29:16]</bitRange>
18474              <access>read-write</access>
18475            </field>
18476          </fields>
18477        </register>
18478        <register>
18479          <name>FIR1_COEFF10</name>
18480          <description>FIR 1 coefficients 10</description>
18481          <addressOffset>0x168</addressOffset>
18482          <size>32</size>
18483          <access>read-write</access>
18484          <resetValue>0x3FEB3C82</resetValue>
18485          <resetMask>0x3FFF3FFF</resetMask>
18486          <fields>
18487            <field>
18488              <name>DATA0</name>
18489              <description>Filter taps 20 and 34 coefficient (default value -894).</description>
18490              <bitRange>[13:0]</bitRange>
18491              <access>read-write</access>
18492            </field>
18493            <field>
18494              <name>DATA1</name>
18495              <description>Filter taps 21 and 33 coefficient (default value -21).</description>
18496              <bitRange>[29:16]</bitRange>
18497              <access>read-write</access>
18498            </field>
18499          </fields>
18500        </register>
18501        <register>
18502          <name>FIR1_COEFF11</name>
18503          <description>FIR 1 coefficients 11</description>
18504          <addressOffset>0x16C</addressOffset>
18505          <size>32</size>
18506          <access>read-write</access>
18507          <resetValue>0xAC052E</resetValue>
18508          <resetMask>0x3FFF3FFF</resetMask>
18509          <fields>
18510            <field>
18511              <name>DATA0</name>
18512              <description>Filter taps 22 and 32 coefficient (default value 1326).</description>
18513              <bitRange>[13:0]</bitRange>
18514              <access>read-write</access>
18515            </field>
18516            <field>
18517              <name>DATA1</name>
18518              <description>Filter taps 23 and 31 coefficient (default value 172).</description>
18519              <bitRange>[29:16]</bitRange>
18520              <access>read-write</access>
18521            </field>
18522          </fields>
18523        </register>
18524        <register>
18525          <name>FIR1_COEFF12</name>
18526          <description>FIR 1 coefficients 12</description>
18527          <addressOffset>0x170</addressOffset>
18528          <size>32</size>
18529          <access>read-write</access>
18530          <resetValue>0x3CFE3771</resetValue>
18531          <resetMask>0x3FFF3FFF</resetMask>
18532          <fields>
18533            <field>
18534              <name>DATA0</name>
18535              <description>Filter taps 24 and 30 coefficient (default value -2191).</description>
18536              <bitRange>[13:0]</bitRange>
18537              <access>read-write</access>
18538            </field>
18539            <field>
18540              <name>DATA1</name>
18541              <description>Filter taps 25 and 29 coefficient (default value -770).</description>
18542              <bitRange>[29:16]</bitRange>
18543              <access>read-write</access>
18544            </field>
18545          </fields>
18546        </register>
18547        <register>
18548          <name>FIR1_COEFF13</name>
18549          <description>FIR 1 coefficients 13</description>
18550          <addressOffset>0x174</addressOffset>
18551          <size>32</size>
18552          <access>read-write</access>
18553          <resetValue>0x1FFF12FB</resetValue>
18554          <resetMask>0x3FFF3FFF</resetMask>
18555          <fields>
18556            <field>
18557              <name>DATA0</name>
18558              <description>Filter taps 26 and 28 coefficient (default value 4859).</description>
18559              <bitRange>[13:0]</bitRange>
18560              <access>read-write</access>
18561            </field>
18562            <field>
18563              <name>DATA1</name>
18564              <description>Filter taps 27 (center tap) coefficient (default value 8191).</description>
18565              <bitRange>[29:16]</bitRange>
18566              <access>read-write</access>
18567            </field>
18568          </fields>
18569        </register>
18570        <cluster>
18571          <dim>2</dim>
18572          <dimIncrement>256</dimIncrement>
18573          <name>CH[%s]</name>
18574          <description>PDM RX structure</description>
18575          <addressOffset>0x00008000</addressOffset>
18576          <register>
18577            <name>CTL</name>
18578            <description>Control</description>
18579            <addressOffset>0x0</addressOffset>
18580            <size>32</size>
18581            <access>read-write</access>
18582            <resetValue>0x100</resetValue>
18583            <resetMask>0x8000010F</resetMask>
18584            <fields>
18585              <field>
18586                <name>WORD_SIZE</name>
18587                <description>PCM word size:
18588'0': 8 bit.
18589'1': 10 bit.
18590'2': 12 bit.
18591'3': 14 bit.
18592'4': 16 bit.
18593'5': 18 bit.
18594'6': 20 bit.
18595'7': 24 bit.
18596'8': 32 bit.
18597'9'-'15': Undefined.</description>
18598                <bitRange>[3:0]</bitRange>
18599                <access>read-write</access>
18600                <enumeratedValues>
18601                  <enumeratedValue>
18602                    <name>SIZE_8</name>
18603                    <description>N/A</description>
18604                    <value>0</value>
18605                  </enumeratedValue>
18606                  <enumeratedValue>
18607                    <name>SIZE_10</name>
18608                    <description>N/A</description>
18609                    <value>1</value>
18610                  </enumeratedValue>
18611                  <enumeratedValue>
18612                    <name>SIZE_12</name>
18613                    <description>N/A</description>
18614                    <value>2</value>
18615                  </enumeratedValue>
18616                  <enumeratedValue>
18617                    <name>SIZE_14</name>
18618                    <description>N/A</description>
18619                    <value>3</value>
18620                  </enumeratedValue>
18621                  <enumeratedValue>
18622                    <name>SIZE_16</name>
18623                    <description>N/A</description>
18624                    <value>4</value>
18625                  </enumeratedValue>
18626                  <enumeratedValue>
18627                    <name>SIZE_18</name>
18628                    <description>N/A</description>
18629                    <value>5</value>
18630                  </enumeratedValue>
18631                  <enumeratedValue>
18632                    <name>SIZE_20</name>
18633                    <description>N/A</description>
18634                    <value>6</value>
18635                  </enumeratedValue>
18636                  <enumeratedValue>
18637                    <name>SIZE_24</name>
18638                    <description>N/A</description>
18639                    <value>7</value>
18640                  </enumeratedValue>
18641                  <enumeratedValue>
18642                    <name>SIZE_32</name>
18643                    <description>N/A</description>
18644                    <value>8</value>
18645                  </enumeratedValue>
18646                </enumeratedValues>
18647              </field>
18648              <field>
18649                <name>WORD_SIGN_EXTEND</name>
18650                <description>Word extension:
18651'0': zero extension.
18652'1': sign extension.</description>
18653                <bitRange>[8:8]</bitRange>
18654                <access>read-write</access>
18655                <enumeratedValues>
18656                  <enumeratedValue>
18657                    <name>ZERO_EXTEND</name>
18658                    <description>N/A</description>
18659                    <value>0</value>
18660                  </enumeratedValue>
18661                  <enumeratedValue>
18662                    <name>SIGN_EXTEND</name>
18663                    <description>N/A</description>
18664                    <value>1</value>
18665                  </enumeratedValue>
18666                </enumeratedValues>
18667              </field>
18668              <field>
18669                <name>ENABLED</name>
18670                <description>Receiver enable:
18671'0': Disabled. If a receiver is disabled, all non-retained MMIO registers (e.g. the RX_FIFO_STATUS and INTR_RX registers) have their fields reset to their default value.
18672
18673'1': Enabled.
18674
18675Note: when all receivers are disabled, the SRAMs are driven into low power mode, if supported by the SRAM. When exiting such low power mode software needs to allow for a certain power up time before SRAM can be used, i.e. before ACTIVE can be asserted. The power up time is equivalent to the system SRAM power up time specified in the CPUSS.RAM_PWR_DELAY_CTL register (or equivalent for platforms other than MXS40).</description>
18676                <bitRange>[31:31]</bitRange>
18677                <access>read-write</access>
18678              </field>
18679            </fields>
18680          </register>
18681          <register>
18682            <name>IF_CTL</name>
18683            <description>Interface control</description>
18684            <addressOffset>0x10</addressOffset>
18685            <size>32</size>
18686            <access>read-write</access>
18687            <resetValue>0x3</resetValue>
18688            <resetMask>0xFF</resetMask>
18689            <fields>
18690              <field>
18691                <name>SAMPLE_DELAY</name>
18692                <description>Interface sample delay. This field specifies when a PDM value is captured, expressed in clk_if clock cycles.
18693
18694When CLOCK_CTL.HALVE=0:
18695'0': Capture PDM value 1 clk_if cycle after the rising edge of clk_pdm.
18696'1': Capture PDM value 2 clk_if cycles after the rising edge of clk_pdm.
18697...
18698'255': Capture PDM value 256 clk_if cycles after the rising edge of clk_pdm.
18699
18700When CLOCK_CTL.HALVE=1:
18701'0': Capture PDM value 1 and 2 clk_if cycles after the rising edge of clk_pdm.
18702'1': Capture PDM value 3 and 4 clk_if cycles after the rising edge of clk_pdm.
18703...
18704'255': Capture PDM value 511 and 512 clk_if cycles after the rising edge of clk_pdm.
18705
18706SAMPLE_DELAY should be set such that the clk_if capture edge is at the middle point between pdm_clk_out edges. Under ideal conditions the middle point is 1/4 of the PDM interface period for the first/even/left channel, and 3/4 of the PDM interface period for the second/odd/right channel, which corresponds to the following programmings:
18707
18708SAMPLE_DELAY(left)=((CLOCK_DIV+1)/4) - 1
18709SAMPLE_DELAY(right)=(3*(CLOCK_DIV+1)/4) - 1
18710
18711In practice, due to the roundtrip delay, SAMPLE_DELAY may be set to a later point with respect to the ideal middle point.
18712
18713Note: in all cases a SAMPLE_DELAY value that brings the capture edge close to the pdm_clk_out edges should be avoided.</description>
18714                <bitRange>[7:0]</bitRange>
18715                <access>read-write</access>
18716              </field>
18717            </fields>
18718          </register>
18719          <register>
18720            <name>CIC_CTL</name>
18721            <description>CIC control</description>
18722            <addressOffset>0x14</addressOffset>
18723            <size>32</size>
18724            <access>read-write</access>
18725            <resetValue>0x4</resetValue>
18726            <resetMask>0x7</resetMask>
18727            <fields>
18728              <field>
18729                <name>DECIM_CODE</name>
18730                <description>CIC filter decimation. The CIC filter PCM frequency is a fraction of the PDM frequency:
18731'0': CIC filter PCM frequency is 1/2 * PDM frequency. CIC PCM values are in the range [-0x10, 0x10].
18732'1': CIC filter PCM frequency is 1/4 * PDM frequency. CIC PCM values are in the range [-0x200, 0x200].
18733'2': CIC filter PCM frequency is 1/8 * PDM frequency. CIC PCM values are in the range [-0x4000, 0x4000].
18734'3': CIC filter PCM frequency is 1/16 * PDM frequency. CIC PCM values are in the range [-0x8:0000, 0x8:0000].
18735'4': CIC filter PCM frequency is 1/32 * PDM frequency. CIC PCM values are in the range [-0x100:0000, 0x100:0000].
18736'5'-'7': Illegal values.
18737
18738Note: The CIC filter functionality includes offsetting logic to ensure that 'digital silence' on the PDM interface (an alternating pattern of '0', '1', '0', '1' ... PDM  values) results in CIC filter PCM values of '0'. Similarly, a pattern of '0', '0', '0', ... PDM values results in minimum CIC PCM value (-0x100:0000 when DECIMATION is '4') and a pattern of '1', '1', '1', ... PDM values results in maximum CIC PCM value (0x100:0000 when DECIMATION is '4').
18739
18740Note: The IP's desired 'clk_sys' frequency is a function of the PDM interface clock, the CIC filter decimation (CIC_CTL.DECIM_CODE[]) and the FIR filter decimation (FIR_CTL.DECIM_CODE[]).</description>
18741                <bitRange>[2:0]</bitRange>
18742                <access>read-write</access>
18743                <enumeratedValues>
18744                  <enumeratedValue>
18745                    <name>DECIM_2</name>
18746                    <description>N/A</description>
18747                    <value>0</value>
18748                  </enumeratedValue>
18749                  <enumeratedValue>
18750                    <name>DECIM_4</name>
18751                    <description>N/A</description>
18752                    <value>1</value>
18753                  </enumeratedValue>
18754                  <enumeratedValue>
18755                    <name>DECIM_8</name>
18756                    <description>N/A</description>
18757                    <value>2</value>
18758                  </enumeratedValue>
18759                  <enumeratedValue>
18760                    <name>DECIM_16</name>
18761                    <description>N/A</description>
18762                    <value>3</value>
18763                  </enumeratedValue>
18764                  <enumeratedValue>
18765                    <name>DECIM_32</name>
18766                    <description>This is the default value and the most realistic value (together with the value '3'). Typically, an overall decimation (or oversample rate (OSR)) of 64 is used, and this is achieved with the default CIC and FIR decimation values.</description>
18767                    <value>4</value>
18768                  </enumeratedValue>
18769                </enumeratedValues>
18770              </field>
18771            </fields>
18772          </register>
18773          <register>
18774            <name>FIR0_CTL</name>
18775            <description>FIR 0 control</description>
18776            <addressOffset>0x18</addressOffset>
18777            <size>32</size>
18778            <access>read-write</access>
18779            <resetValue>0x0</resetValue>
18780            <resetMask>0x80001F07</resetMask>
18781            <fields>
18782              <field>
18783                <name>DECIM3</name>
18784                <description>FIR filter decimation. The FIR filter PCM frequency is a fraction of the CIC filter PCM frequency:
18785'0': FIR 0 filter PCM frequency is 1 * CIC filter PCM frequency. The FIR 0 filter is performed for every CIC filter PCM sample.
18786'1': FIR 0 filter PCM frequency is 1/2 * CIC filter PCM frequency. The FIR 0 filter is performed for every second CIC filter PCM sample.
18787'2': FIR 0 filter PCM frequency is 1/3 * CIC filter PCM frequency. The FIR 0 filter is performed for every third CIC filter PCM sample.
18788'3': FIR 0 filter PCM frequency is 1/4 * CIC filter PCM frequency. The FIR 0 filter is performed for every fourth CIC filter PCM sample.
18789'4': FIR 0 filter PCM frequency is 1/5 * CIC filter PCM frequency. The FIR 0 filter is performed for every fifth CIC filter PCM sample.</description>
18790                <bitRange>[2:0]</bitRange>
18791                <access>read-write</access>
18792                <enumeratedValues>
18793                  <enumeratedValue>
18794                    <name>DECIM_1</name>
18795                    <description>N/A</description>
18796                    <value>0</value>
18797                  </enumeratedValue>
18798                  <enumeratedValue>
18799                    <name>DECIM_2</name>
18800                    <description>N/A</description>
18801                    <value>1</value>
18802                  </enumeratedValue>
18803                  <enumeratedValue>
18804                    <name>DECIM_3</name>
18805                    <description>N/A</description>
18806                    <value>2</value>
18807                  </enumeratedValue>
18808                  <enumeratedValue>
18809                    <name>DECIM_4</name>
18810                    <description>N/A</description>
18811                    <value>3</value>
18812                  </enumeratedValue>
18813                  <enumeratedValue>
18814                    <name>DECIM_5</name>
18815                    <description>N/A</description>
18816                    <value>4</value>
18817                  </enumeratedValue>
18818                </enumeratedValues>
18819              </field>
18820              <field>
18821                <name>SCALE</name>
18822                <description>FIR 0 filter PCM scaling. FIR 0 filter PCM values (fir0_pcm[44:0]) are scaled (right shifted, rounded and clipped) to 26-bit signed PCM values (fir0_scaled_pcm[25:0]). These 26-bit PCM values are input to the FIR 1 filter. SCALE specifies the right shift amount (and performs a rounding):
18823'0': fir0_scaled_pcm = CLIP26 (fir0_pcm[44:0]).
18824'1': fir0_scaled_pcm = CLIP26 (fir0_pcm[44:1] + fir0_pcm[0]).
18825...
18826'31': fir0_scaled_pcm = CLIP26 (fir0_pcm[44:31] + fir0_pcm[30]).
18827
18828With CLIP26(a) defined as:
18829   if      (a &gt;= 0x1ff:ffff) result =  0x1ff:ffff;
18830   else if (a &lt; -0x200:0000) result = -0x200:0000;
18831   else                      result = a;
18832
18833Note: Clipping is not necessary for larger SCALE values, as the scaled value is guarneteed to be within the 26-bit signed integer range.</description>
18834                <bitRange>[12:8]</bitRange>
18835                <access>read-write</access>
18836                <enumeratedValues>
18837                  <enumeratedValue>
18838                    <name>SCALE_0</name>
18839                    <description>N/A</description>
18840                    <value>0</value>
18841                  </enumeratedValue>
18842                  <enumeratedValue>
18843                    <name>SCALE_1</name>
18844                    <description>N/A</description>
18845                    <value>1</value>
18846                  </enumeratedValue>
18847                  <enumeratedValue>
18848                    <name>SCALE_31</name>
18849                    <description>N/A</description>
18850                    <value>31</value>
18851                  </enumeratedValue>
18852                </enumeratedValues>
18853              </field>
18854              <field>
18855                <name>ENABLED</name>
18856                <description>FIR 0 filter coefficient enable (does NOT effect FIR filter scaling and FIR filter decimation):
18857'0': Disabled. The middle FIR filter coefficient (16th coefficient, or tap 15 in [0:29] range) is '1' and all other FIR filter coefficients are '0'; i.e. the FIR filter is a pass through filter and the filter gain is '1'.
18858   fir0_pcm[44:0] = cic_pcm[25:0] (with sign extension)
18859'1': Enabled.
18860
18861Note: This filter is disabled by default, and typically only used for sample frequencies (Fs) of 8 and 16 kHz.</description>
18862                <bitRange>[31:31]</bitRange>
18863                <access>read-write</access>
18864              </field>
18865            </fields>
18866          </register>
18867          <register>
18868            <name>FIR1_CTL</name>
18869            <description>FIR 1 control</description>
18870            <addressOffset>0x1C</addressOffset>
18871            <size>32</size>
18872            <access>read-write</access>
18873            <resetValue>0x80000F01</resetValue>
18874            <resetMask>0x80001F03</resetMask>
18875            <fields>
18876              <field>
18877                <name>DECIM2</name>
18878                <description>FIR 1 filter decimation. The FIR filter PCM frequency is a fraction of the CIC filter PCM frequency:
18879'0': FIR 1 filter PCM frequency is 1 * FIR 0 filter PCM frequency. The FIR filter is performed for every FIR 0 filter PCM sample.
18880'1': FIR 1 filter PCM frequency is 1/2 * FIR 0 filter PCM frequency. The FIR filter is performed for every second FIR 0 filter PCM sample.
18881'2': FIR 1 filter PCM frequency is 1/3 * FIR 0 filter PCM frequency. The FIR filter is performed for every third FIR 0 filter PCM sample.
18882'3': FIR 1 filter PCM frequency is 1/4 * FIR 0 filter PCM frequency. The FIR filter is performed for every fourth FIR 0 filter PCM sample.</description>
18883                <bitRange>[1:0]</bitRange>
18884                <access>read-write</access>
18885                <enumeratedValues>
18886                  <enumeratedValue>
18887                    <name>DECIM_1</name>
18888                    <description>N/A</description>
18889                    <value>0</value>
18890                  </enumeratedValue>
18891                  <enumeratedValue>
18892                    <name>DECIM_2</name>
18893                    <description>N/A</description>
18894                    <value>1</value>
18895                  </enumeratedValue>
18896                  <enumeratedValue>
18897                    <name>DECIM_3</name>
18898                    <description>N/A</description>
18899                    <value>2</value>
18900                  </enumeratedValue>
18901                  <enumeratedValue>
18902                    <name>DECIM_4</name>
18903                    <description>N/A</description>
18904                    <value>3</value>
18905                  </enumeratedValue>
18906                </enumeratedValues>
18907              </field>
18908              <field>
18909                <name>SCALE</name>
18910                <description>FIR 1 filter PCM scaling. FIR filter PCM values (fir1_pcm[43:0]) are scaled (right shifted, rounded and clipped) to 24-bit signed PCM values (fir1_scaled_pcm[23:0]). These 24-bit PCM values are input to the DC blocker. SCALE specifies the right shift amount (and performs a rounding):
18911'0': fir1_scaled_pcm = CLIP24 (fir1_pcm[43:0]).
18912'1': fir1_scaled_pcm = CLIP24 (fir1_pcm[43:1] + fir1_pcm[0]).
18913...
18914'31': fir1_scaled_pcm = CLIP24 (fir1_pcm[43:31] + fir1_pcm[30]).
18915
18916With CLIP24(a) defined as:
18917   if      (a &gt;= 0x7f:ffff) result =  0x7f:ffff;
18918   else if (a &lt; -0x80:0000) result = -0x80:0000;
18919   else                     result = a;
18920
18921Note: Clipping is not necessary for larger SCALE values, as the scaled value is guarneteed to be within the 24-bit signed integer range.</description>
18922                <bitRange>[12:8]</bitRange>
18923                <access>read-write</access>
18924                <enumeratedValues>
18925                  <enumeratedValue>
18926                    <name>SCALE_0</name>
18927                    <description>N/A</description>
18928                    <value>0</value>
18929                  </enumeratedValue>
18930                  <enumeratedValue>
18931                    <name>SCALE_1</name>
18932                    <description>N/A</description>
18933                    <value>1</value>
18934                  </enumeratedValue>
18935                  <enumeratedValue>
18936                    <name>SCALE_31</name>
18937                    <description>N/A</description>
18938                    <value>31</value>
18939                  </enumeratedValue>
18940                </enumeratedValues>
18941              </field>
18942              <field>
18943                <name>ENABLED</name>
18944                <description>FIR 1 filter coefficient enable (does NOT effect FIR filter scaling and FIR filter decimation):
18945'0': Disabled. The middle FIR filter coefficient (28th coefficient, or tap 27 in [0:54] range) is '1' and all other FIR filter coefficients are '0'; i.e. the FIR filter is a pass through filter and the filter gain is '1'.
18946   fir1_pcm[43:0] = fir0_scaled_pcm[25:0] (with sign extension)
18947'1': Enabled.
18948
18949Note: Disabling of the filter functionality is provided for debug purposes.</description>
18950                <bitRange>[31:31]</bitRange>
18951                <access>read-write</access>
18952              </field>
18953            </fields>
18954          </register>
18955          <register>
18956            <name>DC_BLOCK_CTL</name>
18957            <description>DC block control</description>
18958            <addressOffset>0x20</addressOffset>
18959            <size>32</size>
18960            <access>read-write</access>
18961            <resetValue>0x80000001</resetValue>
18962            <resetMask>0x80000007</resetMask>
18963            <fields>
18964              <field>
18965                <name>CODE</name>
18966                <description>DC blocker coefficient. The DC blocker is defined as:
18967
18968dc_block_state_scaled(n-1) =
18969       dc_block_state(n-1)
18970     - (dc_block_state(n-1) &gt;&gt; (12-CODE))
18971dc_block_state(n)          = CLIP37 (
18972       2^13 * (fir1_scaled_pcm(n) - fir1_scaled_pcm(n-1))
18973     + dc_block_state_scaled(n-1))
18974dc_block_pcm(n)            = dc_block_state(n) &gt;&gt; 13
18975
18976This first step is a scaling step of the DC block state. It effectively multiplies the DC block state with a variable 'alpha' that is close to '1':
18977'0': alpha = 1 - (1/2^(12-0)) = 0.999755859.
18978'1': alpha = 1 - (1/2^(12-1)) = 0.999511719.
18979'2': alpha = 1 - (1/2^(12-2)) = 0.999023438.
18980'3': alpha = 1 - (1/2^(12-3)) = 0.998046875.
18981'4': alpha = 1 - (1/2^(12-4)) = 0.99609375.
18982'5': alpha = 1 - (1/2^(12-5)) = 0.9921875.
18983'6': alpha = 1 - (1/2^(12-6)) = 0.984375.
18984'7': alpha = 1 - (1/2^(12-7)) = 0.96875.</description>
18985                <bitRange>[2:0]</bitRange>
18986                <access>read-write</access>
18987                <enumeratedValues>
18988                  <enumeratedValue>
18989                    <name>CODE_1</name>
18990                    <description>N/A</description>
18991                    <value>0</value>
18992                  </enumeratedValue>
18993                  <enumeratedValue>
18994                    <name>CODE_2</name>
18995                    <description>N/A</description>
18996                    <value>1</value>
18997                  </enumeratedValue>
18998                  <enumeratedValue>
18999                    <name>CODE_4</name>
19000                    <description>N/A</description>
19001                    <value>2</value>
19002                  </enumeratedValue>
19003                  <enumeratedValue>
19004                    <name>CODE_8</name>
19005                    <description>N/A</description>
19006                    <value>3</value>
19007                  </enumeratedValue>
19008                  <enumeratedValue>
19009                    <name>CODE_16</name>
19010                    <description>N/A</description>
19011                    <value>4</value>
19012                  </enumeratedValue>
19013                  <enumeratedValue>
19014                    <name>CODE_32</name>
19015                    <description>N/A</description>
19016                    <value>5</value>
19017                  </enumeratedValue>
19018                  <enumeratedValue>
19019                    <name>CODE_64</name>
19020                    <description>N/A</description>
19021                    <value>6</value>
19022                  </enumeratedValue>
19023                  <enumeratedValue>
19024                    <name>CODE_128</name>
19025                    <description>N/A</description>
19026                    <value>7</value>
19027                  </enumeratedValue>
19028                </enumeratedValues>
19029              </field>
19030              <field>
19031                <name>ENABLED</name>
19032                <description>DC blocker enable:
19033'0': Disabled. The functionality is defined as:
19034dc_block_pcm(n) = fir1_scaled_pcm(n)
19035'1': Enabled. The functionality is as specified by the CODE field.
19036
19037Note: disabling of the DC blocker filter functionality is provided for debug purposes.</description>
19038                <bitRange>[31:31]</bitRange>
19039                <access>read-write</access>
19040              </field>
19041            </fields>
19042          </register>
19043          <register>
19044            <name>RX_FIFO_CTL</name>
19045            <description>RX FIFO control</description>
19046            <addressOffset>0x80</addressOffset>
19047            <size>32</size>
19048            <access>read-write</access>
19049            <resetValue>0x0</resetValue>
19050            <resetMask>0x2003F</resetMask>
19051            <fields>
19052              <field>
19053                <name>TRIGGER_LEVEL</name>
19054                <description>Trigger level. When the RX FIFO has more entries than the number of this field, a receiver trigger event is generated:
19055- INTR_RX.FIFO_TRIGGER = (# FIFO entries &gt; TRIGGER_LEVEL)</description>
19056                <bitRange>[5:0]</bitRange>
19057                <access>read-write</access>
19058                <enumeratedValues>
19059                  <enumeratedValue>
19060                    <name>EMPTY</name>
19061                    <description>N/A</description>
19062                    <value>0</value>
19063                  </enumeratedValue>
19064                  <enumeratedValue>
19065                    <name>USED_1</name>
19066                    <description>N/A</description>
19067                    <value>1</value>
19068                  </enumeratedValue>
19069                  <enumeratedValue>
19070                    <name>USED_63</name>
19071                    <description>N/A</description>
19072                    <value>63</value>
19073                  </enumeratedValue>
19074                </enumeratedValues>
19075              </field>
19076              <field>
19077                <name>FREEZE</name>
19078                <description>Freeze functionality:
19079'0': HW writes to the RX FIFO and advances the FIFO write pointer.
19080'1': HW writes from the RX FIFO have no effect: freeze will not advance the FIFO write pointer.
19081
19082Note: This functionality is intended for debugging purposes.</description>
19083                <bitRange>[17:17]</bitRange>
19084                <access>read-write</access>
19085              </field>
19086            </fields>
19087          </register>
19088          <register>
19089            <name>RX_FIFO_STATUS</name>
19090            <description>RX FIFO status</description>
19091            <addressOffset>0x84</addressOffset>
19092            <size>32</size>
19093            <access>read-only</access>
19094            <resetValue>0x0</resetValue>
19095            <resetMask>0x3F3F007F</resetMask>
19096            <fields>
19097              <field>
19098                <name>USED</name>
19099                <description>Number of used/occupied entries in the RX FIFO. The field value is in the range [0, 64]. When '0', the FIFO is empty. When '64', the FIFO is full.</description>
19100                <bitRange>[6:0]</bitRange>
19101                <access>read-only</access>
19102              </field>
19103              <field>
19104                <name>RD_PTR</name>
19105                <description>RX FIFO read pointer: FIFO location from which a data is read.
19106
19107Note: This functionality is intended for debugging purposes.</description>
19108                <bitRange>[21:16]</bitRange>
19109                <access>read-only</access>
19110              </field>
19111              <field>
19112                <name>WR_PTR</name>
19113                <description>RX FIFO write pointer: FIFO location at which a new data is written by the hardware.
19114
19115Note: This functionality is intended for debugging purposes.</description>
19116                <bitRange>[29:24]</bitRange>
19117                <access>read-only</access>
19118              </field>
19119            </fields>
19120          </register>
19121          <register>
19122            <name>RX_FIFO_RD</name>
19123            <description>RX FIFO read</description>
19124            <addressOffset>0x88</addressOffset>
19125            <size>32</size>
19126            <access>read-only</access>
19127            <resetValue>0x0</resetValue>
19128            <resetMask>0xFFFFFFFF</resetMask>
19129            <fields>
19130              <field>
19131                <name>DATA</name>
19132                <description>Data (PCM sample) read from the RX FIFO. Reading removes the data from the RX FIFO; i.e. behavior is similar to that of a POP operation (RX_FIFO_STATUS.RD_PTR is incremented and RX_FIFO_STATUS.USED is decremented). The read data (DATA) is right aligned (unused bit positions follow the specified sign extension per CTL.WORD_SIGN_EXTEND) when it is read from the FIFO entry (data[23:0]):
19133- 8 bit, DATA[7:0] = data[23:16].
19134- 10 bit, DATA[9:0] = data[23:14].
19135- 12 bit, DATA[11:0] = data[23:12].
19136- 14 bit, DATA[13:0] = data[23:10].
19137- 16 bit, DATA[15:0] = data[23:8].
19138- 18 bit, DATA[17:0] = data[23:6].
19139- 20 bit, DATA[19:0] = data[23:4].
19140- 24 bit, DATA[23:0] = data[23:0].
19141- 32 bit, DATA[31:0] = data[23:0] &lt;&lt; 8.
19142
19143Note: Reading from an empty RX FIFO activates INTR_RX.FIFO_UNDERFLOW.</description>
19144                <bitRange>[31:0]</bitRange>
19145                <access>read-only</access>
19146              </field>
19147            </fields>
19148          </register>
19149          <register>
19150            <name>RX_FIFO_RD_SILENT</name>
19151            <description>RX FIFO silent read</description>
19152            <addressOffset>0x8C</addressOffset>
19153            <size>32</size>
19154            <access>read-only</access>
19155            <resetValue>0x0</resetValue>
19156            <resetMask>0xFFFFFFFF</resetMask>
19157            <fields>
19158              <field>
19159                <name>DATA</name>
19160                <description>Data (PCM sample) read from the RX FIFO. Reading will NOT remove the data  from the RX FIFO; i.e. behavior is similar to that of a PEEK operation. See RX_FIFO_RD for data alignment.
19161
19162Note: Reading from an empty RX FIFO activates INTR.RX_FIFO_UNDERFLOW (the read returns 0xffff:ffff).
19163
19164Note: This functionality is intended for debugging purposes.</description>
19165                <bitRange>[31:0]</bitRange>
19166                <access>read-only</access>
19167              </field>
19168            </fields>
19169          </register>
19170          <register>
19171            <name>INTR_RX</name>
19172            <description>Interrupt</description>
19173            <addressOffset>0xC0</addressOffset>
19174            <size>32</size>
19175            <access>read-write</access>
19176            <resetValue>0x0</resetValue>
19177            <resetMask>0x117</resetMask>
19178            <fields>
19179              <field>
19180                <name>FIFO_TRIGGER</name>
19181                <description>HW sets this field to '1', when a RX trigger is generated.</description>
19182                <bitRange>[0:0]</bitRange>
19183                <access>read-write</access>
19184              </field>
19185              <field>
19186                <name>FIFO_OVERFLOW</name>
19187                <description>HW sets this field to '1', when writing to a full RX FIFO (RX_FIFO_STATUS.USED is '64').</description>
19188                <bitRange>[1:1]</bitRange>
19189                <access>read-write</access>
19190              </field>
19191              <field>
19192                <name>FIFO_UNDERFLOW</name>
19193                <description>HW sets this field to '1', when reading from an empty RX FIFO (RX_FIFO_STATUS.USED is '0').</description>
19194                <bitRange>[2:2]</bitRange>
19195                <access>read-write</access>
19196              </field>
19197              <field>
19198                <name>FIR_OVERFLOW</name>
19199                <description>HW sets this field to '1', when CIC filter PCM samples are produced at a faster rate than the FIR filter can process them. This is an indication that the IP system frequency is too low.
19200
19201Note: This functionality is intended for debugging purposes.</description>
19202                <bitRange>[4:4]</bitRange>
19203                <access>read-write</access>
19204              </field>
19205              <field>
19206                <name>IF_OVERFLOW</name>
19207                <description>HW sets this field to '1', when PDM samples are generated too fast by the interface logic (interface overflow). This may be an indication that the IP system frequency is too low wrt. the interface frequency (a SW configuration error). The interface overflow is a non-recoverable error and requires SW disabling (CTL.ENABLED) of the receiver clearing INTR_RX.IF_OVERFLOW to '0' does not resolve the interface underflow).
19208
19209Note: This functionality is intended for debug purposes.</description>
19210                <bitRange>[8:8]</bitRange>
19211                <access>read-write</access>
19212              </field>
19213            </fields>
19214          </register>
19215          <register>
19216            <name>INTR_RX_SET</name>
19217            <description>Interrupt set</description>
19218            <addressOffset>0xC4</addressOffset>
19219            <size>32</size>
19220            <access>read-write</access>
19221            <resetValue>0x0</resetValue>
19222            <resetMask>0x117</resetMask>
19223            <fields>
19224              <field>
19225                <name>FIFO_TRIGGER</name>
19226                <description>Write this field with '1' to set corresponding INTR_RX field (a write of '0' has no effect).</description>
19227                <bitRange>[0:0]</bitRange>
19228                <access>read-write</access>
19229              </field>
19230              <field>
19231                <name>FIFO_OVERFLOW</name>
19232                <description>Write this field with '1' to set corresponding INTR_RX field (a write of '0' has no effect).</description>
19233                <bitRange>[1:1]</bitRange>
19234                <access>read-write</access>
19235              </field>
19236              <field>
19237                <name>FIFO_UNDERFLOW</name>
19238                <description>Write this field with '1' to set corresponding INTR_RX field (a write of '0' has no effect).</description>
19239                <bitRange>[2:2]</bitRange>
19240                <access>read-write</access>
19241              </field>
19242              <field>
19243                <name>FIR_OVERFLOW</name>
19244                <description>Write this field with '1' to set corresponding INTR_RX field (a write of '0' has no effect).</description>
19245                <bitRange>[4:4]</bitRange>
19246                <access>read-write</access>
19247              </field>
19248              <field>
19249                <name>IF_OVERFLOW</name>
19250                <description>Write this field with '1' to set corresponding INTR_RX field (a write of '0' has no effect).</description>
19251                <bitRange>[8:8]</bitRange>
19252                <access>read-write</access>
19253              </field>
19254            </fields>
19255          </register>
19256          <register>
19257            <name>INTR_RX_MASK</name>
19258            <description>Interrupt mask</description>
19259            <addressOffset>0xC8</addressOffset>
19260            <size>32</size>
19261            <access>read-write</access>
19262            <resetValue>0x0</resetValue>
19263            <resetMask>0x117</resetMask>
19264            <fields>
19265              <field>
19266                <name>FIFO_TRIGGER</name>
19267                <description>Mask for corresponding field in INTR_RX register.</description>
19268                <bitRange>[0:0]</bitRange>
19269                <access>read-write</access>
19270              </field>
19271              <field>
19272                <name>FIFO_OVERFLOW</name>
19273                <description>Mask for corresponding field in INTR_RX register.</description>
19274                <bitRange>[1:1]</bitRange>
19275                <access>read-write</access>
19276              </field>
19277              <field>
19278                <name>FIFO_UNDERFLOW</name>
19279                <description>Mask for corresponding field in INTR_RX register.</description>
19280                <bitRange>[2:2]</bitRange>
19281                <access>read-write</access>
19282              </field>
19283              <field>
19284                <name>FIR_OVERFLOW</name>
19285                <description>Mask for corresponding field in INTR_RX register.</description>
19286                <bitRange>[4:4]</bitRange>
19287                <access>read-write</access>
19288              </field>
19289              <field>
19290                <name>IF_OVERFLOW</name>
19291                <description>Mask for corresponding field in INTR_RX register.</description>
19292                <bitRange>[8:8]</bitRange>
19293                <access>read-write</access>
19294              </field>
19295            </fields>
19296          </register>
19297          <register>
19298            <name>INTR_RX_MASKED</name>
19299            <description>Interrupt masked</description>
19300            <addressOffset>0xCC</addressOffset>
19301            <size>32</size>
19302            <access>read-only</access>
19303            <resetValue>0x0</resetValue>
19304            <resetMask>0x117</resetMask>
19305            <fields>
19306              <field>
19307                <name>FIFO_TRIGGER</name>
19308                <description>Logical AND of corresponding INTR_RX and INTR_RX_MASK fields.</description>
19309                <bitRange>[0:0]</bitRange>
19310                <access>read-only</access>
19311              </field>
19312              <field>
19313                <name>FIFO_OVERFLOW</name>
19314                <description>Logical AND of corresponding INTR_RX and INTR_RX_MASK fields.</description>
19315                <bitRange>[1:1]</bitRange>
19316                <access>read-only</access>
19317              </field>
19318              <field>
19319                <name>FIFO_UNDERFLOW</name>
19320                <description>Logical AND of corresponding INTR_RX and INTR_RX_MASK fields.</description>
19321                <bitRange>[2:2]</bitRange>
19322                <access>read-only</access>
19323              </field>
19324              <field>
19325                <name>FIR_OVERFLOW</name>
19326                <description>Logical AND of corresponding INTR_RX and INTR_RX_MASK fields.</description>
19327                <bitRange>[4:4]</bitRange>
19328                <access>read-only</access>
19329              </field>
19330              <field>
19331                <name>IF_OVERFLOW</name>
19332                <description>Logical AND of corresponding INTR_RX and INTR_RX_MASK fields.</description>
19333                <bitRange>[8:8]</bitRange>
19334                <access>read-only</access>
19335              </field>
19336            </fields>
19337          </register>
19338        </cluster>
19339      </registers>
19340    </peripheral>
19341    <peripheral>
19342      <name>TCPWM0</name>
19343      <description>Timer/Counter/PWM</description>
19344      <headerStructName>TCPWM</headerStructName>
19345      <baseAddress>0x40400000</baseAddress>
19346      <addressBlock>
19347        <offset>0</offset>
19348        <size>65536</size>
19349        <usage>registers</usage>
19350      </addressBlock>
19351      <registers>
19352        <register>
19353          <name>CTRL</name>
19354          <description>TCPWM control register</description>
19355          <addressOffset>0x0</addressOffset>
19356          <size>32</size>
19357          <access>read-write</access>
19358          <resetValue>0x0</resetValue>
19359          <resetMask>0xFFFFFFFF</resetMask>
19360          <fields>
19361            <field>
19362              <name>COUNTER_ENABLED</name>
19363              <description>Counter enables for counters 0 up to CNT_NR-1.
19364'0': counter disabled.
19365'1': counter enabled.
19366Counter static configuration information (e.g. CTRL.MODE, all TR_CTRL0, TR_CTRL1, and TR_CTRL2 register fields) should only be modified when the counter is disabled. When a counter is disabled, command and status information associated to the counter is cleared by HW, this includes:
19367- the associated counter triggers in the CMD register are set to '0'.
19368- the counter's interrupt cause fields in counter's INTR register.
19369- the counter's status fields in counter's STATUS register..
19370- the counter's trigger outputs ('tr_overflow', 'tr_underflow' and 'tr_compare_match').
19371- the counter's line outputs ('line_out' and 'line_compl_out').
19372In multi-core environments, use the CTRL_SET/CTRL_CLR registers to avoid race-conditions on read-modify-write attempts to this register.</description>
19373              <bitRange>[31:0]</bitRange>
19374              <access>read-write</access>
19375            </field>
19376          </fields>
19377        </register>
19378        <register>
19379          <name>CTRL_CLR</name>
19380          <description>TCPWM control clear register</description>
19381          <addressOffset>0x4</addressOffset>
19382          <size>32</size>
19383          <access>read-write</access>
19384          <resetValue>0x0</resetValue>
19385          <resetMask>0xFFFFFFFF</resetMask>
19386          <fields>
19387            <field>
19388              <name>COUNTER_ENABLED</name>
19389              <description>Alias of CTRL that only allows disabling of counters. A write access:
19390'0': Does nothing.
19391'1': Clears respective COUNTER_ENABLED field.
19392
19393A read access returns CTRL.COUNTER_ENABLED.</description>
19394              <bitRange>[31:0]</bitRange>
19395              <access>read-write</access>
19396            </field>
19397          </fields>
19398        </register>
19399        <register>
19400          <name>CTRL_SET</name>
19401          <description>TCPWM control set register</description>
19402          <addressOffset>0x8</addressOffset>
19403          <size>32</size>
19404          <access>read-write</access>
19405          <resetValue>0x0</resetValue>
19406          <resetMask>0xFFFFFFFF</resetMask>
19407          <fields>
19408            <field>
19409              <name>COUNTER_ENABLED</name>
19410              <description>Alias of CTRL that only allows enabling of counters. A write access:
19411'0': Does nothing.
19412'1': Sets respective COUNTER_ENABLED field.
19413
19414A read access returns CTRL.COUNTER_ENABLED.</description>
19415              <bitRange>[31:0]</bitRange>
19416              <access>read-write</access>
19417            </field>
19418          </fields>
19419        </register>
19420        <register>
19421          <name>CMD_CAPTURE</name>
19422          <description>TCPWM capture command register</description>
19423          <addressOffset>0xC</addressOffset>
19424          <size>32</size>
19425          <access>read-write</access>
19426          <resetValue>0x0</resetValue>
19427          <resetMask>0xFFFFFFFF</resetMask>
19428          <fields>
19429            <field>
19430              <name>COUNTER_CAPTURE</name>
19431              <description>Counters SW capture trigger. When written with '1', a capture trigger is generated and the HW sets the field to '0' when the SW trigger has taken effect. It should be noted that the HW operates on the counter frequency. If the counter is disabled through CTRL.COUNTER_ENABLED, the field is immediately set to '0'.</description>
19432              <bitRange>[31:0]</bitRange>
19433              <access>read-write</access>
19434            </field>
19435          </fields>
19436        </register>
19437        <register>
19438          <name>CMD_RELOAD</name>
19439          <description>TCPWM reload command register</description>
19440          <addressOffset>0x10</addressOffset>
19441          <size>32</size>
19442          <access>read-write</access>
19443          <resetValue>0x0</resetValue>
19444          <resetMask>0xFFFFFFFF</resetMask>
19445          <fields>
19446            <field>
19447              <name>COUNTER_RELOAD</name>
19448              <description>Counters SW reload trigger. For HW behavior, see COUNTER_CAPTURE field.</description>
19449              <bitRange>[31:0]</bitRange>
19450              <access>read-write</access>
19451            </field>
19452          </fields>
19453        </register>
19454        <register>
19455          <name>CMD_STOP</name>
19456          <description>TCPWM stop command register</description>
19457          <addressOffset>0x14</addressOffset>
19458          <size>32</size>
19459          <access>read-write</access>
19460          <resetValue>0x0</resetValue>
19461          <resetMask>0xFFFFFFFF</resetMask>
19462          <fields>
19463            <field>
19464              <name>COUNTER_STOP</name>
19465              <description>Counters SW stop trigger. For HW behavior, see COUNTER_CAPTURE field.</description>
19466              <bitRange>[31:0]</bitRange>
19467              <access>read-write</access>
19468            </field>
19469          </fields>
19470        </register>
19471        <register>
19472          <name>CMD_START</name>
19473          <description>TCPWM start command register</description>
19474          <addressOffset>0x18</addressOffset>
19475          <size>32</size>
19476          <access>read-write</access>
19477          <resetValue>0x0</resetValue>
19478          <resetMask>0xFFFFFFFF</resetMask>
19479          <fields>
19480            <field>
19481              <name>COUNTER_START</name>
19482              <description>Counters SW start trigger. For HW behavior, see COUNTER_CAPTURE field.</description>
19483              <bitRange>[31:0]</bitRange>
19484              <access>read-write</access>
19485            </field>
19486          </fields>
19487        </register>
19488        <register>
19489          <name>INTR_CAUSE</name>
19490          <description>TCPWM Counter interrupt cause register</description>
19491          <addressOffset>0x1C</addressOffset>
19492          <size>32</size>
19493          <access>read-only</access>
19494          <resetValue>0x0</resetValue>
19495          <resetMask>0xFFFFFFFF</resetMask>
19496          <fields>
19497            <field>
19498              <name>COUNTER_INT</name>
19499              <description>Counters interrupt signal active. If the counter is disabled through CTRL.COUNTER_ENABLED, the associated interrupt field is immediately set to '0'.</description>
19500              <bitRange>[31:0]</bitRange>
19501              <access>read-only</access>
19502            </field>
19503          </fields>
19504        </register>
19505        <cluster>
19506          <dim>8</dim>
19507          <dimIncrement>64</dimIncrement>
19508          <name>CNT[%s]</name>
19509          <description>Timer/Counter/PWM Counter Module</description>
19510          <addressOffset>0x00000100</addressOffset>
19511          <register>
19512            <name>CTRL</name>
19513            <description>Counter control register</description>
19514            <addressOffset>0x0</addressOffset>
19515            <size>32</size>
19516            <access>read-write</access>
19517            <resetValue>0x0</resetValue>
19518            <resetMask>0x737FF0F</resetMask>
19519            <fields>
19520              <field>
19521                <name>AUTO_RELOAD_CC</name>
19522                <description>Specifies switching of the CC and buffered CC values. This field has a function in TIMER, PWM, PWM_DT and PWM_PR modes.
19523Timer mode:
19524'0': never switch.
19525'1': switch on a compare match event.
19526PWM, PWM_DT, PWM_PR modes:
19527'0: never switch.
19528'1': switch on a terminal count event with an actively pending switch event.</description>
19529                <bitRange>[0:0]</bitRange>
19530                <access>read-write</access>
19531              </field>
19532              <field>
19533                <name>AUTO_RELOAD_PERIOD</name>
19534                <description>Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM, PWM_DT and PWM_PR modes.
19535'0': never switch.
19536'1': switch on a terminal count event with and actively pending switch event.</description>
19537                <bitRange>[1:1]</bitRange>
19538                <access>read-write</access>
19539              </field>
19540              <field>
19541                <name>PWM_SYNC_KILL</name>
19542                <description>Specifies asynchronous/synchronous kill behavior:
19543'1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill). In synchronous kill mode, STOP_EDGE should  be RISING_EDGE.
19544'0': asynchronous kill mode: the kill event only disables the 'dt_line_out' and 'dt_line_compl_out' signals when present. In asynchronous kill mode, STOP_EDGE should be NO_EDGE_DET.
19545
19546This field has a function in PWM and PWM_DT modes only. This field is only used when PWM_STOP_ON_KILL is '0'.</description>
19547                <bitRange>[2:2]</bitRange>
19548                <access>read-write</access>
19549              </field>
19550              <field>
19551                <name>PWM_STOP_ON_KILL</name>
19552                <description>Specifies whether the counter stops on a kill events:
19553'0': kill event does NOT stop counter.
19554'1': kill event stops counter.
19555
19556This field has a function in PWM, PWM_DT and PWM_PR modes only.</description>
19557                <bitRange>[3:3]</bitRange>
19558                <access>read-write</access>
19559              </field>
19560              <field>
19561                <name>GENERIC</name>
19562                <description>Generic 8-bit control field. In PWM_DT mode, this field is used to determine the dead time: amount of dead time cycles in the counter clock domain. In all other modes, the lower 3 bits of this field determine pre-scaling of the selected counter clock.</description>
19563                <bitRange>[15:8]</bitRange>
19564                <access>read-write</access>
19565              </field>
19566              <field>
19567                <name>UP_DOWN_MODE</name>
19568                <description>Determines counter direction.</description>
19569                <bitRange>[17:16]</bitRange>
19570                <access>read-write</access>
19571                <enumeratedValues>
19572                  <enumeratedValue>
19573                    <name>COUNT_UP</name>
19574                    <description>Count up (to PERIOD). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. A terminal count event is generated when the counter changes from a state in which COUNTER equals PERIOD.</description>
19575                    <value>0</value>
19576                  </enumeratedValue>
19577                  <enumeratedValue>
19578                    <name>COUNT_DOWN</name>
19579                    <description>Count down (to '0'). An underflow event is generated when  the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'.</description>
19580                    <value>1</value>
19581                  </enumeratedValue>
19582                  <enumeratedValue>
19583                    <name>COUNT_UPDN1</name>
19584                    <description>Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'.</description>
19585                    <value>2</value>
19586                  </enumeratedValue>
19587                  <enumeratedValue>
19588                    <name>COUNT_UPDN2</name>
19589                    <description>Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0' AND when the counter changes from a state in which COUNTER equals PERIOD (this counter direction can be used for PWM functionality with asymmetrical updates).</description>
19590                    <value>3</value>
19591                  </enumeratedValue>
19592                </enumeratedValues>
19593              </field>
19594              <field>
19595                <name>ONE_SHOT</name>
19596                <description>When '0', counter runs continuous. When '1', counter is turned off by hardware when a terminal count event is generated.</description>
19597                <bitRange>[18:18]</bitRange>
19598                <access>read-write</access>
19599              </field>
19600              <field>
19601                <name>QUADRATURE_MODE</name>
19602                <description>In QUAD mode selects quadrature encoding mode (X1/X2/X4).
19603In PWM, PWM_DT and PWM_PR modes, these two bits can be used to invert 'dt_line_out' and 'dt_line_compl_out'.  Inversion is the last step in generation of 'dt_line_out' and 'dt_line_compl_out'; i.e. a disabled output line 'dt_line_out' has the value QUADRATURE_MODE[0] and a disabled output line 'dt_line_compl_out' has the value QUADRATURE_MODE[1].</description>
19604                <bitRange>[21:20]</bitRange>
19605                <access>read-write</access>
19606                <enumeratedValues>
19607                  <enumeratedValue>
19608                    <name>X1</name>
19609                    <description>X1 encoding (QUAD mode)</description>
19610                    <value>0</value>
19611                  </enumeratedValue>
19612                  <enumeratedValue>
19613                    <name>X2</name>
19614                    <description>X2 encoding (QUAD mode)</description>
19615                    <value>1</value>
19616                  </enumeratedValue>
19617                  <enumeratedValue>
19618                    <name>X4</name>
19619                    <description>X4 encoding (QUAD mode)</description>
19620                    <value>2</value>
19621                  </enumeratedValue>
19622                </enumeratedValues>
19623              </field>
19624              <field>
19625                <name>MODE</name>
19626                <description>Counter mode.</description>
19627                <bitRange>[26:24]</bitRange>
19628                <access>read-write</access>
19629                <enumeratedValues>
19630                  <enumeratedValue>
19631                    <name>TIMER</name>
19632                    <description>Timer mode</description>
19633                    <value>0</value>
19634                  </enumeratedValue>
19635                  <enumeratedValue>
19636                    <name>CAPTURE</name>
19637                    <description>Capture mode</description>
19638                    <value>2</value>
19639                  </enumeratedValue>
19640                  <enumeratedValue>
19641                    <name>QUAD</name>
19642                    <description>Quadrature encoding mode</description>
19643                    <value>3</value>
19644                  </enumeratedValue>
19645                  <enumeratedValue>
19646                    <name>PWM</name>
19647                    <description>Pulse width modulation (PWM) mode</description>
19648                    <value>4</value>
19649                  </enumeratedValue>
19650                  <enumeratedValue>
19651                    <name>PWM_DT</name>
19652                    <description>PWM with deadtime insertion mode</description>
19653                    <value>5</value>
19654                  </enumeratedValue>
19655                  <enumeratedValue>
19656                    <name>PWM_PR</name>
19657                    <description>Pseudo random pulse width modulation</description>
19658                    <value>6</value>
19659                  </enumeratedValue>
19660                </enumeratedValues>
19661              </field>
19662            </fields>
19663          </register>
19664          <register>
19665            <name>STATUS</name>
19666            <description>Counter status register</description>
19667            <addressOffset>0x4</addressOffset>
19668            <size>32</size>
19669            <access>read-only</access>
19670            <resetValue>0x0</resetValue>
19671            <resetMask>0x8000FF01</resetMask>
19672            <fields>
19673              <field>
19674                <name>DOWN</name>
19675                <description>When '0', counter is counting up. When '1', counter is counting down. In QUAD mode, this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented.</description>
19676                <bitRange>[0:0]</bitRange>
19677                <access>read-only</access>
19678              </field>
19679              <field>
19680                <name>GENERIC</name>
19681                <description>Generic 8-bit counter field. In PWM_DT mode, this counter is used for dead time insertion. In all other modes, this counter is used for pre-scaling the selected counter clock. PWM_DT mode can NOT use prescaled clock functionality.</description>
19682                <bitRange>[15:8]</bitRange>
19683                <access>read-only</access>
19684              </field>
19685              <field>
19686                <name>RUNNING</name>
19687                <description>When '0', the counter is NOT running. When '1', the counter is running.</description>
19688                <bitRange>[31:31]</bitRange>
19689                <access>read-only</access>
19690              </field>
19691            </fields>
19692          </register>
19693          <register>
19694            <name>COUNTER</name>
19695            <description>Counter count register</description>
19696            <addressOffset>0x8</addressOffset>
19697            <size>32</size>
19698            <access>read-write</access>
19699            <resetValue>0x0</resetValue>
19700            <resetMask>0xFFFFFFFF</resetMask>
19701            <fields>
19702              <field>
19703                <name>COUNTER</name>
19704                <description>16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running.</description>
19705                <bitRange>[31:0]</bitRange>
19706                <access>read-write</access>
19707              </field>
19708            </fields>
19709          </register>
19710          <register>
19711            <name>CC</name>
19712            <description>Counter compare/capture register</description>
19713            <addressOffset>0xC</addressOffset>
19714            <size>32</size>
19715            <access>read-write</access>
19716            <resetValue>0xFFFFFFFF</resetValue>
19717            <resetMask>0xFFFFFFFF</resetMask>
19718            <fields>
19719              <field>
19720                <name>CC</name>
19721                <description>In CAPTURE mode, captures the counter value. In other modes, compared to counter value.</description>
19722                <bitRange>[31:0]</bitRange>
19723                <access>read-write</access>
19724              </field>
19725            </fields>
19726          </register>
19727          <register>
19728            <name>CC_BUFF</name>
19729            <description>Counter buffered compare/capture register</description>
19730            <addressOffset>0x10</addressOffset>
19731            <size>32</size>
19732            <access>read-write</access>
19733            <resetValue>0xFFFFFFFF</resetValue>
19734            <resetMask>0xFFFFFFFF</resetMask>
19735            <fields>
19736              <field>
19737                <name>CC</name>
19738                <description>Additional buffer for counter CC register.</description>
19739                <bitRange>[31:0]</bitRange>
19740                <access>read-write</access>
19741              </field>
19742            </fields>
19743          </register>
19744          <register>
19745            <name>PERIOD</name>
19746            <description>Counter period register</description>
19747            <addressOffset>0x14</addressOffset>
19748            <size>32</size>
19749            <access>read-write</access>
19750            <resetValue>0xFFFFFFFF</resetValue>
19751            <resetMask>0xFFFFFFFF</resetMask>
19752            <fields>
19753              <field>
19754                <name>PERIOD</name>
19755                <description>Period value: upper value of the counter. When the counter should count for n cycles, this field should be set to n-1.</description>
19756                <bitRange>[31:0]</bitRange>
19757                <access>read-write</access>
19758              </field>
19759            </fields>
19760          </register>
19761          <register>
19762            <name>PERIOD_BUFF</name>
19763            <description>Counter buffered period register</description>
19764            <addressOffset>0x18</addressOffset>
19765            <size>32</size>
19766            <access>read-write</access>
19767            <resetValue>0xFFFFFFFF</resetValue>
19768            <resetMask>0xFFFFFFFF</resetMask>
19769            <fields>
19770              <field>
19771                <name>PERIOD</name>
19772                <description>Additional buffer for counter PERIOD register.</description>
19773                <bitRange>[31:0]</bitRange>
19774                <access>read-write</access>
19775              </field>
19776            </fields>
19777          </register>
19778          <register>
19779            <name>TR_CTRL0</name>
19780            <description>Counter trigger control register 0</description>
19781            <addressOffset>0x20</addressOffset>
19782            <size>32</size>
19783            <access>read-write</access>
19784            <resetValue>0x10</resetValue>
19785            <resetMask>0xFFFFF</resetMask>
19786            <fields>
19787              <field>
19788                <name>CAPTURE_SEL</name>
19789                <description>Selects one of the 16 input triggers as a capture trigger. Input trigger 0 is always '0' and input trigger is always '1'. In the PWM, PWM_DT and PWM_PR modes this trigger is used to switch the values if the compare and period registers with their buffer counterparts.</description>
19790                <bitRange>[3:0]</bitRange>
19791                <access>read-write</access>
19792              </field>
19793              <field>
19794                <name>COUNT_SEL</name>
19795                <description>Selects one of the 16 input triggers as a count trigger. In QUAD mode, this is the first phase (phi A). Default setting selects input trigger 1, which is always '1'.</description>
19796                <bitRange>[7:4]</bitRange>
19797                <access>read-write</access>
19798              </field>
19799              <field>
19800                <name>RELOAD_SEL</name>
19801                <description>Selects one of the 16 input triggers as a reload trigger. In QUAD mode, this is the index or revolution pulse. In this mode, it will update the counter with 0x8000 (counter midpoint).</description>
19802                <bitRange>[11:8]</bitRange>
19803                <access>read-write</access>
19804              </field>
19805              <field>
19806                <name>STOP_SEL</name>
19807                <description>Selects one of the 16 input triggers as a stop trigger. In PWM, PWM_DT and PWM_PR modes, this is the kill trigger. In these modes, the kill trigger is used to either temporarily block the PWM outputs (PWM_STOP_ON_KILL is '0') or stop the functionality (PWM_STOP_ON_KILL is '1'). For the PWM and PWM_DT modes, the blocking of the output signals can be  asynchronous (STOP_EDGE should be NO_EDGE_DET) in which case the blocking is as long as the trigger is '1' or synchronous (STOP_EDGE should be RISING_EDGE) in which case it extends till the next terminal count event.</description>
19808                <bitRange>[15:12]</bitRange>
19809                <access>read-write</access>
19810              </field>
19811              <field>
19812                <name>START_SEL</name>
19813                <description>Selects one of the 16 input triggers as a start trigger. In QUAD mode, this is the second phase (phi B).</description>
19814                <bitRange>[19:16]</bitRange>
19815                <access>read-write</access>
19816              </field>
19817            </fields>
19818          </register>
19819          <register>
19820            <name>TR_CTRL1</name>
19821            <description>Counter trigger control register 1</description>
19822            <addressOffset>0x24</addressOffset>
19823            <size>32</size>
19824            <access>read-write</access>
19825            <resetValue>0x3FF</resetValue>
19826            <resetMask>0x3FF</resetMask>
19827            <fields>
19828              <field>
19829                <name>CAPTURE_EDGE</name>
19830                <description>A capture event will copy the counter value into the CC register.</description>
19831                <bitRange>[1:0]</bitRange>
19832                <access>read-write</access>
19833                <enumeratedValues>
19834                  <enumeratedValue>
19835                    <name>RISING_EDGE</name>
19836                    <description>Rising edge. Any rising edge generates an event.</description>
19837                    <value>0</value>
19838                  </enumeratedValue>
19839                  <enumeratedValue>
19840                    <name>FALLING_EDGE</name>
19841                    <description>Falling edge. Any falling edge generates an event.</description>
19842                    <value>1</value>
19843                  </enumeratedValue>
19844                  <enumeratedValue>
19845                    <name>BOTH_EDGES</name>
19846                    <description>Rising AND falling edge. Any odd amount of edges generates an event.</description>
19847                    <value>2</value>
19848                  </enumeratedValue>
19849                  <enumeratedValue>
19850                    <name>NO_EDGE_DET</name>
19851                    <description>No edge detection, use trigger as is.</description>
19852                    <value>3</value>
19853                  </enumeratedValue>
19854                </enumeratedValues>
19855              </field>
19856              <field>
19857                <name>COUNT_EDGE</name>
19858                <description>A counter event will increase or decrease the counter by '1'.</description>
19859                <bitRange>[3:2]</bitRange>
19860                <access>read-write</access>
19861                <enumeratedValues>
19862                  <enumeratedValue>
19863                    <name>RISING_EDGE</name>
19864                    <description>Rising edge. Any rising edge generates an event.</description>
19865                    <value>0</value>
19866                  </enumeratedValue>
19867                  <enumeratedValue>
19868                    <name>FALLING_EDGE</name>
19869                    <description>Falling edge. Any falling edge generates an event.</description>
19870                    <value>1</value>
19871                  </enumeratedValue>
19872                  <enumeratedValue>
19873                    <name>BOTH_EDGES</name>
19874                    <description>Rising AND falling edge. Any odd amount of edges generates an event.</description>
19875                    <value>2</value>
19876                  </enumeratedValue>
19877                  <enumeratedValue>
19878                    <name>NO_EDGE_DET</name>
19879                    <description>No edge detection, use trigger as is.</description>
19880                    <value>3</value>
19881                  </enumeratedValue>
19882                </enumeratedValues>
19883              </field>
19884              <field>
19885                <name>RELOAD_EDGE</name>
19886                <description>A reload event will initialize the counter. When counting up, the counter is initialized to '0'. When counting down, the counter is initialized with PERIOD.</description>
19887                <bitRange>[5:4]</bitRange>
19888                <access>read-write</access>
19889                <enumeratedValues>
19890                  <enumeratedValue>
19891                    <name>RISING_EDGE</name>
19892                    <description>Rising edge. Any rising edge generates an event.</description>
19893                    <value>0</value>
19894                  </enumeratedValue>
19895                  <enumeratedValue>
19896                    <name>FALLING_EDGE</name>
19897                    <description>Falling edge. Any falling edge generates an event.</description>
19898                    <value>1</value>
19899                  </enumeratedValue>
19900                  <enumeratedValue>
19901                    <name>BOTH_EDGES</name>
19902                    <description>Rising AND falling edge. Any odd amount of edges generates an event.</description>
19903                    <value>2</value>
19904                  </enumeratedValue>
19905                  <enumeratedValue>
19906                    <name>NO_EDGE_DET</name>
19907                    <description>No edge detection, use trigger as is.</description>
19908                    <value>3</value>
19909                  </enumeratedValue>
19910                </enumeratedValues>
19911              </field>
19912              <field>
19913                <name>STOP_EDGE</name>
19914                <description>A stop event, will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter.</description>
19915                <bitRange>[7:6]</bitRange>
19916                <access>read-write</access>
19917                <enumeratedValues>
19918                  <enumeratedValue>
19919                    <name>RISING_EDGE</name>
19920                    <description>Rising edge. Any rising edge generates an event.</description>
19921                    <value>0</value>
19922                  </enumeratedValue>
19923                  <enumeratedValue>
19924                    <name>FALLING_EDGE</name>
19925                    <description>Falling edge. Any falling edge generates an event.</description>
19926                    <value>1</value>
19927                  </enumeratedValue>
19928                  <enumeratedValue>
19929                    <name>BOTH_EDGES</name>
19930                    <description>Rising AND falling edge. Any odd amount of edges generates an event.</description>
19931                    <value>2</value>
19932                  </enumeratedValue>
19933                  <enumeratedValue>
19934                    <name>NO_EDGE_DET</name>
19935                    <description>No edge detection, use trigger as is.</description>
19936                    <value>3</value>
19937                  </enumeratedValue>
19938                </enumeratedValues>
19939              </field>
19940              <field>
19941                <name>START_EDGE</name>
19942                <description>A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does.</description>
19943                <bitRange>[9:8]</bitRange>
19944                <access>read-write</access>
19945                <enumeratedValues>
19946                  <enumeratedValue>
19947                    <name>RISING_EDGE</name>
19948                    <description>Rising edge. Any rising edge generates an event.</description>
19949                    <value>0</value>
19950                  </enumeratedValue>
19951                  <enumeratedValue>
19952                    <name>FALLING_EDGE</name>
19953                    <description>Falling edge. Any falling edge generates an event.</description>
19954                    <value>1</value>
19955                  </enumeratedValue>
19956                  <enumeratedValue>
19957                    <name>BOTH_EDGES</name>
19958                    <description>Rising AND falling edge. Any odd amount of edges generates an event.</description>
19959                    <value>2</value>
19960                  </enumeratedValue>
19961                  <enumeratedValue>
19962                    <name>NO_EDGE_DET</name>
19963                    <description>No edge detection, use trigger as is.</description>
19964                    <value>3</value>
19965                  </enumeratedValue>
19966                </enumeratedValues>
19967              </field>
19968            </fields>
19969          </register>
19970          <register>
19971            <name>TR_CTRL2</name>
19972            <description>Counter trigger control register 2</description>
19973            <addressOffset>0x28</addressOffset>
19974            <size>32</size>
19975            <access>read-write</access>
19976            <resetValue>0x3F</resetValue>
19977            <resetMask>0x3F</resetMask>
19978            <fields>
19979              <field>
19980                <name>CC_MATCH_MODE</name>
19981                <description>Determines the effect of a compare match event (COUNTER equals CC register) on the 'line_out' output signals.  Note that INVERT is especially useful for center aligned pulse width modulation.
19982To generate a duty cycle of 0 percent, the counter CC register should be set to '0'. For a 100 percent duty cycle, the counter CC register should be set to larger than the counter PERIOD register.</description>
19983                <bitRange>[1:0]</bitRange>
19984                <access>read-write</access>
19985                <enumeratedValues>
19986                  <enumeratedValue>
19987                    <name>SET</name>
19988                    <description>Set to '1'</description>
19989                    <value>0</value>
19990                  </enumeratedValue>
19991                  <enumeratedValue>
19992                    <name>CLEAR</name>
19993                    <description>Set to '0'</description>
19994                    <value>1</value>
19995                  </enumeratedValue>
19996                  <enumeratedValue>
19997                    <name>INVERT</name>
19998                    <description>Invert</description>
19999                    <value>2</value>
20000                  </enumeratedValue>
20001                  <enumeratedValue>
20002                    <name>NO_CHANGE</name>
20003                    <description>No Change</description>
20004                    <value>3</value>
20005                  </enumeratedValue>
20006                </enumeratedValues>
20007              </field>
20008              <field>
20009                <name>OVERFLOW_MODE</name>
20010                <description>Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals.</description>
20011                <bitRange>[3:2]</bitRange>
20012                <access>read-write</access>
20013                <enumeratedValues>
20014                  <enumeratedValue>
20015                    <name>SET</name>
20016                    <description>Set to '1'</description>
20017                    <value>0</value>
20018                  </enumeratedValue>
20019                  <enumeratedValue>
20020                    <name>CLEAR</name>
20021                    <description>Set to '0'</description>
20022                    <value>1</value>
20023                  </enumeratedValue>
20024                  <enumeratedValue>
20025                    <name>INVERT</name>
20026                    <description>Invert</description>
20027                    <value>2</value>
20028                  </enumeratedValue>
20029                  <enumeratedValue>
20030                    <name>NO_CHANGE</name>
20031                    <description>No Change</description>
20032                    <value>3</value>
20033                  </enumeratedValue>
20034                </enumeratedValues>
20035              </field>
20036              <field>
20037                <name>UNDERFLOW_MODE</name>
20038                <description>Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals.</description>
20039                <bitRange>[5:4]</bitRange>
20040                <access>read-write</access>
20041                <enumeratedValues>
20042                  <enumeratedValue>
20043                    <name>SET</name>
20044                    <description>Set to '1'</description>
20045                    <value>0</value>
20046                  </enumeratedValue>
20047                  <enumeratedValue>
20048                    <name>CLEAR</name>
20049                    <description>Set to '0'</description>
20050                    <value>1</value>
20051                  </enumeratedValue>
20052                  <enumeratedValue>
20053                    <name>INVERT</name>
20054                    <description>Invert</description>
20055                    <value>2</value>
20056                  </enumeratedValue>
20057                  <enumeratedValue>
20058                    <name>NO_CHANGE</name>
20059                    <description>No Change</description>
20060                    <value>3</value>
20061                  </enumeratedValue>
20062                </enumeratedValues>
20063              </field>
20064            </fields>
20065          </register>
20066          <register>
20067            <name>INTR</name>
20068            <description>Interrupt request register</description>
20069            <addressOffset>0x30</addressOffset>
20070            <size>32</size>
20071            <access>read-write</access>
20072            <resetValue>0x0</resetValue>
20073            <resetMask>0x3</resetMask>
20074            <fields>
20075              <field>
20076                <name>TC</name>
20077                <description>Terminal count event. Set to '1', when event is detected. Write with '1' to clear bit.</description>
20078                <bitRange>[0:0]</bitRange>
20079                <access>read-write</access>
20080              </field>
20081              <field>
20082                <name>CC_MATCH</name>
20083                <description>Counter matches CC register event. Set to '1', when event is detected. Write with '1' to clear bit.</description>
20084                <bitRange>[1:1]</bitRange>
20085                <access>read-write</access>
20086              </field>
20087            </fields>
20088          </register>
20089          <register>
20090            <name>INTR_SET</name>
20091            <description>Interrupt set request register</description>
20092            <addressOffset>0x34</addressOffset>
20093            <size>32</size>
20094            <access>read-write</access>
20095            <resetValue>0x0</resetValue>
20096            <resetMask>0x3</resetMask>
20097            <fields>
20098              <field>
20099                <name>TC</name>
20100                <description>Write with '1' to set corresponding bit in interrupt request register.</description>
20101                <bitRange>[0:0]</bitRange>
20102                <access>read-write</access>
20103              </field>
20104              <field>
20105                <name>CC_MATCH</name>
20106                <description>Write with '1' to set corresponding bit in interrupt request register.</description>
20107                <bitRange>[1:1]</bitRange>
20108                <access>read-write</access>
20109              </field>
20110            </fields>
20111          </register>
20112          <register>
20113            <name>INTR_MASK</name>
20114            <description>Interrupt mask register</description>
20115            <addressOffset>0x38</addressOffset>
20116            <size>32</size>
20117            <access>read-write</access>
20118            <resetValue>0x0</resetValue>
20119            <resetMask>0x3</resetMask>
20120            <fields>
20121              <field>
20122                <name>TC</name>
20123                <description>Mask bit for corresponding bit in interrupt request register.</description>
20124                <bitRange>[0:0]</bitRange>
20125                <access>read-write</access>
20126              </field>
20127              <field>
20128                <name>CC_MATCH</name>
20129                <description>Mask bit for corresponding bit in interrupt request register.</description>
20130                <bitRange>[1:1]</bitRange>
20131                <access>read-write</access>
20132              </field>
20133            </fields>
20134          </register>
20135          <register>
20136            <name>INTR_MASKED</name>
20137            <description>Interrupt masked request register</description>
20138            <addressOffset>0x3C</addressOffset>
20139            <size>32</size>
20140            <access>read-only</access>
20141            <resetValue>0x0</resetValue>
20142            <resetMask>0x3</resetMask>
20143            <fields>
20144              <field>
20145                <name>TC</name>
20146                <description>Logical and of corresponding request and mask bits.</description>
20147                <bitRange>[0:0]</bitRange>
20148                <access>read-only</access>
20149              </field>
20150              <field>
20151                <name>CC_MATCH</name>
20152                <description>Logical and of corresponding request and mask bits.</description>
20153                <bitRange>[1:1]</bitRange>
20154                <access>read-only</access>
20155              </field>
20156            </fields>
20157          </register>
20158        </cluster>
20159      </registers>
20160    </peripheral>
20161    <peripheral>
20162      <name>SMIF0</name>
20163      <description>Serial Memory Interface</description>
20164      <headerStructName>SMIF</headerStructName>
20165      <baseAddress>0x40410000</baseAddress>
20166      <addressBlock>
20167        <offset>0</offset>
20168        <size>65536</size>
20169        <usage>registers</usage>
20170      </addressBlock>
20171      <registers>
20172        <register>
20173          <name>CTL</name>
20174          <description>Control</description>
20175          <addressOffset>0x0</addressOffset>
20176          <size>32</size>
20177          <access>read-write</access>
20178          <resetValue>0x3000</resetValue>
20179          <resetMask>0x81073001</resetMask>
20180          <fields>
20181            <field>
20182              <name>XIP_MODE</name>
20183              <description>Mode of operation.
20184
20185Note: this field should only be changed when the IP is disabled or when STATUS.BUSY is '0' and SW should not be executing from the XIP interface or MMIO interface.</description>
20186              <bitRange>[0:0]</bitRange>
20187              <access>read-write</access>
20188              <enumeratedValues>
20189                <enumeratedValue>
20190                  <name>MMIO_MODE</name>
20191                  <description>'0': MMIO mode. Individual MMIO accesses to TX and RX FIFOs are used to generate a sequence of SPI transfers. This mode of operation allows for large flexibility in terms of the SPI transfers that can be generated.</description>
20192                  <value>0</value>
20193                </enumeratedValue>
20194                <enumeratedValue>
20195                  <name>XIP_MODE</name>
20196                  <description>1': XIP mode. eXecute-In-Place mode: incoming read and write transfers over the AHB-Lite bus infrastructure are automatically translated in SPI transfers to read data from and write data to a device. This mode of operation allow for efficient device read and write operations. This mode is only supported in SPI_MODE.</description>
20197                  <value>1</value>
20198                </enumeratedValue>
20199              </enumeratedValues>
20200            </field>
20201            <field>
20202              <name>CLOCK_IF_RX_SEL</name>
20203              <description>Specifies device interface receiver clock 'clk_if_rx' source. MISO data is captured on the rising edge of 'clk_if_rx'.
20204'0': 'spi_clk_out' (internal clock)
20205'1': !'spi_clk_out' (internal clock)
20206'2': 'spi_clk_in' (feedback clock)
20207'3': !'spi_clk_in' (feedback clock)
20208
20209Note: the device interface transmitter clock 'clk_if_tx' is fixed and is 'spi_clk_out' MOSI data is driven on the falling edge of 'clk_if_tx'.</description>
20210              <bitRange>[13:12]</bitRange>
20211              <access>read-write</access>
20212            </field>
20213            <field>
20214              <name>DESELECT_DELAY</name>
20215              <description>Specifies the minimum duration of SPI deselection ('spi_select_out[]' is high/'1') in between SPI transfers:
20216'0': 1 interface clock cycle.
20217'1': 2 interface clock cycles.
20218'2': 3 interface clock cycles.
20219'3': 4 interface clock cycles.
20220'4': 5 interface clock cycles.
20221'5': 6 interface clock cycles.
20222'6': 7 interface clock cycles.
20223'7': 8 interface clock cycles.
20224
20225During SPI deselection, 'spi_select_out[]' are '1'/inactive, 'spi_data_out[]' are '1' and 'spi_clk_out' is '0'/inactive.</description>
20226              <bitRange>[18:16]</bitRange>
20227              <access>read-write</access>
20228            </field>
20229            <field>
20230              <name>BLOCK</name>
20231              <description>Specifies what happens for MMIO interface read accesses to an empty RX data FIFO or to a full TX format/data FIFO. Note: the FIFOs can only be accessed in MMIO_MODE.
20232
20233This field is not used for test controller accesses.</description>
20234              <bitRange>[24:24]</bitRange>
20235              <access>read-write</access>
20236              <enumeratedValues>
20237                <enumeratedValue>
20238                  <name>BUS_ERROR</name>
20239                  <description>0': Generate an AHB-Lite bus error. This option is useful when SW decides to use polling on STATUS.TR_BUSY to determine if a interface transfer is no longer busy (transfer is completed). This option adds SW complexity, but limits the number of AHB-Lite wait states (and limits ISR latency).</description>
20240                  <value>0</value>
20241                </enumeratedValue>
20242                <enumeratedValue>
20243                  <name>WAIT_STATES</name>
20244                  <description>1': Introduce wait states. This setting potentially locks up the AHB-Lite infrastructure and may increase the CPU interrupt latency.This option is useful when SW performs TX/RX data FIFO accesses immediately after a command is setup using the TX format FIFO. This option has low SW complexity, but may result in a significant number of AHB-Lite wait states (and may increase ISR latency).</description>
20245                  <value>1</value>
20246                </enumeratedValue>
20247              </enumeratedValues>
20248            </field>
20249            <field>
20250              <name>ENABLED</name>
20251              <description>IP enable:
20252'0': Disabled. All non-retention registers are reset to their default value when the IP is disabled. When the IP is disabled, the XIP accesses produce AHB-Lite bus errors.
20253'1': Enabled.
20254
20255Note: Before disabling the IP, SW should ensure that the IP is NOT busy (STATUS.BUSY is '0'), otherwise illegal interface transfers may occur.</description>
20256              <bitRange>[31:31]</bitRange>
20257              <access>read-write</access>
20258              <enumeratedValues>
20259                <enumeratedValue>
20260                  <name>DISABLED</name>
20261                  <description>N/A</description>
20262                  <value>0</value>
20263                </enumeratedValue>
20264                <enumeratedValue>
20265                  <name>ENABLED</name>
20266                  <description>N/A</description>
20267                  <value>1</value>
20268                </enumeratedValue>
20269              </enumeratedValues>
20270            </field>
20271          </fields>
20272        </register>
20273        <register>
20274          <name>STATUS</name>
20275          <description>Status</description>
20276          <addressOffset>0x4</addressOffset>
20277          <size>32</size>
20278          <access>read-only</access>
20279          <resetValue>0x0</resetValue>
20280          <resetMask>0x80000000</resetMask>
20281          <fields>
20282            <field>
20283              <name>BUSY</name>
20284              <description>Cache, cryptography, XIP, device interface or any other logic busy in the IP:
20285'0': not busy
20286'1': busy
20287When BUSY is '0', the IP can be safely disabled without:
20288- the potential loss of transient write data.
20289- the potential risk of aborting an inflight SPI device interface transfer.
20290When BUSY is '0', the mode of operation (XIP_MODE or MMIO_MODE) can be safely changed.</description>
20291              <bitRange>[31:31]</bitRange>
20292              <access>read-only</access>
20293            </field>
20294          </fields>
20295        </register>
20296        <register>
20297          <name>TX_CMD_FIFO_STATUS</name>
20298          <description>Transmitter command FIFO status</description>
20299          <addressOffset>0x44</addressOffset>
20300          <size>32</size>
20301          <access>read-only</access>
20302          <resetValue>0x0</resetValue>
20303          <resetMask>0x7</resetMask>
20304          <fields>
20305            <field>
20306              <name>USED3</name>
20307              <description>Number of entries that are used in the TX command FIFO (available in both XIP_MODE and MMIO_MODE). Legal range: [0, 4].</description>
20308              <bitRange>[2:0]</bitRange>
20309              <access>read-only</access>
20310            </field>
20311          </fields>
20312        </register>
20313        <register>
20314          <name>TX_CMD_FIFO_WR</name>
20315          <description>Transmitter command FIFO write</description>
20316          <addressOffset>0x50</addressOffset>
20317          <size>32</size>
20318          <access>write-only</access>
20319          <resetValue>0x0</resetValue>
20320          <resetMask>0xFFFFF</resetMask>
20321          <fields>
20322            <field>
20323              <name>DATA20</name>
20324              <description>Command data. The higher two bits DATA[19:18] specify the specific command
20325'0'/TX: A SPI transfer always start with a TX command FIFO entry of the 'TX' format.
20326- DATA[17:16] specifies the width of the data transfer:
20327   - '0': 1 bit/cycle (single data transfer).
20328   - '1': 2 bits/cycle (dual data transfer).
20329   - '2': 4 bits/cycle (quad data transfer).
20330   - '3': 8 bits/cycle (octal data transfer).
20331- DATA[15]: specifies whether this is the last TX Byte; i.e. whether the 'spi_select_out[3:0]' IO output signals are de-activated after the transfer.
20332- DATA[11:8] specifies which of the four devices are selected. DATA[11:8] are directly mapped to 'spi_select_out[3:0]'. Two devices can be selected at the same time in dual-quad mode.
20333  - '0': device deselected
20334  - '1': device selected
20335- DATA[7:0] specifies the transmitted Byte.
20336
20337'1'/TX_COUNT: The 'TX_COUNT' command relies on the TX data FIFO to provide the transmitted bytes. The 'TX_COUNT' command is ALWAYS considered to be the last command of a SPI data transfers.
20338- DATA[17:16] specifies the width of the transfer.
20339- DATA[15:0] specifies the number of to be transmitted Bytes (minus 1) from the TX data FIFO.
20340
20341'2'/RX_COUNT: The 'RX_COUNT' command relies on the RX data FIFO to accept the received bytes. The 'RX_COUNT' command is ALWAYS considered to be the last command of a SPI data transfers.
20342- DATA[17:16] specifies the width of the transfer.
20343- DATA[15:0] specifies the number of to be transmitted Bytes (minus 1) to the RX data FIFO.
20344
20345'3'/DUMMY_COUNT: The 'DUMMY_COUNT' command conveys dummy cycles. Dummy cycles are used to implement a Turn-Around time in which the SPI master changes from a transmitter driving the data lines to a receiver receiving on the same data lines. The 'DUMMY_COUNT' command is ALWAYS considered to be NOT the last command of a SPI data transfers; i.e. it needs to be followed by another command.
20346- DATA[15:0] specifies the number of dummy cycles (minus 1). In dummy cycles, the data lines are not driven.</description>
20347              <bitRange>[19:0]</bitRange>
20348              <access>write-only</access>
20349            </field>
20350          </fields>
20351        </register>
20352        <register>
20353          <name>TX_DATA_FIFO_CTL</name>
20354          <description>Transmitter data FIFO control</description>
20355          <addressOffset>0x80</addressOffset>
20356          <size>32</size>
20357          <access>read-write</access>
20358          <resetValue>0x0</resetValue>
20359          <resetMask>0x7</resetMask>
20360          <fields>
20361            <field>
20362              <name>TRIGGER_LEVEL</name>
20363              <description>Determines when the TX data FIFO 'tr_tx_req' trigger is activated  (trigger activation requires MMIO_MODE, the trigger is NOT activated in XIP_MODE):
20364- Trigger is active when TX_DATA_FIFO_STATUS.USED &lt;= TRIGGER_LEVEL.</description>
20365              <bitRange>[2:0]</bitRange>
20366              <access>read-write</access>
20367            </field>
20368          </fields>
20369        </register>
20370        <register>
20371          <name>TX_DATA_FIFO_STATUS</name>
20372          <description>Transmitter data FIFO status</description>
20373          <addressOffset>0x84</addressOffset>
20374          <size>32</size>
20375          <access>read-only</access>
20376          <resetValue>0x0</resetValue>
20377          <resetMask>0xF</resetMask>
20378          <fields>
20379            <field>
20380              <name>USED4</name>
20381              <description>Number of entries that are used in the TX data FIFO (available in both XIP_MODE and MMIO_MODE). Legal range: [0, 8].</description>
20382              <bitRange>[3:0]</bitRange>
20383              <access>read-only</access>
20384            </field>
20385          </fields>
20386        </register>
20387        <register>
20388          <name>TX_DATA_FIFO_WR1</name>
20389          <description>Transmitter data FIFO write</description>
20390          <addressOffset>0x90</addressOffset>
20391          <size>32</size>
20392          <access>write-only</access>
20393          <resetValue>0x0</resetValue>
20394          <resetMask>0xFF</resetMask>
20395          <fields>
20396            <field>
20397              <name>DATA0</name>
20398              <description>TX data (written to TX data FIFO).</description>
20399              <bitRange>[7:0]</bitRange>
20400              <access>write-only</access>
20401            </field>
20402          </fields>
20403        </register>
20404        <register>
20405          <name>TX_DATA_FIFO_WR2</name>
20406          <description>Transmitter data FIFO write</description>
20407          <addressOffset>0x94</addressOffset>
20408          <size>32</size>
20409          <access>write-only</access>
20410          <resetValue>0x0</resetValue>
20411          <resetMask>0xFFFF</resetMask>
20412          <fields>
20413            <field>
20414              <name>DATA0</name>
20415              <description>TX data (written to TX data FIFO, first byte).</description>
20416              <bitRange>[7:0]</bitRange>
20417              <access>write-only</access>
20418            </field>
20419            <field>
20420              <name>DATA1</name>
20421              <description>TX data (written to TX data FIFO, second byte).</description>
20422              <bitRange>[15:8]</bitRange>
20423              <access>write-only</access>
20424            </field>
20425          </fields>
20426        </register>
20427        <register>
20428          <name>TX_DATA_FIFO_WR4</name>
20429          <description>Transmitter data FIFO write</description>
20430          <addressOffset>0x98</addressOffset>
20431          <size>32</size>
20432          <access>write-only</access>
20433          <resetValue>0x0</resetValue>
20434          <resetMask>0xFFFFFFFF</resetMask>
20435          <fields>
20436            <field>
20437              <name>DATA0</name>
20438              <description>TX data (written to TX data FIFO, first byte).</description>
20439              <bitRange>[7:0]</bitRange>
20440              <access>write-only</access>
20441            </field>
20442            <field>
20443              <name>DATA1</name>
20444              <description>TX data (written to TX data FIFO, second byte).</description>
20445              <bitRange>[15:8]</bitRange>
20446              <access>write-only</access>
20447            </field>
20448            <field>
20449              <name>DATA2</name>
20450              <description>TX data (written to TX data FIFO, third byte).</description>
20451              <bitRange>[23:16]</bitRange>
20452              <access>write-only</access>
20453            </field>
20454            <field>
20455              <name>DATA3</name>
20456              <description>TX data (written to TX data FIFO, fourth byte).</description>
20457              <bitRange>[31:24]</bitRange>
20458              <access>write-only</access>
20459            </field>
20460          </fields>
20461        </register>
20462        <register>
20463          <name>RX_DATA_FIFO_CTL</name>
20464          <description>Receiver data FIFO control</description>
20465          <addressOffset>0xC0</addressOffset>
20466          <size>32</size>
20467          <access>read-write</access>
20468          <resetValue>0x0</resetValue>
20469          <resetMask>0x7</resetMask>
20470          <fields>
20471            <field>
20472              <name>TRIGGER_LEVEL</name>
20473              <description>Determines when RX data FIFO 'tr_rx_req' trigger is activated (trigger activation requires MMIO_MODE, the trigger is NOT activated in XIP_MODE):
20474- Trigger is active when RX_DATA_FIFO_STATUS.USED &gt; TRIGGER_LEVEL.</description>
20475              <bitRange>[2:0]</bitRange>
20476              <access>read-write</access>
20477            </field>
20478          </fields>
20479        </register>
20480        <register>
20481          <name>RX_DATA_FIFO_STATUS</name>
20482          <description>Receiver data FIFO status</description>
20483          <addressOffset>0xC4</addressOffset>
20484          <size>32</size>
20485          <access>read-only</access>
20486          <resetValue>0x0</resetValue>
20487          <resetMask>0xF</resetMask>
20488          <fields>
20489            <field>
20490              <name>USED4</name>
20491              <description>Number of entries that are used in the RX data FIFO (available in both XIP_MODE and MMIO_MODE). Legal range: [0, 8].</description>
20492              <bitRange>[3:0]</bitRange>
20493              <access>read-only</access>
20494            </field>
20495          </fields>
20496        </register>
20497        <register>
20498          <name>RX_DATA_FIFO_RD1</name>
20499          <description>Receiver data FIFO read</description>
20500          <addressOffset>0xD0</addressOffset>
20501          <size>32</size>
20502          <access>read-only</access>
20503          <resetValue>0x0</resetValue>
20504          <resetMask>0xFF</resetMask>
20505          <fields>
20506            <field>
20507              <name>DATA0</name>
20508              <description>RX data (read from RX data FIFO).</description>
20509              <bitRange>[7:0]</bitRange>
20510              <access>read-only</access>
20511            </field>
20512          </fields>
20513        </register>
20514        <register>
20515          <name>RX_DATA_FIFO_RD2</name>
20516          <description>Receiver data FIFO read</description>
20517          <addressOffset>0xD4</addressOffset>
20518          <size>32</size>
20519          <access>read-only</access>
20520          <resetValue>0x0</resetValue>
20521          <resetMask>0xFFFF</resetMask>
20522          <fields>
20523            <field>
20524              <name>DATA0</name>
20525              <description>RX data (read from RX data FIFO, first byte).</description>
20526              <bitRange>[7:0]</bitRange>
20527              <access>read-only</access>
20528            </field>
20529            <field>
20530              <name>DATA1</name>
20531              <description>RX data (read from RX data FIFO, second byte).</description>
20532              <bitRange>[15:8]</bitRange>
20533              <access>read-only</access>
20534            </field>
20535          </fields>
20536        </register>
20537        <register>
20538          <name>RX_DATA_FIFO_RD4</name>
20539          <description>Receiver data FIFO read</description>
20540          <addressOffset>0xD8</addressOffset>
20541          <size>32</size>
20542          <access>read-only</access>
20543          <resetValue>0x0</resetValue>
20544          <resetMask>0xFFFFFFFF</resetMask>
20545          <fields>
20546            <field>
20547              <name>DATA0</name>
20548              <description>RX data (read from RX data FIFO, first byte).</description>
20549              <bitRange>[7:0]</bitRange>
20550              <access>read-only</access>
20551            </field>
20552            <field>
20553              <name>DATA1</name>
20554              <description>RX data (read from RX data FIFO, second byte).</description>
20555              <bitRange>[15:8]</bitRange>
20556              <access>read-only</access>
20557            </field>
20558            <field>
20559              <name>DATA2</name>
20560              <description>RX data (read from RX data FIFO, third byte).</description>
20561              <bitRange>[23:16]</bitRange>
20562              <access>read-only</access>
20563            </field>
20564            <field>
20565              <name>DATA3</name>
20566              <description>RX data (read from RX data FIFO, fourth byte).</description>
20567              <bitRange>[31:24]</bitRange>
20568              <access>read-only</access>
20569            </field>
20570          </fields>
20571        </register>
20572        <register>
20573          <name>RX_DATA_FIFO_RD1_SILENT</name>
20574          <description>Receiver data FIFO silent read</description>
20575          <addressOffset>0xE0</addressOffset>
20576          <size>32</size>
20577          <access>read-only</access>
20578          <resetValue>0x0</resetValue>
20579          <resetMask>0xFF</resetMask>
20580          <fields>
20581            <field>
20582              <name>DATA0</name>
20583              <description>RX data (read from RX data FIFO).</description>
20584              <bitRange>[7:0]</bitRange>
20585              <access>read-only</access>
20586            </field>
20587          </fields>
20588        </register>
20589        <register>
20590          <name>SLOW_CA_CTL</name>
20591          <description>Slow cache control</description>
20592          <addressOffset>0x100</addressOffset>
20593          <size>32</size>
20594          <access>read-write</access>
20595          <resetValue>0xC0000000</resetValue>
20596          <resetMask>0xC3030000</resetMask>
20597          <fields>
20598            <field>
20599              <name>WAY</name>
20600              <description>Specifies the cache way for which cache information is provided in SLOW_CA_STATUS0/1/2.</description>
20601              <bitRange>[17:16]</bitRange>
20602              <access>read-write</access>
20603            </field>
20604            <field>
20605              <name>SET_ADDR</name>
20606              <description>Specifies the cache set for which cache information is provided in SLOW_CA_STATUS0/1/2.</description>
20607              <bitRange>[25:24]</bitRange>
20608              <access>read-write</access>
20609            </field>
20610            <field>
20611              <name>PREF_EN</name>
20612              <description>Prefetch enable:
20613'0': Disabled.
20614'1': Enabled.
20615
20616Prefetching requires the cache to be enabled; i.e. ENABLED is '1'.</description>
20617              <bitRange>[30:30]</bitRange>
20618              <access>read-write</access>
20619            </field>
20620            <field>
20621              <name>ENABLED</name>
20622              <description>Cache enable:
20623'0': Disabled.
20624'1': Enabled.</description>
20625              <bitRange>[31:31]</bitRange>
20626              <access>read-write</access>
20627            </field>
20628          </fields>
20629        </register>
20630        <register>
20631          <name>SLOW_CA_CMD</name>
20632          <description>Slow cache command</description>
20633          <addressOffset>0x108</addressOffset>
20634          <size>32</size>
20635          <access>read-write</access>
20636          <resetValue>0x0</resetValue>
20637          <resetMask>0x1</resetMask>
20638          <fields>
20639            <field>
20640              <name>INV</name>
20641              <description>Cache and prefetch buffer invalidation.
20642SW writes a '1' to clear the cache and prefetch buffer. The cache's LRU structure is also reset to its default state.
20643Note,
20644A write access will invalidate the prefetch buffer automatically in hardware.
20645A write access should invalidate both fast and slow caches, by firmware.
20646Note, firmware should invalidate the cache and prefetch buffer only when STATUS.BUSY is '0'.</description>
20647              <bitRange>[0:0]</bitRange>
20648              <access>read-write</access>
20649            </field>
20650          </fields>
20651        </register>
20652        <register>
20653          <name>FAST_CA_CTL</name>
20654          <description>Fast cache control</description>
20655          <addressOffset>0x180</addressOffset>
20656          <size>32</size>
20657          <access>read-write</access>
20658          <resetValue>0xC0000000</resetValue>
20659          <resetMask>0xC3030000</resetMask>
20660          <fields>
20661            <field>
20662              <name>WAY</name>
20663              <description>See SLOW_CA_CTL.WAY.</description>
20664              <bitRange>[17:16]</bitRange>
20665              <access>read-write</access>
20666            </field>
20667            <field>
20668              <name>SET_ADDR</name>
20669              <description>See SLOW_CA_CTL.SET_ADDR.</description>
20670              <bitRange>[25:24]</bitRange>
20671              <access>read-write</access>
20672            </field>
20673            <field>
20674              <name>PREF_EN</name>
20675              <description>See SLOW_CA_CTL.PREF_EN.</description>
20676              <bitRange>[30:30]</bitRange>
20677              <access>read-write</access>
20678            </field>
20679            <field>
20680              <name>ENABLED</name>
20681              <description>See SLOW_CA_CTL.ENABLED.</description>
20682              <bitRange>[31:31]</bitRange>
20683              <access>read-write</access>
20684            </field>
20685          </fields>
20686        </register>
20687        <register>
20688          <name>FAST_CA_CMD</name>
20689          <description>Fast cache command</description>
20690          <addressOffset>0x188</addressOffset>
20691          <size>32</size>
20692          <access>read-write</access>
20693          <resetValue>0x0</resetValue>
20694          <resetMask>0x1</resetMask>
20695          <fields>
20696            <field>
20697              <name>INV</name>
20698              <description>See SLOW_CA_CMD.INV.</description>
20699              <bitRange>[0:0]</bitRange>
20700              <access>read-write</access>
20701            </field>
20702          </fields>
20703        </register>
20704        <register>
20705          <name>CRYPTO_CMD</name>
20706          <description>Cryptography Command</description>
20707          <addressOffset>0x200</addressOffset>
20708          <size>32</size>
20709          <access>read-write</access>
20710          <resetValue>0x0</resetValue>
20711          <resetMask>0x1</resetMask>
20712          <fields>
20713            <field>
20714              <name>START</name>
20715              <description>SW sets this field to '1' to start a AES-128 forward block cipher operation (on the address in CRYPTO_ADDR). HW sets this field to '0' to indicate that the operation has completed. Once completed, the result of the operation can be read from CRYPTO_RESULT0, ..., CRYPTO_RESULT3.
20716
20717The operation takes roughly 13 clk_hf clock cycles.
20718
20719Note: An operation can only be started in MMIO_MODE.</description>
20720              <bitRange>[0:0]</bitRange>
20721              <access>read-write</access>
20722            </field>
20723          </fields>
20724        </register>
20725        <register>
20726          <name>CRYPTO_INPUT0</name>
20727          <description>Cryptography input 0</description>
20728          <addressOffset>0x220</addressOffset>
20729          <size>32</size>
20730          <access>read-write</access>
20731          <resetValue>0x0</resetValue>
20732          <resetMask>0x0</resetMask>
20733          <fields>
20734            <field>
20735              <name>INPUT</name>
20736              <description>Four Bytes of the plaintext PT[31:0] = CRYPTO_INPUT0.INPUT[31:0].</description>
20737              <bitRange>[31:0]</bitRange>
20738              <access>read-write</access>
20739            </field>
20740          </fields>
20741        </register>
20742        <register>
20743          <name>CRYPTO_INPUT1</name>
20744          <description>Cryptography input 1</description>
20745          <addressOffset>0x224</addressOffset>
20746          <size>32</size>
20747          <access>read-write</access>
20748          <resetValue>0x0</resetValue>
20749          <resetMask>0x0</resetMask>
20750          <fields>
20751            <field>
20752              <name>INPUT</name>
20753              <description>Four Bytes of the plaintext PT[63:32] = CRYPTO_INPUT1.INPUT[31:0].</description>
20754              <bitRange>[31:0]</bitRange>
20755              <access>read-write</access>
20756            </field>
20757          </fields>
20758        </register>
20759        <register>
20760          <name>CRYPTO_INPUT2</name>
20761          <description>Cryptography input 2</description>
20762          <addressOffset>0x228</addressOffset>
20763          <size>32</size>
20764          <access>read-write</access>
20765          <resetValue>0x0</resetValue>
20766          <resetMask>0x0</resetMask>
20767          <fields>
20768            <field>
20769              <name>INPUT</name>
20770              <description>Four Bytes of the plaintext PT[95:64] = CRYPTO_INPUT2.INPUT[31:0].</description>
20771              <bitRange>[31:0]</bitRange>
20772              <access>read-write</access>
20773            </field>
20774          </fields>
20775        </register>
20776        <register>
20777          <name>CRYPTO_INPUT3</name>
20778          <description>Cryptography input 3</description>
20779          <addressOffset>0x22C</addressOffset>
20780          <size>32</size>
20781          <access>read-write</access>
20782          <resetValue>0x0</resetValue>
20783          <resetMask>0x0</resetMask>
20784          <fields>
20785            <field>
20786              <name>INPUT</name>
20787              <description>Four Bytes of the plaintext PT[127:96] = CRYPTO_INPUT3.INPUT[31:0].</description>
20788              <bitRange>[31:0]</bitRange>
20789              <access>read-write</access>
20790            </field>
20791          </fields>
20792        </register>
20793        <register>
20794          <name>CRYPTO_KEY0</name>
20795          <description>Cryptography key 0</description>
20796          <addressOffset>0x240</addressOffset>
20797          <size>32</size>
20798          <access>write-only</access>
20799          <resetValue>0x0</resetValue>
20800          <resetMask>0x0</resetMask>
20801          <fields>
20802            <field>
20803              <name>KEY</name>
20804              <description>Four Bytes of the key KEY[31:0] = CRYPTO_KEY0.KEY[31:0].</description>
20805              <bitRange>[31:0]</bitRange>
20806              <access>write-only</access>
20807            </field>
20808          </fields>
20809        </register>
20810        <register>
20811          <name>CRYPTO_KEY1</name>
20812          <description>Cryptography key 1</description>
20813          <addressOffset>0x244</addressOffset>
20814          <size>32</size>
20815          <access>write-only</access>
20816          <resetValue>0x0</resetValue>
20817          <resetMask>0x0</resetMask>
20818          <fields>
20819            <field>
20820              <name>KEY</name>
20821              <description>Four Bytes of the key KEY[63:32] = CRYPTO_KEY1.KEY[31:0].</description>
20822              <bitRange>[31:0]</bitRange>
20823              <access>write-only</access>
20824            </field>
20825          </fields>
20826        </register>
20827        <register>
20828          <name>CRYPTO_KEY2</name>
20829          <description>Cryptography key 2</description>
20830          <addressOffset>0x248</addressOffset>
20831          <size>32</size>
20832          <access>write-only</access>
20833          <resetValue>0x0</resetValue>
20834          <resetMask>0x0</resetMask>
20835          <fields>
20836            <field>
20837              <name>KEY</name>
20838              <description>Four Bytes of the key KEY[95:64] = CRYPTO_KEY2.KEY[31:0].</description>
20839              <bitRange>[31:0]</bitRange>
20840              <access>write-only</access>
20841            </field>
20842          </fields>
20843        </register>
20844        <register>
20845          <name>CRYPTO_KEY3</name>
20846          <description>Cryptography key 3</description>
20847          <addressOffset>0x24C</addressOffset>
20848          <size>32</size>
20849          <access>write-only</access>
20850          <resetValue>0x0</resetValue>
20851          <resetMask>0x0</resetMask>
20852          <fields>
20853            <field>
20854              <name>KEY</name>
20855              <description>Four Bytes of the key KEY[127:96] = CRYPTO_KEY3.KEY[31:0].</description>
20856              <bitRange>[31:0]</bitRange>
20857              <access>write-only</access>
20858            </field>
20859          </fields>
20860        </register>
20861        <register>
20862          <name>CRYPTO_OUTPUT0</name>
20863          <description>Cryptography output 0</description>
20864          <addressOffset>0x260</addressOffset>
20865          <size>32</size>
20866          <access>read-write</access>
20867          <resetValue>0x0</resetValue>
20868          <resetMask>0x0</resetMask>
20869          <fields>
20870            <field>
20871              <name>OUTPUT</name>
20872              <description>Four Bytes of the ciphertext CT[31:0] = CRYPTO_OUTPUT0.OUTPUT[31:0].</description>
20873              <bitRange>[31:0]</bitRange>
20874              <access>read-write</access>
20875            </field>
20876          </fields>
20877        </register>
20878        <register>
20879          <name>CRYPTO_OUTPUT1</name>
20880          <description>Cryptography output 1</description>
20881          <addressOffset>0x264</addressOffset>
20882          <size>32</size>
20883          <access>read-write</access>
20884          <resetValue>0x0</resetValue>
20885          <resetMask>0x0</resetMask>
20886          <fields>
20887            <field>
20888              <name>OUTPUT</name>
20889              <description>Four Bytes of the ciphertext CT[63:32] = CRYPTO_OUTPUT1.OUTPUT[31:0].</description>
20890              <bitRange>[31:0]</bitRange>
20891              <access>read-write</access>
20892            </field>
20893          </fields>
20894        </register>
20895        <register>
20896          <name>CRYPTO_OUTPUT2</name>
20897          <description>Cryptography output 2</description>
20898          <addressOffset>0x268</addressOffset>
20899          <size>32</size>
20900          <access>read-write</access>
20901          <resetValue>0x0</resetValue>
20902          <resetMask>0x0</resetMask>
20903          <fields>
20904            <field>
20905              <name>OUTPUT</name>
20906              <description>Four Bytes of the ciphertext CT[95:64] = CRYPTO_OUTPUT2.OUTPUT[31:0].</description>
20907              <bitRange>[31:0]</bitRange>
20908              <access>read-write</access>
20909            </field>
20910          </fields>
20911        </register>
20912        <register>
20913          <name>CRYPTO_OUTPUT3</name>
20914          <description>Cryptography output 3</description>
20915          <addressOffset>0x26C</addressOffset>
20916          <size>32</size>
20917          <access>read-write</access>
20918          <resetValue>0x0</resetValue>
20919          <resetMask>0x0</resetMask>
20920          <fields>
20921            <field>
20922              <name>OUTPUT</name>
20923              <description>Four Bytes of the ciphertext CT[127:96] = CRYPTO_OUTPUT3.OUTPUT[31:0].</description>
20924              <bitRange>[31:0]</bitRange>
20925              <access>read-write</access>
20926            </field>
20927          </fields>
20928        </register>
20929        <register>
20930          <name>INTR</name>
20931          <description>Interrupt register</description>
20932          <addressOffset>0x7C0</addressOffset>
20933          <size>32</size>
20934          <access>read-write</access>
20935          <resetValue>0x0</resetValue>
20936          <resetMask>0x3F</resetMask>
20937          <fields>
20938            <field>
20939              <name>TR_TX_REQ</name>
20940              <description>Activated in MMIO mode, when a TX data FIFO trigger 'tr_tx_req' is activated.</description>
20941              <bitRange>[0:0]</bitRange>
20942              <access>read-write</access>
20943            </field>
20944            <field>
20945              <name>TR_RX_REQ</name>
20946              <description>Activated in MMIO mode, when a RX data FIFO trigger 'tr_rx_req' is activated.</description>
20947              <bitRange>[1:1]</bitRange>
20948              <access>read-write</access>
20949            </field>
20950            <field>
20951              <name>XIP_ALIGNMENT_ERROR</name>
20952              <description>Activated in XIP mode, if:
20953- The selected device's ADDR_CTL.DIV2 is '1' and the AHB-Lite bus transfer address is not a multiple of 2.
20954- The selected device's ADDR_CTL.DIV2 is '1' and the XIP transfer request is NOT for a multiple of 2 Bytes.
20955
20956Note: In dual-quad SPI mode (ADDR_CTL.DIV is '1'), each memory device contributes a 4-bit nibble for read data or write data. This is only possible if the request address is a multiple of 2 and the number of requested Bytes is a multiple of 2.</description>
20957              <bitRange>[2:2]</bitRange>
20958              <access>read-write</access>
20959            </field>
20960            <field>
20961              <name>TX_CMD_FIFO_OVERFLOW</name>
20962              <description>Activated in MMIO mode, on an AHB-Lite write transfer to the TX command FIFO (TX_CMD_FIFO_WR) with not enough free entries available.</description>
20963              <bitRange>[3:3]</bitRange>
20964              <access>read-write</access>
20965            </field>
20966            <field>
20967              <name>TX_DATA_FIFO_OVERFLOW</name>
20968              <description>Activated in MMIO mode, on an AHB-Lite write transfer to the TX data FIFO (TX_DATA_FIFO_WR1, TX_DATA_FIFO_WR2, TX_DATA_FIFO_WR4) with not enough free entries available.</description>
20969              <bitRange>[4:4]</bitRange>
20970              <access>read-write</access>
20971            </field>
20972            <field>
20973              <name>RX_DATA_FIFO_UNDERFLOW</name>
20974              <description>Activated in MMIO mode, on an AHB-Lite read transfer from the RX data FIFO (RX_DATA_FIFO_RD1, RX_DATA_FIFO_RD2, RX_DATA_FIFO_RD4) with not enough entries available. Only activated for NON test bus controller transfers.</description>
20975              <bitRange>[5:5]</bitRange>
20976              <access>read-write</access>
20977            </field>
20978          </fields>
20979        </register>
20980        <register>
20981          <name>INTR_SET</name>
20982          <description>Interrupt set register</description>
20983          <addressOffset>0x7C4</addressOffset>
20984          <size>32</size>
20985          <access>read-write</access>
20986          <resetValue>0x0</resetValue>
20987          <resetMask>0x3F</resetMask>
20988          <fields>
20989            <field>
20990              <name>TR_TX_REQ</name>
20991              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
20992              <bitRange>[0:0]</bitRange>
20993              <access>read-write</access>
20994            </field>
20995            <field>
20996              <name>TR_RX_REQ</name>
20997              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
20998              <bitRange>[1:1]</bitRange>
20999              <access>read-write</access>
21000            </field>
21001            <field>
21002              <name>XIP_ALIGNMENT_ERROR</name>
21003              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
21004              <bitRange>[2:2]</bitRange>
21005              <access>read-write</access>
21006            </field>
21007            <field>
21008              <name>TX_CMD_FIFO_OVERFLOW</name>
21009              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
21010              <bitRange>[3:3]</bitRange>
21011              <access>read-write</access>
21012            </field>
21013            <field>
21014              <name>TX_DATA_FIFO_OVERFLOW</name>
21015              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
21016              <bitRange>[4:4]</bitRange>
21017              <access>read-write</access>
21018            </field>
21019            <field>
21020              <name>RX_DATA_FIFO_UNDERFLOW</name>
21021              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
21022              <bitRange>[5:5]</bitRange>
21023              <access>read-write</access>
21024            </field>
21025          </fields>
21026        </register>
21027        <register>
21028          <name>INTR_MASK</name>
21029          <description>Interrupt mask register</description>
21030          <addressOffset>0x7C8</addressOffset>
21031          <size>32</size>
21032          <access>read-write</access>
21033          <resetValue>0x0</resetValue>
21034          <resetMask>0x3F</resetMask>
21035          <fields>
21036            <field>
21037              <name>TR_TX_REQ</name>
21038              <description>Mask bit for corresponding bit in interrupt request register.</description>
21039              <bitRange>[0:0]</bitRange>
21040              <access>read-write</access>
21041            </field>
21042            <field>
21043              <name>TR_RX_REQ</name>
21044              <description>Mask bit for corresponding bit in interrupt request register.</description>
21045              <bitRange>[1:1]</bitRange>
21046              <access>read-write</access>
21047            </field>
21048            <field>
21049              <name>XIP_ALIGNMENT_ERROR</name>
21050              <description>Mask bit for corresponding bit in interrupt request register.</description>
21051              <bitRange>[2:2]</bitRange>
21052              <access>read-write</access>
21053            </field>
21054            <field>
21055              <name>TX_CMD_FIFO_OVERFLOW</name>
21056              <description>Mask bit for corresponding bit in interrupt request register.</description>
21057              <bitRange>[3:3]</bitRange>
21058              <access>read-write</access>
21059            </field>
21060            <field>
21061              <name>TX_DATA_FIFO_OVERFLOW</name>
21062              <description>Mask bit for corresponding bit in interrupt request register.</description>
21063              <bitRange>[4:4]</bitRange>
21064              <access>read-write</access>
21065            </field>
21066            <field>
21067              <name>RX_DATA_FIFO_UNDERFLOW</name>
21068              <description>Mask bit for corresponding bit in interrupt request register.</description>
21069              <bitRange>[5:5]</bitRange>
21070              <access>read-write</access>
21071            </field>
21072          </fields>
21073        </register>
21074        <register>
21075          <name>INTR_MASKED</name>
21076          <description>Interrupt masked register</description>
21077          <addressOffset>0x7CC</addressOffset>
21078          <size>32</size>
21079          <access>read-only</access>
21080          <resetValue>0x0</resetValue>
21081          <resetMask>0x3F</resetMask>
21082          <fields>
21083            <field>
21084              <name>TR_TX_REQ</name>
21085              <description>Logical and of corresponding request and mask bits.</description>
21086              <bitRange>[0:0]</bitRange>
21087              <access>read-only</access>
21088            </field>
21089            <field>
21090              <name>TR_RX_REQ</name>
21091              <description>Logical and of corresponding request and mask bits.</description>
21092              <bitRange>[1:1]</bitRange>
21093              <access>read-only</access>
21094            </field>
21095            <field>
21096              <name>XIP_ALIGNMENT_ERROR</name>
21097              <description>Logical and of corresponding request and mask bits.</description>
21098              <bitRange>[2:2]</bitRange>
21099              <access>read-only</access>
21100            </field>
21101            <field>
21102              <name>TX_CMD_FIFO_OVERFLOW</name>
21103              <description>Logical and of corresponding request and mask bits.</description>
21104              <bitRange>[3:3]</bitRange>
21105              <access>read-only</access>
21106            </field>
21107            <field>
21108              <name>TX_DATA_FIFO_OVERFLOW</name>
21109              <description>Logical and of corresponding request and mask bits.</description>
21110              <bitRange>[4:4]</bitRange>
21111              <access>read-only</access>
21112            </field>
21113            <field>
21114              <name>RX_DATA_FIFO_UNDERFLOW</name>
21115              <description>Logical and of corresponding request and mask bits.</description>
21116              <bitRange>[5:5]</bitRange>
21117              <access>read-only</access>
21118            </field>
21119          </fields>
21120        </register>
21121        <cluster>
21122          <dim>3</dim>
21123          <dimIncrement>128</dimIncrement>
21124          <name>DEVICE[%s]</name>
21125          <description>Device (only used in XIP mode)</description>
21126          <addressOffset>0x00000800</addressOffset>
21127          <register>
21128            <name>CTL</name>
21129            <description>Control</description>
21130            <addressOffset>0x0</addressOffset>
21131            <size>32</size>
21132            <access>read-write</access>
21133            <resetValue>0x0</resetValue>
21134            <resetMask>0x80030101</resetMask>
21135            <fields>
21136              <field>
21137                <name>WR_EN</name>
21138                <description>Write enable:
21139'0': write transfers are not allowed to this device. An attempt to write to this device results in an AHB-Lite bus error.
21140'1': write transfers are allowed to this device.</description>
21141                <bitRange>[0:0]</bitRange>
21142                <access>read-write</access>
21143              </field>
21144              <field>
21145                <name>CRYPTO_EN</name>
21146                <description>Cryptography on read/write accesses:
21147'0': disabled.
21148'1': enabled.</description>
21149                <bitRange>[8:8]</bitRange>
21150                <access>read-write</access>
21151              </field>
21152              <field>
21153                <name>DATA_SEL</name>
21154                <description>Specifies the connection of the IP's data lines (spi_data[0], ..., spi_data[7]) to the device's data lines (SI/IO0, SO/IO1, IO2, IO3, IO4, IO5, IO6, IO7):
21155'0': spi_data[0] = IO0, spi_data[1] = IO1, ..., spi_data[7] = IO7. This value is allowed for single, dual, quad, dual quad and octal SPI modes. This value must be used for the first device in dual quad SPI mode. This value must be used for octal SPI mode.
21156'1': spi_data[2] = IO0, spi_data[3] = IO1. This value is only allowed for single and dual SPI modes.
21157'2': spi_data[4] = IO0, spi_data[5] = IO1, ..., spi_data[7] = IO3. This value is only allowed for single, dual, quad and dual quad  SPI modes. In dual quad SPI mode, this value must be used for the second device.
21158'3': spi_data[6] = IO0, spi_data[7] = IO1. This value is only allowed for single and dual SPI modes.</description>
21159                <bitRange>[17:16]</bitRange>
21160                <access>read-write</access>
21161              </field>
21162              <field>
21163                <name>ENABLED</name>
21164                <description>Device enable:
21165'0': Disabled.
21166'1': Enabled.</description>
21167                <bitRange>[31:31]</bitRange>
21168                <access>read-write</access>
21169              </field>
21170            </fields>
21171          </register>
21172          <register>
21173            <name>ADDR</name>
21174            <description>Device region base address</description>
21175            <addressOffset>0x8</addressOffset>
21176            <size>32</size>
21177            <access>read-write</access>
21178            <resetValue>0x0</resetValue>
21179            <resetMask>0x0</resetMask>
21180            <fields>
21181              <field>
21182                <name>ADDR</name>
21183                <description>Specifies the base address of the device region. If the device region is 2^m Bytes, ADDR MUST be a multiple of 2^m.
21184
21185In dual quad SPI data transfer, the two devices should have the same ADDR and MASK register settings. The device control information (ADDR_CTL, RD_CMD_CTL, etc.) are provided by the MMIO control registers of the device with the lowest index.
21186
21187The most significant bit fields are constants and set based on the SMIF_XIP_ADDR parameter. The most significant bits are identified on the SMIF_XIP_MASK parameter. E.g., if SMIF_XIP_MASK is 0xff00:0000 (16 MB XIP memory region), ADDR[31:24] = SMIF_XIP_ADDR[31:24].</description>
21188                <bitRange>[31:8]</bitRange>
21189                <access>read-write</access>
21190              </field>
21191            </fields>
21192          </register>
21193          <register>
21194            <name>MASK</name>
21195            <description>Device region mask</description>
21196            <addressOffset>0xC</addressOffset>
21197            <size>32</size>
21198            <access>read-write</access>
21199            <resetValue>0x0</resetValue>
21200            <resetMask>0x0</resetMask>
21201            <fields>
21202              <field>
21203                <name>MASK</name>
21204                <description>Specifies the size of the device region. All '1' bits are used to compare the incoming transfer request address A[31:0] with the address as specified in ADDR.ADDR: Address A is in the device when (A[31:8] &amp; MASK[31:8]) == ADDR.ADDR[31:8].
21205
21206The most significant bit fields are constants and set to'1'. The most significant bits are identified on the SMIF_XIP_MASK parameter. E.g., if SMIF_XIP_MASK  is 0xff00:0000 (16 MB XIP memory region), MASK[31:24] = 0xff.
21207
21208Note: a transfer request that is not in any device region results in an AHB-Lite bus error.</description>
21209                <bitRange>[31:8]</bitRange>
21210                <access>read-write</access>
21211              </field>
21212            </fields>
21213          </register>
21214          <register>
21215            <name>ADDR_CTL</name>
21216            <description>Address control</description>
21217            <addressOffset>0x20</addressOffset>
21218            <size>32</size>
21219            <access>read-write</access>
21220            <resetValue>0x0</resetValue>
21221            <resetMask>0x103</resetMask>
21222            <fields>
21223              <field>
21224                <name>SIZE2</name>
21225                <description>Specifies the size of the XIP device address in Bytes:
21226'0': 1 Byte address.
21227'1': 2 Byte address.
21228'2': 3 Byte address.
21229'3': 4 Byte address.
21230The lower significant address Bytes of the transfer request are used as XIP address to the external device. Note that for dual quad SPI data transfer, the transfer request address is divided by 2. Therefore, the transfer request address needs to be a multiple of 2. If the trasnfer requestaddress is NOT a multiple of 2, the XIP_ALIGNMENT_ERROR interrupt cause is activated.</description>
21231                <bitRange>[1:0]</bitRange>
21232                <access>read-write</access>
21233              </field>
21234              <field>
21235                <name>DIV2</name>
21236                <description>Specifies if the AHB-Lite bus transfer address is divided by 2 or not:
21237'0': No divide by 2.
21238'1': Divide by 2.
21239
21240This functionality is used for read and write operation in XIP, dual quad SPI mode; i.e. this DIV2 must be set to '1' in dual quad SPI mode. If the transfer request address is NOT a multiple of 2 or the requested number of Bytes is not a multiple of 2, the XIP_ALIGNMENT_ERROR interrupt cause is activated.</description>
21241                <bitRange>[8:8]</bitRange>
21242                <access>read-write</access>
21243              </field>
21244            </fields>
21245          </register>
21246          <register>
21247            <name>RD_CMD_CTL</name>
21248            <description>Read command control</description>
21249            <addressOffset>0x40</addressOffset>
21250            <size>32</size>
21251            <access>read-write</access>
21252            <resetValue>0x0</resetValue>
21253            <resetMask>0x800300FF</resetMask>
21254            <fields>
21255              <field>
21256                <name>CODE</name>
21257                <description>Command byte code.</description>
21258                <bitRange>[7:0]</bitRange>
21259                <access>read-write</access>
21260              </field>
21261              <field>
21262                <name>WIDTH</name>
21263                <description>Width of data transfer:
21264'0': 1 bit/cycle (single data transfer).
21265'1': 2 bits/cycle (dual data transfer).
21266'2': 4 bits/cycle (quad data transfer).
21267'3': 8 bits/cycle (octal data transfer).</description>
21268                <bitRange>[17:16]</bitRange>
21269                <access>read-write</access>
21270              </field>
21271              <field>
21272                <name>PRESENT</name>
21273                <description>Presence of command field:
21274'0': not present
21275'1': present</description>
21276                <bitRange>[31:31]</bitRange>
21277                <access>read-write</access>
21278              </field>
21279            </fields>
21280          </register>
21281          <register>
21282            <name>RD_ADDR_CTL</name>
21283            <description>Read address control</description>
21284            <addressOffset>0x44</addressOffset>
21285            <size>32</size>
21286            <access>read-write</access>
21287            <resetValue>0x0</resetValue>
21288            <resetMask>0x30000</resetMask>
21289            <fields>
21290              <field>
21291                <name>WIDTH</name>
21292                <description>Width of transfer.</description>
21293                <bitRange>[17:16]</bitRange>
21294                <access>read-write</access>
21295              </field>
21296            </fields>
21297          </register>
21298          <register>
21299            <name>RD_MODE_CTL</name>
21300            <description>Read mode control</description>
21301            <addressOffset>0x48</addressOffset>
21302            <size>32</size>
21303            <access>read-write</access>
21304            <resetValue>0x0</resetValue>
21305            <resetMask>0x800300FF</resetMask>
21306            <fields>
21307              <field>
21308                <name>CODE</name>
21309                <description>Mode byte code.</description>
21310                <bitRange>[7:0]</bitRange>
21311                <access>read-write</access>
21312              </field>
21313              <field>
21314                <name>WIDTH</name>
21315                <description>Width of transfer.</description>
21316                <bitRange>[17:16]</bitRange>
21317                <access>read-write</access>
21318              </field>
21319              <field>
21320                <name>PRESENT</name>
21321                <description>Presence of mode field:
21322'0': not present
21323'1': present</description>
21324                <bitRange>[31:31]</bitRange>
21325                <access>read-write</access>
21326              </field>
21327            </fields>
21328          </register>
21329          <register>
21330            <name>RD_DUMMY_CTL</name>
21331            <description>Read dummy control</description>
21332            <addressOffset>0x4C</addressOffset>
21333            <size>32</size>
21334            <access>read-write</access>
21335            <resetValue>0x0</resetValue>
21336            <resetMask>0x8000001F</resetMask>
21337            <fields>
21338              <field>
21339                <name>SIZE5</name>
21340                <description>Number of dummy cycles (minus 1):
21341'0': 1 cycles
21342...
21343'31': 32 cycles.
21344
21345Note: this field specifies dummy cycles, not dummy Bytes!</description>
21346                <bitRange>[4:0]</bitRange>
21347                <access>read-write</access>
21348              </field>
21349              <field>
21350                <name>PRESENT</name>
21351                <description>Presence of dummy cycles:
21352'0': not present
21353'1': present</description>
21354                <bitRange>[31:31]</bitRange>
21355                <access>read-write</access>
21356              </field>
21357            </fields>
21358          </register>
21359          <register>
21360            <name>RD_DATA_CTL</name>
21361            <description>Read data control</description>
21362            <addressOffset>0x50</addressOffset>
21363            <size>32</size>
21364            <access>read-write</access>
21365            <resetValue>0x0</resetValue>
21366            <resetMask>0x30000</resetMask>
21367            <fields>
21368              <field>
21369                <name>WIDTH</name>
21370                <description>Width of transfer.</description>
21371                <bitRange>[17:16]</bitRange>
21372                <access>read-write</access>
21373              </field>
21374            </fields>
21375          </register>
21376          <register>
21377            <name>WR_CMD_CTL</name>
21378            <description>Write command control</description>
21379            <addressOffset>0x60</addressOffset>
21380            <size>32</size>
21381            <access>read-write</access>
21382            <resetValue>0x0</resetValue>
21383            <resetMask>0x800300FF</resetMask>
21384            <fields>
21385              <field>
21386                <name>CODE</name>
21387                <description>Command byte code.</description>
21388                <bitRange>[7:0]</bitRange>
21389                <access>read-write</access>
21390              </field>
21391              <field>
21392                <name>WIDTH</name>
21393                <description>Width of transfer.</description>
21394                <bitRange>[17:16]</bitRange>
21395                <access>read-write</access>
21396              </field>
21397              <field>
21398                <name>PRESENT</name>
21399                <description>Presence of command field:
21400'0': not present
21401'1': present</description>
21402                <bitRange>[31:31]</bitRange>
21403                <access>read-write</access>
21404              </field>
21405            </fields>
21406          </register>
21407          <register>
21408            <name>WR_ADDR_CTL</name>
21409            <description>Write address control</description>
21410            <addressOffset>0x64</addressOffset>
21411            <size>32</size>
21412            <access>read-write</access>
21413            <resetValue>0x0</resetValue>
21414            <resetMask>0x30000</resetMask>
21415            <fields>
21416              <field>
21417                <name>WIDTH</name>
21418                <description>Width of transfer.</description>
21419                <bitRange>[17:16]</bitRange>
21420                <access>read-write</access>
21421              </field>
21422            </fields>
21423          </register>
21424          <register>
21425            <name>WR_MODE_CTL</name>
21426            <description>Write mode control</description>
21427            <addressOffset>0x68</addressOffset>
21428            <size>32</size>
21429            <access>read-write</access>
21430            <resetValue>0x0</resetValue>
21431            <resetMask>0x800300FF</resetMask>
21432            <fields>
21433              <field>
21434                <name>CODE</name>
21435                <description>Mode byte code.</description>
21436                <bitRange>[7:0]</bitRange>
21437                <access>read-write</access>
21438              </field>
21439              <field>
21440                <name>WIDTH</name>
21441                <description>Width of transfer.</description>
21442                <bitRange>[17:16]</bitRange>
21443                <access>read-write</access>
21444              </field>
21445              <field>
21446                <name>PRESENT</name>
21447                <description>Presence of mode field:
21448'0': not present
21449'1': present</description>
21450                <bitRange>[31:31]</bitRange>
21451                <access>read-write</access>
21452              </field>
21453            </fields>
21454          </register>
21455          <register>
21456            <name>WR_DUMMY_CTL</name>
21457            <description>Write dummy control</description>
21458            <addressOffset>0x6C</addressOffset>
21459            <size>32</size>
21460            <access>read-write</access>
21461            <resetValue>0x0</resetValue>
21462            <resetMask>0x8000001F</resetMask>
21463            <fields>
21464              <field>
21465                <name>SIZE5</name>
21466                <description>Number of dummy cycles (minus 1):
21467'0': 1 cycles
21468...
21469'31': 32 cycles.</description>
21470                <bitRange>[4:0]</bitRange>
21471                <access>read-write</access>
21472              </field>
21473              <field>
21474                <name>PRESENT</name>
21475                <description>Presence of dummy cycles:
21476'0': not present
21477'1': present</description>
21478                <bitRange>[31:31]</bitRange>
21479                <access>read-write</access>
21480              </field>
21481            </fields>
21482          </register>
21483          <register>
21484            <name>WR_DATA_CTL</name>
21485            <description>Write data control</description>
21486            <addressOffset>0x70</addressOffset>
21487            <size>32</size>
21488            <access>read-write</access>
21489            <resetValue>0x0</resetValue>
21490            <resetMask>0x30000</resetMask>
21491            <fields>
21492              <field>
21493                <name>WIDTH</name>
21494                <description>Width of transfer.</description>
21495                <bitRange>[17:16]</bitRange>
21496                <access>read-write</access>
21497              </field>
21498            </fields>
21499          </register>
21500        </cluster>
21501      </registers>
21502    </peripheral>
21503    <peripheral>
21504      <name>USBFS0</name>
21505      <description>USB Host and Device Controller</description>
21506      <headerStructName>USBFS</headerStructName>
21507      <baseAddress>0x40420000</baseAddress>
21508      <addressBlock>
21509        <offset>0</offset>
21510        <size>65536</size>
21511        <usage>registers</usage>
21512      </addressBlock>
21513      <registers>
21514        <cluster>
21515          <name>USBDEV</name>
21516          <description>USB Device</description>
21517          <addressOffset>0x00000000</addressOffset>
21518          <register>
21519            <dim>8</dim>
21520            <dimIncrement>4</dimIncrement>
21521            <name>EP0_DR[%s]</name>
21522            <description>Control End point EP0 Data Register</description>
21523            <addressOffset>0x0</addressOffset>
21524            <size>32</size>
21525            <access>read-write</access>
21526            <resetValue>0x0</resetValue>
21527            <resetMask>0xFF</resetMask>
21528            <fields>
21529              <field>
21530                <name>DATA_BYTE</name>
21531                <description>This register is shared for both transmit and receive. The count in the EP0_CNT register determines the number of bytes received or to be transferred.</description>
21532                <bitRange>[7:0]</bitRange>
21533                <access>read-write</access>
21534              </field>
21535            </fields>
21536          </register>
21537          <register>
21538            <name>CR0</name>
21539            <description>USB control 0 Register</description>
21540            <addressOffset>0x20</addressOffset>
21541            <size>32</size>
21542            <access>read-write</access>
21543            <resetValue>0x0</resetValue>
21544            <resetMask>0xFF</resetMask>
21545            <fields>
21546              <field>
21547                <name>DEVICE_ADDRESS</name>
21548                <description>These bits specify the USB device address to which the SIE will respond. This address must be set by firmware and is specified by the USB Host with a SET ADDRESS command during USB enumeration. This value must be programmed by firmware when assigned during enumeration. It is not set automatically by the hardware.
21549If USB bus reset is detected, these bits are initialized.</description>
21550                <bitRange>[6:0]</bitRange>
21551                <access>read-write</access>
21552              </field>
21553              <field>
21554                <name>USB_ENABLE</name>
21555                <description>This bit enables the device to respond to USB traffic.
21556If USB bus reset is detected, this bit is cleared.
21557Note:
21558When USB PHY is GPIO mode(USBIO_CR1.IOMODE=0), USB bus reset is detected. Therefore, when USB PHY is GPIO mode, this bit is cleared even if this bit is set to 1. If this bit is set to 1, write this bit upon USB bus reset interrupt, and do not write to this bit during initialization steps.</description>
21559                <bitRange>[7:7]</bitRange>
21560                <access>read-write</access>
21561              </field>
21562            </fields>
21563          </register>
21564          <register>
21565            <name>CR1</name>
21566            <description>USB control 1 Register</description>
21567            <addressOffset>0x24</addressOffset>
21568            <size>32</size>
21569            <access>read-write</access>
21570            <resetValue>0x0</resetValue>
21571            <resetMask>0xF</resetMask>
21572            <fields>
21573              <field>
21574                <name>REG_ENABLE</name>
21575                <description>This bit controls the operation of the internal USB regulator. For applications with supply voltages in the 5V range this bit is set high to enable the internal regulator. For device supply voltage in the 3.3V range this bit is cleared to connect the transceiver directly to the supply.</description>
21576                <bitRange>[0:0]</bitRange>
21577                <access>read-write</access>
21578              </field>
21579              <field>
21580                <name>ENABLE_LOCK</name>
21581                <description>This bit is set to turn on the automatic frequency locking of the internal oscillator to USB traffic.  Unless an external clock is being provided this bit should remain set for proper USB operation.</description>
21582                <bitRange>[1:1]</bitRange>
21583                <access>read-write</access>
21584              </field>
21585              <field>
21586                <name>BUS_ACTIVITY</name>
21587                <description>The Bus Activity bit is a stickybit that detects any non-idle USB event that has occurred on the USB bus. Once set to High by the SIE to indicate the bus activity this bit retains its logical High
21588value until firmware clears it.</description>
21589                <bitRange>[2:2]</bitRange>
21590                <access>read-write</access>
21591              </field>
21592              <field>
21593                <name>RSVD_3</name>
21594                <description>N/A</description>
21595                <bitRange>[3:3]</bitRange>
21596                <access>read-write</access>
21597              </field>
21598            </fields>
21599          </register>
21600          <register>
21601            <name>SIE_EP_INT_EN</name>
21602            <description>USB SIE Data Endpoints Interrupt Enable Register</description>
21603            <addressOffset>0x28</addressOffset>
21604            <size>32</size>
21605            <access>read-write</access>
21606            <resetValue>0x0</resetValue>
21607            <resetMask>0xFF</resetMask>
21608            <fields>
21609              <field>
21610                <name>EP1_INTR_EN</name>
21611                <description>Enables interrupt for EP1</description>
21612                <bitRange>[0:0]</bitRange>
21613                <access>read-write</access>
21614              </field>
21615              <field>
21616                <name>EP2_INTR_EN</name>
21617                <description>Enables interrupt for EP2</description>
21618                <bitRange>[1:1]</bitRange>
21619                <access>read-write</access>
21620              </field>
21621              <field>
21622                <name>EP3_INTR_EN</name>
21623                <description>Enables interrupt for EP3</description>
21624                <bitRange>[2:2]</bitRange>
21625                <access>read-write</access>
21626              </field>
21627              <field>
21628                <name>EP4_INTR_EN</name>
21629                <description>Enables interrupt for EP4</description>
21630                <bitRange>[3:3]</bitRange>
21631                <access>read-write</access>
21632              </field>
21633              <field>
21634                <name>EP5_INTR_EN</name>
21635                <description>Enables interrupt for EP5</description>
21636                <bitRange>[4:4]</bitRange>
21637                <access>read-write</access>
21638              </field>
21639              <field>
21640                <name>EP6_INTR_EN</name>
21641                <description>Enables interrupt for EP6</description>
21642                <bitRange>[5:5]</bitRange>
21643                <access>read-write</access>
21644              </field>
21645              <field>
21646                <name>EP7_INTR_EN</name>
21647                <description>Enables interrupt for EP7</description>
21648                <bitRange>[6:6]</bitRange>
21649                <access>read-write</access>
21650              </field>
21651              <field>
21652                <name>EP8_INTR_EN</name>
21653                <description>Enables interrupt for EP8</description>
21654                <bitRange>[7:7]</bitRange>
21655                <access>read-write</access>
21656              </field>
21657            </fields>
21658          </register>
21659          <register>
21660            <name>SIE_EP_INT_SR</name>
21661            <description>USB SIE Data Endpoint Interrupt Status</description>
21662            <addressOffset>0x2C</addressOffset>
21663            <size>32</size>
21664            <access>read-write</access>
21665            <resetValue>0x0</resetValue>
21666            <resetMask>0xFF</resetMask>
21667            <fields>
21668              <field>
21669                <name>EP1_INTR</name>
21670                <description>Interrupt status for EP1</description>
21671                <bitRange>[0:0]</bitRange>
21672                <access>read-write</access>
21673              </field>
21674              <field>
21675                <name>EP2_INTR</name>
21676                <description>Interrupt status for EP2</description>
21677                <bitRange>[1:1]</bitRange>
21678                <access>read-write</access>
21679              </field>
21680              <field>
21681                <name>EP3_INTR</name>
21682                <description>Interrupt status for EP3</description>
21683                <bitRange>[2:2]</bitRange>
21684                <access>read-write</access>
21685              </field>
21686              <field>
21687                <name>EP4_INTR</name>
21688                <description>Interrupt status for EP4</description>
21689                <bitRange>[3:3]</bitRange>
21690                <access>read-write</access>
21691              </field>
21692              <field>
21693                <name>EP5_INTR</name>
21694                <description>Interrupt status for EP5</description>
21695                <bitRange>[4:4]</bitRange>
21696                <access>read-write</access>
21697              </field>
21698              <field>
21699                <name>EP6_INTR</name>
21700                <description>Interrupt status for EP6</description>
21701                <bitRange>[5:5]</bitRange>
21702                <access>read-write</access>
21703              </field>
21704              <field>
21705                <name>EP7_INTR</name>
21706                <description>Interrupt status for EP7</description>
21707                <bitRange>[6:6]</bitRange>
21708                <access>read-write</access>
21709              </field>
21710              <field>
21711                <name>EP8_INTR</name>
21712                <description>Interrupt status for EP8</description>
21713                <bitRange>[7:7]</bitRange>
21714                <access>read-write</access>
21715              </field>
21716            </fields>
21717          </register>
21718          <register>
21719            <name>SIE_EP1_CNT0</name>
21720            <description>Non-control endpoint count register</description>
21721            <addressOffset>0x30</addressOffset>
21722            <size>32</size>
21723            <access>read-write</access>
21724            <resetValue>0x0</resetValue>
21725            <resetMask>0xC7</resetMask>
21726            <fields>
21727              <field>
21728                <name>DATA_COUNT_MSB</name>
21729                <description>These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information.</description>
21730                <bitRange>[2:0]</bitRange>
21731                <access>read-write</access>
21732              </field>
21733              <field>
21734                <name>DATA_VALID</name>
21735                <description>This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings.</description>
21736                <bitRange>[6:6]</bitRange>
21737                <access>read-write</access>
21738                <enumeratedValues>
21739                  <enumeratedValue>
21740                    <name>DATA_ERROR</name>
21741                    <description>No ACK'd transactions since bit was last cleared.</description>
21742                    <value>0</value>
21743                  </enumeratedValue>
21744                  <enumeratedValue>
21745                    <name>DATA_VALID</name>
21746                    <description>Indicates a transaction ended with an ACK.</description>
21747                    <value>1</value>
21748                  </enumeratedValue>
21749                </enumeratedValues>
21750              </field>
21751              <field>
21752                <name>DATA_TOGGLE</name>
21753                <description>This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit.</description>
21754                <bitRange>[7:7]</bitRange>
21755                <access>read-write</access>
21756              </field>
21757            </fields>
21758          </register>
21759          <register>
21760            <name>SIE_EP1_CNT1</name>
21761            <description>Non-control endpoint count register</description>
21762            <addressOffset>0x34</addressOffset>
21763            <size>32</size>
21764            <access>read-write</access>
21765            <resetValue>0x0</resetValue>
21766            <resetMask>0xFF</resetMask>
21767            <fields>
21768              <field>
21769                <name>DATA_COUNT</name>
21770                <description>These bits are the 8 LSb of a 11-bit counter.  The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction.</description>
21771                <bitRange>[7:0]</bitRange>
21772                <access>read-write</access>
21773              </field>
21774            </fields>
21775          </register>
21776          <register>
21777            <name>SIE_EP1_CR0</name>
21778            <description>Non-control endpoint's control Register</description>
21779            <addressOffset>0x38</addressOffset>
21780            <size>32</size>
21781            <access>read-write</access>
21782            <resetValue>0x0</resetValue>
21783            <resetMask>0xFF</resetMask>
21784            <fields>
21785              <field>
21786                <name>MODE</name>
21787                <description>The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint.</description>
21788                <bitRange>[3:0]</bitRange>
21789                <access>read-write</access>
21790                <enumeratedValues>
21791                  <enumeratedValue>
21792                    <name>DISABLE</name>
21793                    <description>Ignore all USB traffic to this endpoint</description>
21794                    <value>0</value>
21795                  </enumeratedValue>
21796                  <enumeratedValue>
21797                    <name>NAK_INOUT</name>
21798                    <description>SETUP: Accept
21799IN: NAK
21800OUT:  NAK</description>
21801                    <value>1</value>
21802                  </enumeratedValue>
21803                  <enumeratedValue>
21804                    <name>STATUS_OUT_ONLY</name>
21805                    <description>SETUP: Accept
21806IN: STALL
21807OUT:  ACK 0B tokens, NAK others</description>
21808                    <value>2</value>
21809                  </enumeratedValue>
21810                  <enumeratedValue>
21811                    <name>STALL_INOUT</name>
21812                    <description>SETUP: Accept
21813IN: STALL
21814OUT:  STALL</description>
21815                    <value>3</value>
21816                  </enumeratedValue>
21817                  <enumeratedValue>
21818                    <name>ISO_OUT</name>
21819                    <description>SETUP: Ignore
21820IN: Ignore
21821OUT:  Accept Isochronous OUT token</description>
21822                    <value>5</value>
21823                  </enumeratedValue>
21824                  <enumeratedValue>
21825                    <name>STATUS_IN_ONLY</name>
21826                    <description>SETUP: Accept
21827IN: Respond with 0B data
21828OUT:  Stall</description>
21829                    <value>6</value>
21830                  </enumeratedValue>
21831                  <enumeratedValue>
21832                    <name>ISO_IN</name>
21833                    <description>SETUP: Ignore
21834IN: Accept Isochronous IN token
21835OUT:  Ignore</description>
21836                    <value>7</value>
21837                  </enumeratedValue>
21838                  <enumeratedValue>
21839                    <name>NAK_OUT</name>
21840                    <description>SETUP: Ignore
21841IN: Ignore
21842OUT:  NAK</description>
21843                    <value>8</value>
21844                  </enumeratedValue>
21845                  <enumeratedValue>
21846                    <name>ACK_OUT</name>
21847                    <description>SETUP: Ignore
21848IN: Ignore
21849OUT:  Accept data and ACK if STALL=0, STALL otherwise.
21850Change to MODE=8 after one succesfull OUT token.</description>
21851                    <value>9</value>
21852                  </enumeratedValue>
21853                  <enumeratedValue>
21854                    <name>ACK_OUT_STATUS_IN</name>
21855                    <description>SETUP: Accept
21856IN: Respond with 0B data
21857OUT:  Accept data</description>
21858                    <value>11</value>
21859                  </enumeratedValue>
21860                  <enumeratedValue>
21861                    <name>NAK_IN</name>
21862                    <description>SETUP: Ignore
21863IN: NAK
21864OUT:  Ignore</description>
21865                    <value>12</value>
21866                  </enumeratedValue>
21867                  <enumeratedValue>
21868                    <name>ACK_IN</name>
21869                    <description>SETUP: Ignore
21870IN: Respond to IN with data if STALL=0, STALL otherwise
21871OUT:  Ignore</description>
21872                    <value>13</value>
21873                  </enumeratedValue>
21874                  <enumeratedValue>
21875                    <name>ACK_IN_STATUS_OUT</name>
21876                    <description>SETUP: Accept
21877IN: Respond to IN with data
21878OUT:  ACK 0B tokens, NAK others</description>
21879                    <value>15</value>
21880                  </enumeratedValue>
21881                </enumeratedValues>
21882              </field>
21883              <field>
21884                <name>ACKED_TXN</name>
21885                <description>The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register.</description>
21886                <bitRange>[4:4]</bitRange>
21887                <access>read-write</access>
21888                <enumeratedValues>
21889                  <enumeratedValue>
21890                    <name>ACKED_NO</name>
21891                    <description>No ACK'd transactions since bit was last cleared.</description>
21892                    <value>0</value>
21893                  </enumeratedValue>
21894                  <enumeratedValue>
21895                    <name>ACKED_YES</name>
21896                    <description>Indicates a transaction ended with an ACK.</description>
21897                    <value>1</value>
21898                  </enumeratedValue>
21899                </enumeratedValues>
21900              </field>
21901              <field>
21902                <name>NAK_INT_EN</name>
21903                <description>When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK.</description>
21904                <bitRange>[5:5]</bitRange>
21905                <access>read-write</access>
21906              </field>
21907              <field>
21908                <name>ERR_IN_TXN</name>
21909                <description>The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID
21910error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register.</description>
21911                <bitRange>[6:6]</bitRange>
21912                <access>read-write</access>
21913              </field>
21914              <field>
21915                <name>STALL</name>
21916                <description>When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes.</description>
21917                <bitRange>[7:7]</bitRange>
21918                <access>read-write</access>
21919              </field>
21920            </fields>
21921          </register>
21922          <register>
21923            <name>USBIO_CR0</name>
21924            <description>USBIO Control 0 Register</description>
21925            <addressOffset>0x40</addressOffset>
21926            <size>32</size>
21927            <access>read-write</access>
21928            <resetValue>0x0</resetValue>
21929            <resetMask>0xE0</resetMask>
21930            <fields>
21931              <field>
21932                <name>RD</name>
21933                <description>Received Data. This read only bit gives the state of the USB differential receiver when IOMODE bit is '0'  and USB doesn't transmit. This bit is valid if USB Device.
21934If D+=D- (SE0), this value is undefined.</description>
21935                <bitRange>[0:0]</bitRange>
21936                <access>read-only</access>
21937                <enumeratedValues>
21938                  <enumeratedValue>
21939                    <name>DIFF_LOW</name>
21940                    <description>D+ &lt; D- (K state)</description>
21941                    <value>0</value>
21942                  </enumeratedValue>
21943                  <enumeratedValue>
21944                    <name>DIFF_HIGH</name>
21945                    <description>D+ &gt; D- (J state)</description>
21946                    <value>1</value>
21947                  </enumeratedValue>
21948                </enumeratedValues>
21949              </field>
21950              <field>
21951                <name>TD</name>
21952                <description>Transmit Data. Transmit a USB J or K state on the USB bus. No effect if TEN=0 or TSE0=1.</description>
21953                <bitRange>[5:5]</bitRange>
21954                <access>read-write</access>
21955                <enumeratedValues>
21956                  <enumeratedValue>
21957                    <name>DIFF_K</name>
21958                    <description>Force USB K state (D+ is low D- is high).</description>
21959                    <value>0</value>
21960                  </enumeratedValue>
21961                  <enumeratedValue>
21962                    <name>DIFF_J</name>
21963                    <description>Force USB J state (D+ is high D- is low).</description>
21964                    <value>1</value>
21965                  </enumeratedValue>
21966                </enumeratedValues>
21967              </field>
21968              <field>
21969                <name>TSE0</name>
21970                <description>Transmit Single-Ended Zero. SE0: both D+ and D- low. No effect if TEN=0.</description>
21971                <bitRange>[6:6]</bitRange>
21972                <access>read-write</access>
21973              </field>
21974              <field>
21975                <name>TEN</name>
21976                <description>USB Transmit Enable. This is used to manually transmit on the D+ and D- pins. Normally this bit should be cleared to allow the internal SIE to drive the pins. The most common reason for manually
21977transmitting is to force a resume state on the bus.</description>
21978                <bitRange>[7:7]</bitRange>
21979                <access>read-write</access>
21980              </field>
21981            </fields>
21982          </register>
21983          <register>
21984            <name>USBIO_CR2</name>
21985            <description>USBIO control 2 Register</description>
21986            <addressOffset>0x44</addressOffset>
21987            <size>32</size>
21988            <access>read-write</access>
21989            <resetValue>0x0</resetValue>
21990            <resetMask>0xFF</resetMask>
21991            <fields>
21992              <field>
21993                <name>RSVD_5_0</name>
21994                <description>N/A</description>
21995                <bitRange>[5:0]</bitRange>
21996                <access>read-only</access>
21997              </field>
21998              <field>
21999                <name>TEST_PKT</name>
22000                <description>This bit enables the device to transmit a packet in response to an internally generated IN packet.  When set, one packet will be generated.</description>
22001                <bitRange>[6:6]</bitRange>
22002                <access>read-write</access>
22003              </field>
22004              <field>
22005                <name>RSVD_7</name>
22006                <description>N/A</description>
22007                <bitRange>[7:7]</bitRange>
22008                <access>read-write</access>
22009              </field>
22010            </fields>
22011          </register>
22012          <register>
22013            <name>USBIO_CR1</name>
22014            <description>USBIO control 1 Register</description>
22015            <addressOffset>0x48</addressOffset>
22016            <size>32</size>
22017            <access>read-write</access>
22018            <resetValue>0x20</resetValue>
22019            <resetMask>0x20</resetMask>
22020            <fields>
22021              <field>
22022                <name>DMO</name>
22023                <description>This read only bit gives the state of the D- pin when IOMODE bit is '0'  and USB doesn't transmit.
22024This bit is '0' when USB transmits SE0, and this bit is '1' when USB transmits other than SE0.
22025This bit is valid if USB Device.</description>
22026                <bitRange>[0:0]</bitRange>
22027                <access>read-only</access>
22028              </field>
22029              <field>
22030                <name>DPO</name>
22031                <description>This read only bit gives the state of the D+ pin when IOMODE bit is '0' and USB doesn't transmit.
22032This bit displays the output value of D+ pin when USB transmits SE0 or data.
22033This bit is valid if USB Device.</description>
22034                <bitRange>[1:1]</bitRange>
22035                <access>read-only</access>
22036              </field>
22037              <field>
22038                <name>RSVD_2</name>
22039                <description>N/A</description>
22040                <bitRange>[2:2]</bitRange>
22041                <access>read-write</access>
22042              </field>
22043              <field>
22044                <name>IOMODE</name>
22045                <description>This bit allows the D+ and D- pins to be configured for either USB mode or bit-banged modes. If this bit is set the DMI and DPI bits are used to drive the D- and D+ pins.</description>
22046                <bitRange>[5:5]</bitRange>
22047                <access>read-write</access>
22048              </field>
22049            </fields>
22050          </register>
22051          <register>
22052            <name>DYN_RECONFIG</name>
22053            <description>USB Dynamic reconfiguration register</description>
22054            <addressOffset>0x50</addressOffset>
22055            <size>32</size>
22056            <access>read-write</access>
22057            <resetValue>0x0</resetValue>
22058            <resetMask>0x1F</resetMask>
22059            <fields>
22060              <field>
22061                <name>DYN_CONFIG_EN</name>
22062                <description>This bit is used to enable the dynamic re-configuration for the selected EP. If set to 1, indicates the reconfiguration required for selected EP.
22063Use 0 for EP1, 1 for EP2, etc.</description>
22064                <bitRange>[0:0]</bitRange>
22065                <access>read-write</access>
22066              </field>
22067              <field>
22068                <name>DYN_RECONFIG_EPNO</name>
22069                <description>These bits indicates the EP number for which reconfiguration is required when dyn_config_en bit is set to 1.</description>
22070                <bitRange>[3:1]</bitRange>
22071                <access>read-write</access>
22072              </field>
22073              <field>
22074                <name>DYN_RECONFIG_RDY_STS</name>
22075                <description>This bit indicates the ready status for the dynamic reconfiguration, when set to 1, indicates the block is ready for reconfiguration.</description>
22076                <bitRange>[4:4]</bitRange>
22077                <access>read-only</access>
22078              </field>
22079            </fields>
22080          </register>
22081          <register>
22082            <name>SOF0</name>
22083            <description>Start Of Frame Register</description>
22084            <addressOffset>0x60</addressOffset>
22085            <size>32</size>
22086            <access>read-only</access>
22087            <resetValue>0x0</resetValue>
22088            <resetMask>0xFF</resetMask>
22089            <fields>
22090              <field>
22091                <name>FRAME_NUMBER</name>
22092                <description>It has the lower 8 bits [7:0] of the SOF frame number.</description>
22093                <bitRange>[7:0]</bitRange>
22094                <access>read-only</access>
22095              </field>
22096            </fields>
22097          </register>
22098          <register>
22099            <name>SOF1</name>
22100            <description>Start Of Frame Register</description>
22101            <addressOffset>0x64</addressOffset>
22102            <size>32</size>
22103            <access>read-only</access>
22104            <resetValue>0x0</resetValue>
22105            <resetMask>0x7</resetMask>
22106            <fields>
22107              <field>
22108                <name>FRAME_NUMBER_MSB</name>
22109                <description>It has the upper 3 bits [10:8] of the SOF frame number.</description>
22110                <bitRange>[2:0]</bitRange>
22111                <access>read-only</access>
22112              </field>
22113            </fields>
22114          </register>
22115          <register>
22116            <name>SIE_EP2_CNT0</name>
22117            <description>Non-control endpoint count register</description>
22118            <addressOffset>0x70</addressOffset>
22119            <size>32</size>
22120            <access>read-write</access>
22121            <resetValue>0x0</resetValue>
22122            <resetMask>0xC7</resetMask>
22123            <fields>
22124              <field>
22125                <name>DATA_COUNT_MSB</name>
22126                <description>These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information.</description>
22127                <bitRange>[2:0]</bitRange>
22128                <access>read-write</access>
22129              </field>
22130              <field>
22131                <name>DATA_VALID</name>
22132                <description>This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings.</description>
22133                <bitRange>[6:6]</bitRange>
22134                <access>read-write</access>
22135                <enumeratedValues>
22136                  <enumeratedValue>
22137                    <name>DATA_ERROR</name>
22138                    <description>No ACK'd transactions since bit was last cleared.</description>
22139                    <value>0</value>
22140                  </enumeratedValue>
22141                  <enumeratedValue>
22142                    <name>DATA_VALID</name>
22143                    <description>Indicates a transaction ended with an ACK.</description>
22144                    <value>1</value>
22145                  </enumeratedValue>
22146                </enumeratedValues>
22147              </field>
22148              <field>
22149                <name>DATA_TOGGLE</name>
22150                <description>This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit.</description>
22151                <bitRange>[7:7]</bitRange>
22152                <access>read-write</access>
22153              </field>
22154            </fields>
22155          </register>
22156          <register>
22157            <name>SIE_EP2_CNT1</name>
22158            <description>Non-control endpoint count register</description>
22159            <addressOffset>0x74</addressOffset>
22160            <size>32</size>
22161            <access>read-write</access>
22162            <resetValue>0x0</resetValue>
22163            <resetMask>0xFF</resetMask>
22164            <fields>
22165              <field>
22166                <name>DATA_COUNT</name>
22167                <description>These bits are the 8 LSb of a 11-bit counter.  The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction.</description>
22168                <bitRange>[7:0]</bitRange>
22169                <access>read-write</access>
22170              </field>
22171            </fields>
22172          </register>
22173          <register>
22174            <name>SIE_EP2_CR0</name>
22175            <description>Non-control endpoint's control Register</description>
22176            <addressOffset>0x78</addressOffset>
22177            <size>32</size>
22178            <access>read-write</access>
22179            <resetValue>0x0</resetValue>
22180            <resetMask>0xFF</resetMask>
22181            <fields>
22182              <field>
22183                <name>MODE</name>
22184                <description>The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint.</description>
22185                <bitRange>[3:0]</bitRange>
22186                <access>read-write</access>
22187                <enumeratedValues>
22188                  <enumeratedValue>
22189                    <name>DISABLE</name>
22190                    <description>Ignore all USB traffic to this endpoint</description>
22191                    <value>0</value>
22192                  </enumeratedValue>
22193                  <enumeratedValue>
22194                    <name>NAK_INOUT</name>
22195                    <description>SETUP: Accept
22196IN: NAK
22197OUT:  NAK</description>
22198                    <value>1</value>
22199                  </enumeratedValue>
22200                  <enumeratedValue>
22201                    <name>STATUS_OUT_ONLY</name>
22202                    <description>SETUP: Accept
22203IN: STALL
22204OUT:  ACK 0B tokens, NAK others</description>
22205                    <value>2</value>
22206                  </enumeratedValue>
22207                  <enumeratedValue>
22208                    <name>STALL_INOUT</name>
22209                    <description>SETUP: Accept
22210IN: STALL
22211OUT:  STALL</description>
22212                    <value>3</value>
22213                  </enumeratedValue>
22214                  <enumeratedValue>
22215                    <name>ISO_OUT</name>
22216                    <description>SETUP: Ignore
22217IN: Ignore
22218OUT:  Accept Isochronous OUT token</description>
22219                    <value>5</value>
22220                  </enumeratedValue>
22221                  <enumeratedValue>
22222                    <name>STATUS_IN_ONLY</name>
22223                    <description>SETUP: Accept
22224IN: Respond with 0B data
22225OUT:  Stall</description>
22226                    <value>6</value>
22227                  </enumeratedValue>
22228                  <enumeratedValue>
22229                    <name>ISO_IN</name>
22230                    <description>SETUP: Ignore
22231IN: Accept Isochronous IN token
22232OUT:  Ignore</description>
22233                    <value>7</value>
22234                  </enumeratedValue>
22235                  <enumeratedValue>
22236                    <name>NAK_OUT</name>
22237                    <description>SETUP: Ignore
22238IN: Ignore
22239OUT:  NAK</description>
22240                    <value>8</value>
22241                  </enumeratedValue>
22242                  <enumeratedValue>
22243                    <name>ACK_OUT</name>
22244                    <description>SETUP: Ignore
22245IN: Ignore
22246OUT:  Accept data and ACK if STALL=0, STALL otherwise.
22247Change to MODE=8 after one succesfull OUT token.</description>
22248                    <value>9</value>
22249                  </enumeratedValue>
22250                  <enumeratedValue>
22251                    <name>ACK_OUT_STATUS_IN</name>
22252                    <description>SETUP: Accept
22253IN: Respond with 0B data
22254OUT:  Accept data</description>
22255                    <value>11</value>
22256                  </enumeratedValue>
22257                  <enumeratedValue>
22258                    <name>NAK_IN</name>
22259                    <description>SETUP: Ignore
22260IN: NAK
22261OUT:  Ignore</description>
22262                    <value>12</value>
22263                  </enumeratedValue>
22264                  <enumeratedValue>
22265                    <name>ACK_IN</name>
22266                    <description>SETUP: Ignore
22267IN: Respond to IN with data if STALL=0, STALL otherwise
22268OUT:  Ignore</description>
22269                    <value>13</value>
22270                  </enumeratedValue>
22271                  <enumeratedValue>
22272                    <name>ACK_IN_STATUS_OUT</name>
22273                    <description>SETUP: Accept
22274IN: Respond to IN with data
22275OUT:  ACK 0B tokens, NAK others</description>
22276                    <value>15</value>
22277                  </enumeratedValue>
22278                </enumeratedValues>
22279              </field>
22280              <field>
22281                <name>ACKED_TXN</name>
22282                <description>The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register.</description>
22283                <bitRange>[4:4]</bitRange>
22284                <access>read-write</access>
22285                <enumeratedValues>
22286                  <enumeratedValue>
22287                    <name>ACKED_NO</name>
22288                    <description>No ACK'd transactions since bit was last cleared.</description>
22289                    <value>0</value>
22290                  </enumeratedValue>
22291                  <enumeratedValue>
22292                    <name>ACKED_YES</name>
22293                    <description>Indicates a transaction ended with an ACK.</description>
22294                    <value>1</value>
22295                  </enumeratedValue>
22296                </enumeratedValues>
22297              </field>
22298              <field>
22299                <name>NAK_INT_EN</name>
22300                <description>When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK.</description>
22301                <bitRange>[5:5]</bitRange>
22302                <access>read-write</access>
22303              </field>
22304              <field>
22305                <name>ERR_IN_TXN</name>
22306                <description>The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID
22307error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register.</description>
22308                <bitRange>[6:6]</bitRange>
22309                <access>read-write</access>
22310              </field>
22311              <field>
22312                <name>STALL</name>
22313                <description>When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes.</description>
22314                <bitRange>[7:7]</bitRange>
22315                <access>read-write</access>
22316              </field>
22317            </fields>
22318          </register>
22319          <register>
22320            <name>OSCLK_DR0</name>
22321            <description>Oscillator lock data register 0</description>
22322            <addressOffset>0x80</addressOffset>
22323            <size>32</size>
22324            <access>read-only</access>
22325            <resetValue>0x0</resetValue>
22326            <resetMask>0x0</resetMask>
22327            <fields>
22328              <field>
22329                <name>ADDER</name>
22330                <description>These bits return the lower 8 bits of the oscillator locking circuits adder output.</description>
22331                <bitRange>[7:0]</bitRange>
22332                <access>read-only</access>
22333              </field>
22334            </fields>
22335          </register>
22336          <register>
22337            <name>OSCLK_DR1</name>
22338            <description>Oscillator lock data register 1</description>
22339            <addressOffset>0x84</addressOffset>
22340            <size>32</size>
22341            <access>read-only</access>
22342            <resetValue>0x0</resetValue>
22343            <resetMask>0x0</resetMask>
22344            <fields>
22345              <field>
22346                <name>ADDER_MSB</name>
22347                <description>These bits return the upper 7 bits of the oscillator locking circuits adder output.</description>
22348                <bitRange>[6:0]</bitRange>
22349                <access>read-only</access>
22350              </field>
22351            </fields>
22352          </register>
22353          <register>
22354            <name>EP0_CR</name>
22355            <description>Endpoint0 control Register</description>
22356            <addressOffset>0xA0</addressOffset>
22357            <size>32</size>
22358            <access>read-write</access>
22359            <resetValue>0x0</resetValue>
22360            <resetMask>0xFF</resetMask>
22361            <fields>
22362              <field>
22363                <name>MODE</name>
22364                <description>The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint.</description>
22365                <bitRange>[3:0]</bitRange>
22366                <access>read-write</access>
22367                <enumeratedValues>
22368                  <enumeratedValue>
22369                    <name>DISABLE</name>
22370                    <description>Ignore all USB traffic to this endpoint</description>
22371                    <value>0</value>
22372                  </enumeratedValue>
22373                  <enumeratedValue>
22374                    <name>NAK_INOUT</name>
22375                    <description>SETUP: Accept
22376IN: NAK
22377OUT:  NAK</description>
22378                    <value>1</value>
22379                  </enumeratedValue>
22380                  <enumeratedValue>
22381                    <name>STATUS_OUT_ONLY</name>
22382                    <description>SETUP: Accept
22383IN: STALL
22384OUT:  ACK 0B tokens, NAK others</description>
22385                    <value>2</value>
22386                  </enumeratedValue>
22387                  <enumeratedValue>
22388                    <name>STALL_INOUT</name>
22389                    <description>SETUP: Accept
22390IN: STALL
22391OUT:  STALL</description>
22392                    <value>3</value>
22393                  </enumeratedValue>
22394                  <enumeratedValue>
22395                    <name>ISO_OUT</name>
22396                    <description>SETUP: Ignore
22397IN: Ignore
22398OUT:  Accept Isochronous OUT token</description>
22399                    <value>5</value>
22400                  </enumeratedValue>
22401                  <enumeratedValue>
22402                    <name>STATUS_IN_ONLY</name>
22403                    <description>SETUP: Accept
22404IN: Respond with 0B data
22405OUT:  Stall</description>
22406                    <value>6</value>
22407                  </enumeratedValue>
22408                  <enumeratedValue>
22409                    <name>ISO_IN</name>
22410                    <description>SETUP: Ignore
22411IN: Accept Isochronous IN token
22412OUT:  Ignore</description>
22413                    <value>7</value>
22414                  </enumeratedValue>
22415                  <enumeratedValue>
22416                    <name>NAK_OUT</name>
22417                    <description>SETUP: Ignore
22418IN: Ignore
22419OUT:  NAK</description>
22420                    <value>8</value>
22421                  </enumeratedValue>
22422                  <enumeratedValue>
22423                    <name>ACK_OUT</name>
22424                    <description>SETUP: Ignore
22425IN: Ignore
22426OUT:  Accept data and ACK if STALL=0, STALL otherwise.
22427Change to MODE=8 after one succesfull OUT token.</description>
22428                    <value>9</value>
22429                  </enumeratedValue>
22430                  <enumeratedValue>
22431                    <name>ACK_OUT_STATUS_IN</name>
22432                    <description>SETUP: Accept
22433IN: Respond with 0B data
22434OUT:  Accept data</description>
22435                    <value>11</value>
22436                  </enumeratedValue>
22437                  <enumeratedValue>
22438                    <name>NAK_IN</name>
22439                    <description>SETUP: Ignore
22440IN: NAK
22441OUT:  Ignore</description>
22442                    <value>12</value>
22443                  </enumeratedValue>
22444                  <enumeratedValue>
22445                    <name>ACK_IN</name>
22446                    <description>SETUP: Ignore
22447IN: Respond to IN with data if STALL=0, STALL otherwise
22448OUT:  Ignore</description>
22449                    <value>13</value>
22450                  </enumeratedValue>
22451                  <enumeratedValue>
22452                    <name>ACK_IN_STATUS_OUT</name>
22453                    <description>SETUP: Accept
22454IN: Respond to IN with data
22455OUT:  ACK 0B tokens, NAK others</description>
22456                    <value>15</value>
22457                  </enumeratedValue>
22458                </enumeratedValues>
22459              </field>
22460              <field>
22461                <name>ACKED_TXN</name>
22462                <description>The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register.</description>
22463                <bitRange>[4:4]</bitRange>
22464                <access>read-write</access>
22465                <enumeratedValues>
22466                  <enumeratedValue>
22467                    <name>ACKED_NO</name>
22468                    <description>No ACK'd transactions since bit was last cleared.</description>
22469                    <value>0</value>
22470                  </enumeratedValue>
22471                  <enumeratedValue>
22472                    <name>ACKED_YES</name>
22473                    <description>Indicates a transaction ended with an ACK.</description>
22474                    <value>1</value>
22475                  </enumeratedValue>
22476                </enumeratedValues>
22477              </field>
22478              <field>
22479                <name>OUT_RCVD</name>
22480                <description>When set this bit indicates a valid OUT packet has been received and ACKed. This bit is updated to '1' after the last received packet in an OUT transaction. When clear this bit indicates no OUT received. It is cleared by any writes to the register.</description>
22481                <bitRange>[5:5]</bitRange>
22482                <access>read-write</access>
22483              </field>
22484              <field>
22485                <name>IN_RCVD</name>
22486                <description>When set this bit indicates a valid IN packet has been received. This bit is updated to '1' after the host acknowledges an IN data packet. When clear this bit indicates either no IN has been received or that the host did not acknowledge the IN data by sending ACK handshake. It is cleared by any writes to the register.</description>
22487                <bitRange>[6:6]</bitRange>
22488                <access>read-write</access>
22489              </field>
22490              <field>
22491                <name>SETUP_RCVD</name>
22492                <description>When set this bit indicates a valid SETUP packet was received and ACKed. This bit is forced HIGH from the start of the data packet phase of the SETUP transaction until the start of the ACK packet returned by the SIE. The CPU is prevented from clearing this bit during this interval. After this interval the bit will remain set until cleared by firmware. While this bit is set to '1' the CPU cannot write to the EP0_DRx registers. This prevents firmware from overwriting an incoming SETUP transaction before firmware has a chance to read the SETUP data. This bit is cleared by any non-locked writes to the register.</description>
22493                <bitRange>[7:7]</bitRange>
22494                <access>read-write</access>
22495              </field>
22496            </fields>
22497          </register>
22498          <register>
22499            <name>EP0_CNT</name>
22500            <description>Endpoint0 count Register</description>
22501            <addressOffset>0xA4</addressOffset>
22502            <size>32</size>
22503            <access>read-write</access>
22504            <resetValue>0x0</resetValue>
22505            <resetMask>0xCF</resetMask>
22506            <fields>
22507              <field>
22508                <name>BYTE_COUNT</name>
22509                <description>These bits indicate the number of data bytes in a transaction. For IN transactions firmware loads the count with the number of bytes to be transmitted to the host from the endpoint FIFO. Valid values are 0 to 8. For OUT or SETUP transactions the count is updated by hardware to the number of data bytes received plus two for the CRC bytes. Valid values are 2 to 10.</description>
22510                <bitRange>[3:0]</bitRange>
22511                <access>read-write</access>
22512              </field>
22513              <field>
22514                <name>DATA_VALID</name>
22515                <description>This bit is used for OUT/SETUP transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings.</description>
22516                <bitRange>[6:6]</bitRange>
22517                <access>read-write</access>
22518                <enumeratedValues>
22519                  <enumeratedValue>
22520                    <name>DATA_ERROR</name>
22521                    <description>No ACK'd transactions since bit was last cleared.</description>
22522                    <value>0</value>
22523                  </enumeratedValue>
22524                  <enumeratedValue>
22525                    <name>DATA_VALID</name>
22526                    <description>Indicates a transaction ended with an ACK.</description>
22527                    <value>1</value>
22528                  </enumeratedValue>
22529                </enumeratedValues>
22530              </field>
22531              <field>
22532                <name>DATA_TOGGLE</name>
22533                <description>This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit.</description>
22534                <bitRange>[7:7]</bitRange>
22535                <access>read-write</access>
22536              </field>
22537            </fields>
22538          </register>
22539          <register>
22540            <name>SIE_EP3_CNT0</name>
22541            <description>Non-control endpoint count register</description>
22542            <addressOffset>0xB0</addressOffset>
22543            <size>32</size>
22544            <access>read-write</access>
22545            <resetValue>0x0</resetValue>
22546            <resetMask>0xC7</resetMask>
22547            <fields>
22548              <field>
22549                <name>DATA_COUNT_MSB</name>
22550                <description>These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information.</description>
22551                <bitRange>[2:0]</bitRange>
22552                <access>read-write</access>
22553              </field>
22554              <field>
22555                <name>DATA_VALID</name>
22556                <description>This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings.</description>
22557                <bitRange>[6:6]</bitRange>
22558                <access>read-write</access>
22559                <enumeratedValues>
22560                  <enumeratedValue>
22561                    <name>DATA_ERROR</name>
22562                    <description>No ACK'd transactions since bit was last cleared.</description>
22563                    <value>0</value>
22564                  </enumeratedValue>
22565                  <enumeratedValue>
22566                    <name>DATA_VALID</name>
22567                    <description>Indicates a transaction ended with an ACK.</description>
22568                    <value>1</value>
22569                  </enumeratedValue>
22570                </enumeratedValues>
22571              </field>
22572              <field>
22573                <name>DATA_TOGGLE</name>
22574                <description>This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit.</description>
22575                <bitRange>[7:7]</bitRange>
22576                <access>read-write</access>
22577              </field>
22578            </fields>
22579          </register>
22580          <register>
22581            <name>SIE_EP3_CNT1</name>
22582            <description>Non-control endpoint count register</description>
22583            <addressOffset>0xB4</addressOffset>
22584            <size>32</size>
22585            <access>read-write</access>
22586            <resetValue>0x0</resetValue>
22587            <resetMask>0xFF</resetMask>
22588            <fields>
22589              <field>
22590                <name>DATA_COUNT</name>
22591                <description>These bits are the 8 LSb of a 11-bit counter.  The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction.</description>
22592                <bitRange>[7:0]</bitRange>
22593                <access>read-write</access>
22594              </field>
22595            </fields>
22596          </register>
22597          <register>
22598            <name>SIE_EP3_CR0</name>
22599            <description>Non-control endpoint's control Register</description>
22600            <addressOffset>0xB8</addressOffset>
22601            <size>32</size>
22602            <access>read-write</access>
22603            <resetValue>0x0</resetValue>
22604            <resetMask>0xFF</resetMask>
22605            <fields>
22606              <field>
22607                <name>MODE</name>
22608                <description>The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint.</description>
22609                <bitRange>[3:0]</bitRange>
22610                <access>read-write</access>
22611                <enumeratedValues>
22612                  <enumeratedValue>
22613                    <name>DISABLE</name>
22614                    <description>Ignore all USB traffic to this endpoint</description>
22615                    <value>0</value>
22616                  </enumeratedValue>
22617                  <enumeratedValue>
22618                    <name>NAK_INOUT</name>
22619                    <description>SETUP: Accept
22620IN: NAK
22621OUT:  NAK</description>
22622                    <value>1</value>
22623                  </enumeratedValue>
22624                  <enumeratedValue>
22625                    <name>STATUS_OUT_ONLY</name>
22626                    <description>SETUP: Accept
22627IN: STALL
22628OUT:  ACK 0B tokens, NAK others</description>
22629                    <value>2</value>
22630                  </enumeratedValue>
22631                  <enumeratedValue>
22632                    <name>STALL_INOUT</name>
22633                    <description>SETUP: Accept
22634IN: STALL
22635OUT:  STALL</description>
22636                    <value>3</value>
22637                  </enumeratedValue>
22638                  <enumeratedValue>
22639                    <name>ISO_OUT</name>
22640                    <description>SETUP: Ignore
22641IN: Ignore
22642OUT:  Accept Isochronous OUT token</description>
22643                    <value>5</value>
22644                  </enumeratedValue>
22645                  <enumeratedValue>
22646                    <name>STATUS_IN_ONLY</name>
22647                    <description>SETUP: Accept
22648IN: Respond with 0B data
22649OUT:  Stall</description>
22650                    <value>6</value>
22651                  </enumeratedValue>
22652                  <enumeratedValue>
22653                    <name>ISO_IN</name>
22654                    <description>SETUP: Ignore
22655IN: Accept Isochronous IN token
22656OUT:  Ignore</description>
22657                    <value>7</value>
22658                  </enumeratedValue>
22659                  <enumeratedValue>
22660                    <name>NAK_OUT</name>
22661                    <description>SETUP: Ignore
22662IN: Ignore
22663OUT:  NAK</description>
22664                    <value>8</value>
22665                  </enumeratedValue>
22666                  <enumeratedValue>
22667                    <name>ACK_OUT</name>
22668                    <description>SETUP: Ignore
22669IN: Ignore
22670OUT:  Accept data and ACK if STALL=0, STALL otherwise.
22671Change to MODE=8 after one succesfull OUT token.</description>
22672                    <value>9</value>
22673                  </enumeratedValue>
22674                  <enumeratedValue>
22675                    <name>ACK_OUT_STATUS_IN</name>
22676                    <description>SETUP: Accept
22677IN: Respond with 0B data
22678OUT:  Accept data</description>
22679                    <value>11</value>
22680                  </enumeratedValue>
22681                  <enumeratedValue>
22682                    <name>NAK_IN</name>
22683                    <description>SETUP: Ignore
22684IN: NAK
22685OUT:  Ignore</description>
22686                    <value>12</value>
22687                  </enumeratedValue>
22688                  <enumeratedValue>
22689                    <name>ACK_IN</name>
22690                    <description>SETUP: Ignore
22691IN: Respond to IN with data if STALL=0, STALL otherwise
22692OUT:  Ignore</description>
22693                    <value>13</value>
22694                  </enumeratedValue>
22695                  <enumeratedValue>
22696                    <name>ACK_IN_STATUS_OUT</name>
22697                    <description>SETUP: Accept
22698IN: Respond to IN with data
22699OUT:  ACK 0B tokens, NAK others</description>
22700                    <value>15</value>
22701                  </enumeratedValue>
22702                </enumeratedValues>
22703              </field>
22704              <field>
22705                <name>ACKED_TXN</name>
22706                <description>The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register.</description>
22707                <bitRange>[4:4]</bitRange>
22708                <access>read-write</access>
22709                <enumeratedValues>
22710                  <enumeratedValue>
22711                    <name>ACKED_NO</name>
22712                    <description>No ACK'd transactions since bit was last cleared.</description>
22713                    <value>0</value>
22714                  </enumeratedValue>
22715                  <enumeratedValue>
22716                    <name>ACKED_YES</name>
22717                    <description>Indicates a transaction ended with an ACK.</description>
22718                    <value>1</value>
22719                  </enumeratedValue>
22720                </enumeratedValues>
22721              </field>
22722              <field>
22723                <name>NAK_INT_EN</name>
22724                <description>When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK.</description>
22725                <bitRange>[5:5]</bitRange>
22726                <access>read-write</access>
22727              </field>
22728              <field>
22729                <name>ERR_IN_TXN</name>
22730                <description>The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID
22731error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register.</description>
22732                <bitRange>[6:6]</bitRange>
22733                <access>read-write</access>
22734              </field>
22735              <field>
22736                <name>STALL</name>
22737                <description>When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes.</description>
22738                <bitRange>[7:7]</bitRange>
22739                <access>read-write</access>
22740              </field>
22741            </fields>
22742          </register>
22743          <register>
22744            <name>SIE_EP4_CNT0</name>
22745            <description>Non-control endpoint count register</description>
22746            <addressOffset>0xF0</addressOffset>
22747            <size>32</size>
22748            <access>read-write</access>
22749            <resetValue>0x0</resetValue>
22750            <resetMask>0xC7</resetMask>
22751            <fields>
22752              <field>
22753                <name>DATA_COUNT_MSB</name>
22754                <description>These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information.</description>
22755                <bitRange>[2:0]</bitRange>
22756                <access>read-write</access>
22757              </field>
22758              <field>
22759                <name>DATA_VALID</name>
22760                <description>This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings.</description>
22761                <bitRange>[6:6]</bitRange>
22762                <access>read-write</access>
22763                <enumeratedValues>
22764                  <enumeratedValue>
22765                    <name>DATA_ERROR</name>
22766                    <description>No ACK'd transactions since bit was last cleared.</description>
22767                    <value>0</value>
22768                  </enumeratedValue>
22769                  <enumeratedValue>
22770                    <name>DATA_VALID</name>
22771                    <description>Indicates a transaction ended with an ACK.</description>
22772                    <value>1</value>
22773                  </enumeratedValue>
22774                </enumeratedValues>
22775              </field>
22776              <field>
22777                <name>DATA_TOGGLE</name>
22778                <description>This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit.</description>
22779                <bitRange>[7:7]</bitRange>
22780                <access>read-write</access>
22781              </field>
22782            </fields>
22783          </register>
22784          <register>
22785            <name>SIE_EP4_CNT1</name>
22786            <description>Non-control endpoint count register</description>
22787            <addressOffset>0xF4</addressOffset>
22788            <size>32</size>
22789            <access>read-write</access>
22790            <resetValue>0x0</resetValue>
22791            <resetMask>0xFF</resetMask>
22792            <fields>
22793              <field>
22794                <name>DATA_COUNT</name>
22795                <description>These bits are the 8 LSb of a 11-bit counter.  The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction.</description>
22796                <bitRange>[7:0]</bitRange>
22797                <access>read-write</access>
22798              </field>
22799            </fields>
22800          </register>
22801          <register>
22802            <name>SIE_EP4_CR0</name>
22803            <description>Non-control endpoint's control Register</description>
22804            <addressOffset>0xF8</addressOffset>
22805            <size>32</size>
22806            <access>read-write</access>
22807            <resetValue>0x0</resetValue>
22808            <resetMask>0xFF</resetMask>
22809            <fields>
22810              <field>
22811                <name>MODE</name>
22812                <description>The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint.</description>
22813                <bitRange>[3:0]</bitRange>
22814                <access>read-write</access>
22815                <enumeratedValues>
22816                  <enumeratedValue>
22817                    <name>DISABLE</name>
22818                    <description>Ignore all USB traffic to this endpoint</description>
22819                    <value>0</value>
22820                  </enumeratedValue>
22821                  <enumeratedValue>
22822                    <name>NAK_INOUT</name>
22823                    <description>SETUP: Accept
22824IN: NAK
22825OUT:  NAK</description>
22826                    <value>1</value>
22827                  </enumeratedValue>
22828                  <enumeratedValue>
22829                    <name>STATUS_OUT_ONLY</name>
22830                    <description>SETUP: Accept
22831IN: STALL
22832OUT:  ACK 0B tokens, NAK others</description>
22833                    <value>2</value>
22834                  </enumeratedValue>
22835                  <enumeratedValue>
22836                    <name>STALL_INOUT</name>
22837                    <description>SETUP: Accept
22838IN: STALL
22839OUT:  STALL</description>
22840                    <value>3</value>
22841                  </enumeratedValue>
22842                  <enumeratedValue>
22843                    <name>ISO_OUT</name>
22844                    <description>SETUP: Ignore
22845IN: Ignore
22846OUT:  Accept Isochronous OUT token</description>
22847                    <value>5</value>
22848                  </enumeratedValue>
22849                  <enumeratedValue>
22850                    <name>STATUS_IN_ONLY</name>
22851                    <description>SETUP: Accept
22852IN: Respond with 0B data
22853OUT:  Stall</description>
22854                    <value>6</value>
22855                  </enumeratedValue>
22856                  <enumeratedValue>
22857                    <name>ISO_IN</name>
22858                    <description>SETUP: Ignore
22859IN: Accept Isochronous IN token
22860OUT:  Ignore</description>
22861                    <value>7</value>
22862                  </enumeratedValue>
22863                  <enumeratedValue>
22864                    <name>NAK_OUT</name>
22865                    <description>SETUP: Ignore
22866IN: Ignore
22867OUT:  NAK</description>
22868                    <value>8</value>
22869                  </enumeratedValue>
22870                  <enumeratedValue>
22871                    <name>ACK_OUT</name>
22872                    <description>SETUP: Ignore
22873IN: Ignore
22874OUT:  Accept data and ACK if STALL=0, STALL otherwise.
22875Change to MODE=8 after one succesfull OUT token.</description>
22876                    <value>9</value>
22877                  </enumeratedValue>
22878                  <enumeratedValue>
22879                    <name>ACK_OUT_STATUS_IN</name>
22880                    <description>SETUP: Accept
22881IN: Respond with 0B data
22882OUT:  Accept data</description>
22883                    <value>11</value>
22884                  </enumeratedValue>
22885                  <enumeratedValue>
22886                    <name>NAK_IN</name>
22887                    <description>SETUP: Ignore
22888IN: NAK
22889OUT:  Ignore</description>
22890                    <value>12</value>
22891                  </enumeratedValue>
22892                  <enumeratedValue>
22893                    <name>ACK_IN</name>
22894                    <description>SETUP: Ignore
22895IN: Respond to IN with data if STALL=0, STALL otherwise
22896OUT:  Ignore</description>
22897                    <value>13</value>
22898                  </enumeratedValue>
22899                  <enumeratedValue>
22900                    <name>ACK_IN_STATUS_OUT</name>
22901                    <description>SETUP: Accept
22902IN: Respond to IN with data
22903OUT:  ACK 0B tokens, NAK others</description>
22904                    <value>15</value>
22905                  </enumeratedValue>
22906                </enumeratedValues>
22907              </field>
22908              <field>
22909                <name>ACKED_TXN</name>
22910                <description>The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register.</description>
22911                <bitRange>[4:4]</bitRange>
22912                <access>read-write</access>
22913                <enumeratedValues>
22914                  <enumeratedValue>
22915                    <name>ACKED_NO</name>
22916                    <description>No ACK'd transactions since bit was last cleared.</description>
22917                    <value>0</value>
22918                  </enumeratedValue>
22919                  <enumeratedValue>
22920                    <name>ACKED_YES</name>
22921                    <description>Indicates a transaction ended with an ACK.</description>
22922                    <value>1</value>
22923                  </enumeratedValue>
22924                </enumeratedValues>
22925              </field>
22926              <field>
22927                <name>NAK_INT_EN</name>
22928                <description>When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK.</description>
22929                <bitRange>[5:5]</bitRange>
22930                <access>read-write</access>
22931              </field>
22932              <field>
22933                <name>ERR_IN_TXN</name>
22934                <description>The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID
22935error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register.</description>
22936                <bitRange>[6:6]</bitRange>
22937                <access>read-write</access>
22938              </field>
22939              <field>
22940                <name>STALL</name>
22941                <description>When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes.</description>
22942                <bitRange>[7:7]</bitRange>
22943                <access>read-write</access>
22944              </field>
22945            </fields>
22946          </register>
22947          <register>
22948            <name>SIE_EP5_CNT0</name>
22949            <description>Non-control endpoint count register</description>
22950            <addressOffset>0x130</addressOffset>
22951            <size>32</size>
22952            <access>read-write</access>
22953            <resetValue>0x0</resetValue>
22954            <resetMask>0xC7</resetMask>
22955            <fields>
22956              <field>
22957                <name>DATA_COUNT_MSB</name>
22958                <description>These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information.</description>
22959                <bitRange>[2:0]</bitRange>
22960                <access>read-write</access>
22961              </field>
22962              <field>
22963                <name>DATA_VALID</name>
22964                <description>This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings.</description>
22965                <bitRange>[6:6]</bitRange>
22966                <access>read-write</access>
22967                <enumeratedValues>
22968                  <enumeratedValue>
22969                    <name>DATA_ERROR</name>
22970                    <description>No ACK'd transactions since bit was last cleared.</description>
22971                    <value>0</value>
22972                  </enumeratedValue>
22973                  <enumeratedValue>
22974                    <name>DATA_VALID</name>
22975                    <description>Indicates a transaction ended with an ACK.</description>
22976                    <value>1</value>
22977                  </enumeratedValue>
22978                </enumeratedValues>
22979              </field>
22980              <field>
22981                <name>DATA_TOGGLE</name>
22982                <description>This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit.</description>
22983                <bitRange>[7:7]</bitRange>
22984                <access>read-write</access>
22985              </field>
22986            </fields>
22987          </register>
22988          <register>
22989            <name>SIE_EP5_CNT1</name>
22990            <description>Non-control endpoint count register</description>
22991            <addressOffset>0x134</addressOffset>
22992            <size>32</size>
22993            <access>read-write</access>
22994            <resetValue>0x0</resetValue>
22995            <resetMask>0xFF</resetMask>
22996            <fields>
22997              <field>
22998                <name>DATA_COUNT</name>
22999                <description>These bits are the 8 LSb of a 11-bit counter.  The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction.</description>
23000                <bitRange>[7:0]</bitRange>
23001                <access>read-write</access>
23002              </field>
23003            </fields>
23004          </register>
23005          <register>
23006            <name>SIE_EP5_CR0</name>
23007            <description>Non-control endpoint's control Register</description>
23008            <addressOffset>0x138</addressOffset>
23009            <size>32</size>
23010            <access>read-write</access>
23011            <resetValue>0x0</resetValue>
23012            <resetMask>0xFF</resetMask>
23013            <fields>
23014              <field>
23015                <name>MODE</name>
23016                <description>The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint.</description>
23017                <bitRange>[3:0]</bitRange>
23018                <access>read-write</access>
23019                <enumeratedValues>
23020                  <enumeratedValue>
23021                    <name>DISABLE</name>
23022                    <description>Ignore all USB traffic to this endpoint</description>
23023                    <value>0</value>
23024                  </enumeratedValue>
23025                  <enumeratedValue>
23026                    <name>NAK_INOUT</name>
23027                    <description>SETUP: Accept
23028IN: NAK
23029OUT:  NAK</description>
23030                    <value>1</value>
23031                  </enumeratedValue>
23032                  <enumeratedValue>
23033                    <name>STATUS_OUT_ONLY</name>
23034                    <description>SETUP: Accept
23035IN: STALL
23036OUT:  ACK 0B tokens, NAK others</description>
23037                    <value>2</value>
23038                  </enumeratedValue>
23039                  <enumeratedValue>
23040                    <name>STALL_INOUT</name>
23041                    <description>SETUP: Accept
23042IN: STALL
23043OUT:  STALL</description>
23044                    <value>3</value>
23045                  </enumeratedValue>
23046                  <enumeratedValue>
23047                    <name>ISO_OUT</name>
23048                    <description>SETUP: Ignore
23049IN: Ignore
23050OUT:  Accept Isochronous OUT token</description>
23051                    <value>5</value>
23052                  </enumeratedValue>
23053                  <enumeratedValue>
23054                    <name>STATUS_IN_ONLY</name>
23055                    <description>SETUP: Accept
23056IN: Respond with 0B data
23057OUT:  Stall</description>
23058                    <value>6</value>
23059                  </enumeratedValue>
23060                  <enumeratedValue>
23061                    <name>ISO_IN</name>
23062                    <description>SETUP: Ignore
23063IN: Accept Isochronous IN token
23064OUT:  Ignore</description>
23065                    <value>7</value>
23066                  </enumeratedValue>
23067                  <enumeratedValue>
23068                    <name>NAK_OUT</name>
23069                    <description>SETUP: Ignore
23070IN: Ignore
23071OUT:  NAK</description>
23072                    <value>8</value>
23073                  </enumeratedValue>
23074                  <enumeratedValue>
23075                    <name>ACK_OUT</name>
23076                    <description>SETUP: Ignore
23077IN: Ignore
23078OUT:  Accept data and ACK if STALL=0, STALL otherwise.
23079Change to MODE=8 after one succesfull OUT token.</description>
23080                    <value>9</value>
23081                  </enumeratedValue>
23082                  <enumeratedValue>
23083                    <name>ACK_OUT_STATUS_IN</name>
23084                    <description>SETUP: Accept
23085IN: Respond with 0B data
23086OUT:  Accept data</description>
23087                    <value>11</value>
23088                  </enumeratedValue>
23089                  <enumeratedValue>
23090                    <name>NAK_IN</name>
23091                    <description>SETUP: Ignore
23092IN: NAK
23093OUT:  Ignore</description>
23094                    <value>12</value>
23095                  </enumeratedValue>
23096                  <enumeratedValue>
23097                    <name>ACK_IN</name>
23098                    <description>SETUP: Ignore
23099IN: Respond to IN with data if STALL=0, STALL otherwise
23100OUT:  Ignore</description>
23101                    <value>13</value>
23102                  </enumeratedValue>
23103                  <enumeratedValue>
23104                    <name>ACK_IN_STATUS_OUT</name>
23105                    <description>SETUP: Accept
23106IN: Respond to IN with data
23107OUT:  ACK 0B tokens, NAK others</description>
23108                    <value>15</value>
23109                  </enumeratedValue>
23110                </enumeratedValues>
23111              </field>
23112              <field>
23113                <name>ACKED_TXN</name>
23114                <description>The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register.</description>
23115                <bitRange>[4:4]</bitRange>
23116                <access>read-write</access>
23117                <enumeratedValues>
23118                  <enumeratedValue>
23119                    <name>ACKED_NO</name>
23120                    <description>No ACK'd transactions since bit was last cleared.</description>
23121                    <value>0</value>
23122                  </enumeratedValue>
23123                  <enumeratedValue>
23124                    <name>ACKED_YES</name>
23125                    <description>Indicates a transaction ended with an ACK.</description>
23126                    <value>1</value>
23127                  </enumeratedValue>
23128                </enumeratedValues>
23129              </field>
23130              <field>
23131                <name>NAK_INT_EN</name>
23132                <description>When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK.</description>
23133                <bitRange>[5:5]</bitRange>
23134                <access>read-write</access>
23135              </field>
23136              <field>
23137                <name>ERR_IN_TXN</name>
23138                <description>The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID
23139error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register.</description>
23140                <bitRange>[6:6]</bitRange>
23141                <access>read-write</access>
23142              </field>
23143              <field>
23144                <name>STALL</name>
23145                <description>When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes.</description>
23146                <bitRange>[7:7]</bitRange>
23147                <access>read-write</access>
23148              </field>
23149            </fields>
23150          </register>
23151          <register>
23152            <name>SIE_EP6_CNT0</name>
23153            <description>Non-control endpoint count register</description>
23154            <addressOffset>0x170</addressOffset>
23155            <size>32</size>
23156            <access>read-write</access>
23157            <resetValue>0x0</resetValue>
23158            <resetMask>0xC7</resetMask>
23159            <fields>
23160              <field>
23161                <name>DATA_COUNT_MSB</name>
23162                <description>These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information.</description>
23163                <bitRange>[2:0]</bitRange>
23164                <access>read-write</access>
23165              </field>
23166              <field>
23167                <name>DATA_VALID</name>
23168                <description>This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings.</description>
23169                <bitRange>[6:6]</bitRange>
23170                <access>read-write</access>
23171                <enumeratedValues>
23172                  <enumeratedValue>
23173                    <name>DATA_ERROR</name>
23174                    <description>No ACK'd transactions since bit was last cleared.</description>
23175                    <value>0</value>
23176                  </enumeratedValue>
23177                  <enumeratedValue>
23178                    <name>DATA_VALID</name>
23179                    <description>Indicates a transaction ended with an ACK.</description>
23180                    <value>1</value>
23181                  </enumeratedValue>
23182                </enumeratedValues>
23183              </field>
23184              <field>
23185                <name>DATA_TOGGLE</name>
23186                <description>This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit.</description>
23187                <bitRange>[7:7]</bitRange>
23188                <access>read-write</access>
23189              </field>
23190            </fields>
23191          </register>
23192          <register>
23193            <name>SIE_EP6_CNT1</name>
23194            <description>Non-control endpoint count register</description>
23195            <addressOffset>0x174</addressOffset>
23196            <size>32</size>
23197            <access>read-write</access>
23198            <resetValue>0x0</resetValue>
23199            <resetMask>0xFF</resetMask>
23200            <fields>
23201              <field>
23202                <name>DATA_COUNT</name>
23203                <description>These bits are the 8 LSb of a 11-bit counter.  The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction.</description>
23204                <bitRange>[7:0]</bitRange>
23205                <access>read-write</access>
23206              </field>
23207            </fields>
23208          </register>
23209          <register>
23210            <name>SIE_EP6_CR0</name>
23211            <description>Non-control endpoint's control Register</description>
23212            <addressOffset>0x178</addressOffset>
23213            <size>32</size>
23214            <access>read-write</access>
23215            <resetValue>0x0</resetValue>
23216            <resetMask>0xFF</resetMask>
23217            <fields>
23218              <field>
23219                <name>MODE</name>
23220                <description>The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint.</description>
23221                <bitRange>[3:0]</bitRange>
23222                <access>read-write</access>
23223                <enumeratedValues>
23224                  <enumeratedValue>
23225                    <name>DISABLE</name>
23226                    <description>Ignore all USB traffic to this endpoint</description>
23227                    <value>0</value>
23228                  </enumeratedValue>
23229                  <enumeratedValue>
23230                    <name>NAK_INOUT</name>
23231                    <description>SETUP: Accept
23232IN: NAK
23233OUT:  NAK</description>
23234                    <value>1</value>
23235                  </enumeratedValue>
23236                  <enumeratedValue>
23237                    <name>STATUS_OUT_ONLY</name>
23238                    <description>SETUP: Accept
23239IN: STALL
23240OUT:  ACK 0B tokens, NAK others</description>
23241                    <value>2</value>
23242                  </enumeratedValue>
23243                  <enumeratedValue>
23244                    <name>STALL_INOUT</name>
23245                    <description>SETUP: Accept
23246IN: STALL
23247OUT:  STALL</description>
23248                    <value>3</value>
23249                  </enumeratedValue>
23250                  <enumeratedValue>
23251                    <name>ISO_OUT</name>
23252                    <description>SETUP: Ignore
23253IN: Ignore
23254OUT:  Accept Isochronous OUT token</description>
23255                    <value>5</value>
23256                  </enumeratedValue>
23257                  <enumeratedValue>
23258                    <name>STATUS_IN_ONLY</name>
23259                    <description>SETUP: Accept
23260IN: Respond with 0B data
23261OUT:  Stall</description>
23262                    <value>6</value>
23263                  </enumeratedValue>
23264                  <enumeratedValue>
23265                    <name>ISO_IN</name>
23266                    <description>SETUP: Ignore
23267IN: Accept Isochronous IN token
23268OUT:  Ignore</description>
23269                    <value>7</value>
23270                  </enumeratedValue>
23271                  <enumeratedValue>
23272                    <name>NAK_OUT</name>
23273                    <description>SETUP: Ignore
23274IN: Ignore
23275OUT:  NAK</description>
23276                    <value>8</value>
23277                  </enumeratedValue>
23278                  <enumeratedValue>
23279                    <name>ACK_OUT</name>
23280                    <description>SETUP: Ignore
23281IN: Ignore
23282OUT:  Accept data and ACK if STALL=0, STALL otherwise.
23283Change to MODE=8 after one succesfull OUT token.</description>
23284                    <value>9</value>
23285                  </enumeratedValue>
23286                  <enumeratedValue>
23287                    <name>ACK_OUT_STATUS_IN</name>
23288                    <description>SETUP: Accept
23289IN: Respond with 0B data
23290OUT:  Accept data</description>
23291                    <value>11</value>
23292                  </enumeratedValue>
23293                  <enumeratedValue>
23294                    <name>NAK_IN</name>
23295                    <description>SETUP: Ignore
23296IN: NAK
23297OUT:  Ignore</description>
23298                    <value>12</value>
23299                  </enumeratedValue>
23300                  <enumeratedValue>
23301                    <name>ACK_IN</name>
23302                    <description>SETUP: Ignore
23303IN: Respond to IN with data if STALL=0, STALL otherwise
23304OUT:  Ignore</description>
23305                    <value>13</value>
23306                  </enumeratedValue>
23307                  <enumeratedValue>
23308                    <name>ACK_IN_STATUS_OUT</name>
23309                    <description>SETUP: Accept
23310IN: Respond to IN with data
23311OUT:  ACK 0B tokens, NAK others</description>
23312                    <value>15</value>
23313                  </enumeratedValue>
23314                </enumeratedValues>
23315              </field>
23316              <field>
23317                <name>ACKED_TXN</name>
23318                <description>The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register.</description>
23319                <bitRange>[4:4]</bitRange>
23320                <access>read-write</access>
23321                <enumeratedValues>
23322                  <enumeratedValue>
23323                    <name>ACKED_NO</name>
23324                    <description>No ACK'd transactions since bit was last cleared.</description>
23325                    <value>0</value>
23326                  </enumeratedValue>
23327                  <enumeratedValue>
23328                    <name>ACKED_YES</name>
23329                    <description>Indicates a transaction ended with an ACK.</description>
23330                    <value>1</value>
23331                  </enumeratedValue>
23332                </enumeratedValues>
23333              </field>
23334              <field>
23335                <name>NAK_INT_EN</name>
23336                <description>When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK.</description>
23337                <bitRange>[5:5]</bitRange>
23338                <access>read-write</access>
23339              </field>
23340              <field>
23341                <name>ERR_IN_TXN</name>
23342                <description>The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID
23343error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register.</description>
23344                <bitRange>[6:6]</bitRange>
23345                <access>read-write</access>
23346              </field>
23347              <field>
23348                <name>STALL</name>
23349                <description>When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes.</description>
23350                <bitRange>[7:7]</bitRange>
23351                <access>read-write</access>
23352              </field>
23353            </fields>
23354          </register>
23355          <register>
23356            <name>SIE_EP7_CNT0</name>
23357            <description>Non-control endpoint count register</description>
23358            <addressOffset>0x1B0</addressOffset>
23359            <size>32</size>
23360            <access>read-write</access>
23361            <resetValue>0x0</resetValue>
23362            <resetMask>0xC7</resetMask>
23363            <fields>
23364              <field>
23365                <name>DATA_COUNT_MSB</name>
23366                <description>These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information.</description>
23367                <bitRange>[2:0]</bitRange>
23368                <access>read-write</access>
23369              </field>
23370              <field>
23371                <name>DATA_VALID</name>
23372                <description>This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings.</description>
23373                <bitRange>[6:6]</bitRange>
23374                <access>read-write</access>
23375                <enumeratedValues>
23376                  <enumeratedValue>
23377                    <name>DATA_ERROR</name>
23378                    <description>No ACK'd transactions since bit was last cleared.</description>
23379                    <value>0</value>
23380                  </enumeratedValue>
23381                  <enumeratedValue>
23382                    <name>DATA_VALID</name>
23383                    <description>Indicates a transaction ended with an ACK.</description>
23384                    <value>1</value>
23385                  </enumeratedValue>
23386                </enumeratedValues>
23387              </field>
23388              <field>
23389                <name>DATA_TOGGLE</name>
23390                <description>This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit.</description>
23391                <bitRange>[7:7]</bitRange>
23392                <access>read-write</access>
23393              </field>
23394            </fields>
23395          </register>
23396          <register>
23397            <name>SIE_EP7_CNT1</name>
23398            <description>Non-control endpoint count register</description>
23399            <addressOffset>0x1B4</addressOffset>
23400            <size>32</size>
23401            <access>read-write</access>
23402            <resetValue>0x0</resetValue>
23403            <resetMask>0xFF</resetMask>
23404            <fields>
23405              <field>
23406                <name>DATA_COUNT</name>
23407                <description>These bits are the 8 LSb of a 11-bit counter.  The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction.</description>
23408                <bitRange>[7:0]</bitRange>
23409                <access>read-write</access>
23410              </field>
23411            </fields>
23412          </register>
23413          <register>
23414            <name>SIE_EP7_CR0</name>
23415            <description>Non-control endpoint's control Register</description>
23416            <addressOffset>0x1B8</addressOffset>
23417            <size>32</size>
23418            <access>read-write</access>
23419            <resetValue>0x0</resetValue>
23420            <resetMask>0xFF</resetMask>
23421            <fields>
23422              <field>
23423                <name>MODE</name>
23424                <description>The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint.</description>
23425                <bitRange>[3:0]</bitRange>
23426                <access>read-write</access>
23427                <enumeratedValues>
23428                  <enumeratedValue>
23429                    <name>DISABLE</name>
23430                    <description>Ignore all USB traffic to this endpoint</description>
23431                    <value>0</value>
23432                  </enumeratedValue>
23433                  <enumeratedValue>
23434                    <name>NAK_INOUT</name>
23435                    <description>SETUP: Accept
23436IN: NAK
23437OUT:  NAK</description>
23438                    <value>1</value>
23439                  </enumeratedValue>
23440                  <enumeratedValue>
23441                    <name>STATUS_OUT_ONLY</name>
23442                    <description>SETUP: Accept
23443IN: STALL
23444OUT:  ACK 0B tokens, NAK others</description>
23445                    <value>2</value>
23446                  </enumeratedValue>
23447                  <enumeratedValue>
23448                    <name>STALL_INOUT</name>
23449                    <description>SETUP: Accept
23450IN: STALL
23451OUT:  STALL</description>
23452                    <value>3</value>
23453                  </enumeratedValue>
23454                  <enumeratedValue>
23455                    <name>ISO_OUT</name>
23456                    <description>SETUP: Ignore
23457IN: Ignore
23458OUT:  Accept Isochronous OUT token</description>
23459                    <value>5</value>
23460                  </enumeratedValue>
23461                  <enumeratedValue>
23462                    <name>STATUS_IN_ONLY</name>
23463                    <description>SETUP: Accept
23464IN: Respond with 0B data
23465OUT:  Stall</description>
23466                    <value>6</value>
23467                  </enumeratedValue>
23468                  <enumeratedValue>
23469                    <name>ISO_IN</name>
23470                    <description>SETUP: Ignore
23471IN: Accept Isochronous IN token
23472OUT:  Ignore</description>
23473                    <value>7</value>
23474                  </enumeratedValue>
23475                  <enumeratedValue>
23476                    <name>NAK_OUT</name>
23477                    <description>SETUP: Ignore
23478IN: Ignore
23479OUT:  NAK</description>
23480                    <value>8</value>
23481                  </enumeratedValue>
23482                  <enumeratedValue>
23483                    <name>ACK_OUT</name>
23484                    <description>SETUP: Ignore
23485IN: Ignore
23486OUT:  Accept data and ACK if STALL=0, STALL otherwise.
23487Change to MODE=8 after one succesfull OUT token.</description>
23488                    <value>9</value>
23489                  </enumeratedValue>
23490                  <enumeratedValue>
23491                    <name>ACK_OUT_STATUS_IN</name>
23492                    <description>SETUP: Accept
23493IN: Respond with 0B data
23494OUT:  Accept data</description>
23495                    <value>11</value>
23496                  </enumeratedValue>
23497                  <enumeratedValue>
23498                    <name>NAK_IN</name>
23499                    <description>SETUP: Ignore
23500IN: NAK
23501OUT:  Ignore</description>
23502                    <value>12</value>
23503                  </enumeratedValue>
23504                  <enumeratedValue>
23505                    <name>ACK_IN</name>
23506                    <description>SETUP: Ignore
23507IN: Respond to IN with data if STALL=0, STALL otherwise
23508OUT:  Ignore</description>
23509                    <value>13</value>
23510                  </enumeratedValue>
23511                  <enumeratedValue>
23512                    <name>ACK_IN_STATUS_OUT</name>
23513                    <description>SETUP: Accept
23514IN: Respond to IN with data
23515OUT:  ACK 0B tokens, NAK others</description>
23516                    <value>15</value>
23517                  </enumeratedValue>
23518                </enumeratedValues>
23519              </field>
23520              <field>
23521                <name>ACKED_TXN</name>
23522                <description>The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register.</description>
23523                <bitRange>[4:4]</bitRange>
23524                <access>read-write</access>
23525                <enumeratedValues>
23526                  <enumeratedValue>
23527                    <name>ACKED_NO</name>
23528                    <description>No ACK'd transactions since bit was last cleared.</description>
23529                    <value>0</value>
23530                  </enumeratedValue>
23531                  <enumeratedValue>
23532                    <name>ACKED_YES</name>
23533                    <description>Indicates a transaction ended with an ACK.</description>
23534                    <value>1</value>
23535                  </enumeratedValue>
23536                </enumeratedValues>
23537              </field>
23538              <field>
23539                <name>NAK_INT_EN</name>
23540                <description>When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK.</description>
23541                <bitRange>[5:5]</bitRange>
23542                <access>read-write</access>
23543              </field>
23544              <field>
23545                <name>ERR_IN_TXN</name>
23546                <description>The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID
23547error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register.</description>
23548                <bitRange>[6:6]</bitRange>
23549                <access>read-write</access>
23550              </field>
23551              <field>
23552                <name>STALL</name>
23553                <description>When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes.</description>
23554                <bitRange>[7:7]</bitRange>
23555                <access>read-write</access>
23556              </field>
23557            </fields>
23558          </register>
23559          <register>
23560            <name>SIE_EP8_CNT0</name>
23561            <description>Non-control endpoint count register</description>
23562            <addressOffset>0x1F0</addressOffset>
23563            <size>32</size>
23564            <access>read-write</access>
23565            <resetValue>0x0</resetValue>
23566            <resetMask>0xC7</resetMask>
23567            <fields>
23568              <field>
23569                <name>DATA_COUNT_MSB</name>
23570                <description>These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information.</description>
23571                <bitRange>[2:0]</bitRange>
23572                <access>read-write</access>
23573              </field>
23574              <field>
23575                <name>DATA_VALID</name>
23576                <description>This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings.</description>
23577                <bitRange>[6:6]</bitRange>
23578                <access>read-write</access>
23579                <enumeratedValues>
23580                  <enumeratedValue>
23581                    <name>DATA_ERROR</name>
23582                    <description>No ACK'd transactions since bit was last cleared.</description>
23583                    <value>0</value>
23584                  </enumeratedValue>
23585                  <enumeratedValue>
23586                    <name>DATA_VALID</name>
23587                    <description>Indicates a transaction ended with an ACK.</description>
23588                    <value>1</value>
23589                  </enumeratedValue>
23590                </enumeratedValues>
23591              </field>
23592              <field>
23593                <name>DATA_TOGGLE</name>
23594                <description>This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit.</description>
23595                <bitRange>[7:7]</bitRange>
23596                <access>read-write</access>
23597              </field>
23598            </fields>
23599          </register>
23600          <register>
23601            <name>SIE_EP8_CNT1</name>
23602            <description>Non-control endpoint count register</description>
23603            <addressOffset>0x1F4</addressOffset>
23604            <size>32</size>
23605            <access>read-write</access>
23606            <resetValue>0x0</resetValue>
23607            <resetMask>0xFF</resetMask>
23608            <fields>
23609              <field>
23610                <name>DATA_COUNT</name>
23611                <description>These bits are the 8 LSb of a 11-bit counter.  The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction.</description>
23612                <bitRange>[7:0]</bitRange>
23613                <access>read-write</access>
23614              </field>
23615            </fields>
23616          </register>
23617          <register>
23618            <name>SIE_EP8_CR0</name>
23619            <description>Non-control endpoint's control Register</description>
23620            <addressOffset>0x1F8</addressOffset>
23621            <size>32</size>
23622            <access>read-write</access>
23623            <resetValue>0x0</resetValue>
23624            <resetMask>0xFF</resetMask>
23625            <fields>
23626              <field>
23627                <name>MODE</name>
23628                <description>The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint.</description>
23629                <bitRange>[3:0]</bitRange>
23630                <access>read-write</access>
23631                <enumeratedValues>
23632                  <enumeratedValue>
23633                    <name>DISABLE</name>
23634                    <description>Ignore all USB traffic to this endpoint</description>
23635                    <value>0</value>
23636                  </enumeratedValue>
23637                  <enumeratedValue>
23638                    <name>NAK_INOUT</name>
23639                    <description>SETUP: Accept
23640IN: NAK
23641OUT:  NAK</description>
23642                    <value>1</value>
23643                  </enumeratedValue>
23644                  <enumeratedValue>
23645                    <name>STATUS_OUT_ONLY</name>
23646                    <description>SETUP: Accept
23647IN: STALL
23648OUT:  ACK 0B tokens, NAK others</description>
23649                    <value>2</value>
23650                  </enumeratedValue>
23651                  <enumeratedValue>
23652                    <name>STALL_INOUT</name>
23653                    <description>SETUP: Accept
23654IN: STALL
23655OUT:  STALL</description>
23656                    <value>3</value>
23657                  </enumeratedValue>
23658                  <enumeratedValue>
23659                    <name>ISO_OUT</name>
23660                    <description>SETUP: Ignore
23661IN: Ignore
23662OUT:  Accept Isochronous OUT token</description>
23663                    <value>5</value>
23664                  </enumeratedValue>
23665                  <enumeratedValue>
23666                    <name>STATUS_IN_ONLY</name>
23667                    <description>SETUP: Accept
23668IN: Respond with 0B data
23669OUT:  Stall</description>
23670                    <value>6</value>
23671                  </enumeratedValue>
23672                  <enumeratedValue>
23673                    <name>ISO_IN</name>
23674                    <description>SETUP: Ignore
23675IN: Accept Isochronous IN token
23676OUT:  Ignore</description>
23677                    <value>7</value>
23678                  </enumeratedValue>
23679                  <enumeratedValue>
23680                    <name>NAK_OUT</name>
23681                    <description>SETUP: Ignore
23682IN: Ignore
23683OUT:  NAK</description>
23684                    <value>8</value>
23685                  </enumeratedValue>
23686                  <enumeratedValue>
23687                    <name>ACK_OUT</name>
23688                    <description>SETUP: Ignore
23689IN: Ignore
23690OUT:  Accept data and ACK if STALL=0, STALL otherwise.
23691Change to MODE=8 after one succesfull OUT token.</description>
23692                    <value>9</value>
23693                  </enumeratedValue>
23694                  <enumeratedValue>
23695                    <name>ACK_OUT_STATUS_IN</name>
23696                    <description>SETUP: Accept
23697IN: Respond with 0B data
23698OUT:  Accept data</description>
23699                    <value>11</value>
23700                  </enumeratedValue>
23701                  <enumeratedValue>
23702                    <name>NAK_IN</name>
23703                    <description>SETUP: Ignore
23704IN: NAK
23705OUT:  Ignore</description>
23706                    <value>12</value>
23707                  </enumeratedValue>
23708                  <enumeratedValue>
23709                    <name>ACK_IN</name>
23710                    <description>SETUP: Ignore
23711IN: Respond to IN with data if STALL=0, STALL otherwise
23712OUT:  Ignore</description>
23713                    <value>13</value>
23714                  </enumeratedValue>
23715                  <enumeratedValue>
23716                    <name>ACK_IN_STATUS_OUT</name>
23717                    <description>SETUP: Accept
23718IN: Respond to IN with data
23719OUT:  ACK 0B tokens, NAK others</description>
23720                    <value>15</value>
23721                  </enumeratedValue>
23722                </enumeratedValues>
23723              </field>
23724              <field>
23725                <name>ACKED_TXN</name>
23726                <description>The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register.</description>
23727                <bitRange>[4:4]</bitRange>
23728                <access>read-write</access>
23729                <enumeratedValues>
23730                  <enumeratedValue>
23731                    <name>ACKED_NO</name>
23732                    <description>No ACK'd transactions since bit was last cleared.</description>
23733                    <value>0</value>
23734                  </enumeratedValue>
23735                  <enumeratedValue>
23736                    <name>ACKED_YES</name>
23737                    <description>Indicates a transaction ended with an ACK.</description>
23738                    <value>1</value>
23739                  </enumeratedValue>
23740                </enumeratedValues>
23741              </field>
23742              <field>
23743                <name>NAK_INT_EN</name>
23744                <description>When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK.</description>
23745                <bitRange>[5:5]</bitRange>
23746                <access>read-write</access>
23747              </field>
23748              <field>
23749                <name>ERR_IN_TXN</name>
23750                <description>The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID
23751error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register.</description>
23752                <bitRange>[6:6]</bitRange>
23753                <access>read-write</access>
23754              </field>
23755              <field>
23756                <name>STALL</name>
23757                <description>When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes.</description>
23758                <bitRange>[7:7]</bitRange>
23759                <access>read-write</access>
23760              </field>
23761            </fields>
23762          </register>
23763          <register>
23764            <name>ARB_EP1_CFG</name>
23765            <description>Endpoint Configuration Register  *1</description>
23766            <addressOffset>0x200</addressOffset>
23767            <size>32</size>
23768            <access>read-write</access>
23769            <resetValue>0x0</resetValue>
23770            <resetMask>0xF</resetMask>
23771            <fields>
23772              <field>
23773                <name>IN_DATA_RDY</name>
23774                <description>Indication that Endpoint Packet Data is Ready in Main memory</description>
23775                <bitRange>[0:0]</bitRange>
23776                <access>read-write</access>
23777              </field>
23778              <field>
23779                <name>DMA_REQ</name>
23780                <description>Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated.</description>
23781                <bitRange>[1:1]</bitRange>
23782                <access>read-write</access>
23783              </field>
23784              <field>
23785                <name>CRC_BYPASS</name>
23786                <description>Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware</description>
23787                <bitRange>[2:2]</bitRange>
23788                <access>read-write</access>
23789                <enumeratedValues>
23790                  <enumeratedValue>
23791                    <name>CRC_NORMAL</name>
23792                    <description>No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s</description>
23793                    <value>0</value>
23794                  </enumeratedValue>
23795                  <enumeratedValue>
23796                    <name>CRC_BYPASS</name>
23797                    <description>CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s</description>
23798                    <value>1</value>
23799                  </enumeratedValue>
23800                </enumeratedValues>
23801              </field>
23802              <field>
23803                <name>RESET_PTR</name>
23804                <description>Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction.</description>
23805                <bitRange>[3:3]</bitRange>
23806                <access>read-write</access>
23807                <enumeratedValues>
23808                  <enumeratedValue>
23809                    <name>RESET_KRYPTON</name>
23810                    <description>Do not Reset Pointer; Krypton Backward compatibility mode</description>
23811                    <value>0</value>
23812                  </enumeratedValue>
23813                  <enumeratedValue>
23814                    <name>RESET_NORMAL</name>
23815                    <description>Reset Pointer; recommended value for reduction of CPU Configuration Writes.</description>
23816                    <value>1</value>
23817                  </enumeratedValue>
23818                </enumeratedValues>
23819              </field>
23820            </fields>
23821          </register>
23822          <register>
23823            <name>ARB_EP1_INT_EN</name>
23824            <description>Endpoint Interrupt Enable Register  *1</description>
23825            <addressOffset>0x204</addressOffset>
23826            <size>32</size>
23827            <access>read-write</access>
23828            <resetValue>0x0</resetValue>
23829            <resetMask>0x3F</resetMask>
23830            <fields>
23831              <field>
23832                <name>IN_BUF_FULL_EN</name>
23833                <description>IN Endpoint Local Buffer Full Enable</description>
23834                <bitRange>[0:0]</bitRange>
23835                <access>read-write</access>
23836              </field>
23837              <field>
23838                <name>DMA_GNT_EN</name>
23839                <description>Endpoint DMA Grant Enable</description>
23840                <bitRange>[1:1]</bitRange>
23841                <access>read-write</access>
23842              </field>
23843              <field>
23844                <name>BUF_OVER_EN</name>
23845                <description>Endpoint Buffer Overflow Enable</description>
23846                <bitRange>[2:2]</bitRange>
23847                <access>read-write</access>
23848              </field>
23849              <field>
23850                <name>BUF_UNDER_EN</name>
23851                <description>Endpoint Buffer Underflow Enable</description>
23852                <bitRange>[3:3]</bitRange>
23853                <access>read-write</access>
23854              </field>
23855              <field>
23856                <name>ERR_INT_EN</name>
23857                <description>Endpoint Error in Transaction Interrupt Enable</description>
23858                <bitRange>[4:4]</bitRange>
23859                <access>read-write</access>
23860              </field>
23861              <field>
23862                <name>DMA_TERMIN_EN</name>
23863                <description>Endpoint DMA Terminated Enable</description>
23864                <bitRange>[5:5]</bitRange>
23865                <access>read-write</access>
23866              </field>
23867            </fields>
23868          </register>
23869          <register>
23870            <name>ARB_EP1_SR</name>
23871            <description>Endpoint Interrupt Enable Register  *1</description>
23872            <addressOffset>0x208</addressOffset>
23873            <size>32</size>
23874            <access>read-write</access>
23875            <resetValue>0x0</resetValue>
23876            <resetMask>0x2F</resetMask>
23877            <fields>
23878              <field>
23879                <name>IN_BUF_FULL</name>
23880                <description>IN Endpoint Local Buffer Full Interrupt</description>
23881                <bitRange>[0:0]</bitRange>
23882                <access>read-write</access>
23883              </field>
23884              <field>
23885                <name>DMA_GNT</name>
23886                <description>Endpoint DMA Grant Interrupt</description>
23887                <bitRange>[1:1]</bitRange>
23888                <access>read-write</access>
23889              </field>
23890              <field>
23891                <name>BUF_OVER</name>
23892                <description>Endpoint Buffer Overflow Interrupt</description>
23893                <bitRange>[2:2]</bitRange>
23894                <access>read-write</access>
23895              </field>
23896              <field>
23897                <name>BUF_UNDER</name>
23898                <description>Endpoint Buffer Underflow Interrupt</description>
23899                <bitRange>[3:3]</bitRange>
23900                <access>read-write</access>
23901              </field>
23902              <field>
23903                <name>DMA_TERMIN</name>
23904                <description>Endpoint DMA Terminated Interrupt</description>
23905                <bitRange>[5:5]</bitRange>
23906                <access>read-write</access>
23907              </field>
23908            </fields>
23909          </register>
23910          <register>
23911            <name>ARB_RW1_WA</name>
23912            <description>Endpoint Write Address value  *1, *2</description>
23913            <addressOffset>0x210</addressOffset>
23914            <size>32</size>
23915            <access>read-write</access>
23916            <resetValue>0x0</resetValue>
23917            <resetMask>0xFF</resetMask>
23918            <fields>
23919              <field>
23920                <name>WA</name>
23921                <description>Write Address for EP</description>
23922                <bitRange>[7:0]</bitRange>
23923                <access>read-write</access>
23924              </field>
23925            </fields>
23926          </register>
23927          <register>
23928            <name>ARB_RW1_WA_MSB</name>
23929            <description>Endpoint Write Address value  *1, *2</description>
23930            <addressOffset>0x214</addressOffset>
23931            <size>32</size>
23932            <access>read-write</access>
23933            <resetValue>0x0</resetValue>
23934            <resetMask>0x1</resetMask>
23935            <fields>
23936              <field>
23937                <name>WA_MSB</name>
23938                <description>Write Address for EP</description>
23939                <bitRange>[0:0]</bitRange>
23940                <access>read-write</access>
23941              </field>
23942            </fields>
23943          </register>
23944          <register>
23945            <name>ARB_RW1_RA</name>
23946            <description>Endpoint Read Address value  *1, *2</description>
23947            <addressOffset>0x218</addressOffset>
23948            <size>32</size>
23949            <access>read-write</access>
23950            <resetValue>0x0</resetValue>
23951            <resetMask>0xFF</resetMask>
23952            <fields>
23953              <field>
23954                <name>RA</name>
23955                <description>Read Address for EP</description>
23956                <bitRange>[7:0]</bitRange>
23957                <access>read-write</access>
23958              </field>
23959            </fields>
23960          </register>
23961          <register>
23962            <name>ARB_RW1_RA_MSB</name>
23963            <description>Endpoint Read Address value  *1, *2</description>
23964            <addressOffset>0x21C</addressOffset>
23965            <size>32</size>
23966            <access>read-write</access>
23967            <resetValue>0x0</resetValue>
23968            <resetMask>0x1</resetMask>
23969            <fields>
23970              <field>
23971                <name>RA_MSB</name>
23972                <description>Read Address for EP</description>
23973                <bitRange>[0:0]</bitRange>
23974                <access>read-write</access>
23975              </field>
23976            </fields>
23977          </register>
23978          <register>
23979            <name>ARB_RW1_DR</name>
23980            <description>Endpoint Data Register</description>
23981            <addressOffset>0x220</addressOffset>
23982            <size>32</size>
23983            <access>read-write</access>
23984            <resetValue>0x0</resetValue>
23985            <resetMask>0x0</resetMask>
23986            <fields>
23987              <field>
23988                <name>DR</name>
23989                <description>Data Register for EP ; This register is linked to the memory, hence reset value is undefined</description>
23990                <bitRange>[7:0]</bitRange>
23991                <access>read-write</access>
23992              </field>
23993            </fields>
23994          </register>
23995          <register>
23996            <name>BUF_SIZE</name>
23997            <description>Dedicated Endpoint Buffer Size Register  *1</description>
23998            <addressOffset>0x230</addressOffset>
23999            <size>32</size>
24000            <access>read-write</access>
24001            <resetValue>0x0</resetValue>
24002            <resetMask>0xFF</resetMask>
24003            <fields>
24004              <field>
24005                <name>IN_BUF</name>
24006                <description>Buffer size for IN Endpoints.</description>
24007                <bitRange>[3:0]</bitRange>
24008                <access>read-write</access>
24009              </field>
24010              <field>
24011                <name>OUT_BUF</name>
24012                <description>Buffer size for OUT Endpoints.</description>
24013                <bitRange>[7:4]</bitRange>
24014                <access>read-write</access>
24015              </field>
24016            </fields>
24017          </register>
24018          <register>
24019            <name>EP_ACTIVE</name>
24020            <description>Endpoint Active Indication Register  *1</description>
24021            <addressOffset>0x238</addressOffset>
24022            <size>32</size>
24023            <access>read-write</access>
24024            <resetValue>0x0</resetValue>
24025            <resetMask>0xFF</resetMask>
24026            <fields>
24027              <field>
24028                <name>EP1_ACT</name>
24029                <description>Indicates that Endpoint is currently active.</description>
24030                <bitRange>[0:0]</bitRange>
24031                <access>read-write</access>
24032              </field>
24033              <field>
24034                <name>EP2_ACT</name>
24035                <description>Indicates that Endpoint is currently active.</description>
24036                <bitRange>[1:1]</bitRange>
24037                <access>read-write</access>
24038              </field>
24039              <field>
24040                <name>EP3_ACT</name>
24041                <description>Indicates that Endpoint is currently active.</description>
24042                <bitRange>[2:2]</bitRange>
24043                <access>read-write</access>
24044              </field>
24045              <field>
24046                <name>EP4_ACT</name>
24047                <description>Indicates that Endpoint is currently active.</description>
24048                <bitRange>[3:3]</bitRange>
24049                <access>read-write</access>
24050              </field>
24051              <field>
24052                <name>EP5_ACT</name>
24053                <description>Indicates that Endpoint is currently active.</description>
24054                <bitRange>[4:4]</bitRange>
24055                <access>read-write</access>
24056              </field>
24057              <field>
24058                <name>EP6_ACT</name>
24059                <description>Indicates that Endpoint is currently active.</description>
24060                <bitRange>[5:5]</bitRange>
24061                <access>read-write</access>
24062              </field>
24063              <field>
24064                <name>EP7_ACT</name>
24065                <description>Indicates that Endpoint is currently active.</description>
24066                <bitRange>[6:6]</bitRange>
24067                <access>read-write</access>
24068              </field>
24069              <field>
24070                <name>EP8_ACT</name>
24071                <description>Indicates that Endpoint is currently active.</description>
24072                <bitRange>[7:7]</bitRange>
24073                <access>read-write</access>
24074              </field>
24075            </fields>
24076          </register>
24077          <register>
24078            <name>EP_TYPE</name>
24079            <description>Endpoint Type (IN/OUT) Indication  *1</description>
24080            <addressOffset>0x23C</addressOffset>
24081            <size>32</size>
24082            <access>read-write</access>
24083            <resetValue>0x0</resetValue>
24084            <resetMask>0xFF</resetMask>
24085            <fields>
24086              <field>
24087                <name>EP1_TYP</name>
24088                <description>Endpoint Type Indication.</description>
24089                <bitRange>[0:0]</bitRange>
24090                <access>read-write</access>
24091                <enumeratedValues>
24092                  <enumeratedValue>
24093                    <name>EP_IN</name>
24094                    <description>IN outpoint</description>
24095                    <value>0</value>
24096                  </enumeratedValue>
24097                  <enumeratedValue>
24098                    <name>EP_OUT</name>
24099                    <description>OUT outpoint</description>
24100                    <value>1</value>
24101                  </enumeratedValue>
24102                </enumeratedValues>
24103              </field>
24104              <field>
24105                <name>EP2_TYP</name>
24106                <description>Endpoint Type Indication.</description>
24107                <bitRange>[1:1]</bitRange>
24108                <access>read-write</access>
24109                <enumeratedValues>
24110                  <enumeratedValue>
24111                    <name>EP_IN</name>
24112                    <description>IN outpoint</description>
24113                    <value>0</value>
24114                  </enumeratedValue>
24115                  <enumeratedValue>
24116                    <name>EP_OUT</name>
24117                    <description>OUT outpoint</description>
24118                    <value>1</value>
24119                  </enumeratedValue>
24120                </enumeratedValues>
24121              </field>
24122              <field>
24123                <name>EP3_TYP</name>
24124                <description>Endpoint Type Indication.</description>
24125                <bitRange>[2:2]</bitRange>
24126                <access>read-write</access>
24127                <enumeratedValues>
24128                  <enumeratedValue>
24129                    <name>EP_IN</name>
24130                    <description>IN outpoint</description>
24131                    <value>0</value>
24132                  </enumeratedValue>
24133                  <enumeratedValue>
24134                    <name>EP_OUT</name>
24135                    <description>OUT outpoint</description>
24136                    <value>1</value>
24137                  </enumeratedValue>
24138                </enumeratedValues>
24139              </field>
24140              <field>
24141                <name>EP4_TYP</name>
24142                <description>Endpoint Type Indication.</description>
24143                <bitRange>[3:3]</bitRange>
24144                <access>read-write</access>
24145                <enumeratedValues>
24146                  <enumeratedValue>
24147                    <name>EP_IN</name>
24148                    <description>IN outpoint</description>
24149                    <value>0</value>
24150                  </enumeratedValue>
24151                  <enumeratedValue>
24152                    <name>EP_OUT</name>
24153                    <description>OUT outpoint</description>
24154                    <value>1</value>
24155                  </enumeratedValue>
24156                </enumeratedValues>
24157              </field>
24158              <field>
24159                <name>EP5_TYP</name>
24160                <description>Endpoint Type Indication.</description>
24161                <bitRange>[4:4]</bitRange>
24162                <access>read-write</access>
24163                <enumeratedValues>
24164                  <enumeratedValue>
24165                    <name>EP_IN</name>
24166                    <description>IN outpoint</description>
24167                    <value>0</value>
24168                  </enumeratedValue>
24169                  <enumeratedValue>
24170                    <name>EP_OUT</name>
24171                    <description>OUT outpoint</description>
24172                    <value>1</value>
24173                  </enumeratedValue>
24174                </enumeratedValues>
24175              </field>
24176              <field>
24177                <name>EP6_TYP</name>
24178                <description>Endpoint Type Indication.</description>
24179                <bitRange>[5:5]</bitRange>
24180                <access>read-write</access>
24181                <enumeratedValues>
24182                  <enumeratedValue>
24183                    <name>EP_IN</name>
24184                    <description>IN outpoint</description>
24185                    <value>0</value>
24186                  </enumeratedValue>
24187                  <enumeratedValue>
24188                    <name>EP_OUT</name>
24189                    <description>OUT outpoint</description>
24190                    <value>1</value>
24191                  </enumeratedValue>
24192                </enumeratedValues>
24193              </field>
24194              <field>
24195                <name>EP7_TYP</name>
24196                <description>Endpoint Type Indication.</description>
24197                <bitRange>[6:6]</bitRange>
24198                <access>read-write</access>
24199                <enumeratedValues>
24200                  <enumeratedValue>
24201                    <name>EP_IN</name>
24202                    <description>IN outpoint</description>
24203                    <value>0</value>
24204                  </enumeratedValue>
24205                  <enumeratedValue>
24206                    <name>EP_OUT</name>
24207                    <description>OUT outpoint</description>
24208                    <value>1</value>
24209                  </enumeratedValue>
24210                </enumeratedValues>
24211              </field>
24212              <field>
24213                <name>EP8_TYP</name>
24214                <description>Endpoint Type Indication.</description>
24215                <bitRange>[7:7]</bitRange>
24216                <access>read-write</access>
24217                <enumeratedValues>
24218                  <enumeratedValue>
24219                    <name>EP_IN</name>
24220                    <description>IN outpoint</description>
24221                    <value>0</value>
24222                  </enumeratedValue>
24223                  <enumeratedValue>
24224                    <name>EP_OUT</name>
24225                    <description>OUT outpoint</description>
24226                    <value>1</value>
24227                  </enumeratedValue>
24228                </enumeratedValues>
24229              </field>
24230            </fields>
24231          </register>
24232          <register>
24233            <name>ARB_EP2_CFG</name>
24234            <description>Endpoint Configuration Register  *1</description>
24235            <addressOffset>0x240</addressOffset>
24236            <size>32</size>
24237            <access>read-write</access>
24238            <resetValue>0x0</resetValue>
24239            <resetMask>0xF</resetMask>
24240            <fields>
24241              <field>
24242                <name>IN_DATA_RDY</name>
24243                <description>Indication that Endpoint Packet Data is Ready in Main memory</description>
24244                <bitRange>[0:0]</bitRange>
24245                <access>read-write</access>
24246              </field>
24247              <field>
24248                <name>DMA_REQ</name>
24249                <description>Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated.</description>
24250                <bitRange>[1:1]</bitRange>
24251                <access>read-write</access>
24252              </field>
24253              <field>
24254                <name>CRC_BYPASS</name>
24255                <description>Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware</description>
24256                <bitRange>[2:2]</bitRange>
24257                <access>read-write</access>
24258                <enumeratedValues>
24259                  <enumeratedValue>
24260                    <name>CRC_NORMAL</name>
24261                    <description>No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s</description>
24262                    <value>0</value>
24263                  </enumeratedValue>
24264                  <enumeratedValue>
24265                    <name>CRC_BYPASS</name>
24266                    <description>CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s</description>
24267                    <value>1</value>
24268                  </enumeratedValue>
24269                </enumeratedValues>
24270              </field>
24271              <field>
24272                <name>RESET_PTR</name>
24273                <description>Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction.</description>
24274                <bitRange>[3:3]</bitRange>
24275                <access>read-write</access>
24276                <enumeratedValues>
24277                  <enumeratedValue>
24278                    <name>RESET_KRYPTON</name>
24279                    <description>Do not Reset Pointer; Krypton Backward compatibility mode</description>
24280                    <value>0</value>
24281                  </enumeratedValue>
24282                  <enumeratedValue>
24283                    <name>RESET_NORMAL</name>
24284                    <description>Reset Pointer; recommended value for reduction of CPU Configuration Writes.</description>
24285                    <value>1</value>
24286                  </enumeratedValue>
24287                </enumeratedValues>
24288              </field>
24289            </fields>
24290          </register>
24291          <register>
24292            <name>ARB_EP2_INT_EN</name>
24293            <description>Endpoint Interrupt Enable Register  *1</description>
24294            <addressOffset>0x244</addressOffset>
24295            <size>32</size>
24296            <access>read-write</access>
24297            <resetValue>0x0</resetValue>
24298            <resetMask>0x3F</resetMask>
24299            <fields>
24300              <field>
24301                <name>IN_BUF_FULL_EN</name>
24302                <description>IN Endpoint Local Buffer Full Enable</description>
24303                <bitRange>[0:0]</bitRange>
24304                <access>read-write</access>
24305              </field>
24306              <field>
24307                <name>DMA_GNT_EN</name>
24308                <description>Endpoint DMA Grant Enable</description>
24309                <bitRange>[1:1]</bitRange>
24310                <access>read-write</access>
24311              </field>
24312              <field>
24313                <name>BUF_OVER_EN</name>
24314                <description>Endpoint Buffer Overflow Enable</description>
24315                <bitRange>[2:2]</bitRange>
24316                <access>read-write</access>
24317              </field>
24318              <field>
24319                <name>BUF_UNDER_EN</name>
24320                <description>Endpoint Buffer Underflow Enable</description>
24321                <bitRange>[3:3]</bitRange>
24322                <access>read-write</access>
24323              </field>
24324              <field>
24325                <name>ERR_INT_EN</name>
24326                <description>Endpoint Error in Transaction Interrupt Enable</description>
24327                <bitRange>[4:4]</bitRange>
24328                <access>read-write</access>
24329              </field>
24330              <field>
24331                <name>DMA_TERMIN_EN</name>
24332                <description>Endpoint DMA Terminated Enable</description>
24333                <bitRange>[5:5]</bitRange>
24334                <access>read-write</access>
24335              </field>
24336            </fields>
24337          </register>
24338          <register>
24339            <name>ARB_EP2_SR</name>
24340            <description>Endpoint Interrupt Enable Register  *1</description>
24341            <addressOffset>0x248</addressOffset>
24342            <size>32</size>
24343            <access>read-write</access>
24344            <resetValue>0x0</resetValue>
24345            <resetMask>0x2F</resetMask>
24346            <fields>
24347              <field>
24348                <name>IN_BUF_FULL</name>
24349                <description>IN Endpoint Local Buffer Full Interrupt</description>
24350                <bitRange>[0:0]</bitRange>
24351                <access>read-write</access>
24352              </field>
24353              <field>
24354                <name>DMA_GNT</name>
24355                <description>Endpoint DMA Grant Interrupt</description>
24356                <bitRange>[1:1]</bitRange>
24357                <access>read-write</access>
24358              </field>
24359              <field>
24360                <name>BUF_OVER</name>
24361                <description>Endpoint Buffer Overflow Interrupt</description>
24362                <bitRange>[2:2]</bitRange>
24363                <access>read-write</access>
24364              </field>
24365              <field>
24366                <name>BUF_UNDER</name>
24367                <description>Endpoint Buffer Underflow Interrupt</description>
24368                <bitRange>[3:3]</bitRange>
24369                <access>read-write</access>
24370              </field>
24371              <field>
24372                <name>DMA_TERMIN</name>
24373                <description>Endpoint DMA Terminated Interrupt</description>
24374                <bitRange>[5:5]</bitRange>
24375                <access>read-write</access>
24376              </field>
24377            </fields>
24378          </register>
24379          <register>
24380            <name>ARB_RW2_WA</name>
24381            <description>Endpoint Write Address value  *1, *2</description>
24382            <addressOffset>0x250</addressOffset>
24383            <size>32</size>
24384            <access>read-write</access>
24385            <resetValue>0x0</resetValue>
24386            <resetMask>0xFF</resetMask>
24387            <fields>
24388              <field>
24389                <name>WA</name>
24390                <description>Write Address for EP</description>
24391                <bitRange>[7:0]</bitRange>
24392                <access>read-write</access>
24393              </field>
24394            </fields>
24395          </register>
24396          <register>
24397            <name>ARB_RW2_WA_MSB</name>
24398            <description>Endpoint Write Address value  *1, *2</description>
24399            <addressOffset>0x254</addressOffset>
24400            <size>32</size>
24401            <access>read-write</access>
24402            <resetValue>0x0</resetValue>
24403            <resetMask>0x1</resetMask>
24404            <fields>
24405              <field>
24406                <name>WA_MSB</name>
24407                <description>Write Address for EP</description>
24408                <bitRange>[0:0]</bitRange>
24409                <access>read-write</access>
24410              </field>
24411            </fields>
24412          </register>
24413          <register>
24414            <name>ARB_RW2_RA</name>
24415            <description>Endpoint Read Address value  *1, *2</description>
24416            <addressOffset>0x258</addressOffset>
24417            <size>32</size>
24418            <access>read-write</access>
24419            <resetValue>0x0</resetValue>
24420            <resetMask>0xFF</resetMask>
24421            <fields>
24422              <field>
24423                <name>RA</name>
24424                <description>Read Address for EP</description>
24425                <bitRange>[7:0]</bitRange>
24426                <access>read-write</access>
24427              </field>
24428            </fields>
24429          </register>
24430          <register>
24431            <name>ARB_RW2_RA_MSB</name>
24432            <description>Endpoint Read Address value  *1, *2</description>
24433            <addressOffset>0x25C</addressOffset>
24434            <size>32</size>
24435            <access>read-write</access>
24436            <resetValue>0x0</resetValue>
24437            <resetMask>0x1</resetMask>
24438            <fields>
24439              <field>
24440                <name>RA_MSB</name>
24441                <description>Read Address for EP</description>
24442                <bitRange>[0:0]</bitRange>
24443                <access>read-write</access>
24444              </field>
24445            </fields>
24446          </register>
24447          <register>
24448            <name>ARB_RW2_DR</name>
24449            <description>Endpoint Data Register</description>
24450            <addressOffset>0x260</addressOffset>
24451            <size>32</size>
24452            <access>read-write</access>
24453            <resetValue>0x0</resetValue>
24454            <resetMask>0x0</resetMask>
24455            <fields>
24456              <field>
24457                <name>DR</name>
24458                <description>Data Register for EP ; This register is linked to the memory, hence reset value is undefined</description>
24459                <bitRange>[7:0]</bitRange>
24460                <access>read-write</access>
24461              </field>
24462            </fields>
24463          </register>
24464          <register>
24465            <name>ARB_CFG</name>
24466            <description>Arbiter Configuration Register  *1</description>
24467            <addressOffset>0x270</addressOffset>
24468            <size>32</size>
24469            <access>read-write</access>
24470            <resetValue>0x0</resetValue>
24471            <resetMask>0xF0</resetMask>
24472            <fields>
24473              <field>
24474                <name>AUTO_MEM</name>
24475                <description>Enables Auto Memory Configuration.  Manual memory configuration by default.</description>
24476                <bitRange>[4:4]</bitRange>
24477                <access>read-write</access>
24478              </field>
24479              <field>
24480                <name>DMA_CFG</name>
24481                <description>DMA Access Configuration.</description>
24482                <bitRange>[6:5]</bitRange>
24483                <access>read-write</access>
24484                <enumeratedValues>
24485                  <enumeratedValue>
24486                    <name>DMA_NONE</name>
24487                    <description>No DMA</description>
24488                    <value>0</value>
24489                  </enumeratedValue>
24490                  <enumeratedValue>
24491                    <name>DMA_MANUAL</name>
24492                    <description>Manual DMA</description>
24493                    <value>1</value>
24494                  </enumeratedValue>
24495                  <enumeratedValue>
24496                    <name>DMA_AUTO</name>
24497                    <description>Auto DMA</description>
24498                    <value>2</value>
24499                  </enumeratedValue>
24500                </enumeratedValues>
24501              </field>
24502              <field>
24503                <name>CFG_CMP</name>
24504                <description>Register Configuration Complete Indication. Posedge is detected on this bit. Hence a 0 to 1 transition is required.</description>
24505                <bitRange>[7:7]</bitRange>
24506                <access>read-write</access>
24507              </field>
24508            </fields>
24509          </register>
24510          <register>
24511            <name>USB_CLK_EN</name>
24512            <description>USB Block Clock Enable Register</description>
24513            <addressOffset>0x274</addressOffset>
24514            <size>32</size>
24515            <access>read-write</access>
24516            <resetValue>0x0</resetValue>
24517            <resetMask>0x1</resetMask>
24518            <fields>
24519              <field>
24520                <name>CSR_CLK_EN</name>
24521                <description>Clock Enable for Core Logic clocked by AHB bus clock</description>
24522                <bitRange>[0:0]</bitRange>
24523                <access>read-write</access>
24524              </field>
24525            </fields>
24526          </register>
24527          <register>
24528            <name>ARB_INT_EN</name>
24529            <description>Arbiter Interrupt Enable  *1</description>
24530            <addressOffset>0x278</addressOffset>
24531            <size>32</size>
24532            <access>read-write</access>
24533            <resetValue>0x0</resetValue>
24534            <resetMask>0xFF</resetMask>
24535            <fields>
24536              <field>
24537                <name>EP1_INTR_EN</name>
24538                <description>Enables interrupt for EP1</description>
24539                <bitRange>[0:0]</bitRange>
24540                <access>read-write</access>
24541              </field>
24542              <field>
24543                <name>EP2_INTR_EN</name>
24544                <description>Enables interrupt for EP2</description>
24545                <bitRange>[1:1]</bitRange>
24546                <access>read-write</access>
24547              </field>
24548              <field>
24549                <name>EP3_INTR_EN</name>
24550                <description>Enables interrupt for EP3</description>
24551                <bitRange>[2:2]</bitRange>
24552                <access>read-write</access>
24553              </field>
24554              <field>
24555                <name>EP4_INTR_EN</name>
24556                <description>Enables interrupt for EP4</description>
24557                <bitRange>[3:3]</bitRange>
24558                <access>read-write</access>
24559              </field>
24560              <field>
24561                <name>EP5_INTR_EN</name>
24562                <description>Enables interrupt for EP5</description>
24563                <bitRange>[4:4]</bitRange>
24564                <access>read-write</access>
24565              </field>
24566              <field>
24567                <name>EP6_INTR_EN</name>
24568                <description>Enables interrupt for EP6</description>
24569                <bitRange>[5:5]</bitRange>
24570                <access>read-write</access>
24571              </field>
24572              <field>
24573                <name>EP7_INTR_EN</name>
24574                <description>Enables interrupt for EP7</description>
24575                <bitRange>[6:6]</bitRange>
24576                <access>read-write</access>
24577              </field>
24578              <field>
24579                <name>EP8_INTR_EN</name>
24580                <description>Enables interrupt for EP8</description>
24581                <bitRange>[7:7]</bitRange>
24582                <access>read-write</access>
24583              </field>
24584            </fields>
24585          </register>
24586          <register>
24587            <name>ARB_INT_SR</name>
24588            <description>Arbiter Interrupt Status  *1</description>
24589            <addressOffset>0x27C</addressOffset>
24590            <size>32</size>
24591            <access>read-only</access>
24592            <resetValue>0x0</resetValue>
24593            <resetMask>0xFF</resetMask>
24594            <fields>
24595              <field>
24596                <name>EP1_INTR</name>
24597                <description>Interrupt status for EP1</description>
24598                <bitRange>[0:0]</bitRange>
24599                <access>read-only</access>
24600              </field>
24601              <field>
24602                <name>EP2_INTR</name>
24603                <description>Interrupt status for EP2</description>
24604                <bitRange>[1:1]</bitRange>
24605                <access>read-only</access>
24606              </field>
24607              <field>
24608                <name>EP3_INTR</name>
24609                <description>Interrupt status for EP3</description>
24610                <bitRange>[2:2]</bitRange>
24611                <access>read-only</access>
24612              </field>
24613              <field>
24614                <name>EP4_INTR</name>
24615                <description>Interrupt status for EP4</description>
24616                <bitRange>[3:3]</bitRange>
24617                <access>read-only</access>
24618              </field>
24619              <field>
24620                <name>EP5_INTR</name>
24621                <description>Interrupt status for EP5</description>
24622                <bitRange>[4:4]</bitRange>
24623                <access>read-only</access>
24624              </field>
24625              <field>
24626                <name>EP6_INTR</name>
24627                <description>Interrupt status for EP6</description>
24628                <bitRange>[5:5]</bitRange>
24629                <access>read-only</access>
24630              </field>
24631              <field>
24632                <name>EP7_INTR</name>
24633                <description>Interrupt status for EP7</description>
24634                <bitRange>[6:6]</bitRange>
24635                <access>read-only</access>
24636              </field>
24637              <field>
24638                <name>EP8_INTR</name>
24639                <description>Interrupt status for EP8</description>
24640                <bitRange>[7:7]</bitRange>
24641                <access>read-only</access>
24642              </field>
24643            </fields>
24644          </register>
24645          <register>
24646            <name>ARB_EP3_CFG</name>
24647            <description>Endpoint Configuration Register  *1</description>
24648            <addressOffset>0x280</addressOffset>
24649            <size>32</size>
24650            <access>read-write</access>
24651            <resetValue>0x0</resetValue>
24652            <resetMask>0xF</resetMask>
24653            <fields>
24654              <field>
24655                <name>IN_DATA_RDY</name>
24656                <description>Indication that Endpoint Packet Data is Ready in Main memory</description>
24657                <bitRange>[0:0]</bitRange>
24658                <access>read-write</access>
24659              </field>
24660              <field>
24661                <name>DMA_REQ</name>
24662                <description>Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated.</description>
24663                <bitRange>[1:1]</bitRange>
24664                <access>read-write</access>
24665              </field>
24666              <field>
24667                <name>CRC_BYPASS</name>
24668                <description>Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware</description>
24669                <bitRange>[2:2]</bitRange>
24670                <access>read-write</access>
24671                <enumeratedValues>
24672                  <enumeratedValue>
24673                    <name>CRC_NORMAL</name>
24674                    <description>No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s</description>
24675                    <value>0</value>
24676                  </enumeratedValue>
24677                  <enumeratedValue>
24678                    <name>CRC_BYPASS</name>
24679                    <description>CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s</description>
24680                    <value>1</value>
24681                  </enumeratedValue>
24682                </enumeratedValues>
24683              </field>
24684              <field>
24685                <name>RESET_PTR</name>
24686                <description>Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction.</description>
24687                <bitRange>[3:3]</bitRange>
24688                <access>read-write</access>
24689                <enumeratedValues>
24690                  <enumeratedValue>
24691                    <name>RESET_KRYPTON</name>
24692                    <description>Do not Reset Pointer; Krypton Backward compatibility mode</description>
24693                    <value>0</value>
24694                  </enumeratedValue>
24695                  <enumeratedValue>
24696                    <name>RESET_NORMAL</name>
24697                    <description>Reset Pointer; recommended value for reduction of CPU Configuration Writes.</description>
24698                    <value>1</value>
24699                  </enumeratedValue>
24700                </enumeratedValues>
24701              </field>
24702            </fields>
24703          </register>
24704          <register>
24705            <name>ARB_EP3_INT_EN</name>
24706            <description>Endpoint Interrupt Enable Register  *1</description>
24707            <addressOffset>0x284</addressOffset>
24708            <size>32</size>
24709            <access>read-write</access>
24710            <resetValue>0x0</resetValue>
24711            <resetMask>0x3F</resetMask>
24712            <fields>
24713              <field>
24714                <name>IN_BUF_FULL_EN</name>
24715                <description>IN Endpoint Local Buffer Full Enable</description>
24716                <bitRange>[0:0]</bitRange>
24717                <access>read-write</access>
24718              </field>
24719              <field>
24720                <name>DMA_GNT_EN</name>
24721                <description>Endpoint DMA Grant Enable</description>
24722                <bitRange>[1:1]</bitRange>
24723                <access>read-write</access>
24724              </field>
24725              <field>
24726                <name>BUF_OVER_EN</name>
24727                <description>Endpoint Buffer Overflow Enable</description>
24728                <bitRange>[2:2]</bitRange>
24729                <access>read-write</access>
24730              </field>
24731              <field>
24732                <name>BUF_UNDER_EN</name>
24733                <description>Endpoint Buffer Underflow Enable</description>
24734                <bitRange>[3:3]</bitRange>
24735                <access>read-write</access>
24736              </field>
24737              <field>
24738                <name>ERR_INT_EN</name>
24739                <description>Endpoint Error in Transaction Interrupt Enable</description>
24740                <bitRange>[4:4]</bitRange>
24741                <access>read-write</access>
24742              </field>
24743              <field>
24744                <name>DMA_TERMIN_EN</name>
24745                <description>Endpoint DMA Terminated Enable</description>
24746                <bitRange>[5:5]</bitRange>
24747                <access>read-write</access>
24748              </field>
24749            </fields>
24750          </register>
24751          <register>
24752            <name>ARB_EP3_SR</name>
24753            <description>Endpoint Interrupt Enable Register  *1</description>
24754            <addressOffset>0x288</addressOffset>
24755            <size>32</size>
24756            <access>read-write</access>
24757            <resetValue>0x0</resetValue>
24758            <resetMask>0x2F</resetMask>
24759            <fields>
24760              <field>
24761                <name>IN_BUF_FULL</name>
24762                <description>IN Endpoint Local Buffer Full Interrupt</description>
24763                <bitRange>[0:0]</bitRange>
24764                <access>read-write</access>
24765              </field>
24766              <field>
24767                <name>DMA_GNT</name>
24768                <description>Endpoint DMA Grant Interrupt</description>
24769                <bitRange>[1:1]</bitRange>
24770                <access>read-write</access>
24771              </field>
24772              <field>
24773                <name>BUF_OVER</name>
24774                <description>Endpoint Buffer Overflow Interrupt</description>
24775                <bitRange>[2:2]</bitRange>
24776                <access>read-write</access>
24777              </field>
24778              <field>
24779                <name>BUF_UNDER</name>
24780                <description>Endpoint Buffer Underflow Interrupt</description>
24781                <bitRange>[3:3]</bitRange>
24782                <access>read-write</access>
24783              </field>
24784              <field>
24785                <name>DMA_TERMIN</name>
24786                <description>Endpoint DMA Terminated Interrupt</description>
24787                <bitRange>[5:5]</bitRange>
24788                <access>read-write</access>
24789              </field>
24790            </fields>
24791          </register>
24792          <register>
24793            <name>ARB_RW3_WA</name>
24794            <description>Endpoint Write Address value  *1, *2</description>
24795            <addressOffset>0x290</addressOffset>
24796            <size>32</size>
24797            <access>read-write</access>
24798            <resetValue>0x0</resetValue>
24799            <resetMask>0xFF</resetMask>
24800            <fields>
24801              <field>
24802                <name>WA</name>
24803                <description>Write Address for EP</description>
24804                <bitRange>[7:0]</bitRange>
24805                <access>read-write</access>
24806              </field>
24807            </fields>
24808          </register>
24809          <register>
24810            <name>ARB_RW3_WA_MSB</name>
24811            <description>Endpoint Write Address value  *1, *2</description>
24812            <addressOffset>0x294</addressOffset>
24813            <size>32</size>
24814            <access>read-write</access>
24815            <resetValue>0x0</resetValue>
24816            <resetMask>0x1</resetMask>
24817            <fields>
24818              <field>
24819                <name>WA_MSB</name>
24820                <description>Write Address for EP</description>
24821                <bitRange>[0:0]</bitRange>
24822                <access>read-write</access>
24823              </field>
24824            </fields>
24825          </register>
24826          <register>
24827            <name>ARB_RW3_RA</name>
24828            <description>Endpoint Read Address value  *1, *2</description>
24829            <addressOffset>0x298</addressOffset>
24830            <size>32</size>
24831            <access>read-write</access>
24832            <resetValue>0x0</resetValue>
24833            <resetMask>0xFF</resetMask>
24834            <fields>
24835              <field>
24836                <name>RA</name>
24837                <description>Read Address for EP</description>
24838                <bitRange>[7:0]</bitRange>
24839                <access>read-write</access>
24840              </field>
24841            </fields>
24842          </register>
24843          <register>
24844            <name>ARB_RW3_RA_MSB</name>
24845            <description>Endpoint Read Address value  *1, *2</description>
24846            <addressOffset>0x29C</addressOffset>
24847            <size>32</size>
24848            <access>read-write</access>
24849            <resetValue>0x0</resetValue>
24850            <resetMask>0x1</resetMask>
24851            <fields>
24852              <field>
24853                <name>RA_MSB</name>
24854                <description>Read Address for EP</description>
24855                <bitRange>[0:0]</bitRange>
24856                <access>read-write</access>
24857              </field>
24858            </fields>
24859          </register>
24860          <register>
24861            <name>ARB_RW3_DR</name>
24862            <description>Endpoint Data Register</description>
24863            <addressOffset>0x2A0</addressOffset>
24864            <size>32</size>
24865            <access>read-write</access>
24866            <resetValue>0x0</resetValue>
24867            <resetMask>0x0</resetMask>
24868            <fields>
24869              <field>
24870                <name>DR</name>
24871                <description>Data Register for EP ; This register is linked to the memory, hence reset value is undefined</description>
24872                <bitRange>[7:0]</bitRange>
24873                <access>read-write</access>
24874              </field>
24875            </fields>
24876          </register>
24877          <register>
24878            <name>CWA</name>
24879            <description>Common Area Write Address  *1</description>
24880            <addressOffset>0x2B0</addressOffset>
24881            <size>32</size>
24882            <access>read-write</access>
24883            <resetValue>0x0</resetValue>
24884            <resetMask>0xFF</resetMask>
24885            <fields>
24886              <field>
24887                <name>CWA</name>
24888                <description>Write Address for Common Area</description>
24889                <bitRange>[7:0]</bitRange>
24890                <access>read-write</access>
24891              </field>
24892            </fields>
24893          </register>
24894          <register>
24895            <name>CWA_MSB</name>
24896            <description>Endpoint Read Address value  *1</description>
24897            <addressOffset>0x2B4</addressOffset>
24898            <size>32</size>
24899            <access>read-write</access>
24900            <resetValue>0x0</resetValue>
24901            <resetMask>0x1</resetMask>
24902            <fields>
24903              <field>
24904                <name>CWA_MSB</name>
24905                <description>Write Address for Common Area</description>
24906                <bitRange>[0:0]</bitRange>
24907                <access>read-write</access>
24908              </field>
24909            </fields>
24910          </register>
24911          <register>
24912            <name>ARB_EP4_CFG</name>
24913            <description>Endpoint Configuration Register  *1</description>
24914            <addressOffset>0x2C0</addressOffset>
24915            <size>32</size>
24916            <access>read-write</access>
24917            <resetValue>0x0</resetValue>
24918            <resetMask>0xF</resetMask>
24919            <fields>
24920              <field>
24921                <name>IN_DATA_RDY</name>
24922                <description>Indication that Endpoint Packet Data is Ready in Main memory</description>
24923                <bitRange>[0:0]</bitRange>
24924                <access>read-write</access>
24925              </field>
24926              <field>
24927                <name>DMA_REQ</name>
24928                <description>Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated.</description>
24929                <bitRange>[1:1]</bitRange>
24930                <access>read-write</access>
24931              </field>
24932              <field>
24933                <name>CRC_BYPASS</name>
24934                <description>Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware</description>
24935                <bitRange>[2:2]</bitRange>
24936                <access>read-write</access>
24937                <enumeratedValues>
24938                  <enumeratedValue>
24939                    <name>CRC_NORMAL</name>
24940                    <description>No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s</description>
24941                    <value>0</value>
24942                  </enumeratedValue>
24943                  <enumeratedValue>
24944                    <name>CRC_BYPASS</name>
24945                    <description>CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s</description>
24946                    <value>1</value>
24947                  </enumeratedValue>
24948                </enumeratedValues>
24949              </field>
24950              <field>
24951                <name>RESET_PTR</name>
24952                <description>Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction.</description>
24953                <bitRange>[3:3]</bitRange>
24954                <access>read-write</access>
24955                <enumeratedValues>
24956                  <enumeratedValue>
24957                    <name>RESET_KRYPTON</name>
24958                    <description>Do not Reset Pointer; Krypton Backward compatibility mode</description>
24959                    <value>0</value>
24960                  </enumeratedValue>
24961                  <enumeratedValue>
24962                    <name>RESET_NORMAL</name>
24963                    <description>Reset Pointer; recommended value for reduction of CPU Configuration Writes.</description>
24964                    <value>1</value>
24965                  </enumeratedValue>
24966                </enumeratedValues>
24967              </field>
24968            </fields>
24969          </register>
24970          <register>
24971            <name>ARB_EP4_INT_EN</name>
24972            <description>Endpoint Interrupt Enable Register  *1</description>
24973            <addressOffset>0x2C4</addressOffset>
24974            <size>32</size>
24975            <access>read-write</access>
24976            <resetValue>0x0</resetValue>
24977            <resetMask>0x3F</resetMask>
24978            <fields>
24979              <field>
24980                <name>IN_BUF_FULL_EN</name>
24981                <description>IN Endpoint Local Buffer Full Enable</description>
24982                <bitRange>[0:0]</bitRange>
24983                <access>read-write</access>
24984              </field>
24985              <field>
24986                <name>DMA_GNT_EN</name>
24987                <description>Endpoint DMA Grant Enable</description>
24988                <bitRange>[1:1]</bitRange>
24989                <access>read-write</access>
24990              </field>
24991              <field>
24992                <name>BUF_OVER_EN</name>
24993                <description>Endpoint Buffer Overflow Enable</description>
24994                <bitRange>[2:2]</bitRange>
24995                <access>read-write</access>
24996              </field>
24997              <field>
24998                <name>BUF_UNDER_EN</name>
24999                <description>Endpoint Buffer Underflow Enable</description>
25000                <bitRange>[3:3]</bitRange>
25001                <access>read-write</access>
25002              </field>
25003              <field>
25004                <name>ERR_INT_EN</name>
25005                <description>Endpoint Error in Transaction Interrupt Enable</description>
25006                <bitRange>[4:4]</bitRange>
25007                <access>read-write</access>
25008              </field>
25009              <field>
25010                <name>DMA_TERMIN_EN</name>
25011                <description>Endpoint DMA Terminated Enable</description>
25012                <bitRange>[5:5]</bitRange>
25013                <access>read-write</access>
25014              </field>
25015            </fields>
25016          </register>
25017          <register>
25018            <name>ARB_EP4_SR</name>
25019            <description>Endpoint Interrupt Enable Register  *1</description>
25020            <addressOffset>0x2C8</addressOffset>
25021            <size>32</size>
25022            <access>read-write</access>
25023            <resetValue>0x0</resetValue>
25024            <resetMask>0x2F</resetMask>
25025            <fields>
25026              <field>
25027                <name>IN_BUF_FULL</name>
25028                <description>IN Endpoint Local Buffer Full Interrupt</description>
25029                <bitRange>[0:0]</bitRange>
25030                <access>read-write</access>
25031              </field>
25032              <field>
25033                <name>DMA_GNT</name>
25034                <description>Endpoint DMA Grant Interrupt</description>
25035                <bitRange>[1:1]</bitRange>
25036                <access>read-write</access>
25037              </field>
25038              <field>
25039                <name>BUF_OVER</name>
25040                <description>Endpoint Buffer Overflow Interrupt</description>
25041                <bitRange>[2:2]</bitRange>
25042                <access>read-write</access>
25043              </field>
25044              <field>
25045                <name>BUF_UNDER</name>
25046                <description>Endpoint Buffer Underflow Interrupt</description>
25047                <bitRange>[3:3]</bitRange>
25048                <access>read-write</access>
25049              </field>
25050              <field>
25051                <name>DMA_TERMIN</name>
25052                <description>Endpoint DMA Terminated Interrupt</description>
25053                <bitRange>[5:5]</bitRange>
25054                <access>read-write</access>
25055              </field>
25056            </fields>
25057          </register>
25058          <register>
25059            <name>ARB_RW4_WA</name>
25060            <description>Endpoint Write Address value  *1, *2</description>
25061            <addressOffset>0x2D0</addressOffset>
25062            <size>32</size>
25063            <access>read-write</access>
25064            <resetValue>0x0</resetValue>
25065            <resetMask>0xFF</resetMask>
25066            <fields>
25067              <field>
25068                <name>WA</name>
25069                <description>Write Address for EP</description>
25070                <bitRange>[7:0]</bitRange>
25071                <access>read-write</access>
25072              </field>
25073            </fields>
25074          </register>
25075          <register>
25076            <name>ARB_RW4_WA_MSB</name>
25077            <description>Endpoint Write Address value  *1, *2</description>
25078            <addressOffset>0x2D4</addressOffset>
25079            <size>32</size>
25080            <access>read-write</access>
25081            <resetValue>0x0</resetValue>
25082            <resetMask>0x1</resetMask>
25083            <fields>
25084              <field>
25085                <name>WA_MSB</name>
25086                <description>Write Address for EP</description>
25087                <bitRange>[0:0]</bitRange>
25088                <access>read-write</access>
25089              </field>
25090            </fields>
25091          </register>
25092          <register>
25093            <name>ARB_RW4_RA</name>
25094            <description>Endpoint Read Address value  *1, *2</description>
25095            <addressOffset>0x2D8</addressOffset>
25096            <size>32</size>
25097            <access>read-write</access>
25098            <resetValue>0x0</resetValue>
25099            <resetMask>0xFF</resetMask>
25100            <fields>
25101              <field>
25102                <name>RA</name>
25103                <description>Read Address for EP</description>
25104                <bitRange>[7:0]</bitRange>
25105                <access>read-write</access>
25106              </field>
25107            </fields>
25108          </register>
25109          <register>
25110            <name>ARB_RW4_RA_MSB</name>
25111            <description>Endpoint Read Address value  *1, *2</description>
25112            <addressOffset>0x2DC</addressOffset>
25113            <size>32</size>
25114            <access>read-write</access>
25115            <resetValue>0x0</resetValue>
25116            <resetMask>0x1</resetMask>
25117            <fields>
25118              <field>
25119                <name>RA_MSB</name>
25120                <description>Read Address for EP</description>
25121                <bitRange>[0:0]</bitRange>
25122                <access>read-write</access>
25123              </field>
25124            </fields>
25125          </register>
25126          <register>
25127            <name>ARB_RW4_DR</name>
25128            <description>Endpoint Data Register</description>
25129            <addressOffset>0x2E0</addressOffset>
25130            <size>32</size>
25131            <access>read-write</access>
25132            <resetValue>0x0</resetValue>
25133            <resetMask>0x0</resetMask>
25134            <fields>
25135              <field>
25136                <name>DR</name>
25137                <description>Data Register for EP ; This register is linked to the memory, hence reset value is undefined</description>
25138                <bitRange>[7:0]</bitRange>
25139                <access>read-write</access>
25140              </field>
25141            </fields>
25142          </register>
25143          <register>
25144            <name>DMA_THRES</name>
25145            <description>DMA Burst / Threshold Configuration</description>
25146            <addressOffset>0x2F0</addressOffset>
25147            <size>32</size>
25148            <access>read-write</access>
25149            <resetValue>0x0</resetValue>
25150            <resetMask>0xFF</resetMask>
25151            <fields>
25152              <field>
25153                <name>DMA_THS</name>
25154                <description>DMA Threshold count</description>
25155                <bitRange>[7:0]</bitRange>
25156                <access>read-write</access>
25157              </field>
25158            </fields>
25159          </register>
25160          <register>
25161            <name>DMA_THRES_MSB</name>
25162            <description>DMA Burst / Threshold Configuration</description>
25163            <addressOffset>0x2F4</addressOffset>
25164            <size>32</size>
25165            <access>read-write</access>
25166            <resetValue>0x0</resetValue>
25167            <resetMask>0x1</resetMask>
25168            <fields>
25169              <field>
25170                <name>DMA_THS_MSB</name>
25171                <description>DMA Threshold count</description>
25172                <bitRange>[0:0]</bitRange>
25173                <access>read-write</access>
25174              </field>
25175            </fields>
25176          </register>
25177          <register>
25178            <name>ARB_EP5_CFG</name>
25179            <description>Endpoint Configuration Register  *1</description>
25180            <addressOffset>0x300</addressOffset>
25181            <size>32</size>
25182            <access>read-write</access>
25183            <resetValue>0x0</resetValue>
25184            <resetMask>0xF</resetMask>
25185            <fields>
25186              <field>
25187                <name>IN_DATA_RDY</name>
25188                <description>Indication that Endpoint Packet Data is Ready in Main memory</description>
25189                <bitRange>[0:0]</bitRange>
25190                <access>read-write</access>
25191              </field>
25192              <field>
25193                <name>DMA_REQ</name>
25194                <description>Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated.</description>
25195                <bitRange>[1:1]</bitRange>
25196                <access>read-write</access>
25197              </field>
25198              <field>
25199                <name>CRC_BYPASS</name>
25200                <description>Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware</description>
25201                <bitRange>[2:2]</bitRange>
25202                <access>read-write</access>
25203                <enumeratedValues>
25204                  <enumeratedValue>
25205                    <name>CRC_NORMAL</name>
25206                    <description>No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s</description>
25207                    <value>0</value>
25208                  </enumeratedValue>
25209                  <enumeratedValue>
25210                    <name>CRC_BYPASS</name>
25211                    <description>CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s</description>
25212                    <value>1</value>
25213                  </enumeratedValue>
25214                </enumeratedValues>
25215              </field>
25216              <field>
25217                <name>RESET_PTR</name>
25218                <description>Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction.</description>
25219                <bitRange>[3:3]</bitRange>
25220                <access>read-write</access>
25221                <enumeratedValues>
25222                  <enumeratedValue>
25223                    <name>RESET_KRYPTON</name>
25224                    <description>Do not Reset Pointer; Krypton Backward compatibility mode</description>
25225                    <value>0</value>
25226                  </enumeratedValue>
25227                  <enumeratedValue>
25228                    <name>RESET_NORMAL</name>
25229                    <description>Reset Pointer; recommended value for reduction of CPU Configuration Writes.</description>
25230                    <value>1</value>
25231                  </enumeratedValue>
25232                </enumeratedValues>
25233              </field>
25234            </fields>
25235          </register>
25236          <register>
25237            <name>ARB_EP5_INT_EN</name>
25238            <description>Endpoint Interrupt Enable Register  *1</description>
25239            <addressOffset>0x304</addressOffset>
25240            <size>32</size>
25241            <access>read-write</access>
25242            <resetValue>0x0</resetValue>
25243            <resetMask>0x3F</resetMask>
25244            <fields>
25245              <field>
25246                <name>IN_BUF_FULL_EN</name>
25247                <description>IN Endpoint Local Buffer Full Enable</description>
25248                <bitRange>[0:0]</bitRange>
25249                <access>read-write</access>
25250              </field>
25251              <field>
25252                <name>DMA_GNT_EN</name>
25253                <description>Endpoint DMA Grant Enable</description>
25254                <bitRange>[1:1]</bitRange>
25255                <access>read-write</access>
25256              </field>
25257              <field>
25258                <name>BUF_OVER_EN</name>
25259                <description>Endpoint Buffer Overflow Enable</description>
25260                <bitRange>[2:2]</bitRange>
25261                <access>read-write</access>
25262              </field>
25263              <field>
25264                <name>BUF_UNDER_EN</name>
25265                <description>Endpoint Buffer Underflow Enable</description>
25266                <bitRange>[3:3]</bitRange>
25267                <access>read-write</access>
25268              </field>
25269              <field>
25270                <name>ERR_INT_EN</name>
25271                <description>Endpoint Error in Transaction Interrupt Enable</description>
25272                <bitRange>[4:4]</bitRange>
25273                <access>read-write</access>
25274              </field>
25275              <field>
25276                <name>DMA_TERMIN_EN</name>
25277                <description>Endpoint DMA Terminated Enable</description>
25278                <bitRange>[5:5]</bitRange>
25279                <access>read-write</access>
25280              </field>
25281            </fields>
25282          </register>
25283          <register>
25284            <name>ARB_EP5_SR</name>
25285            <description>Endpoint Interrupt Enable Register  *1</description>
25286            <addressOffset>0x308</addressOffset>
25287            <size>32</size>
25288            <access>read-write</access>
25289            <resetValue>0x0</resetValue>
25290            <resetMask>0x2F</resetMask>
25291            <fields>
25292              <field>
25293                <name>IN_BUF_FULL</name>
25294                <description>IN Endpoint Local Buffer Full Interrupt</description>
25295                <bitRange>[0:0]</bitRange>
25296                <access>read-write</access>
25297              </field>
25298              <field>
25299                <name>DMA_GNT</name>
25300                <description>Endpoint DMA Grant Interrupt</description>
25301                <bitRange>[1:1]</bitRange>
25302                <access>read-write</access>
25303              </field>
25304              <field>
25305                <name>BUF_OVER</name>
25306                <description>Endpoint Buffer Overflow Interrupt</description>
25307                <bitRange>[2:2]</bitRange>
25308                <access>read-write</access>
25309              </field>
25310              <field>
25311                <name>BUF_UNDER</name>
25312                <description>Endpoint Buffer Underflow Interrupt</description>
25313                <bitRange>[3:3]</bitRange>
25314                <access>read-write</access>
25315              </field>
25316              <field>
25317                <name>DMA_TERMIN</name>
25318                <description>Endpoint DMA Terminated Interrupt</description>
25319                <bitRange>[5:5]</bitRange>
25320                <access>read-write</access>
25321              </field>
25322            </fields>
25323          </register>
25324          <register>
25325            <name>ARB_RW5_WA</name>
25326            <description>Endpoint Write Address value  *1, *2</description>
25327            <addressOffset>0x310</addressOffset>
25328            <size>32</size>
25329            <access>read-write</access>
25330            <resetValue>0x0</resetValue>
25331            <resetMask>0xFF</resetMask>
25332            <fields>
25333              <field>
25334                <name>WA</name>
25335                <description>Write Address for EP</description>
25336                <bitRange>[7:0]</bitRange>
25337                <access>read-write</access>
25338              </field>
25339            </fields>
25340          </register>
25341          <register>
25342            <name>ARB_RW5_WA_MSB</name>
25343            <description>Endpoint Write Address value  *1, *2</description>
25344            <addressOffset>0x314</addressOffset>
25345            <size>32</size>
25346            <access>read-write</access>
25347            <resetValue>0x0</resetValue>
25348            <resetMask>0x1</resetMask>
25349            <fields>
25350              <field>
25351                <name>WA_MSB</name>
25352                <description>Write Address for EP</description>
25353                <bitRange>[0:0]</bitRange>
25354                <access>read-write</access>
25355              </field>
25356            </fields>
25357          </register>
25358          <register>
25359            <name>ARB_RW5_RA</name>
25360            <description>Endpoint Read Address value  *1, *2</description>
25361            <addressOffset>0x318</addressOffset>
25362            <size>32</size>
25363            <access>read-write</access>
25364            <resetValue>0x0</resetValue>
25365            <resetMask>0xFF</resetMask>
25366            <fields>
25367              <field>
25368                <name>RA</name>
25369                <description>Read Address for EP</description>
25370                <bitRange>[7:0]</bitRange>
25371                <access>read-write</access>
25372              </field>
25373            </fields>
25374          </register>
25375          <register>
25376            <name>ARB_RW5_RA_MSB</name>
25377            <description>Endpoint Read Address value  *1, *2</description>
25378            <addressOffset>0x31C</addressOffset>
25379            <size>32</size>
25380            <access>read-write</access>
25381            <resetValue>0x0</resetValue>
25382            <resetMask>0x1</resetMask>
25383            <fields>
25384              <field>
25385                <name>RA_MSB</name>
25386                <description>Read Address for EP</description>
25387                <bitRange>[0:0]</bitRange>
25388                <access>read-write</access>
25389              </field>
25390            </fields>
25391          </register>
25392          <register>
25393            <name>ARB_RW5_DR</name>
25394            <description>Endpoint Data Register</description>
25395            <addressOffset>0x320</addressOffset>
25396            <size>32</size>
25397            <access>read-write</access>
25398            <resetValue>0x0</resetValue>
25399            <resetMask>0x0</resetMask>
25400            <fields>
25401              <field>
25402                <name>DR</name>
25403                <description>Data Register for EP ; This register is linked to the memory, hence reset value is undefined</description>
25404                <bitRange>[7:0]</bitRange>
25405                <access>read-write</access>
25406              </field>
25407            </fields>
25408          </register>
25409          <register>
25410            <name>BUS_RST_CNT</name>
25411            <description>Bus Reset Count Register</description>
25412            <addressOffset>0x330</addressOffset>
25413            <size>32</size>
25414            <access>read-write</access>
25415            <resetValue>0xA</resetValue>
25416            <resetMask>0xF</resetMask>
25417            <fields>
25418              <field>
25419                <name>BUS_RST_CNT</name>
25420                <description>Bus Reset Count Length</description>
25421                <bitRange>[3:0]</bitRange>
25422                <access>read-write</access>
25423              </field>
25424            </fields>
25425          </register>
25426          <register>
25427            <name>ARB_EP6_CFG</name>
25428            <description>Endpoint Configuration Register  *1</description>
25429            <addressOffset>0x340</addressOffset>
25430            <size>32</size>
25431            <access>read-write</access>
25432            <resetValue>0x0</resetValue>
25433            <resetMask>0xF</resetMask>
25434            <fields>
25435              <field>
25436                <name>IN_DATA_RDY</name>
25437                <description>Indication that Endpoint Packet Data is Ready in Main memory</description>
25438                <bitRange>[0:0]</bitRange>
25439                <access>read-write</access>
25440              </field>
25441              <field>
25442                <name>DMA_REQ</name>
25443                <description>Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated.</description>
25444                <bitRange>[1:1]</bitRange>
25445                <access>read-write</access>
25446              </field>
25447              <field>
25448                <name>CRC_BYPASS</name>
25449                <description>Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware</description>
25450                <bitRange>[2:2]</bitRange>
25451                <access>read-write</access>
25452                <enumeratedValues>
25453                  <enumeratedValue>
25454                    <name>CRC_NORMAL</name>
25455                    <description>No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s</description>
25456                    <value>0</value>
25457                  </enumeratedValue>
25458                  <enumeratedValue>
25459                    <name>CRC_BYPASS</name>
25460                    <description>CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s</description>
25461                    <value>1</value>
25462                  </enumeratedValue>
25463                </enumeratedValues>
25464              </field>
25465              <field>
25466                <name>RESET_PTR</name>
25467                <description>Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction.</description>
25468                <bitRange>[3:3]</bitRange>
25469                <access>read-write</access>
25470                <enumeratedValues>
25471                  <enumeratedValue>
25472                    <name>RESET_KRYPTON</name>
25473                    <description>Do not Reset Pointer; Krypton Backward compatibility mode</description>
25474                    <value>0</value>
25475                  </enumeratedValue>
25476                  <enumeratedValue>
25477                    <name>RESET_NORMAL</name>
25478                    <description>Reset Pointer; recommended value for reduction of CPU Configuration Writes.</description>
25479                    <value>1</value>
25480                  </enumeratedValue>
25481                </enumeratedValues>
25482              </field>
25483            </fields>
25484          </register>
25485          <register>
25486            <name>ARB_EP6_INT_EN</name>
25487            <description>Endpoint Interrupt Enable Register  *1</description>
25488            <addressOffset>0x344</addressOffset>
25489            <size>32</size>
25490            <access>read-write</access>
25491            <resetValue>0x0</resetValue>
25492            <resetMask>0x3F</resetMask>
25493            <fields>
25494              <field>
25495                <name>IN_BUF_FULL_EN</name>
25496                <description>IN Endpoint Local Buffer Full Enable</description>
25497                <bitRange>[0:0]</bitRange>
25498                <access>read-write</access>
25499              </field>
25500              <field>
25501                <name>DMA_GNT_EN</name>
25502                <description>Endpoint DMA Grant Enable</description>
25503                <bitRange>[1:1]</bitRange>
25504                <access>read-write</access>
25505              </field>
25506              <field>
25507                <name>BUF_OVER_EN</name>
25508                <description>Endpoint Buffer Overflow Enable</description>
25509                <bitRange>[2:2]</bitRange>
25510                <access>read-write</access>
25511              </field>
25512              <field>
25513                <name>BUF_UNDER_EN</name>
25514                <description>Endpoint Buffer Underflow Enable</description>
25515                <bitRange>[3:3]</bitRange>
25516                <access>read-write</access>
25517              </field>
25518              <field>
25519                <name>ERR_INT_EN</name>
25520                <description>Endpoint Error in Transaction Interrupt Enable</description>
25521                <bitRange>[4:4]</bitRange>
25522                <access>read-write</access>
25523              </field>
25524              <field>
25525                <name>DMA_TERMIN_EN</name>
25526                <description>Endpoint DMA Terminated Enable</description>
25527                <bitRange>[5:5]</bitRange>
25528                <access>read-write</access>
25529              </field>
25530            </fields>
25531          </register>
25532          <register>
25533            <name>ARB_EP6_SR</name>
25534            <description>Endpoint Interrupt Enable Register  *1</description>
25535            <addressOffset>0x348</addressOffset>
25536            <size>32</size>
25537            <access>read-write</access>
25538            <resetValue>0x0</resetValue>
25539            <resetMask>0x2F</resetMask>
25540            <fields>
25541              <field>
25542                <name>IN_BUF_FULL</name>
25543                <description>IN Endpoint Local Buffer Full Interrupt</description>
25544                <bitRange>[0:0]</bitRange>
25545                <access>read-write</access>
25546              </field>
25547              <field>
25548                <name>DMA_GNT</name>
25549                <description>Endpoint DMA Grant Interrupt</description>
25550                <bitRange>[1:1]</bitRange>
25551                <access>read-write</access>
25552              </field>
25553              <field>
25554                <name>BUF_OVER</name>
25555                <description>Endpoint Buffer Overflow Interrupt</description>
25556                <bitRange>[2:2]</bitRange>
25557                <access>read-write</access>
25558              </field>
25559              <field>
25560                <name>BUF_UNDER</name>
25561                <description>Endpoint Buffer Underflow Interrupt</description>
25562                <bitRange>[3:3]</bitRange>
25563                <access>read-write</access>
25564              </field>
25565              <field>
25566                <name>DMA_TERMIN</name>
25567                <description>Endpoint DMA Terminated Interrupt</description>
25568                <bitRange>[5:5]</bitRange>
25569                <access>read-write</access>
25570              </field>
25571            </fields>
25572          </register>
25573          <register>
25574            <name>ARB_RW6_WA</name>
25575            <description>Endpoint Write Address value  *1, *2</description>
25576            <addressOffset>0x350</addressOffset>
25577            <size>32</size>
25578            <access>read-write</access>
25579            <resetValue>0x0</resetValue>
25580            <resetMask>0xFF</resetMask>
25581            <fields>
25582              <field>
25583                <name>WA</name>
25584                <description>Write Address for EP</description>
25585                <bitRange>[7:0]</bitRange>
25586                <access>read-write</access>
25587              </field>
25588            </fields>
25589          </register>
25590          <register>
25591            <name>ARB_RW6_WA_MSB</name>
25592            <description>Endpoint Write Address value  *1, *2</description>
25593            <addressOffset>0x354</addressOffset>
25594            <size>32</size>
25595            <access>read-write</access>
25596            <resetValue>0x0</resetValue>
25597            <resetMask>0x1</resetMask>
25598            <fields>
25599              <field>
25600                <name>WA_MSB</name>
25601                <description>Write Address for EP</description>
25602                <bitRange>[0:0]</bitRange>
25603                <access>read-write</access>
25604              </field>
25605            </fields>
25606          </register>
25607          <register>
25608            <name>ARB_RW6_RA</name>
25609            <description>Endpoint Read Address value  *1, *2</description>
25610            <addressOffset>0x358</addressOffset>
25611            <size>32</size>
25612            <access>read-write</access>
25613            <resetValue>0x0</resetValue>
25614            <resetMask>0xFF</resetMask>
25615            <fields>
25616              <field>
25617                <name>RA</name>
25618                <description>Read Address for EP</description>
25619                <bitRange>[7:0]</bitRange>
25620                <access>read-write</access>
25621              </field>
25622            </fields>
25623          </register>
25624          <register>
25625            <name>ARB_RW6_RA_MSB</name>
25626            <description>Endpoint Read Address value  *1, *2</description>
25627            <addressOffset>0x35C</addressOffset>
25628            <size>32</size>
25629            <access>read-write</access>
25630            <resetValue>0x0</resetValue>
25631            <resetMask>0x1</resetMask>
25632            <fields>
25633              <field>
25634                <name>RA_MSB</name>
25635                <description>Read Address for EP</description>
25636                <bitRange>[0:0]</bitRange>
25637                <access>read-write</access>
25638              </field>
25639            </fields>
25640          </register>
25641          <register>
25642            <name>ARB_RW6_DR</name>
25643            <description>Endpoint Data Register</description>
25644            <addressOffset>0x360</addressOffset>
25645            <size>32</size>
25646            <access>read-write</access>
25647            <resetValue>0x0</resetValue>
25648            <resetMask>0x0</resetMask>
25649            <fields>
25650              <field>
25651                <name>DR</name>
25652                <description>Data Register for EP ; This register is linked to the memory, hence reset value is undefined</description>
25653                <bitRange>[7:0]</bitRange>
25654                <access>read-write</access>
25655              </field>
25656            </fields>
25657          </register>
25658          <register>
25659            <name>ARB_EP7_CFG</name>
25660            <description>Endpoint Configuration Register  *1</description>
25661            <addressOffset>0x380</addressOffset>
25662            <size>32</size>
25663            <access>read-write</access>
25664            <resetValue>0x0</resetValue>
25665            <resetMask>0xF</resetMask>
25666            <fields>
25667              <field>
25668                <name>IN_DATA_RDY</name>
25669                <description>Indication that Endpoint Packet Data is Ready in Main memory</description>
25670                <bitRange>[0:0]</bitRange>
25671                <access>read-write</access>
25672              </field>
25673              <field>
25674                <name>DMA_REQ</name>
25675                <description>Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated.</description>
25676                <bitRange>[1:1]</bitRange>
25677                <access>read-write</access>
25678              </field>
25679              <field>
25680                <name>CRC_BYPASS</name>
25681                <description>Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware</description>
25682                <bitRange>[2:2]</bitRange>
25683                <access>read-write</access>
25684                <enumeratedValues>
25685                  <enumeratedValue>
25686                    <name>CRC_NORMAL</name>
25687                    <description>No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s</description>
25688                    <value>0</value>
25689                  </enumeratedValue>
25690                  <enumeratedValue>
25691                    <name>CRC_BYPASS</name>
25692                    <description>CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s</description>
25693                    <value>1</value>
25694                  </enumeratedValue>
25695                </enumeratedValues>
25696              </field>
25697              <field>
25698                <name>RESET_PTR</name>
25699                <description>Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction.</description>
25700                <bitRange>[3:3]</bitRange>
25701                <access>read-write</access>
25702                <enumeratedValues>
25703                  <enumeratedValue>
25704                    <name>RESET_KRYPTON</name>
25705                    <description>Do not Reset Pointer; Krypton Backward compatibility mode</description>
25706                    <value>0</value>
25707                  </enumeratedValue>
25708                  <enumeratedValue>
25709                    <name>RESET_NORMAL</name>
25710                    <description>Reset Pointer; recommended value for reduction of CPU Configuration Writes.</description>
25711                    <value>1</value>
25712                  </enumeratedValue>
25713                </enumeratedValues>
25714              </field>
25715            </fields>
25716          </register>
25717          <register>
25718            <name>ARB_EP7_INT_EN</name>
25719            <description>Endpoint Interrupt Enable Register  *1</description>
25720            <addressOffset>0x384</addressOffset>
25721            <size>32</size>
25722            <access>read-write</access>
25723            <resetValue>0x0</resetValue>
25724            <resetMask>0x3F</resetMask>
25725            <fields>
25726              <field>
25727                <name>IN_BUF_FULL_EN</name>
25728                <description>IN Endpoint Local Buffer Full Enable</description>
25729                <bitRange>[0:0]</bitRange>
25730                <access>read-write</access>
25731              </field>
25732              <field>
25733                <name>DMA_GNT_EN</name>
25734                <description>Endpoint DMA Grant Enable</description>
25735                <bitRange>[1:1]</bitRange>
25736                <access>read-write</access>
25737              </field>
25738              <field>
25739                <name>BUF_OVER_EN</name>
25740                <description>Endpoint Buffer Overflow Enable</description>
25741                <bitRange>[2:2]</bitRange>
25742                <access>read-write</access>
25743              </field>
25744              <field>
25745                <name>BUF_UNDER_EN</name>
25746                <description>Endpoint Buffer Underflow Enable</description>
25747                <bitRange>[3:3]</bitRange>
25748                <access>read-write</access>
25749              </field>
25750              <field>
25751                <name>ERR_INT_EN</name>
25752                <description>Endpoint Error in Transaction Interrupt Enable</description>
25753                <bitRange>[4:4]</bitRange>
25754                <access>read-write</access>
25755              </field>
25756              <field>
25757                <name>DMA_TERMIN_EN</name>
25758                <description>Endpoint DMA Terminated Enable</description>
25759                <bitRange>[5:5]</bitRange>
25760                <access>read-write</access>
25761              </field>
25762            </fields>
25763          </register>
25764          <register>
25765            <name>ARB_EP7_SR</name>
25766            <description>Endpoint Interrupt Enable Register  *1</description>
25767            <addressOffset>0x388</addressOffset>
25768            <size>32</size>
25769            <access>read-write</access>
25770            <resetValue>0x0</resetValue>
25771            <resetMask>0x2F</resetMask>
25772            <fields>
25773              <field>
25774                <name>IN_BUF_FULL</name>
25775                <description>IN Endpoint Local Buffer Full Interrupt</description>
25776                <bitRange>[0:0]</bitRange>
25777                <access>read-write</access>
25778              </field>
25779              <field>
25780                <name>DMA_GNT</name>
25781                <description>Endpoint DMA Grant Interrupt</description>
25782                <bitRange>[1:1]</bitRange>
25783                <access>read-write</access>
25784              </field>
25785              <field>
25786                <name>BUF_OVER</name>
25787                <description>Endpoint Buffer Overflow Interrupt</description>
25788                <bitRange>[2:2]</bitRange>
25789                <access>read-write</access>
25790              </field>
25791              <field>
25792                <name>BUF_UNDER</name>
25793                <description>Endpoint Buffer Underflow Interrupt</description>
25794                <bitRange>[3:3]</bitRange>
25795                <access>read-write</access>
25796              </field>
25797              <field>
25798                <name>DMA_TERMIN</name>
25799                <description>Endpoint DMA Terminated Interrupt</description>
25800                <bitRange>[5:5]</bitRange>
25801                <access>read-write</access>
25802              </field>
25803            </fields>
25804          </register>
25805          <register>
25806            <name>ARB_RW7_WA</name>
25807            <description>Endpoint Write Address value  *1, *2</description>
25808            <addressOffset>0x390</addressOffset>
25809            <size>32</size>
25810            <access>read-write</access>
25811            <resetValue>0x0</resetValue>
25812            <resetMask>0xFF</resetMask>
25813            <fields>
25814              <field>
25815                <name>WA</name>
25816                <description>Write Address for EP</description>
25817                <bitRange>[7:0]</bitRange>
25818                <access>read-write</access>
25819              </field>
25820            </fields>
25821          </register>
25822          <register>
25823            <name>ARB_RW7_WA_MSB</name>
25824            <description>Endpoint Write Address value  *1, *2</description>
25825            <addressOffset>0x394</addressOffset>
25826            <size>32</size>
25827            <access>read-write</access>
25828            <resetValue>0x0</resetValue>
25829            <resetMask>0x1</resetMask>
25830            <fields>
25831              <field>
25832                <name>WA_MSB</name>
25833                <description>Write Address for EP</description>
25834                <bitRange>[0:0]</bitRange>
25835                <access>read-write</access>
25836              </field>
25837            </fields>
25838          </register>
25839          <register>
25840            <name>ARB_RW7_RA</name>
25841            <description>Endpoint Read Address value  *1, *2</description>
25842            <addressOffset>0x398</addressOffset>
25843            <size>32</size>
25844            <access>read-write</access>
25845            <resetValue>0x0</resetValue>
25846            <resetMask>0xFF</resetMask>
25847            <fields>
25848              <field>
25849                <name>RA</name>
25850                <description>Read Address for EP</description>
25851                <bitRange>[7:0]</bitRange>
25852                <access>read-write</access>
25853              </field>
25854            </fields>
25855          </register>
25856          <register>
25857            <name>ARB_RW7_RA_MSB</name>
25858            <description>Endpoint Read Address value  *1, *2</description>
25859            <addressOffset>0x39C</addressOffset>
25860            <size>32</size>
25861            <access>read-write</access>
25862            <resetValue>0x0</resetValue>
25863            <resetMask>0x1</resetMask>
25864            <fields>
25865              <field>
25866                <name>RA_MSB</name>
25867                <description>Read Address for EP</description>
25868                <bitRange>[0:0]</bitRange>
25869                <access>read-write</access>
25870              </field>
25871            </fields>
25872          </register>
25873          <register>
25874            <name>ARB_RW7_DR</name>
25875            <description>Endpoint Data Register</description>
25876            <addressOffset>0x3A0</addressOffset>
25877            <size>32</size>
25878            <access>read-write</access>
25879            <resetValue>0x0</resetValue>
25880            <resetMask>0x0</resetMask>
25881            <fields>
25882              <field>
25883                <name>DR</name>
25884                <description>Data Register for EP ; This register is linked to the memory, hence reset value is undefined</description>
25885                <bitRange>[7:0]</bitRange>
25886                <access>read-write</access>
25887              </field>
25888            </fields>
25889          </register>
25890          <register>
25891            <name>ARB_EP8_CFG</name>
25892            <description>Endpoint Configuration Register  *1</description>
25893            <addressOffset>0x3C0</addressOffset>
25894            <size>32</size>
25895            <access>read-write</access>
25896            <resetValue>0x0</resetValue>
25897            <resetMask>0xF</resetMask>
25898            <fields>
25899              <field>
25900                <name>IN_DATA_RDY</name>
25901                <description>Indication that Endpoint Packet Data is Ready in Main memory</description>
25902                <bitRange>[0:0]</bitRange>
25903                <access>read-write</access>
25904              </field>
25905              <field>
25906                <name>DMA_REQ</name>
25907                <description>Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated.</description>
25908                <bitRange>[1:1]</bitRange>
25909                <access>read-write</access>
25910              </field>
25911              <field>
25912                <name>CRC_BYPASS</name>
25913                <description>Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware</description>
25914                <bitRange>[2:2]</bitRange>
25915                <access>read-write</access>
25916                <enumeratedValues>
25917                  <enumeratedValue>
25918                    <name>CRC_NORMAL</name>
25919                    <description>No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s</description>
25920                    <value>0</value>
25921                  </enumeratedValue>
25922                  <enumeratedValue>
25923                    <name>CRC_BYPASS</name>
25924                    <description>CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s</description>
25925                    <value>1</value>
25926                  </enumeratedValue>
25927                </enumeratedValues>
25928              </field>
25929              <field>
25930                <name>RESET_PTR</name>
25931                <description>Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction.</description>
25932                <bitRange>[3:3]</bitRange>
25933                <access>read-write</access>
25934                <enumeratedValues>
25935                  <enumeratedValue>
25936                    <name>RESET_KRYPTON</name>
25937                    <description>Do not Reset Pointer; Krypton Backward compatibility mode</description>
25938                    <value>0</value>
25939                  </enumeratedValue>
25940                  <enumeratedValue>
25941                    <name>RESET_NORMAL</name>
25942                    <description>Reset Pointer; recommended value for reduction of CPU Configuration Writes.</description>
25943                    <value>1</value>
25944                  </enumeratedValue>
25945                </enumeratedValues>
25946              </field>
25947            </fields>
25948          </register>
25949          <register>
25950            <name>ARB_EP8_INT_EN</name>
25951            <description>Endpoint Interrupt Enable Register  *1</description>
25952            <addressOffset>0x3C4</addressOffset>
25953            <size>32</size>
25954            <access>read-write</access>
25955            <resetValue>0x0</resetValue>
25956            <resetMask>0x3F</resetMask>
25957            <fields>
25958              <field>
25959                <name>IN_BUF_FULL_EN</name>
25960                <description>IN Endpoint Local Buffer Full Enable</description>
25961                <bitRange>[0:0]</bitRange>
25962                <access>read-write</access>
25963              </field>
25964              <field>
25965                <name>DMA_GNT_EN</name>
25966                <description>Endpoint DMA Grant Enable</description>
25967                <bitRange>[1:1]</bitRange>
25968                <access>read-write</access>
25969              </field>
25970              <field>
25971                <name>BUF_OVER_EN</name>
25972                <description>Endpoint Buffer Overflow Enable</description>
25973                <bitRange>[2:2]</bitRange>
25974                <access>read-write</access>
25975              </field>
25976              <field>
25977                <name>BUF_UNDER_EN</name>
25978                <description>Endpoint Buffer Underflow Enable</description>
25979                <bitRange>[3:3]</bitRange>
25980                <access>read-write</access>
25981              </field>
25982              <field>
25983                <name>ERR_INT_EN</name>
25984                <description>Endpoint Error in Transaction Interrupt Enable</description>
25985                <bitRange>[4:4]</bitRange>
25986                <access>read-write</access>
25987              </field>
25988              <field>
25989                <name>DMA_TERMIN_EN</name>
25990                <description>Endpoint DMA Terminated Enable</description>
25991                <bitRange>[5:5]</bitRange>
25992                <access>read-write</access>
25993              </field>
25994            </fields>
25995          </register>
25996          <register>
25997            <name>ARB_EP8_SR</name>
25998            <description>Endpoint Interrupt Enable Register  *1</description>
25999            <addressOffset>0x3C8</addressOffset>
26000            <size>32</size>
26001            <access>read-write</access>
26002            <resetValue>0x0</resetValue>
26003            <resetMask>0x2F</resetMask>
26004            <fields>
26005              <field>
26006                <name>IN_BUF_FULL</name>
26007                <description>IN Endpoint Local Buffer Full Interrupt</description>
26008                <bitRange>[0:0]</bitRange>
26009                <access>read-write</access>
26010              </field>
26011              <field>
26012                <name>DMA_GNT</name>
26013                <description>Endpoint DMA Grant Interrupt</description>
26014                <bitRange>[1:1]</bitRange>
26015                <access>read-write</access>
26016              </field>
26017              <field>
26018                <name>BUF_OVER</name>
26019                <description>Endpoint Buffer Overflow Interrupt</description>
26020                <bitRange>[2:2]</bitRange>
26021                <access>read-write</access>
26022              </field>
26023              <field>
26024                <name>BUF_UNDER</name>
26025                <description>Endpoint Buffer Underflow Interrupt</description>
26026                <bitRange>[3:3]</bitRange>
26027                <access>read-write</access>
26028              </field>
26029              <field>
26030                <name>DMA_TERMIN</name>
26031                <description>Endpoint DMA Terminated Interrupt</description>
26032                <bitRange>[5:5]</bitRange>
26033                <access>read-write</access>
26034              </field>
26035            </fields>
26036          </register>
26037          <register>
26038            <name>ARB_RW8_WA</name>
26039            <description>Endpoint Write Address value  *1, *2</description>
26040            <addressOffset>0x3D0</addressOffset>
26041            <size>32</size>
26042            <access>read-write</access>
26043            <resetValue>0x0</resetValue>
26044            <resetMask>0xFF</resetMask>
26045            <fields>
26046              <field>
26047                <name>WA</name>
26048                <description>Write Address for EP</description>
26049                <bitRange>[7:0]</bitRange>
26050                <access>read-write</access>
26051              </field>
26052            </fields>
26053          </register>
26054          <register>
26055            <name>ARB_RW8_WA_MSB</name>
26056            <description>Endpoint Write Address value  *1, *2</description>
26057            <addressOffset>0x3D4</addressOffset>
26058            <size>32</size>
26059            <access>read-write</access>
26060            <resetValue>0x0</resetValue>
26061            <resetMask>0x1</resetMask>
26062            <fields>
26063              <field>
26064                <name>WA_MSB</name>
26065                <description>Write Address for EP</description>
26066                <bitRange>[0:0]</bitRange>
26067                <access>read-write</access>
26068              </field>
26069            </fields>
26070          </register>
26071          <register>
26072            <name>ARB_RW8_RA</name>
26073            <description>Endpoint Read Address value  *1, *2</description>
26074            <addressOffset>0x3D8</addressOffset>
26075            <size>32</size>
26076            <access>read-write</access>
26077            <resetValue>0x0</resetValue>
26078            <resetMask>0xFF</resetMask>
26079            <fields>
26080              <field>
26081                <name>RA</name>
26082                <description>Read Address for EP</description>
26083                <bitRange>[7:0]</bitRange>
26084                <access>read-write</access>
26085              </field>
26086            </fields>
26087          </register>
26088          <register>
26089            <name>ARB_RW8_RA_MSB</name>
26090            <description>Endpoint Read Address value  *1, *2</description>
26091            <addressOffset>0x3DC</addressOffset>
26092            <size>32</size>
26093            <access>read-write</access>
26094            <resetValue>0x0</resetValue>
26095            <resetMask>0x1</resetMask>
26096            <fields>
26097              <field>
26098                <name>RA_MSB</name>
26099                <description>Read Address for EP</description>
26100                <bitRange>[0:0]</bitRange>
26101                <access>read-write</access>
26102              </field>
26103            </fields>
26104          </register>
26105          <register>
26106            <name>ARB_RW8_DR</name>
26107            <description>Endpoint Data Register</description>
26108            <addressOffset>0x3E0</addressOffset>
26109            <size>32</size>
26110            <access>read-write</access>
26111            <resetValue>0x0</resetValue>
26112            <resetMask>0x0</resetMask>
26113            <fields>
26114              <field>
26115                <name>DR</name>
26116                <description>Data Register for EP ; This register is linked to the memory, hence reset value is undefined</description>
26117                <bitRange>[7:0]</bitRange>
26118                <access>read-write</access>
26119              </field>
26120            </fields>
26121          </register>
26122          <register>
26123            <dim>512</dim>
26124            <dimIncrement>4</dimIncrement>
26125            <name>MEM_DATA[%s]</name>
26126            <description>DATA</description>
26127            <addressOffset>0x400</addressOffset>
26128            <size>32</size>
26129            <access>read-write</access>
26130            <resetValue>0x0</resetValue>
26131            <resetMask>0x0</resetMask>
26132            <fields>
26133              <field>
26134                <name>DR</name>
26135                <description>Data Register for EP ; This register is linked to the memory, hence reset value is undefined</description>
26136                <bitRange>[7:0]</bitRange>
26137                <access>read-write</access>
26138              </field>
26139            </fields>
26140          </register>
26141          <register>
26142            <name>SOF16</name>
26143            <description>Start Of Frame Register</description>
26144            <addressOffset>0x1060</addressOffset>
26145            <size>32</size>
26146            <access>read-only</access>
26147            <resetValue>0x0</resetValue>
26148            <resetMask>0x7FF</resetMask>
26149            <fields>
26150              <field>
26151                <name>FRAME_NUMBER16</name>
26152                <description>The frame number (11b)</description>
26153                <bitRange>[10:0]</bitRange>
26154                <access>read-only</access>
26155              </field>
26156            </fields>
26157          </register>
26158          <register>
26159            <name>OSCLK_DR16</name>
26160            <description>Oscillator lock data register</description>
26161            <addressOffset>0x1080</addressOffset>
26162            <size>32</size>
26163            <access>read-only</access>
26164            <resetValue>0x0</resetValue>
26165            <resetMask>0x0</resetMask>
26166            <fields>
26167              <field>
26168                <name>ADDER16</name>
26169                <description>These bits return the oscillator locking circuits adder output.</description>
26170                <bitRange>[14:0]</bitRange>
26171                <access>read-only</access>
26172              </field>
26173            </fields>
26174          </register>
26175          <register>
26176            <name>ARB_RW1_WA16</name>
26177            <description>Endpoint Write Address value  *3</description>
26178            <addressOffset>0x1210</addressOffset>
26179            <size>32</size>
26180            <access>read-write</access>
26181            <resetValue>0x0</resetValue>
26182            <resetMask>0x1FF</resetMask>
26183            <fields>
26184              <field>
26185                <name>WA16</name>
26186                <description>Write Address for EP</description>
26187                <bitRange>[8:0]</bitRange>
26188                <access>read-write</access>
26189              </field>
26190            </fields>
26191          </register>
26192          <register>
26193            <name>ARB_RW1_RA16</name>
26194            <description>Endpoint Read Address value  *3</description>
26195            <addressOffset>0x1218</addressOffset>
26196            <size>32</size>
26197            <access>read-write</access>
26198            <resetValue>0x0</resetValue>
26199            <resetMask>0x1FF</resetMask>
26200            <fields>
26201              <field>
26202                <name>RA16</name>
26203                <description>Read Address for EP</description>
26204                <bitRange>[8:0]</bitRange>
26205                <access>read-write</access>
26206              </field>
26207            </fields>
26208          </register>
26209          <register>
26210            <name>ARB_RW1_DR16</name>
26211            <description>Endpoint Data Register</description>
26212            <addressOffset>0x1220</addressOffset>
26213            <size>32</size>
26214            <access>read-write</access>
26215            <resetValue>0x0</resetValue>
26216            <resetMask>0x0</resetMask>
26217            <fields>
26218              <field>
26219                <name>DR16</name>
26220                <description>Data Register for EP ; This register is linked to the memory, hence reset value is undefined</description>
26221                <bitRange>[15:0]</bitRange>
26222                <access>read-write</access>
26223              </field>
26224            </fields>
26225          </register>
26226          <register>
26227            <name>ARB_RW2_WA16</name>
26228            <description>Endpoint Write Address value  *3</description>
26229            <addressOffset>0x1250</addressOffset>
26230            <size>32</size>
26231            <access>read-write</access>
26232            <resetValue>0x0</resetValue>
26233            <resetMask>0x1FF</resetMask>
26234            <fields>
26235              <field>
26236                <name>WA16</name>
26237                <description>Write Address for EP</description>
26238                <bitRange>[8:0]</bitRange>
26239                <access>read-write</access>
26240              </field>
26241            </fields>
26242          </register>
26243          <register>
26244            <name>ARB_RW2_RA16</name>
26245            <description>Endpoint Read Address value  *3</description>
26246            <addressOffset>0x1258</addressOffset>
26247            <size>32</size>
26248            <access>read-write</access>
26249            <resetValue>0x0</resetValue>
26250            <resetMask>0x1FF</resetMask>
26251            <fields>
26252              <field>
26253                <name>RA16</name>
26254                <description>Read Address for EP</description>
26255                <bitRange>[8:0]</bitRange>
26256                <access>read-write</access>
26257              </field>
26258            </fields>
26259          </register>
26260          <register>
26261            <name>ARB_RW2_DR16</name>
26262            <description>Endpoint Data Register</description>
26263            <addressOffset>0x1260</addressOffset>
26264            <size>32</size>
26265            <access>read-write</access>
26266            <resetValue>0x0</resetValue>
26267            <resetMask>0x0</resetMask>
26268            <fields>
26269              <field>
26270                <name>DR16</name>
26271                <description>Data Register for EP ; This register is linked to the memory, hence reset value is undefined</description>
26272                <bitRange>[15:0]</bitRange>
26273                <access>read-write</access>
26274              </field>
26275            </fields>
26276          </register>
26277          <register>
26278            <name>ARB_RW3_WA16</name>
26279            <description>Endpoint Write Address value  *3</description>
26280            <addressOffset>0x1290</addressOffset>
26281            <size>32</size>
26282            <access>read-write</access>
26283            <resetValue>0x0</resetValue>
26284            <resetMask>0x1FF</resetMask>
26285            <fields>
26286              <field>
26287                <name>WA16</name>
26288                <description>Write Address for EP</description>
26289                <bitRange>[8:0]</bitRange>
26290                <access>read-write</access>
26291              </field>
26292            </fields>
26293          </register>
26294          <register>
26295            <name>ARB_RW3_RA16</name>
26296            <description>Endpoint Read Address value  *3</description>
26297            <addressOffset>0x1298</addressOffset>
26298            <size>32</size>
26299            <access>read-write</access>
26300            <resetValue>0x0</resetValue>
26301            <resetMask>0x1FF</resetMask>
26302            <fields>
26303              <field>
26304                <name>RA16</name>
26305                <description>Read Address for EP</description>
26306                <bitRange>[8:0]</bitRange>
26307                <access>read-write</access>
26308              </field>
26309            </fields>
26310          </register>
26311          <register>
26312            <name>ARB_RW3_DR16</name>
26313            <description>Endpoint Data Register</description>
26314            <addressOffset>0x12A0</addressOffset>
26315            <size>32</size>
26316            <access>read-write</access>
26317            <resetValue>0x0</resetValue>
26318            <resetMask>0x0</resetMask>
26319            <fields>
26320              <field>
26321                <name>DR16</name>
26322                <description>Data Register for EP ; This register is linked to the memory, hence reset value is undefined</description>
26323                <bitRange>[15:0]</bitRange>
26324                <access>read-write</access>
26325              </field>
26326            </fields>
26327          </register>
26328          <register>
26329            <name>CWA16</name>
26330            <description>Common Area Write Address</description>
26331            <addressOffset>0x12B0</addressOffset>
26332            <size>32</size>
26333            <access>read-write</access>
26334            <resetValue>0x0</resetValue>
26335            <resetMask>0x1FF</resetMask>
26336            <fields>
26337              <field>
26338                <name>CWA16</name>
26339                <description>Write Address for Common Area</description>
26340                <bitRange>[8:0]</bitRange>
26341                <access>read-write</access>
26342              </field>
26343            </fields>
26344          </register>
26345          <register>
26346            <name>ARB_RW4_WA16</name>
26347            <description>Endpoint Write Address value  *3</description>
26348            <addressOffset>0x12D0</addressOffset>
26349            <size>32</size>
26350            <access>read-write</access>
26351            <resetValue>0x0</resetValue>
26352            <resetMask>0x1FF</resetMask>
26353            <fields>
26354              <field>
26355                <name>WA16</name>
26356                <description>Write Address for EP</description>
26357                <bitRange>[8:0]</bitRange>
26358                <access>read-write</access>
26359              </field>
26360            </fields>
26361          </register>
26362          <register>
26363            <name>ARB_RW4_RA16</name>
26364            <description>Endpoint Read Address value  *3</description>
26365            <addressOffset>0x12D8</addressOffset>
26366            <size>32</size>
26367            <access>read-write</access>
26368            <resetValue>0x0</resetValue>
26369            <resetMask>0x1FF</resetMask>
26370            <fields>
26371              <field>
26372                <name>RA16</name>
26373                <description>Read Address for EP</description>
26374                <bitRange>[8:0]</bitRange>
26375                <access>read-write</access>
26376              </field>
26377            </fields>
26378          </register>
26379          <register>
26380            <name>ARB_RW4_DR16</name>
26381            <description>Endpoint Data Register</description>
26382            <addressOffset>0x12E0</addressOffset>
26383            <size>32</size>
26384            <access>read-write</access>
26385            <resetValue>0x0</resetValue>
26386            <resetMask>0x0</resetMask>
26387            <fields>
26388              <field>
26389                <name>DR16</name>
26390                <description>Data Register for EP ; This register is linked to the memory, hence reset value is undefined</description>
26391                <bitRange>[15:0]</bitRange>
26392                <access>read-write</access>
26393              </field>
26394            </fields>
26395          </register>
26396          <register>
26397            <name>DMA_THRES16</name>
26398            <description>DMA Burst / Threshold Configuration</description>
26399            <addressOffset>0x12F0</addressOffset>
26400            <size>32</size>
26401            <access>read-write</access>
26402            <resetValue>0x0</resetValue>
26403            <resetMask>0x1FF</resetMask>
26404            <fields>
26405              <field>
26406                <name>DMA_THS16</name>
26407                <description>DMA Threshold count</description>
26408                <bitRange>[8:0]</bitRange>
26409                <access>read-write</access>
26410              </field>
26411            </fields>
26412          </register>
26413          <register>
26414            <name>ARB_RW5_WA16</name>
26415            <description>Endpoint Write Address value  *3</description>
26416            <addressOffset>0x1310</addressOffset>
26417            <size>32</size>
26418            <access>read-write</access>
26419            <resetValue>0x0</resetValue>
26420            <resetMask>0x1FF</resetMask>
26421            <fields>
26422              <field>
26423                <name>WA16</name>
26424                <description>Write Address for EP</description>
26425                <bitRange>[8:0]</bitRange>
26426                <access>read-write</access>
26427              </field>
26428            </fields>
26429          </register>
26430          <register>
26431            <name>ARB_RW5_RA16</name>
26432            <description>Endpoint Read Address value  *3</description>
26433            <addressOffset>0x1318</addressOffset>
26434            <size>32</size>
26435            <access>read-write</access>
26436            <resetValue>0x0</resetValue>
26437            <resetMask>0x1FF</resetMask>
26438            <fields>
26439              <field>
26440                <name>RA16</name>
26441                <description>Read Address for EP</description>
26442                <bitRange>[8:0]</bitRange>
26443                <access>read-write</access>
26444              </field>
26445            </fields>
26446          </register>
26447          <register>
26448            <name>ARB_RW5_DR16</name>
26449            <description>Endpoint Data Register</description>
26450            <addressOffset>0x1320</addressOffset>
26451            <size>32</size>
26452            <access>read-write</access>
26453            <resetValue>0x0</resetValue>
26454            <resetMask>0x0</resetMask>
26455            <fields>
26456              <field>
26457                <name>DR16</name>
26458                <description>Data Register for EP ; This register is linked to the memory, hence reset value is undefined</description>
26459                <bitRange>[15:0]</bitRange>
26460                <access>read-write</access>
26461              </field>
26462            </fields>
26463          </register>
26464          <register>
26465            <name>ARB_RW6_WA16</name>
26466            <description>Endpoint Write Address value  *3</description>
26467            <addressOffset>0x1350</addressOffset>
26468            <size>32</size>
26469            <access>read-write</access>
26470            <resetValue>0x0</resetValue>
26471            <resetMask>0x1FF</resetMask>
26472            <fields>
26473              <field>
26474                <name>WA16</name>
26475                <description>Write Address for EP</description>
26476                <bitRange>[8:0]</bitRange>
26477                <access>read-write</access>
26478              </field>
26479            </fields>
26480          </register>
26481          <register>
26482            <name>ARB_RW6_RA16</name>
26483            <description>Endpoint Read Address value  *3</description>
26484            <addressOffset>0x1358</addressOffset>
26485            <size>32</size>
26486            <access>read-write</access>
26487            <resetValue>0x0</resetValue>
26488            <resetMask>0x1FF</resetMask>
26489            <fields>
26490              <field>
26491                <name>RA16</name>
26492                <description>Read Address for EP</description>
26493                <bitRange>[8:0]</bitRange>
26494                <access>read-write</access>
26495              </field>
26496            </fields>
26497          </register>
26498          <register>
26499            <name>ARB_RW6_DR16</name>
26500            <description>Endpoint Data Register</description>
26501            <addressOffset>0x1360</addressOffset>
26502            <size>32</size>
26503            <access>read-write</access>
26504            <resetValue>0x0</resetValue>
26505            <resetMask>0x0</resetMask>
26506            <fields>
26507              <field>
26508                <name>DR16</name>
26509                <description>Data Register for EP ; This register is linked to the memory, hence reset value is undefined</description>
26510                <bitRange>[15:0]</bitRange>
26511                <access>read-write</access>
26512              </field>
26513            </fields>
26514          </register>
26515          <register>
26516            <name>ARB_RW7_WA16</name>
26517            <description>Endpoint Write Address value  *3</description>
26518            <addressOffset>0x1390</addressOffset>
26519            <size>32</size>
26520            <access>read-write</access>
26521            <resetValue>0x0</resetValue>
26522            <resetMask>0x1FF</resetMask>
26523            <fields>
26524              <field>
26525                <name>WA16</name>
26526                <description>Write Address for EP</description>
26527                <bitRange>[8:0]</bitRange>
26528                <access>read-write</access>
26529              </field>
26530            </fields>
26531          </register>
26532          <register>
26533            <name>ARB_RW7_RA16</name>
26534            <description>Endpoint Read Address value  *3</description>
26535            <addressOffset>0x1398</addressOffset>
26536            <size>32</size>
26537            <access>read-write</access>
26538            <resetValue>0x0</resetValue>
26539            <resetMask>0x1FF</resetMask>
26540            <fields>
26541              <field>
26542                <name>RA16</name>
26543                <description>Read Address for EP</description>
26544                <bitRange>[8:0]</bitRange>
26545                <access>read-write</access>
26546              </field>
26547            </fields>
26548          </register>
26549          <register>
26550            <name>ARB_RW7_DR16</name>
26551            <description>Endpoint Data Register</description>
26552            <addressOffset>0x13A0</addressOffset>
26553            <size>32</size>
26554            <access>read-write</access>
26555            <resetValue>0x0</resetValue>
26556            <resetMask>0x0</resetMask>
26557            <fields>
26558              <field>
26559                <name>DR16</name>
26560                <description>Data Register for EP ; This register is linked to the memory, hence reset value is undefined</description>
26561                <bitRange>[15:0]</bitRange>
26562                <access>read-write</access>
26563              </field>
26564            </fields>
26565          </register>
26566          <register>
26567            <name>ARB_RW8_WA16</name>
26568            <description>Endpoint Write Address value  *3</description>
26569            <addressOffset>0x13D0</addressOffset>
26570            <size>32</size>
26571            <access>read-write</access>
26572            <resetValue>0x0</resetValue>
26573            <resetMask>0x1FF</resetMask>
26574            <fields>
26575              <field>
26576                <name>WA16</name>
26577                <description>Write Address for EP</description>
26578                <bitRange>[8:0]</bitRange>
26579                <access>read-write</access>
26580              </field>
26581            </fields>
26582          </register>
26583          <register>
26584            <name>ARB_RW8_RA16</name>
26585            <description>Endpoint Read Address value  *3</description>
26586            <addressOffset>0x13D8</addressOffset>
26587            <size>32</size>
26588            <access>read-write</access>
26589            <resetValue>0x0</resetValue>
26590            <resetMask>0x1FF</resetMask>
26591            <fields>
26592              <field>
26593                <name>RA16</name>
26594                <description>Read Address for EP</description>
26595                <bitRange>[8:0]</bitRange>
26596                <access>read-write</access>
26597              </field>
26598            </fields>
26599          </register>
26600          <register>
26601            <name>ARB_RW8_DR16</name>
26602            <description>Endpoint Data Register</description>
26603            <addressOffset>0x13E0</addressOffset>
26604            <size>32</size>
26605            <access>read-write</access>
26606            <resetValue>0x0</resetValue>
26607            <resetMask>0x0</resetMask>
26608            <fields>
26609              <field>
26610                <name>DR16</name>
26611                <description>Data Register for EP ; This register is linked to the memory, hence reset value is undefined</description>
26612                <bitRange>[15:0]</bitRange>
26613                <access>read-write</access>
26614              </field>
26615            </fields>
26616          </register>
26617        </cluster>
26618        <cluster>
26619          <name>USBLPM</name>
26620          <description>USB Device LPM and PHY Test</description>
26621          <addressOffset>0x00002000</addressOffset>
26622          <register>
26623            <name>POWER_CTL</name>
26624            <description>Power Control Register</description>
26625            <addressOffset>0x0</addressOffset>
26626            <size>32</size>
26627            <access>read-write</access>
26628            <resetValue>0x0</resetValue>
26629            <resetMask>0x303F0004</resetMask>
26630            <fields>
26631              <field>
26632                <name>SUSPEND</name>
26633                <description>Put PHY into Suspend mode.  If the PHY is enabled, this bit MUST be set before entering a low power mode (DeepSleep).
26634Note:
26635- This bit is invalid if the HOST bit of the Host Control 0 Register (HOST_CTL0) is '1'.</description>
26636                <bitRange>[2:2]</bitRange>
26637                <access>read-write</access>
26638              </field>
26639              <field>
26640                <name>DP_UP_EN</name>
26641                <description>Enables the pull up on the DP.
26642'0' : Disable.
26643'1' : Enable.</description>
26644                <bitRange>[16:16]</bitRange>
26645                <access>read-write</access>
26646              </field>
26647              <field>
26648                <name>DP_BIG</name>
26649                <description>Select the resister value if POWER_CTL.DP_EN='1'. This bit is valid in GPIO.
26650'0' : The resister value is from 900 to1575Ohmpull up on the DP.
26651'1' : The resister value is from 1425 to 3090Ohmpull up on the DP</description>
26652                <bitRange>[17:17]</bitRange>
26653                <access>read-write</access>
26654              </field>
26655              <field>
26656                <name>DP_DOWN_EN</name>
26657                <description>Enables the ~15k pull down on the DP.</description>
26658                <bitRange>[18:18]</bitRange>
26659                <access>read-write</access>
26660              </field>
26661              <field>
26662                <name>DM_UP_EN</name>
26663                <description>Enables the pull up on the DM. The bit is valid in GPIO. The pull up resistor is disabled in not GPIO.
26664'0' : Disable.
26665'1' : Enable.</description>
26666                <bitRange>[19:19]</bitRange>
26667                <access>read-write</access>
26668              </field>
26669              <field>
26670                <name>DM_BIG</name>
26671                <description>Select the resister value if POWER_CTL.DM_EN='1'. This bit is valid in GPIO.
26672'0' : The resister value is from 900 to1575Ohmpull up on the DM.
26673'1' : The resister value is from 1425 to 3090Ohmpull up on the DM</description>
26674                <bitRange>[20:20]</bitRange>
26675                <access>read-write</access>
26676              </field>
26677              <field>
26678                <name>DM_DOWN_EN</name>
26679                <description>Enables the ~15k pull down on the DP.</description>
26680                <bitRange>[21:21]</bitRange>
26681                <access>read-write</access>
26682              </field>
26683              <field>
26684                <name>ENABLE_DPO</name>
26685                <description>Enables the single ended receiver on D+.</description>
26686                <bitRange>[28:28]</bitRange>
26687                <access>read-write</access>
26688              </field>
26689              <field>
26690                <name>ENABLE_DMO</name>
26691                <description>Enables the signle ended receiver on D-.</description>
26692                <bitRange>[29:29]</bitRange>
26693                <access>read-write</access>
26694              </field>
26695            </fields>
26696          </register>
26697          <register>
26698            <name>USBIO_CTL</name>
26699            <description>USB IO Control Register</description>
26700            <addressOffset>0x8</addressOffset>
26701            <size>32</size>
26702            <access>read-write</access>
26703            <resetValue>0x0</resetValue>
26704            <resetMask>0x3F</resetMask>
26705            <fields>
26706              <field>
26707                <name>DM_P</name>
26708                <description>The GPIO Drive Mode for DP IO pad. This field only applies if USBIO_CR1.IOMODE =1. Data comes from the corresponding GPIO.DR register.</description>
26709                <bitRange>[2:0]</bitRange>
26710                <access>read-write</access>
26711                <enumeratedValues>
26712                  <enumeratedValue>
26713                    <name>OFF</name>
26714                    <description>Mode 0: Output buffer off (high Z). Input buffer off.</description>
26715                    <value>0</value>
26716                  </enumeratedValue>
26717                  <enumeratedValue>
26718                    <name>INPUT</name>
26719                    <description>Mode 1: Output buffer off (high Z). Input buffer on.
26720
26721Other values, not supported.</description>
26722                    <value>1</value>
26723                  </enumeratedValue>
26724                </enumeratedValues>
26725              </field>
26726              <field>
26727                <name>DM_M</name>
26728                <description>The GPIO Drive Mode for DM IO pad.</description>
26729                <bitRange>[5:3]</bitRange>
26730                <access>read-write</access>
26731              </field>
26732            </fields>
26733          </register>
26734          <register>
26735            <name>FLOW_CTL</name>
26736            <description>Flow Control Register</description>
26737            <addressOffset>0xC</addressOffset>
26738            <size>32</size>
26739            <access>read-write</access>
26740            <resetValue>0x0</resetValue>
26741            <resetMask>0xFF</resetMask>
26742            <fields>
26743              <field>
26744                <name>EP1_ERR_RESP</name>
26745                <description>End Point 1 error response
267460: do nothing (backward compatibility mode)
267471: if this is an IN EP and an underflow occurs then cause a CRC error, if this is an OUT EP and an overflow occurs then send a NAK</description>
26748                <bitRange>[0:0]</bitRange>
26749                <access>read-write</access>
26750              </field>
26751              <field>
26752                <name>EP2_ERR_RESP</name>
26753                <description>End Point 2 error response</description>
26754                <bitRange>[1:1]</bitRange>
26755                <access>read-write</access>
26756              </field>
26757              <field>
26758                <name>EP3_ERR_RESP</name>
26759                <description>End Point 3 error response</description>
26760                <bitRange>[2:2]</bitRange>
26761                <access>read-write</access>
26762              </field>
26763              <field>
26764                <name>EP4_ERR_RESP</name>
26765                <description>End Point 4 error response</description>
26766                <bitRange>[3:3]</bitRange>
26767                <access>read-write</access>
26768              </field>
26769              <field>
26770                <name>EP5_ERR_RESP</name>
26771                <description>End Point 5 error response</description>
26772                <bitRange>[4:4]</bitRange>
26773                <access>read-write</access>
26774              </field>
26775              <field>
26776                <name>EP6_ERR_RESP</name>
26777                <description>End Point 6 error response</description>
26778                <bitRange>[5:5]</bitRange>
26779                <access>read-write</access>
26780              </field>
26781              <field>
26782                <name>EP7_ERR_RESP</name>
26783                <description>End Point 7 error response</description>
26784                <bitRange>[6:6]</bitRange>
26785                <access>read-write</access>
26786              </field>
26787              <field>
26788                <name>EP8_ERR_RESP</name>
26789                <description>End Point 8 error response</description>
26790                <bitRange>[7:7]</bitRange>
26791                <access>read-write</access>
26792              </field>
26793            </fields>
26794          </register>
26795          <register>
26796            <name>LPM_CTL</name>
26797            <description>LPM Control Register</description>
26798            <addressOffset>0x10</addressOffset>
26799            <size>32</size>
26800            <access>read-write</access>
26801            <resetValue>0x0</resetValue>
26802            <resetMask>0x17</resetMask>
26803            <fields>
26804              <field>
26805                <name>LPM_EN</name>
26806                <description>LPM enable
268070: Disabled, LPM token will not get a response (backward compatibility mode)
268081: Enable, LPM token will get a handshake response (ACK, STALL, NYET or NAK)
26809       A STALL will be sent if the bLinkState is not 0001b
26810       A NYET, NAK or ACK response will be sent depending on the NYET_EN and LPM_ACK_RESP bits below</description>
26811                <bitRange>[0:0]</bitRange>
26812                <access>read-write</access>
26813              </field>
26814              <field>
26815                <name>LPM_ACK_RESP</name>
26816                <description>LPM ACK response enable (if LPM_EN=1), to allow firmware to refuse a low power request
268170: a LPM token will get a NYET or NAK (depending on NYET_EN bit below) response and the device will NOT go to a low power mode
268181: a LPM token will get an ACK response and the device will go to the requested low power mode</description>
26819                <bitRange>[1:1]</bitRange>
26820                <access>read-write</access>
26821              </field>
26822              <field>
26823                <name>NYET_EN</name>
26824                <description>Allow firmware to choose which response to use for an LPM token (LPM_EN=1) when the device is NOT ready to go to the requested low power mode (LPM_ACK_RESP=0).
268250: a LPM token will get an NAK response (indicating a CRC error),  the host is expected to repeat the LPM token.
268261: a LPM token will get a NYET response</description>
26827                <bitRange>[2:2]</bitRange>
26828                <access>read-write</access>
26829              </field>
26830              <field>
26831                <name>SUB_RESP</name>
26832                <description>Enable a STALL response for all undefined SubPIDs, i.e. other than LPM (0011b). If not enabled then there will be no response (Error) for the undefined SubPIDs.</description>
26833                <bitRange>[4:4]</bitRange>
26834                <access>read-write</access>
26835              </field>
26836            </fields>
26837          </register>
26838          <register>
26839            <name>LPM_STAT</name>
26840            <description>LPM Status register</description>
26841            <addressOffset>0x14</addressOffset>
26842            <size>32</size>
26843            <access>read-only</access>
26844            <resetValue>0x0</resetValue>
26845            <resetMask>0x1F</resetMask>
26846            <fields>
26847              <field>
26848                <name>LPM_BESL</name>
26849                <description>Best Effort Service Latency
26850This value should match either the Baseline (DeepSleep) or Deep (Hibernate) BESL in the BOS descriptor.</description>
26851                <bitRange>[3:0]</bitRange>
26852                <access>read-only</access>
26853              </field>
26854              <field>
26855                <name>LPM_REMOTEWAKE</name>
26856                <description>0: Device is prohibited from initiating a remote wake
268571: Device is allow to wake the host</description>
26858                <bitRange>[4:4]</bitRange>
26859                <access>read-only</access>
26860              </field>
26861            </fields>
26862          </register>
26863          <register>
26864            <name>INTR_SIE</name>
26865            <description>USB SOF, BUS RESET and EP0 Interrupt Status</description>
26866            <addressOffset>0x20</addressOffset>
26867            <size>32</size>
26868            <access>read-write</access>
26869            <resetValue>0x0</resetValue>
26870            <resetMask>0x1F</resetMask>
26871            <fields>
26872              <field>
26873                <name>SOF_INTR</name>
26874                <description>Interrupt status for USB SOF</description>
26875                <bitRange>[0:0]</bitRange>
26876                <access>read-write</access>
26877              </field>
26878              <field>
26879                <name>BUS_RESET_INTR</name>
26880                <description>Interrupt status for BUS RESET</description>
26881                <bitRange>[1:1]</bitRange>
26882                <access>read-write</access>
26883              </field>
26884              <field>
26885                <name>EP0_INTR</name>
26886                <description>Interrupt status for EP0</description>
26887                <bitRange>[2:2]</bitRange>
26888                <access>read-write</access>
26889              </field>
26890              <field>
26891                <name>LPM_INTR</name>
26892                <description>Interrupt status for LPM  (Link Power Management, L1 entry)</description>
26893                <bitRange>[3:3]</bitRange>
26894                <access>read-write</access>
26895              </field>
26896              <field>
26897                <name>RESUME_INTR</name>
26898                <description>Interrupt status for Resume</description>
26899                <bitRange>[4:4]</bitRange>
26900                <access>read-write</access>
26901              </field>
26902            </fields>
26903          </register>
26904          <register>
26905            <name>INTR_SIE_SET</name>
26906            <description>USB SOF, BUS RESET and EP0 Interrupt Set</description>
26907            <addressOffset>0x24</addressOffset>
26908            <size>32</size>
26909            <access>read-write</access>
26910            <resetValue>0x0</resetValue>
26911            <resetMask>0x1F</resetMask>
26912            <fields>
26913              <field>
26914                <name>SOF_INTR_SET</name>
26915                <description>Write with '1' to set corresponding bit in interrupt request register.</description>
26916                <bitRange>[0:0]</bitRange>
26917                <access>read-write</access>
26918              </field>
26919              <field>
26920                <name>BUS_RESET_INTR_SET</name>
26921                <description>Write with '1' to set corresponding bit in interrupt request register.</description>
26922                <bitRange>[1:1]</bitRange>
26923                <access>read-write</access>
26924              </field>
26925              <field>
26926                <name>EP0_INTR_SET</name>
26927                <description>Write with '1' to set corresponding bit in interrupt request register.</description>
26928                <bitRange>[2:2]</bitRange>
26929                <access>read-write</access>
26930              </field>
26931              <field>
26932                <name>LPM_INTR_SET</name>
26933                <description>Write with '1' to set corresponding bit in interrupt request register.</description>
26934                <bitRange>[3:3]</bitRange>
26935                <access>read-write</access>
26936              </field>
26937              <field>
26938                <name>RESUME_INTR_SET</name>
26939                <description>Write with '1' to set corresponding bit in interrupt request register.</description>
26940                <bitRange>[4:4]</bitRange>
26941                <access>read-write</access>
26942              </field>
26943            </fields>
26944          </register>
26945          <register>
26946            <name>INTR_SIE_MASK</name>
26947            <description>USB SOF, BUS RESET and EP0 Interrupt Mask</description>
26948            <addressOffset>0x28</addressOffset>
26949            <size>32</size>
26950            <access>read-write</access>
26951            <resetValue>0x0</resetValue>
26952            <resetMask>0x1F</resetMask>
26953            <fields>
26954              <field>
26955                <name>SOF_INTR_MASK</name>
26956                <description>Set to 1 to enable interrupt corresponding to interrupt request register</description>
26957                <bitRange>[0:0]</bitRange>
26958                <access>read-write</access>
26959              </field>
26960              <field>
26961                <name>BUS_RESET_INTR_MASK</name>
26962                <description>Set to 1 to enable interrupt corresponding to interrupt request register</description>
26963                <bitRange>[1:1]</bitRange>
26964                <access>read-write</access>
26965              </field>
26966              <field>
26967                <name>EP0_INTR_MASK</name>
26968                <description>Set to 1 to enable interrupt corresponding to interrupt request register</description>
26969                <bitRange>[2:2]</bitRange>
26970                <access>read-write</access>
26971              </field>
26972              <field>
26973                <name>LPM_INTR_MASK</name>
26974                <description>Set to 1 to enable interrupt corresponding to interrupt request register</description>
26975                <bitRange>[3:3]</bitRange>
26976                <access>read-write</access>
26977              </field>
26978              <field>
26979                <name>RESUME_INTR_MASK</name>
26980                <description>Set to 1 to enable interrupt corresponding to interrupt request register</description>
26981                <bitRange>[4:4]</bitRange>
26982                <access>read-write</access>
26983              </field>
26984            </fields>
26985          </register>
26986          <register>
26987            <name>INTR_SIE_MASKED</name>
26988            <description>USB SOF, BUS RESET and EP0 Interrupt Masked</description>
26989            <addressOffset>0x2C</addressOffset>
26990            <size>32</size>
26991            <access>read-only</access>
26992            <resetValue>0x0</resetValue>
26993            <resetMask>0x1F</resetMask>
26994            <fields>
26995              <field>
26996                <name>SOF_INTR_MASKED</name>
26997                <description>Logical and of corresponding request and mask bits.</description>
26998                <bitRange>[0:0]</bitRange>
26999                <access>read-only</access>
27000              </field>
27001              <field>
27002                <name>BUS_RESET_INTR_MASKED</name>
27003                <description>Logical and of corresponding request and mask bits.</description>
27004                <bitRange>[1:1]</bitRange>
27005                <access>read-only</access>
27006              </field>
27007              <field>
27008                <name>EP0_INTR_MASKED</name>
27009                <description>Logical and of corresponding request and mask bits.</description>
27010                <bitRange>[2:2]</bitRange>
27011                <access>read-only</access>
27012              </field>
27013              <field>
27014                <name>LPM_INTR_MASKED</name>
27015                <description>Logical and of corresponding request and mask bits.</description>
27016                <bitRange>[3:3]</bitRange>
27017                <access>read-only</access>
27018              </field>
27019              <field>
27020                <name>RESUME_INTR_MASKED</name>
27021                <description>Logical and of corresponding request and mask bits.</description>
27022                <bitRange>[4:4]</bitRange>
27023                <access>read-only</access>
27024              </field>
27025            </fields>
27026          </register>
27027          <register>
27028            <name>INTR_LVL_SEL</name>
27029            <description>Select interrupt level for each interrupt source</description>
27030            <addressOffset>0x30</addressOffset>
27031            <size>32</size>
27032            <access>read-write</access>
27033            <resetValue>0x0</resetValue>
27034            <resetMask>0xFFFFC3FF</resetMask>
27035            <fields>
27036              <field>
27037                <name>SOF_LVL_SEL</name>
27038                <description>USB SOF Interrupt level select</description>
27039                <bitRange>[1:0]</bitRange>
27040                <access>read-write</access>
27041                <enumeratedValues>
27042                  <enumeratedValue>
27043                    <name>HI</name>
27044                    <description>High priority interrupt</description>
27045                    <value>0</value>
27046                  </enumeratedValue>
27047                  <enumeratedValue>
27048                    <name>MED</name>
27049                    <description>Medium priority interrupt</description>
27050                    <value>1</value>
27051                  </enumeratedValue>
27052                  <enumeratedValue>
27053                    <name>LO</name>
27054                    <description>Low priority interrupt</description>
27055                    <value>2</value>
27056                  </enumeratedValue>
27057                  <enumeratedValue>
27058                    <name>RSVD</name>
27059                    <description>illegal</description>
27060                    <value>3</value>
27061                  </enumeratedValue>
27062                </enumeratedValues>
27063              </field>
27064              <field>
27065                <name>BUS_RESET_LVL_SEL</name>
27066                <description>BUS RESET Interrupt level select</description>
27067                <bitRange>[3:2]</bitRange>
27068                <access>read-write</access>
27069              </field>
27070              <field>
27071                <name>EP0_LVL_SEL</name>
27072                <description>EP0 Interrupt level select</description>
27073                <bitRange>[5:4]</bitRange>
27074                <access>read-write</access>
27075              </field>
27076              <field>
27077                <name>LPM_LVL_SEL</name>
27078                <description>LPM Interrupt level select</description>
27079                <bitRange>[7:6]</bitRange>
27080                <access>read-write</access>
27081              </field>
27082              <field>
27083                <name>RESUME_LVL_SEL</name>
27084                <description>Resume Interrupt level select</description>
27085                <bitRange>[9:8]</bitRange>
27086                <access>read-write</access>
27087              </field>
27088              <field>
27089                <name>ARB_EP_LVL_SEL</name>
27090                <description>Arbiter Endpoint Interrupt level select</description>
27091                <bitRange>[15:14]</bitRange>
27092                <access>read-write</access>
27093              </field>
27094              <field>
27095                <name>EP1_LVL_SEL</name>
27096                <description>EP1 Interrupt level select</description>
27097                <bitRange>[17:16]</bitRange>
27098                <access>read-write</access>
27099              </field>
27100              <field>
27101                <name>EP2_LVL_SEL</name>
27102                <description>EP2 Interrupt level select</description>
27103                <bitRange>[19:18]</bitRange>
27104                <access>read-write</access>
27105              </field>
27106              <field>
27107                <name>EP3_LVL_SEL</name>
27108                <description>EP3 Interrupt level select</description>
27109                <bitRange>[21:20]</bitRange>
27110                <access>read-write</access>
27111              </field>
27112              <field>
27113                <name>EP4_LVL_SEL</name>
27114                <description>EP4 Interrupt level select</description>
27115                <bitRange>[23:22]</bitRange>
27116                <access>read-write</access>
27117              </field>
27118              <field>
27119                <name>EP5_LVL_SEL</name>
27120                <description>EP5 Interrupt level select</description>
27121                <bitRange>[25:24]</bitRange>
27122                <access>read-write</access>
27123              </field>
27124              <field>
27125                <name>EP6_LVL_SEL</name>
27126                <description>EP6 Interrupt level select</description>
27127                <bitRange>[27:26]</bitRange>
27128                <access>read-write</access>
27129              </field>
27130              <field>
27131                <name>EP7_LVL_SEL</name>
27132                <description>EP7 Interrupt level select</description>
27133                <bitRange>[29:28]</bitRange>
27134                <access>read-write</access>
27135              </field>
27136              <field>
27137                <name>EP8_LVL_SEL</name>
27138                <description>EP8 Interrupt level select</description>
27139                <bitRange>[31:30]</bitRange>
27140                <access>read-write</access>
27141              </field>
27142            </fields>
27143          </register>
27144          <register>
27145            <name>INTR_CAUSE_HI</name>
27146            <description>High priority interrupt Cause register</description>
27147            <addressOffset>0x34</addressOffset>
27148            <size>32</size>
27149            <access>read-only</access>
27150            <resetValue>0x0</resetValue>
27151            <resetMask>0xFF9F</resetMask>
27152            <fields>
27153              <field>
27154                <name>SOF_INTR</name>
27155                <description>USB SOF Interrupt</description>
27156                <bitRange>[0:0]</bitRange>
27157                <access>read-only</access>
27158              </field>
27159              <field>
27160                <name>BUS_RESET_INTR</name>
27161                <description>BUS RESET Interrupt</description>
27162                <bitRange>[1:1]</bitRange>
27163                <access>read-only</access>
27164              </field>
27165              <field>
27166                <name>EP0_INTR</name>
27167                <description>EP0 Interrupt</description>
27168                <bitRange>[2:2]</bitRange>
27169                <access>read-only</access>
27170              </field>
27171              <field>
27172                <name>LPM_INTR</name>
27173                <description>LPM Interrupt</description>
27174                <bitRange>[3:3]</bitRange>
27175                <access>read-only</access>
27176              </field>
27177              <field>
27178                <name>RESUME_INTR</name>
27179                <description>Resume Interrupt</description>
27180                <bitRange>[4:4]</bitRange>
27181                <access>read-only</access>
27182              </field>
27183              <field>
27184                <name>ARB_EP_INTR</name>
27185                <description>Arbiter Endpoint Interrupt</description>
27186                <bitRange>[7:7]</bitRange>
27187                <access>read-only</access>
27188              </field>
27189              <field>
27190                <name>EP1_INTR</name>
27191                <description>EP1 Interrupt</description>
27192                <bitRange>[8:8]</bitRange>
27193                <access>read-only</access>
27194              </field>
27195              <field>
27196                <name>EP2_INTR</name>
27197                <description>EP2 Interrupt</description>
27198                <bitRange>[9:9]</bitRange>
27199                <access>read-only</access>
27200              </field>
27201              <field>
27202                <name>EP3_INTR</name>
27203                <description>EP3 Interrupt</description>
27204                <bitRange>[10:10]</bitRange>
27205                <access>read-only</access>
27206              </field>
27207              <field>
27208                <name>EP4_INTR</name>
27209                <description>EP4 Interrupt</description>
27210                <bitRange>[11:11]</bitRange>
27211                <access>read-only</access>
27212              </field>
27213              <field>
27214                <name>EP5_INTR</name>
27215                <description>EP5 Interrupt</description>
27216                <bitRange>[12:12]</bitRange>
27217                <access>read-only</access>
27218              </field>
27219              <field>
27220                <name>EP6_INTR</name>
27221                <description>EP6 Interrupt</description>
27222                <bitRange>[13:13]</bitRange>
27223                <access>read-only</access>
27224              </field>
27225              <field>
27226                <name>EP7_INTR</name>
27227                <description>EP7 Interrupt</description>
27228                <bitRange>[14:14]</bitRange>
27229                <access>read-only</access>
27230              </field>
27231              <field>
27232                <name>EP8_INTR</name>
27233                <description>EP8 Interrupt</description>
27234                <bitRange>[15:15]</bitRange>
27235                <access>read-only</access>
27236              </field>
27237            </fields>
27238          </register>
27239          <register>
27240            <name>INTR_CAUSE_MED</name>
27241            <description>Medium priority interrupt Cause register</description>
27242            <addressOffset>0x38</addressOffset>
27243            <size>32</size>
27244            <access>read-only</access>
27245            <resetValue>0x0</resetValue>
27246            <resetMask>0xFF9F</resetMask>
27247            <fields>
27248              <field>
27249                <name>SOF_INTR</name>
27250                <description>USB SOF Interrupt</description>
27251                <bitRange>[0:0]</bitRange>
27252                <access>read-only</access>
27253              </field>
27254              <field>
27255                <name>BUS_RESET_INTR</name>
27256                <description>BUS RESET Interrupt</description>
27257                <bitRange>[1:1]</bitRange>
27258                <access>read-only</access>
27259              </field>
27260              <field>
27261                <name>EP0_INTR</name>
27262                <description>EP0 Interrupt</description>
27263                <bitRange>[2:2]</bitRange>
27264                <access>read-only</access>
27265              </field>
27266              <field>
27267                <name>LPM_INTR</name>
27268                <description>LPM Interrupt</description>
27269                <bitRange>[3:3]</bitRange>
27270                <access>read-only</access>
27271              </field>
27272              <field>
27273                <name>RESUME_INTR</name>
27274                <description>Resume Interrupt</description>
27275                <bitRange>[4:4]</bitRange>
27276                <access>read-only</access>
27277              </field>
27278              <field>
27279                <name>ARB_EP_INTR</name>
27280                <description>Arbiter Endpoint Interrupt</description>
27281                <bitRange>[7:7]</bitRange>
27282                <access>read-only</access>
27283              </field>
27284              <field>
27285                <name>EP1_INTR</name>
27286                <description>EP1 Interrupt</description>
27287                <bitRange>[8:8]</bitRange>
27288                <access>read-only</access>
27289              </field>
27290              <field>
27291                <name>EP2_INTR</name>
27292                <description>EP2 Interrupt</description>
27293                <bitRange>[9:9]</bitRange>
27294                <access>read-only</access>
27295              </field>
27296              <field>
27297                <name>EP3_INTR</name>
27298                <description>EP3 Interrupt</description>
27299                <bitRange>[10:10]</bitRange>
27300                <access>read-only</access>
27301              </field>
27302              <field>
27303                <name>EP4_INTR</name>
27304                <description>EP4 Interrupt</description>
27305                <bitRange>[11:11]</bitRange>
27306                <access>read-only</access>
27307              </field>
27308              <field>
27309                <name>EP5_INTR</name>
27310                <description>EP5 Interrupt</description>
27311                <bitRange>[12:12]</bitRange>
27312                <access>read-only</access>
27313              </field>
27314              <field>
27315                <name>EP6_INTR</name>
27316                <description>EP6 Interrupt</description>
27317                <bitRange>[13:13]</bitRange>
27318                <access>read-only</access>
27319              </field>
27320              <field>
27321                <name>EP7_INTR</name>
27322                <description>EP7 Interrupt</description>
27323                <bitRange>[14:14]</bitRange>
27324                <access>read-only</access>
27325              </field>
27326              <field>
27327                <name>EP8_INTR</name>
27328                <description>EP8 Interrupt</description>
27329                <bitRange>[15:15]</bitRange>
27330                <access>read-only</access>
27331              </field>
27332            </fields>
27333          </register>
27334          <register>
27335            <name>INTR_CAUSE_LO</name>
27336            <description>Low priority interrupt Cause register</description>
27337            <addressOffset>0x3C</addressOffset>
27338            <size>32</size>
27339            <access>read-only</access>
27340            <resetValue>0x0</resetValue>
27341            <resetMask>0xFF9F</resetMask>
27342            <fields>
27343              <field>
27344                <name>SOF_INTR</name>
27345                <description>USB SOF Interrupt</description>
27346                <bitRange>[0:0]</bitRange>
27347                <access>read-only</access>
27348              </field>
27349              <field>
27350                <name>BUS_RESET_INTR</name>
27351                <description>BUS RESET Interrupt</description>
27352                <bitRange>[1:1]</bitRange>
27353                <access>read-only</access>
27354              </field>
27355              <field>
27356                <name>EP0_INTR</name>
27357                <description>EP0 Interrupt</description>
27358                <bitRange>[2:2]</bitRange>
27359                <access>read-only</access>
27360              </field>
27361              <field>
27362                <name>LPM_INTR</name>
27363                <description>LPM Interrupt</description>
27364                <bitRange>[3:3]</bitRange>
27365                <access>read-only</access>
27366              </field>
27367              <field>
27368                <name>RESUME_INTR</name>
27369                <description>Resume Interrupt</description>
27370                <bitRange>[4:4]</bitRange>
27371                <access>read-only</access>
27372              </field>
27373              <field>
27374                <name>ARB_EP_INTR</name>
27375                <description>Arbiter Endpoint Interrupt</description>
27376                <bitRange>[7:7]</bitRange>
27377                <access>read-only</access>
27378              </field>
27379              <field>
27380                <name>EP1_INTR</name>
27381                <description>EP1 Interrupt</description>
27382                <bitRange>[8:8]</bitRange>
27383                <access>read-only</access>
27384              </field>
27385              <field>
27386                <name>EP2_INTR</name>
27387                <description>EP2 Interrupt</description>
27388                <bitRange>[9:9]</bitRange>
27389                <access>read-only</access>
27390              </field>
27391              <field>
27392                <name>EP3_INTR</name>
27393                <description>EP3 Interrupt</description>
27394                <bitRange>[10:10]</bitRange>
27395                <access>read-only</access>
27396              </field>
27397              <field>
27398                <name>EP4_INTR</name>
27399                <description>EP4 Interrupt</description>
27400                <bitRange>[11:11]</bitRange>
27401                <access>read-only</access>
27402              </field>
27403              <field>
27404                <name>EP5_INTR</name>
27405                <description>EP5 Interrupt</description>
27406                <bitRange>[12:12]</bitRange>
27407                <access>read-only</access>
27408              </field>
27409              <field>
27410                <name>EP6_INTR</name>
27411                <description>EP6 Interrupt</description>
27412                <bitRange>[13:13]</bitRange>
27413                <access>read-only</access>
27414              </field>
27415              <field>
27416                <name>EP7_INTR</name>
27417                <description>EP7 Interrupt</description>
27418                <bitRange>[14:14]</bitRange>
27419                <access>read-only</access>
27420              </field>
27421              <field>
27422                <name>EP8_INTR</name>
27423                <description>EP8 Interrupt</description>
27424                <bitRange>[15:15]</bitRange>
27425                <access>read-only</access>
27426              </field>
27427            </fields>
27428          </register>
27429          <register>
27430            <name>DFT_CTL</name>
27431            <description>DFT control</description>
27432            <addressOffset>0x70</addressOffset>
27433            <size>32</size>
27434            <access>read-write</access>
27435            <resetValue>0x0</resetValue>
27436            <resetMask>0x1F</resetMask>
27437            <fields>
27438              <field>
27439                <name>DDFT_OUT_SEL</name>
27440                <description>DDFT output select signal</description>
27441                <bitRange>[2:0]</bitRange>
27442                <access>read-write</access>
27443                <enumeratedValues>
27444                  <enumeratedValue>
27445                    <name>OFF</name>
27446                    <description>Nothing connected, output 0</description>
27447                    <value>0</value>
27448                  </enumeratedValue>
27449                  <enumeratedValue>
27450                    <name>DP_SE</name>
27451                    <description>Single Ended output of DP</description>
27452                    <value>1</value>
27453                  </enumeratedValue>
27454                  <enumeratedValue>
27455                    <name>DM_SE</name>
27456                    <description>Single Ended output of DM</description>
27457                    <value>2</value>
27458                  </enumeratedValue>
27459                  <enumeratedValue>
27460                    <name>TXOE</name>
27461                    <description>Output Enable</description>
27462                    <value>3</value>
27463                  </enumeratedValue>
27464                  <enumeratedValue>
27465                    <name>RCV_DF</name>
27466                    <description>Differential Receiver output</description>
27467                    <value>4</value>
27468                  </enumeratedValue>
27469                  <enumeratedValue>
27470                    <name>GPIO_DP_OUT</name>
27471                    <description>GPIO output of DP</description>
27472                    <value>5</value>
27473                  </enumeratedValue>
27474                  <enumeratedValue>
27475                    <name>GPIO_DM_OUT</name>
27476                    <description>GPIO output of DM</description>
27477                    <value>6</value>
27478                  </enumeratedValue>
27479                </enumeratedValues>
27480              </field>
27481              <field>
27482                <name>DDFT_IN_SEL</name>
27483                <description>DDFT input select signal</description>
27484                <bitRange>[4:3]</bitRange>
27485                <access>read-write</access>
27486                <enumeratedValues>
27487                  <enumeratedValue>
27488                    <name>OFF</name>
27489                    <description>Nothing connected, output 0</description>
27490                    <value>0</value>
27491                  </enumeratedValue>
27492                  <enumeratedValue>
27493                    <name>GPIO_DP_IN</name>
27494                    <description>GPIO input of DP</description>
27495                    <value>1</value>
27496                  </enumeratedValue>
27497                  <enumeratedValue>
27498                    <name>GPIO_DM_IN</name>
27499                    <description>GPIO input of DM</description>
27500                    <value>2</value>
27501                  </enumeratedValue>
27502                </enumeratedValues>
27503              </field>
27504            </fields>
27505          </register>
27506        </cluster>
27507        <cluster>
27508          <name>USBHOST</name>
27509          <description>USB Host Controller</description>
27510          <addressOffset>0x00004000</addressOffset>
27511          <register>
27512            <name>HOST_CTL0</name>
27513            <description>Host Control 0 Register.</description>
27514            <addressOffset>0x0</addressOffset>
27515            <size>32</size>
27516            <access>read-write</access>
27517            <resetValue>0x0</resetValue>
27518            <resetMask>0x80000001</resetMask>
27519            <fields>
27520              <field>
27521                <name>HOST</name>
27522                <description>This bit selects an operating mode of this IP.
27523'0' : USB Device
27524'1' : USB Host
27525Notes:
27526- The mode of operation mode does not transition immediately after setting this bit.  Read this bit to confirm that the operation mode has changed.
27527- This bit is reset to '0' if the ENABLE bit in this register changes from '1' to '0'.
27528- Before changing from the USB Host to the USB Device, check that the following conditions are satisfied and also set the RST bit of the Host Control 1 Register (HOST_CTL1). to '1'.
27529     * The SOFBUSY bit of the Host Status Register (HOST_STATUS) is set to '0'.
27530     * The TKNEN bits of the Host Token Endpoint Register (HOST_TOKEN) is set to '000'.
27531     * The SUSP bit of the Host Status Register (HOST_STATUS) is set to '0'.</description>
27532                <bitRange>[0:0]</bitRange>
27533                <access>read-write</access>
27534              </field>
27535              <field>
27536                <name>ENABLE</name>
27537                <description>This bit enables the operation of this IP.
27538'0' : Disable USB Host
27539'1' : Enable USB Host
27540Note:
27541- This bit doesn't affect the USB Device.</description>
27542                <bitRange>[31:31]</bitRange>
27543                <access>read-write</access>
27544              </field>
27545            </fields>
27546          </register>
27547          <register>
27548            <name>HOST_CTL1</name>
27549            <description>Host Control 1 Register.</description>
27550            <addressOffset>0x10</addressOffset>
27551            <size>32</size>
27552            <access>read-write</access>
27553            <resetValue>0x83</resetValue>
27554            <resetMask>0x83</resetMask>
27555            <fields>
27556              <field>
27557                <name>CLKSEL</name>
27558                <description>This bit selects the operating clock of USB Host.
27559'0' : Low-speed clock
27560'1' : Full-speed clock
27561Notes:
27562- This bit is set to it's default vaulue '1' if the ENABLE bit of the Host Control 0 Register (HOST_CTL0) changes from '1' to '0'.
27563- This bit must always be set to '1' in the USB Device mode.</description>
27564                <bitRange>[0:0]</bitRange>
27565                <access>read-write</access>
27566              </field>
27567              <field>
27568                <name>USTP</name>
27569                <description>This bit stops the clock for the USB Host operating unit. When this bit is '1', power consumption can be reduced by configuring this bit.
27570'0' : Normal operating mode.
27571'1' : Stops the clock for the USB Host operating unit.
27572Notes:
27573- If this bit is set to '1', the function of USB Host can't be used because internal clock is stopped.
27574- This bit is initialized if ENABLE bit of the Host Control 0 Register (HOST_CTL0) changes from '1' to '0'.</description>
27575                <bitRange>[1:1]</bitRange>
27576                <access>read-write</access>
27577              </field>
27578              <field>
27579                <name>RST</name>
27580                <description>This bit resets the USB Host.
27581'0' : Normal operating mode.
27582'1' : USB Host is reset.
27583Notes:
27584- This bit is to it's default value '1' if  the ENABLE bit of the Host Control 0 Register (HOST_CTL0) changes from '1' to '0'.
27585- If this bit is set to '1', both the BFINI bits of the Host Endpoint 1 Control Register (HOST_EP1_CTL) and Host Endpoint 2 Control Register (HOST_EP2_CTL) are set to '1'.</description>
27586                <bitRange>[7:7]</bitRange>
27587                <access>read-write</access>
27588              </field>
27589            </fields>
27590          </register>
27591          <register>
27592            <name>HOST_CTL2</name>
27593            <description>Host Control 2 Register.</description>
27594            <addressOffset>0x100</addressOffset>
27595            <size>32</size>
27596            <access>read-write</access>
27597            <resetValue>0x1</resetValue>
27598            <resetMask>0xFF</resetMask>
27599            <fields>
27600              <field>
27601                <name>RETRY</name>
27602                <description>If this bit is set to '1', the target token is retried if a NAK or error* occurs. Retry processing is performed after the time that is specified in the Host Retry Timer Setup Register (HOST_RTIMER).
27603* : HOST_ERR.RERR='1', HOST_ERR.TOUT='1', HOST_ERR.CRC='1', HOST_ERR.TGERR='1', HOST_ERR.STUFF='1'
27604'0' : Doesn't retry token sending.
27605'1' : Retries token sending
27606Note:
27607- This bit isn't initialized even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
27608                <bitRange>[0:0]</bitRange>
27609                <access>read-write</access>
27610              </field>
27611              <field>
27612                <name>CANCEL</name>
27613                <description>When this bit is set to '1', if the target token is written to the Host Token Endpoint Register (HOST_TOKEN) in the EOF area (specified in the Host EOF Setup Register), its sending is canceled. When this bit is set to '0', token sending is not canceled even if the target token is written to the register. The cancellation of token sending is detected by reading the TCAN bit of the Interrupt USB Host Register (INTR_USBHOST).
27614'0' : Continues a token.
27615'1' : Cancels a token.</description>
27616                <bitRange>[1:1]</bitRange>
27617                <access>read-write</access>
27618              </field>
27619              <field>
27620                <name>SOFSTEP</name>
27621                <description>If this bit is set to '1', the SOF interrupt flag (INTR_USBHOST.SOFIRQ) is set to '1' each time SOF is sent.
27622If this bit is set to '0', the set value of the Host SOF Interrupt Frame Compare Register (HOST_FCOMP) is compared with the low-order eight bits of the SOF frame number. If they match, the SOF interrupt flag (INTR_USBHOST.SOFIRQ) is set to '1'.
27623'0' : An interrupt occurred due to the HOST_HFCOMP setting.
27624'1' : An interrupt occurred.
27625Notes:
27626- If a SOF token (TKNEN='001') is sent by the setting of the Host Token Endpoint Register (HOST_TOKEN), the SOF interrupt flag (INTR_USBHOST.SOFIRQ) is not set to '1' regardless of the setting of this bit.</description>
27627                <bitRange>[2:2]</bitRange>
27628                <access>read-write</access>
27629              </field>
27630              <field>
27631                <name>ALIVE</name>
27632                <description>This bit is used to specify the keep-alive function in the low-speed mode. If this bit it set to '1' while the CLKSEL bit of the Host Control 1 Register (HOST_CTL1) is '0', SE0 is output instead of SOF. This bit is only effective when the CLKSEL bit is '0'. If the CLKSEL bit is '1' (Full-Speed mode), SOF is output regardless of the setting of the ALIVE bit.
27633'0' : SOF output.
27634'1' : SE0 output (Keep alive)</description>
27635                <bitRange>[3:3]</bitRange>
27636                <access>read-write</access>
27637              </field>
27638              <field>
27639                <name>RSVD_4</name>
27640                <description>N/A</description>
27641                <bitRange>[4:4]</bitRange>
27642                <access>read-write</access>
27643              </field>
27644              <field>
27645                <name>RSVD_5</name>
27646                <description>N/A</description>
27647                <bitRange>[5:5]</bitRange>
27648                <access>read-write</access>
27649              </field>
27650              <field>
27651                <name>TTEST</name>
27652                <description>N/A</description>
27653                <bitRange>[7:6]</bitRange>
27654                <access>read-write</access>
27655              </field>
27656            </fields>
27657          </register>
27658          <register>
27659            <name>HOST_ERR</name>
27660            <description>Host Error Status Register.</description>
27661            <addressOffset>0x104</addressOffset>
27662            <size>32</size>
27663            <access>read-write</access>
27664            <resetValue>0x3</resetValue>
27665            <resetMask>0xFF</resetMask>
27666            <fields>
27667              <field>
27668                <name>HS</name>
27669                <description>These flags indicate the status of a handshake packet to be sent or received.
27670These flags are set to 'NULL' when no handshake occurs due to an error or when a SOF token has been ended with the TKNEN bit of the Host Token Endpoint Register (HOST_TOKEN).
27671These bits are updated when sending or receiving has been ended.
27672Write '11' to set the status back to 'NULL', all other write values are ignored.
27673Note:
27674This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
27675                <bitRange>[1:0]</bitRange>
27676                <access>read-write</access>
27677                <enumeratedValues>
27678                  <enumeratedValue>
27679                    <name>ACK</name>
27680                    <description>Acknowledge Packet</description>
27681                    <value>0</value>
27682                  </enumeratedValue>
27683                  <enumeratedValue>
27684                    <name>NAK</name>
27685                    <description>Non-Acknowledge Packet</description>
27686                    <value>1</value>
27687                  </enumeratedValue>
27688                  <enumeratedValue>
27689                    <name>STALL</name>
27690                    <description>Stall Packet</description>
27691                    <value>2</value>
27692                  </enumeratedValue>
27693                  <enumeratedValue>
27694                    <name>NULL</name>
27695                    <description>Null Packet</description>
27696                    <value>3</value>
27697                  </enumeratedValue>
27698                </enumeratedValues>
27699              </field>
27700              <field>
27701                <name>STUFF</name>
27702                <description>If this bit is set to '1', it means that a bit stuffing error has been detected. When this bit is '0', it means that no error is detected. If a stuffing error is detected, bit5 (TOUT) of this register is also set to '1'.  Write '1' to clear, a write of '0' is ignored.
27703'0' : No stuffing error.
27704'1' : Stuffing error detected.
27705Note:
27706- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
27707                <bitRange>[2:2]</bitRange>
27708                <access>read-write</access>
27709              </field>
27710              <field>
27711                <name>TGERR</name>
27712                <description>If this bit is set to '1', it means that the data does not match the TGGL data. When this bit is '0', it means that no error is detected. Write '1' to clear, a write of '0' is ignored.
27713'0' : No toggle error.
27714'1' : Toggle error detected.
27715Note:
27716- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
27717                <bitRange>[3:3]</bitRange>
27718                <access>read-write</access>
27719              </field>
27720              <field>
27721                <name>CRC</name>
27722                <description>If this bit is set to '1', it means that a CRC error is detected in the USB Host. When this bit is '0', it means that no error is detected. If a CRC error is detected, bit5 (TOUT) of this register is also set to '1'.  Write '1' to clear, a write of '0' is ignored.
27723'0' : No CRC error.
27724'1' : CRC error detected.
27725Note:
27726- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
27727                <bitRange>[4:4]</bitRange>
27728                <access>read-write</access>
27729              </field>
27730              <field>
27731                <name>TOUT</name>
27732                <description>If this bit is set to '1', it means that no response is returned from the device within the specified time after a token has been sent in the USB Host. When this bit is '0', it means that no timeout is detected.  Write '1' to clear, a write of '0' is ignored.
27733'0' : No timeout.
27734'1' : Timeout has detected.
27735Note:
27736- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
27737                <bitRange>[5:5]</bitRange>
27738                <access>read-write</access>
27739              </field>
27740              <field>
27741                <name>RERR</name>
27742                <description>When this bit is set to '1', it means that the received data exceeds the specified maximum number of packets in the USB Host. If a receive error is detected, bit5 (TOUT) of this register is also set to '1'. When this bit is '0', it means that no error is detected. Write '1' to clear, a write of '0' is ignored.
27743'0' : No receive error.
27744'1' : Maximum packet receive error detected.
27745- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
27746                <bitRange>[6:6]</bitRange>
27747                <access>read-write</access>
27748              </field>
27749              <field>
27750                <name>LSTSOF</name>
27751                <description>If this bit is set to '1', it means that the SOF token can't be sent in the USB Host because other token is in process. When this bit is '0', it means that SOF token was sent with no error. Write '1' to clear, a write of '0' is ignored.
27752'0' : SOF sent without error.
27753'1' : SOF error detected.
27754Note:
27755- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
27756                <bitRange>[7:7]</bitRange>
27757                <access>read-write</access>
27758              </field>
27759            </fields>
27760          </register>
27761          <register>
27762            <name>HOST_STATUS</name>
27763            <description>Host Status Register.</description>
27764            <addressOffset>0x108</addressOffset>
27765            <size>32</size>
27766            <access>read-write</access>
27767            <resetValue>0xC2</resetValue>
27768            <resetMask>0x1FF</resetMask>
27769            <fields>
27770              <field>
27771                <name>CSTAT</name>
27772                <description>When this bit is '1', it means that the device is connected. When this bit is '0', it means that the device is disconnected.
27773'0' : Device is disconnected.
27774'1' : Device is connected.
27775Notes:
27776- This bit is set to the default value if the RST bit of the Host Control 1 Register (Host_CTL1) is set to '1'.
27777- The transition to disconnected on RST isn't immediate.  Read this bit to confirm the transition is complete.</description>
27778                <bitRange>[0:0]</bitRange>
27779                <access>read-only</access>
27780              </field>
27781              <field>
27782                <name>TMODE</name>
27783                <description>If this bit is '1', it means that the device is connected in the full-speed mode. When this bit is '0', it means that the device is connected in the low-speed mode. This bit is valid when the CSTAT bit of the Host Status Register (HOST_STATUS) is '1'.
27784'0' : Low-speed.
27785'1' : Full-speed.
27786Notes:
27787- This bit is set to the default value if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.
27788- The transition to disconnected on RST isn't immediate.  Read this bit to confirm the transition is complete.</description>
27789                <bitRange>[1:1]</bitRange>
27790                <access>read-only</access>
27791              </field>
27792              <field>
27793                <name>SUSP</name>
27794                <description>If this bit is set to '1', the USB Host is placed into the suspend state. If this bit is set to '0' while it is '1' or the USB bus is placed into the k-state mode, then suspend state is released, and the RWIRQ bit of the Interrupt USB Host Register (INTR_USBHOST) is set to '1'.
27795Set to '1' : Suspend.
27796Set '0' when this bit is '1' : Resume.
27797Other conditions : Holds the status.
27798Notes:
27799- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.
27800- The transition to disconnected on RST isn't immediate.  Read this bit to confirm the transition is complete.
27801- If this bit is set to '1', this bit must not be set to '1' until the RWIRQ bit of the Interrupt USB Host Register (INTR_USBHOST) is set to '1'.
27802- Do not set this bit to '1' while the USB is active (during USB bus resetting, data transfer, or SOF timer running).
27803- If the value of this bit is changed, it is not immediately reflected on the state of the USB bus. To check whether or not the state is updated, read this bit.</description>
27804                <bitRange>[2:2]</bitRange>
27805                <access>read-write</access>
27806              </field>
27807              <field>
27808                <name>SOFBUSY</name>
27809                <description>When a SOF token is sent using the Host Token Endpoint Register (HOST_TOKEN), this bit is set to '1', which means that the SOF timer is active. When this bit is '0', it means that the SOF timer is under suspension. To stop the active SOF timer, write '0' to this bit. However, if this bit is written with '1', its value is ignored.
27810'0' : The SOF timer is stopped.
27811'1' : The SOF timer is active.
27812Notes:
27813- This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.
27814- This bit takes time to be initialized by the RST bit of the Host Control 1 Resgiter (HOST_CTL1).
27815- The SOF timer does not stop immediately after this bit has been set to '0' to stop the SOF timer. To check whether or not the SOF timer is stopped, read this bit.</description>
27816                <bitRange>[3:3]</bitRange>
27817                <access>read-write</access>
27818              </field>
27819              <field>
27820                <name>URST</name>
27821                <description>When this bit is set to '1', the USB bus is reset. This bit remains a '1' during USB bus resetting, and changes to '0' when USB bus resetting is ended. If this bit is set to '0', the USB bus reset is complete</description>
27822                <bitRange>[4:4]</bitRange>
27823                <access>read-write</access>
27824              </field>
27825              <field>
27826                <name>RSVD_5</name>
27827                <description>N/A</description>
27828                <bitRange>[5:5]</bitRange>
27829                <access>read-only</access>
27830              </field>
27831              <field>
27832                <name>RSTBUSY</name>
27833                <description>This bit shows that USB Host is being reset internally. If the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1', this bit is set to '1'.
27834If the RST bit of Host Control 1 Register (HOST_CTL1) is set to '0', this bit is set to '0'.
27835'0' : USB Host isn't being reset.
27836'1' : USB Host is being reset.
27837Notes:
27838- If this bit is '1', the a token must not be executed.
27839- This bit isn't set to '0' or '1' immediately even if the RST bit of Host Control 1 Register (HOST_CTL1) is set to '0' or '1'. Read this bit to confirm the operation is complete.</description>
27840                <bitRange>[6:6]</bitRange>
27841                <access>read-only</access>
27842              </field>
27843              <field>
27844                <name>CLKSEL_ST</name>
27845                <description>This bit shows whether it is full-speed or not. If the CLKSEL bit of the Host Control 1 Register (HOST_CTL1) is set to '1', this bit is set to '1'.
27846'0' : Low speed
27847'1' : Full speed
27848Note:
27849- If this bit is different from the CLKSEL bit, The execution of the token and bus reset must wait these bits match.
27850- This bit takes time to be initialized by the RST bit of the Host Control 1 Resgiter (HOST_CTL1). Read this bit to confirm the operation is complete.</description>
27851                <bitRange>[7:7]</bitRange>
27852                <access>read-only</access>
27853              </field>
27854              <field>
27855                <name>HOST_ST</name>
27856                <description>This bit shows whether the device is in USB Host mode. If the HOST bit of the Host Control Register (HOST_CTL0) is set to '1', this bit is set to '1'.
27857'0' : USB Device
27858'1' : USB Host
27859Notes:
27860- If this bit is different from the HOST bit, The execution of a token must wait these bits match.
27861- This bit takes time to be initialized by the RST bit of the Host Control 1 Resgiter (HOST_CTL1). Read this bit to confirm the operation is complete.</description>
27862                <bitRange>[8:8]</bitRange>
27863                <access>read-only</access>
27864              </field>
27865            </fields>
27866          </register>
27867          <register>
27868            <name>HOST_FCOMP</name>
27869            <description>Host SOF Interrupt Frame Compare Register</description>
27870            <addressOffset>0x10C</addressOffset>
27871            <size>32</size>
27872            <access>read-write</access>
27873            <resetValue>0x0</resetValue>
27874            <resetMask>0xFF</resetMask>
27875            <fields>
27876              <field>
27877                <name>FRAMECOMP</name>
27878                <description>These bits are used to specify the data to be compared with the low-order eight bits of a frame number when sending a SOF token.
27879If the SOFSTEP bit of Host Control 2 Register (HOST_CTL2) is '0', the frame number of SOF is compared with the value of this register when sending a SOF token. If they match, the SOFIRQ bit of the Interrupt USB Host Register (INTR_USBHOST) is set to '1'.
27880The setting of this register is invalid when the SOFSTEP bit of Host Control 2 Register (HOST_CTL2) is '1'.
27881Note:
27882- This bit is not reset to default even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
27883                <bitRange>[7:0]</bitRange>
27884                <access>read-write</access>
27885              </field>
27886            </fields>
27887          </register>
27888          <register>
27889            <name>HOST_RTIMER</name>
27890            <description>Host Retry Timer Setup Register</description>
27891            <addressOffset>0x110</addressOffset>
27892            <size>32</size>
27893            <access>read-write</access>
27894            <resetValue>0x0</resetValue>
27895            <resetMask>0x3FFFF</resetMask>
27896            <fields>
27897              <field>
27898                <name>RTIMER</name>
27899                <description>These bits are used to specify the retry time in this register. The retry timer is activated when token sending starts while the RETRY bit of Host Control 2 Register (HOST_CTL2) is '1'. The retry time is then decremented by one when a 1-bit transfer clock (12 MHz in the full-speed mode) is output. When the retry timer reaches 0, the target token is sent, and processing ends.
27900If a token retry occurs in the EOF area, the retry timer is stopped until SOF sending is ended. After SOF sending has been completed, the retry timer restarts with the value that is set when the timer stopped.</description>
27901                <bitRange>[17:0]</bitRange>
27902                <access>read-write</access>
27903              </field>
27904            </fields>
27905          </register>
27906          <register>
27907            <name>HOST_ADDR</name>
27908            <description>Host Address Register</description>
27909            <addressOffset>0x114</addressOffset>
27910            <size>32</size>
27911            <access>read-write</access>
27912            <resetValue>0x0</resetValue>
27913            <resetMask>0x7F</resetMask>
27914            <fields>
27915              <field>
27916                <name>ADDRESS</name>
27917                <description>These bits are used to specify a token address.
27918Note:
27919- This bit is reset to default even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
27920                <bitRange>[6:0]</bitRange>
27921                <access>read-write</access>
27922              </field>
27923            </fields>
27924          </register>
27925          <register>
27926            <name>HOST_EOF</name>
27927            <description>Host EOF Setup Register</description>
27928            <addressOffset>0x118</addressOffset>
27929            <size>32</size>
27930            <access>read-write</access>
27931            <resetValue>0x0</resetValue>
27932            <resetMask>0x3FFF</resetMask>
27933            <fields>
27934              <field>
27935                <name>EOF</name>
27936                <description>These bits are used to specify the time to disable token sending before transferring SOF. Specify the time with a margin, which is longer than the one-packet length. The time unit is the 1-bit transfer time.
27937Setting example: MAXPKT = 64 bytes, full-speed mode
27938 (Token_length + packet_length + header + CRC)*7/6 + Turn_around_time
27939  =(34 bit + 546 bit)*7/6 + 36 bit = 712.7 bit
27940 Therefore, set 0x2C9.
27941Note:
27942- This bit is not reset to default even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
27943                <bitRange>[13:0]</bitRange>
27944                <access>read-write</access>
27945              </field>
27946            </fields>
27947          </register>
27948          <register>
27949            <name>HOST_FRAME</name>
27950            <description>Host Frame Setup Register</description>
27951            <addressOffset>0x11C</addressOffset>
27952            <size>32</size>
27953            <access>read-write</access>
27954            <resetValue>0x0</resetValue>
27955            <resetMask>0x7FF</resetMask>
27956            <fields>
27957              <field>
27958                <name>FRAME</name>
27959                <description>These bits are used to specify a frame number of SOF.
27960Notes:
27961- This bit isn't reset to default even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.
27962- Specify a frame number in this register before setting SOF in the TKNEN bit of the Host Token Endpoint Register (HOST_TOKEN).
27963- This register cannot be written while the SOFBUSY bit of the Host Status Register (HOST_STATUS) is '1' and a SOF token is in process.</description>
27964                <bitRange>[10:0]</bitRange>
27965                <access>read-write</access>
27966              </field>
27967            </fields>
27968          </register>
27969          <register>
27970            <name>HOST_TOKEN</name>
27971            <description>Host Token Endpoint Register</description>
27972            <addressOffset>0x120</addressOffset>
27973            <size>32</size>
27974            <access>read-write</access>
27975            <resetValue>0x0</resetValue>
27976            <resetMask>0x17F</resetMask>
27977            <fields>
27978              <field>
27979                <name>ENDPT</name>
27980                <description>These bits are used to specify an endpoint to send or receive data to or from the device.
27981Note:
27982- This bit isn't reset to default even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
27983                <bitRange>[3:0]</bitRange>
27984                <access>read-write</access>
27985              </field>
27986              <field>
27987                <name>TKNEN</name>
27988                <description>These bits send a token according to the current settings. After operation is complete, the TKNEN bit is set to '000', and the CMPIRQ bit of the Interrupt USB Host Register (INTR_USBHOST) is set to '1'.
27989The settings of the TGGL and ENDPT bits are ignored when sending a SOF token.
27990Notes:
27991- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.
27992- The PRE packet isn't supported.
27993- Do not set '100' to the TKNEN bit when the SOFBUSY bit of the Host Status Register (HOST_STATUS) is '1'
27994- Mode should be USB Host before writing data to this bit.
27995- When issuing a token again after the token interrupt flag (CMPIRQ) has been set to '1', wait for 3 cycles or more after a USB transfer clock (12 MHz in the full-speed mode, 1.5 MHz in the low-speed mode) was output, then write data to this bit.
27996- Read the value of TKNEN bit if a new value is written in it .Continue writing in this bit until a retrieved value equals a new value written in. During this checking process, it is needed to prevent any interrupt.
27997- Take the following steps when CMPIRQ bit of Interrupt USB Host Register (INTR_USBHOST) is set to '1' by finishing IN token or Isochronous IN token.
279981. Read HS bit of Host Error Status Register (HOST_ERR), then set CMPIRQ bit to '0'.
279992. Set EPn bit of Host DMA Enable Register (HOST_DMA_ENBL) (n=1 or 2) to '1' if HS bit of Host Error Status Register (HOST_ERR) is equal to '00' and wait until EPn bit of Host DMA Data Request Register (HOST_DMA_DREQ) changes to '1'. Finish the IN token processing if HS bit is not equal to '00'.
280003. Read the received data if EPn bit of Host DMA Data Requet (HOST_DMA_DREQ) (n=1 or 2) changes to '1'.</description>
28001                <bitRange>[6:4]</bitRange>
28002                <access>read-write</access>
28003                <enumeratedValues>
28004                  <enumeratedValue>
28005                    <name>NONE</name>
28006                    <description>Sends no data.</description>
28007                    <value>0</value>
28008                  </enumeratedValue>
28009                  <enumeratedValue>
28010                    <name>SETUP</name>
28011                    <description>Sends SETUP token.</description>
28012                    <value>1</value>
28013                  </enumeratedValue>
28014                  <enumeratedValue>
28015                    <name>IN</name>
28016                    <description>Sends IN token.</description>
28017                    <value>2</value>
28018                  </enumeratedValue>
28019                  <enumeratedValue>
28020                    <name>OUT</name>
28021                    <description>Sends OUT token.</description>
28022                    <value>3</value>
28023                  </enumeratedValue>
28024                  <enumeratedValue>
28025                    <name>SOF</name>
28026                    <description>Sends SOF token.</description>
28027                    <value>4</value>
28028                  </enumeratedValue>
28029                  <enumeratedValue>
28030                    <name>ISO_IN</name>
28031                    <description>Sends Isochronous IN.</description>
28032                    <value>5</value>
28033                  </enumeratedValue>
28034                  <enumeratedValue>
28035                    <name>ISO_OUT</name>
28036                    <description>Sends Isochronous OUT.</description>
28037                    <value>6</value>
28038                  </enumeratedValue>
28039                  <enumeratedValue>
28040                    <name>RSV</name>
28041                    <description>N/A</description>
28042                    <value>7</value>
28043                  </enumeratedValue>
28044                </enumeratedValues>
28045              </field>
28046              <field>
28047                <name>TGGL</name>
28048                <description>This bit is used to set toggle data. Toggle data is sent depending on the setting of this bit. When receiving toggle data, received toggle data is compared with the toggle data of this bit to verify whether or not an error occurs.
28049'0' : DATA0
28050'1' : DATA1
28051Notes:
28052- This bit isn't reset to the default value even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.
28053- Set this bit when the TKNEN bit of the Host Token Endpoint Register (HOST_TOKEN) is '000'.</description>
28054                <bitRange>[8:8]</bitRange>
28055                <access>read-write</access>
28056              </field>
28057            </fields>
28058          </register>
28059          <register>
28060            <name>HOST_EP1_CTL</name>
28061            <description>Host Endpoint 1 Control Register</description>
28062            <addressOffset>0x400</addressOffset>
28063            <size>32</size>
28064            <access>read-write</access>
28065            <resetValue>0x8100</resetValue>
28066            <resetMask>0x9DFF</resetMask>
28067            <fields>
28068              <field>
28069                <name>PKS1</name>
28070                <description>This bit specifies the maximum size transferred by one packet. The configurable range is from 0x001 to 0x100.
28071- If automatic buffer transfer mode (DMAE='1') is used, Endpoint 0,1, or 2 cannot be used,</description>
28072                <bitRange>[8:0]</bitRange>
28073                <access>read-write</access>
28074              </field>
28075              <field>
28076                <name>NULLE</name>
28077                <description>When a data transfer request in OUT the direction is transmitted while automatic buffer transfer mode is set (DMAE = 1), this bit sets a mode that transfers 0-byte data automatically upon the detection of the last packet transfer.
28078'0' : Releases the NULL automatic transfer mode.
28079'1' : Sets the NULL automatic transfer mode.
28080Note :
28081- For data transfer in the IN direction or when automatic buffer transfer mode is not set, the NULL bit configuration does not affect communication.</description>
28082                <bitRange>[10:10]</bitRange>
28083                <access>read-write</access>
28084              </field>
28085              <field>
28086                <name>DMAE</name>
28087                <description>This bit sets a mode that uses DMA for writing or reading transfer data to/from send/receive buffer, and automatically transfers the send/receive data synchronized with an data request in the IN or OUT direction. Until the data size set in the DMA is reached, the data is transferred.
28088'0' : Releases the packet transfer mode.
28089'1' : Sets the packet transfer mode.
28090Note :
28091- The CPU must not access the send/receive buffer while the DMAE bit is set to '1'. For data transfer in the IN direction, set the DMA transfer size to the multiples of that set in PKS1 bits of the Host EP1 Control Register (HOST_EP1_CTL) and Host EP2 Control Register (HOST_EP2_CTR).</description>
28092                <bitRange>[11:11]</bitRange>
28093                <access>read-write</access>
28094              </field>
28095              <field>
28096                <name>DIR</name>
28097                <description>This bit specifies the transfer direction the Endpoint support.
28098'0' : IN Endpoint.
28099'1' : OUT Endpoint
28100Note:
28101- This bit must be changed when INI_ST bit of the Host Endpoint 1 Status Register (HOST_EP1_STATUS) is '1'.</description>
28102                <bitRange>[12:12]</bitRange>
28103                <access>read-write</access>
28104              </field>
28105              <field>
28106                <name>BFINI</name>
28107                <description>This bit initializes the send/receive buffer of transfer data. The BFINI bit is also automatically set by setting the RST bit of the HOST Control 1 Register (HOST_CTL1). If the RST bit was used for resetting, therefore, set the RST bit to '0' before clearing the BFINI bit.
28108'0' : Clears the initialization.
28109'1' : Initializes the send/receive buffer
28110Note :
28111- The EP1 buffer has a double-buffer configuration. The BFINI bit initialization initializes the double buffers concurrently and also initializes the EP1DRQ and EP1SPK bits.</description>
28112                <bitRange>[15:15]</bitRange>
28113                <access>read-write</access>
28114              </field>
28115            </fields>
28116          </register>
28117          <register>
28118            <name>HOST_EP1_STATUS</name>
28119            <description>Host Endpoint 1 Status Register</description>
28120            <addressOffset>0x404</addressOffset>
28121            <size>32</size>
28122            <access>read-only</access>
28123            <resetValue>0x60000</resetValue>
28124            <resetMask>0x70000</resetMask>
28125            <fields>
28126              <field>
28127                <name>SIZE1</name>
28128                <description>These bits indicate the number of data bytes written to the receive buffer when IN packet transfer of EP1 has finished.
28129The indication range is from 0x000 to 0x100.
28130Note :
28131- These bits are set to the data size transferred in the IN direction and written to the buffer. Therefore, a value read during transfer in the OUT direction has no effect.</description>
28132                <bitRange>[8:0]</bitRange>
28133                <access>read-only</access>
28134              </field>
28135              <field>
28136                <name>VAL_DATA</name>
28137                <description>This bit shows that there is valid data in the EP1 buffer.
28138'0' : Invalid data in the buffer
28139'1' : Valid data in the buffer</description>
28140                <bitRange>[16:16]</bitRange>
28141                <access>read-only</access>
28142              </field>
28143              <field>
28144                <name>INI_ST</name>
28145                <description>This bit shows that EP1 is initialized. If the init bit of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is set to '1' and EP1 is initialized, this bit is to '1'.
28146'0' : Not initiatialized
28147'1' : Initialized
28148Note:
28149- This bit isn't set to '0' or '1' immediately even if BFINI bit of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is set to '0' or '1'.  Read this bit to confirm the transition.</description>
28150                <bitRange>[17:17]</bitRange>
28151                <access>read-only</access>
28152              </field>
28153              <field>
28154                <name>RSVD_18</name>
28155                <description>N/A</description>
28156                <bitRange>[18:18]</bitRange>
28157                <access>read-only</access>
28158              </field>
28159            </fields>
28160          </register>
28161          <register>
28162            <name>HOST_EP1_RW1_DR</name>
28163            <description>Host Endpoint 1 Data 1-Byte Register</description>
28164            <addressOffset>0x408</addressOffset>
28165            <size>32</size>
28166            <access>read-write</access>
28167            <resetValue>0x0</resetValue>
28168            <resetMask>0xFF</resetMask>
28169            <fields>
28170              <field>
28171                <name>BFDT8</name>
28172                <description>Data Register for EP1 for 1-byte data</description>
28173                <bitRange>[7:0]</bitRange>
28174                <access>read-write</access>
28175              </field>
28176            </fields>
28177          </register>
28178          <register>
28179            <name>HOST_EP1_RW2_DR</name>
28180            <description>Host Endpoint 1 Data 2-Byte Register</description>
28181            <addressOffset>0x40C</addressOffset>
28182            <size>32</size>
28183            <access>read-write</access>
28184            <resetValue>0x0</resetValue>
28185            <resetMask>0xFFFF</resetMask>
28186            <fields>
28187              <field>
28188                <name>BFDT16</name>
28189                <description>Data Register for EP1 for 2-byte data</description>
28190                <bitRange>[15:0]</bitRange>
28191                <access>read-write</access>
28192              </field>
28193            </fields>
28194          </register>
28195          <register>
28196            <name>HOST_EP2_CTL</name>
28197            <description>Host Endpoint 2 Control Register</description>
28198            <addressOffset>0x500</addressOffset>
28199            <size>32</size>
28200            <access>read-write</access>
28201            <resetValue>0x8040</resetValue>
28202            <resetMask>0x9C7F</resetMask>
28203            <fields>
28204              <field>
28205                <name>PKS2</name>
28206                <description>This bit specifies the maximum size transferred by one packet. The configurable range is from 0x001 to 0x40.
28207- If automatic buffer transfer mode (DMAE='1') is used, this Endpoint must not set from 0 to 2.</description>
28208                <bitRange>[6:0]</bitRange>
28209                <access>read-write</access>
28210              </field>
28211              <field>
28212                <name>NULLE</name>
28213                <description>When a data transfer request in the OUT direction transmitted while packet transfer mode is set (DMAE = 1), this bit sets a mode that transfers 0-byte data automatically upon the detection of the last packet transfer.
28214'0' : Releases the NULL automatic transfer mode.
28215'1' : Sets the NULL automatic transfer mode.
28216Note :
28217- For data transfer in the IN direction or when automatic buffer transfer mode is not set, the NULL bit configuration does not affect communication.</description>
28218                <bitRange>[10:10]</bitRange>
28219                <access>read-write</access>
28220              </field>
28221              <field>
28222                <name>DMAE</name>
28223                <description>This bit sets a mode that uses DMA for writing or reading transfer data to/from send/receive buffer, and automatically transfers the send/receive data synchronized with an data request in the IN or OUT direction. Until the data size set in the DMA is reached, the data is transferred.
28224'0' : Releases the automatic buffer transfer mode.
28225'1' : Sets the automatic buffer transfer mode.
28226Note :
28227- The CPU must not access the send/receive buffer while the DMAE bit is set to '1'. For data transfer in the IN direction, set the DMA transfer size to the multiples of that set in PKS bits of the Host EP1 Control Register (HOST_EP1_CTL) and Host EP2 Control Register (HOST_EP2_CTR).</description>
28228                <bitRange>[11:11]</bitRange>
28229                <access>read-write</access>
28230              </field>
28231              <field>
28232                <name>DIR</name>
28233                <description>This bit specifies the transfer direction the Endpoint support.
28234'0' : IN Endpoint.
28235'1' : OUT Endpoint
28236Note:
28237- This bit must be changed when INI_ST bit of the Host Endpoint 2 Status Register (HOST_EP2_STATUS) is '1'.</description>
28238                <bitRange>[12:12]</bitRange>
28239                <access>read-write</access>
28240              </field>
28241              <field>
28242                <name>BFINI</name>
28243                <description>This bit initializes the send/receive buffer of transfer data. The BFINI bit is also automatically set by setting the RST bit of the HOST Control 1 Register (HOST_CTL1). If the RST bit was used for resetting, therefore, set the RST bit to '0' before clearing the BFINI bit.
28244'0' : Clears the initialization.
28245'1' : Initializes the send/receive buffer
28246Note :
28247- The EP2 buffer has a double-buffer configuration. The BFINI bit initialization initializes the double buffers concurrently and also initializes the EP2DRQ and EP2SPK bits.</description>
28248                <bitRange>[15:15]</bitRange>
28249                <access>read-write</access>
28250              </field>
28251            </fields>
28252          </register>
28253          <register>
28254            <name>HOST_EP2_STATUS</name>
28255            <description>Host Endpoint 2 Status Register</description>
28256            <addressOffset>0x504</addressOffset>
28257            <size>32</size>
28258            <access>read-only</access>
28259            <resetValue>0x60000</resetValue>
28260            <resetMask>0x70000</resetMask>
28261            <fields>
28262              <field>
28263                <name>SIZE2</name>
28264                <description>These bits indicate the number of data bytes written to the receive buffer when IN packet transfer of EP2 has finished.
28265The indication range is from 0x000 to 0x40.
28266Note :
28267- These bits are set to the data size transferred in the IN direction and written to the buffer. Therefore, a value read during transfer in the OUT direction has no effect.</description>
28268                <bitRange>[6:0]</bitRange>
28269                <access>read-only</access>
28270              </field>
28271              <field>
28272                <name>VAL_DATA</name>
28273                <description>This bit shows that there is valid data in the EP2 buffer.
28274'0' : Invalid data in the buffer
28275'1' : Valid data in the buffer</description>
28276                <bitRange>[16:16]</bitRange>
28277                <access>read-only</access>
28278              </field>
28279              <field>
28280                <name>INI_ST</name>
28281                <description>This bit shows that EP2 is initialized. If the BFINI bit of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is set to '1' and EP2 is initialized, this bit is to '1'.
28282'0' : Not Initialized
28283'1' : Initialized
28284Note:
28285- This bit isn't set to '0' or '1' immediately evne if BFINI bit of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is set to '0' or '1'.</description>
28286                <bitRange>[17:17]</bitRange>
28287                <access>read-only</access>
28288              </field>
28289              <field>
28290                <name>RSVD_18</name>
28291                <description>N/A</description>
28292                <bitRange>[18:18]</bitRange>
28293                <access>read-only</access>
28294              </field>
28295            </fields>
28296          </register>
28297          <register>
28298            <name>HOST_EP2_RW1_DR</name>
28299            <description>Host Endpoint 2 Data 1-Byte Register</description>
28300            <addressOffset>0x508</addressOffset>
28301            <size>32</size>
28302            <access>read-write</access>
28303            <resetValue>0x0</resetValue>
28304            <resetMask>0xFF</resetMask>
28305            <fields>
28306              <field>
28307                <name>BFDT8</name>
28308                <description>Data Register for EP2 for 1-byte data.</description>
28309                <bitRange>[7:0]</bitRange>
28310                <access>read-write</access>
28311              </field>
28312            </fields>
28313          </register>
28314          <register>
28315            <name>HOST_EP2_RW2_DR</name>
28316            <description>Host Endpoint 2 Data 2-Byte Register</description>
28317            <addressOffset>0x50C</addressOffset>
28318            <size>32</size>
28319            <access>read-write</access>
28320            <resetValue>0x0</resetValue>
28321            <resetMask>0xFFFF</resetMask>
28322            <fields>
28323              <field>
28324                <name>BFDT16</name>
28325                <description>Data Register for EP2 for 2 byte data.</description>
28326                <bitRange>[15:0]</bitRange>
28327                <access>read-write</access>
28328              </field>
28329            </fields>
28330          </register>
28331          <register>
28332            <name>HOST_LVL1_SEL</name>
28333            <description>Host Interrupt Level 1 Selection Register</description>
28334            <addressOffset>0x800</addressOffset>
28335            <size>32</size>
28336            <access>read-write</access>
28337            <resetValue>0x0</resetValue>
28338            <resetMask>0xFFFF</resetMask>
28339            <fields>
28340              <field>
28341                <name>SOFIRQ_SEL</name>
28342                <description>These bits assign SOFIRQ interrupt flag to selected interrupt signals.</description>
28343                <bitRange>[1:0]</bitRange>
28344                <access>read-write</access>
28345                <enumeratedValues>
28346                  <enumeratedValue>
28347                    <name>HI</name>
28348                    <description>High priority interrupt</description>
28349                    <value>0</value>
28350                  </enumeratedValue>
28351                  <enumeratedValue>
28352                    <name>MED</name>
28353                    <description>Medium priority interrupt</description>
28354                    <value>1</value>
28355                  </enumeratedValue>
28356                  <enumeratedValue>
28357                    <name>LO</name>
28358                    <description>Low priority interrupt</description>
28359                    <value>2</value>
28360                  </enumeratedValue>
28361                  <enumeratedValue>
28362                    <name>RSVD</name>
28363                    <description>N/A</description>
28364                    <value>3</value>
28365                  </enumeratedValue>
28366                </enumeratedValues>
28367              </field>
28368              <field>
28369                <name>DIRQ_SEL</name>
28370                <description>These bits assign DIRQ interrupt flag to selected interrupt signals.</description>
28371                <bitRange>[3:2]</bitRange>
28372                <access>read-write</access>
28373              </field>
28374              <field>
28375                <name>CNNIRQ_SEL</name>
28376                <description>These bits assign CNNIRQ interrupt flag to selected interrupt signals.</description>
28377                <bitRange>[5:4]</bitRange>
28378                <access>read-write</access>
28379              </field>
28380              <field>
28381                <name>CMPIRQ_SEL</name>
28382                <description>These bits assign URIRQ interrupt flag to selected interrupt signals.</description>
28383                <bitRange>[7:6]</bitRange>
28384                <access>read-write</access>
28385              </field>
28386              <field>
28387                <name>URIRQ_SEL</name>
28388                <description>These bits assign URIRQ interrupt flag to selected interrupt signals.</description>
28389                <bitRange>[9:8]</bitRange>
28390                <access>read-write</access>
28391              </field>
28392              <field>
28393                <name>RWKIRQ_SEL</name>
28394                <description>These bits assign RWKIRQ interrupt flag to selected interrupt signals.</description>
28395                <bitRange>[11:10]</bitRange>
28396                <access>read-write</access>
28397              </field>
28398              <field>
28399                <name>RSVD_13_12</name>
28400                <description>N/A</description>
28401                <bitRange>[13:12]</bitRange>
28402                <access>read-write</access>
28403              </field>
28404              <field>
28405                <name>TCAN_SEL</name>
28406                <description>These bits assign TCAN interrupt flag to selected interrupt signals.</description>
28407                <bitRange>[15:14]</bitRange>
28408                <access>read-write</access>
28409              </field>
28410            </fields>
28411          </register>
28412          <register>
28413            <name>HOST_LVL2_SEL</name>
28414            <description>Host Interrupt Level 2 Selection Register</description>
28415            <addressOffset>0x804</addressOffset>
28416            <size>32</size>
28417            <access>read-write</access>
28418            <resetValue>0x0</resetValue>
28419            <resetMask>0xFF0</resetMask>
28420            <fields>
28421              <field>
28422                <name>EP1_DRQ_SEL</name>
28423                <description>These bits assign EP1_DRQ interrupt flag to selected interrupt signals.</description>
28424                <bitRange>[5:4]</bitRange>
28425                <access>read-write</access>
28426                <enumeratedValues>
28427                  <enumeratedValue>
28428                    <name>HI</name>
28429                    <description>High priority interrupt</description>
28430                    <value>0</value>
28431                  </enumeratedValue>
28432                  <enumeratedValue>
28433                    <name>MED</name>
28434                    <description>Medium priority interrupt</description>
28435                    <value>1</value>
28436                  </enumeratedValue>
28437                  <enumeratedValue>
28438                    <name>LO</name>
28439                    <description>Low priority interrupt</description>
28440                    <value>2</value>
28441                  </enumeratedValue>
28442                  <enumeratedValue>
28443                    <name>RSVD</name>
28444                    <description>N/A</description>
28445                    <value>3</value>
28446                  </enumeratedValue>
28447                </enumeratedValues>
28448              </field>
28449              <field>
28450                <name>EP1_SPK_SEL</name>
28451                <description>These bits assign EP1_SPK interrupt flag to selected interrupt signals.</description>
28452                <bitRange>[7:6]</bitRange>
28453                <access>read-write</access>
28454              </field>
28455              <field>
28456                <name>EP2_DRQ_SEL</name>
28457                <description>These bits assign EP2_DRQ interrupt flag to selected interrupt signals.</description>
28458                <bitRange>[9:8]</bitRange>
28459                <access>read-write</access>
28460              </field>
28461              <field>
28462                <name>EP2_SPK_SEL</name>
28463                <description>These bits assign EP2_SPK interrupt flag to selected interrupt signals.</description>
28464                <bitRange>[11:10]</bitRange>
28465                <access>read-write</access>
28466              </field>
28467            </fields>
28468          </register>
28469          <register>
28470            <name>INTR_USBHOST_CAUSE_HI</name>
28471            <description>Interrupt USB Host Cause High Register</description>
28472            <addressOffset>0x900</addressOffset>
28473            <size>32</size>
28474            <access>read-only</access>
28475            <resetValue>0x0</resetValue>
28476            <resetMask>0xFF</resetMask>
28477            <fields>
28478              <field>
28479                <name>SOFIRQ_INT</name>
28480                <description>SOFIRQ interrupt</description>
28481                <bitRange>[0:0]</bitRange>
28482                <access>read-only</access>
28483              </field>
28484              <field>
28485                <name>DIRQ_INT</name>
28486                <description>DIRQ interrupt</description>
28487                <bitRange>[1:1]</bitRange>
28488                <access>read-only</access>
28489              </field>
28490              <field>
28491                <name>CNNIRQ_INT</name>
28492                <description>CNNIRQ interrupt</description>
28493                <bitRange>[2:2]</bitRange>
28494                <access>read-only</access>
28495              </field>
28496              <field>
28497                <name>CMPIRQ_INT</name>
28498                <description>CMPIRQ interrupt</description>
28499                <bitRange>[3:3]</bitRange>
28500                <access>read-only</access>
28501              </field>
28502              <field>
28503                <name>URIRQ_INT</name>
28504                <description>URIRQ interrupt</description>
28505                <bitRange>[4:4]</bitRange>
28506                <access>read-only</access>
28507              </field>
28508              <field>
28509                <name>RWKIRQ_INT</name>
28510                <description>RWKIRQ interrupt</description>
28511                <bitRange>[5:5]</bitRange>
28512                <access>read-only</access>
28513              </field>
28514              <field>
28515                <name>RSVD_6</name>
28516                <description>N/A</description>
28517                <bitRange>[6:6]</bitRange>
28518                <access>read-only</access>
28519              </field>
28520              <field>
28521                <name>TCAN_INT</name>
28522                <description>TCAN interrupt</description>
28523                <bitRange>[7:7]</bitRange>
28524                <access>read-only</access>
28525              </field>
28526            </fields>
28527          </register>
28528          <register>
28529            <name>INTR_USBHOST_CAUSE_MED</name>
28530            <description>Interrupt USB Host Cause Medium Register</description>
28531            <addressOffset>0x904</addressOffset>
28532            <size>32</size>
28533            <access>read-only</access>
28534            <resetValue>0x0</resetValue>
28535            <resetMask>0xFF</resetMask>
28536            <fields>
28537              <field>
28538                <name>SOFIRQ_INT</name>
28539                <description>SOFIRQ interrupt</description>
28540                <bitRange>[0:0]</bitRange>
28541                <access>read-only</access>
28542              </field>
28543              <field>
28544                <name>DIRQ_INT</name>
28545                <description>DIRQ interrupt</description>
28546                <bitRange>[1:1]</bitRange>
28547                <access>read-only</access>
28548              </field>
28549              <field>
28550                <name>CNNIRQ_INT</name>
28551                <description>CNNIRQ interrupt</description>
28552                <bitRange>[2:2]</bitRange>
28553                <access>read-only</access>
28554              </field>
28555              <field>
28556                <name>CMPIRQ_INT</name>
28557                <description>CMPIRQ interrupt</description>
28558                <bitRange>[3:3]</bitRange>
28559                <access>read-only</access>
28560              </field>
28561              <field>
28562                <name>URIRQ_INT</name>
28563                <description>URIRQ interrupt</description>
28564                <bitRange>[4:4]</bitRange>
28565                <access>read-only</access>
28566              </field>
28567              <field>
28568                <name>RWKIRQ_INT</name>
28569                <description>RWKIRQ interrupt</description>
28570                <bitRange>[5:5]</bitRange>
28571                <access>read-only</access>
28572              </field>
28573              <field>
28574                <name>RSVD_6</name>
28575                <description>N/A</description>
28576                <bitRange>[6:6]</bitRange>
28577                <access>read-only</access>
28578              </field>
28579              <field>
28580                <name>TCAN_INT</name>
28581                <description>TCAN interrupt</description>
28582                <bitRange>[7:7]</bitRange>
28583                <access>read-only</access>
28584              </field>
28585            </fields>
28586          </register>
28587          <register>
28588            <name>INTR_USBHOST_CAUSE_LO</name>
28589            <description>Interrupt USB Host Cause Low Register</description>
28590            <addressOffset>0x908</addressOffset>
28591            <size>32</size>
28592            <access>read-only</access>
28593            <resetValue>0x0</resetValue>
28594            <resetMask>0xFF</resetMask>
28595            <fields>
28596              <field>
28597                <name>SOFIRQ_INT</name>
28598                <description>SOFIRQ interrupt</description>
28599                <bitRange>[0:0]</bitRange>
28600                <access>read-only</access>
28601              </field>
28602              <field>
28603                <name>DIRQ_INT</name>
28604                <description>DIRQ interrupt</description>
28605                <bitRange>[1:1]</bitRange>
28606                <access>read-only</access>
28607              </field>
28608              <field>
28609                <name>CNNIRQ_INT</name>
28610                <description>CNNIRQ interrupt</description>
28611                <bitRange>[2:2]</bitRange>
28612                <access>read-only</access>
28613              </field>
28614              <field>
28615                <name>CMPIRQ_INT</name>
28616                <description>CMPIRQ interrupt</description>
28617                <bitRange>[3:3]</bitRange>
28618                <access>read-only</access>
28619              </field>
28620              <field>
28621                <name>URIRQ_INT</name>
28622                <description>URIRQ interrupt</description>
28623                <bitRange>[4:4]</bitRange>
28624                <access>read-only</access>
28625              </field>
28626              <field>
28627                <name>RWKIRQ_INT</name>
28628                <description>RWKIRQ interrupt</description>
28629                <bitRange>[5:5]</bitRange>
28630                <access>read-only</access>
28631              </field>
28632              <field>
28633                <name>RSVD_6</name>
28634                <description>N/A</description>
28635                <bitRange>[6:6]</bitRange>
28636                <access>read-only</access>
28637              </field>
28638              <field>
28639                <name>TCAN_INT</name>
28640                <description>TCAN interrupt</description>
28641                <bitRange>[7:7]</bitRange>
28642                <access>read-only</access>
28643              </field>
28644            </fields>
28645          </register>
28646          <register>
28647            <name>INTR_HOST_EP_CAUSE_HI</name>
28648            <description>Interrupt USB Host Endpoint Cause High Register</description>
28649            <addressOffset>0x920</addressOffset>
28650            <size>32</size>
28651            <access>read-only</access>
28652            <resetValue>0x0</resetValue>
28653            <resetMask>0x3C</resetMask>
28654            <fields>
28655              <field>
28656                <name>EP1DRQ_INT</name>
28657                <description>EP1DRQ interrupt</description>
28658                <bitRange>[2:2]</bitRange>
28659                <access>read-only</access>
28660              </field>
28661              <field>
28662                <name>EP1SPK_INT</name>
28663                <description>EP1SPK interrupt</description>
28664                <bitRange>[3:3]</bitRange>
28665                <access>read-only</access>
28666              </field>
28667              <field>
28668                <name>EP2DRQ_INT</name>
28669                <description>EP2DRQ interrupt</description>
28670                <bitRange>[4:4]</bitRange>
28671                <access>read-only</access>
28672              </field>
28673              <field>
28674                <name>EP2SPK_INT</name>
28675                <description>EP2SPK interrupt</description>
28676                <bitRange>[5:5]</bitRange>
28677                <access>read-only</access>
28678              </field>
28679            </fields>
28680          </register>
28681          <register>
28682            <name>INTR_HOST_EP_CAUSE_MED</name>
28683            <description>Interrupt USB Host Endpoint Cause Medium Register</description>
28684            <addressOffset>0x924</addressOffset>
28685            <size>32</size>
28686            <access>read-only</access>
28687            <resetValue>0x0</resetValue>
28688            <resetMask>0x3C</resetMask>
28689            <fields>
28690              <field>
28691                <name>EP1DRQ_INT</name>
28692                <description>EP1DRQ interrupt</description>
28693                <bitRange>[2:2]</bitRange>
28694                <access>read-only</access>
28695              </field>
28696              <field>
28697                <name>EP1SPK_INT</name>
28698                <description>EP1SPK interrupt</description>
28699                <bitRange>[3:3]</bitRange>
28700                <access>read-only</access>
28701              </field>
28702              <field>
28703                <name>EP2DRQ_INT</name>
28704                <description>EP2DRQ interrupt</description>
28705                <bitRange>[4:4]</bitRange>
28706                <access>read-only</access>
28707              </field>
28708              <field>
28709                <name>EP2SPK_INT</name>
28710                <description>EP2SPK interrupt</description>
28711                <bitRange>[5:5]</bitRange>
28712                <access>read-only</access>
28713              </field>
28714            </fields>
28715          </register>
28716          <register>
28717            <name>INTR_HOST_EP_CAUSE_LO</name>
28718            <description>Interrupt USB Host Endpoint Cause Low Register</description>
28719            <addressOffset>0x928</addressOffset>
28720            <size>32</size>
28721            <access>read-only</access>
28722            <resetValue>0x0</resetValue>
28723            <resetMask>0x3C</resetMask>
28724            <fields>
28725              <field>
28726                <name>EP1DRQ_INT</name>
28727                <description>EP1DRQ interrupt</description>
28728                <bitRange>[2:2]</bitRange>
28729                <access>read-only</access>
28730              </field>
28731              <field>
28732                <name>EP1SPK_INT</name>
28733                <description>EP1SPK interrupt</description>
28734                <bitRange>[3:3]</bitRange>
28735                <access>read-only</access>
28736              </field>
28737              <field>
28738                <name>EP2DRQ_INT</name>
28739                <description>EP2DRQ interrupt</description>
28740                <bitRange>[4:4]</bitRange>
28741                <access>read-only</access>
28742              </field>
28743              <field>
28744                <name>EP2SPK_INT</name>
28745                <description>EP2SPK interrupt</description>
28746                <bitRange>[5:5]</bitRange>
28747                <access>read-only</access>
28748              </field>
28749            </fields>
28750          </register>
28751          <register>
28752            <name>INTR_USBHOST</name>
28753            <description>Interrupt USB Host Register</description>
28754            <addressOffset>0x940</addressOffset>
28755            <size>32</size>
28756            <access>read-write</access>
28757            <resetValue>0x0</resetValue>
28758            <resetMask>0xFF</resetMask>
28759            <fields>
28760              <field>
28761                <name>SOFIRQ</name>
28762                <description>If this bit is set to '1', it means that SOF token sending is started. When this bit is '0', it has no meaning. Write '1' to clear, a write of '0' is ignored.
28763'0' : Does not issue an interrupt request by starting a SOF token.
28764'1' : Issues an interrupt request by starting a SOF token.
28765Note :
28766- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
28767                <bitRange>[0:0]</bitRange>
28768                <access>read-write</access>
28769              </field>
28770              <field>
28771                <name>DIRQ</name>
28772                <description>If this bit is set to '1', it means that a device disconnection is detected. When this bit is '0', it has no meaning. Write '1' to clear, a write of '0' is ignored.
28773'0' : Issues no interrupt request by detecting a device disconnection.
28774'1' : Issues an interrupt request by detecting a device disconnection.
28775Note :
28776- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
28777                <bitRange>[1:1]</bitRange>
28778                <access>read-write</access>
28779              </field>
28780              <field>
28781                <name>CNNIRQ</name>
28782                <description>If this bit is set to '1', it means that a device connection is detected. When this bit is '0', it has no meaning. Write '1' to clear, a write of '0' is ignored.
28783'0' : Issues no interrupt request by detecting a device connection.
28784'1' : Issues an interrupt request by detecting a device connection.
28785Note :
28786- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
28787                <bitRange>[2:2]</bitRange>
28788                <access>read-write</access>
28789              </field>
28790              <field>
28791                <name>CMPIRQ</name>
28792                <description>If this bit is set to '1', it means that a token is completed. When this bit is '0', it has no meaning. Write '1' to clear, a write of '0' is ignored.
28793'0' : Issues no interrupt request by token completion.
28794'1' : Issues an interrupt request by token completion.
28795Note :
28796- This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.
28797- This bit is not set to '1' even if the TCAN bit of the Interrupt USBHost Register (INTR_USBHOST) changes to '1'.
28798- Take the following steps when this bit is set to '1' by finishing IN token or Isochronous IN token.
287991. Read HS bit of Host Error Status Register (HOST_ERR), then set CMPIRQ bit to '0'.
288002. Set EPn bit of Host DMA Enable Register (HOST_DMA_ENBL) (n=1 or 2) to '1' if HS bit of Host Error Status Register (HOST_ERR) is equal to '00' and wait until EPn bit of Host DMA Data Request Register (HOST_DMA_DREQ) changes to '1'. Finish the IN token processing if HS bit is not equal to '00'.
288013. Read the received data if EPn bit of Host DMA Data Requet (HOST_DMA_DREQ) (n=1 or 2) changes to '1'.</description>
28802                <bitRange>[3:3]</bitRange>
28803                <access>read-write</access>
28804              </field>
28805              <field>
28806                <name>URIRQ</name>
28807                <description>If this bit is set to '1', it means that USB bus resetting is ended. When this bit is '0', it has no meaning. If this bit is written with '1', it is set to '0'. However, if this bit is written with '0', its value is ignored.
28808'0' : Issues no interrupt request by USB bus resetting.
28809'1' : Issues an interrupt request by USB bus resetting.
28810Note :
28811- This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
28812                <bitRange>[4:4]</bitRange>
28813                <access>read-write</access>
28814              </field>
28815              <field>
28816                <name>RWKIRQ</name>
28817                <description>If this bit is set to '1', it means that remote Wake-up is ended. When this bit is '0', it has no meaning. Write '1' to clear, a write of '0' is ignored.
28818'0' : Issues no interrupt request by restart.
28819'1' : Issues an interrupt request by restart.
28820Note :
28821- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
28822                <bitRange>[5:5]</bitRange>
28823                <access>read-write</access>
28824              </field>
28825              <field>
28826                <name>RSVD_6</name>
28827                <description>N/A</description>
28828                <bitRange>[6:6]</bitRange>
28829                <access>read-write</access>
28830              </field>
28831              <field>
28832                <name>TCAN</name>
28833                <description>If this bit is set to '1', it means that token sending is canceled based on the setting of the CANCEL bit of Host Control 2 Register (HOST_CTL2). When this bit is '0', it means that token sending is not canceled. Write '1' to clear, a write of '0' is ignored.
28834'0' : Does not cancel token sending.
28835'1' : Cancels token sending.
28836Note :
28837- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
28838                <bitRange>[7:7]</bitRange>
28839                <access>read-write</access>
28840              </field>
28841            </fields>
28842          </register>
28843          <register>
28844            <name>INTR_USBHOST_SET</name>
28845            <description>Interrupt USB Host Set Register</description>
28846            <addressOffset>0x944</addressOffset>
28847            <size>32</size>
28848            <access>read-write</access>
28849            <resetValue>0x0</resetValue>
28850            <resetMask>0xFF</resetMask>
28851            <fields>
28852              <field>
28853                <name>SOFIRQS</name>
28854                <description>This bit sets SOFIRQ bit. If this bit is written to '1', SOFIRQ is set to '1'. However, if this bit is written with '0', its value is ignored.</description>
28855                <bitRange>[0:0]</bitRange>
28856                <access>read-write</access>
28857              </field>
28858              <field>
28859                <name>DIRQS</name>
28860                <description>This bit sets DIRQ bit. If this bit is written to '1', DIRQ is set to '1'. However, if this bit is written with '0', its value is ignored.</description>
28861                <bitRange>[1:1]</bitRange>
28862                <access>read-write</access>
28863              </field>
28864              <field>
28865                <name>CNNIRQS</name>
28866                <description>This bit sets CNNIRQ bit. If this bit is written to '1', CNNIRQ is set to '1'. However, if this bit is written with '0', its value is ignored.</description>
28867                <bitRange>[2:2]</bitRange>
28868                <access>read-write</access>
28869              </field>
28870              <field>
28871                <name>CMPIRQS</name>
28872                <description>This bit sets CMPIRQ bit. If this bit is written to '1', CMPIRQ is set to '1'. However, if this bit is written with '0', its value is ignored.</description>
28873                <bitRange>[3:3]</bitRange>
28874                <access>read-write</access>
28875              </field>
28876              <field>
28877                <name>URIRQS</name>
28878                <description>This bit sets URIRQ bit. If this bit is written to '1', URIRQ is set to '1'. However, if this bit is written with '0', its value is ignored.</description>
28879                <bitRange>[4:4]</bitRange>
28880                <access>read-write</access>
28881              </field>
28882              <field>
28883                <name>RWKIRQS</name>
28884                <description>This bit sets RWKIRQ bit. If this bit is written to '1', RWKIRQ is set to '1'. However, if this bit is written with '0', its value is ignored.</description>
28885                <bitRange>[5:5]</bitRange>
28886                <access>read-write</access>
28887              </field>
28888              <field>
28889                <name>RSVD_6</name>
28890                <description>N/A</description>
28891                <bitRange>[6:6]</bitRange>
28892                <access>read-write</access>
28893              </field>
28894              <field>
28895                <name>TCANS</name>
28896                <description>This bit sets TCAN bit. If this bit is written to '1', TCAN is set to '1'. However, if this bit is written with '0', its value is ignored.</description>
28897                <bitRange>[7:7]</bitRange>
28898                <access>read-write</access>
28899              </field>
28900            </fields>
28901          </register>
28902          <register>
28903            <name>INTR_USBHOST_MASK</name>
28904            <description>Interrupt USB Host Mask Register</description>
28905            <addressOffset>0x948</addressOffset>
28906            <size>32</size>
28907            <access>read-write</access>
28908            <resetValue>0x0</resetValue>
28909            <resetMask>0xFF</resetMask>
28910            <fields>
28911              <field>
28912                <name>SOFIRQM</name>
28913                <description>This bit masks the interrupt by SOF flag.
28914'0' : Disables
28915'1' : Enables</description>
28916                <bitRange>[0:0]</bitRange>
28917                <access>read-write</access>
28918              </field>
28919              <field>
28920                <name>DIRQM</name>
28921                <description>This bit masks the interrupt by DIRQ flag.
28922'0' : Disables
28923'1' : Enables</description>
28924                <bitRange>[1:1]</bitRange>
28925                <access>read-write</access>
28926              </field>
28927              <field>
28928                <name>CNNIRQM</name>
28929                <description>This bit masks the interrupt by CNNIRQ flag.
28930'0' : Disables
28931'1' : Enables</description>
28932                <bitRange>[2:2]</bitRange>
28933                <access>read-write</access>
28934              </field>
28935              <field>
28936                <name>CMPIRQM</name>
28937                <description>This bit masks the interrupt by CMPIRQ flag.
28938'0' : Disables
28939'1' : Enables</description>
28940                <bitRange>[3:3]</bitRange>
28941                <access>read-write</access>
28942              </field>
28943              <field>
28944                <name>URIRQM</name>
28945                <description>This bit masks the interrupt by URIRQ flag.
28946'0' : Disables
28947'1' : Enables</description>
28948                <bitRange>[4:4]</bitRange>
28949                <access>read-write</access>
28950              </field>
28951              <field>
28952                <name>RWKIRQM</name>
28953                <description>This bit masks the interrupt by RWKIRQ flag.
28954'0' : Disables
28955'1' : Enables</description>
28956                <bitRange>[5:5]</bitRange>
28957                <access>read-write</access>
28958              </field>
28959              <field>
28960                <name>RSVD_6</name>
28961                <description>N/A</description>
28962                <bitRange>[6:6]</bitRange>
28963                <access>read-write</access>
28964              </field>
28965              <field>
28966                <name>TCANM</name>
28967                <description>This bit masks the interrupt by TCAN flag.
28968'0' : Disables
28969'1' : Enables</description>
28970                <bitRange>[7:7]</bitRange>
28971                <access>read-write</access>
28972              </field>
28973            </fields>
28974          </register>
28975          <register>
28976            <name>INTR_USBHOST_MASKED</name>
28977            <description>Interrupt USB Host Masked Register</description>
28978            <addressOffset>0x94C</addressOffset>
28979            <size>32</size>
28980            <access>read-only</access>
28981            <resetValue>0x0</resetValue>
28982            <resetMask>0xFF</resetMask>
28983            <fields>
28984              <field>
28985                <name>SOFIRQED</name>
28986                <description>This bit indicates the interrupt by SOF flag.
28987'0' : Doesn't request the interrupt by SOF
28988'1' : Request the interrupt by SOF</description>
28989                <bitRange>[0:0]</bitRange>
28990                <access>read-only</access>
28991              </field>
28992              <field>
28993                <name>DIRQED</name>
28994                <description>This bit indicates the interrupt by DIRQ flag.
28995'0' : Doesn't request the interrupt by DIRQ
28996'1' : Request the interrupt by DIRQ</description>
28997                <bitRange>[1:1]</bitRange>
28998                <access>read-only</access>
28999              </field>
29000              <field>
29001                <name>CNNIRQED</name>
29002                <description>This bit indicates the interrupt by CNNIRQ flag.
29003'0' : Doesn't request the interrupt by CNNIRQ
29004'1' : Request the interrupt by CNNIRQ</description>
29005                <bitRange>[2:2]</bitRange>
29006                <access>read-only</access>
29007              </field>
29008              <field>
29009                <name>CMPIRQED</name>
29010                <description>This bit indicates the interrupt by CMPIRQ flag.
29011'0' : Doesn't request the interrupt by CMPIRQ
29012'1' : Request the interrupt by CMPIRQ</description>
29013                <bitRange>[3:3]</bitRange>
29014                <access>read-only</access>
29015              </field>
29016              <field>
29017                <name>URIRQED</name>
29018                <description>This bit indicates the interrupt by URIRQ flag.
29019'0' : Doesn't request the interrupt by URIRQ
29020'1' : Request the interrupt by URIRQ</description>
29021                <bitRange>[4:4]</bitRange>
29022                <access>read-only</access>
29023              </field>
29024              <field>
29025                <name>RWKIRQED</name>
29026                <description>This bit indicates the interrupt by RWKIRQ flag.
29027'0' : Doesn't request the interrupt by RWKIRQ
29028'1' : Request the interrupt by RWKIRQ</description>
29029                <bitRange>[5:5]</bitRange>
29030                <access>read-only</access>
29031              </field>
29032              <field>
29033                <name>RSVD_6</name>
29034                <description>N/A</description>
29035                <bitRange>[6:6]</bitRange>
29036                <access>read-only</access>
29037              </field>
29038              <field>
29039                <name>TCANED</name>
29040                <description>This bit indicates the interrupt by TCAN flag.
29041'0' : Doesn't request the interrupt by TCAN
29042'1' : Request the interrupt by TCAN</description>
29043                <bitRange>[7:7]</bitRange>
29044                <access>read-only</access>
29045              </field>
29046            </fields>
29047          </register>
29048          <register>
29049            <name>INTR_HOST_EP</name>
29050            <description>Interrupt USB Host Endpoint Register</description>
29051            <addressOffset>0xA00</addressOffset>
29052            <size>32</size>
29053            <access>read-write</access>
29054            <resetValue>0x0</resetValue>
29055            <resetMask>0x3C</resetMask>
29056            <fields>
29057              <field>
29058                <name>EP1DRQ</name>
29059                <description>This bit indicates that the EP1 packet transfer has normally ended, and processing of the data is required. The DRQ bit is an interrupt cause, and writing '0' is ignored. Clear the DRQ bit by writing '1'.
29060'0' : Clears the interrupt cause
29061'1' : Packet transfer normally ended
29062Note :
29063- If automatic buffer transfer mode (DMAE = '1') is not used, '1' must be written to the DRQ bit after data has been written or read to/from the send/receive buffer. Switch the access buffers once the DRQ bit is cleared. That DRQ = '0' may not be read after the DRQ bit is cleared. If the transfer direction is set to OUT, and the DRQ bit is cleared without writing buffer data while the DRQ bit is '1', it implies that 0-byte data is set. If DIR of the Host Endpoint 1 Control Register (HOST_EP1_CTL)  is set to '1' at initial settings, the DRQ bit of corresponding Endpoint is set at the same time. Also while the DRQ bit is not set, '1' must not be written.</description>
29064                <bitRange>[2:2]</bitRange>
29065                <access>read-write</access>
29066              </field>
29067              <field>
29068                <name>EP1SPK</name>
29069                <description>This bit indicates that the data size transferred from the host does not satisfy the maximum packet size (including 0-byte) set by PKS in the Host Endpoint 1 Control Register (HOST_EP1_CTL) when the data has been received successfully. This bit is an interrupt cause, and writing '0' is ignored. Clear it by writing '1'.
29070'0' : Received data size satisfies the maximum packet size
29071'1' : Received data size does not satisfy the maximum packet size
29072Note :
29073- The EP1SPK bit is not set during data transfer in the OUT direction.</description>
29074                <bitRange>[3:3]</bitRange>
29075                <access>read-write</access>
29076              </field>
29077              <field>
29078                <name>EP2DRQ</name>
29079                <description>This bit indicates that the EP2 packet transfer has normally ended, and processing of the data is required. The DRQ bit is an interrupt cause, and writing '0' is ignored. Clear the DRQ bit by writing '1'.
29080'0' : Clears the interrupt cause
29081'1' : Packet transfer normally ended
29082Note :
29083- If packet transfer mode (DMAE = '1') is not used, '1' must be written to the DRQ bit after data has been written or read to/from the send/receive buffer. Switch the access buffers once the DRQ bit is cleared. That DRQ = '0' may not be read after the DRQ bit is cleared. If the transfer direction is set to OUT, and the DRQ bit is cleared without writing buffer data while the DRQ bit is '1', it implies that 0-byte data is set. If DIR of the Host Endpoint 2 Control Register (HOST_EP2_CTL)  is set to '1' at initial settings, the DRQ bit of corresponding Endpoint is set at the same time. Also while the DRQ bit is not set, '1' must not be written.</description>
29084                <bitRange>[4:4]</bitRange>
29085                <access>read-write</access>
29086              </field>
29087              <field>
29088                <name>EP2SPK</name>
29089                <description>This bit indicates that the data size transferred from the host does not satisfy the maximum packet size (including 0-byte) set by PKS1 in the Host Endpoint 2 Control Register (HOST_EP2_CTL) when the data has been received successfully. This bit is an interrupt cause, and writing '0' is ignored. Clear it by writing '1'.
29090'0' : Received data size satisfies the maximum packet size
29091'1' : Received data size does not satisfy the maximum packet size
29092Note :
29093- The SPK bit is not set during data transfer in the OUT direction.</description>
29094                <bitRange>[5:5]</bitRange>
29095                <access>read-write</access>
29096              </field>
29097            </fields>
29098          </register>
29099          <register>
29100            <name>INTR_HOST_EP_SET</name>
29101            <description>Interrupt USB Host Endpoint Set Register</description>
29102            <addressOffset>0xA04</addressOffset>
29103            <size>32</size>
29104            <access>read-write</access>
29105            <resetValue>0x0</resetValue>
29106            <resetMask>0x3C</resetMask>
29107            <fields>
29108              <field>
29109                <name>EP1DRQS</name>
29110                <description>This bit sets EP1DRQ bit. If this bit is written to '1', EP1DRQ is set to '1'. However, if this bit is written with '0', its value is ignored.
29111Note:
29112If BFINI bit of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is '1', EP1DRQ can't be set to '1'.</description>
29113                <bitRange>[2:2]</bitRange>
29114                <access>read-write</access>
29115              </field>
29116              <field>
29117                <name>EP1SPKS</name>
29118                <description>This bit sets EP1SPK bit. If this bit is written to '1', EP1SPK is set to '1'. However, if this bit is written with '0', its value is ignored.
29119Note:
29120If BFINI bit of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is '1', EP1SPK can't be set to '1'.</description>
29121                <bitRange>[3:3]</bitRange>
29122                <access>read-write</access>
29123              </field>
29124              <field>
29125                <name>EP2DRQS</name>
29126                <description>This bit sets EP2DRQ bit. If this bit is written to '1', EP2DRQ is set to '1'. However, if this bit is written with '0', its value is ignored.
29127Note:
29128If BFINI bit of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is '1', EP2DRQ can't be set to '1'.</description>
29129                <bitRange>[4:4]</bitRange>
29130                <access>read-write</access>
29131              </field>
29132              <field>
29133                <name>EP2SPKS</name>
29134                <description>This bit sets EP2SPK bit. If this bit is written to '1', EP2SPK is set to '1'. However, if this bit is written with '0', its value is ignored.
29135Note:
29136If BFINI bit of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is '1', EP2SPK can't be set to '1'.</description>
29137                <bitRange>[5:5]</bitRange>
29138                <access>read-write</access>
29139              </field>
29140            </fields>
29141          </register>
29142          <register>
29143            <name>INTR_HOST_EP_MASK</name>
29144            <description>Interrupt USB Host Endpoint Mask Register</description>
29145            <addressOffset>0xA08</addressOffset>
29146            <size>32</size>
29147            <access>read-write</access>
29148            <resetValue>0x0</resetValue>
29149            <resetMask>0x3C</resetMask>
29150            <fields>
29151              <field>
29152                <name>EP1DRQM</name>
29153                <description>This bit masks the interrupt by EP1DRQ flag.
29154'0' : Disables
29155'1' : Enables</description>
29156                <bitRange>[2:2]</bitRange>
29157                <access>read-write</access>
29158              </field>
29159              <field>
29160                <name>EP1SPKM</name>
29161                <description>This bit masks the interrupt by EP1SPK flag.
29162'0' : Disables
29163'1' : Enables</description>
29164                <bitRange>[3:3]</bitRange>
29165                <access>read-write</access>
29166              </field>
29167              <field>
29168                <name>EP2DRQM</name>
29169                <description>This bit masks the interrupt by EP2DRQ flag.
29170'0' : Disables
29171'1' : Enables</description>
29172                <bitRange>[4:4]</bitRange>
29173                <access>read-write</access>
29174              </field>
29175              <field>
29176                <name>EP2SPKM</name>
29177                <description>This bit masks the interrupt by EP2SPK flag.
29178'0' : Disables
29179'1' : Enables</description>
29180                <bitRange>[5:5]</bitRange>
29181                <access>read-write</access>
29182              </field>
29183            </fields>
29184          </register>
29185          <register>
29186            <name>INTR_HOST_EP_MASKED</name>
29187            <description>Interrupt USB Host Endpoint Masked Register</description>
29188            <addressOffset>0xA0C</addressOffset>
29189            <size>32</size>
29190            <access>read-only</access>
29191            <resetValue>0x0</resetValue>
29192            <resetMask>0x3C</resetMask>
29193            <fields>
29194              <field>
29195                <name>EP1DRQED</name>
29196                <description>This bit indicates the interrupt by EP1DRQ flag.
29197'0' : Doesn't request the interrupt by EP1DRQ
29198'1' : Request the interrupt by EP1DRQ</description>
29199                <bitRange>[2:2]</bitRange>
29200                <access>read-only</access>
29201              </field>
29202              <field>
29203                <name>EP1SPKED</name>
29204                <description>This bit indicates the interrupt by EP1SPK flag.
29205'0' : Doesn't request the interrupt by EP1SPK
29206'1' : Request the interrupt by EP1SPK</description>
29207                <bitRange>[3:3]</bitRange>
29208                <access>read-only</access>
29209              </field>
29210              <field>
29211                <name>EP2DRQED</name>
29212                <description>This bit indicates the interrupt by EP2DRQ flag.
29213'0' : Doesn't request the interrupt by EP2DRQ
29214'1' : Request the interrupt by EP2DRQ</description>
29215                <bitRange>[4:4]</bitRange>
29216                <access>read-only</access>
29217              </field>
29218              <field>
29219                <name>EP2SPKED</name>
29220                <description>This bit indicates the interrupt by EP2SPK flag.
29221'0' : Doesn't request the interrupt by EP2SPK
29222'1' : Request the interrupt by EP2SPK</description>
29223                <bitRange>[5:5]</bitRange>
29224                <access>read-only</access>
29225              </field>
29226            </fields>
29227          </register>
29228          <register>
29229            <name>HOST_DMA_ENBL</name>
29230            <description>Host DMA Enable Register</description>
29231            <addressOffset>0xB00</addressOffset>
29232            <size>32</size>
29233            <access>read-write</access>
29234            <resetValue>0x0</resetValue>
29235            <resetMask>0xC</resetMask>
29236            <fields>
29237              <field>
29238                <name>DM_EP1DRQE</name>
29239                <description>This bit enables DMA Request by EP1DRQ.
29240'0' : Disable
29241'1' : Enable</description>
29242                <bitRange>[2:2]</bitRange>
29243                <access>read-write</access>
29244              </field>
29245              <field>
29246                <name>DM_EP2DRQE</name>
29247                <description>This bit enables DMA Request by EP2DRQ.
29248'0' : Disable
29249'1' : Enable</description>
29250                <bitRange>[3:3]</bitRange>
29251                <access>read-write</access>
29252              </field>
29253            </fields>
29254          </register>
29255          <register>
29256            <name>HOST_EP1_BLK</name>
29257            <description>Host Endpoint 1 Block Register</description>
29258            <addressOffset>0xB20</addressOffset>
29259            <size>32</size>
29260            <access>read-write</access>
29261            <resetValue>0x0</resetValue>
29262            <resetMask>0xFFFF0000</resetMask>
29263            <fields>
29264              <field>
29265                <name>BLK_NUM</name>
29266                <description>Set the total byte number for DMA transfer. If HOST_EP1_RW1_DR or HOST_EP1_RW2_DR is written, the block number counter is decremented when DMAE='1'.
29267- Set this bits before DMA transfer is enabled (HOST_DMA_ENBL.DM_DP1DRQE='1')</description>
29268                <bitRange>[31:16]</bitRange>
29269                <access>read-write</access>
29270              </field>
29271            </fields>
29272          </register>
29273          <register>
29274            <name>HOST_EP2_BLK</name>
29275            <description>Host Endpoint 2 Block Register</description>
29276            <addressOffset>0xB30</addressOffset>
29277            <size>32</size>
29278            <access>read-write</access>
29279            <resetValue>0x0</resetValue>
29280            <resetMask>0xFFFF0000</resetMask>
29281            <fields>
29282              <field>
29283                <name>BLK_NUM</name>
29284                <description>Set the total byte number for DMA transfer. If HOST_EP2_RW1_DR or HOST_EP2_RW2_DR is written, the block number counter is decremented when DMAE='1'.
29285- Set this bits before DMA transfer is enabled (HOST_DMA_ENBL.DM_DP2DRQE='1')</description>
29286                <bitRange>[31:16]</bitRange>
29287                <access>read-write</access>
29288              </field>
29289            </fields>
29290          </register>
29291        </cluster>
29292      </registers>
29293    </peripheral>
29294    <peripheral>
29295      <name>MXS40USBHSDEV</name>
29296      <description>USB 2 Device Controller Memory Register Map</description>
29297      <baseAddress>0x40430000</baseAddress>
29298      <addressBlock>
29299        <offset>0</offset>
29300        <size>4096</size>
29301        <usage>registers</usage>
29302      </addressBlock>
29303      <registers>
29304        <cluster>
29305          <name>USBHSDEV</name>
29306          <description>USB 2.0 Device Controller Registers</description>
29307          <addressOffset>0x00000000</addressOffset>
29308          <register>
29309            <name>DEV_CS</name>
29310            <description>Device controller Master Control and Status</description>
29311            <addressOffset>0x0</addressOffset>
29312            <size>32</size>
29313            <access>read-write</access>
29314            <resetValue>0x4</resetValue>
29315            <resetMask>0x87FFFFFF</resetMask>
29316            <fields>
29317              <field>
29318                <name>ERR_LIMIT</name>
29319                <description>Error interrupt limit (COUNT &gt;= LIMIT will cause UIB_ERR_INTR.ERRLIMIT interrupt)</description>
29320                <bitRange>[7:0]</bitRange>
29321                <access>read-write</access>
29322              </field>
29323              <field>
29324                <name>COUNT</name>
29325                <description>Number of errors detected. To clear the error count write 0 to these bits</description>
29326                <bitRange>[15:8]</bitRange>
29327                <access>read-write</access>
29328              </field>
29329              <field>
29330                <name>DEVICEADDR</name>
29331                <description>During the USB enumeration process, the host sends a device a unique 7-bit address, which the USB core copies into this register. The USB Core will automatically respond only to its assigned address.  During the USB RESET, this register will be cleared to zero.</description>
29332                <bitRange>[22:16]</bitRange>
29333                <access>read-write</access>
29334              </field>
29335              <field>
29336                <name>TEST_MODE</name>
29337                <description>USB Test Mode
29338    000:  normal operation
29339    001:  Test_J
29340    010:  Test_K
29341    011:  Test_SE0_NAK
29342    100:  Test_Packet
29343[USB 2.0, Sec 7.1.20, p 169; Sec 9.4.9, Table 9-7, p 259]</description>
29344                <bitRange>[25:23]</bitRange>
29345                <access>read-write</access>
29346              </field>
29347              <field>
29348                <name>SETUP_CLR_BUSY</name>
29349                <description>Allow device to ACK SETUP data/status phase packets</description>
29350                <bitRange>[26:26]</bitRange>
29351                <access>read-write</access>
29352              </field>
29353              <field>
29354                <name>NAKALL</name>
29355                <description>Set '1' to this bit, the HW will NAK all transfers from the host in all endpoint1-31.</description>
29356                <bitRange>[31:31]</bitRange>
29357                <access>read-write</access>
29358              </field>
29359            </fields>
29360          </register>
29361          <register>
29362            <name>DEV_FRAMECNT</name>
29363            <description>FRAMECNT register</description>
29364            <addressOffset>0x4</addressOffset>
29365            <size>32</size>
29366            <access>read-only</access>
29367            <resetValue>0x0</resetValue>
29368            <resetMask>0x3FFF</resetMask>
29369            <fields>
29370              <field>
29371                <name>MICROFRAME</name>
29372                <description>MICROFRAME contains a count 0-7 which indicates which of the 8 125-microsecond micro-frames last occurred. This register is active only when Bay is operating at high speed (480 Mbits/sec).</description>
29373                <bitRange>[2:0]</bitRange>
29374                <access>read-only</access>
29375              </field>
29376              <field>
29377                <name>FRAMECNT</name>
29378                <description>Every millisecond the host sends a SOF token indicating 'Start Of Frame,' along with an 11-bit incrementing frame count. The Bay copies the frame count into these registers at every SOF. One use of the frame count is to respond to the USB SYNC_FRAME Request. If the USB core detects a missing or garbled SOF, it generates an internal SOF and increments USBFRAMEL-USBRAMEH.</description>
29379                <bitRange>[13:3]</bitRange>
29380                <access>read-only</access>
29381              </field>
29382            </fields>
29383          </register>
29384          <register>
29385            <name>DEV_PWR_CS</name>
29386            <description>Power management control and status</description>
29387            <addressOffset>0x8</addressOffset>
29388            <size>32</size>
29389            <access>read-write</access>
29390            <resetValue>0x8</resetValue>
29391            <resetMask>0xDD</resetMask>
29392            <fields>
29393              <field>
29394                <name>SIGRSUME</name>
29395                <description>L2-Suspend: Set SIGRSUME=1 to drive the 'K' state onto the USB bus. This should be done only by a device that is capable of remote wakeup, and then only during the SUSPEND state. To signal RESUME, set SIGRSUME=1, waits 10-15 ms, then set SIGRSUME=0. The bit is set and cleared by firmware for device-initiated resume from suspend state.
29396L1-Sleep: The bit is set by firmware and cleared by hardware for device-initiated resume from L1-sleep. The resume is driven for 50us.</description>
29397                <bitRange>[0:0]</bitRange>
29398                <access>read-write</access>
29399              </field>
29400              <field>
29401                <name>NOSYNSOF</name>
29402                <description>If set to 1, disable synthesizing missing SOFs.</description>
29403                <bitRange>[2:2]</bitRange>
29404                <access>read-write</access>
29405              </field>
29406              <field>
29407                <name>DISCON</name>
29408                <description>Setting this bit to '1' will disconnect HW from the USB bus by removing the internal 1.5 K pull-up resistor from the D+</description>
29409                <bitRange>[3:3]</bitRange>
29410                <access>read-write</access>
29411              </field>
29412              <field>
29413                <name>DEV_SUSPEND</name>
29414                <description>Puts the USB device controller and PHY into suspend mode (pull up connected, drivers, PLLs etc turned off).</description>
29415                <bitRange>[4:4]</bitRange>
29416                <access>read-write</access>
29417              </field>
29418              <field>
29419                <name>FORCE_FS</name>
29420                <description>Forces the device controller to enumerate as FS-only device.</description>
29421                <bitRange>[6:6]</bitRange>
29422                <access>read-write</access>
29423              </field>
29424              <field>
29425                <name>HSM</name>
29426                <description>If HSM=1, the SIE is operating in High Speed Mode
294270-1 transition of this bit causes a HSGRANT interrupt request.</description>
29428                <bitRange>[7:7]</bitRange>
29429                <access>read-only</access>
29430              </field>
29431            </fields>
29432          </register>
29433          <register>
29434            <name>DEV_SETUPDAT_0</name>
29435            <description>SETUPDAT0 register</description>
29436            <addressOffset>0xC</addressOffset>
29437            <size>32</size>
29438            <access>read-only</access>
29439            <resetValue>0x0</resetValue>
29440            <resetMask>0xFFFFFFFF</resetMask>
29441            <fields>
29442              <field>
29443                <name>SETUP_REQUEST_TYPE</name>
29444                <description>Setup data field</description>
29445                <bitRange>[7:0]</bitRange>
29446                <access>read-only</access>
29447              </field>
29448              <field>
29449                <name>SETUP_REQUEST</name>
29450                <description>Setup data field</description>
29451                <bitRange>[15:8]</bitRange>
29452                <access>read-only</access>
29453              </field>
29454              <field>
29455                <name>SETUP_VALUE</name>
29456                <description>Setup data field</description>
29457                <bitRange>[31:16]</bitRange>
29458                <access>read-only</access>
29459              </field>
29460            </fields>
29461          </register>
29462          <register>
29463            <name>DEV_SETUPDAT_1</name>
29464            <description>SETUPDAT1 register</description>
29465            <addressOffset>0x10</addressOffset>
29466            <size>32</size>
29467            <access>read-only</access>
29468            <resetValue>0x0</resetValue>
29469            <resetMask>0xFFFFFFFF</resetMask>
29470            <fields>
29471              <field>
29472                <name>SETUP_INDEX</name>
29473                <description>Setup data field</description>
29474                <bitRange>[15:0]</bitRange>
29475                <access>read-only</access>
29476              </field>
29477              <field>
29478                <name>SETUP_LENGTH</name>
29479                <description>Setup data field</description>
29480                <bitRange>[31:16]</bitRange>
29481                <access>read-only</access>
29482              </field>
29483            </fields>
29484          </register>
29485          <register>
29486            <name>DEV_TOGGLE</name>
29487            <description>Data toggle for endpoints</description>
29488            <addressOffset>0x14</addressOffset>
29489            <size>32</size>
29490            <access>read-write</access>
29491            <resetValue>0x100</resetValue>
29492            <resetMask>0x1FF</resetMask>
29493            <fields>
29494              <field>
29495                <name>ENDPOINT</name>
29496                <description>Endpoint</description>
29497                <bitRange>[3:0]</bitRange>
29498                <access>read-write</access>
29499              </field>
29500              <field>
29501                <name>IO</name>
29502                <description>1=IN, 0=OUT</description>
29503                <bitRange>[4:4]</bitRange>
29504                <access>read-write</access>
29505              </field>
29506              <field>
29507                <name>R</name>
29508                <description>Write '1' to reset data toggle to '0'.  When both R and S are set, behavior is undefined.</description>
29509                <bitRange>[5:5]</bitRange>
29510                <access>read-write</access>
29511              </field>
29512              <field>
29513                <name>S</name>
29514                <description>Write '1' to set data toggle to '1'.  When both R and S are set, behavior is undefined.</description>
29515                <bitRange>[6:6]</bitRange>
29516                <access>read-write</access>
29517              </field>
29518              <field>
29519                <name>Q</name>
29520                <description>Current value of toggle bit for EP selected in IO/ENDPOINT</description>
29521                <bitRange>[7:7]</bitRange>
29522                <access>read-only</access>
29523              </field>
29524              <field>
29525                <name>TOGGLE_VALID</name>
29526                <description>Indicates Q is valid for selected endpoint, may be polled in s/w.
29527After writing to R/S, indicates write completion.
29528This bit must be cleared by s/w to initiate an operation.</description>
29529                <bitRange>[8:8]</bitRange>
29530                <access>read-write</access>
29531              </field>
29532            </fields>
29533          </register>
29534          <register>
29535            <dim>16</dim>
29536            <dimIncrement>4</dimIncrement>
29537            <name>DEV_EPI_CS[%s]</name>
29538            <description>IN Endpoint Control and Status register</description>
29539            <addressOffset>0x18</addressOffset>
29540            <size>32</size>
29541            <access>read-write</access>
29542            <resetValue>0x4040</resetValue>
29543            <resetMask>0xFCFDFFFF</resetMask>
29544            <fields>
29545              <field>
29546                <name>PAYLOAD</name>
29547                <description>Max number of bytes transferred for each token
295480=1024 (Powerup default value = 64)</description>
29549                <bitRange>[9:0]</bitRange>
29550                <access>read-write</access>
29551              </field>
29552              <field>
29553                <name>TYPE</name>
29554                <description>The End Point Type (Control on EP0 only)
2955500: Control
2955601: Isochronous
2955710: Bulk
2955811: Interrupt</description>
29559                <bitRange>[11:10]</bitRange>
29560                <access>read-write</access>
29561              </field>
29562              <field>
29563                <name>ISOINPKS</name>
29564                <description>Number of packets to be sent per microframe (aka high-bandwidth mode ISO).  For this implementation only EP3 and EP7 support values other than 1.  EP3 and EP7 support values 1..3.  This field must be 0 for non-ISO endpoints.</description>
29565                <bitRange>[13:12]</bitRange>
29566                <access>read-write</access>
29567              </field>
29568              <field>
29569                <name>VALID</name>
29570                <description>Set VALID=1 to activate an endpoint, and VALID=0 to de-activate it. All USB endpoints default to valid. An endpoint whose VALID bit is 0 does not respond to any USB traffic.</description>
29571                <bitRange>[14:14]</bitRange>
29572                <access>read-write</access>
29573              </field>
29574              <field>
29575                <name>NAK</name>
29576                <description>Setting this bit causes NAK on IN transactions.</description>
29577                <bitRange>[15:15]</bitRange>
29578                <access>read-write</access>
29579              </field>
29580              <field>
29581                <name>STALL</name>
29582                <description>Set this bit to '1' to stall an endpoint, and to '0' to clear a stall.</description>
29583                <bitRange>[16:16]</bitRange>
29584                <access>read-write</access>
29585              </field>
29586              <field>
29587                <name>COMMIT</name>
29588                <description>Set whenever an IN token was ACKed by the host.</description>
29589                <bitRange>[18:18]</bitRange>
29590                <access>read-write</access>
29591              </field>
29592              <field>
29593                <name>BNAK</name>
29594                <description>When the host sends an IN token to any Bulk IN endpoint which does not have data to send, the Bay automatically NAKs the IN token and asserts this interrupt.
29595Note that this bit will not be set if either the Endpoint NAK or global NAK_ALL bits are set when the NAK is transmitted</description>
29596                <bitRange>[19:19]</bitRange>
29597                <access>read-write</access>
29598              </field>
29599              <field>
29600                <name>DONE</name>
29601                <description>Indicates transfer is done (UIB_EPI_XFER_CNT=0).
29602This bit must be cleared by s/w.</description>
29603                <bitRange>[20:20]</bitRange>
29604                <access>read-write</access>
29605              </field>
29606              <field>
29607                <name>ZERO</name>
29608                <description>Indicates a zero length packet was returned to the host in an IN transaction.  Must be cleared by s/w.</description>
29609                <bitRange>[21:21]</bitRange>
29610                <access>read-write</access>
29611              </field>
29612              <field>
29613                <name>SHORT</name>
29614                <description>Indicates a shorter-than-maxsize packet was received, but UIB_EPI_XFER_CNT did not reach 0).</description>
29615                <bitRange>[22:22]</bitRange>
29616                <access>read-write</access>
29617              </field>
29618              <field>
29619                <name>ISOERR</name>
29620                <description>The ISO_ERR is set when ISO data PIDs arrive out of sequence (applies to high speed only), or when an an ISO packet was dropped because no data was available (FS or HS)</description>
29621                <bitRange>[23:23]</bitRange>
29622                <access>read-write</access>
29623              </field>
29624              <field>
29625                <name>COMMIT_MASK</name>
29626                <description>Interrupt mask for COMMIT bit</description>
29627                <bitRange>[26:26]</bitRange>
29628                <access>read-write</access>
29629              </field>
29630              <field>
29631                <name>BNAK_MASK</name>
29632                <description>Interrupt mask for BNAK bit</description>
29633                <bitRange>[27:27]</bitRange>
29634                <access>read-write</access>
29635              </field>
29636              <field>
29637                <name>DONE_MASK</name>
29638                <description>Interrupt mask for DONE bit</description>
29639                <bitRange>[28:28]</bitRange>
29640                <access>read-write</access>
29641              </field>
29642              <field>
29643                <name>ZERO_MASK</name>
29644                <description>Interrupt mask for ZERO bit</description>
29645                <bitRange>[29:29]</bitRange>
29646                <access>read-write</access>
29647              </field>
29648              <field>
29649                <name>SHORT_MASK</name>
29650                <description>Interrupt mask for SHORT bit</description>
29651                <bitRange>[30:30]</bitRange>
29652                <access>read-write</access>
29653              </field>
29654              <field>
29655                <name>ISOERR_MASK</name>
29656                <description>Interrupt mask for ISOERR bit</description>
29657                <bitRange>[31:31]</bitRange>
29658                <access>read-write</access>
29659              </field>
29660            </fields>
29661          </register>
29662          <register>
29663            <dim>16</dim>
29664            <dimIncrement>4</dimIncrement>
29665            <name>DEV_EPI_XFER_CNT[%s]</name>
29666            <description>IN Endpoint remaining transfer length register</description>
29667            <addressOffset>0x58</addressOffset>
29668            <size>32</size>
29669            <access>read-write</access>
29670            <resetValue>0x0</resetValue>
29671            <resetMask>0xFFFFFFFF</resetMask>
29672            <fields>
29673              <field>
29674                <name>BYTES_REMAINING</name>
29675                <description>Number of bytes remaining in the transfer.  This value will never go negative (if more bytes are transferred than remaining in counter, counter will go to 0).</description>
29676                <bitRange>[31:0]</bitRange>
29677                <access>read-write</access>
29678              </field>
29679            </fields>
29680          </register>
29681          <register>
29682            <dim>16</dim>
29683            <dimIncrement>4</dimIncrement>
29684            <name>DEV_EPO_CS[%s]</name>
29685            <description>OUT Endpoint Control and Status</description>
29686            <addressOffset>0x98</addressOffset>
29687            <size>32</size>
29688            <access>read-write</access>
29689            <resetValue>0x4040</resetValue>
29690            <resetMask>0xFEFFFFFF</resetMask>
29691            <fields>
29692              <field>
29693                <name>PAYLOAD</name>
29694                <description>Max number of bytes transferred for each token
296950=1024 (Powerup default value = 64)</description>
29696                <bitRange>[9:0]</bitRange>
29697                <access>read-write</access>
29698              </field>
29699              <field>
29700                <name>TYPE</name>
29701                <description>The End Point Type (Control on EP0 only)
2970200: Control
2970301: Isochronous
2970410: Bulk
2970511: Interrupt</description>
29706                <bitRange>[11:10]</bitRange>
29707                <access>read-write</access>
29708              </field>
29709              <field>
29710                <name>ISOINPKS</name>
29711                <description>Number of packets to be sent per microframe (aka high-bandwidth mode ISO).  For this implementation only EP3 and EP7 support values other than 1.  EP3 and EP7 support values 1..3.  This field must be 0 for non-ISO endpoints.</description>
29712                <bitRange>[13:12]</bitRange>
29713                <access>read-write</access>
29714              </field>
29715              <field>
29716                <name>VALID</name>
29717                <description>Set VALID=1 to activate an endpoint, and VALID=0 to de-activate it. All USB endpoints default to valid. An endpoint whose VALID bit is 0 does not respond to any USB traffic.</description>
29718                <bitRange>[14:14]</bitRange>
29719                <access>read-write</access>
29720              </field>
29721              <field>
29722                <name>NAK</name>
29723                <description>Setting this bit causes NAK on OUT and PING transactions.</description>
29724                <bitRange>[15:15]</bitRange>
29725                <access>read-write</access>
29726              </field>
29727              <field>
29728                <name>STALL</name>
29729                <description>Set this bit to '1' to stall an endpoint, and to '0' to clear a stall.</description>
29730                <bitRange>[16:16]</bitRange>
29731                <access>read-write</access>
29732              </field>
29733              <field>
29734                <name>OVF</name>
29735                <description>Indicates a packet was received in an OUT token with more bytes than PAYLOAD.</description>
29736                <bitRange>[17:17]</bitRange>
29737                <access>read-write</access>
29738              </field>
29739              <field>
29740                <name>COMMIT</name>
29741                <description>Set whenever device controller ACKs an OUT token.</description>
29742                <bitRange>[18:18]</bitRange>
29743                <access>read-write</access>
29744              </field>
29745              <field>
29746                <name>BNAK</name>
29747                <description>When the host sends a PING/OUT token to any Bulk OUT endpoint, which does not have an empty buffer, the Bay automatically NAKs the token and asserts this interrupt.
29748Note that this bit will be set if there is no empty buffer at the receipt of the OUT Packet and if neither the Endpoint NAK or global NAK_ALL bits are set when the NAK is transmitted.</description>
29749                <bitRange>[19:19]</bitRange>
29750                <access>read-write</access>
29751              </field>
29752              <field>
29753                <name>DONE</name>
29754                <description>Indicates transfer is done (UIB_EPI_XFER_CNT=0).
29755This bit must be cleared by s/w.</description>
29756                <bitRange>[20:20]</bitRange>
29757                <access>read-write</access>
29758              </field>
29759              <field>
29760                <name>ZERO</name>
29761                <description>Indicates a zero length packet was returned to the host in an IN transaction.  Must be cleared by s/w.</description>
29762                <bitRange>[21:21]</bitRange>
29763                <access>read-write</access>
29764              </field>
29765              <field>
29766                <name>SHORT</name>
29767                <description>Indicates a shorter-than-maxsize packet was received, but UIB_EPI_XFER_CNT did not reach 0).</description>
29768                <bitRange>[22:22]</bitRange>
29769                <access>read-write</access>
29770              </field>
29771              <field>
29772                <name>ISOERR</name>
29773                <description>The ISO_ERR is set when ISO data PIDs arrive out of sequence (applies to high speed only), or when an an ISO packet was dropped because no buffer space was available (FS or HS)</description>
29774                <bitRange>[23:23]</bitRange>
29775                <access>read-write</access>
29776              </field>
29777              <field>
29778                <name>OVF_MASK</name>
29779                <description>Interrupt mask for OVUF bit</description>
29780                <bitRange>[25:25]</bitRange>
29781                <access>read-write</access>
29782              </field>
29783              <field>
29784                <name>COMMIT_MASK</name>
29785                <description>Intterupt mask for COMMIT bit</description>
29786                <bitRange>[26:26]</bitRange>
29787                <access>read-write</access>
29788              </field>
29789              <field>
29790                <name>BNAK_MASK</name>
29791                <description>Interrupt mask for BNAK bit</description>
29792                <bitRange>[27:27]</bitRange>
29793                <access>read-write</access>
29794              </field>
29795              <field>
29796                <name>DONE_MASK</name>
29797                <description>Interrupt mask for DONE bit</description>
29798                <bitRange>[28:28]</bitRange>
29799                <access>read-write</access>
29800              </field>
29801              <field>
29802                <name>ZERO_MASK</name>
29803                <description>Interrupt mask for ZERO bit</description>
29804                <bitRange>[29:29]</bitRange>
29805                <access>read-write</access>
29806              </field>
29807              <field>
29808                <name>SHORT_MASK</name>
29809                <description>Interrupt mask for SHORT bit</description>
29810                <bitRange>[30:30]</bitRange>
29811                <access>read-write</access>
29812              </field>
29813              <field>
29814                <name>ISOERR_MASK</name>
29815                <description>Interrupt mask for ISOERR bit</description>
29816                <bitRange>[31:31]</bitRange>
29817                <access>read-write</access>
29818              </field>
29819            </fields>
29820          </register>
29821          <register>
29822            <dim>16</dim>
29823            <dimIncrement>4</dimIncrement>
29824            <name>DEV_EPO_XFER_CNT[%s]</name>
29825            <description>OUT Endpoint remaining transfer length register</description>
29826            <addressOffset>0xD8</addressOffset>
29827            <size>32</size>
29828            <access>read-write</access>
29829            <resetValue>0x0</resetValue>
29830            <resetMask>0xFFFFFFFF</resetMask>
29831            <fields>
29832              <field>
29833                <name>BYTES_REMAINING</name>
29834                <description>Number of bytes remaining in the transfer.  This value will never go negative (if more bytes are transferred than remaining in counter, counter will go to 0).</description>
29835                <bitRange>[31:0]</bitRange>
29836                <access>read-write</access>
29837              </field>
29838            </fields>
29839          </register>
29840          <register>
29841            <name>DEV_CTL_INTR_MASK</name>
29842            <description>CONTROL interrupt mask register</description>
29843            <addressOffset>0x118</addressOffset>
29844            <size>32</size>
29845            <access>read-write</access>
29846            <resetValue>0x0</resetValue>
29847            <resetMask>0x1FFF</resetMask>
29848            <fields>
29849              <field>
29850                <name>SETADDR</name>
29851                <description>Active high. 1 - Masks the SET_ADDRESS interrupt. 0 - Unmasks the SET_ADDRESS interrupt.</description>
29852                <bitRange>[0:0]</bitRange>
29853                <access>read-write</access>
29854              </field>
29855              <field>
29856                <name>SOF</name>
29857                <description>Set whenever a SOF occurrs</description>
29858                <bitRange>[1:1]</bitRange>
29859                <access>read-write</access>
29860              </field>
29861              <field>
29862                <name>SUSP</name>
29863                <description>Set when the host suspends the USB bus (USB SUSPEND)</description>
29864                <bitRange>[2:2]</bitRange>
29865                <access>read-write</access>
29866              </field>
29867              <field>
29868                <name>URESET</name>
29869                <description>Set when the host has initiated USB RESET (2.5us single ended 0 on bus)</description>
29870                <bitRange>[3:3]</bitRange>
29871                <access>read-write</access>
29872              </field>
29873              <field>
29874                <name>HSGRANT</name>
29875                <description>Set when the host grants high speed communications.</description>
29876                <bitRange>[4:4]</bitRange>
29877                <access>read-write</access>
29878              </field>
29879              <field>
29880                <name>SUTOK</name>
29881                <description>Set whenever a (valid of invalid) SETUP token is received</description>
29882                <bitRange>[5:5]</bitRange>
29883                <access>read-write</access>
29884              </field>
29885              <field>
29886                <name>SUDAV</name>
29887                <description>Set when a valid SETUP token and data is received.  Data from this token can be read from UIB_DEV_SETUPDAT.</description>
29888                <bitRange>[6:6]</bitRange>
29889                <access>read-write</access>
29890              </field>
29891              <field>
29892                <name>ERRLIMIT</name>
29893                <description>USB Error limit detect from UIB_DEV_CS (COUNT&gt;=LIMIT)</description>
29894                <bitRange>[7:7]</bitRange>
29895                <access>read-write</access>
29896              </field>
29897              <field>
29898                <name>URESUME</name>
29899                <description>Set when the host has initiated USB RESUME (&gt;2.5us K state on bus)</description>
29900                <bitRange>[8:8]</bitRange>
29901                <access>read-write</access>
29902              </field>
29903              <field>
29904                <name>STATUS_STAGE</name>
29905                <description>Set when host completes Status Stage of a Control Transfer</description>
29906                <bitRange>[9:9]</bitRange>
29907                <access>read-write</access>
29908              </field>
29909              <field>
29910                <name>L1_SLEEP_REQ</name>
29911                <description>Set when host issues a LPM-L1-SLEEP request</description>
29912                <bitRange>[10:10]</bitRange>
29913                <access>read-write</access>
29914              </field>
29915              <field>
29916                <name>L1_URESUME</name>
29917                <description>Set when the host has initiated USB RESUME to exit from L1-Sleep low-power mode. It indicates both host-initiated and host-reflected resume request.</description>
29918                <bitRange>[11:11]</bitRange>
29919                <access>read-write</access>
29920              </field>
29921              <field>
29922                <name>RESETDONE</name>
29923                <description>Set when an end-of-reset signaling is detected by the device.</description>
29924                <bitRange>[12:12]</bitRange>
29925                <access>read-write</access>
29926              </field>
29927            </fields>
29928          </register>
29929          <register>
29930            <name>DEV_CTL_INTR</name>
29931            <description>CONTROL interrupt request register</description>
29932            <addressOffset>0x11C</addressOffset>
29933            <size>32</size>
29934            <access>read-write</access>
29935            <resetValue>0x0</resetValue>
29936            <resetMask>0x1FFF</resetMask>
29937            <fields>
29938              <field>
29939                <name>SETADDR</name>
29940                <description>Set when host issues a SET_ADDR request to the device</description>
29941                <bitRange>[0:0]</bitRange>
29942                <access>read-write</access>
29943              </field>
29944              <field>
29945                <name>SOF</name>
29946                <description>Set whenever a SOF occurrs</description>
29947                <bitRange>[1:1]</bitRange>
29948                <access>read-write</access>
29949              </field>
29950              <field>
29951                <name>SUSP</name>
29952                <description>Set when the host suspends the USB bus (USB SUSPEND)</description>
29953                <bitRange>[2:2]</bitRange>
29954                <access>read-write</access>
29955              </field>
29956              <field>
29957                <name>URESET</name>
29958                <description>Set when the host has initiated USB RESET (2.5us single ended 0 on bus)</description>
29959                <bitRange>[3:3]</bitRange>
29960                <access>read-write</access>
29961              </field>
29962              <field>
29963                <name>HSGRANT</name>
29964                <description>Set when the host grants high speed communications.</description>
29965                <bitRange>[4:4]</bitRange>
29966                <access>read-write</access>
29967              </field>
29968              <field>
29969                <name>SUTOK</name>
29970                <description>Set whenever a (valid of invalid) SETUP token is received</description>
29971                <bitRange>[5:5]</bitRange>
29972                <access>read-write</access>
29973              </field>
29974              <field>
29975                <name>SUDAV</name>
29976                <description>Set when a valid SETUP token and data is received.  Data from this token can be read from UIB_DEV_SETUPDAT.</description>
29977                <bitRange>[6:6]</bitRange>
29978                <access>read-write</access>
29979              </field>
29980              <field>
29981                <name>ERRLIMIT</name>
29982                <description>USB Error limit detect from UIB_DEV_CS (COUNT&gt;=LIMIT)</description>
29983                <bitRange>[7:7]</bitRange>
29984                <access>read-write</access>
29985              </field>
29986              <field>
29987                <name>URESUME</name>
29988                <description>Set when the host has initiated USB RESUME (&gt;2.5us K state on bus)</description>
29989                <bitRange>[8:8]</bitRange>
29990                <access>read-write</access>
29991              </field>
29992              <field>
29993                <name>STATUS_STAGE</name>
29994                <description>Set when host completes Status Stage of a Control Transfer</description>
29995                <bitRange>[9:9]</bitRange>
29996                <access>read-write</access>
29997              </field>
29998              <field>
29999                <name>L1_SLEEP_REQ</name>
30000                <description>Set when host issues a LPM token to enter L1-SLEEP request</description>
30001                <bitRange>[10:10]</bitRange>
30002                <access>read-write</access>
30003              </field>
30004              <field>
30005                <name>L1_URESUME</name>
30006                <description>Set when host sent a USB RESUME request when in L1-Sleep low-power mode. It indicates both host-initiated and host-reflected resume request.</description>
30007                <bitRange>[11:11]</bitRange>
30008                <access>read-write</access>
30009              </field>
30010              <field>
30011                <name>RESETDONE</name>
30012                <description>Set when an end-of-reset signaling is detected by the device</description>
30013                <bitRange>[12:12]</bitRange>
30014                <access>read-write</access>
30015              </field>
30016            </fields>
30017          </register>
30018          <register>
30019            <name>DEV_CTL_INTR_MASKED</name>
30020            <description>CONTROL interrupt masked register</description>
30021            <addressOffset>0x120</addressOffset>
30022            <size>32</size>
30023            <access>read-only</access>
30024            <resetValue>0x0</resetValue>
30025            <resetMask>0x1FFF</resetMask>
30026            <fields>
30027              <field>
30028                <name>SETADDR_MASKED</name>
30029                <description>Mask status for SET_ADDRESS interrupt</description>
30030                <bitRange>[0:0]</bitRange>
30031                <access>read-only</access>
30032              </field>
30033              <field>
30034                <name>SOF_MASKED</name>
30035                <description>Mask status for SOF interrupt</description>
30036                <bitRange>[1:1]</bitRange>
30037                <access>read-only</access>
30038              </field>
30039              <field>
30040                <name>SUSP_MASKED</name>
30041                <description>Mask status for Suspend interrupt</description>
30042                <bitRange>[2:2]</bitRange>
30043                <access>read-only</access>
30044              </field>
30045              <field>
30046                <name>URESET_MASKED</name>
30047                <description>Mask status for USB interface interrupt</description>
30048                <bitRange>[3:3]</bitRange>
30049                <access>read-only</access>
30050              </field>
30051              <field>
30052                <name>HSGRANT_MASKED</name>
30053                <description>Mask status for interrupt indicating the host accepting high speed communications.</description>
30054                <bitRange>[4:4]</bitRange>
30055                <access>read-only</access>
30056              </field>
30057              <field>
30058                <name>SUTOK_MASKED</name>
30059                <description>Mask status for SETUP token interrupt.</description>
30060                <bitRange>[5:5]</bitRange>
30061                <access>read-only</access>
30062              </field>
30063              <field>
30064                <name>SUDAV_MASKED</name>
30065                <description>Mask status for interrupt - Receiving SETUP and Data tokens.</description>
30066                <bitRange>[6:6]</bitRange>
30067                <access>read-only</access>
30068              </field>
30069              <field>
30070                <name>ERRLIMIT_MASKED</name>
30071                <description>Mask status for USB Error limit detect interrupt</description>
30072                <bitRange>[7:7]</bitRange>
30073                <access>read-only</access>
30074              </field>
30075              <field>
30076                <name>URESUME_MASKED</name>
30077                <description>Mask status for host initiated USB RESUME interrupt (&gt;2.5us K state on bus)</description>
30078                <bitRange>[8:8]</bitRange>
30079                <access>read-only</access>
30080              </field>
30081              <field>
30082                <name>STATUS_STAGE_MASKED</name>
30083                <description>Mask status for interrupt indicating host completed Status Stage of a Control Transfer</description>
30084                <bitRange>[9:9]</bitRange>
30085                <access>read-only</access>
30086              </field>
30087              <field>
30088                <name>L1_SLEEP_REQ_MASKED</name>
30089                <description>Mask status for interrupt indicating host issued a LPM token for L1-SLEEP request</description>
30090                <bitRange>[10:10]</bitRange>
30091                <access>read-only</access>
30092              </field>
30093              <field>
30094                <name>L1_URESUME_MASKED</name>
30095                <description>Mask status for interrupt indicating host sent a resume request when in L1-Sleep low-power mode. It indicates both host-initiated and host-reflected resume request.</description>
30096                <bitRange>[11:11]</bitRange>
30097                <access>read-only</access>
30098              </field>
30099              <field>
30100                <name>RESETDONE_MASKED</name>
30101                <description>Mask status for interrupt indicating end-of-reset signaling detected by the device controller.</description>
30102                <bitRange>[12:12]</bitRange>
30103                <access>read-only</access>
30104              </field>
30105            </fields>
30106          </register>
30107          <register>
30108            <name>DEV_CTL_INTR_SET</name>
30109            <description>CONTROL interrupt set register</description>
30110            <addressOffset>0x124</addressOffset>
30111            <size>32</size>
30112            <access>read-write</access>
30113            <resetValue>0x0</resetValue>
30114            <resetMask>0x1FFF</resetMask>
30115            <fields>
30116              <field>
30117                <name>SETADDR_MASKED</name>
30118                <description>Write with '1' to set corresponding bit in interrupt request register.</description>
30119                <bitRange>[0:0]</bitRange>
30120                <access>read-write</access>
30121              </field>
30122              <field>
30123                <name>SOF_MASKED</name>
30124                <description>Write with '1' to set corresponding bit in interrupt request register.</description>
30125                <bitRange>[1:1]</bitRange>
30126                <access>read-write</access>
30127              </field>
30128              <field>
30129                <name>SUSP_MASKED</name>
30130                <description>Write with '1' to set corresponding bit in interrupt request register.</description>
30131                <bitRange>[2:2]</bitRange>
30132                <access>read-write</access>
30133              </field>
30134              <field>
30135                <name>URESET_MASKED</name>
30136                <description>Write with '1' to set corresponding bit in interrupt request register.</description>
30137                <bitRange>[3:3]</bitRange>
30138                <access>read-write</access>
30139              </field>
30140              <field>
30141                <name>HSGRANT_MASKED</name>
30142                <description>Write with '1' to set corresponding bit in interrupt request register.</description>
30143                <bitRange>[4:4]</bitRange>
30144                <access>read-write</access>
30145              </field>
30146              <field>
30147                <name>SUTOK_MASKED</name>
30148                <description>Write with '1' to set corresponding bit in interrupt request register.</description>
30149                <bitRange>[5:5]</bitRange>
30150                <access>read-write</access>
30151              </field>
30152              <field>
30153                <name>SUDAV_MASKED</name>
30154                <description>Write with '1' to set corresponding bit in interrupt request register.</description>
30155                <bitRange>[6:6]</bitRange>
30156                <access>read-write</access>
30157              </field>
30158              <field>
30159                <name>ERRLIMIT_MASKED</name>
30160                <description>Write with '1' to set corresponding bit in interrupt request register.</description>
30161                <bitRange>[7:7]</bitRange>
30162                <access>read-write</access>
30163              </field>
30164              <field>
30165                <name>URESUME_MASKED</name>
30166                <description>Write with '1' to set corresponding bit in interrupt request register.</description>
30167                <bitRange>[8:8]</bitRange>
30168                <access>read-write</access>
30169              </field>
30170              <field>
30171                <name>STATUS_STAGE_MASKED</name>
30172                <description>Write with '1' to set corresponding bit in interrupt request register.</description>
30173                <bitRange>[9:9]</bitRange>
30174                <access>read-write</access>
30175              </field>
30176              <field>
30177                <name>L1_SLEEP_REQ_MASKED</name>
30178                <description>Write with '1' to set corresponding bit in interrupt request register.</description>
30179                <bitRange>[10:10]</bitRange>
30180                <access>read-write</access>
30181              </field>
30182              <field>
30183                <name>L1_URESUME_MASKED</name>
30184                <description>Write with '1' to set corresponding bit in interrupt request register.</description>
30185                <bitRange>[11:11]</bitRange>
30186                <access>read-write</access>
30187              </field>
30188              <field>
30189                <name>RESETDONE_MASKED</name>
30190                <description>Write with '1' to set corresponding bit in interrupt request register.</description>
30191                <bitRange>[12:12]</bitRange>
30192                <access>read-write</access>
30193              </field>
30194            </fields>
30195          </register>
30196          <register>
30197            <name>DEV_EP_INTR_MASK</name>
30198            <description>USB EP interrupt mask register</description>
30199            <addressOffset>0x128</addressOffset>
30200            <size>32</size>
30201            <access>read-write</access>
30202            <resetValue>0x0</resetValue>
30203            <resetMask>0xFFFFFFFF</resetMask>
30204            <fields>
30205              <field>
30206                <name>EP_IN</name>
30207                <description>Bit &lt;x&gt; masks any interrupt from EPI_CS[x]</description>
30208                <bitRange>[15:0]</bitRange>
30209                <access>read-write</access>
30210              </field>
30211              <field>
30212                <name>EP_OUT</name>
30213                <description>Bit &lt;16+x&gt; masks any interrupt from EPO_CS[x]</description>
30214                <bitRange>[31:16]</bitRange>
30215                <access>read-write</access>
30216              </field>
30217            </fields>
30218          </register>
30219          <register>
30220            <name>DEV_EP_INTR</name>
30221            <description>USB EP interrupt request register</description>
30222            <addressOffset>0x12C</addressOffset>
30223            <size>32</size>
30224            <access>read-write</access>
30225            <resetValue>0x0</resetValue>
30226            <resetMask>0xFFFFFFFF</resetMask>
30227            <fields>
30228              <field>
30229                <name>EP_IN</name>
30230                <description>Bit &lt;x&gt; indicates an interrupt from EPI_CS[x]</description>
30231                <bitRange>[15:0]</bitRange>
30232                <access>read-write</access>
30233              </field>
30234              <field>
30235                <name>EP_OUT</name>
30236                <description>Bit &lt;16+x&gt; indicates an interrupt from EPO_CS[x]</description>
30237                <bitRange>[31:16]</bitRange>
30238                <access>read-write</access>
30239              </field>
30240            </fields>
30241          </register>
30242          <register>
30243            <name>DEV_EP_INTR_MASKED</name>
30244            <description>USB EP interrupt masked register</description>
30245            <addressOffset>0x130</addressOffset>
30246            <size>32</size>
30247            <access>read-only</access>
30248            <resetValue>0x0</resetValue>
30249            <resetMask>0xFFFFFFFF</resetMask>
30250            <fields>
30251              <field>
30252                <name>EP_IN</name>
30253                <description>1 - Corresponding interrupt is masked. 0 - Not masked.
30254Bit &lt;x&gt; indicates an interrupt from EPI_CS[x]</description>
30255                <bitRange>[15:0]</bitRange>
30256                <access>read-only</access>
30257              </field>
30258              <field>
30259                <name>EP_OUT</name>
30260                <description>1 - Corresponding interrupt is masked. 0 - Not masked. Bit &lt;16+x&gt; indicates an interrupt from EPO_CS[x]</description>
30261                <bitRange>[31:16]</bitRange>
30262                <access>read-only</access>
30263              </field>
30264            </fields>
30265          </register>
30266          <register>
30267            <name>DEV_EP_INTR_SET</name>
30268            <description>USB EP interrupt set register</description>
30269            <addressOffset>0x134</addressOffset>
30270            <size>32</size>
30271            <access>read-write</access>
30272            <resetValue>0x0</resetValue>
30273            <resetMask>0xFFFFFFFF</resetMask>
30274            <fields>
30275              <field>
30276                <name>EP_IN</name>
30277                <description>Write with '1' to set corresponding bit in interrupt request register.</description>
30278                <bitRange>[15:0]</bitRange>
30279                <access>read-write</access>
30280              </field>
30281              <field>
30282                <name>EP_OUT</name>
30283                <description>Write with '1' to set corresponding bit in interrupt request register.</description>
30284                <bitRange>[31:16]</bitRange>
30285                <access>read-write</access>
30286              </field>
30287            </fields>
30288          </register>
30289          <register>
30290            <name>DEV_EP_INGRS_INTR_MASK</name>
30291            <description>USB EP INGRS interrupt mask register</description>
30292            <addressOffset>0x138</addressOffset>
30293            <size>32</size>
30294            <access>read-write</access>
30295            <resetValue>0x0</resetValue>
30296            <resetMask>0xFFFFFFFF</resetMask>
30297            <fields>
30298              <field>
30299                <name>EP_INGRS_ZLP_RCVD</name>
30300                <description>Bit &lt;x&gt; masks any interrupt from DEV_EP_INGRS_INTR[x]</description>
30301                <bitRange>[15:0]</bitRange>
30302                <access>read-write</access>
30303              </field>
30304              <field>
30305                <name>EP_INGRS_SLP_RCVD</name>
30306                <description>Bit &lt;16+x&gt; masks any interrupt from DEV_EP_INGRS_INTR[x]</description>
30307                <bitRange>[31:16]</bitRange>
30308                <access>read-write</access>
30309              </field>
30310            </fields>
30311          </register>
30312          <register>
30313            <name>DEV_EP_INGRS_INTR</name>
30314            <description>USB EP INGRS interrupt request register</description>
30315            <addressOffset>0x13C</addressOffset>
30316            <size>32</size>
30317            <access>read-write</access>
30318            <resetValue>0x0</resetValue>
30319            <resetMask>0xFFFFFFFF</resetMask>
30320            <fields>
30321              <field>
30322                <name>EP_INGRS_ZLP_RCVD</name>
30323                <description>Bit &lt;x&gt; indicates a zero-packet arrival interrupt for each endpoint.</description>
30324                <bitRange>[15:0]</bitRange>
30325                <access>read-write</access>
30326              </field>
30327              <field>
30328                <name>EP_INGRS_SLP_RCVD</name>
30329                <description>Bit &lt;16+x&gt; indicates a zero-packet arrival interrupt for each endpoint.</description>
30330                <bitRange>[31:16]</bitRange>
30331                <access>read-write</access>
30332              </field>
30333            </fields>
30334          </register>
30335          <register>
30336            <name>DEV_EP_INGRS_INTR_MASKED</name>
30337            <description>USB EP INGRS interrupt masked register</description>
30338            <addressOffset>0x140</addressOffset>
30339            <size>32</size>
30340            <access>read-only</access>
30341            <resetValue>0x0</resetValue>
30342            <resetMask>0xFFFFFFFF</resetMask>
30343            <fields>
30344              <field>
30345                <name>EP_INGRS_ZLP_RCVD</name>
30346                <description>1 - Corresponding interrupt is masked. 0 - Not masked.
30347Bit &lt;x&gt; indicates masked bit for DEV_EP_INGRS_INTR[x]</description>
30348                <bitRange>[15:0]</bitRange>
30349                <access>read-only</access>
30350              </field>
30351              <field>
30352                <name>EP_INGRS_SLP_RCVD</name>
30353                <description>1 - Corresponding interrupt is masked. 0 - Not masked. Bit &lt;16+x&gt; indicates masked bit for DEV_EP_INGRS_INTR[x]</description>
30354                <bitRange>[31:16]</bitRange>
30355                <access>read-only</access>
30356              </field>
30357            </fields>
30358          </register>
30359          <register>
30360            <name>DEV_EP_INGRS_INTR_SET</name>
30361            <description>USB EP INGRS interrupt set register</description>
30362            <addressOffset>0x144</addressOffset>
30363            <size>32</size>
30364            <access>read-write</access>
30365            <resetValue>0x0</resetValue>
30366            <resetMask>0xFFFFFFFF</resetMask>
30367            <fields>
30368              <field>
30369                <name>EP_INGRS_ZLP_RCVD</name>
30370                <description>Write with '1' to set corresponding bit in interrupt request register.</description>
30371                <bitRange>[15:0]</bitRange>
30372                <access>read-write</access>
30373              </field>
30374              <field>
30375                <name>EP_INGRS_SLP_RCVD</name>
30376                <description>Write with '1' to set corresponding bit in interrupt request register.</description>
30377                <bitRange>[31:16]</bitRange>
30378                <access>read-write</access>
30379              </field>
30380            </fields>
30381          </register>
30382          <register>
30383            <name>DEV_EP_EGRS_INTR_MASK</name>
30384            <description>USB EP EGRS interrupt mask register</description>
30385            <addressOffset>0x148</addressOffset>
30386            <size>32</size>
30387            <access>read-write</access>
30388            <resetValue>0x0</resetValue>
30389            <resetMask>0xFFFFFFFF</resetMask>
30390            <fields>
30391              <field>
30392                <name>EP_EGRS_ZLP_SENT</name>
30393                <description>Bit &lt;x&gt; masks any interrupt from DEV_EP_EGRS_INTR[x]</description>
30394                <bitRange>[15:0]</bitRange>
30395                <access>read-write</access>
30396              </field>
30397              <field>
30398                <name>EP_EGRS_SLP_SENT</name>
30399                <description>Bit &lt;16+x&gt; masks any interrupt from DEV_EP_EGRS_INTR[x]</description>
30400                <bitRange>[31:16]</bitRange>
30401                <access>read-write</access>
30402              </field>
30403            </fields>
30404          </register>
30405          <register>
30406            <name>DEV_EP_EGRS_INTR</name>
30407            <description>USB EP EGRS interrupt request register</description>
30408            <addressOffset>0x14C</addressOffset>
30409            <size>32</size>
30410            <access>read-write</access>
30411            <resetValue>0x0</resetValue>
30412            <resetMask>0xFFFFFFFF</resetMask>
30413            <fields>
30414              <field>
30415                <name>EP_EGRS_ZLP_SENT</name>
30416                <description>1 - Firmware sets to schedule a ZLP request on egress path for an endpoint.
304170 - Hardware clears to indicate a ZLP packet is sent after all pending transfers for an endpoint.
30418Each bit represents an endpoint on egress path.</description>
30419                <bitRange>[15:0]</bitRange>
30420                <access>read-write</access>
30421              </field>
30422              <field>
30423                <name>EP_EGRS_SLP_SENT</name>
30424                <description>1 - Firmware sets to schedule a SLP request on egress path for an endpoint.
304250 - Hardware clears to indicate a SLP packet is sent on egress path for an endpoint.
30426Each bit represents an endpoint on egress path.</description>
30427                <bitRange>[31:16]</bitRange>
30428                <access>read-write</access>
30429              </field>
30430            </fields>
30431          </register>
30432          <register>
30433            <name>DEV_EP_EGRS_INTR_MASKED</name>
30434            <description>USB EP EGRS interrupt masked register</description>
30435            <addressOffset>0x150</addressOffset>
30436            <size>32</size>
30437            <access>read-only</access>
30438            <resetValue>0x0</resetValue>
30439            <resetMask>0xFFFFFFFF</resetMask>
30440            <fields>
30441              <field>
30442                <name>EP_EGRS_ZLP_SENT</name>
30443                <description>1 - Corresponding interrupt is masked. 0 - Not masked.
30444Bit &lt;x&gt; indicates an interrupt from DEV_EP_EGRS_INTR[x]</description>
30445                <bitRange>[15:0]</bitRange>
30446                <access>read-only</access>
30447              </field>
30448              <field>
30449                <name>EP_EGRS_SLP_SENT</name>
30450                <description>1 - Corresponding interrupt is masked. 0 - Not masked. Bit &lt;16+x&gt; indicates an interrupt from DEV_EP_EGRS_INTR[x]</description>
30451                <bitRange>[31:16]</bitRange>
30452                <access>read-only</access>
30453              </field>
30454            </fields>
30455          </register>
30456          <register>
30457            <name>DEV_EP_EGRS_INTR_SET</name>
30458            <description>USB EP EGRS interrupt set register</description>
30459            <addressOffset>0x154</addressOffset>
30460            <size>32</size>
30461            <access>read-write</access>
30462            <resetValue>0x0</resetValue>
30463            <resetMask>0xFFFFFFFF</resetMask>
30464            <fields>
30465              <field>
30466                <name>EP_EGRS_ZLP_SENT</name>
30467                <description>Write with '1' to set corresponding bit in interrupt request register.</description>
30468                <bitRange>[15:0]</bitRange>
30469                <access>read-write</access>
30470              </field>
30471              <field>
30472                <name>EP_EGRS_SLP_SENT</name>
30473                <description>Write with '1' to set corresponding bit in interrupt request register.</description>
30474                <bitRange>[31:16]</bitRange>
30475                <access>read-write</access>
30476              </field>
30477            </fields>
30478          </register>
30479          <register>
30480            <name>POWER</name>
30481            <description>USB 2.0 Device Power, Clock &amp; Reset Control Register</description>
30482            <addressOffset>0x158</addressOffset>
30483            <size>32</size>
30484            <access>read-write</access>
30485            <resetValue>0x12</resetValue>
30486            <resetMask>0x3F</resetMask>
30487            <fields>
30488              <field>
30489                <name>RESETN</name>
30490                <description>Active LOW reset signal for all logic in the block.  Note that reset is active on all flops in the block when either system reset is asserted (RESET# pin or SYSTEM_POWER.RESETN is asserted) or this signal is active.
30491After setting this bit to 1, firmware shall poll and wait for the 'active' bit to assert.  Reading '1' from 'resetn' does not indicate the block is out of reset - this may take some time depending on initialization tasks and clock frequencies.</description>
30492                <bitRange>[0:0]</bitRange>
30493                <access>read-write</access>
30494              </field>
30495              <field>
30496                <name>EPM_DCG_ENABLE</name>
30497                <description>Active High. 1 - Indicates that dynamic clock gating is enabled in the EPM core. 0 - Indicates that dynamic clock gating is disabled in the EPM core.</description>
30498                <bitRange>[1:1]</bitRange>
30499                <access>read-write</access>
30500              </field>
30501              <field>
30502                <name>CLK_SCALING_EN</name>
30503                <description>Active High. 1 - Improves timing margin for HS mode when clk_slow is scaled down to 75MHz. 0 - No change in timing margin for HS mode when clk_slow is at 100MHz.</description>
30504                <bitRange>[2:2]</bitRange>
30505                <access>read-write</access>
30506              </field>
30507              <field>
30508                <name>SEL_EXT_FS_CLK</name>
30509                <description>Active High. 1 - Selects an external PLL to provide clock during full-speed mode of operation. 0 - Selects an internal PLL in PHY to provide clock during full-speed mode of operation.</description>
30510                <bitRange>[3:3]</bitRange>
30511                <access>read-write</access>
30512              </field>
30513              <field>
30514                <name>LPM_ENABLE</name>
30515                <description>Active High. 1 - Indicates LPM feature is enabled in controller. 0 - Indicates LPM feature is disabledi n controller.</description>
30516                <bitRange>[4:4]</bitRange>
30517                <access>read-write</access>
30518              </field>
30519              <field>
30520                <name>VBUS_VALID</name>
30521                <description>Active High. 1 - Indicates VBUS supply ready and stable on USB interface. 0 - Indicates VBUS supply is not ready on USB interface.</description>
30522                <bitRange>[5:5]</bitRange>
30523                <access>read-write</access>
30524              </field>
30525            </fields>
30526          </register>
30527          <register>
30528            <name>DEV_LPM_ATTR</name>
30529            <description>USB 2.0 Device LPM HIRD Register</description>
30530            <addressOffset>0x15C</addressOffset>
30531            <size>32</size>
30532            <access>read-write</access>
30533            <resetValue>0x10E00</resetValue>
30534            <resetMask>0xFFFF3F</resetMask>
30535            <fields>
30536              <field>
30537                <name>RMT_WAKEUP_ENABLE</name>
30538                <description>Active High. 1 - Host enabled support for remote wake-up by device during L1-Sleep. 0 - Host disabled support for remote wake-up by device during L1-sleep.</description>
30539                <bitRange>[0:0]</bitRange>
30540                <access>read-only</access>
30541              </field>
30542              <field>
30543                <name>HIRD</name>
30544                <description>Host publishes value of the HIRD ranging from 75us till 9.95ms for the device.
305450x0: Duration of resume sequence by host 75us.
305460x1: Duration of resume sequence by host 100us.
305470x2: Duration of resume sequence by host 150us.
305480x3: Duration of resume sequence by host 250us.
305490x4: Duration of resume sequence by host 350us.
305500x5: Duration of resume sequence by host 450us.
305510x6: Duration of resume sequence by host 950us.
305520x7: Duration of resume sequence by host 1950us.
305530x8: Duration of resume sequence by host 2950us.
305540x9: Duration of resume sequence by host 3950us.
305550xA: Duration of resume sequence by host 4950us.
305560xB: Duration of resume sequence by host 5950us.
305570xC: Duration of resume sequence by host 6950us.
305580xD: Duration of resume sequence by host 7950us.
305590xE: Duration of resume sequence by host 8950us.
305600xF: Duration of resume sequence by host 9950us.</description>
30561                <bitRange>[4:1]</bitRange>
30562                <access>read-only</access>
30563              </field>
30564              <field>
30565                <name>NYET</name>
30566                <description>Active High. 1 - Sends a NYET response for a LPM token received from the Host. 0 - No NYET response sent to the host for a LPM token received.</description>
30567                <bitRange>[5:5]</bitRange>
30568                <access>read-write</access>
30569              </field>
30570              <field>
30571                <name>T_L1_TOKEN_RETRY</name>
30572                <description>Programmable value to wait for 10us after a LPM token is received and before the device enters L1-state. Allowed values range from 240 till 300 as required by USB LPM specification.</description>
30573                <bitRange>[23:8]</bitRange>
30574                <access>read-write</access>
30575              </field>
30576            </fields>
30577          </register>
30578          <register>
30579            <name>DEV_LPM_TIM_1</name>
30580            <description>USB 2.0 Device LPM Timer Parameter Register</description>
30581            <addressOffset>0x160</addressOffset>
30582            <size>32</size>
30583            <access>read-write</access>
30584            <resetValue>0x5DC</resetValue>
30585            <resetMask>0xFFF</resetMask>
30586            <fields>
30587              <field>
30588                <name>T_L1_DEV_DRV_RESUME</name>
30589                <description>Programmable value to wait for 50us while driving resume when in L1-sleep low-power mode. Allowed values range from 0x5BE till 0x5FA as required by USB LPM specification.</description>
30590                <bitRange>[11:0]</bitRange>
30591                <access>read-write</access>
30592              </field>
30593            </fields>
30594          </register>
30595          <register>
30596            <name>DEV_CHIRP_OVERRIDE</name>
30597            <description>USB 2.0 Device Chirp Override Register</description>
30598            <addressOffset>0x164</addressOffset>
30599            <size>32</size>
30600            <access>read-write</access>
30601            <resetValue>0x0</resetValue>
30602            <resetMask>0xFF</resetMask>
30603            <fields>
30604              <field>
30605                <name>OVERRIDE_FSM</name>
30606                <description>Active High. 1 - Allows override of initialization sequence by forcing transitions indicated by other bits of this register. 0 - Override is disabled.</description>
30607                <bitRange>[0:0]</bitRange>
30608                <access>read-write</access>
30609              </field>
30610              <field>
30611                <name>FORCE_CHIRP_K</name>
30612                <description>Active High. 1 - Forces chirp-K sequence on interface if override is enabled. 0 - Disables chirp-K sequence on interface.</description>
30613                <bitRange>[1:1]</bitRange>
30614                <access>read-write</access>
30615              </field>
30616              <field>
30617                <name>FORCE_CHIRP_J</name>
30618                <description>Active High. 1 - Forces chirp-J sequence on interface if override is enabled. 0 - Disables chirp-J sequence on interface.</description>
30619                <bitRange>[2:2]</bitRange>
30620                <access>read-write</access>
30621              </field>
30622              <field>
30623                <name>STATE</name>
30624                <description>Override state value for chirp state machine when override is enabled. 0x0 - Full-Speed Mode, 0xD - High-Speed Mode.</description>
30625                <bitRange>[7:3]</bitRange>
30626                <access>read-write</access>
30627              </field>
30628            </fields>
30629          </register>
30630          <register>
30631            <name>CRU_EXT_LSFS_CLK_DIVIDER</name>
30632            <description>EXT LSFS Clock Divider Register</description>
30633            <addressOffset>0x168</addressOffset>
30634            <size>32</size>
30635            <access>read-write</access>
30636            <resetValue>0x0</resetValue>
30637            <resetMask>0xF</resetMask>
30638            <fields>
30639              <field>
30640                <name>DIVN_VALUE</name>
30641                <description>Programmable divider to generated 30MHz UTMI clock from external clk_hf_i source (150MHz). Duty cycle is ((1/divn_value)*100)) percent for the generated clock.
306420x0: Disables the clock.
306430xN: Divide-by-N of clk_hf.</description>
30644                <bitRange>[3:0]</bitRange>
30645                <access>read-write</access>
30646              </field>
30647            </fields>
30648          </register>
30649          <register>
30650            <name>DEV_TIM_T_DETRST_FILT</name>
30651            <description>USB 2.0 Device Init Timing 1 Register</description>
30652            <addressOffset>0x16C</addressOffset>
30653            <size>32</size>
30654            <access>read-write</access>
30655            <resetValue>0x780005A</resetValue>
30656            <resetMask>0xFFFFFFFF</resetMask>
30657            <fields>
30658              <field>
30659                <name>T_DETRST</name>
30660                <description>Programmable value to detect T_DETRST timing parameter for reset detection as governed by USB 2.0 specification. The value ranges from 0x4B to 0x493E0.</description>
30661                <bitRange>[19:0]</bitRange>
30662                <access>read-write</access>
30663              </field>
30664              <field>
30665                <name>T_FILT</name>
30666                <description>Programmable value to detect T_FILT timing parameter for chirp detection as governed by USB 2.0 specification. Supports from 2.5us to 136.5us. The specification does not provide an upper limit for this field.</description>
30667                <bitRange>[31:20]</bitRange>
30668                <access>read-write</access>
30669              </field>
30670            </fields>
30671          </register>
30672          <register>
30673            <name>DEV_TIM_T_WTFS</name>
30674            <description>USB 2.0 Device Init Timing 2 Register</description>
30675            <addressOffset>0x170</addressOffset>
30676            <size>32</size>
30677            <access>read-write</access>
30678            <resetValue>0xEAC4</resetValue>
30679            <resetMask>0x1FFFF</resetMask>
30680            <fields>
30681              <field>
30682                <name>T_WTFS</name>
30683                <description>Programmable value to detect T_WTFS timing parameter to switch to full-speed mode after no chirp is detected during interface reset request. The value ranges from 0x7530 to 0x124F8.</description>
30684                <bitRange>[16:0]</bitRange>
30685                <access>read-write</access>
30686              </field>
30687            </fields>
30688          </register>
30689          <register>
30690            <name>DEV_TIM_T_SUSP</name>
30691            <description>USB 2.0 Device Init Timing 3 Register</description>
30692            <addressOffset>0x174</addressOffset>
30693            <size>32</size>
30694            <access>read-write</access>
30695            <resetValue>0x15FF4</resetValue>
30696            <resetMask>0x1FFFF</resetMask>
30697            <fields>
30698              <field>
30699                <name>T_SUSP</name>
30700                <description>Programmable timing parameter value to detect suspend in full-speed or high-speed mode.</description>
30701                <bitRange>[16:0]</bitRange>
30702                <access>read-write</access>
30703              </field>
30704            </fields>
30705          </register>
30706          <register>
30707            <name>DEV_TIM_T_WTRSTHS</name>
30708            <description>USB 2.0 Device Init Timing 4 Register</description>
30709            <addressOffset>0x178</addressOffset>
30710            <size>32</size>
30711            <access>read-write</access>
30712            <resetValue>0x3A98</resetValue>
30713            <resetMask>0xFFFF</resetMask>
30714            <fields>
30715              <field>
30716                <name>T_WTRSTHS</name>
30717                <description>Programmable timing parameter value. It indicates time a device must wait after reverting to FS before sampling the bus state for SE0. Support values range from 0xBB8 to 0x668A.</description>
30718                <bitRange>[15:0]</bitRange>
30719                <access>read-write</access>
30720              </field>
30721            </fields>
30722          </register>
30723          <register>
30724            <name>DEV_TIM_T_UCH</name>
30725            <description>USB 2.0 Device Init Timing 5 Register</description>
30726            <addressOffset>0x17C</addressOffset>
30727            <size>32</size>
30728            <access>read-write</access>
30729            <resetValue>0xEA60</resetValue>
30730            <resetMask>0x1FFFF</resetMask>
30731            <fields>
30732              <field>
30733                <name>T_UCH</name>
30734                <description>Programmable timing parameter value. It indicates minimum chirp pulse width in a device in SE0. Support values range from 0x7530 to 0x15F90.</description>
30735                <bitRange>[16:0]</bitRange>
30736                <access>read-write</access>
30737              </field>
30738            </fields>
30739          </register>
30740          <register>
30741            <name>DEV_TIM_T_WTREV_WTRSTFS</name>
30742            <description>USB 2.0 Device Init Timing 6 Register</description>
30743            <addressOffset>0x180</addressOffset>
30744            <size>32</size>
30745            <access>read-write</access>
30746            <resetValue>0x15F90</resetValue>
30747            <resetMask>0x1FFFF</resetMask>
30748            <fields>
30749              <field>
30750                <name>T_WTREV_WTRSTFS</name>
30751                <description>Programmable timing parameter value. It indicates minimum chirp pulse width in a device in SE0. Support values range from 0x7530 to 0x15F90.</description>
30752                <bitRange>[16:0]</bitRange>
30753                <access>read-write</access>
30754              </field>
30755            </fields>
30756          </register>
30757          <register>
30758            <name>EPM_CS</name>
30759            <description>EPM Control and Status Register</description>
30760            <addressOffset>0x200</addressOffset>
30761            <size>32</size>
30762            <access>read-write</access>
30763            <resetValue>0x0</resetValue>
30764            <resetMask>0x7</resetMask>
30765            <fields>
30766              <field>
30767                <name>EGRS_FORCE_FLUSH_ALL</name>
30768                <description>1 - Forcefully flushes the Egress SRAM. 0 - Does not flush the Egress SRAM.</description>
30769                <bitRange>[0:0]</bitRange>
30770                <access>read-write</access>
30771              </field>
30772              <field>
30773                <name>IGRS_FORCE_FLUSH_ALL</name>
30774                <description>1 - Forcefully flush the contents in Ingress SRAM. 0 - Does not flush Ingress SRAM.</description>
30775                <bitRange>[1:1]</bitRange>
30776                <access>read-write</access>
30777              </field>
30778              <field>
30779                <name>ALLOW_TRIG_ON_SLP</name>
30780                <description>1 - Allow EPM to send a trigger to DMA when interrupt is cleared by the processor for SLP on ingress path. 0 - Allow processor to send a trigger to DMA for SLP on ingress path</description>
30781                <bitRange>[2:2]</bitRange>
30782                <access>read-write</access>
30783              </field>
30784            </fields>
30785          </register>
30786          <register>
30787            <name>EPM_DEBUG</name>
30788            <description>EPM Debug Register</description>
30789            <addressOffset>0x208</addressOffset>
30790            <size>32</size>
30791            <access>read-only</access>
30792            <resetValue>0x0</resetValue>
30793            <resetMask>0xF3F</resetMask>
30794            <fields>
30795              <field>
30796                <name>C_EPNUM</name>
30797                <description>Indicates the active endpoint for which the transfer is going on in egress path.</description>
30798                <bitRange>[3:0]</bitRange>
30799                <access>read-only</access>
30800              </field>
30801              <field>
30802                <name>C_REQUEST</name>
30803                <description>Indicates current request for active endpoint for which the transfer is going on in egress path.</description>
30804                <bitRange>[5:4]</bitRange>
30805                <access>read-only</access>
30806              </field>
30807              <field>
30808                <name>ACTIVE_EP_NUM</name>
30809                <description>Indicates the active endpoint for which the transfer is going on in ingress path.</description>
30810                <bitRange>[11:8]</bitRange>
30811                <access>read-only</access>
30812              </field>
30813            </fields>
30814          </register>
30815          <register>
30816            <dim>16</dim>
30817            <dimIncrement>4</dimIncrement>
30818            <name>EEPM_ENDPOINT[%s]</name>
30819            <description>Egress EPM per Endpoint Control and Status</description>
30820            <addressOffset>0x220</addressOffset>
30821            <size>32</size>
30822            <access>read-only</access>
30823            <resetValue>0x0</resetValue>
30824            <resetMask>0x3FF</resetMask>
30825            <fields>
30826              <field>
30827                <name>EGRS_SLP_BYTE_COUNT</name>
30828                <description>Number of bytes in short-length packet in the last USB transaction.</description>
30829                <bitRange>[9:0]</bitRange>
30830                <access>read-only</access>
30831              </field>
30832            </fields>
30833          </register>
30834          <register>
30835            <dim>16</dim>
30836            <dimIncrement>4</dimIncrement>
30837            <name>IEPM_ENDPOINT[%s]</name>
30838            <description>Ingress EPM Per Endpoint Control and Status</description>
30839            <addressOffset>0x260</addressOffset>
30840            <size>32</size>
30841            <access>read-only</access>
30842            <resetValue>0x0</resetValue>
30843            <resetMask>0x3FF</resetMask>
30844            <fields>
30845              <field>
30846                <name>INGRS_SLP_BYTE_COUNT</name>
30847                <description>Number of bytes in short-length packet in last USB transaction.</description>
30848                <bitRange>[9:0]</bitRange>
30849                <access>read-only</access>
30850              </field>
30851            </fields>
30852          </register>
30853          <register>
30854            <dim>16</dim>
30855            <dimIncrement>4</dimIncrement>
30856            <name>EEPM_DEBUG_ENDPOINT[%s]</name>
30857            <description>Egress EPM Per Endpoint Debug</description>
30858            <addressOffset>0x2A0</addressOffset>
30859            <size>32</size>
30860            <access>read-only</access>
30861            <resetValue>0x0</resetValue>
30862            <resetMask>0x7</resetMask>
30863            <fields>
30864              <field>
30865                <name>EGRS_P_REQUESTS</name>
30866                <description>Number of pending requests for each endpoint in Egress SRAM. Used for debug only.</description>
30867                <bitRange>[1:0]</bitRange>
30868                <access>read-only</access>
30869              </field>
30870              <field>
30871                <name>EGRS_DMA_TRIGGERED</name>
30872                <description>1 - Egress path sent a trigger to the DMA. 0 - No trigger is sent to the DMA. Used for debug only.</description>
30873                <bitRange>[2:2]</bitRange>
30874                <access>read-only</access>
30875              </field>
30876            </fields>
30877          </register>
30878          <register>
30879            <dim>16</dim>
30880            <dimIncrement>4</dimIncrement>
30881            <name>IEPM_DEBUG_ENDPOINT[%s]</name>
30882            <description>Ingress EPM Per Endpoint Debug</description>
30883            <addressOffset>0x2F0</addressOffset>
30884            <size>32</size>
30885            <access>read-only</access>
30886            <resetValue>0x0</resetValue>
30887            <resetMask>0x1</resetMask>
30888            <fields>
30889              <field>
30890                <name>INGRS_DMA_TRIGGERED</name>
30891                <description>1 - Indicates the DMA was triggered on ingress path. 0 - No trigger sent to DMA on ingress path. Used for debug only.</description>
30892                <bitRange>[0:0]</bitRange>
30893                <access>read-only</access>
30894              </field>
30895            </fields>
30896          </register>
30897        </cluster>
30898        <cluster>
30899          <name>USBHSPHY</name>
30900          <description>USB 2.0 PHY Registers</description>
30901          <addressOffset>0x00000800</addressOffset>
30902          <register>
30903            <name>AFE_CONTROL_1</name>
30904            <description>AFE Control register #1</description>
30905            <addressOffset>0x0</addressOffset>
30906            <size>32</size>
30907            <access>read-write</access>
30908            <resetValue>0x0</resetValue>
30909            <resetMask>0xFFFFFFFF</resetMask>
30910            <fields>
30911              <field>
30912                <name>HS_PRED_DP_SEL</name>
30913                <description>HS PMOS Pre-driver Skew</description>
30914                <bitRange>[1:0]</bitRange>
30915                <access>read-write</access>
30916              </field>
30917              <field>
30918                <name>HS_PRED_DN_SEL</name>
30919                <description>HS NMOS Pre-driver Skew</description>
30920                <bitRange>[3:2]</bitRange>
30921                <access>read-write</access>
30922              </field>
30923              <field>
30924                <name>HS_AMP_SEL</name>
30925                <description>HS Driver Amplitude Control</description>
30926                <bitRange>[7:4]</bitRange>
30927                <access>read-write</access>
30928              </field>
30929              <field>
30930                <name>HS_PREE_SEL</name>
30931                <description>HS Driver Pre-emphasis Amplitude</description>
30932                <bitRange>[10:8]</bitRange>
30933                <access>read-write</access>
30934              </field>
30935              <field>
30936                <name>HS_SR_FINE_SEL</name>
30937                <description>HS Driver Fine Slew Rate Control</description>
30938                <bitRange>[13:11]</bitRange>
30939                <access>read-write</access>
30940              </field>
30941              <field>
30942                <name>HS_TED_LP_MODE</name>
30943                <description>HS TED Low Power Mode
309440: Normal operation
309451: Reduced current mode</description>
30946                <bitRange>[14:14]</bitRange>
30947                <access>read-write</access>
30948              </field>
30949              <field>
30950                <name>EN_LANE_SWAP</name>
30951                <description>The DP/DN pins are swapped on both the transmit and receive direction</description>
30952                <bitRange>[15:15]</bitRange>
30953                <access>read-write</access>
30954              </field>
30955              <field>
30956                <name>HS_CTLE_SEL</name>
30957                <description>HS Receiver CTLE Control</description>
30958                <bitRange>[18:16]</bitRange>
30959                <access>read-write</access>
30960              </field>
30961              <field>
30962                <name>FS_VTRIG_SEL</name>
30963                <description>FS Receiver Trigger Voltage Control</description>
30964                <bitRange>[21:19]</bitRange>
30965                <access>read-write</access>
30966              </field>
30967              <field>
30968                <name>FS_SR_SEL</name>
30969                <description>FS Driver Slew Rate Control</description>
30970                <bitRange>[25:22]</bitRange>
30971                <access>read-write</access>
30972              </field>
30973              <field>
30974                <name>LS_SR_SEL</name>
30975                <description>LS Driver Slew Rate Control</description>
30976                <bitRange>[27:26]</bitRange>
30977                <access>read-write</access>
30978              </field>
30979              <field>
30980                <name>HS_LB_EN</name>
30981                <description>This bit enables the loopback mode.
30982In this mode, the TX can either be looped back at the pads or at the input of the AFE.
30983This is specified by the RX_EN of the AFE.</description>
30984                <bitRange>[28:28]</bitRange>
30985                <access>read-write</access>
30986              </field>
30987              <field>
30988                <name>HS_TED_25_MODE</name>
30989                <description>HS Squelch VDDD Selection bit
309901: VDDD = 3.3V range - DONOT USE THIS SETTING for normal operation
309910: VDDD = 1.8V range</description>
30992                <bitRange>[29:29]</bitRange>
30993                <access>read-write</access>
30994              </field>
30995              <field>
30996                <name>CPU_DELAY_ENABLE_VCCD</name>
30997                <description>INTR0.ENABLE_VCCD indicates that the 2p5 regulator is powered up. FW is required to set this bit after a delay as specified in the AFE requirements</description>
30998                <bitRange>[30:30]</bitRange>
30999                <access>read-write</access>
31000              </field>
31001              <field>
31002                <name>CPU_DELAY_ENABLE_HS_VCCD</name>
31003                <description>INTR0.ENABLE_HS_VCCD indicates that the 1p1 regulator is powere up. FW is required to set this aftera a delay as specifed in the AFE requirements</description>
31004                <bitRange>[31:31]</bitRange>
31005                <access>read-write</access>
31006              </field>
31007            </fields>
31008          </register>
31009          <register>
31010            <name>AFE_CONTROL_2</name>
31011            <description>AFE Control register #2</description>
31012            <addressOffset>0x4</addressOffset>
31013            <size>32</size>
31014            <access>read-write</access>
31015            <resetValue>0x0</resetValue>
31016            <resetMask>0x27FFF</resetMask>
31017            <fields>
31018              <field>
31019                <name>AFE_DFT_SEL</name>
31020                <description>N/A</description>
31021                <bitRange>[9:0]</bitRange>
31022                <access>read-write</access>
31023              </field>
31024              <field>
31025                <name>EUSB_RX_CRUDE_EN</name>
31026                <description>Enables the OVERRIDE function for the eUSB receiver. This bit is used in conjunction with EUSB_RX_MUX_SEL and EUSB_RX_MISSION_EN. When 0, the switching between default and mission mode receiver happens through ENABLE_EUSB_RX</description>
31027                <bitRange>[10:10]</bitRange>
31028                <access>read-write</access>
31029              </field>
31030              <field>
31031                <name>EUSB_RX_MUX_SEL</name>
31032                <description>This bit selects between the default  receiver and mission mode receiver
310330 - Default receiver  selected
310341 - Mission mode receiver selected</description>
31035                <bitRange>[11:11]</bitRange>
31036                <access>read-write</access>
31037              </field>
31038              <field>
31039                <name>EUSB_RX_OVERRIDE</name>
31040                <description>N/A</description>
31041                <bitRange>[12:12]</bitRange>
31042                <access>read-write</access>
31043              </field>
31044              <field>
31045                <name>EUSB_RX_MISSION_EN</name>
31046                <description>This bit enables the default receiver
310470 - mission mode receiver enabled based on se_rx_en. In testmode this can be done by setting ENABLE_EUSB_RX and AFE_CONTROL_3.SE_RX_EN_EDP
310481 - default mode receiver enabled</description>
31049                <bitRange>[13:13]</bitRange>
31050                <access>read-write</access>
31051              </field>
31052              <field>
31053                <name>SE_RX_SE1_FILTER_EN_N</name>
31054                <description>Enable signal for SE1 RX filter, active LOW</description>
31055                <bitRange>[14:14]</bitRange>
31056                <access>read-write</access>
31057              </field>
31058              <field>
31059                <name>ENABLE_EUSB_RX</name>
31060                <description>This bit enabled the mission mode receiver for EUSB. Until this the default crude receiver is ON. This bit must be set after REG_SW_1P2 is turned on and cleared before disabling REG_SW_1P2</description>
31061                <bitRange>[17:17]</bitRange>
31062                <access>read-write</access>
31063              </field>
31064            </fields>
31065          </register>
31066          <register>
31067            <name>UTMI_CONTROL</name>
31068            <description>UTMI Control register</description>
31069            <addressOffset>0x8</addressOffset>
31070            <size>32</size>
31071            <access>read-write</access>
31072            <resetValue>0x55420000</resetValue>
31073            <resetMask>0xFFFFFFFF</resetMask>
31074            <fields>
31075              <field>
31076                <name>SOFT_DISCONNECT_N</name>
31077                <description>1: Connect D+/D Pull downs for DS PHY and Pull-ups for US PHY in Non-Driving Mode indicated by op_mode=01. For test-mode controllability only.</description>
31078                <bitRange>[0:0]</bitRange>
31079                <access>read-write</access>
31080              </field>
31081              <field>
31082                <name>VLOAD</name>
31083                <description>Active Low Signal. On setting this signal to 1, the  VCONTROL values determin the PHY Test modes. To change the testmode this bit has to be cleared and set again.</description>
31084                <bitRange>[1:1]</bitRange>
31085                <access>read-write</access>
31086              </field>
31087              <field>
31088                <name>VCONTROL_TESTCODE</name>
31089                <description>This will contain the TESTCODE PHY during PHY Test modes and BISTMODE for BIST operation.
31090 This value is latched by PHY using VLOAD during Test Modes and  BIST_EN during BIST mode.
31091Refer to the PHY BROS for the Testcodes</description>
31092                <bitRange>[5:2]</bitRange>
31093                <access>read-write</access>
31094              </field>
31095              <field>
31096                <name>VCONTROL_TESTDATA</name>
31097                <description>This will contain the TESTDATA for the PHY during PHY Test modes. This value is latched by PHY using VLOAD during Test Modes and  BIST_EN during BIST mode. Refer to the PHY BROS for the testdata</description>
31098                <bitRange>[9:6]</bitRange>
31099                <access>read-write</access>
31100              </field>
31101              <field>
31102                <name>BIST_EN</name>
31103                <description>Triggers bist operation. VCONTROL values specifies the parameters of bist are latched when this bit is test.</description>
31104                <bitRange>[10:10]</bitRange>
31105                <access>read-write</access>
31106              </field>
31107              <field>
31108                <name>TUNE_BYPASS_EN</name>
31109                <description>1: Bypass calibration for D+ and D- lines</description>
31110                <bitRange>[11:11]</bitRange>
31111                <access>read-write</access>
31112              </field>
31113              <field>
31114                <name>EXT_CAL_VALUE</name>
31115                <description>Apply this value to D+ and D- lines when self calibration is bypassed through CAL_BYPASS_EN=1</description>
31116                <bitRange>[16:12]</bitRange>
31117                <access>read-write</access>
31118              </field>
31119              <field>
31120                <name>OTG_IN_SUSPEND</name>
31121                <description>N/A</description>
31122                <bitRange>[17:17]</bitRange>
31123                <access>read-write</access>
31124              </field>
31125              <field>
31126                <name>BIST_CONTINOUS_EN</name>
31127                <description>1: If BIST_EN is 1, Bist will continue a long pattern specified in BIST_CONTINUOUS_PATTERN until BIST_EN==0.
311280: If BIST_EN is 1, Bist will send one packet.</description>
31129                <bitRange>[18:18]</bitRange>
31130                <access>read-write</access>
31131              </field>
31132              <field>
31133                <name>LINESTATE_COMBO_SEQ</name>
31134                <description>Specifies if the generated linestate is filtered or unfiltered
311350: use combo logic
311361: use sequential logic</description>
31137                <bitRange>[19:19]</bitRange>
31138                <access>read-write</access>
31139              </field>
31140              <field>
31141                <name>LINESTATE_EXT_SEL</name>
31142                <description>Selects where the selection between combo and sequential logic is coming from.
311430: Internal. Done by HW.
311441: from LINE_STATE_COMBO_SEQ</description>
31145                <bitRange>[20:20]</bitRange>
31146                <access>read-write</access>
31147              </field>
31148              <field>
31149                <name>LINESTATE_CLK_SEL</name>
31150                <description>Selects clock input for the linestate module.
311510: selects sieclk
311521: selects clk480m</description>
31153                <bitRange>[21:21]</bitRange>
31154                <access>read-write</access>
31155              </field>
31156              <field>
31157                <name>CAL_BIG_LITTLE_ENDIAN</name>
31158                <description>0: Little endian 5,4,3,2,1,0
311591: Big   endian  0,1,2,3,4,5</description>
31160                <bitRange>[22:22]</bitRange>
31161                <access>read-write</access>
31162              </field>
31163              <field>
31164                <name>BIST_CONTINOUS_PATTERN</name>
31165                <description>Bist pattern sent when BIST_CONTINOUS_EN==1 and BIST_EN==1</description>
31166                <bitRange>[30:23]</bitRange>
31167                <access>read-write</access>
31168              </field>
31169              <field>
31170                <name>REVERT_RPU_CTRL</name>
31171                <description>Setting this bit will revert the RPU control to the old logic used on HX3/Benicia.
311720 - New implementation
311731 - RPU Control not available in Serial Mode of operation</description>
31174                <bitRange>[31:31]</bitRange>
31175                <access>read-write</access>
31176              </field>
31177            </fields>
31178          </register>
31179          <register>
31180            <name>CDR_CONTROL</name>
31181            <description>CDR registers</description>
31182            <addressOffset>0xC</addressOffset>
31183            <size>32</size>
31184            <access>read-write</access>
31185            <resetValue>0x2143</resetValue>
31186            <resetMask>0xFFFF</resetMask>
31187            <fields>
31188              <field>
31189                <name>CONF_EOI_VEC</name>
31190                <description>N/A</description>
31191                <bitRange>[2:0]</bitRange>
31192                <access>read-write</access>
31193              </field>
31194              <field>
31195                <name>CONF_HS_6_SYNC</name>
31196                <description>Enables 6 or 4 bit SYNC detection in HS Serial Interface for PHY
311971: Enables 6 Bit SYNC detection
311980: Enables 4 Bit SYNC detection</description>
31199                <bitRange>[3:3]</bitRange>
31200                <access>read-write</access>
31201              </field>
31202              <field>
31203                <name>EBUF_DEPTH</name>
31204                <description>Specifies the half depth of the elastic buffer.
312050: 13
312061: 12
312072: 14
312083: 15</description>
31209                <bitRange>[5:4]</bitRange>
31210                <access>read-write</access>
31211              </field>
31212              <field>
31213                <name>CDR_CONFIG_1</name>
31214                <description>It specifies the phase offset at which serial data is selected during recovery
312150 : Serial data is captured 3 phases before clkrec.
312161: serial data is captured 2 phasses before clkrec</description>
31217                <bitRange>[6:6]</bitRange>
31218                <access>read-write</access>
31219              </field>
31220              <field>
31221                <name>CDR_ENABLE</name>
31222                <description>0: CDR is kept in reset
312231: CDR is enabled
31224CDR has to be enabled only after the PLL is locked</description>
31225                <bitRange>[7:7]</bitRange>
31226                <access>read-write</access>
31227              </field>
31228              <field>
31229                <name>SQUELCH_FILTER</name>
31230                <description>Squelch Filter specified in terms of 480MHz cycles
312310 - no filtering
312321-5 - 2-6 cycles of filtering</description>
31233                <bitRange>[10:8]</bitRange>
31234                <access>read-write</access>
31235              </field>
31236              <field>
31237                <name>SYNC_MATCH_PATTERN</name>
31238                <description>0: SYNC declared on seeing 3 KJ pairs
312391: SYNC delcared on seeing 2 KJ pairs</description>
31240                <bitRange>[11:11]</bitRange>
31241                <access>read-write</access>
31242              </field>
31243              <field>
31244                <name>GATE_SERIAL_IN_TILL_SQUELCH</name>
31245                <description>0: Data is synchronized in parallel to squelch. Recovered data is qualified by squelch filter
312461: Data input to CDR is qualified by squelch. Introduces delay on the repeater latency path</description>
31247                <bitRange>[12:12]</bitRange>
31248                <access>read-write</access>
31249              </field>
31250              <field>
31251                <name>SERIAL_IN_DELAY</name>
31252                <description>Bits [1:0]Delaying the Serial_in signal in CDR. There is a mismatch of 3 cycles between data and TED on the input to the elasticbuffer. This can be used to delay the data also to the elastic buffer. The squelch filter gates the output of this delay
31253Bit[2] Risk Mitigation for CDR. Will fasten lock time by changing phases once in 2 cycles, instead of once in 3 cycles</description>
31254                <bitRange>[15:13]</bitRange>
31255                <access>read-write</access>
31256              </field>
31257            </fields>
31258          </register>
31259          <register>
31260            <name>BC_CONTROL</name>
31261            <description>UHC Battery Charging CSR Bank</description>
31262            <addressOffset>0x10</addressOffset>
31263            <size>32</size>
31264            <access>read-write</access>
31265            <resetValue>0x0</resetValue>
31266            <resetMask>0x7</resetMask>
31267            <fields>
31268              <field>
31269                <name>CHRGR_DET_ON</name>
31270                <description>1: Power on AFE charger detector circuit</description>
31271                <bitRange>[0:0]</bitRange>
31272                <access>read-write</access>
31273              </field>
31274              <field>
31275                <name>VDM_SRC_EN</name>
31276                <description>1: Enables voltage source on DN pin. If lane swap is enabled, enables voltage source on DP pin</description>
31277                <bitRange>[1:1]</bitRange>
31278                <access>read-write</access>
31279              </field>
31280              <field>
31281                <name>VDP_SRC_EN</name>
31282                <description>1: Enables voltage source on DP pin. If lane swap is enabled, enables voltage source on DN pin</description>
31283                <bitRange>[2:2]</bitRange>
31284                <access>read-write</access>
31285              </field>
31286            </fields>
31287          </register>
31288          <register>
31289            <name>PLL_CONTROL_1</name>
31290            <description>Primary PLL control register#1</description>
31291            <addressOffset>0x14</addressOffset>
31292            <size>32</size>
31293            <access>read-write</access>
31294            <resetValue>0x0</resetValue>
31295            <resetMask>0x3FFFEF7F</resetMask>
31296            <fields>
31297              <field>
31298                <name>RUN_AWAY_DEL</name>
31299                <description>Internal delay from comparator indicate run away to output rise</description>
31300                <bitRange>[1:0]</bitRange>
31301                <access>read-write</access>
31302              </field>
31303              <field>
31304                <name>RUN_AWAY_DIS</name>
31305                <description>Disable run away operation</description>
31306                <bitRange>[2:2]</bitRange>
31307                <access>read-write</access>
31308              </field>
31309              <field>
31310                <name>VCO_GAIN</name>
31311                <description>Gain of the vco circuit</description>
31312                <bitRange>[6:3]</bitRange>
31313                <access>read-write</access>
31314              </field>
31315              <field>
31316                <name>PLL_EN</name>
31317                <description>Enable pll core operation. This bit can only be set after SUPPLY_EN is set. Refer to PLL BROS for further details of startup sequencing</description>
31318                <bitRange>[8:8]</bitRange>
31319                <access>read-write</access>
31320              </field>
31321              <field>
31322                <name>SUPPLY_EN</name>
31323                <description>Enable the PLL suply</description>
31324                <bitRange>[9:9]</bitRange>
31325                <access>read-write</access>
31326              </field>
31327              <field>
31328                <name>LD_DELAY</name>
31329                <description>Lock window adjust</description>
31330                <bitRange>[11:10]</bitRange>
31331                <access>read-write</access>
31332              </field>
31333              <field>
31334                <name>LDO_VCO_BYPASS</name>
31335                <description>Bypass LDO operation - PLL core operate from vccd</description>
31336                <bitRange>[13:13]</bitRange>
31337                <access>read-write</access>
31338              </field>
31339              <field>
31340                <name>P_DIV</name>
31341                <description>Feedback divider - division</description>
31342                <bitRange>[15:14]</bitRange>
31343                <access>read-write</access>
31344              </field>
31345              <field>
31346                <name>Q_DIV</name>
31347                <description>Input divider division</description>
31348                <bitRange>[17:16]</bitRange>
31349                <access>read-write</access>
31350              </field>
31351              <field>
31352                <name>PLL_SPARE</name>
31353                <description>Spare bit for future use</description>
31354                <bitRange>[18:18]</bitRange>
31355                <access>read-write</access>
31356              </field>
31357              <field>
31358                <name>VCO_INIT_DIS</name>
31359                <description>Bypass core LDO</description>
31360                <bitRange>[19:19]</bitRange>
31361                <access>read-write</access>
31362              </field>
31363              <field>
31364                <name>ATST_SEL</name>
31365                <description>Test mode bits</description>
31366                <bitRange>[23:20]</bitRange>
31367                <access>read-write</access>
31368              </field>
31369              <field>
31370                <name>CAL_UP_DN</name>
31371                <description>Trim for up/dn calibration mismatch</description>
31372                <bitRange>[27:24]</bitRange>
31373                <access>read-write</access>
31374              </field>
31375              <field>
31376                <name>RA_UP_TR</name>
31377                <description>Trim for run away detector upper level threshold</description>
31378                <bitRange>[29:28]</bitRange>
31379                <access>read-write</access>
31380              </field>
31381            </fields>
31382          </register>
31383          <register>
31384            <name>PLL_CONTROL_2</name>
31385            <description>Primary PLL control register#2</description>
31386            <addressOffset>0x18</addressOffset>
31387            <size>32</size>
31388            <access>read-write</access>
31389            <resetValue>0x2080</resetValue>
31390            <resetMask>0xFE01FFFF</resetMask>
31391            <fields>
31392              <field>
31393                <name>EN_CPU_OVERIDE_PLL_LOCK</name>
31394                <description>Setting this bit will drive the CPU_OVERIDE_PLL_LOCK_VALUE to pll_lock</description>
31395                <bitRange>[0:0]</bitRange>
31396                <access>read-write</access>
31397              </field>
31398              <field>
31399                <name>CPU_OVERIDE_PLL_LOCK_VALUE</name>
31400                <description>Value to driven on pll_lock</description>
31401                <bitRange>[1:1]</bitRange>
31402                <access>read-write</access>
31403              </field>
31404              <field>
31405                <name>SOURCE_OF_PLL_LOCK</name>
31406                <description>Specifies whether the pll_lock towards the logic is filtered version or from the PLL Hard-IP directly
314070: Filter
314081: s40pllusb2</description>
31409                <bitRange>[2:2]</bitRange>
31410                <access>read-write</access>
31411              </field>
31412              <field>
31413                <name>LOCK_DELAY</name>
31414                <description>The output of the PLL lock signal is filtered for #LOCK_DELAY of refclk. The PLL lock signal must be high for # of LOCK_DELAY before declaring LOCKED.  Once the PLL lock signal is high, the internal counter for lock detection restarts.
31415This register should be programmed when PLL_CONTROL.PLL_EN is 0.</description>
31416                <bitRange>[10:3]</bitRange>
31417                <access>read-write</access>
31418              </field>
31419              <field>
31420                <name>LOSS_LOCK_DELAY</name>
31421                <description>The output of the PLL lock signal is filtered for #LOSS_LOCK_DELAY of refclk. The PLL lock signal must be low for # of LOSS_LOCK_DELAY before declaring UNLOCKED.  Once the PLL lock signal is low, the internal counter for lock loss detection restarts.
31422This register should be programmed when PLL_CONTROL.PLL_EN is 0.</description>
31423                <bitRange>[15:11]</bitRange>
31424                <access>read-write</access>
31425              </field>
31426              <field>
31427                <name>JITTER_TEST_MODE</name>
31428                <description>Setting this bit will put the PHY that has the PLL inJitter measurement mode. In this mode a 240MHz signal generated on p0 is output through the HS transmitter. The References required for HS and the PLL should be enabled before setting this bit</description>
31429                <bitRange>[16:16]</bitRange>
31430                <access>read-write</access>
31431              </field>
31432              <field>
31433                <name>DIV_VALUE</name>
31434                <description>This register is used to divide the selected PLL output phase (Per PLL_CLKOUT_DDFT_SEL) for observing on DDFT</description>
31435                <bitRange>[28:25]</bitRange>
31436                <access>read-write</access>
31437              </field>
31438              <field>
31439                <name>PLL_CLKOUT_DDFT_SEL</name>
31440                <description>The selected PLL output will be divided by DIV_VALUE and routed to IP DDFT mux.
31441DDFT selection:
314420: p0
314431: p45
314442: p90
314453: p135
314464: p180
314475: p225
314486: p270
314497: p315</description>
31450                <bitRange>[31:29]</bitRange>
31451                <access>read-write</access>
31452              </field>
31453            </fields>
31454          </register>
31455          <register>
31456            <name>TEST_PLL_CONTROL</name>
31457            <description>Test PLL control register</description>
31458            <addressOffset>0x1C</addressOffset>
31459            <size>32</size>
31460            <access>read-write</access>
31461            <resetValue>0x0</resetValue>
31462            <resetMask>0xFFFFEF7F</resetMask>
31463            <fields>
31464              <field>
31465                <name>RUN_AWAY_DEL</name>
31466                <description>Internal delay from comparator indicate run away to signal rise</description>
31467                <bitRange>[1:0]</bitRange>
31468                <access>read-write</access>
31469              </field>
31470              <field>
31471                <name>RUN_AWAY_DIS</name>
31472                <description>Disable run away operation</description>
31473                <bitRange>[2:2]</bitRange>
31474                <access>read-write</access>
31475              </field>
31476              <field>
31477                <name>VCO_GAIN</name>
31478                <description>Gain of the vco circuit</description>
31479                <bitRange>[6:3]</bitRange>
31480                <access>read-write</access>
31481              </field>
31482              <field>
31483                <name>PLL_EN</name>
31484                <description>Enable pll core operation</description>
31485                <bitRange>[8:8]</bitRange>
31486                <access>read-write</access>
31487              </field>
31488              <field>
31489                <name>SUPPLY_EN</name>
31490                <description>Enable the PLL suply</description>
31491                <bitRange>[9:9]</bitRange>
31492                <access>read-write</access>
31493              </field>
31494              <field>
31495                <name>LD_DELAY</name>
31496                <description>Lock window adjust</description>
31497                <bitRange>[11:10]</bitRange>
31498                <access>read-write</access>
31499              </field>
31500              <field>
31501                <name>LDO_VCO_BYPASS</name>
31502                <description>Bypass LDO operation - PLL core operate from vccd</description>
31503                <bitRange>[13:13]</bitRange>
31504                <access>read-write</access>
31505              </field>
31506              <field>
31507                <name>P_DIV</name>
31508                <description>Feedback divider - division</description>
31509                <bitRange>[15:14]</bitRange>
31510                <access>read-write</access>
31511              </field>
31512              <field>
31513                <name>Q_DIV</name>
31514                <description>Input divider division</description>
31515                <bitRange>[17:16]</bitRange>
31516                <access>read-write</access>
31517              </field>
31518              <field>
31519                <name>PLL_SPARE</name>
31520                <description>N/A</description>
31521                <bitRange>[18:18]</bitRange>
31522                <access>read-write</access>
31523              </field>
31524              <field>
31525                <name>VCO_INIT_DIS</name>
31526                <description>Bypass core LDO</description>
31527                <bitRange>[19:19]</bitRange>
31528                <access>read-write</access>
31529              </field>
31530              <field>
31531                <name>ATST_SEL</name>
31532                <description>Test mode bits</description>
31533                <bitRange>[23:20]</bitRange>
31534                <access>read-write</access>
31535              </field>
31536              <field>
31537                <name>CAL_UP_DN</name>
31538                <description>Trim for up/dn calibration mismatch</description>
31539                <bitRange>[27:24]</bitRange>
31540                <access>read-write</access>
31541              </field>
31542              <field>
31543                <name>RA_UP_TR</name>
31544                <description>Trim for run away detector upper level threshold</description>
31545                <bitRange>[29:28]</bitRange>
31546                <access>read-write</access>
31547              </field>
31548              <field>
31549                <name>TEST_LOCK_DELAY</name>
31550                <description>The output of the PLL lock signal is filtered for # of LOCK_DELAY. The PLL lock signal must be high for # of LOCK_DELAY before declaring LOCKED.  Once the PLL lock signal is low, the internal counter for lock detection restarts.
31551This register should be programmed when TEST_PLL_CONTROL.PLL_EN is 0.
315520: 16 REFCLK
315531: 32 REFCLK
315542: 64 REFCLK
315553: 128 REFCLK</description>
31556                <bitRange>[31:30]</bitRange>
31557                <access>read-write</access>
31558              </field>
31559            </fields>
31560          </register>
31561          <register>
31562            <name>TEST_CONTROL</name>
31563            <description>Test control register</description>
31564            <addressOffset>0x20</addressOffset>
31565            <size>32</size>
31566            <access>read-write</access>
31567            <resetValue>0x0</resetValue>
31568            <resetMask>0x3F</resetMask>
31569            <fields>
31570              <field>
31571                <name>RUN_CALIBRATION</name>
31572                <description>Test mode trigger to run calibration</description>
31573                <bitRange>[0:0]</bitRange>
31574                <access>read-write</access>
31575              </field>
31576              <field>
31577                <name>CALIBRATED_VALUE</name>
31578                <description>Calibration value from calibration logic</description>
31579                <bitRange>[5:1]</bitRange>
31580                <access>read-only</access>
31581              </field>
31582            </fields>
31583          </register>
31584          <register>
31585            <name>DDFT_CFG</name>
31586            <description>DDFT configuration</description>
31587            <addressOffset>0x24</addressOffset>
31588            <size>32</size>
31589            <access>read-write</access>
31590            <resetValue>0x0</resetValue>
31591            <resetMask>0xFFFF</resetMask>
31592            <fields>
31593              <field>
31594                <name>DDFT0_SEL</name>
31595                <description>77                       controlled_oncal,
3159676                        controlled_cal_f1,
3159775                       controlled_cal_f2,
3159874                        controlled_hs_pree_en,
3159973                        controlled_conn_rpu1,
3160072                        controlled_conn_rpu2,
3160171                        controlled_hs_ded_en,
3160270                       controlled_hs_ded_reset,
3160369                        controlled_hs_ded_start,
3160468                       controlled_rpu_sel,
3160567                        controlled_ls_nfs,
3160666                       controlled_lsfs_diff_rx_en,
3160765                        controlled_conn_rpd_dp,
3160864                        controlled_conn_rpd_dn,
3160963                        controlled_iref_en,
3161062                        controlled_hs_rx_en,
3161161                        controlled_hs_rx_buf_on,
3161260                        controlled_hs_ted_en,
3161359                        controlled_hs_tx_en_slow,
3161458                        controlled_se_rx_en_dp,
3161557                        controlled_se_rx_en_dn,
3161656                        controlled_lfs_tx_en,
3161755                        controlled_lfs_tx_in,
3161854                        controlled_lfs_tx_on,
3161953                        controlled_enase0,
3162052                        eusb_onlfsserec,
3162151                       controlled_enase1,
3162250                        controlled_se_tx_in_edn,
3162349                        controlled_se_tx_en_edn,
3162448:47                       increase_ted_threshold[1:0],
3162546                        irefgen_bypass_mode,
3162645 PLL_SUPPLY_EN
3162744 PLL_EN
3162843 AFE hs_ted_out
3162942 AFE cal_out
3163041 AFE se_rx_out_dn/se_rx_out_edn
3163140  AFE se_rx_out_dp/se_rx_out_edp
3163239  AFE hs_rx_out
3163338 AFE hs_ded_out
3163437 AFE lsfs_diff_rx_out
3163536 AFE stress_out
3163635 s40usb2afe_reg_2p5.ok_v25_vccd
3163734 s40usb2afe_reg_1p1.ok_vhs_vccd
3163833 0
3163932: PLL clockoutput per PLL_CONTROL2.PLL_CLKOUT_DDFT_SEL
3164031: reg_sw_1p2_control_enable_lv,
3164130: reg_2p5_control_enable_lv,
3164229: vrefgen_control_enable_lv
3164328: regulator_1p1_enable
3164427: irefgen_enable
3164526:19: lbstatus
3164618:11: vstatustester
3164710:   intr0_cause_bistdone_done
316489:   intr0_cause_pll_run_away_sticky_change_done
316498:   intr0_cause_test_pll_run_away_sticky_change_done
316507:   0
316516:   0
316525:   test_pll_lock
316534:   pll_lock
316543:   test_pll_dft
316552:   pll_dft
316561:0:   afe_ddft</description>
31657                <bitRange>[6:0]</bitRange>
31658                <access>read-write</access>
31659              </field>
31660              <field>
31661                <name>DDFT0_POLARITY</name>
31662                <description>0 - Observed DDFT output is not inverted
316631 - DDFT output is inverted</description>
31664                <bitRange>[7:7]</bitRange>
31665                <access>read-write</access>
31666              </field>
31667              <field>
31668                <name>DDFT1_SEL</name>
31669                <description>77                       controlled_oncal,
3167076                        controlled_cal_f1,
3167175                       controlled_cal_f2,
3167274                        controlled_hs_pree_en,
3167373                        controlled_conn_rpu1,
3167472                        controlled_conn_rpu2,
3167571                        controlled_hs_ded_en,
3167670                       controlled_hs_ded_reset,
3167769                        controlled_hs_ded_start,
3167868                       controlled_rpu_sel,
3167967                        controlled_ls_nfs,
3168066                       controlled_lsfs_diff_rx_en,
3168165                        controlled_conn_rpd_dp,
3168264                        controlled_conn_rpd_dn,
3168363                        controlled_iref_en,
3168462                        controlled_hs_rx_en,
3168561                        controlled_hs_rx_buf_on,
3168660                        controlled_hs_ted_en,
3168759                        controlled_hs_tx_en_slow,
3168858                        controlled_se_rx_en_dp,
3168957                        controlled_se_rx_en_dn,
3169056                        controlled_lfs_tx_en,
3169155                        controlled_lfs_tx_in,
3169254                        controlled_lfs_tx_on,
3169353                        controlled_enase0,
3169452                        eusb_onlfsserec,
3169551                       controlled_enase1,
3169650                        controlled_se_tx_in_edn,
3169749                        controlled_se_tx_en_edn,
3169848:47                       increase_ted_threshold[1:0],
3169946                        irefgen_bypass_mode,
3170045 PLL_SUPPLY_EN
3170144 PLL_EN
3170243 AFE hs_ted_out
3170342 AFE cal_out
3170441 AFE se_rx_out_dn/se_rx_out_edn
3170540  AFE se_rx_out_dp/se_rx_out_edp
3170639  AFE hs_rx_out
3170738 AFE hs_ded_out
3170837 AFE lsfs_diff_rx_out
3170936 AFE stress_out
3171035 s40usb2afe_reg_2p5.ok_v25_vccd
3171134 s40usb2afe_reg_1p1.ok_vhs_vccd
3171233 0
3171332: PLL clockoutput per PLL_CONTROL2.PLL_CLKOUT_DDFT_SEL
3171431: reg_sw_1p2_control_enable_lv,
3171530: reg_2p5_control_enable_lv,
3171629: vrefgen_control_enable_lv
3171728: regulator_1p1_enable
3171827: irefgen_enable
3171926:19: lbstatus
3172018:11: vstatustester
3172110:   intr0_cause_bistdone_done
317229:   intr0_cause_pll_run_away_sticky_change_done
317238:   intr0_cause_test_pll_run_away_sticky_change_done
317247:   0
317256:   0
317265:   test_pll_lock
317274:   pll_lock
317283:   test_pll_dft
317292:   pll_dft
317301:0:   afe_ddft</description>
31731                <bitRange>[14:8]</bitRange>
31732                <access>read-write</access>
31733              </field>
31734              <field>
31735                <name>DDFT1_POLARITY</name>
31736                <description>0 - Observed DDFT output is not inverted
317371 - DDFT output is inverted</description>
31738                <bitRange>[15:15]</bitRange>
31739                <access>read-write</access>
31740              </field>
31741            </fields>
31742          </register>
31743          <register>
31744            <name>DIGITAL_CONTROL</name>
31745            <description>Provides control and configuration to digital blocks</description>
31746            <addressOffset>0x28</addressOffset>
31747            <size>32</size>
31748            <access>read-write</access>
31749            <resetValue>0x120</resetValue>
31750            <resetMask>0xEFFF7FEF</resetMask>
31751            <fields>
31752              <field>
31753                <name>DLAUNCH_SEL</name>
31754                <description>selects pre-emphasis phase
317550: Pre-emphasis disabled
317561: pll phase 2
317572: pll phase 4
317583: pll phase 6</description>
31759                <bitRange>[1:0]</bitRange>
31760                <access>read-write</access>
31761              </field>
31762              <field>
31763                <name>TX_CLOCK_SOURCE_DFT</name>
31764                <description>Selects the source of TX clock.
317650: TX clock source is the Primary of primary PLL,
317661: TX clock source is the test PLL
31767This bit should be set when loopback is enabled if the CDR is to be validated</description>
31768                <bitRange>[2:2]</bitRange>
31769                <access>read-write</access>
31770              </field>
31771              <field>
31772                <name>CLK480_PHASE_SEL</name>
31773                <description>Selects which phase of PLL to use as the TX clock for the PHY
317740: selects phase 0
317751: selects phase 4</description>
31776                <bitRange>[3:3]</bitRange>
31777                <access>read-write</access>
31778              </field>
31779              <field>
31780                <name>DLAUNCH_ON_DELAY</name>
31781                <description>This field controls the delay from assertion of hs_tx_en_fast to assertion of hs_dum_sr_sel. The actual delay applied is DLAUNCH_ON_DELAY+1</description>
31782                <bitRange>[7:5]</bitRange>
31783                <access>read-write</access>
31784              </field>
31785              <field>
31786                <name>DLAUNCH_OFF_DELAY</name>
31787                <description>N/A</description>
31788                <bitRange>[10:8]</bitRange>
31789                <access>read-write</access>
31790              </field>
31791              <field>
31792                <name>BURN_IN_EN</name>
31793                <description>Enables Burn-in Mode</description>
31794                <bitRange>[11:11]</bitRange>
31795                <access>read-write</access>
31796              </field>
31797              <field>
31798                <name>BURN</name>
31799                <description>2p5 Regulator Burn-in Output Voltage Select</description>
31800                <bitRange>[13:12]</bitRange>
31801                <access>read-write</access>
31802              </field>
31803              <field>
31804                <name>DIS_PRE_EMPHASIS_HS_SOF</name>
31805                <description>Setting this bit to 1 disables the PRE_EMPHASIS during the EOP of an SOF packet. The bit position at which the pre-emphasis is disabled is determined by BIT_TIME_DIS_PRE_EMPHASIS</description>
31806                <bitRange>[14:14]</bitRange>
31807                <access>read-write</access>
31808              </field>
31809              <field>
31810                <name>BIT_TIME_DIS_PRE_EMPHASIS</name>
31811                <description>The 40-bit EOP counter is designed as two counter of 3-bits each to meet 480MHZ timing
31812A 3-bit counter counts every 6 bits and another every 6-bit word (x6)
31813The counters cycle through values as follows 0,4,6,7,3,1 - starting with 0
31814This field specifies the bit position,
31815[21:19] specify the word and [18:16] specify the bit in the word</description>
31816                <bitRange>[21:16]</bitRange>
31817                <access>read-write</access>
31818              </field>
31819              <field>
31820                <name>CONTROL_HS_TX_IN</name>
31821                <description>1: The hs_tx_in_dp/hs_tx_in_dn output ports of D-Launch block
31822     will be driven by the HX_TX_IN_DP_VALUE/HX_TX_IN_DN_VALUE
318230: The hs_tx_in_dp/hs_tx_in_dn will be driven by D-launch logic</description>
31824                <bitRange>[22:22]</bitRange>
31825                <access>read-write</access>
31826              </field>
31827              <field>
31828                <name>HX_TX_IN_DP_VALUE</name>
31829                <description>When CONTROL_HS_TX_IN is set, hs_tx_in_dp output port of D-Launch
31830block is driven by this register, otherwise it is driven by the D-Luanch logic.</description>
31831                <bitRange>[23:23]</bitRange>
31832                <access>read-write</access>
31833              </field>
31834              <field>
31835                <name>HX_TX_IN_DN_VALUE</name>
31836                <description>When CONTROL_HS_TX_IN is set, hs_tx_in_dn output port of D-Launch
31837block is driven by this register, otherwise it is driven by the D-Luanch logic.</description>
31838                <bitRange>[24:24]</bitRange>
31839                <access>read-write</access>
31840              </field>
31841              <field>
31842                <name>CONTROL_HS_TX_PREE</name>
31843                <description>1: The hs_tx_pree_dp/hs_tx_pree_dn output ports of D-Launch block
31844     will be driven by the HX_TX_PREE_DP_VALUE/HX_TX_PREE_DN_VALUE
318450: The hs_tx_pree_dp/hs_tx_pree_dn will be driven by D-launch logic</description>
31846                <bitRange>[25:25]</bitRange>
31847                <access>read-write</access>
31848              </field>
31849              <field>
31850                <name>HX_TX_PREE_DP_VALUE</name>
31851                <description>When CONTROL_HS_TX_PREE is set, hs_tx_pree_dp output port of D-Launch
31852block is driven by this register, otherwise it is driven by the D-Luanch logic.</description>
31853                <bitRange>[26:26]</bitRange>
31854                <access>read-write</access>
31855              </field>
31856              <field>
31857                <name>HX_TX_PREE_DN_VALUE</name>
31858                <description>When CONTROL_HS_TX_PREE is set, hs_tx_pree_dn output port of D-Launch
31859block is driven by this register, otherwise it is driven by the D-Luanch logic.</description>
31860                <bitRange>[27:27]</bitRange>
31861                <access>read-write</access>
31862              </field>
31863              <field>
31864                <name>DISABLE_POWER_SAVING_CDR_CLK480M</name>
31865                <description>This bit disables the dynamic clock gating on CDR clock .</description>
31866                <bitRange>[29:29]</bitRange>
31867                <access>read-write</access>
31868              </field>
31869              <field>
31870                <name>DISABLE_POWER_SAVING_UTMI_HSRX_CLK480M</name>
31871                <description>This bit disables the dynamic clock gating on UTMI RX clock</description>
31872                <bitRange>[30:30]</bitRange>
31873                <access>read-write</access>
31874              </field>
31875              <field>
31876                <name>DISABLE_POWER_SAVING_UTMI_HSTX_CLK480M</name>
31877                <description>This bit disables the dynamic clock gating on UTMI TX clock</description>
31878                <bitRange>[31:31]</bitRange>
31879                <access>read-write</access>
31880              </field>
31881            </fields>
31882          </register>
31883          <register>
31884            <name>VREFGEN_CONTROL</name>
31885            <description>VREFGEN control</description>
31886            <addressOffset>0x2C</addressOffset>
31887            <size>32</size>
31888            <access>read-write</access>
31889            <resetValue>0x0</resetValue>
31890            <resetMask>0x801FFFFF</resetMask>
31891            <fields>
31892              <field>
31893                <name>TED_SEL_0</name>
31894                <description>TED Threshold Select for vref_ted_hi&lt;0&gt;</description>
31895                <bitRange>[3:0]</bitRange>
31896                <access>read-write</access>
31897              </field>
31898              <field>
31899                <name>TED_SEL_1</name>
31900                <description>TED Threshold Select for vref_ted_hi&lt;1&gt;</description>
31901                <bitRange>[7:4]</bitRange>
31902                <access>read-write</access>
31903              </field>
31904              <field>
31905                <name>DED_SEL_0</name>
31906                <description>DED Threshold Select for vref_ded&lt;0&gt;</description>
31907                <bitRange>[11:8]</bitRange>
31908                <access>read-write</access>
31909              </field>
31910              <field>
31911                <name>DED_SEL_1</name>
31912                <description>DED Threshold Select for vref_ded&lt;1&gt;</description>
31913                <bitRange>[15:12]</bitRange>
31914                <access>read-write</access>
31915              </field>
31916              <field>
31917                <name>VREFGEN_ADFT_CTRL</name>
31918                <description>Analog DFT mode slection bits</description>
31919                <bitRange>[19:16]</bitRange>
31920                <access>read-write</access>
31921              </field>
31922              <field>
31923                <name>VREFGEN_ADFT_EN</name>
31924                <description>Analog DFT master enable</description>
31925                <bitRange>[20:20]</bitRange>
31926                <access>read-write</access>
31927              </field>
31928              <field>
31929                <name>ENABLE_LV</name>
31930                <description>Vrefgen block enable</description>
31931                <bitRange>[31:31]</bitRange>
31932                <access>read-write</access>
31933              </field>
31934            </fields>
31935          </register>
31936          <register>
31937            <name>REG_SW_1P2_CONTROL</name>
31938            <description>REG_SW_1P2 control</description>
31939            <addressOffset>0x30</addressOffset>
31940            <size>32</size>
31941            <access>read-write</access>
31942            <resetValue>0x0</resetValue>
31943            <resetMask>0x8000003F</resetMask>
31944            <fields>
31945              <field>
31946                <name>SW_ADFT_CTRL</name>
31947                <description>analog DFT mode slection bits</description>
31948                <bitRange>[3:0]</bitRange>
31949                <access>read-write</access>
31950              </field>
31951              <field>
31952                <name>SW_ADFT_EN</name>
31953                <description>analog DFT master enable</description>
31954                <bitRange>[4:4]</bitRange>
31955                <access>read-write</access>
31956              </field>
31957              <field>
31958                <name>USE_REG</name>
31959                <description>Indicator that selects vout_1p2 driver:
319600: regulator
319611: switch</description>
31962                <bitRange>[5:5]</bitRange>
31963                <access>read-write</access>
31964              </field>
31965              <field>
31966                <name>ENABLE_LV</name>
31967                <description>Regulator block enable</description>
31968                <bitRange>[31:31]</bitRange>
31969                <access>read-write</access>
31970              </field>
31971            </fields>
31972          </register>
31973          <register>
31974            <name>REG_1P1_CONTROL</name>
31975            <description>REG_1P1 control</description>
31976            <addressOffset>0x34</addressOffset>
31977            <size>32</size>
31978            <access>read-write</access>
31979            <resetValue>0x0</resetValue>
31980            <resetMask>0x8000011F</resetMask>
31981            <fields>
31982              <field>
31983                <name>ONEP1_ADFT_CTRL</name>
31984                <description>analog DFT mode slection bits</description>
31985                <bitRange>[3:0]</bitRange>
31986                <access>read-write</access>
31987              </field>
31988              <field>
31989                <name>ONEP1_ADFT_EN</name>
31990                <description>analog DFT master enable</description>
31991                <bitRange>[4:4]</bitRange>
31992                <access>read-write</access>
31993              </field>
31994              <field>
31995                <name>SWITCH_EN</name>
31996                <description>Indicator that selects vout_1p1 driver:
319970: regulator
319981: switch</description>
31999                <bitRange>[8:8]</bitRange>
32000                <access>read-write</access>
32001              </field>
32002              <field>
32003                <name>ENABLE_LV</name>
32004                <description>Regulator block enable</description>
32005                <bitRange>[31:31]</bitRange>
32006                <access>read-write</access>
32007              </field>
32008            </fields>
32009          </register>
32010          <register>
32011            <name>REG_2P5_CONTROL</name>
32012            <description>REG_2P5_ control</description>
32013            <addressOffset>0x38</addressOffset>
32014            <size>32</size>
32015            <access>read-write</access>
32016            <resetValue>0x0</resetValue>
32017            <resetMask>0x8000011F</resetMask>
32018            <fields>
32019              <field>
32020                <name>TWOP5_ADFT_CTRL</name>
32021                <description>analog DFT mode slection bits</description>
32022                <bitRange>[3:0]</bitRange>
32023                <access>read-write</access>
32024              </field>
32025              <field>
32026                <name>TWOP5_ADFT_EN</name>
32027                <description>analog DFT master enable</description>
32028                <bitRange>[4:4]</bitRange>
32029                <access>read-write</access>
32030              </field>
32031              <field>
32032                <name>BYPASS_MODE</name>
32033                <description>When set the 2.5V regulator is bypassed to 3V3 supply.This bit has to be set to allow Deepsleep in Suspend mode</description>
32034                <bitRange>[8:8]</bitRange>
32035                <access>read-write</access>
32036              </field>
32037              <field>
32038                <name>ENABLE_LV</name>
32039                <description>Regulator block enable</description>
32040                <bitRange>[31:31]</bitRange>
32041                <access>read-write</access>
32042              </field>
32043            </fields>
32044          </register>
32045          <register>
32046            <name>IREFGEN_CONTROL</name>
32047            <description>IREFGEN_ control</description>
32048            <addressOffset>0x3C</addressOffset>
32049            <size>32</size>
32050            <access>read-write</access>
32051            <resetValue>0x0</resetValue>
32052            <resetMask>0x8000011F</resetMask>
32053            <fields>
32054              <field>
32055                <name>IREF_ADFT_CTRL</name>
32056                <description>analog DFT mode slection bits</description>
32057                <bitRange>[3:0]</bitRange>
32058                <access>read-write</access>
32059              </field>
32060              <field>
32061                <name>IREF_ADFT_EN</name>
32062                <description>analog DFT master enable</description>
32063                <bitRange>[4:4]</bitRange>
32064                <access>read-write</access>
32065              </field>
32066              <field>
32067                <name>BYPASS_MODE</name>
32068                <description>When set vref/iref to PLL is generated from 3.3 supply and not SRSS vref.
32069Forced to 1 in SCAN_TDF mode</description>
32070                <bitRange>[8:8]</bitRange>
32071                <access>read-write</access>
32072              </field>
32073              <field>
32074                <name>ENABLE_LV</name>
32075                <description>Irefgen block enable</description>
32076                <bitRange>[31:31]</bitRange>
32077                <access>read-write</access>
32078              </field>
32079            </fields>
32080          </register>
32081          <register>
32082            <name>STATUS</name>
32083            <description>Status</description>
32084            <addressOffset>0x40</addressOffset>
32085            <size>32</size>
32086            <access>read-only</access>
32087            <resetValue>0x0</resetValue>
32088            <resetMask>0x7FFFFFD</resetMask>
32089            <fields>
32090              <field>
32091                <name>PLL_LOCK</name>
32092                <description>Live status of pll.pll_lock</description>
32093                <bitRange>[0:0]</bitRange>
32094                <access>read-only</access>
32095              </field>
32096              <field>
32097                <name>TEST_PLL_LOCK</name>
32098                <description>Live status of test_pll.pll_lock</description>
32099                <bitRange>[2:2]</bitRange>
32100                <access>read-only</access>
32101              </field>
32102              <field>
32103                <name>VSTATUSTESTER</name>
32104                <description>Refer to TEST_CONTROL.VCONTROL</description>
32105                <bitRange>[10:3]</bitRange>
32106                <access>read-only</access>
32107              </field>
32108              <field>
32109                <name>LBSTATUS</name>
32110                <description>17: reginprogress
3211116: error
3211215: startbist
3211314: bistdone
3211413: txready
3211512: txvalid
3211611: rxactive
3211710: rxerror</description>
32118                <bitRange>[18:11]</bitRange>
32119                <access>read-only</access>
32120              </field>
32121              <field>
32122                <name>LINE_STATE</name>
32123                <description>Current state of single ended D+/D- receivers. Used in production test</description>
32124                <bitRange>[20:19]</bitRange>
32125                <access>read-only</access>
32126              </field>
32127              <field>
32128                <name>HOST_DISCONNECT</name>
32129                <description>Indicates Peripheral disconnect detection. Only valid if dppulldown and dmpulldown signals are '1'. In UHC, all the DS Ports dppulldown and dmpulldown are tied to '1'. Hence this bit is valid only for DS ports and invalid for US port. So named to keep UTMO spec compatibility, should have been named DEVICE_DISCONNECT otherwise.
321300: Device Connected
321311: Device Disconnect Detected
32132This signal is the output from the UTMI+ PHY. During reset, the value resets to 0 and reflects the current status of the ports  TDIS ot TCONN after reset is deasserted, typically in 2.5us.</description>
32133                <bitRange>[21:21]</bitRange>
32134                <access>read-only</access>
32135              </field>
32136              <field>
32137                <name>PLL_LOSS_CNT</name>
32138                <description>Count of PLL lossing lock</description>
32139                <bitRange>[25:22]</bitRange>
32140                <access>read-only</access>
32141              </field>
32142              <field>
32143                <name>BISTOK</name>
32144                <description>This bit should be read after INTR0.BISTDONE
321450: BIST failed
321461: BIST passed</description>
32147                <bitRange>[26:26]</bitRange>
32148                <access>read-only</access>
32149              </field>
32150            </fields>
32151          </register>
32152          <register>
32153            <name>INTR0</name>
32154            <description>INTR0 Cause.  These are the wakeup interrupts get reflected on interrupt_wakeup pin.</description>
32155            <addressOffset>0x44</addressOffset>
32156            <size>32</size>
32157            <access>read-write</access>
32158            <resetValue>0x0</resetValue>
32159            <resetMask>0x7FF</resetMask>
32160            <fields>
32161              <field>
32162                <name>PLL_LOCK</name>
32163                <description>PLL is locked</description>
32164                <bitRange>[0:0]</bitRange>
32165                <access>read-write</access>
32166              </field>
32167              <field>
32168                <name>PLL_LOSS</name>
32169                <description>PLL lost lock.</description>
32170                <bitRange>[1:1]</bitRange>
32171                <access>read-write</access>
32172              </field>
32173              <field>
32174                <name>TEST_PLL_LOCK</name>
32175                <description>test_pll.pll_lock</description>
32176                <bitRange>[2:2]</bitRange>
32177                <access>read-write</access>
32178              </field>
32179              <field>
32180                <name>PLL_RUN_AWAY_STICKY_CHANGE</name>
32181                <description>pll.pll_run_away_sticky</description>
32182                <bitRange>[3:3]</bitRange>
32183                <access>read-write</access>
32184              </field>
32185              <field>
32186                <name>TEST_PLL_RUN_AWAY_STICKY_CHANGE</name>
32187                <description>pll.pll_run_away_sticky</description>
32188                <bitRange>[4:4]</bitRange>
32189                <access>read-write</access>
32190              </field>
32191              <field>
32192                <name>ENABLE_VCCD</name>
32193                <description>s40usb2afe_reg_2p5.ok_v25_vccd is detected</description>
32194                <bitRange>[5:5]</bitRange>
32195                <access>read-write</access>
32196              </field>
32197              <field>
32198                <name>ENABLE_HS_VCCD</name>
32199                <description>s40usb2afe_reg_1p1.ok_vhs_vccd is detected</description>
32200                <bitRange>[6:6]</bitRange>
32201                <access>read-write</access>
32202              </field>
32203              <field>
32204                <name>BISTDONE</name>
32205                <description>Bist is done if BIST_CONTINOUS_EN is 0.
32206Status of BIST is BISTOK STATUS register</description>
32207                <bitRange>[7:7]</bitRange>
32208                <access>read-write</access>
32209              </field>
32210              <field>
32211                <name>ERRORFLOW</name>
32212                <description>Elasticity buffer overflow error indicator</description>
32213                <bitRange>[8:8]</bitRange>
32214                <access>read-write</access>
32215              </field>
32216              <field>
32217                <name>STRESS_OUT</name>
32218                <description>Over-voltage stress event detected on the dp or dn pins</description>
32219                <bitRange>[9:9]</bitRange>
32220                <access>read-write</access>
32221              </field>
32222              <field>
32223                <name>CAL_DONE</name>
32224                <description>Calibration Complete</description>
32225                <bitRange>[10:10]</bitRange>
32226                <access>read-write</access>
32227              </field>
32228            </fields>
32229          </register>
32230          <register>
32231            <name>INTR0_SET</name>
32232            <description>INTR0 Set</description>
32233            <addressOffset>0x48</addressOffset>
32234            <size>32</size>
32235            <access>read-write</access>
32236            <resetValue>0x0</resetValue>
32237            <resetMask>0x7FF</resetMask>
32238            <fields>
32239              <field>
32240                <name>PLL_LOCK</name>
32241                <description>Write with '1' to set corresponding bit in interrupt request register.</description>
32242                <bitRange>[0:0]</bitRange>
32243                <access>read-write</access>
32244              </field>
32245              <field>
32246                <name>PLL_LOSS</name>
32247                <description>Write with '1' to set corresponding bit in interrupt request register.</description>
32248                <bitRange>[1:1]</bitRange>
32249                <access>read-write</access>
32250              </field>
32251              <field>
32252                <name>TEST_PLL_LOCK</name>
32253                <description>Write with '1' to set corresponding bit in interrupt request register.</description>
32254                <bitRange>[2:2]</bitRange>
32255                <access>read-write</access>
32256              </field>
32257              <field>
32258                <name>PLL_RUN_AWAY_STICKY_CHANGE</name>
32259                <description>Write with '1' to set corresponding bit in interrupt request register.</description>
32260                <bitRange>[3:3]</bitRange>
32261                <access>read-write</access>
32262              </field>
32263              <field>
32264                <name>TEST_PLL_RUN_AWAY_STICKY_CHANGE</name>
32265                <description>Write with '1' to set corresponding bit in interrupt request register.</description>
32266                <bitRange>[4:4]</bitRange>
32267                <access>read-write</access>
32268              </field>
32269              <field>
32270                <name>ENABLE_VCCD</name>
32271                <description>Write with '1' to set corresponding bit in interrupt request register.</description>
32272                <bitRange>[5:5]</bitRange>
32273                <access>read-write</access>
32274              </field>
32275              <field>
32276                <name>ENABLE_HS_VCCD</name>
32277                <description>Write with '1' to set corresponding bit in interrupt request register.</description>
32278                <bitRange>[6:6]</bitRange>
32279                <access>read-write</access>
32280              </field>
32281              <field>
32282                <name>BISTDONE</name>
32283                <description>Write with '1' to set corresponding bit in interrupt request register.</description>
32284                <bitRange>[7:7]</bitRange>
32285                <access>read-write</access>
32286              </field>
32287              <field>
32288                <name>ERRORFLOW</name>
32289                <description>Write with '1' to set corresponding bit in interrupt request register.</description>
32290                <bitRange>[8:8]</bitRange>
32291                <access>read-write</access>
32292              </field>
32293              <field>
32294                <name>STRESS_OUT</name>
32295                <description>Write with '1' to set corresponding bit in interrupt request register.</description>
32296                <bitRange>[9:9]</bitRange>
32297                <access>read-write</access>
32298              </field>
32299              <field>
32300                <name>CAL_DONE</name>
32301                <description>Write with '1' to set corresponding bit in interrupt request register.</description>
32302                <bitRange>[10:10]</bitRange>
32303                <access>read-write</access>
32304              </field>
32305            </fields>
32306          </register>
32307          <register>
32308            <name>INTR0_MASK</name>
32309            <description>INTR0 Mask</description>
32310            <addressOffset>0x4C</addressOffset>
32311            <size>32</size>
32312            <access>read-write</access>
32313            <resetValue>0x0</resetValue>
32314            <resetMask>0x7FF</resetMask>
32315            <fields>
32316              <field>
32317                <name>PLL_LOCK_MASK</name>
32318                <description>Mask bit for corresponding bit in interrupt request register.</description>
32319                <bitRange>[0:0]</bitRange>
32320                <access>read-write</access>
32321              </field>
32322              <field>
32323                <name>PLL_LOSS_MASK</name>
32324                <description>Mask bit for corresponding bit in interrupt request register.</description>
32325                <bitRange>[1:1]</bitRange>
32326                <access>read-write</access>
32327              </field>
32328              <field>
32329                <name>TEST_PLL_LOCK_MASK</name>
32330                <description>Mask bit for corresponding bit in interrupt request register.</description>
32331                <bitRange>[2:2]</bitRange>
32332                <access>read-write</access>
32333              </field>
32334              <field>
32335                <name>PLL_RUN_AWAY_STICKY_CHANGE_MASK</name>
32336                <description>Mask bit for corresponding bit in interrupt request register.</description>
32337                <bitRange>[3:3]</bitRange>
32338                <access>read-write</access>
32339              </field>
32340              <field>
32341                <name>TEST_PLL_RUN_AWAY_STICKY_CHANGE_MASK</name>
32342                <description>Mask bit for corresponding bit in interrupt request register.</description>
32343                <bitRange>[4:4]</bitRange>
32344                <access>read-write</access>
32345              </field>
32346              <field>
32347                <name>ENABLE_VCCD_MASK</name>
32348                <description>Mask bit for corresponding bit in interrupt request register.</description>
32349                <bitRange>[5:5]</bitRange>
32350                <access>read-write</access>
32351              </field>
32352              <field>
32353                <name>ENABLE_HS_VCCD_MASK</name>
32354                <description>Mask bit for corresponding bit in interrupt request register.</description>
32355                <bitRange>[6:6]</bitRange>
32356                <access>read-write</access>
32357              </field>
32358              <field>
32359                <name>BISTDONE_MASK</name>
32360                <description>Mask bit for corresponding bit in interrupt request register.</description>
32361                <bitRange>[7:7]</bitRange>
32362                <access>read-write</access>
32363              </field>
32364              <field>
32365                <name>ERRORFLOW_MASK</name>
32366                <description>Mask bit for corresponding bit in interrupt request register.</description>
32367                <bitRange>[8:8]</bitRange>
32368                <access>read-write</access>
32369              </field>
32370              <field>
32371                <name>STRESS_OUT_MASK</name>
32372                <description>Mask bit for corresponding bit in interrupt request register.</description>
32373                <bitRange>[9:9]</bitRange>
32374                <access>read-write</access>
32375              </field>
32376              <field>
32377                <name>CAL_DONE_MASK</name>
32378                <description>Mask bit for corresponding bit in interrupt request register.</description>
32379                <bitRange>[10:10]</bitRange>
32380                <access>read-write</access>
32381              </field>
32382            </fields>
32383          </register>
32384          <register>
32385            <name>INTR0_MASKED</name>
32386            <description>INTR0 Masked</description>
32387            <addressOffset>0x50</addressOffset>
32388            <size>32</size>
32389            <access>read-only</access>
32390            <resetValue>0x0</resetValue>
32391            <resetMask>0x7FF</resetMask>
32392            <fields>
32393              <field>
32394                <name>PLL_LOCK_MASKED</name>
32395                <description>Logical and of corresponding request and mask bits.</description>
32396                <bitRange>[0:0]</bitRange>
32397                <access>read-only</access>
32398              </field>
32399              <field>
32400                <name>PLL_LOSS_MASKED</name>
32401                <description>Logical and of corresponding request and mask bits.</description>
32402                <bitRange>[1:1]</bitRange>
32403                <access>read-only</access>
32404              </field>
32405              <field>
32406                <name>TEST_PLL_LOCK_MASKED</name>
32407                <description>Logical and of corresponding request and mask bits.</description>
32408                <bitRange>[2:2]</bitRange>
32409                <access>read-only</access>
32410              </field>
32411              <field>
32412                <name>PLL_RUN_AWAY_STICKY_CHANGE_MASKED</name>
32413                <description>Logical and of corresponding request and mask bits.</description>
32414                <bitRange>[3:3]</bitRange>
32415                <access>read-only</access>
32416              </field>
32417              <field>
32418                <name>TEST_PLL_RUN_AWAY_STICKY_CHANGE_MASKED</name>
32419                <description>Logical and of corresponding request and mask bits.</description>
32420                <bitRange>[4:4]</bitRange>
32421                <access>read-only</access>
32422              </field>
32423              <field>
32424                <name>ENABLE_VCCD_MASKED</name>
32425                <description>Logical and of corresponding request and mask bits.</description>
32426                <bitRange>[5:5]</bitRange>
32427                <access>read-only</access>
32428              </field>
32429              <field>
32430                <name>ENABLE_HS_VCCD_MASKED</name>
32431                <description>Logical and of corresponding request and mask bits.</description>
32432                <bitRange>[6:6]</bitRange>
32433                <access>read-only</access>
32434              </field>
32435              <field>
32436                <name>BISTDONE_MASKED</name>
32437                <description>Logical and of corresponding request and mask bits.</description>
32438                <bitRange>[7:7]</bitRange>
32439                <access>read-only</access>
32440              </field>
32441              <field>
32442                <name>ERRORFLOW_MASKED</name>
32443                <description>Logical and of corresponding request and mask bits.</description>
32444                <bitRange>[8:8]</bitRange>
32445                <access>read-only</access>
32446              </field>
32447              <field>
32448                <name>STRESS_OUT_MASKED</name>
32449                <description>Logical and of corresponding request and mask bits.</description>
32450                <bitRange>[9:9]</bitRange>
32451                <access>read-only</access>
32452              </field>
32453              <field>
32454                <name>CAL_DONE_MASKED</name>
32455                <description>Logical and of corresponding request and mask bits.</description>
32456                <bitRange>[10:10]</bitRange>
32457                <access>read-only</access>
32458              </field>
32459            </fields>
32460          </register>
32461          <register>
32462            <name>SPARE</name>
32463            <description>Spare</description>
32464            <addressOffset>0x54</addressOffset>
32465            <size>32</size>
32466            <access>read-write</access>
32467            <resetValue>0xFF000000</resetValue>
32468            <resetMask>0xFFFFFFFF</resetMask>
32469            <fields>
32470              <field>
32471                <name>DFT</name>
32472                <description>Spare</description>
32473                <bitRange>[11:0]</bitRange>
32474                <access>read-only</access>
32475              </field>
32476              <field>
32477                <name>SPARE0</name>
32478                <description>Spare with default 0</description>
32479                <bitRange>[23:12]</bitRange>
32480                <access>read-write</access>
32481              </field>
32482              <field>
32483                <name>SPARE1</name>
32484                <description>Spare with default 1</description>
32485                <bitRange>[31:24]</bitRange>
32486                <access>read-write</access>
32487              </field>
32488            </fields>
32489          </register>
32490          <register>
32491            <name>AFE_CONTROL_3</name>
32492            <description>AFE Control register #3</description>
32493            <addressOffset>0x58</addressOffset>
32494            <size>32</size>
32495            <access>read-write</access>
32496            <resetValue>0x0</resetValue>
32497            <resetMask>0xFFFFFFFF</resetMask>
32498            <fields>
32499              <field>
32500                <name>CONTROL_CONN_RPD</name>
32501                <description>1: The conn_rpd_dp/conn_rpd_dn input ports of AFE block
32502     will be driven by the CONN_RPD_DP_VALUE/CONN_RPD_DN_VALUE
325030: The conn_rpd_dp/conn_rpd_dn will be driven by logic</description>
32504                <bitRange>[0:0]</bitRange>
32505                <access>read-write</access>
32506              </field>
32507              <field>
32508                <name>CONN_RPD_DP_VALUE</name>
32509                <description>When CONTROL_CONN_RPT is set, conn_rpd_dp input port of AFE block
32510block is driven by this register, otherwise it is driven by logic.</description>
32511                <bitRange>[1:1]</bitRange>
32512                <access>read-write</access>
32513              </field>
32514              <field>
32515                <name>CONN_RPD_DN_VALUE</name>
32516                <description>When CONTROL_CONN_RPT is set, conn_rpd_dn input port of AFE block
32517block is driven by this register, otherwise it is driven by logic.</description>
32518                <bitRange>[2:2]</bitRange>
32519                <access>read-write</access>
32520              </field>
32521              <field>
32522                <name>CONTROL_CONN_RPU</name>
32523                <description>1: The conn_rpu1/conn_rpu2 input ports of AFE block
32524     will be driven by the CONN_RPU1_VALUE/CONN_RPU2_VALUE
325250: The conn_rpu1/conn_rpu2 will be driven by logic</description>
32526                <bitRange>[3:3]</bitRange>
32527                <access>read-write</access>
32528              </field>
32529              <field>
32530                <name>CONN_RPU1_VALUE</name>
32531                <description>When CONTROL_CONN_RPU is set, conn_rpu1 input port of AFE block
32532block is driven by this register, otherwise it is driven by logic.</description>
32533                <bitRange>[4:4]</bitRange>
32534                <access>read-write</access>
32535              </field>
32536              <field>
32537                <name>CONN_RPU2_VALUE</name>
32538                <description>When CONTROL_CONN_RPU is set, conn_rpu2 input port of AFE block
32539block is driven by this register, otherwise it is driven by logic.</description>
32540                <bitRange>[5:5]</bitRange>
32541                <access>read-write</access>
32542              </field>
32543              <field>
32544                <name>CONTROL_HS_DED</name>
32545                <description>1: The hs_ded_en/hs_ded_reset/hs_ded_start input ports of AFE block
32546     will be driven by the HS_DED_EN_VALUE/HS_DED_RESET_VALUE/HS_DED_START_VALUE
325470: The hs_ded_en/hs_ded_reset/hs_ded_start will be driven by logic</description>
32548                <bitRange>[6:6]</bitRange>
32549                <access>read-write</access>
32550              </field>
32551              <field>
32552                <name>HS_DED_EN_VALUE</name>
32553                <description>When CONTROL_HS_DED is set, hs_ded_en input ports of AFE block
32554block is driven by this register, otherwise it is driven by logic.</description>
32555                <bitRange>[7:7]</bitRange>
32556                <access>read-write</access>
32557              </field>
32558              <field>
32559                <name>HS_DED_RESET_VALUE</name>
32560                <description>When CONTROL_HS_DED is set, hs_ded_reset input port of AFE block
32561block is driven by this register, otherwise it is driven by logic.</description>
32562                <bitRange>[8:8]</bitRange>
32563                <access>read-write</access>
32564              </field>
32565              <field>
32566                <name>HS_DED_START_VALUE</name>
32567                <description>When CONTROL_HS_DED is set, chs_ded_start input port of AFE block
32568block is driven by this register, otherwise it is driven by logic.</description>
32569                <bitRange>[9:9]</bitRange>
32570                <access>read-write</access>
32571              </field>
32572              <field>
32573                <name>CONTROL_IREF_EN</name>
32574                <description>1: The iref_en input ports of AFE block will be driven by the IREF_EN_VALUE
325750: The iref_en will be driven by logic</description>
32576                <bitRange>[10:10]</bitRange>
32577                <access>read-write</access>
32578              </field>
32579              <field>
32580                <name>IREF_EN_VALUE</name>
32581                <description>When CONTROL_IREF_EN is set, iref_en input ports of AFE block
32582block is driven by this register, otherwise it is driven by logic.</description>
32583                <bitRange>[11:11]</bitRange>
32584                <access>read-write</access>
32585              </field>
32586              <field>
32587                <name>CONTROL_HS_RX_EN</name>
32588                <description>1: The hs_rx_en input ports of AFE block will be driven by the HS_RX_EN_VALUE
325890: The hs_rx_en will be driven by logic</description>
32590                <bitRange>[12:12]</bitRange>
32591                <access>read-write</access>
32592              </field>
32593              <field>
32594                <name>HS_RX_EN_VALUE</name>
32595                <description>When CONTROL_HS_RX_EN is set, hs_rx_en input ports of AFE block
32596block is driven by this register, otherwise it is driven by logic.</description>
32597                <bitRange>[13:13]</bitRange>
32598                <access>read-write</access>
32599              </field>
32600              <field>
32601                <name>CONTROL_HS_RX_BUF_ON</name>
32602                <description>1: The hs_rx_buf_on input ports of AFE block will be driven by the HS_RX_BUF_ON_VALUE
326030: The hs_rx_buf_on will be driven by logic</description>
32604                <bitRange>[14:14]</bitRange>
32605                <access>read-write</access>
32606              </field>
32607              <field>
32608                <name>HS_RX_BUF_ON_VALUE</name>
32609                <description>When CONTROL_HS_RX_BUF_ON is set, hs_rx_buf_on input ports of AFE block
32610block is driven by this register, otherwise it is driven by logic.</description>
32611                <bitRange>[15:15]</bitRange>
32612                <access>read-write</access>
32613              </field>
32614              <field>
32615                <name>CONTROL_HS_TED_EN</name>
32616                <description>1: The hs_ted_en input ports of AFE block will be driven by the HS_TED_EN_VALUE
326170: The hs_ted_en will be driven by logic</description>
32618                <bitRange>[16:16]</bitRange>
32619                <access>read-write</access>
32620              </field>
32621              <field>
32622                <name>HS_TED_EN_VALUE</name>
32623                <description>When CONTROL_HS_TED_EN is set, hs_ted_en input ports of AFE block
32624block is driven by this register, otherwise it is driven by logic.</description>
32625                <bitRange>[17:17]</bitRange>
32626                <access>read-write</access>
32627              </field>
32628              <field>
32629                <name>CONTROL_HS_TX_EN_SLOW</name>
32630                <description>1: The hs_tx_en_slow input ports of AFE block will be driven by the HS_TX_EN_SLOW_VALUE
326310: The hs_tx_en_slow will be driven by logic</description>
32632                <bitRange>[18:18]</bitRange>
32633                <access>read-write</access>
32634              </field>
32635              <field>
32636                <name>HS_TX_EN_SLOW_VALUE</name>
32637                <description>When CONTROL_HS_TX_EN_SLOW is set, hs_tx_en_slow input ports of AFE block
32638block is driven by this register, otherwise it is driven by logic.</description>
32639                <bitRange>[19:19]</bitRange>
32640                <access>read-write</access>
32641              </field>
32642              <field>
32643                <name>CONTROL_RPU_SEL</name>
32644                <description>1: The rpu_sel input ports of AFE block will be driven by the RPU_SEL_VALUE
326450: The rpu_sel will be driven by logic</description>
32646                <bitRange>[20:20]</bitRange>
32647                <access>read-write</access>
32648              </field>
32649              <field>
32650                <name>RPU_SEL_VALUE</name>
32651                <description>When CONTROL_RPU_SEL is set, rpu_sel input ports of AFE block
32652block is driven by this register, otherwise it is driven by logic.</description>
32653                <bitRange>[21:21]</bitRange>
32654                <access>read-write</access>
32655              </field>
32656              <field>
32657                <name>CONTROL_SE_RX_EN_DP</name>
32658                <description>1: The se_rx_en_dp input ports of AFE block will be driven by the SE_RX_EN_DP_VALUE
326590: The se_rx_en_dp will be driven by logic</description>
32660                <bitRange>[22:22]</bitRange>
32661                <access>read-write</access>
32662              </field>
32663              <field>
32664                <name>SE_RX_EN_DP_VALUE</name>
32665                <description>When CONTROL_SE_RX_EN_DP is set, se_rx_en_dp input ports of AFE block
32666block is driven by this register, otherwise it is driven by logic.</description>
32667                <bitRange>[23:23]</bitRange>
32668                <access>read-write</access>
32669              </field>
32670              <field>
32671                <name>CONTROL_SE_RX_EN_DN</name>
32672                <description>1: The se_rx_en_dn input ports of AFE block will be driven by the SE_RX_EN_DN_VALUE
326730: The se_rx_en_dn will be driven by logic</description>
32674                <bitRange>[24:24]</bitRange>
32675                <access>read-write</access>
32676              </field>
32677              <field>
32678                <name>SE_RX_EN_DN_VALUE</name>
32679                <description>When CONTROL_SE_RX_EN_DN is set, se_rx_en_dn input ports of AFE block
32680block is driven by this register, otherwise it is driven by logic.</description>
32681                <bitRange>[25:25]</bitRange>
32682                <access>read-write</access>
32683              </field>
32684              <field>
32685                <name>CONTROL_LS_NFS</name>
32686                <description>1: The ls_nfs input ports of AFE block will be driven by the LS_NFS_VALUE
326870: The ls_nfs will be driven by logic</description>
32688                <bitRange>[26:26]</bitRange>
32689                <access>read-write</access>
32690              </field>
32691              <field>
32692                <name>LS_NFS_VALUE</name>
32693                <description>When CONTROL_LS_NFS is set, ls_nfs input ports of AFE block
32694block is driven by this register, otherwise it is driven by logic.</description>
32695                <bitRange>[27:27]</bitRange>
32696                <access>read-write</access>
32697              </field>
32698              <field>
32699                <name>CONTROL_LSFS_DIFF_RX_EN</name>
32700                <description>1: The lsfs_diff_rx_en input ports of AFE block will be driven by the LSFS_DIFF_RX_EN_VALUE
327010: The lsfs_diff_rx_en will be driven by logic</description>
32702                <bitRange>[28:28]</bitRange>
32703                <access>read-write</access>
32704              </field>
32705              <field>
32706                <name>LSFS_DIFF_RX_EN_VALUE</name>
32707                <description>When CONTROL_LSFS_DIFF_RX_EN is set, lsfs_diff_rx_en input ports of AFE block
32708block is driven by this register, otherwise it is driven by logic.</description>
32709                <bitRange>[29:29]</bitRange>
32710                <access>read-write</access>
32711              </field>
32712              <field>
32713                <name>CONTROL_LFS_TX_EN</name>
32714                <description>1: The lfs_tx_en input ports of AFE block will be driven by the LFS_TX_EN_VALUE
327150: The lfs_tx_en will be driven by logic</description>
32716                <bitRange>[30:30]</bitRange>
32717                <access>read-write</access>
32718              </field>
32719              <field>
32720                <name>LFS_TX_EN_VALUE</name>
32721                <description>When CONTROL_LFS_TX_EN is set, lfs_tx_en input ports of AFE block
32722block is driven by this register, otherwise it is driven by logic.</description>
32723                <bitRange>[31:31]</bitRange>
32724                <access>read-write</access>
32725              </field>
32726            </fields>
32727          </register>
32728          <register>
32729            <name>AFE_CONTROL_4</name>
32730            <description>AFE Control register #4</description>
32731            <addressOffset>0x5C</addressOffset>
32732            <size>32</size>
32733            <access>read-write</access>
32734            <resetValue>0x0</resetValue>
32735            <resetMask>0xFFFFFFF</resetMask>
32736            <fields>
32737              <field>
32738                <name>CONTROL_LFS_TX_IN</name>
32739                <description>1: The lfs_tx_in input ports of AFE block will be driven by the LFS_TX_IN_VALUE
327400: The lfs_tx_in will be driven by logic</description>
32741                <bitRange>[0:0]</bitRange>
32742                <access>read-write</access>
32743              </field>
32744              <field>
32745                <name>LFS_TX_IN_VALUE</name>
32746                <description>When CONTROL_LFS_TX_IN is set, lfs_tx_in input ports of AFE block
32747block is driven by this register, otherwise it is driven by logic.</description>
32748                <bitRange>[1:1]</bitRange>
32749                <access>read-write</access>
32750              </field>
32751              <field>
32752                <name>CONTROL_LFS_TX_ON</name>
32753                <description>1: The lfs_tx_on input ports of AFE block will be driven by the LFS_TX_ON_VALUE
327540: The lfs_tx_on will be driven by logic</description>
32755                <bitRange>[2:2]</bitRange>
32756                <access>read-write</access>
32757              </field>
32758              <field>
32759                <name>LFS_TX_ON_VALUE</name>
32760                <description>When CONTROL_LFS_TX_ON is set, lfs_tx_on input ports of AFE block
32761block is driven by this register, otherwise it is driven by logic.</description>
32762                <bitRange>[3:3]</bitRange>
32763                <access>read-write</access>
32764              </field>
32765              <field>
32766                <name>CONTROL_ENASE0</name>
32767                <description>1: The enase0 input ports of AFE block will be driven by the ENASE0_VALUE
327680: The enase0 will be driven by logic</description>
32769                <bitRange>[4:4]</bitRange>
32770                <access>read-write</access>
32771              </field>
32772              <field>
32773                <name>ENASE0_VALUE</name>
32774                <description>When CONTROL_ENASE0 is set, enase0 input ports of AFE block
32775block is driven by this register, otherwise it is driven by logic.</description>
32776                <bitRange>[5:5]</bitRange>
32777                <access>read-write</access>
32778              </field>
32779              <field>
32780                <name>CONTROL_ENASE1</name>
32781                <description>1: The enase1 input ports of AFE block will be driven by the ENASE1_VALUE
327820: The enase0 will be driven by logic</description>
32783                <bitRange>[6:6]</bitRange>
32784                <access>read-write</access>
32785              </field>
32786              <field>
32787                <name>ENASE1_VALUE</name>
32788                <description>When CONTROL_ENASE1 is set, enase1 input ports of AFE block
32789block is driven by this register, otherwise it is driven by logic.</description>
32790                <bitRange>[7:7]</bitRange>
32791                <access>read-write</access>
32792              </field>
32793              <field>
32794                <name>CONTROL_CAL</name>
32795                <description>1: The cal/oncal/cal_f1/cal_f2 input ports of AFE block will be driven by the
32796     CAL_VALUE, ONCAL_VALUE, CAL_F1_VALUE, CAL_F2_VALUE
327970: The cal/oncal/cal_f1/cal_f2 will be driven by logic</description>
32798                <bitRange>[8:8]</bitRange>
32799                <access>read-write</access>
32800              </field>
32801              <field>
32802                <name>CAL_VALUE</name>
32803                <description>When CONTROL_CAL is set, cal input ports of AFE block
32804block is driven by this register, otherwise it is driven by logic.</description>
32805                <bitRange>[13:9]</bitRange>
32806                <access>read-write</access>
32807              </field>
32808              <field>
32809                <name>ONCAL_VALUE</name>
32810                <description>When CONTROL_CAL is set, cal input ports of AFE block
32811block is driven by this register, otherwise it is driven by logic.</description>
32812                <bitRange>[14:14]</bitRange>
32813                <access>read-write</access>
32814              </field>
32815              <field>
32816                <name>CAL_F1_VALUE</name>
32817                <description>When CONTROL_CAL is set, cal input ports of AFE block
32818block is driven by this register, otherwise it is driven by logic.</description>
32819                <bitRange>[15:15]</bitRange>
32820                <access>read-write</access>
32821              </field>
32822              <field>
32823                <name>CAL_F2_VALUE</name>
32824                <description>When CONTROL_CAL is set, cal input ports of AFE block
32825block is driven by this register, otherwise it is driven by logic.</description>
32826                <bitRange>[16:16]</bitRange>
32827                <access>read-write</access>
32828              </field>
32829              <field>
32830                <name>CONTROL_SE_TX_IN_EDN</name>
32831                <description>1: The se_tx_in_edn input ports of AFE block will be driven by the SE_TX_IN_EDN_VALUE
328320: The se_tx_in_edn will be driven by logic</description>
32833                <bitRange>[17:17]</bitRange>
32834                <access>read-write</access>
32835              </field>
32836              <field>
32837                <name>SE_TX_IN_EDN_VALUE</name>
32838                <description>When CONTROL_SE_TX_IN_EDN is set, se_tx_in_edn input ports of AFE block
32839block is driven by this register, otherwise it is driven by logic.</description>
32840                <bitRange>[18:18]</bitRange>
32841                <access>read-write</access>
32842              </field>
32843              <field>
32844                <name>CONTROL_SE_TX_EN_EDN</name>
32845                <description>1: The se_tx_en_edn input ports of AFE block will be driven by the SE_TX_EN_EDN_VALUE
328460: The se_tx_en_edn will be driven by logic</description>
32847                <bitRange>[19:19]</bitRange>
32848                <access>read-write</access>
32849              </field>
32850              <field>
32851                <name>SE_TX_EN_EDN_VALUE</name>
32852                <description>When CONTROL_SE_TX_EN_EDN is set, se_tx_en_edn input ports of AFE block
32853block is driven by this register, otherwise it is driven by logic.</description>
32854                <bitRange>[20:20]</bitRange>
32855                <access>read-write</access>
32856              </field>
32857              <field>
32858                <name>CONTROL_HS_PREE_EN</name>
32859                <description>1: The hs_pree_en input ports of AFE block will be driven by the HS_PREE_EN_VALUE
328600: The hs_pree_en will be driven by logic</description>
32861                <bitRange>[21:21]</bitRange>
32862                <access>read-write</access>
32863              </field>
32864              <field>
32865                <name>HS_PREE_EN_VALUE</name>
32866                <description>When CONTROL_HS_PREE_EN is set, hs_pree_en input ports of AFE block
32867block is driven by this register, otherwise it is driven by logic.</description>
32868                <bitRange>[22:22]</bitRange>
32869                <access>read-write</access>
32870              </field>
32871              <field>
32872                <name>CONTROL_HS_TERM_EN</name>
32873                <description>1: hs_term_en input ports of USB2 AFE will be driven by HS_TERM_EN_VALUE
328740:Controlled by logic</description>
32875                <bitRange>[23:23]</bitRange>
32876                <access>read-write</access>
32877              </field>
32878              <field>
32879                <name>HS_TERM_EN_VALUE</name>
32880                <description>When CONTROL.HS_TERM_EN is set, hs_term_en input of USB2 AFE is driven by this register</description>
32881                <bitRange>[24:24]</bitRange>
32882                <access>read-write</access>
32883              </field>
32884              <field>
32885                <name>CONTROL_HS_TX_EN</name>
32886                <description>1: HS Tranmit control signals are generated in dlaunch based on HS_TX_EN_VALUE and HS_TX_EN_FAST_VALUE
328870:Controlled by logic</description>
32888                <bitRange>[25:25]</bitRange>
32889                <access>read-write</access>
32890              </field>
32891              <field>
32892                <name>HS_TX_EN_VALUE</name>
32893                <description>When CONTROL.HS_TX_EN is set, the AFE hs_tx_en_n signal is controlled from this filed through dlaunch</description>
32894                <bitRange>[26:26]</bitRange>
32895                <access>read-write</access>
32896              </field>
32897              <field>
32898                <name>HS_TX_EN_FAST_VALUE</name>
32899                <description>1: *dum* ports of the AFE are controlled in dlaunch through this field
329000:Controlled by logic</description>
32901                <bitRange>[27:27]</bitRange>
32902                <access>read-write</access>
32903              </field>
32904            </fields>
32905          </register>
32906          <register>
32907            <name>UTMI_CONTROL_2</name>
32908            <description>UTMI Configurtation Registers</description>
32909            <addressOffset>0x60</addressOffset>
32910            <size>32</size>
32911            <access>read-write</access>
32912            <resetValue>0x809C21</resetValue>
32913            <resetMask>0xFFFFFF</resetMask>
32914            <fields>
32915              <field>
32916                <name>DED_RESET_ASSERT_X6_BIT</name>
32917                <description>To detect HS disconnect 2 signals reset and start are generated during the 40-bit of the EOP
32918The 40-bit EOP counter is designed as two counter of 3-bits each to meet 480MHZ timing
32919A 3-bit counter counts every 6 bits and another every 6-bit word (x6)
32920The counters cycle through values as follows 0,4,6,7,3,1 - starting with 0
32921This field specifies the word position at which RESET is asserted - currently set to 32nd bit of EOP</description>
32922                <bitRange>[2:0]</bitRange>
32923                <access>read-write</access>
32924              </field>
32925              <field>
32926                <name>DED_RESET_ASSERT_BIT</name>
32927                <description>This filed specifies the bit position at which RESET is asserted - current set to 32nd bit of EOP</description>
32928                <bitRange>[5:3]</bitRange>
32929                <access>read-write</access>
32930              </field>
32931              <field>
32932                <name>DED_RESET_DEASSERT_X6_BIT</name>
32933                <description>This field specifies the word position at which RESET is deasserted - currently set to 39th bit of EOP</description>
32934                <bitRange>[8:6]</bitRange>
32935                <access>read-write</access>
32936              </field>
32937              <field>
32938                <name>DED_RESET_DEASSERT_BIT</name>
32939                <description>This filed specifies the bit position at which RESET is deasserted - current set to 39th bit of EOP</description>
32940                <bitRange>[11:9]</bitRange>
32941                <access>read-write</access>
32942              </field>
32943              <field>
32944                <name>DED_START_ASSERT_X6_BIT</name>
32945                <description>This filed specifies the bit position at which START is asserted - current set to 36th bit of EOP</description>
32946                <bitRange>[14:12]</bitRange>
32947                <access>read-write</access>
32948              </field>
32949              <field>
32950                <name>DED_START_ASSERT_BIT</name>
32951                <description>This filed specifies the bit position at which START is asserted - current set to 36th bit of EOP</description>
32952                <bitRange>[17:15]</bitRange>
32953                <access>read-write</access>
32954              </field>
32955              <field>
32956                <name>DED_START_DEASSERT_X6_BIT</name>
32957                <description>This field specifies the word position at which START is deasserted - currently set to 38th bit of EOP</description>
32958                <bitRange>[20:18]</bitRange>
32959                <access>read-write</access>
32960              </field>
32961              <field>
32962                <name>DED_START_DEASSERT_BIT</name>
32963                <description>This filed specifies the bit position at which START is deasserted - current set to 38th bit of EOP</description>
32964                <bitRange>[23:21]</bitRange>
32965                <access>read-write</access>
32966              </field>
32967            </fields>
32968          </register>
32969          <register>
32970            <name>PLL_TRIMS</name>
32971            <description>Trim register for the PLL</description>
32972            <addressOffset>0xF0</addressOffset>
32973            <size>32</size>
32974            <access>read-write</access>
32975            <resetValue>0x92A4A</resetValue>
32976            <resetMask>0xFFFFF</resetMask>
32977            <fields>
32978              <field>
32979                <name>RUN_AWAY</name>
32980                <description>PLL Run away detector level trim</description>
32981                <bitRange>[1:0]</bitRange>
32982                <access>read-write</access>
32983              </field>
32984              <field>
32985                <name>CP_CUR</name>
32986                <description>PLL Trim option for analog charge pump</description>
32987                <bitRange>[3:2]</bitRange>
32988                <access>read-write</access>
32989              </field>
32990              <field>
32991                <name>LDO_VCO</name>
32992                <description>PLL LDO VCO voltage trim</description>
32993                <bitRange>[6:4]</bitRange>
32994                <access>read-write</access>
32995              </field>
32996              <field>
32997                <name>LDO_CORE</name>
32998                <description>PLL Spare bits - unused</description>
32999                <bitRange>[9:7]</bitRange>
33000                <access>read-write</access>
33001              </field>
33002              <field>
33003                <name>TEST_RUN_AWAY</name>
33004                <description>TEST PLL Run away detector level trim</description>
33005                <bitRange>[11:10]</bitRange>
33006                <access>read-write</access>
33007              </field>
33008              <field>
33009                <name>TEST_CP_CUR</name>
33010                <description>TEST PLL Trim option for analog charge pump</description>
33011                <bitRange>[13:12]</bitRange>
33012                <access>read-write</access>
33013              </field>
33014              <field>
33015                <name>TEST_LDO_VCO</name>
33016                <description>TEST PLL LDO VCO voltage trim</description>
33017                <bitRange>[16:14]</bitRange>
33018                <access>read-write</access>
33019              </field>
33020              <field>
33021                <name>TEST_LDO_CORE</name>
33022                <description>TEST PLL Spare bits - unused</description>
33023                <bitRange>[19:17]</bitRange>
33024                <access>read-write</access>
33025              </field>
33026            </fields>
33027          </register>
33028          <register>
33029            <name>AFE_TRIMS</name>
33030            <description>Trim register for the AFE</description>
33031            <addressOffset>0xF4</addressOffset>
33032            <size>32</size>
33033            <access>read-write</access>
33034            <resetValue>0x0</resetValue>
33035            <resetMask>0x7FFFFFFF</resetMask>
33036            <fields>
33037              <field>
33038                <name>TRIM_VREF</name>
33039                <description>Vrefgen - Trim output reference voltage level</description>
33040                <bitRange>[3:0]</bitRange>
33041                <access>read-write</access>
33042              </field>
33043              <field>
33044                <name>TRIM_IREF</name>
33045                <description>Irefgen - Trim output reference current level</description>
33046                <bitRange>[7:4]</bitRange>
33047                <access>read-write</access>
33048              </field>
33049              <field>
33050                <name>TRIM_VREG_2P5</name>
33051                <description>2p5 Regulator output votlage trim control</description>
33052                <bitRange>[11:8]</bitRange>
33053                <access>read-write</access>
33054              </field>
33055              <field>
33056                <name>TRIM_VREG_1P1</name>
33057                <description>1p1 Regulator output votlage trim control</description>
33058                <bitRange>[15:12]</bitRange>
33059                <access>read-write</access>
33060              </field>
33061              <field>
33062                <name>TRIM_REG_SW_1P2</name>
33063                <description>1p2 Regulator output votlage trim control</description>
33064                <bitRange>[19:16]</bitRange>
33065                <access>read-write</access>
33066              </field>
33067              <field>
33068                <name>TRIM_AFE_HS_IREF</name>
33069                <description>High Speed Transmit Current Source Trim</description>
33070                <bitRange>[22:20]</bitRange>
33071                <access>read-write</access>
33072              </field>
33073              <field>
33074                <name>TRIM_VREF_600M_0</name>
33075                <description>Voltage Select for vref_600m&lt;0&gt;</description>
33076                <bitRange>[26:23]</bitRange>
33077                <access>read-write</access>
33078              </field>
33079              <field>
33080                <name>TRIM_VREF_600M_1</name>
33081                <description>Voltage Select for vref_600m&lt;1&gt;</description>
33082                <bitRange>[30:27]</bitRange>
33083                <access>read-write</access>
33084              </field>
33085            </fields>
33086          </register>
33087        </cluster>
33088      </registers>
33089    </peripheral>
33090    <peripheral>
33091      <name>MAIN_REG</name>
33092      <description>HBWSS Main Registers</description>
33093      <baseAddress>0x40440000</baseAddress>
33094      <addressBlock>
33095        <offset>0</offset>
33096        <size>4096</size>
33097        <usage>registers</usage>
33098      </addressBlock>
33099      <registers>
33100        <register>
33101          <name>CTRL</name>
33102          <description>Main Control Register</description>
33103          <addressOffset>0x0</addressOffset>
33104          <size>32</size>
33105          <access>read-write</access>
33106          <resetValue>0x4</resetValue>
33107          <resetMask>0x80000007</resetMask>
33108          <fields>
33109            <field>
33110              <name>DMA_SRC_SEL</name>
33111              <description>AXI clock select
3311200: 480Mhz from USB2 divided to 320Mhz
3311301: Not used
3311410: 312.5Mhz from USB32
3311511: 100Mhz from System Interface</description>
33116              <bitRange>[1:0]</bitRange>
33117              <access>read-write</access>
33118            </field>
33119            <field>
33120              <name>DMA_DIV2_ENA</name>
33121              <description>Enables div2 of DMA src clock - active high - default enabled</description>
33122              <bitRange>[2:2]</bitRange>
33123              <access>read-write</access>
33124            </field>
33125            <field>
33126              <name>IP_ENABLED</name>
33127              <description>0: IP is disabled, Resets the IP, this reset is an async reset.
331281: IP is enabled.
33129Note that when the IP is disabled, all the interrupt sources are also disabled.
33130All the clocks that their source is clk_hf will be turned off when IP is disabled.</description>
33131              <bitRange>[31:31]</bitRange>
33132              <access>read-write</access>
33133            </field>
33134          </fields>
33135        </register>
33136        <register>
33137          <name>MTRIM</name>
33138          <description>Memory Control Register</description>
33139          <addressOffset>0x4</addressOffset>
33140          <size>32</size>
33141          <access>read-write</access>
33142          <resetValue>0x0</resetValue>
33143          <resetMask>0x73FF</resetMask>
33144          <fields>
33145            <field>
33146              <name>SRAM_RM</name>
33147              <description>SRAM trim bus - match mxsramwrap bit order</description>
33148              <bitRange>[3:0]</bitRange>
33149              <access>read-write</access>
33150            </field>
33151            <field>
33152              <name>SRAM_RME</name>
33153              <description>SRAM trim bus enable</description>
33154              <bitRange>[4:4]</bitRange>
33155              <access>read-write</access>
33156            </field>
33157            <field>
33158              <name>SRAM_WPULSE</name>
33159              <description>SRAM trim bus</description>
33160              <bitRange>[7:5]</bitRange>
33161              <access>read-write</access>
33162            </field>
33163            <field>
33164              <name>SRAM_RA</name>
33165              <description>SRAM trim bus</description>
33166              <bitRange>[9:8]</bitRange>
33167              <access>read-write</access>
33168            </field>
33169            <field>
33170              <name>SRAM_WA</name>
33171              <description>SRAM trim bus</description>
33172              <bitRange>[14:12]</bitRange>
33173              <access>read-write</access>
33174            </field>
33175          </fields>
33176        </register>
33177        <register>
33178          <name>SPCTRL</name>
33179          <description>SRAM Power Control Register</description>
33180          <addressOffset>0x8</addressOffset>
33181          <size>32</size>
33182          <access>read-write</access>
33183          <resetValue>0x960F</resetValue>
33184          <resetMask>0x13FF0F</resetMask>
33185          <fields>
33186            <field>
33187              <name>PWR_MODE_MACRO_0</name>
33188              <description>Power Mode Control for SRAM MACROs 0,1,2,3.  0x3 - Enabled, 0x2 - Retained, 0x1 - Reset, 0x0 - Off</description>
33189              <bitRange>[1:0]</bitRange>
33190              <access>read-write</access>
33191            </field>
33192            <field>
33193              <name>PWR_MODE_MACRO_1</name>
33194              <description>Power Mode Control for SRAM MACROs 4,5,6,7.  0x3 - Enabled, 0x2 - Retained, 0x1 - Reset, 0x0 - Off</description>
33195              <bitRange>[3:2]</bitRange>
33196              <access>read-write</access>
33197            </field>
33198            <field>
33199              <name>PWRUP_DELAY</name>
33200              <description>Power Up Time</description>
33201              <bitRange>[17:8]</bitRange>
33202              <access>read-write</access>
33203            </field>
33204            <field>
33205              <name>WOUND_BIT</name>
33206              <description>When 1  SRAM MACROs 0,1,2,3 are turned off</description>
33207              <bitRange>[20:20]</bitRange>
33208              <access>read-write</access>
33209            </field>
33210          </fields>
33211        </register>
33212        <register>
33213          <name>TR_CMD</name>
33214          <description>Trigger command</description>
33215          <addressOffset>0x20</addressOffset>
33216          <size>32</size>
33217          <access>read-write</access>
33218          <resetValue>0x0</resetValue>
33219          <resetMask>0xF00000FF</resetMask>
33220          <fields>
33221            <field>
33222              <name>TR_SEL</name>
33223              <description>Specifies the activated trigger when ACTIVATE is '1'. If the specified trigger is not present, the trigger activation has no effect.</description>
33224              <bitRange>[7:0]</bitRange>
33225              <access>read-write</access>
33226            </field>
33227            <field>
33228              <name>TRA_MINTENAB</name>
33229              <description>Trigger Assist logic Master Interrupt Enable</description>
33230              <bitRange>[28:28]</bitRange>
33231              <access>read-write</access>
33232            </field>
33233            <field>
33234              <name>TR_EDGE</name>
33235              <description>Specifies if the activated  trigger is treated as a level sensitive or edge sensitive  trigger.
33236'0': level sensitive. The trigger reflects TR_CMD.ACTIVATE.
33237'1': edge sensitive trigger. The trigger is activated for two clk_peri cycles.</description>
33238              <bitRange>[29:29]</bitRange>
33239              <access>read-write</access>
33240            </field>
33241            <field>
33242              <name>OUT_SEL</name>
33243              <description>Specifies whether trigger activation is for a specific input or output trigger of the trigger multiplexer. Activation of a specific input trigger, will result in activation of all output triggers that have the specific input trigger selected through their TR_OUT_CTL.TR_SEL  field. Activation of a specific output trigger, will result in activation of the specified TR_SEL output trigger only.
33244'0': TR_SEL selection and trigger activation is for an input trigger to the trigger multiplexer.
33245'1': TR_SEL selection and trigger activation is for an output trigger from the trigger multiplexer.
33246
33247Note: this field is not used for trigger 1-to-1 groups.</description>
33248              <bitRange>[30:30]</bitRange>
33249              <access>read-write</access>
33250            </field>
33251            <field>
33252              <name>ACTIVATE</name>
33253              <description>SW sets this field to '1' to activate (set to '1') a trigger as identified by TR_SEL, TR_EDGE and OUT_SEL. HW sets this field to '0' for edge sensitive triggers AFTER the selected trigger is activated for two clk_peri cycles.
33254
33255Note: when ACTIVATE is '1', SW should not modify the other register fields.
33256SW MUST NOT set ACTIVATE bit to '1' while updating the other register bits simultaneously. At first the SW MUST update the other register bits as needed, and then set ACTIVATE to '1' with a new register write.</description>
33257              <bitRange>[31:31]</bitRange>
33258              <access>read-write</access>
33259            </field>
33260          </fields>
33261        </register>
33262        <register>
33263          <name>TRA_CISNP</name>
33264          <description>CDMA input tr_assist snoop mode</description>
33265          <addressOffset>0x24</addressOffset>
33266          <size>32</size>
33267          <access>read-write</access>
33268          <resetValue>0x0</resetValue>
33269          <resetMask>0xFFFFFFFF</resetMask>
33270          <fields>
33271            <field>
33272              <name>ISNP_BITS</name>
33273              <description>Turn on snoop mode per trigger -- used for streaming transfers</description>
33274              <bitRange>[31:0]</bitRange>
33275              <access>read-write</access>
33276            </field>
33277          </fields>
33278        </register>
33279        <register>
33280          <name>TRA_COSNP</name>
33281          <description>CDMA output tr_assist snoop mode</description>
33282          <addressOffset>0x28</addressOffset>
33283          <size>32</size>
33284          <access>read-write</access>
33285          <resetValue>0x0</resetValue>
33286          <resetMask>0xFFFFFFFF</resetMask>
33287          <fields>
33288            <field>
33289              <name>OSNP_BITS</name>
33290              <description>Turn on snoop mode per trigger -- used for streaming transfers</description>
33291              <bitRange>[31:0]</bitRange>
33292              <access>read-write</access>
33293            </field>
33294          </fields>
33295        </register>
33296        <register>
33297          <name>TRA_CI_INTR</name>
33298          <description>CDMA input tr_assist Interrupt Status</description>
33299          <addressOffset>0x30</addressOffset>
33300          <size>32</size>
33301          <access>read-write</access>
33302          <resetValue>0x0</resetValue>
33303          <resetMask>0xFFFFFFFF</resetMask>
33304          <fields>
33305            <field>
33306              <name>IINTR_BITS</name>
33307              <description>Trigger Assist Interrupt per trigger</description>
33308              <bitRange>[31:0]</bitRange>
33309              <access>read-write</access>
33310            </field>
33311          </fields>
33312        </register>
33313        <register>
33314          <name>TRA_CI_INTR_SET</name>
33315          <description>CDMA input tr_assist Interrupt Set</description>
33316          <addressOffset>0x34</addressOffset>
33317          <size>32</size>
33318          <access>read-write</access>
33319          <resetValue>0x0</resetValue>
33320          <resetMask>0xFFFFFFFF</resetMask>
33321          <fields>
33322            <field>
33323              <name>IINTRS_BITS</name>
33324              <description>Trigger Assist Interrupt Set per trigger</description>
33325              <bitRange>[31:0]</bitRange>
33326              <access>read-write</access>
33327            </field>
33328          </fields>
33329        </register>
33330        <register>
33331          <name>TRA_CI_INTR_MASK</name>
33332          <description>CDMA input tr_assist Interrupt Mask</description>
33333          <addressOffset>0x38</addressOffset>
33334          <size>32</size>
33335          <access>read-write</access>
33336          <resetValue>0x0</resetValue>
33337          <resetMask>0xFFFFFFFF</resetMask>
33338          <fields>
33339            <field>
33340              <name>IINTRM_BITS</name>
33341              <description>Trigger Assist Interrupt Mask per trigger</description>
33342              <bitRange>[31:0]</bitRange>
33343              <access>read-write</access>
33344            </field>
33345          </fields>
33346        </register>
33347        <register>
33348          <name>TRA_CI_INTR_MASKED</name>
33349          <description>CDMA input tr_assist Interrupt Masked</description>
33350          <addressOffset>0x3C</addressOffset>
33351          <size>32</size>
33352          <access>read-only</access>
33353          <resetValue>0x0</resetValue>
33354          <resetMask>0xFFFFFFFF</resetMask>
33355          <fields>
33356            <field>
33357              <name>IINTRMD_BITS</name>
33358              <description>Trigger Assist Interrupt Masked per trigger</description>
33359              <bitRange>[31:0]</bitRange>
33360              <access>read-only</access>
33361            </field>
33362          </fields>
33363        </register>
33364        <register>
33365          <name>TRA_CO_INTR</name>
33366          <description>CDMA output tr_assist Interrupt Status</description>
33367          <addressOffset>0x40</addressOffset>
33368          <size>32</size>
33369          <access>read-write</access>
33370          <resetValue>0x0</resetValue>
33371          <resetMask>0xFFFFFFFF</resetMask>
33372          <fields>
33373            <field>
33374              <name>OINTR_BITS</name>
33375              <description>Trigger Assist Interrupt per trigger</description>
33376              <bitRange>[31:0]</bitRange>
33377              <access>read-write</access>
33378            </field>
33379          </fields>
33380        </register>
33381        <register>
33382          <name>TRA_CO_INTR_SET</name>
33383          <description>CDMA output tr_assist Interrupt Set</description>
33384          <addressOffset>0x44</addressOffset>
33385          <size>32</size>
33386          <access>read-write</access>
33387          <resetValue>0x0</resetValue>
33388          <resetMask>0xFFFFFFFF</resetMask>
33389          <fields>
33390            <field>
33391              <name>OINTRS_BITS</name>
33392              <description>Trigger Assist Interrupt Set per trigger</description>
33393              <bitRange>[31:0]</bitRange>
33394              <access>read-write</access>
33395            </field>
33396          </fields>
33397        </register>
33398        <register>
33399          <name>TRA_CO_INTR_MASK</name>
33400          <description>CDMA output tr_assist Interrupt Mask</description>
33401          <addressOffset>0x48</addressOffset>
33402          <size>32</size>
33403          <access>read-write</access>
33404          <resetValue>0x0</resetValue>
33405          <resetMask>0xFFFFFFFF</resetMask>
33406          <fields>
33407            <field>
33408              <name>OINTRM_BITS</name>
33409              <description>Trigger Assist Interrupt Mask per trigger</description>
33410              <bitRange>[31:0]</bitRange>
33411              <access>read-write</access>
33412            </field>
33413          </fields>
33414        </register>
33415        <register>
33416          <name>TRA_CO_INTR_MASKED</name>
33417          <description>CDMA output tr_assist Interrupt Masked</description>
33418          <addressOffset>0x4C</addressOffset>
33419          <size>32</size>
33420          <access>read-only</access>
33421          <resetValue>0x0</resetValue>
33422          <resetMask>0xFFFFFFFF</resetMask>
33423          <fields>
33424            <field>
33425              <name>OINTRMD_BITS</name>
33426              <description>Trigger Assist Interrupt Masked per trigger</description>
33427              <bitRange>[31:0]</bitRange>
33428              <access>read-only</access>
33429            </field>
33430          </fields>
33431        </register>
33432        <cluster>
33433          <name>TR_GR</name>
33434          <description>Trigger group</description>
33435          <addressOffset>0x00000400</addressOffset>
33436          <register>
33437            <dim>96</dim>
33438            <dimIncrement>4</dimIncrement>
33439            <name>TR_CTL[%s]</name>
33440            <description>Trigger control register</description>
33441            <addressOffset>0x20</addressOffset>
33442            <size>32</size>
33443            <access>read-write</access>
33444            <resetValue>0x0</resetValue>
33445            <resetMask>0x13FF</resetMask>
33446            <fields>
33447              <field>
33448                <name>TR_SEL</name>
33449                <description>Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.</description>
33450                <bitRange>[7:0]</bitRange>
33451                <access>read-write</access>
33452              </field>
33453              <field>
33454                <name>TR_INV</name>
33455                <description>Specifies if the output trigger is inverted.</description>
33456                <bitRange>[8:8]</bitRange>
33457                <access>read-write</access>
33458              </field>
33459              <field>
33460                <name>TR_EDGE</name>
33461                <description>Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive  trigger.
33462'0': level sensitive.
33463'1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.</description>
33464                <bitRange>[9:9]</bitRange>
33465                <access>read-write</access>
33466              </field>
33467              <field>
33468                <name>DBG_FREEZE_EN</name>
33469                <description>Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation.</description>
33470                <bitRange>[12:12]</bitRange>
33471                <access>read-write</access>
33472              </field>
33473            </fields>
33474          </register>
33475        </cluster>
33476        <cluster>
33477          <name>TR_ASSIST_GR</name>
33478          <description>Trigger Assist - for CDMA triggers</description>
33479          <addressOffset>0x00000800</addressOffset>
33480          <register>
33481            <dim>32</dim>
33482            <dimIncrement>4</dimIncrement>
33483            <name>TRA_SCK_DSCR[%s]</name>
33484            <description>Trigger Assist current descriptor number register - input</description>
33485            <addressOffset>0x0</addressOffset>
33486            <size>32</size>
33487            <access>read-write</access>
33488            <resetValue>0x0</resetValue>
33489            <resetMask>0x8000FFFF</resetMask>
33490            <fields>
33491              <field>
33492                <name>TR_DSCR_NUMBER</name>
33493                <description>Specifies current dscr number
33494FW init to start of dscr chain
33495tr_assist HW updates on dscr fetch</description>
33496                <bitRange>[15:0]</bitRange>
33497                <access>read-write</access>
33498              </field>
33499              <field>
33500                <name>TR_CONS_PRODN</name>
33501                <description>Specifies if trigger is Consumer or Producer</description>
33502                <bitRange>[31:31]</bitRange>
33503                <access>read-write</access>
33504              </field>
33505            </fields>
33506          </register>
33507          <register>
33508            <dim>32</dim>
33509            <dimIncrement>4</dimIncrement>
33510            <name>TRA_DSCR_SIZE[%s]</name>
33511            <description>Trigger Assist current descriptor size/count/occupied register - input</description>
33512            <addressOffset>0x100</addressOffset>
33513            <size>32</size>
33514            <access>read-write</access>
33515            <resetValue>0x0</resetValue>
33516            <resetMask>0xFFFFFFFF</resetMask>
33517            <fields>
33518              <field>
33519                <name>TR_MARKER</name>
33520                <description>FW use</description>
33521                <bitRange>[0:0]</bitRange>
33522                <access>read-write</access>
33523              </field>
33524              <field>
33525                <name>TR_EOP</name>
33526                <description>EOP indicator</description>
33527                <bitRange>[1:1]</bitRange>
33528                <access>read-write</access>
33529              </field>
33530              <field>
33531                <name>TR_BUFF_ERR</name>
33532                <description>Buffer Error</description>
33533                <bitRange>[2:2]</bitRange>
33534                <access>read-write</access>
33535              </field>
33536              <field>
33537                <name>TR_BUFF_OCCUPIED</name>
33538                <description>Buffer Occupied 1 for Cons, Buffer Empty 0 for Prod</description>
33539                <bitRange>[3:3]</bitRange>
33540                <access>read-write</access>
33541              </field>
33542              <field>
33543                <name>TR_BUFF_SIZE</name>
33544                <description>Specifies buffer size
33545Size in terms of groups of 16 bytes
33546Does this buffer size need byte resolution? Godwin verifies NO</description>
33547                <bitRange>[15:4]</bitRange>
33548                <access>read-write</access>
33549              </field>
33550              <field>
33551                <name>TR_BYTE_COUNT</name>
33552                <description>Byte count of current buffer at event time - not updated during transfer</description>
33553                <bitRange>[31:16]</bitRange>
33554                <access>read-write</access>
33555              </field>
33556            </fields>
33557          </register>
33558          <register>
33559            <dim>32</dim>
33560            <dimIncrement>4</dimIncrement>
33561            <name>TRA_CMD_STAT[%s]</name>
33562            <description>Trigger Assist command and status - input</description>
33563            <addressOffset>0x300</addressOffset>
33564            <size>32</size>
33565            <access>read-write</access>
33566            <resetValue>0x0</resetValue>
33567            <resetMask>0xCFF00000</resetMask>
33568            <fields>
33569              <field>
33570                <name>TRA_STATE</name>
33571                <description>tr_assist internal state</description>
33572                <bitRange>[23:20]</bitRange>
33573                <access>read-only</access>
33574              </field>
33575              <field>
33576                <name>TRA_SNP_MODE</name>
33577                <description>Puts tr_assist logic in snoop mode for this trigger</description>
33578                <bitRange>[24:24]</bitRange>
33579                <access>read-write</access>
33580              </field>
33581              <field>
33582                <name>TRA_NO1STTR</name>
33583                <description>Suppress first trigger event for a transfer</description>
33584                <bitRange>[25:25]</bitRange>
33585                <access>read-write</access>
33586              </field>
33587              <field>
33588                <name>TRA_IN_OUTN</name>
33589                <description>Trigger Registers control - 1 the input trigger - 0 the output trigger</description>
33590                <bitRange>[26:26]</bitRange>
33591                <access>read-write</access>
33592              </field>
33593              <field>
33594                <name>TRA_IS_PROD</name>
33595                <description>1 for trigger muxed to Prod, 0 for trigger muxed to Cons</description>
33596                <bitRange>[27:27]</bitRange>
33597                <access>read-write</access>
33598              </field>
33599              <field>
33600                <name>TRA_GO2MAINST</name>
33601                <description>Atfer FW intervention, write 1 to this cmd bit to enable tr_assist functions again</description>
33602                <bitRange>[30:30]</bitRange>
33603                <access>read-write</access>
33604              </field>
33605              <field>
33606                <name>TRA_INIT_TR</name>
33607                <description>Write 1 to this cmd bit to init the tr_assist logic for this trigger</description>
33608                <bitRange>[31:31]</bitRange>
33609                <access>read-write</access>
33610              </field>
33611            </fields>
33612          </register>
33613        </cluster>
33614      </registers>
33615    </peripheral>
33616    <peripheral>
33617      <name>USB32DEV</name>
33618      <description>USB32 IP Registers</description>
33619      <baseAddress>0x40480000</baseAddress>
33620      <addressBlock>
33621        <offset>0</offset>
33622        <size>196608</size>
33623        <usage>registers</usage>
33624      </addressBlock>
33625      <registers>
33626        <cluster>
33627          <dim>2</dim>
33628          <dimIncrement>196608</dimIncrement>
33629          <name>USB32DEV[%s]</name>
33630          <description>USB32DEV Registers</description>
33631          <addressOffset>0x00000000</addressOffset>
33632          <cluster>
33633            <name>MAIN</name>
33634            <description>USB32 Main Register</description>
33635            <addressOffset>0x00000000</addressOffset>
33636            <register>
33637              <name>CTRL</name>
33638              <description>Main Control Register</description>
33639              <addressOffset>0x0</addressOffset>
33640              <size>32</size>
33641              <access>read-write</access>
33642              <resetValue>0x40</resetValue>
33643              <resetMask>0xE000007F</resetMask>
33644              <fields>
33645                <field>
33646                  <name>SSDEV_ENABLE</name>
33647                  <description>Enables the Super Speed  device function.</description>
33648                  <bitRange>[0:0]</bitRange>
33649                  <access>read-write</access>
33650                </field>
33651                <field>
33652                  <name>LOOPBACK_EN</name>
33653                  <description>TBD: TED</description>
33654                  <bitRange>[1:1]</bitRange>
33655                  <access>read-write</access>
33656                </field>
33657                <field>
33658                  <name>DISABLE_SRAM</name>
33659                  <description>Disable all the SRAMS in this IP</description>
33660                  <bitRange>[2:2]</bitRange>
33661                  <access>read-write</access>
33662                </field>
33663                <field>
33664                  <name>USB2_BUS_RESET</name>
33665                  <description>0: There is no USB2 Bus Reset
336661: There is a   USB2 Bus Reset</description>
33667                  <bitRange>[3:3]</bitRange>
33668                  <access>read-write</access>
33669                </field>
33670                <field>
33671                  <name>CLK_EN</name>
33672                  <description>Steps to enable the Clock for USB3.2 function:
336731: Program CTRL.IP_ENABLED to 1
336742: Program CTRL.CLK_EN to 1 (This will cause the USB3.2 function to use DMA clock)
336753: Program CTRL.SSDEV_ENABLE to 1
336764: Program CTRL.PCLK_SRC to 1 (This will cause the USB3.2 function to use PHY-PCLK)</description>
33677                  <bitRange>[4:4]</bitRange>
33678                  <access>read-write</access>
33679                </field>
33680                <field>
33681                  <name>PCLK_SRC</name>
33682                  <description>Clock source for the USB function:
336830: clk_lf_i (typ 32KHz)
336841: USB3 PHY 312.5/125MHz (Spread Spectrum Clock)
336852: Bus clock (typ 200MHz)
336863: clk_lf_i (typ 32KHz)</description>
33687                  <bitRange>[6:5]</bitRange>
33688                  <access>read-write</access>
33689                </field>
33690                <field>
33691                  <name>SI_MODE</name>
33692                  <description>This register is used to configure how the Egress packets are sent to host in SuperSpeedPlus.
33693This register is not used in Gen1x1. This is mainly used for handling Simultanous-IN.
336940: First-Come/First-Serve:
33695    In this mode, packet are sent to host the same order that the ACK were received for the EPs.
336961: Weight Round-Robin arbitration:
33697   In this mode, the packet are sent to host based on a round-robin function.
33698   The number of packets that can be sent for every arbitation grant for each EP is defined in
33699   Protocol PROT_EPI_ARB_PKT configuration register.</description>
33700                  <bitRange>[29:29]</bitRange>
33701                  <access>read-write</access>
33702                </field>
33703                <field>
33704                  <name>CONFIG_LANE</name>
33705                  <description>Configuration Lane register:
337060: Lane0 is the configuration lane
337071: Lane1 is the configuration lane</description>
33708                  <bitRange>[30:30]</bitRange>
33709                  <access>read-write</access>
33710                </field>
33711                <field>
33712                  <name>IP_ENABLED</name>
33713                  <description>0: IP is disabled, Resets the IP, this reset is an async reset.
337141: IP is enabled.
33715Note that when the IP is disabled, all the interrupt sources are also disabled.
33716All the clocks that their source is clk_hf will be turned off when IP is disabled.</description>
33717                  <bitRange>[31:31]</bitRange>
33718                  <access>read-write</access>
33719                </field>
33720              </fields>
33721            </register>
33722            <register>
33723              <name>INTR</name>
33724              <description>Main Interrupt Register</description>
33725              <addressOffset>0x4</addressOffset>
33726              <size>32</size>
33727              <access>read-write</access>
33728              <resetValue>0x0</resetValue>
33729              <resetMask>0x1F</resetMask>
33730              <fields>
33731                <field>
33732                  <name>LINK</name>
33733                  <description>SuperSpeedPlus Link Controller Interrupt</description>
33734                  <bitRange>[0:0]</bitRange>
33735                  <access>read-write</access>
33736                </field>
33737                <field>
33738                  <name>PROT</name>
33739                  <description>SuperSpeedPlus Protocol Layer Interrupt</description>
33740                  <bitRange>[1:1]</bitRange>
33741                  <access>read-write</access>
33742                </field>
33743                <field>
33744                  <name>PROT_EP</name>
33745                  <description>SuperSpeedPlus Device Endpoint Interrupt</description>
33746                  <bitRange>[2:2]</bitRange>
33747                  <access>read-write</access>
33748                </field>
33749                <field>
33750                  <name>EPM_URUN</name>
33751                  <description>SuperSpeedPlus Egress EPM Interrupt</description>
33752                  <bitRange>[3:3]</bitRange>
33753                  <access>read-write</access>
33754                </field>
33755                <field>
33756                  <name>EPM_URUN_TIMEOUT</name>
33757                  <description>SuperSpeedPlus Egress EPM Interrupt</description>
33758                  <bitRange>[4:4]</bitRange>
33759                  <access>read-write</access>
33760                </field>
33761              </fields>
33762            </register>
33763            <register>
33764              <name>INTR_SET</name>
33765              <description>Main Interrupt Set Register</description>
33766              <addressOffset>0x8</addressOffset>
33767              <size>32</size>
33768              <access>read-write</access>
33769              <resetValue>0x0</resetValue>
33770              <resetMask>0x1F</resetMask>
33771              <fields>
33772                <field>
33773                  <name>LINK</name>
33774                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
33775                  <bitRange>[0:0]</bitRange>
33776                  <access>read-write</access>
33777                </field>
33778                <field>
33779                  <name>PROT</name>
33780                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
33781                  <bitRange>[1:1]</bitRange>
33782                  <access>read-write</access>
33783                </field>
33784                <field>
33785                  <name>PROT_EP</name>
33786                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
33787                  <bitRange>[2:2]</bitRange>
33788                  <access>read-write</access>
33789                </field>
33790                <field>
33791                  <name>EPM_URUN</name>
33792                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
33793                  <bitRange>[3:3]</bitRange>
33794                  <access>read-write</access>
33795                </field>
33796                <field>
33797                  <name>EPM_URUN_TIMEOUT</name>
33798                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
33799                  <bitRange>[4:4]</bitRange>
33800                  <access>read-write</access>
33801                </field>
33802              </fields>
33803            </register>
33804            <register>
33805              <name>INTR_MASK</name>
33806              <description>Main Interrupt Mask Register</description>
33807              <addressOffset>0xC</addressOffset>
33808              <size>32</size>
33809              <access>read-write</access>
33810              <resetValue>0x0</resetValue>
33811              <resetMask>0x1F</resetMask>
33812              <fields>
33813                <field>
33814                  <name>LINK_MASK</name>
33815                  <description>Mask bit for corresponding bit in interrupt request register.</description>
33816                  <bitRange>[0:0]</bitRange>
33817                  <access>read-write</access>
33818                </field>
33819                <field>
33820                  <name>PROT_MASK</name>
33821                  <description>Mask bit for corresponding bit in interrupt request register.</description>
33822                  <bitRange>[1:1]</bitRange>
33823                  <access>read-write</access>
33824                </field>
33825                <field>
33826                  <name>PROT_EP_MASK</name>
33827                  <description>Mask bit for corresponding bit in interrupt request register.</description>
33828                  <bitRange>[2:2]</bitRange>
33829                  <access>read-write</access>
33830                </field>
33831                <field>
33832                  <name>EPM_URUN_MASK</name>
33833                  <description>Mask bit for corresponding bit in interrupt request register.</description>
33834                  <bitRange>[3:3]</bitRange>
33835                  <access>read-write</access>
33836                </field>
33837                <field>
33838                  <name>EPM_URUN_TIMEOUT_MASK</name>
33839                  <description>Mask bit for corresponding bit in interrupt request register.</description>
33840                  <bitRange>[4:4]</bitRange>
33841                  <access>read-write</access>
33842                </field>
33843              </fields>
33844            </register>
33845            <register>
33846              <name>INTR_MASKED</name>
33847              <description>Main Interrupt Masked Register</description>
33848              <addressOffset>0x10</addressOffset>
33849              <size>32</size>
33850              <access>read-only</access>
33851              <resetValue>0x0</resetValue>
33852              <resetMask>0x1F</resetMask>
33853              <fields>
33854                <field>
33855                  <name>LINK_MASKED</name>
33856                  <description>Logical and of corresponding request and mask bits.</description>
33857                  <bitRange>[0:0]</bitRange>
33858                  <access>read-only</access>
33859                </field>
33860                <field>
33861                  <name>PROT_MASKED</name>
33862                  <description>Logical and of corresponding request and mask bits.</description>
33863                  <bitRange>[1:1]</bitRange>
33864                  <access>read-only</access>
33865                </field>
33866                <field>
33867                  <name>PROT_EP_MASKED</name>
33868                  <description>Logical and of corresponding request and mask bits.</description>
33869                  <bitRange>[2:2]</bitRange>
33870                  <access>read-only</access>
33871                </field>
33872                <field>
33873                  <name>EPM_URUN_MASKED</name>
33874                  <description>Logical and of corresponding request and mask bits.</description>
33875                  <bitRange>[3:3]</bitRange>
33876                  <access>read-only</access>
33877                </field>
33878                <field>
33879                  <name>EPM_URUN_TIMEOUT_MASKED</name>
33880                  <description>Logical and of corresponding request and mask bits.</description>
33881                  <bitRange>[4:4]</bitRange>
33882                  <access>read-only</access>
33883                </field>
33884              </fields>
33885            </register>
33886            <register>
33887              <name>DDFT_MUX</name>
33888              <description>DDFT0/1 mux selection Register</description>
33889              <addressOffset>0x14</addressOffset>
33890              <size>32</size>
33891              <access>read-write</access>
33892              <resetValue>0x0</resetValue>
33893              <resetMask>0xFFFF</resetMask>
33894              <fields>
33895                <field>
33896                  <name>DDFT0_SEL</name>
33897                  <description>This register selects the following inputs to be routed to DDFT0.
338980: PHY-SS[0] DDFT0
338991: PHY-SS[0] DDFT1
339002: PHY-SS[1] DDFT0
339013: PHY-SS[1] DDFT1</description>
33902                  <bitRange>[7:0]</bitRange>
33903                  <access>read-write</access>
33904                </field>
33905                <field>
33906                  <name>DDFT1_SEL</name>
33907                  <description>This register selects the following inputs to be routed to DDFT1.
339080: PHY-SS[0] DDFT0
339091: PHY-SS[0] DDFT1
339102: PHY-SS[1] DDFT0
339113: PHY-SS[1] DDFT1</description>
33912                  <bitRange>[15:8]</bitRange>
33913                  <access>read-write</access>
33914                </field>
33915              </fields>
33916            </register>
33917            <register>
33918              <name>GPIO_DDFT_MUX</name>
33919              <description>GPIO DDFT0/1 mux selection Register</description>
33920              <addressOffset>0x18</addressOffset>
33921              <size>32</size>
33922              <access>read-write</access>
33923              <resetValue>0x0</resetValue>
33924              <resetMask>0xFFFF</resetMask>
33925              <fields>
33926                <field>
33927                  <name>DDFT0_SEL</name>
33928                  <description>This register selects the following inputs to be routed to GPIO-DDFT0.
339290: PHY-SS[0] DDFT0
339301: PHY-SS[0] DDFT1
339312: PHY-SS[1] DDFT0
339323: PHY-SS[1] DDFT1</description>
33933                  <bitRange>[7:0]</bitRange>
33934                  <access>read-write</access>
33935                </field>
33936                <field>
33937                  <name>DDFT1_SEL</name>
33938                  <description>This register selects the following inputs to be routed to GPIO-DDFT1.
339390: PHY-SS[0] DDFT0
339401: PHY-SS[0] DDFT1
339412: PHY-SS[1] DDFT0
339423: PHY-SS[1] DDFT1</description>
33943                  <bitRange>[15:8]</bitRange>
33944                  <access>read-write</access>
33945                </field>
33946              </fields>
33947            </register>
33948          </cluster>
33949          <cluster>
33950            <name>EPM</name>
33951            <description>USB32 Controller End Point Manager Registers</description>
33952            <addressOffset>0x00001000</addressOffset>
33953            <register>
33954              <name>EEPM_CS</name>
33955              <description>Egress EPM Retry Buffer Status</description>
33956              <addressOffset>0x0</addressOffset>
33957              <size>32</size>
33958              <access>read-write</access>
33959              <resetValue>0x30000</resetValue>
33960              <resetMask>0xF3FF0000</resetMask>
33961              <fields>
33962                <field>
33963                  <name>URUN_REPAIR_EN</name>
33964                  <description>This bit will repair the EPM whenever there is under run due to SYSTEM EPM will keep on reading the packet from SYSMEM whenever data is ready from SYSMEM. If an under-run occurs, EPM will raise the UIB_INTR.EPM_URUN interrupt.</description>
33965                  <bitRange>[16:16]</bitRange>
33966                  <access>read-write</access>
33967                </field>
33968                <field>
33969                  <name>URUN_REPAIR_TIMEOUT_EN</name>
33970                  <description>If an under run occurs and the URUN_REPAIR_EN is set and this register bit is set, then EPM will start a timmer(16-bit counter). If the repair is not complete after 65535*epm clock, EPM will raise the UIB_INTR.EPM_URUN_TIMEOUT interrupt.</description>
33971                  <bitRange>[17:17]</bitRange>
33972                  <access>read-write</access>
33973                </field>
33974                <field>
33975                  <name>URUN_T1_EP_NUM</name>
33976                  <description>The Type1 End Point that the under-run occurred.</description>
33977                  <bitRange>[21:18]</bitRange>
33978                  <access>read-only</access>
33979                </field>
33980                <field>
33981                  <name>URUN_T2_EP_NUM</name>
33982                  <description>The Type2 End Point that the under-run occurred.</description>
33983                  <bitRange>[25:22]</bitRange>
33984                  <access>read-only</access>
33985                </field>
33986                <field>
33987                  <name>EG_EPNUM</name>
33988                  <description>Active Endpoint Number</description>
33989                  <bitRange>[31:28]</bitRange>
33990                  <access>read-only</access>
33991                </field>
33992              </fields>
33993            </register>
33994            <register>
33995              <name>IEPM_CS</name>
33996              <description>Ingress EPM Control and Status</description>
33997              <addressOffset>0x4</addressOffset>
33998              <size>32</size>
33999              <access>read-write</access>
34000              <resetValue>0x0</resetValue>
34001              <resetMask>0x3FFF0FFF</resetMask>
34002              <fields>
34003                <field>
34004                  <name>READ_PTR</name>
34005                  <description>Number of bytes in packet.</description>
34006                  <bitRange>[11:0]</bitRange>
34007                  <access>read-only</access>
34008                </field>
34009                <field>
34010                  <name>WRITE_PTR</name>
34011                  <description>End of Transfer. Set for short packets.</description>
34012                  <bitRange>[27:16]</bitRange>
34013                  <access>read-only</access>
34014                </field>
34015                <field>
34016                  <name>EPM_FLUSH</name>
34017                  <description>This will flush both the Egress and Ingress EPM.</description>
34018                  <bitRange>[28:28]</bitRange>
34019                  <access>read-write</access>
34020                </field>
34021                <field>
34022                  <name>EPM_MUX_RESET</name>
34023                  <description>This will reset the EPM Mux.</description>
34024                  <bitRange>[29:29]</bitRange>
34025                  <access>read-write</access>
34026                </field>
34027              </fields>
34028            </register>
34029            <register>
34030              <name>IEPM_MULT</name>
34031              <description>Ingress EPM MULT function Control</description>
34032              <addressOffset>0x8</addressOffset>
34033              <size>32</size>
34034              <access>read-write</access>
34035              <resetValue>0x8000</resetValue>
34036              <resetMask>0x3FFFFFF</resetMask>
34037              <fields>
34038                <field>
34039                  <name>MULT_EN</name>
34040                  <description>Mult Enable for EP1-15.</description>
34041                  <bitRange>[14:0]</bitRange>
34042                  <access>read-write</access>
34043                </field>
34044                <field>
34045                  <name>MULT_THRSHOLD</name>
34046                  <description>This field is used to when evaluate the mult signal from ingress adapter.
34047If number of packet space available in the buffer goes down by this field, then
34048mult signal from adapter will be evaluated and if it is set the original buffer space(number of packets) is added to NUM_PACKETS in the IEPM_ENDPOINT register.</description>
34049                  <bitRange>[25:15]</bitRange>
34050                  <access>read-write</access>
34051                </field>
34052              </fields>
34053            </register>
34054            <register>
34055              <dim>16</dim>
34056              <dimIncrement>4</dimIncrement>
34057              <name>EEPM_ENDPOINT[%s]</name>
34058              <description>Egress EPM per Endpoint Control and Status</description>
34059              <addressOffset>0x40</addressOffset>
34060              <size>32</size>
34061              <access>read-write</access>
34062              <resetValue>0x400</resetValue>
34063              <resetMask>0xCFFFFFFF</resetMask>
34064              <fields>
34065                <field>
34066                  <name>PACKET_SIZE</name>
34067                  <description>Maximum packet size for this end-point.  Typically this value is 1024, 512, 64, 1023 (last 2 for USB2 only).</description>
34068                  <bitRange>[10:0]</bitRange>
34069                  <access>read-write</access>
34070                </field>
34071                <field>
34072                  <name>EEPM_BYTE_COUNT</name>
34073                  <description>Number of bytes in the current buffer.</description>
34074                  <bitRange>[26:11]</bitRange>
34075                  <access>read-only</access>
34076                </field>
34077                <field>
34078                  <name>ZLP</name>
34079                  <description>ZLP present in the current buffer</description>
34080                  <bitRange>[27:27]</bitRange>
34081                  <access>read-only</access>
34082                </field>
34083                <field>
34084                  <name>EEPM_EP_READY</name>
34085                  <description>The EPM condition used by USB block.</description>
34086                  <bitRange>[30:30]</bitRange>
34087                  <access>read-only</access>
34088                </field>
34089                <field>
34090                  <name>SOCKET_FLUSH</name>
34091                  <description>This bit will flush the corresponding Socket.</description>
34092                  <bitRange>[31:31]</bitRange>
34093                  <access>read-write</access>
34094                </field>
34095              </fields>
34096            </register>
34097            <register>
34098              <dim>16</dim>
34099              <dimIncrement>4</dimIncrement>
34100              <name>IEPM_ENDPOINT[%s]</name>
34101              <description>Ingress EPM Per Endpoint Control and Status</description>
34102              <addressOffset>0x80</addressOffset>
34103              <size>32</size>
34104              <access>read-write</access>
34105              <resetValue>0x400</resetValue>
34106              <resetMask>0xFF7FFFFF</resetMask>
34107              <fields>
34108                <field>
34109                  <name>PACKET_SIZE</name>
34110                  <description>Maximum packet size for this end-point.  Typically this value is 1024, 512, 64, 1023 (last 2 for USB2 only).</description>
34111                  <bitRange>[10:0]</bitRange>
34112                  <access>read-write</access>
34113                </field>
34114                <field>
34115                  <name>NUM_IN_PACKETS</name>
34116                  <description>Number of packets that are guaranteed to fit in the remaining buffer space of the current and next buffers.  If the computed number of packets available is larger than 16, this number will be assumed to be 16 in the protocol block.</description>
34117                  <bitRange>[21:11]</bitRange>
34118                  <access>read-only</access>
34119                </field>
34120                <field>
34121                  <name>EP_READY</name>
34122                  <description>The EPM condition used by USB block.</description>
34123                  <bitRange>[22:22]</bitRange>
34124                  <access>read-only</access>
34125                </field>
34126                <field>
34127                  <name>ODD_MAX_NUM_PKTS</name>
34128                  <description>Number of odd byte packets that can fit in the DMA buffer. Only valid if ODD_MAX_PKT_SIZE_EN is set.</description>
34129                  <bitRange>[28:24]</bitRange>
34130                  <access>read-write</access>
34131                </field>
34132                <field>
34133                  <name>ODD_MAX_PKT_SIZE_EN</name>
34134                  <description>If this bit is enabled, then at the time of calculation of number of packets space in current DMA buffer, OddMaxNumPkts will over-ride the hardware calculation.</description>
34135                  <bitRange>[29:29]</bitRange>
34136                  <access>read-write</access>
34137                </field>
34138                <field>
34139                  <name>EOT_EOP</name>
34140                  <description>Configure end-of-packet signalling to DMA adapter.
341410: Send EOP at the end of a full packet and EOT for short/zlp packets
341421: Send EOT at the end of every packet
34143Setting this bit to 1 is useful for variable size packet endpoints only.</description>
34144                  <bitRange>[30:30]</bitRange>
34145                  <access>read-write</access>
34146                </field>
34147                <field>
34148                  <name>SOCKET_FLUSH</name>
34149                  <description>This bit will flush the corresponding Socket.</description>
34150                  <bitRange>[31:31]</bitRange>
34151                  <access>read-write</access>
34152                </field>
34153              </fields>
34154            </register>
34155            <register>
34156              <name>IEPM_FIFO</name>
34157              <description>Ingress EPM FIFO Entry</description>
34158              <addressOffset>0xC0</addressOffset>
34159              <size>32</size>
34160              <access>read-only</access>
34161              <resetValue>0x0</resetValue>
34162              <resetMask>0x1FFFF</resetMask>
34163              <fields>
34164                <field>
34165                  <name>BYTES</name>
34166                  <description>Number of bytes in the packet.</description>
34167                  <bitRange>[10:0]</bitRange>
34168                  <access>read-only</access>
34169                </field>
34170                <field>
34171                  <name>EOT</name>
34172                  <description>End of Transfer. Set for by the protocol layer short and zero length packets; forwarded to DMA Adapter.</description>
34173                  <bitRange>[11:11]</bitRange>
34174                  <access>read-only</access>
34175                </field>
34176                <field>
34177                  <name>IN_EPNUM</name>
34178                  <description>Endpoint number for this packet</description>
34179                  <bitRange>[15:12]</bitRange>
34180                  <access>read-only</access>
34181                </field>
34182                <field>
34183                  <name>EP_VALID</name>
34184                  <description>Entry is valid</description>
34185                  <bitRange>[16:16]</bitRange>
34186                  <access>read-only</access>
34187                </field>
34188              </fields>
34189            </register>
34190            <register>
34191              <dim>16</dim>
34192              <dimIncrement>4</dimIncrement>
34193              <name>EEPM_VALID[%s]</name>
34194              <description>Egress EPM Retry Buffer Valid packet</description>
34195              <addressOffset>0xC4</addressOffset>
34196              <size>32</size>
34197              <access>read-only</access>
34198              <resetValue>0x0</resetValue>
34199              <resetMask>0xFFFFFFFF</resetMask>
34200              <fields>
34201                <field>
34202                  <name>TYPE1_VALID_PACKETS</name>
34203                  <description>For Type1 End-Points.
34204Bit vector indicating which of the 16 retry buffer contain a valid packet.
34205In SuperSpeed mode, this buffer functions as a circular buffer trailing packets that can be retried behind the WRITE_PTR.
34206These bits are cleared when the Protocol Layer 'activates' an End Point (as opposed to 'reactivating' it).  In SuperSpeed mode all bits are cleared at once.</description>
34207                  <bitRange>[15:0]</bitRange>
34208                  <access>read-only</access>
34209                </field>
34210                <field>
34211                  <name>TYPE2_VALID_PACKETS</name>
34212                  <description>For Type2 End-Points.
34213Bit vector indicating which of the 16 retry buffer contain a valid packet.
34214In SuperSpeed mode, this buffer functions as a circular buffer trailing packets that can be retried behind the WRITE_PTR.
34215These bits are cleared when the Protocol Layer 'activates' an End Point (as opposed to 'reactivating' it).  In SuperSpeed mode all bits are cleared at once.</description>
34216                  <bitRange>[31:16]</bitRange>
34217                  <access>read-only</access>
34218                </field>
34219              </fields>
34220            </register>
34221            <register>
34222              <dim>16</dim>
34223              <dimIncrement>4</dimIncrement>
34224              <name>EEPM_RETRY_OFFSET[%s]</name>
34225              <description>Egress EPM Retry Buffer EndPoint offset</description>
34226              <addressOffset>0x104</addressOffset>
34227              <size>32</size>
34228              <access>read-write</access>
34229              <resetValue>0x0</resetValue>
34230              <resetMask>0x3FFF</resetMask>
34231              <fields>
34232                <field>
34233                  <name>START_OFFSET</name>
34234                  <description>The Offset is used for Write/Read Address of the 64K Retry-Memory for each End Point.
34235A 64k memory allows retry for 64 packet with size of 1k.
34236The 64k is shared between all the 16 EndPoints.
34237This register is used to indicate where the stating address
34238The offset has to be N*256,  (0&lt;=N&lt;63 ).
34239Note: 4-1K single port sram of 128-bit wide is used to create the 64k memory.
34240Example for calculating the start_offset in decimal:
34241Assume the folloiwng available EndPoint and their MaxBurst size:
34242EP1: EP1-MaxBurst=2
34243EP2: EP2-MaxBurst=5
34244EP3: EP3-MaxBurst=8
34245EP4: EP4-MaxBurst=16
34246Assume the following structure for retry buffer, where EP2 is at the bottom, then EP1, EP4,EP6:
34247EP2: EP2-Start_Offset= 0
34248EP1: EP1-Start_Offset= EP2-Start_Offset+EP2-MaxBurst*256 = 0+256*5 =1280
34249EP4: EP4-Start_offset = EP1-Start_Offset+EP1-MaxBurst*256 = 1280+256*2 =1792
34250EP6: EP6-Start_offset = EP4-Start_Offset+EP4-MaxBurst*256 = 1792+256*16= 5888</description>
34251                  <bitRange>[13:0]</bitRange>
34252                  <access>read-write</access>
34253                </field>
34254              </fields>
34255            </register>
34256          </cluster>
34257          <cluster>
34258            <name>LNK</name>
34259            <description>USB32 SuperSpeedPlus Device Controller Link Layer Registers</description>
34260            <addressOffset>0x00002000</addressOffset>
34261            <register>
34262              <name>LNK_CONF</name>
34263              <description>Link Configuration Register</description>
34264              <addressOffset>0x0</addressOffset>
34265              <size>32</size>
34266              <access>read-write</access>
34267              <resetValue>0xC0005040</resetValue>
34268              <resetMask>0xC000F7C3</resetMask>
34269              <fields>
34270                <field>
34271                  <name>TX_ARBITRATION</name>
34272                  <description>Link Arbitration Scheme
34273    0=Link Commands wins
34274    1=HP wins
34275    2=Round Robin</description>
34276                  <bitRange>[1:0]</bitRange>
34277                  <access>read-write</access>
34278                </field>
34279                <field>
34280                  <name>LCW_IGNORE_RSVD</name>
34281                  <description>N/A</description>
34282                  <bitRange>[6:6]</bitRange>
34283                  <access>read-write</access>
34284                </field>
34285                <field>
34286                  <name>DEBUG_FEATURE_ENABLE</name>
34287                  <description>Enable LNK State Debug Override</description>
34288                  <bitRange>[7:7]</bitRange>
34289                  <access>read-write</access>
34290                </field>
34291                <field>
34292                  <name>FORCE_POWER_PRESENT</name>
34293                  <description>Force PowerPresent from PHY On</description>
34294                  <bitRange>[8:8]</bitRange>
34295                  <access>read-write</access>
34296                </field>
34297                <field>
34298                  <name>LDN_DETECTION</name>
34299                  <description>Enable host LDN detection (see USB ECN#001)</description>
34300                  <bitRange>[9:9]</bitRange>
34301                  <access>read-write</access>
34302                </field>
34303                <field>
34304                  <name>CREDIT_ADV_HOLDOFF</name>
34305                  <description>Hold-off Credit Advertisement until Sequence Number Advertisement Received</description>
34306                  <bitRange>[10:10]</bitRange>
34307                  <access>read-write</access>
34308                </field>
34309                <field>
34310                  <name>EPM_FIRST_DELAY</name>
34311                  <description>Delay sending of first Header in a egress burst in PCLK cycles (125MHz).  This is to give the DMA network time to warmup the data pipeline.</description>
34312                  <bitRange>[15:12]</bitRange>
34313                  <access>read-write</access>
34314                </field>
34315                <field>
34316                  <name>RATE_CONFIG</name>
34317                  <description>Initial rate configuration
343182'b00: Gen1x1
343192'b01: Gen1x2
343202'b10: Gen2x1
343213'b11: Gen2x2</description>
34322                  <bitRange>[31:30]</bitRange>
34323                  <access>read-write</access>
34324                </field>
34325              </fields>
34326            </register>
34327            <register>
34328              <name>LNK_INTR</name>
34329              <description>Link Interrupts</description>
34330              <addressOffset>0x4</addressOffset>
34331              <size>32</size>
34332              <access>read-write</access>
34333              <resetValue>0x0</resetValue>
34334              <resetMask>0x7FFFF</resetMask>
34335              <fields>
34336                <field>
34337                  <name>LTSSM_STATE_CHG</name>
34338                  <description>LTSSM State Change Interrupt</description>
34339                  <bitRange>[0:0]</bitRange>
34340                  <access>read-write</access>
34341                </field>
34342                <field>
34343                  <name>LGOOD</name>
34344                  <description>LGOOD Received Interrupt</description>
34345                  <bitRange>[1:1]</bitRange>
34346                  <access>read-write</access>
34347                </field>
34348                <field>
34349                  <name>LRTY</name>
34350                  <description>LRTY Received Interrupt</description>
34351                  <bitRange>[2:2]</bitRange>
34352                  <access>read-write</access>
34353                </field>
34354                <field>
34355                  <name>LBAD</name>
34356                  <description>LBAD Received Interrupt</description>
34357                  <bitRange>[3:3]</bitRange>
34358                  <access>read-write</access>
34359                </field>
34360                <field>
34361                  <name>LCRD</name>
34362                  <description>LCRD Recevied Interrupt</description>
34363                  <bitRange>[4:4]</bitRange>
34364                  <access>read-write</access>
34365                </field>
34366                <field>
34367                  <name>LGO_U1</name>
34368                  <description>LGO_U1 Received Interrupt</description>
34369                  <bitRange>[5:5]</bitRange>
34370                  <access>read-write</access>
34371                </field>
34372                <field>
34373                  <name>LGO_U2</name>
34374                  <description>LGO_U2 Received Interrupt</description>
34375                  <bitRange>[6:6]</bitRange>
34376                  <access>read-write</access>
34377                </field>
34378                <field>
34379                  <name>LGO_U3</name>
34380                  <description>LGO_U3 Received Interrupt</description>
34381                  <bitRange>[7:7]</bitRange>
34382                  <access>read-write</access>
34383                </field>
34384                <field>
34385                  <name>LAU</name>
34386                  <description>LAU Received Interrupt</description>
34387                  <bitRange>[8:8]</bitRange>
34388                  <access>read-write</access>
34389                </field>
34390                <field>
34391                  <name>LXU</name>
34392                  <description>LXU Received Interrupt</description>
34393                  <bitRange>[9:9]</bitRange>
34394                  <access>read-write</access>
34395                </field>
34396                <field>
34397                  <name>LPMA</name>
34398                  <description>LPMA Received Interrupt</description>
34399                  <bitRange>[10:10]</bitRange>
34400                  <access>read-write</access>
34401                </field>
34402                <field>
34403                  <name>BAD_LCW</name>
34404                  <description>Illegal LCW received (see LNK_CONTROL_WORD for details)</description>
34405                  <bitRange>[11:11]</bitRange>
34406                  <access>read-write</access>
34407                </field>
34408                <field>
34409                  <name>LINK_ERROR</name>
34410                  <description>Link Error Count Threshold Reached</description>
34411                  <bitRange>[12:12]</bitRange>
34412                  <access>read-write</access>
34413                </field>
34414                <field>
34415                  <name>PHY_ERROR</name>
34416                  <description>PHY Error Count Threshold Reached</description>
34417                  <bitRange>[13:13]</bitRange>
34418                  <access>read-write</access>
34419                </field>
34420                <field>
34421                  <name>U2_INACTIVITY_TIMEOUT</name>
34422                  <description>U2 Inactivity Timeout Interrupt</description>
34423                  <bitRange>[14:14]</bitRange>
34424                  <access>read-write</access>
34425                </field>
34426                <field>
34427                  <name>LTSSM_CONNECT</name>
34428                  <description>LTSSM Transition to Polling - indicating successful SuperSpeed far-end receiver termination detection</description>
34429                  <bitRange>[15:15]</bitRange>
34430                  <access>read-write</access>
34431                </field>
34432                <field>
34433                  <name>LTSSM_DISCONNECT</name>
34434                  <description>LTSSM Transitions to SS.Disabled</description>
34435                  <bitRange>[16:16]</bitRange>
34436                  <access>read-write</access>
34437                </field>
34438                <field>
34439                  <name>LTSSM_RESET</name>
34440                  <description>LTSSM Reset Received (Hot or Warm)</description>
34441                  <bitRange>[17:17]</bitRange>
34442                  <access>read-write</access>
34443                </field>
34444                <field>
34445                  <name>DATA_RATE_CHANGE</name>
34446                  <description>Data Rate Changed</description>
34447                  <bitRange>[18:18]</bitRange>
34448                  <access>read-write</access>
34449                </field>
34450              </fields>
34451            </register>
34452            <register>
34453              <name>LNK_INTR_SET</name>
34454              <description>Link Interrupts Set</description>
34455              <addressOffset>0x8</addressOffset>
34456              <size>32</size>
34457              <access>read-write</access>
34458              <resetValue>0x0</resetValue>
34459              <resetMask>0x7FFFF</resetMask>
34460              <fields>
34461                <field>
34462                  <name>LTSSM_STATE_CHG</name>
34463                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
34464                  <bitRange>[0:0]</bitRange>
34465                  <access>read-write</access>
34466                </field>
34467                <field>
34468                  <name>LGOOD</name>
34469                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
34470                  <bitRange>[1:1]</bitRange>
34471                  <access>read-write</access>
34472                </field>
34473                <field>
34474                  <name>LRTY</name>
34475                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
34476                  <bitRange>[2:2]</bitRange>
34477                  <access>read-write</access>
34478                </field>
34479                <field>
34480                  <name>LBAD</name>
34481                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
34482                  <bitRange>[3:3]</bitRange>
34483                  <access>read-write</access>
34484                </field>
34485                <field>
34486                  <name>LCRD</name>
34487                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
34488                  <bitRange>[4:4]</bitRange>
34489                  <access>read-write</access>
34490                </field>
34491                <field>
34492                  <name>LGO_U1</name>
34493                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
34494                  <bitRange>[5:5]</bitRange>
34495                  <access>read-write</access>
34496                </field>
34497                <field>
34498                  <name>LGO_U2</name>
34499                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
34500                  <bitRange>[6:6]</bitRange>
34501                  <access>read-write</access>
34502                </field>
34503                <field>
34504                  <name>LGO_U3</name>
34505                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
34506                  <bitRange>[7:7]</bitRange>
34507                  <access>read-write</access>
34508                </field>
34509                <field>
34510                  <name>LAU</name>
34511                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
34512                  <bitRange>[8:8]</bitRange>
34513                  <access>read-write</access>
34514                </field>
34515                <field>
34516                  <name>LXU</name>
34517                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
34518                  <bitRange>[9:9]</bitRange>
34519                  <access>read-write</access>
34520                </field>
34521                <field>
34522                  <name>LPMA</name>
34523                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
34524                  <bitRange>[10:10]</bitRange>
34525                  <access>read-write</access>
34526                </field>
34527                <field>
34528                  <name>BAD_LCW</name>
34529                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
34530                  <bitRange>[11:11]</bitRange>
34531                  <access>read-write</access>
34532                </field>
34533                <field>
34534                  <name>LINK_ERROR</name>
34535                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
34536                  <bitRange>[12:12]</bitRange>
34537                  <access>read-write</access>
34538                </field>
34539                <field>
34540                  <name>PHY_ERROR</name>
34541                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
34542                  <bitRange>[13:13]</bitRange>
34543                  <access>read-write</access>
34544                </field>
34545                <field>
34546                  <name>U2_INACTIVITY_TIMEOUT</name>
34547                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
34548                  <bitRange>[14:14]</bitRange>
34549                  <access>read-write</access>
34550                </field>
34551                <field>
34552                  <name>LTSSM_CONNECT</name>
34553                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
34554                  <bitRange>[15:15]</bitRange>
34555                  <access>read-write</access>
34556                </field>
34557                <field>
34558                  <name>LTSSM_DISCONNECT</name>
34559                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
34560                  <bitRange>[16:16]</bitRange>
34561                  <access>read-write</access>
34562                </field>
34563                <field>
34564                  <name>LTSSM_RESET</name>
34565                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
34566                  <bitRange>[17:17]</bitRange>
34567                  <access>read-write</access>
34568                </field>
34569                <field>
34570                  <name>DATA_RATE_CHANGE</name>
34571                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
34572                  <bitRange>[18:18]</bitRange>
34573                  <access>read-write</access>
34574                </field>
34575              </fields>
34576            </register>
34577            <register>
34578              <name>LNK_INTR_MASK</name>
34579              <description>LINK Interrupts Mask</description>
34580              <addressOffset>0xC</addressOffset>
34581              <size>32</size>
34582              <access>read-write</access>
34583              <resetValue>0x0</resetValue>
34584              <resetMask>0x7FFFF</resetMask>
34585              <fields>
34586                <field>
34587                  <name>LTSSM_STATE_CHG_MASK</name>
34588                  <description>Mask bit for corresponding bit in interrupt request register.</description>
34589                  <bitRange>[0:0]</bitRange>
34590                  <access>read-write</access>
34591                </field>
34592                <field>
34593                  <name>LGOOD_MASK</name>
34594                  <description>Mask bit for corresponding bit in interrupt request register.</description>
34595                  <bitRange>[1:1]</bitRange>
34596                  <access>read-write</access>
34597                </field>
34598                <field>
34599                  <name>LRTY_MASK</name>
34600                  <description>Mask bit for corresponding bit in interrupt request register.</description>
34601                  <bitRange>[2:2]</bitRange>
34602                  <access>read-write</access>
34603                </field>
34604                <field>
34605                  <name>LBAD_MASK</name>
34606                  <description>Mask bit for corresponding bit in interrupt request register.</description>
34607                  <bitRange>[3:3]</bitRange>
34608                  <access>read-write</access>
34609                </field>
34610                <field>
34611                  <name>LCRD_MASK</name>
34612                  <description>Mask bit for corresponding bit in interrupt request register.</description>
34613                  <bitRange>[4:4]</bitRange>
34614                  <access>read-write</access>
34615                </field>
34616                <field>
34617                  <name>LGO_U1_MASK</name>
34618                  <description>Mask bit for corresponding bit in interrupt request register.</description>
34619                  <bitRange>[5:5]</bitRange>
34620                  <access>read-write</access>
34621                </field>
34622                <field>
34623                  <name>LGO_U2_MASK</name>
34624                  <description>Mask bit for corresponding bit in interrupt request register.</description>
34625                  <bitRange>[6:6]</bitRange>
34626                  <access>read-write</access>
34627                </field>
34628                <field>
34629                  <name>LGO_U3_MASK</name>
34630                  <description>Mask bit for corresponding bit in interrupt request register.</description>
34631                  <bitRange>[7:7]</bitRange>
34632                  <access>read-write</access>
34633                </field>
34634                <field>
34635                  <name>LAU_MASK</name>
34636                  <description>Mask bit for corresponding bit in interrupt request register.</description>
34637                  <bitRange>[8:8]</bitRange>
34638                  <access>read-write</access>
34639                </field>
34640                <field>
34641                  <name>LXU_MASK</name>
34642                  <description>Mask bit for corresponding bit in interrupt request register.</description>
34643                  <bitRange>[9:9]</bitRange>
34644                  <access>read-write</access>
34645                </field>
34646                <field>
34647                  <name>LPMA_MASK</name>
34648                  <description>Mask bit for corresponding bit in interrupt request register.</description>
34649                  <bitRange>[10:10]</bitRange>
34650                  <access>read-write</access>
34651                </field>
34652                <field>
34653                  <name>BAD_LCW_MASK</name>
34654                  <description>Mask bit for corresponding bit in interrupt request register.</description>
34655                  <bitRange>[11:11]</bitRange>
34656                  <access>read-write</access>
34657                </field>
34658                <field>
34659                  <name>LINK_ERROR_MASK</name>
34660                  <description>Mask bit for corresponding bit in interrupt request register.</description>
34661                  <bitRange>[12:12]</bitRange>
34662                  <access>read-write</access>
34663                </field>
34664                <field>
34665                  <name>PHY_ERROR_MASK</name>
34666                  <description>Mask bit for corresponding bit in interrupt request register.</description>
34667                  <bitRange>[13:13]</bitRange>
34668                  <access>read-write</access>
34669                </field>
34670                <field>
34671                  <name>U2_INACTIVITY_TIMEOUT_MASK</name>
34672                  <description>Mask bit for corresponding bit in interrupt request register.</description>
34673                  <bitRange>[14:14]</bitRange>
34674                  <access>read-write</access>
34675                </field>
34676                <field>
34677                  <name>LTSSM_CONNECT_MASK</name>
34678                  <description>Mask bit for corresponding bit in interrupt request register.</description>
34679                  <bitRange>[15:15]</bitRange>
34680                  <access>read-write</access>
34681                </field>
34682                <field>
34683                  <name>LTSSM_DISCONNECT_MASK</name>
34684                  <description>Mask bit for corresponding bit in interrupt request register.</description>
34685                  <bitRange>[16:16]</bitRange>
34686                  <access>read-write</access>
34687                </field>
34688                <field>
34689                  <name>LTSSM_RESET_MASK</name>
34690                  <description>Mask bit for corresponding bit in interrupt request register.</description>
34691                  <bitRange>[17:17]</bitRange>
34692                  <access>read-write</access>
34693                </field>
34694                <field>
34695                  <name>DATA_RATE_CHANGE</name>
34696                  <description>Mask bit for corresponding bit in interrupt request register.</description>
34697                  <bitRange>[18:18]</bitRange>
34698                  <access>read-write</access>
34699                </field>
34700              </fields>
34701            </register>
34702            <register>
34703              <name>LNK_INTR_MASKED</name>
34704              <description>Protocol Interrupts Masked</description>
34705              <addressOffset>0x10</addressOffset>
34706              <size>32</size>
34707              <access>read-only</access>
34708              <resetValue>0x0</resetValue>
34709              <resetMask>0x7FFFF</resetMask>
34710              <fields>
34711                <field>
34712                  <name>LTSSM_STATE_CHG_MASKED</name>
34713                  <description>Logical and of corresponding request and mask bits.</description>
34714                  <bitRange>[0:0]</bitRange>
34715                  <access>read-only</access>
34716                </field>
34717                <field>
34718                  <name>LGOOD_MASKED</name>
34719                  <description>Logical and of corresponding request and mask bits.</description>
34720                  <bitRange>[1:1]</bitRange>
34721                  <access>read-only</access>
34722                </field>
34723                <field>
34724                  <name>LRTY_MASKED</name>
34725                  <description>Logical and of corresponding request and mask bits.</description>
34726                  <bitRange>[2:2]</bitRange>
34727                  <access>read-only</access>
34728                </field>
34729                <field>
34730                  <name>LBAD_MASKED</name>
34731                  <description>Logical and of corresponding request and mask bits.</description>
34732                  <bitRange>[3:3]</bitRange>
34733                  <access>read-only</access>
34734                </field>
34735                <field>
34736                  <name>LCRD_MASKED</name>
34737                  <description>Logical and of corresponding request and mask bits.</description>
34738                  <bitRange>[4:4]</bitRange>
34739                  <access>read-only</access>
34740                </field>
34741                <field>
34742                  <name>LGO_U1_MASKED</name>
34743                  <description>Logical and of corresponding request and mask bits.</description>
34744                  <bitRange>[5:5]</bitRange>
34745                  <access>read-only</access>
34746                </field>
34747                <field>
34748                  <name>LGO_U2_MASKED</name>
34749                  <description>Logical and of corresponding request and mask bits.</description>
34750                  <bitRange>[6:6]</bitRange>
34751                  <access>read-only</access>
34752                </field>
34753                <field>
34754                  <name>LGO_U3_MASKED</name>
34755                  <description>Logical and of corresponding request and mask bits.</description>
34756                  <bitRange>[7:7]</bitRange>
34757                  <access>read-only</access>
34758                </field>
34759                <field>
34760                  <name>LAU_MASKED</name>
34761                  <description>Logical and of corresponding request and mask bits.</description>
34762                  <bitRange>[8:8]</bitRange>
34763                  <access>read-only</access>
34764                </field>
34765                <field>
34766                  <name>LXU_MASKED</name>
34767                  <description>Logical and of corresponding request and mask bits.</description>
34768                  <bitRange>[9:9]</bitRange>
34769                  <access>read-only</access>
34770                </field>
34771                <field>
34772                  <name>LPMA_MASKED</name>
34773                  <description>Logical and of corresponding request and mask bits.</description>
34774                  <bitRange>[10:10]</bitRange>
34775                  <access>read-only</access>
34776                </field>
34777                <field>
34778                  <name>BAD_LCW_MASKED</name>
34779                  <description>Logical and of corresponding request and mask bits.</description>
34780                  <bitRange>[11:11]</bitRange>
34781                  <access>read-only</access>
34782                </field>
34783                <field>
34784                  <name>LINK_ERROR_MASKED</name>
34785                  <description>Logical and of corresponding request and mask bits.</description>
34786                  <bitRange>[12:12]</bitRange>
34787                  <access>read-only</access>
34788                </field>
34789                <field>
34790                  <name>PHY_ERROR_MASKED</name>
34791                  <description>Logical and of corresponding request and mask bits.</description>
34792                  <bitRange>[13:13]</bitRange>
34793                  <access>read-only</access>
34794                </field>
34795                <field>
34796                  <name>U2_INACTIVITY_TIMEOUT_MASKED</name>
34797                  <description>Logical and of corresponding request and mask bits.</description>
34798                  <bitRange>[14:14]</bitRange>
34799                  <access>read-only</access>
34800                </field>
34801                <field>
34802                  <name>LTSSM_CONNECT_MASKED</name>
34803                  <description>Logical and of corresponding request and mask bits.</description>
34804                  <bitRange>[15:15]</bitRange>
34805                  <access>read-only</access>
34806                </field>
34807                <field>
34808                  <name>LTSSM_DISCONNECT_MASKED</name>
34809                  <description>Logical and of corresponding request and mask bits.</description>
34810                  <bitRange>[16:16]</bitRange>
34811                  <access>read-only</access>
34812                </field>
34813                <field>
34814                  <name>LTSSM_RESET_MASKED</name>
34815                  <description>Logical and of corresponding request and mask bits.</description>
34816                  <bitRange>[17:17]</bitRange>
34817                  <access>read-only</access>
34818                </field>
34819                <field>
34820                  <name>DATA_RATE_CHANGE</name>
34821                  <description>Logical and of corresponding request and mask bits.</description>
34822                  <bitRange>[18:18]</bitRange>
34823                  <access>read-only</access>
34824                </field>
34825              </fields>
34826            </register>
34827            <register>
34828              <name>LNK_ERROR_CONF</name>
34829              <description>Link Error Counter Configuration</description>
34830              <addressOffset>0x14</addressOffset>
34831              <size>32</size>
34832              <access>read-write</access>
34833              <resetValue>0x7FFF</resetValue>
34834              <resetMask>0x7FFF</resetMask>
34835              <fields>
34836                <field>
34837                  <name>HP_TIMEOUT_EN</name>
34838                  <description>PENDING_HP_TIMER Timeout Count Enable
34839Header Packet acknowledgement has not been received by PENDING_HP_TIMEOUT.
34840[USB 3.0:  7.2.4.1.10, p 7-21]</description>
34841                  <bitRange>[0:0]</bitRange>
34842                  <access>read-write</access>
34843                </field>
34844                <field>
34845                  <name>RX_SEQ_NUM_ERR_EN</name>
34846                  <description>Rx Header Sequence Number Error Count Enable
34847Received Rx Header Sequence Number does not match what is expected.
34848[USB 3.0:  7.3.3.3, p 7-28]</description>
34849                  <bitRange>[1:1]</bitRange>
34850                  <access>read-write</access>
34851                </field>
34852                <field>
34853                  <name>RX_HP_FAIL_EN</name>
34854                  <description>Receive Header Packet Fail Count Enable
34855Link Layer Block has failed to receive a Header Packet for three consecutive times.  Failures are CRC errors or spurious K-symbols.
34856[USB 3.0:  7.3.3.2, p 7-28]</description>
34857                  <bitRange>[2:2]</bitRange>
34858                  <access>read-write</access>
34859                </field>
34860                <field>
34861                  <name>MISSING_LGOOD_EN</name>
34862                  <description>Missing LGOOD_n Detection Count Enable
34863LGOOD_n Sequence Number does not match what is expected.
34864[USB 3.0:  7.3.4, p 7-29]</description>
34865                  <bitRange>[3:3]</bitRange>
34866                  <access>read-write</access>
34867                </field>
34868                <field>
34869                  <name>MISSING_LCRD_EN</name>
34870                  <description>Missing LCRD_x Detection Count Enable
34871LCRD_x Sequence does not match what is expected.
34872[USB 3.0:  7.3.4, p 7-29]</description>
34873                  <bitRange>[4:4]</bitRange>
34874                  <access>read-write</access>
34875                </field>
34876                <field>
34877                  <name>CREDIT_HP_TIMEOUT_EN</name>
34878                  <description>CREDIT_HP_TIMER Timeout Count Enable
34879Remote Rx Header Buffer Credit has not been received by CREDIT_HP_TIMEOUT.
34880[USB 3.0:  7.2.4.1.10, p 7-21...7-22]</description>
34881                  <bitRange>[5:5]</bitRange>
34882                  <access>read-write</access>
34883                </field>
34884                <field>
34885                  <name>PM_LC_TIMEOUT_EN</name>
34886                  <description>PM_LC_TIMER Timeout Count Enable
34887This indicates that an LGO_Ux, LAU, or LXU Link Command has been missed.
34888[USB 3.0:  7.3.4, p 7-29]</description>
34889                  <bitRange>[6:6]</bitRange>
34890                  <access>read-write</access>
34891                </field>
34892                <field>
34893                  <name>TX_SEQ_NUM_ERR_EN</name>
34894                  <description>ACK Tx Header Sequence Number Error Count Enable
34895Received LGOOD_n does not match ACK Tx Header Sequence Number.
34896[USB 3.0: 7.3.5, p 7-30]</description>
34897                  <bitRange>[7:7]</bitRange>
34898                  <access>read-write</access>
34899                </field>
34900                <field>
34901                  <name>HDR_ADV_TIMEOUT_EN</name>
34902                  <description>Header Sequence Number Advertisement PENDING_HP_TIMER Timeout Count Enable
34903PENDING_HP_TIMER timeout before receipt of Header Sequence Number LGOOD_n Link Command
34904[USB 3.0:  7.3.6, p 7-30]</description>
34905                  <bitRange>[8:8]</bitRange>
34906                  <access>read-write</access>
34907                </field>
34908                <field>
34909                  <name>HDR_ADV_HP_EN</name>
34910                  <description>Header Sequence Number Advertisement HP Received Error Count Enable
34911Header Packet received during Header Sequence Number Advertisement
34912[USB 3.0: 7.3.6, p 7-30]</description>
34913                  <bitRange>[9:9]</bitRange>
34914                  <access>read-write</access>
34915                </field>
34916                <field>
34917                  <name>HDR_ADV_LCRD_EN</name>
34918                  <description>Header Sequence Number Advertisement LCRD_x Received Error Count Enable
34919LCRD_x Link Command received during Header Sequence Number Advertisement
34920[USB 3.0: 7.3.6, p 7-30]</description>
34921                  <bitRange>[10:10]</bitRange>
34922                  <access>read-write</access>
34923                </field>
34924                <field>
34925                  <name>HDR_ADV_LGO_EN</name>
34926                  <description>Header Sequence Number Advertisement LGO_Ux Received Error Count Enable
34927LGO_Ux Link Command received during Header Sequence Number Advertisement
34928[USB 3.0:  7.3.6, p 7-30]</description>
34929                  <bitRange>[11:11]</bitRange>
34930                  <access>read-write</access>
34931                </field>
34932                <field>
34933                  <name>CREDIT_ADV_TIMEOUT_EN</name>
34934                  <description>Rx Header Buffer Credit Advertisement CREDIT_HP_TIMER Timeout Count Enable
34935CREDIT_HP_TIMER timeout before receipt of LCRD_x Link Command during Rx Header Buffer Credit Advertisement
34936[USB 3.0:  7.3.7, p 7-30...7-31]</description>
34937                  <bitRange>[12:12]</bitRange>
34938                  <access>read-write</access>
34939                </field>
34940                <field>
34941                  <name>CREDIT_ADV_HP_EN</name>
34942                  <description>Rx Header Buffer Credit Advertisement HP Received Error Count Enable
34943Header Packet received during Rx Header Buffer Credit Advertisement.
34944[USB 3.0:  7.3.7, p 7-30...7-31]</description>
34945                  <bitRange>[13:13]</bitRange>
34946                  <access>read-write</access>
34947                </field>
34948                <field>
34949                  <name>CREDIT_ADV_LGO_EN</name>
34950                  <description>Rx Header Buffer Credit Advertisement LGO_Ux Received Error Count Enable
34951LGO_Ux Link Command received during Rx Header Buffer Credit Advertisement.
34952[USB 3.0:  7.3.7, p 7-30...7-31]</description>
34953                  <bitRange>[14:14]</bitRange>
34954                  <access>read-write</access>
34955                </field>
34956              </fields>
34957            </register>
34958            <register>
34959              <name>LNK_ERROR_STATUS</name>
34960              <description>Link Error Status Register</description>
34961              <addressOffset>0x18</addressOffset>
34962              <size>32</size>
34963              <access>read-write</access>
34964              <resetValue>0x0</resetValue>
34965              <resetMask>0x7FFF</resetMask>
34966              <fields>
34967                <field>
34968                  <name>HP_TIMEOUT_EV</name>
34969                  <description>Indicates this error (see LNK_ERROR_CONF for description) occurred since this bit was last cleared by firmware.</description>
34970                  <bitRange>[0:0]</bitRange>
34971                  <access>read-write</access>
34972                </field>
34973                <field>
34974                  <name>RX_SEQ_NUM_ERR_EV</name>
34975                  <description>Indicates this error (see LNK_ERROR_CONF for description) occurred since this bit was last cleared by firmware.</description>
34976                  <bitRange>[1:1]</bitRange>
34977                  <access>read-write</access>
34978                </field>
34979                <field>
34980                  <name>RX_HP_FAIL_EV</name>
34981                  <description>Indicates this error (see LNK_ERROR_CONF for description) occurred since this bit was last cleared by firmware.</description>
34982                  <bitRange>[2:2]</bitRange>
34983                  <access>read-write</access>
34984                </field>
34985                <field>
34986                  <name>MISSING_LGOOD_EV</name>
34987                  <description>Indicates this error (see LNK_ERROR_CONF for description) occurred since this bit was last cleared by firmware.</description>
34988                  <bitRange>[3:3]</bitRange>
34989                  <access>read-write</access>
34990                </field>
34991                <field>
34992                  <name>MISSING_LCRD_EV</name>
34993                  <description>Indicates this error (see LNK_ERROR_CONF for description) occurred since this bit was last cleared by firmware.</description>
34994                  <bitRange>[4:4]</bitRange>
34995                  <access>read-write</access>
34996                </field>
34997                <field>
34998                  <name>CREDIT_HP_TIMEOUT_EV</name>
34999                  <description>Indicates this error (see LNK_ERROR_CONF for description) occurred since this bit was last cleared by firmware.</description>
35000                  <bitRange>[5:5]</bitRange>
35001                  <access>read-write</access>
35002                </field>
35003                <field>
35004                  <name>PM_LC_TIMEOUT_EV</name>
35005                  <description>Indicates this error (see LNK_ERROR_CONF for description) occurred since this bit was last cleared by firmware.</description>
35006                  <bitRange>[6:6]</bitRange>
35007                  <access>read-write</access>
35008                </field>
35009                <field>
35010                  <name>TX_SEQ_NUM_ERR_EV</name>
35011                  <description>Indicates this error (see LNK_ERROR_CONF for description) occurred since this bit was last cleared by firmware.</description>
35012                  <bitRange>[7:7]</bitRange>
35013                  <access>read-write</access>
35014                </field>
35015                <field>
35016                  <name>HDR_ADV_TIMEOUT_EV</name>
35017                  <description>Indicates this error (see LNK_ERROR_CONF for description) occurred since this bit was last cleared by firmware.</description>
35018                  <bitRange>[8:8]</bitRange>
35019                  <access>read-write</access>
35020                </field>
35021                <field>
35022                  <name>HDR_ADV_HP_EV</name>
35023                  <description>Indicates this error (see LNK_ERROR_CONF for description) occurred since this bit was last cleared by firmware.</description>
35024                  <bitRange>[9:9]</bitRange>
35025                  <access>read-write</access>
35026                </field>
35027                <field>
35028                  <name>HDR_ADV_LCRD_EV</name>
35029                  <description>Indicates this error (see LNK_ERROR_CONF for description) occurred since this bit was last cleared by firmware.</description>
35030                  <bitRange>[10:10]</bitRange>
35031                  <access>read-write</access>
35032                </field>
35033                <field>
35034                  <name>HDR_ADV_LGO_EV</name>
35035                  <description>Indicates this error (see LNK_ERROR_CONF for description) occurred since this bit was last cleared by firmware.</description>
35036                  <bitRange>[11:11]</bitRange>
35037                  <access>read-write</access>
35038                </field>
35039                <field>
35040                  <name>CREDIT_ADV_TIMEOUT_EV</name>
35041                  <description>Indicates this error (see LNK_ERROR_CONF for description) occurred since this bit was last cleared by firmware.</description>
35042                  <bitRange>[12:12]</bitRange>
35043                  <access>read-write</access>
35044                </field>
35045                <field>
35046                  <name>CREDIT_ADV_HP_EV</name>
35047                  <description>Indicates this error (see LNK_ERROR_CONF for description) occurred since this bit was last cleared by firmware.</description>
35048                  <bitRange>[13:13]</bitRange>
35049                  <access>read-write</access>
35050                </field>
35051                <field>
35052                  <name>CREDIT_ADV_LGO_EV</name>
35053                  <description>Indicates this error (see LNK_ERROR_CONF for description) occurred since this bit was last cleared by firmware.</description>
35054                  <bitRange>[14:14]</bitRange>
35055                  <access>read-write</access>
35056                </field>
35057              </fields>
35058            </register>
35059            <register>
35060              <name>LNK_ERROR_COUNT</name>
35061              <description>Error Counter Register</description>
35062              <addressOffset>0x1C</addressOffset>
35063              <size>32</size>
35064              <access>read-write</access>
35065              <resetValue>0x0</resetValue>
35066              <resetMask>0xFFFFFFFF</resetMask>
35067              <fields>
35068                <field>
35069                  <name>LINK_ERROR_COUNT</name>
35070                  <description>The Link Error Count keeps track of the number of errors for which the Link Layer Block had to transition to the Recovery State before resuming normal operation.  Each error class is enablable (default on) to allow for debugging purposes.</description>
35071                  <bitRange>[15:0]</bitRange>
35072                  <access>read-write</access>
35073                </field>
35074                <field>
35075                  <name>PHY_ERROR_COUNT</name>
35076                  <description>Count of receive errors from the USB 3.0 PHY.  This is for debug purposes.</description>
35077                  <bitRange>[31:16]</bitRange>
35078                  <access>read-write</access>
35079                </field>
35080              </fields>
35081            </register>
35082            <register>
35083              <name>LNK_ERROR_COUNT_THRESHOLD</name>
35084              <description>Error Count Thresholds</description>
35085              <addressOffset>0x20</addressOffset>
35086              <size>32</size>
35087              <access>read-write</access>
35088              <resetValue>0x0</resetValue>
35089              <resetMask>0xFFFFFFFF</resetMask>
35090              <fields>
35091                <field>
35092                  <name>LINK_ERROR_THRESHOLD</name>
35093                  <description>Link Error Count Threshold for Interrupt Generation</description>
35094                  <bitRange>[15:0]</bitRange>
35095                  <access>read-write</access>
35096                </field>
35097                <field>
35098                  <name>PHY_ERROR_THRESHOLD</name>
35099                  <description>PHY Error Count Threshold for Interrupt Generation</description>
35100                  <bitRange>[31:16]</bitRange>
35101                  <access>read-write</access>
35102                </field>
35103              </fields>
35104            </register>
35105            <register>
35106              <name>LNK_PHY_CONF</name>
35107              <description>USB 3.0 PHY Configuration</description>
35108              <addressOffset>0x24</addressOffset>
35109              <size>32</size>
35110              <access>read-write</access>
35111              <resetValue>0x202005</resetValue>
35112              <resetMask>0xFFFFFFFF</resetMask>
35113              <fields>
35114                <field>
35115                  <name>PHY_MODE</name>
35116                  <description>PHY Operation Mode
35117    01 = USB Super Speed</description>
35118                  <bitRange>[1:0]</bitRange>
35119                  <access>read-only</access>
35120                </field>
35121                <field>
35122                  <name>ELASTICIY_BUFFER_MODE</name>
35123                  <description>PHY Elasticity Buffer Operation Mode
35124    0 = half full
35125    1 = empty</description>
35126                  <bitRange>[2:2]</bitRange>
35127                  <access>read-write</access>
35128                </field>
35129                <field>
35130                  <name>TXDETECTRX_LB_OVR</name>
35131                  <description>PHY TxDetectRx/Loopback Override</description>
35132                  <bitRange>[3:3]</bitRange>
35133                  <access>read-write</access>
35134                </field>
35135                <field>
35136                  <name>TXDETECTRX_LB_OVR_VAL</name>
35137                  <description>PHY TxDetectRx/Loopback Override Value</description>
35138                  <bitRange>[4:4]</bitRange>
35139                  <access>read-write</access>
35140                </field>
35141                <field>
35142                  <name>TXELECIDLE_OVR</name>
35143                  <description>PHY TxElecIdle Override</description>
35144                  <bitRange>[5:5]</bitRange>
35145                  <access>read-write</access>
35146                </field>
35147                <field>
35148                  <name>TXELECIDLE_OVR_VAL</name>
35149                  <description>PHY TxElecIdle Override Value</description>
35150                  <bitRange>[6:6]</bitRange>
35151                  <access>read-write</access>
35152                </field>
35153                <field>
35154                  <name>TXCOMPLIANCE_OVR</name>
35155                  <description>PHY TxCompliance Override</description>
35156                  <bitRange>[7:7]</bitRange>
35157                  <access>read-only</access>
35158                </field>
35159                <field>
35160                  <name>TXCOMPLIANCE_OVR_VAL</name>
35161                  <description>PHY TxCompliance Override Value</description>
35162                  <bitRange>[8:8]</bitRange>
35163                  <access>read-only</access>
35164                </field>
35165                <field>
35166                  <name>TXONESZEROS_OVR</name>
35167                  <description>PHY TxOnesZeros Override</description>
35168                  <bitRange>[9:9]</bitRange>
35169                  <access>read-write</access>
35170                </field>
35171                <field>
35172                  <name>TXONESZEROS_OVR_VAL</name>
35173                  <description>PHY TxOnesZeros Override Value</description>
35174                  <bitRange>[10:10]</bitRange>
35175                  <access>read-write</access>
35176                </field>
35177                <field>
35178                  <name>RXPOLARITY_OVR</name>
35179                  <description>PHY RxPolarity Override</description>
35180                  <bitRange>[11:11]</bitRange>
35181                  <access>read-write</access>
35182                </field>
35183                <field>
35184                  <name>RXPOLARITY_OVR_VAL</name>
35185                  <description>PHY RxPolarity Override Value</description>
35186                  <bitRange>[12:12]</bitRange>
35187                  <access>read-write</access>
35188                </field>
35189                <field>
35190                  <name>RXEQ_TRAINING_OVR</name>
35191                  <description>PHY RxEqTraining Override</description>
35192                  <bitRange>[13:13]</bitRange>
35193                  <access>read-write</access>
35194                </field>
35195                <field>
35196                  <name>RXEQ_TRAINING_OVR_VAL</name>
35197                  <description>PHY RxEqTraining Override Value</description>
35198                  <bitRange>[14:14]</bitRange>
35199                  <access>read-write</access>
35200                </field>
35201                <field>
35202                  <name>PHY_RESET_N_OVR</name>
35203                  <description>PHY PIPE RESET# Override</description>
35204                  <bitRange>[15:15]</bitRange>
35205                  <access>read-write</access>
35206                </field>
35207                <field>
35208                  <name>PHY_RESET_N_OVR_VAL</name>
35209                  <description>PHY PIPE RESET# Override Value</description>
35210                  <bitRange>[16:16]</bitRange>
35211                  <access>read-write</access>
35212                </field>
35213                <field>
35214                  <name>PHY_POWERDOWN_OVR</name>
35215                  <description>PHY PowerDown Override</description>
35216                  <bitRange>[17:17]</bitRange>
35217                  <access>read-write</access>
35218                </field>
35219                <field>
35220                  <name>PHY_POWERDOWN_OVR_VAL</name>
35221                  <description>PHY PowerDown Override Value</description>
35222                  <bitRange>[19:18]</bitRange>
35223                  <access>read-write</access>
35224                </field>
35225                <field>
35226                  <name>PHY_RATE_OVR</name>
35227                  <description>PHY Rate Override</description>
35228                  <bitRange>[20:20]</bitRange>
35229                  <access>read-only</access>
35230                </field>
35231                <field>
35232                  <name>PHY_RATE_OVR_VAL</name>
35233                  <description>PHY Rate Override Value</description>
35234                  <bitRange>[21:21]</bitRange>
35235                  <access>read-only</access>
35236                </field>
35237                <field>
35238                  <name>PHY_TX_DEEMPH_OVR</name>
35239                  <description>PHY Transmitter De-emphasis Override</description>
35240                  <bitRange>[22:22]</bitRange>
35241                  <access>read-write</access>
35242                </field>
35243                <field>
35244                  <name>PHY_TX_DEEMPH_OVR_VAL</name>
35245                  <description>PHY Transmitter De-emphasis Override Value</description>
35246                  <bitRange>[24:23]</bitRange>
35247                  <access>read-write</access>
35248                </field>
35249                <field>
35250                  <name>PHY_TX_MARGIN</name>
35251                  <description>PHY Transmitter Voltage Levels</description>
35252                  <bitRange>[27:25]</bitRange>
35253                  <access>read-write</access>
35254                </field>
35255                <field>
35256                  <name>TXSWING</name>
35257                  <description>PHY Transmitter Voltage Swing Level 0=full swing 1=low swing</description>
35258                  <bitRange>[28:28]</bitRange>
35259                  <access>read-write</access>
35260                </field>
35261                <field>
35262                  <name>RX_TERMINATION_OVR</name>
35263                  <description>PHY Receiver Termination Override</description>
35264                  <bitRange>[29:29]</bitRange>
35265                  <access>read-write</access>
35266                </field>
35267                <field>
35268                  <name>RX_TERMINATION_OVR_VAL</name>
35269                  <description>PHY Receiver Termination Override Value 0=removed 1=present</description>
35270                  <bitRange>[30:30]</bitRange>
35271                  <access>read-write</access>
35272                </field>
35273                <field>
35274                  <name>RX_TERMINATION_ENABLE</name>
35275                  <description>PHY Receiver Termination Enable</description>
35276                  <bitRange>[31:31]</bitRange>
35277                  <access>read-write</access>
35278                </field>
35279              </fields>
35280            </register>
35281            <register>
35282              <name>LNK_PHY_STATUS</name>
35283              <description>USB 3.0 PHY Status</description>
35284              <addressOffset>0x28</addressOffset>
35285              <size>32</size>
35286              <access>read-only</access>
35287              <resetValue>0x0</resetValue>
35288              <resetMask>0x3FF</resetMask>
35289              <fields>
35290                <field>
35291                  <name>RXVALID</name>
35292                  <description>PHY Receive Valid (symbol lock and valid data)</description>
35293                  <bitRange>[0:0]</bitRange>
35294                  <access>read-only</access>
35295                </field>
35296                <field>
35297                  <name>PHY_STATUS</name>
35298                  <description>PHY Status (operation complete)</description>
35299                  <bitRange>[1:1]</bitRange>
35300                  <access>read-only</access>
35301                </field>
35302                <field>
35303                  <name>RX_ELEC_IDLE</name>
35304                  <description>Receiver Detection of an Electrical Idle (LFPS Signalling)</description>
35305                  <bitRange>[2:2]</bitRange>
35306                  <access>read-only</access>
35307                </field>
35308                <field>
35309                  <name>RXSTATUS</name>
35310                  <description>PHY Receiver Status and Error Codes
35311    000  Receive Data OK
35312    001  1 SKP Ordered Set added (USB SuperSpeed Mode)
35313    010  1 SKP Ordered Set removed (USB SuperSpeed Mode)
35314    011  Receiver Detected (during Receiver Detection Sequence)
35315    100  8b/10b Decode Error or Receive Disparity Error
35316    101  Elastic Buffer overflow
35317    110  Elastic Buffer underflow
35318    111  Receive Disparity Error</description>
35319                  <bitRange>[5:3]</bitRange>
35320                  <access>read-only</access>
35321                </field>
35322                <field>
35323                  <name>POWER_PRESENT</name>
35324                  <description>Presence of VBUS</description>
35325                  <bitRange>[6:6]</bitRange>
35326                  <access>read-only</access>
35327                </field>
35328                <field>
35329                  <name>DATA_BUS_WIDTH</name>
35330                  <description>Data Bus Width
35331    00: 32-bit mode</description>
35332                  <bitRange>[8:7]</bitRange>
35333                  <access>read-only</access>
35334                </field>
35335                <field>
35336                  <name>RXCONNECT</name>
35337                  <description>Rx Connect/Disconnect - Far-end Receiver Termination Detection
35338Stored result from last Rx.Detect Sequence</description>
35339                  <bitRange>[9:9]</bitRange>
35340                  <access>read-only</access>
35341                </field>
35342              </fields>
35343            </register>
35344            <register>
35345              <name>LNK_PHY_ERROR_CONF</name>
35346              <description>PHY Error Counter Configuration</description>
35347              <addressOffset>0x48</addressOffset>
35348              <size>32</size>
35349              <access>read-write</access>
35350              <resetValue>0x1FF</resetValue>
35351              <resetMask>0x1FF</resetMask>
35352              <fields>
35353                <field>
35354                  <name>PHY_ERROR_DECODE_EN</name>
35355                  <description>Enable Counting of 8b/10b Decode Errors
35356    (RxStatus == 3'b100)</description>
35357                  <bitRange>[0:0]</bitRange>
35358                  <access>read-write</access>
35359                </field>
35360                <field>
35361                  <name>PHY_ERROR_EB_OVR_EN</name>
35362                  <description>Enable Counting of Elastic Buffer Overflow
35363    (RxStatus == 3'b101)</description>
35364                  <bitRange>[1:1]</bitRange>
35365                  <access>read-write</access>
35366                </field>
35367                <field>
35368                  <name>PHY_ERROR_EB_UND_EN</name>
35369                  <description>Enable Counting of Elastic Buffer Underflow
35370    (RxStatus == 3'b110)</description>
35371                  <bitRange>[2:2]</bitRange>
35372                  <access>read-write</access>
35373                </field>
35374                <field>
35375                  <name>PHY_ERROR_DISPARITY_EN</name>
35376                  <description>Enable Counting of Receive Disparity Error
35377    (RxStatus == 3'b111)</description>
35378                  <bitRange>[3:3]</bitRange>
35379                  <access>read-write</access>
35380                </field>
35381                <field>
35382                  <name>RX_ERROR_CRC5_EN</name>
35383                  <description>Enable Counting of Receive CRC-5 Error</description>
35384                  <bitRange>[4:4]</bitRange>
35385                  <access>read-write</access>
35386                </field>
35387                <field>
35388                  <name>RX_ERROR_CRC16_EN</name>
35389                  <description>Enable Counting of Receive CRC-16 Error</description>
35390                  <bitRange>[5:5]</bitRange>
35391                  <access>read-write</access>
35392                </field>
35393                <field>
35394                  <name>RX_ERROR_CRC32_EN</name>
35395                  <description>Enable Counting of Receive CRC-32 Error</description>
35396                  <bitRange>[6:6]</bitRange>
35397                  <access>read-write</access>
35398                </field>
35399                <field>
35400                  <name>TRAINING_ERROR_EN</name>
35401                  <description>Enable Counting of Training Sequence Error</description>
35402                  <bitRange>[7:7]</bitRange>
35403                  <access>read-write</access>
35404                </field>
35405                <field>
35406                  <name>PHY_LOCK_EN</name>
35407                  <description>Enable Counting of PHY Lock Loss
35408   Lock Indicator To Be Determined</description>
35409                  <bitRange>[8:8]</bitRange>
35410                  <access>read-write</access>
35411                </field>
35412              </fields>
35413            </register>
35414            <register>
35415              <name>LNK_PHY_ERROR_STATUS</name>
35416              <description>PHY Error Status Register</description>
35417              <addressOffset>0x4C</addressOffset>
35418              <size>32</size>
35419              <access>read-write</access>
35420              <resetValue>0x0</resetValue>
35421              <resetMask>0x1FF</resetMask>
35422              <fields>
35423                <field>
35424                  <name>PHY_ERROR_DECODE_EV</name>
35425                  <description>Indicates this error (see LNK_ERROR_CONF for description) occurred since this bit was last cleared by firmware.</description>
35426                  <bitRange>[0:0]</bitRange>
35427                  <access>read-write</access>
35428                </field>
35429                <field>
35430                  <name>PHY_ERROR_EB_OVR_EV</name>
35431                  <description>Indicates this error (see LNK_ERROR_CONF for description) occurred since this bit was last cleared by firmware.</description>
35432                  <bitRange>[1:1]</bitRange>
35433                  <access>read-write</access>
35434                </field>
35435                <field>
35436                  <name>PHY_ERROR_EB_UND_EV</name>
35437                  <description>Indicates this error (see LNK_ERROR_CONF for description) occurred since this bit was last cleared by firmware.</description>
35438                  <bitRange>[2:2]</bitRange>
35439                  <access>read-write</access>
35440                </field>
35441                <field>
35442                  <name>PHY_ERROR_DISPARITY_EV</name>
35443                  <description>Indicates this error (see LNK_ERROR_CONF for description) occurred since this bit was last cleared by firmware.</description>
35444                  <bitRange>[3:3]</bitRange>
35445                  <access>read-write</access>
35446                </field>
35447                <field>
35448                  <name>RX_ERROR_CRC5_EV</name>
35449                  <description>Indicates this error (see LNK_ERROR_CONF for description) occurred since this bit was last cleared by firmware.</description>
35450                  <bitRange>[4:4]</bitRange>
35451                  <access>read-write</access>
35452                </field>
35453                <field>
35454                  <name>RX_ERROR_CRC16_EV</name>
35455                  <description>Indicates this error (see LNK_ERROR_CONF for description) occurred since this bit was last cleared by firmware.</description>
35456                  <bitRange>[5:5]</bitRange>
35457                  <access>read-write</access>
35458                </field>
35459                <field>
35460                  <name>RX_ERROR_CRC32_EV</name>
35461                  <description>Indicates this error (see LNK_ERROR_CONF for description) occurred since this bit was last cleared by firmware.</description>
35462                  <bitRange>[6:6]</bitRange>
35463                  <access>read-write</access>
35464                </field>
35465                <field>
35466                  <name>TRAINING_ERROR_EV</name>
35467                  <description>Indicates this error (see LNK_ERROR_CONF for description) occurred since this bit was last cleared by firmware.</description>
35468                  <bitRange>[7:7]</bitRange>
35469                  <access>read-write</access>
35470                </field>
35471                <field>
35472                  <name>PHY_LOCK_EV</name>
35473                  <description>Indicates this error (see LNK_ERROR_CONF for description) occurred since this bit was last cleared by firmware.</description>
35474                  <bitRange>[8:8]</bitRange>
35475                  <access>read-write</access>
35476                </field>
35477              </fields>
35478            </register>
35479            <register>
35480              <name>LNK_PHY_TRAINING_HOLDOFF</name>
35481              <description>PHY Training Hold Off</description>
35482              <addressOffset>0x50</addressOffset>
35483              <size>32</size>
35484              <access>read-write</access>
35485              <resetValue>0x249F0EA6</resetValue>
35486              <resetMask>0xFFFFFFFF</resetMask>
35487              <fields>
35488                <field>
35489                  <name>GEN1_HOLDOFF</name>
35490                  <description>Hold off period before PHY training begins to prevent termination reflection errors.
35491Default is 30 us, period is measured in 125MHz clocks.
35492[USB 3.0:  7.5.4.4.1, p 7-44]</description>
35493                  <bitRange>[15:0]</bitRange>
35494                  <access>read-write</access>
35495                </field>
35496                <field>
35497                  <name>GEN2_HOLDOFF</name>
35498                  <description>Hold off period before PHY training, assertion of the rxequalization of PIPE  begins to prevent termination reflection errors.
35499Default is 30 us, period is measured in 312.5MHz clocks.
35500[USB 3.2:  7.5.4.7.1]</description>
35501                  <bitRange>[31:16]</bitRange>
35502                  <access>read-write</access>
35503                </field>
35504              </fields>
35505            </register>
35506            <register>
35507              <name>LNK_COMMAND_WORD</name>
35508              <description>Link Command Word (received)</description>
35509              <addressOffset>0x54</addressOffset>
35510              <size>32</size>
35511              <access>read-only</access>
35512              <resetValue>0x0</resetValue>
35513              <resetMask>0x7FF</resetMask>
35514              <fields>
35515                <field>
35516                  <name>COMMAND</name>
35517                  <description>Link Command Word</description>
35518                  <bitRange>[10:0]</bitRange>
35519                  <access>read-only</access>
35520                </field>
35521              </fields>
35522            </register>
35523            <register>
35524              <name>LNK_DEVICE_POWER_CONTROL</name>
35525              <description>USB 3.0 Device Power State Control</description>
35526              <addressOffset>0x58</addressOffset>
35527              <size>32</size>
35528              <access>read-write</access>
35529              <resetValue>0x0</resetValue>
35530              <resetMask>0xFC0003F7</resetMask>
35531              <fields>
35532                <field>
35533                  <name>TX_U1</name>
35534                  <description>Transmit LGO_U1 - Request to go to U1 Power State (send LGO_U1)
35535This bit is cleared by h/w when the LCW is transmitted.</description>
35536                  <bitRange>[0:0]</bitRange>
35537                  <access>read-write</access>
35538                </field>
35539                <field>
35540                  <name>TX_U2</name>
35541                  <description>Transmit LGO_U2 - Request to go to U2 Power State (send LGO_U2)
35542This bit is cleared by h/w when the LCW is transmitted.</description>
35543                  <bitRange>[1:1]</bitRange>
35544                  <access>read-write</access>
35545                </field>
35546                <field>
35547                  <name>TX_U3</name>
35548                  <description>Transmit LGO_U3 - Request to go to U3 Power State (send LGO_U3)
35549This bit is cleared by h/w when the LCW is transmitted.
35550Note that an upstream port is not allowed to initiate entry to U3, so this should not be used for device mode.
35551[USB 3.0:  7.2.4.2.4, p 7-25]</description>
35552                  <bitRange>[2:2]</bitRange>
35553                  <access>read-write</access>
35554                </field>
35555                <field>
35556                  <name>RX_U1</name>
35557                  <description>LGO_U1 Received - Request to go to U1 Power State
35558This bit is cleared by h/w concurrent with TX_LAU/TX_LXU being cleared.</description>
35559                  <bitRange>[4:4]</bitRange>
35560                  <access>read-only</access>
35561                </field>
35562                <field>
35563                  <name>RX_U2</name>
35564                  <description>LGO_U2 Received - Request to go to U2 Power State, clear to NAK (send LXU)
35565This bit is cleared by h/w concurrent with TX_LAU/TX_LXU being cleared.</description>
35566                  <bitRange>[5:5]</bitRange>
35567                  <access>read-only</access>
35568                </field>
35569                <field>
35570                  <name>RX_U3</name>
35571                  <description>LGO_U3 Received - Request to go to U3 Power State, clear to NAK (send LXU)
35572This bit is cleared by h/w concurrent with TX_LAU/TX_LXU being cleared.
35573Note that an upstream port is not allowed to reject entry to U3.
35574[USB 3.0:  7.2.4.2.4, p 7-25]</description>
35575                  <bitRange>[6:6]</bitRange>
35576                  <access>read-only</access>
35577                </field>
35578                <field>
35579                  <name>TX_LAU</name>
35580                  <description>Transmit LAU (ACK) in response to RX_U1/RX_U2/RX_U3.
35581Transition to requested power state (LTSSM)
35582This bit is cleared when the acknowledgement is sent.</description>
35583                  <bitRange>[7:7]</bitRange>
35584                  <access>read-write</access>
35585                </field>
35586                <field>
35587                  <name>TX_LXU</name>
35588                  <description>Transmit LXU (NAK) in response to RX_U1/RX_U2/RX_U3.
35589Do not transition to requested power state (LTSSM)
35590This bit is cleared when the acknowledgement is sent.</description>
35591                  <bitRange>[8:8]</bitRange>
35592                  <access>read-write</access>
35593                </field>
35594                <field>
35595                  <name>EXIT_LP</name>
35596                  <description>Exit Low Power State
35597This bit is cleared by h/w when the Link Layer has exited U1/U2/U3.</description>
35598                  <bitRange>[9:9]</bitRange>
35599                  <access>read-write</access>
35600                </field>
35601                <field>
35602                  <name>AUTO_U1</name>
35603                  <description>When host requests transition to U1, automatically accept (send LAU) or rejects (send LXU) depending on pending activity.  The interrupt RX_U1 is still raised for firmware to monitor, take additional power saving actions.</description>
35604                  <bitRange>[26:26]</bitRange>
35605                  <access>read-write</access>
35606                </field>
35607                <field>
35608                  <name>AUTO_U2</name>
35609                  <description>When host requests transition to U2, automatically accept (send LAU) or rejects (send LXU) depending on pending activity. The interrupt RX_U2 is still raised for firmware to monitor, take additional power saving actions.</description>
35610                  <bitRange>[27:27]</bitRange>
35611                  <access>read-write</access>
35612                </field>
35613                <field>
35614                  <name>NO_U1</name>
35615                  <description>When host requests transition to U1, automatically reject (send LXU).
35616The interrupt RX_U1 is still raised for firmware to monitor, take additional actions.
35617This bit must be cleared by firmware when FORCE_PM_ACCEPT is received from host.</description>
35618                  <bitRange>[28:28]</bitRange>
35619                  <access>read-write</access>
35620                </field>
35621                <field>
35622                  <name>NO_U2</name>
35623                  <description>When host requests transition to U2, automatically reject (send LXU).
35624The interrupt RX_U2 is still raised for firmware to monitor, take additional actions. This bit must be cleared by firmware when FORCE_PM_ACCEPT is received from host.</description>
35625                  <bitRange>[29:29]</bitRange>
35626                  <access>read-write</access>
35627                </field>
35628                <field>
35629                  <name>YES_U1</name>
35630                  <description>When host requests transition to U1, automatically accept (send LAU).
35631The interrupt RX_U1 is still raised for firmware to monitor, take additional power saving actions.</description>
35632                  <bitRange>[30:30]</bitRange>
35633                  <access>read-write</access>
35634                </field>
35635                <field>
35636                  <name>YES_U2</name>
35637                  <description>When host requests transition to U2, automatically accept (send LAU).
35638The interrupt RX_U2 is still raised for firmware to monitor, take additional power saving actions.</description>
35639                  <bitRange>[31:31]</bitRange>
35640                  <access>read-write</access>
35641                </field>
35642              </fields>
35643            </register>
35644            <register>
35645              <name>LNK_LTSSM_STATE</name>
35646              <description>Link Training Status State Machine (LTSSM) State</description>
35647              <addressOffset>0x5C</addressOffset>
35648              <size>32</size>
35649              <access>read-write</access>
35650              <resetValue>0x0</resetValue>
35651              <resetMask>0x8003FFFF</resetMask>
35652              <fields>
35653                <field>
35654                  <name>LTSSM_STATE</name>
35655                  <description>LTSSM State
35656See USB3LNK_LTSSM Tab for more details.</description>
35657                  <bitRange>[5:0]</bitRange>
35658                  <access>read-only</access>
35659                </field>
35660                <field>
35661                  <name>LTSSM_OVERRIDE_VALUE</name>
35662                  <description>LTSSM State from FW (if LTSSM_OVERRIDE_ENABLE == 1 or LTSSM_OVERRIDE_GO == 1)</description>
35663                  <bitRange>[11:6]</bitRange>
35664                  <access>read-write</access>
35665                </field>
35666                <field>
35667                  <name>LTSSM_OVERRIDE_EN</name>
35668                  <description>FW Control of LTSSM State
35669Setting this bit will cause the LTSSM State Machine to transition to the state in LTSSM_OVERRIDE_VALUE and remain there.</description>
35670                  <bitRange>[12:12]</bitRange>
35671                  <access>read-write</access>
35672                </field>
35673                <field>
35674                  <name>LTSSM_OVERRIDE_GO</name>
35675                  <description>FW Setting of LTSSM State
35676Setting this bit will cause the LTSSM State Machine to transition to the value given in LTSSM_OVERRIDE_VALUE, but the state machine will not be held there and may transition to other states as dictated by the logic
35677To enable the U0 force entry:
35678// This is for Powerdown as 0
35679      regacc.regrd_n('USB32DEV_LNK_LNK_PHY_CONF', rd_data);
35680      wr_data = rd_data ;
35681      wr_data[17] = 'd1 ;
35682      wr_data[19:18] = 'd0  ;
35683      regacc.regwr_n('USB32DEV_LNK_LNK_PHY_CONF', wr_data);
35684// This is for U0 LTSSM
35685      regacc.regrd_n('USB32DEV_LNK_LNK_LTSSM_STATE', rd_data);
35686      wr_data = rd_data ;
35687      wr_data[11:6] = 'd16 ;
35688      wr_data[12]   = 'd1  ;
35689      regacc.regwr_n('USB32DEV_LNK_LNK_LTSSM_STATE', wr_data);
35690// Wait
35691      #0.5us ;
35692// Here enable is de-asserted and go is asserted
35693      regacc.regrd_n('USB32DEV_LNK_LNK_LTSSM_STATE', rd_data);
35694      wr_data = rd_data ;
35695      wr_data[11:6] = 'd16 ;
35696      wr_data[12]   = 'd0  ;
35697      wr_data[13]   = 'd1  ;
35698      regacc.regwr_n('USB32DEV_LNK_LNK_LTSSM_STATE', wr_data);</description>
35699                  <bitRange>[13:13]</bitRange>
35700                  <access>read-write</access>
35701                </field>
35702                <field>
35703                  <name>LOOPBACK_MASTER</name>
35704                  <description>Loopback Master Enable
35705When transmitting TS2 ordered sets in Polling or Recovery State, the Link Layer Block will enter the Loopback State as the Loopback Master if this bit is set.  The Link Layer Block will then exit the Loopback State when this bit is cleared.
35706[USB 3.0:  7.5.4.6.1, p 7-45;  7.5.10.5.2, p 7-55]</description>
35707                  <bitRange>[14:14]</bitRange>
35708                  <access>read-write</access>
35709                </field>
35710                <field>
35711                  <name>DISABLE_SCRAMBLING</name>
35712                  <description>Scrambling Disable
35713When transmitting TS2 ordered sets in Polling or Recovery State, the Link Layer Block will set the Disable Scrambling bit.
35714[USB 3.0:  7.5.4.6.1, p 7-45]</description>
35715                  <bitRange>[15:15]</bitRange>
35716                  <access>read-write</access>
35717                </field>
35718                <field>
35719                  <name>LOOPBACK_ERROR</name>
35720                  <description>Loopback Master Error Detected</description>
35721                  <bitRange>[16:16]</bitRange>
35722                  <access>read-only</access>
35723                </field>
35724                <field>
35725                  <name>LOOPBACK_GOOD</name>
35726                  <description>Loopback Master Good
35727Transmit sequence is being received correctly.</description>
35728                  <bitRange>[17:17]</bitRange>
35729                  <access>read-only</access>
35730                </field>
35731                <field>
35732                  <name>LTSSM_FREEZE</name>
35733                  <description>Freeze LTSSM to allow FW to inspect its current state.
35734Setting this bit will cease all header packet transmission.  Incoming header packets will still be received and acknowledged but no more header packets will be accepted for transmission from the protocol layer.  It is expected that soon after this bit is set RX a queue will fill up and become stable for firmware to inspect.</description>
35735                  <bitRange>[31:31]</bitRange>
35736                  <access>read-write</access>
35737                </field>
35738              </fields>
35739            </register>
35740            <register>
35741              <name>LNK_LOOPBACK_INIT</name>
35742              <description>Loopback LFSR Initial Value</description>
35743              <addressOffset>0x60</addressOffset>
35744              <size>32</size>
35745              <access>read-write</access>
35746              <resetValue>0x1</resetValue>
35747              <resetMask>0xFFFFFFFF</resetMask>
35748              <fields>
35749                <field>
35750                  <name>INIT</name>
35751                  <description>Initial value for Loopback LFSR Transmitter</description>
35752                  <bitRange>[31:0]</bitRange>
35753                  <access>read-write</access>
35754                </field>
35755              </fields>
35756            </register>
35757            <register>
35758              <name>LNK_LOOPBACK_GENERATOR</name>
35759              <description>Loopback LFSR Transmitter Generator Polynomial</description>
35760              <addressOffset>0x64</addressOffset>
35761              <size>32</size>
35762              <access>read-write</access>
35763              <resetValue>0xC0000030</resetValue>
35764              <resetMask>0xFFFFFFFF</resetMask>
35765              <fields>
35766                <field>
35767                  <name>GENERATOR</name>
35768                  <description>Generator Polynomial for Loopback LFSR Transmitter</description>
35769                  <bitRange>[31:0]</bitRange>
35770                  <access>read-write</access>
35771                </field>
35772              </fields>
35773            </register>
35774            <register>
35775              <name>LNK_LTSSM_OBSERVE</name>
35776              <description>Link Training Status State Machine (LTSSM) Observation</description>
35777              <addressOffset>0x68</addressOffset>
35778              <size>32</size>
35779              <access>read-write</access>
35780              <resetValue>0x4080</resetValue>
35781              <resetMask>0xDFFFFFFF</resetMask>
35782              <fields>
35783                <field>
35784                  <name>RX_DETECT_MISS_CNT</name>
35785                  <description>Number of RxDetect events where no termination was detected since last RxDetect event</description>
35786                  <bitRange>[3:0]</bitRange>
35787                  <access>read-only</access>
35788                </field>
35789                <field>
35790                  <name>RX_DETECT_MISS_LIMIT</name>
35791                  <description>Number of RxDetect attempts before giving up (default 8x as per spec)</description>
35792                  <bitRange>[7:4]</bitRange>
35793                  <access>read-write</access>
35794                </field>
35795                <field>
35796                  <name>RECOVERY_CNT</name>
35797                  <description>Number of Recovery attempts from U0 since last entering U0</description>
35798                  <bitRange>[11:8]</bitRange>
35799                  <access>read-only</access>
35800                </field>
35801                <field>
35802                  <name>RECOVERY_LIMIT</name>
35803                  <description>Number of Recovery attempts before going to SS.Inactive from U0 (default 4x as per spec).</description>
35804                  <bitRange>[15:12]</bitRange>
35805                  <access>read-write</access>
35806                </field>
35807                <field>
35808                  <name>TS1_RCVD_CNT</name>
35809                  <description>Number of TS1 Ordered Sets received since last Polling state entry</description>
35810                  <bitRange>[19:16]</bitRange>
35811                  <access>read-only</access>
35812                </field>
35813                <field>
35814                  <name>TS2_RCVD_CNT</name>
35815                  <description>Number of TS2 Ordered Sets received since last Polling/HotReset state entry</description>
35816                  <bitRange>[23:20]</bitRange>
35817                  <access>read-only</access>
35818                </field>
35819                <field>
35820                  <name>IDLE_RCVD_CNT</name>
35821                  <description>Number of Idle Symbols Received since last HotReset entry</description>
35822                  <bitRange>[27:24]</bitRange>
35823                  <access>read-only</access>
35824                </field>
35825                <field>
35826                  <name>POLLING_LFPS_COMPLETED</name>
35827                  <description>Indicates whether a Polling.LFPS sequence has ever been completed since the last UIB Block Reset or VBUS Off/On event</description>
35828                  <bitRange>[28:28]</bitRange>
35829                  <access>read-only</access>
35830                </field>
35831                <field>
35832                  <name>DATA_RATE_CONFIG</name>
35833                  <description>00: GEN1x1
3583401: GEN1x2
3583510: GEN2x1
3583611: GEN2x2</description>
35837                  <bitRange>[31:30]</bitRange>
35838                  <access>read-only</access>
35839                </field>
35840              </fields>
35841            </register>
35842            <register>
35843              <name>LNK_LFPS_OBSERVE</name>
35844              <description>LFPS Receiver Observability</description>
35845              <addressOffset>0x6C</addressOffset>
35846              <size>32</size>
35847              <access>read-write</access>
35848              <resetValue>0x0</resetValue>
35849              <resetMask>0x3FF0FFF</resetMask>
35850              <fields>
35851                <field>
35852                  <name>POLLING_DET</name>
35853                  <description>LFPS Sequence detected since last cleared by CPU</description>
35854                  <bitRange>[0:0]</bitRange>
35855                  <access>read-write</access>
35856                </field>
35857                <field>
35858                  <name>PING_DET</name>
35859                  <description>LFPS Sequence detected since last cleared by CPU</description>
35860                  <bitRange>[1:1]</bitRange>
35861                  <access>read-write</access>
35862                </field>
35863                <field>
35864                  <name>RESET_DET</name>
35865                  <description>LFPS Sequence detected since last cleared by CPU</description>
35866                  <bitRange>[2:2]</bitRange>
35867                  <access>read-write</access>
35868                </field>
35869                <field>
35870                  <name>U1_EXIT_DET</name>
35871                  <description>LFPS Sequence detected since last cleared by CPU</description>
35872                  <bitRange>[3:3]</bitRange>
35873                  <access>read-write</access>
35874                </field>
35875                <field>
35876                  <name>U2_EXIT_DET</name>
35877                  <description>LFPS Sequence detected since last cleared by CPU</description>
35878                  <bitRange>[4:4]</bitRange>
35879                  <access>read-write</access>
35880                </field>
35881                <field>
35882                  <name>U3_EXIT_DET</name>
35883                  <description>LFPS Sequence detected since last cleared by CPU</description>
35884                  <bitRange>[5:5]</bitRange>
35885                  <access>read-write</access>
35886                </field>
35887                <field>
35888                  <name>LOOPBACK_DET</name>
35889                  <description>LFPS Sequence detected since last cleared by CPU</description>
35890                  <bitRange>[6:6]</bitRange>
35891                  <access>read-write</access>
35892                </field>
35893                <field>
35894                  <name>SCD1_DET</name>
35895                  <description>LFPS Sequence detected since last cleared by CPU</description>
35896                  <bitRange>[7:7]</bitRange>
35897                  <access>read-write</access>
35898                </field>
35899                <field>
35900                  <name>SCD2_DET</name>
35901                  <description>LFPS Sequence detected since last cleared by CPU</description>
35902                  <bitRange>[8:8]</bitRange>
35903                  <access>read-write</access>
35904                </field>
35905                <field>
35906                  <name>PHY_CAP_LBPM_10G_DET</name>
35907                  <description>LFPS Sequence detected since last cleared by CPU</description>
35908                  <bitRange>[9:9]</bitRange>
35909                  <access>read-write</access>
35910                </field>
35911                <field>
35912                  <name>PHY_CAP_LBPM_5G_DET</name>
35913                  <description>LFPS Sequence detected since last cleared by CPU</description>
35914                  <bitRange>[10:10]</bitRange>
35915                  <access>read-write</access>
35916                </field>
35917                <field>
35918                  <name>PHY_READY_LBPM_DET</name>
35919                  <description>LFPS Sequence detected since last cleared by CPU</description>
35920                  <bitRange>[11:11]</bitRange>
35921                  <access>read-write</access>
35922                </field>
35923                <field>
35924                  <name>POLLING_LFPS_RCVD</name>
35925                  <description>Number of LFPS Polling Bursts Received since last Polling.LFPS entry</description>
35926                  <bitRange>[20:16]</bitRange>
35927                  <access>read-only</access>
35928                </field>
35929                <field>
35930                  <name>POLLING_LFPS_SENT</name>
35931                  <description>Number of LFPS Polling Bursts Sent since last Polling.LFPS entry</description>
35932                  <bitRange>[25:21]</bitRange>
35933                  <access>read-only</access>
35934                </field>
35935              </fields>
35936            </register>
35937            <register>
35938              <name>LNK_LFPS_TX_POLLING_BURST</name>
35939              <description>LFPS Polling Transmit Configuration</description>
35940              <addressOffset>0x70</addressOffset>
35941              <size>32</size>
35942              <access>read-write</access>
35943              <resetValue>0x7D</resetValue>
35944              <resetMask>0xFFFF</resetMask>
35945              <fields>
35946                <field>
35947                  <name>BURST16</name>
35948                  <description>Clock periods for LFPS Burst, when LFPS signalling is transmitted  (default:  1.0us)</description>
35949                  <bitRange>[15:0]</bitRange>
35950                  <access>read-write</access>
35951                </field>
35952              </fields>
35953            </register>
35954            <register>
35955              <name>LNK_LFPS_TX_POLLING_REPEAT</name>
35956              <description>LFPS Polling Transmit Configuration</description>
35957              <addressOffset>0x74</addressOffset>
35958              <size>32</size>
35959              <access>read-write</access>
35960              <resetValue>0x4E2</resetValue>
35961              <resetMask>0xFFFF</resetMask>
35962              <fields>
35963                <field>
35964                  <name>REPEAT16</name>
35965                  <description>Clock periods for LFPS Repeat, the time between LFPS Bursts  (default:  10.0 us)</description>
35966                  <bitRange>[15:0]</bitRange>
35967                  <access>read-write</access>
35968                </field>
35969              </fields>
35970            </register>
35971            <register>
35972              <name>LNK_LFPS_TX_PING_BURST</name>
35973              <description>LFPS Ping Transmit Configuration</description>
35974              <addressOffset>0x78</addressOffset>
35975              <size>32</size>
35976              <access>read-write</access>
35977              <resetValue>0xF</resetValue>
35978              <resetMask>0xFFFF</resetMask>
35979              <fields>
35980                <field>
35981                  <name>BURST16</name>
35982                  <description>Clock periods for Ping.LFPS Burst signalling transmission  (default:  120 ns)
35983SS: range of (40ns, 200ns)</description>
35984                  <bitRange>[15:0]</bitRange>
35985                  <access>read-write</access>
35986                </field>
35987              </fields>
35988            </register>
35989            <register>
35990              <name>LNK_LFPS_TX_PING_REPEAT</name>
35991              <description>LFPS Ping Transmit Configuration</description>
35992              <addressOffset>0x7C</addressOffset>
35993              <size>32</size>
35994              <access>read-write</access>
35995              <resetValue>0x17D7840</resetValue>
35996              <resetMask>0xFFFFFFFF</resetMask>
35997              <fields>
35998                <field>
35999                  <name>REPEAT32</name>
36000                  <description>Clock periods for LFPS Repeat</description>
36001                  <bitRange>[31:0]</bitRange>
36002                  <access>read-write</access>
36003                </field>
36004              </fields>
36005            </register>
36006            <register>
36007              <name>LNK_LFPS_TX_U1_EXIT</name>
36008              <description>LFPS U1_EXIT Transmit Configuration</description>
36009              <addressOffset>0x80</addressOffset>
36010              <size>32</size>
36011              <access>read-write</access>
36012              <resetValue>0x71</resetValue>
36013              <resetMask>0xFFFF</resetMask>
36014              <fields>
36015                <field>
36016                  <name>BURST16</name>
36017                  <description>Number of clock periods for LFPS Burst transmission  (default:  904 ns)</description>
36018                  <bitRange>[15:0]</bitRange>
36019                  <access>read-write</access>
36020                </field>
36021              </fields>
36022            </register>
36023            <register>
36024              <name>LNK_LFPS_TX_U2_EXIT</name>
36025              <description>LFPS U2_EXIT Transmit Configuration</description>
36026              <addressOffset>0x84</addressOffset>
36027              <size>32</size>
36028              <access>read-write</access>
36029              <resetValue>0x2710</resetValue>
36030              <resetMask>0xFFFFFF</resetMask>
36031              <fields>
36032                <field>
36033                  <name>BURST24</name>
36034                  <description>Minimum number of clock periods for LFPS Burst transmission  (default:  80 us)</description>
36035                  <bitRange>[23:0]</bitRange>
36036                  <access>read-write</access>
36037                </field>
36038              </fields>
36039            </register>
36040            <register>
36041              <name>LNK_LFPS_TX_U3_EXIT</name>
36042              <description>LFPS U3 Exit Transmit Configuration</description>
36043              <addressOffset>0x88</addressOffset>
36044              <size>32</size>
36045              <access>read-write</access>
36046              <resetValue>0x2710</resetValue>
36047              <resetMask>0xFFFFFF</resetMask>
36048              <fields>
36049                <field>
36050                  <name>BURST24</name>
36051                  <description>Minimum number of clock periods for LFPS Burst transmission (default: 80 us)</description>
36052                  <bitRange>[23:0]</bitRange>
36053                  <access>read-write</access>
36054                </field>
36055              </fields>
36056            </register>
36057            <register>
36058              <name>LNK_LFPS_RX_POLLING_BURST</name>
36059              <description>LFPS Polling Detect Configuration</description>
36060              <addressOffset>0x8C</addressOffset>
36061              <size>32</size>
36062              <access>read-write</access>
36063              <resetValue>0xAF004B</resetValue>
36064              <resetMask>0xFFFFFFFF</resetMask>
36065              <fields>
36066                <field>
36067                  <name>BURST_MIN</name>
36068                  <description>Minimum number of clock periods for detection of Polling.LFPS Burst  (default:  0.6 us)</description>
36069                  <bitRange>[15:0]</bitRange>
36070                  <access>read-write</access>
36071                </field>
36072                <field>
36073                  <name>BURST_MAX</name>
36074                  <description>Maximum number of clock periods for detection of Polling.LFPS Burst  (default:  1.4 us)</description>
36075                  <bitRange>[31:16]</bitRange>
36076                  <access>read-write</access>
36077                </field>
36078              </fields>
36079            </register>
36080            <register>
36081              <name>LNK_LFPS_RX_POLLING_REPEAT</name>
36082              <description>LFPS Polling Detect Configuration</description>
36083              <addressOffset>0x90</addressOffset>
36084              <size>32</size>
36085              <access>read-write</access>
36086              <resetValue>0x6D602EE</resetValue>
36087              <resetMask>0xFFFFFFFF</resetMask>
36088              <fields>
36089                <field>
36090                  <name>REPEAT_MIN</name>
36091                  <description>Minimum number of clock periods of idle (non-LFPS) time between LFPS Bursts for detection of Polling.LFPS signalling  (default:  6 us)</description>
36092                  <bitRange>[15:0]</bitRange>
36093                  <access>read-write</access>
36094                </field>
36095                <field>
36096                  <name>REPEAT_MAX</name>
36097                  <description>Maximum number of clock periods of idle (non-LFPS) time between LFPS Bursts for detection of Polling.LFPS signalling  (default:  14 us)</description>
36098                  <bitRange>[31:16]</bitRange>
36099                  <access>read-write</access>
36100                </field>
36101              </fields>
36102            </register>
36103            <register>
36104              <name>LNK_LFPS_RX_PING</name>
36105              <description>LFPS Ping Detect Configuration</description>
36106              <addressOffset>0x94</addressOffset>
36107              <size>32</size>
36108              <access>read-write</access>
36109              <resetValue>0x190005</resetValue>
36110              <resetMask>0xFFFFFFFF</resetMask>
36111              <fields>
36112                <field>
36113                  <name>BURST_MIN</name>
36114                  <description>Minimum number of clock periods for detection of Ping.LFPS Burst  (default: 40 ns)</description>
36115                  <bitRange>[15:0]</bitRange>
36116                  <access>read-write</access>
36117                </field>
36118                <field>
36119                  <name>BURST_MAX</name>
36120                  <description>Maximum number of clock periods for detection of Ping.LFPS Burst  (default:  200 ns)</description>
36121                  <bitRange>[31:16]</bitRange>
36122                  <access>read-write</access>
36123                </field>
36124              </fields>
36125            </register>
36126            <register>
36127              <name>LNK_LFPS_RX_RESET</name>
36128              <description>LFPS Reset Detect Configuration</description>
36129              <addressOffset>0x98</addressOffset>
36130              <size>32</size>
36131              <access>read-write</access>
36132              <resetValue>0x989680</resetValue>
36133              <resetMask>0xFFFFFF</resetMask>
36134              <fields>
36135                <field>
36136                  <name>BURST24</name>
36137                  <description>Minimum number of clock periods for detection
36138(default: 80ms)</description>
36139                  <bitRange>[23:0]</bitRange>
36140                  <access>read-write</access>
36141                </field>
36142              </fields>
36143            </register>
36144            <register>
36145              <name>LNK_LFPS_RX_U1_EXIT</name>
36146              <description>LFPS U1 Exit Detect Configuration</description>
36147              <addressOffset>0x9C</addressOffset>
36148              <size>32</size>
36149              <access>read-write</access>
36150              <resetValue>0x26</resetValue>
36151              <resetMask>0xFFFF</resetMask>
36152              <fields>
36153                <field>
36154                  <name>BURST16</name>
36155                  <description>Minimum number of clock periods for U1 Exit Burst detection  (default:  304 ns)</description>
36156                  <bitRange>[15:0]</bitRange>
36157                  <access>read-write</access>
36158                </field>
36159              </fields>
36160            </register>
36161            <register>
36162              <name>LNK_LFPS_RX_U2_EXIT</name>
36163              <description>LFPS U2 Exit Detect Configuration</description>
36164              <addressOffset>0xA0</addressOffset>
36165              <size>32</size>
36166              <access>read-write</access>
36167              <resetValue>0x2710</resetValue>
36168              <resetMask>0xFFFFFF</resetMask>
36169              <fields>
36170                <field>
36171                  <name>BURST24</name>
36172                  <description>Minimum number of clock periods for U2 Exit Burst detection  (default:  80 us)</description>
36173                  <bitRange>[23:0]</bitRange>
36174                  <access>read-write</access>
36175                </field>
36176              </fields>
36177            </register>
36178            <register>
36179              <name>LNK_LFPS_RX_U3_EXIT</name>
36180              <description>LFPS U3 Exit Detect Configuration</description>
36181              <addressOffset>0xA4</addressOffset>
36182              <size>32</size>
36183              <access>read-write</access>
36184              <resetValue>0x2</resetValue>
36185              <resetMask>0xFFFF</resetMask>
36186              <fields>
36187                <field>
36188                  <name>BURST16</name>
36189                  <description>Minimum number of clock periods for detection
36190(default: 62.5us)</description>
36191                  <bitRange>[15:0]</bitRange>
36192                  <access>read-write</access>
36193                </field>
36194              </fields>
36195            </register>
36196            <register>
36197              <name>LNK_LFPS_RX_U1_HANDSHAKE</name>
36198              <description>LFPS U1 Exit Handshake Configuration</description>
36199              <addressOffset>0xA8</addressOffset>
36200              <size>32</size>
36201              <access>read-write</access>
36202              <resetValue>0x26</resetValue>
36203              <resetMask>0xFFFF</resetMask>
36204              <fields>
36205                <field>
36206                  <name>BURST16</name>
36207                  <description>Minimum number of clock periods for LFPS handshake detection (default: 304 ns)</description>
36208                  <bitRange>[15:0]</bitRange>
36209                  <access>read-write</access>
36210                </field>
36211              </fields>
36212            </register>
36213            <register>
36214              <name>LNK_LFPS_RX_U2_HANDSHAKE</name>
36215              <description>LFPS U2 Exit Handshake Configuration</description>
36216              <addressOffset>0xAC</addressOffset>
36217              <size>32</size>
36218              <access>read-write</access>
36219              <resetValue>0x2710</resetValue>
36220              <resetMask>0xFFFFFF</resetMask>
36221              <fields>
36222                <field>
36223                  <name>BURST24</name>
36224                  <description>Minimum number of clock periods for LFPS handshake detection (default: 80 us)</description>
36225                  <bitRange>[23:0]</bitRange>
36226                  <access>read-write</access>
36227                </field>
36228              </fields>
36229            </register>
36230            <register>
36231              <name>LNK_LFPS_RX_U3_HANDSHAKE</name>
36232              <description>LFPS U3 Exit Handshake Configuration</description>
36233              <addressOffset>0xB0</addressOffset>
36234              <size>32</size>
36235              <access>read-write</access>
36236              <resetValue>0x2710</resetValue>
36237              <resetMask>0xFFFFFF</resetMask>
36238              <fields>
36239                <field>
36240                  <name>BURST24</name>
36241                  <description>Minimum number of clock periods for LFPS handshake detection (default: 80 us)</description>
36242                  <bitRange>[23:0]</bitRange>
36243                  <access>read-write</access>
36244                </field>
36245              </fields>
36246            </register>
36247            <register>
36248              <name>LNK_LFPS_RX_LOOPBACK_EXIT</name>
36249              <description>LFPS Loopback Exit Detect Configuration</description>
36250              <addressOffset>0xB4</addressOffset>
36251              <size>32</size>
36252              <access>read-write</access>
36253              <resetValue>0x2710</resetValue>
36254              <resetMask>0xFFFFFF</resetMask>
36255              <fields>
36256                <field>
36257                  <name>BURST24</name>
36258                  <description>Minimum number of clock periods for detection
36259(default: 80us)</description>
36260                  <bitRange>[23:0]</bitRange>
36261                  <access>read-write</access>
36262                </field>
36263              </fields>
36264            </register>
36265            <register>
36266              <name>LNK_LFPS_RX_LOOPBACK_HANDSHAKE</name>
36267              <description>LFPS Loopback Exit Handshake Configuration</description>
36268              <addressOffset>0xB8</addressOffset>
36269              <size>32</size>
36270              <access>read-write</access>
36271              <resetValue>0x2710</resetValue>
36272              <resetMask>0xFFFFFF</resetMask>
36273              <fields>
36274                <field>
36275                  <name>BURST24</name>
36276                  <description>Minimum number of clock periods for LFPS handshake detection (default: 80 us)</description>
36277                  <bitRange>[23:0]</bitRange>
36278                  <access>read-write</access>
36279                </field>
36280              </fields>
36281            </register>
36282            <register>
36283              <name>LNK_LFPS_RX_IDLE</name>
36284              <description>LFPS Idle Time</description>
36285              <addressOffset>0xBC</addressOffset>
36286              <size>32</size>
36287              <access>read-only</access>
36288              <resetValue>0x0</resetValue>
36289              <resetMask>0xFFFFFFFF</resetMask>
36290              <fields>
36291                <field>
36292                  <name>TIME</name>
36293                  <description>Idle time before last LFPS burst</description>
36294                  <bitRange>[31:0]</bitRange>
36295                  <access>read-only</access>
36296                </field>
36297              </fields>
36298            </register>
36299            <register>
36300              <name>LNK_LFPS_RX_BURST</name>
36301              <description>LFPS Burst Length</description>
36302              <addressOffset>0xC0</addressOffset>
36303              <size>32</size>
36304              <access>read-only</access>
36305              <resetValue>0x0</resetValue>
36306              <resetMask>0xFFFFFFFF</resetMask>
36307              <fields>
36308                <field>
36309                  <name>TIME</name>
36310                  <description>Last LFPS burst length</description>
36311                  <bitRange>[31:0]</bitRange>
36312                  <access>read-only</access>
36313                </field>
36314              </fields>
36315            </register>
36316            <register>
36317              <name>LNK_LFPS_RX_TIME</name>
36318              <description>LFPS Idle Counter</description>
36319              <addressOffset>0xC4</addressOffset>
36320              <size>32</size>
36321              <access>read-only</access>
36322              <resetValue>0x0</resetValue>
36323              <resetMask>0xFFFFFFFF</resetMask>
36324              <fields>
36325                <field>
36326                  <name>TIME</name>
36327                  <description>Time since end of last LFPS burst</description>
36328                  <bitRange>[31:0]</bitRange>
36329                  <access>read-only</access>
36330                </field>
36331              </fields>
36332            </register>
36333            <register>
36334              <name>LNK_PENDING_HP_TIMER</name>
36335              <description>Header Packet LGOOD/LBAD Timer</description>
36336              <addressOffset>0xC8</addressOffset>
36337              <size>32</size>
36338              <access>read-only</access>
36339              <resetValue>0x0</resetValue>
36340              <resetMask>0xFFFF</resetMask>
36341              <fields>
36342                <field>
36343                  <name>TIMER16</name>
36344                  <description>PENDING_HP_TIMER Value</description>
36345                  <bitRange>[15:0]</bitRange>
36346                  <access>read-only</access>
36347                </field>
36348              </fields>
36349            </register>
36350            <register>
36351              <name>LNK_PENDING_HP_TIMEOUT</name>
36352              <description>Header Packet LGOOD/LBAD Timeout</description>
36353              <addressOffset>0xCC</addressOffset>
36354              <size>32</size>
36355              <access>read-write</access>
36356              <resetValue>0x4E2</resetValue>
36357              <resetMask>0xFFFF</resetMask>
36358              <fields>
36359                <field>
36360                  <name>TIMEOUT16</name>
36361                  <description>PENDING_HP_TIMER Timeout (default: 10 us)  [default:  table 7-7, p 7-22]
36362(0= Timer Disabled)</description>
36363                  <bitRange>[15:0]</bitRange>
36364                  <access>read-write</access>
36365                </field>
36366              </fields>
36367            </register>
36368            <register>
36369              <name>LNK_CREDIT_HP_TIMER</name>
36370              <description>Header Packet LCRDx Timer</description>
36371              <addressOffset>0xD0</addressOffset>
36372              <size>32</size>
36373              <access>read-only</access>
36374              <resetValue>0x0</resetValue>
36375              <resetMask>0xFFFFFFFF</resetMask>
36376              <fields>
36377                <field>
36378                  <name>TIMER</name>
36379                  <description>CREDIT_HP_TIMER Value</description>
36380                  <bitRange>[31:0]</bitRange>
36381                  <access>read-only</access>
36382                </field>
36383              </fields>
36384            </register>
36385            <register>
36386              <name>LNK_CREDIT_HP_TIMEOUT</name>
36387              <description>Header Packet LCRDx Timeout</description>
36388              <addressOffset>0xD4</addressOffset>
36389              <size>32</size>
36390              <access>read-write</access>
36391              <resetValue>0x98968</resetValue>
36392              <resetMask>0xFFFFFFFF</resetMask>
36393              <fields>
36394                <field>
36395                  <name>TIMEOUT</name>
36396                  <description>CREDIT_HP_TIMER Timeout (default: 5 ms)  [default:  table 7-7, p 7-22]
36397(0= Timer Disabled)</description>
36398                  <bitRange>[31:0]</bitRange>
36399                  <access>read-write</access>
36400                </field>
36401              </fields>
36402            </register>
36403            <register>
36404              <name>LNK_PM_TIMER</name>
36405              <description>Power Mode Timer</description>
36406              <addressOffset>0xD8</addressOffset>
36407              <size>32</size>
36408              <access>read-only</access>
36409              <resetValue>0x0</resetValue>
36410              <resetMask>0xFFFFFFFF</resetMask>
36411              <fields>
36412                <field>
36413                  <name>TIMER</name>
36414                  <description>PM_TIMER Value</description>
36415                  <bitRange>[31:0]</bitRange>
36416                  <access>read-only</access>
36417                </field>
36418              </fields>
36419            </register>
36420            <register>
36421              <name>LNK_PM_LC_TIMEOUT</name>
36422              <description>Power Mode PM_LC_TIMER Timeout</description>
36423              <addressOffset>0xDC</addressOffset>
36424              <size>32</size>
36425              <access>read-write</access>
36426              <resetValue>0x1F4</resetValue>
36427              <resetMask>0xFFFF</resetMask>
36428              <fields>
36429                <field>
36430                  <name>TIMEOUT16</name>
36431                  <description>PM_LC_TIMER Gen1x1 Timeout (default: 4 us)
36432(0= Timer Disabled)</description>
36433                  <bitRange>[15:0]</bitRange>
36434                  <access>read-write</access>
36435                </field>
36436              </fields>
36437            </register>
36438            <register>
36439              <name>LNK_PM_ENTRY_TIMEOUT</name>
36440              <description>Power Mode PM_ENTRY_TIMER Timeout</description>
36441              <addressOffset>0xE0</addressOffset>
36442              <size>32</size>
36443              <access>read-write</access>
36444              <resetValue>0x3E8</resetValue>
36445              <resetMask>0xFFFF</resetMask>
36446              <fields>
36447                <field>
36448                  <name>TIMEOUT16</name>
36449                  <description>PM_ENTRY_TIMER Timeout (default: 8 us)
36450(0= Timer Disabled)</description>
36451                  <bitRange>[15:0]</bitRange>
36452                  <access>read-write</access>
36453                </field>
36454              </fields>
36455            </register>
36456            <register>
36457              <name>LNK_PM_UX_EXIT_TIMEOUT</name>
36458              <description>Power Mode Ux_EXIT_TIMER Timeout</description>
36459              <addressOffset>0xE4</addressOffset>
36460              <size>32</size>
36461              <access>read-write</access>
36462              <resetValue>0xB71B0</resetValue>
36463              <resetMask>0xFFFFFFFF</resetMask>
36464              <fields>
36465                <field>
36466                  <name>TIMEOUT</name>
36467                  <description>Ux_EXIT_TIMER Timeout (default: 6 ms)  [default:  table 7-8, p 7-23]
36468(0= Timer Disabled)</description>
36469                  <bitRange>[31:0]</bitRange>
36470                  <access>read-write</access>
36471                </field>
36472              </fields>
36473            </register>
36474            <register>
36475              <name>LNK_LTSSM_TIMER</name>
36476              <description>LTSSM Timer Register</description>
36477              <addressOffset>0xE8</addressOffset>
36478              <size>32</size>
36479              <access>read-only</access>
36480              <resetValue>0x0</resetValue>
36481              <resetMask>0xFFFFFFFF</resetMask>
36482              <fields>
36483                <field>
36484                  <name>TIMER</name>
36485                  <description>LTSSM State Transition Timer</description>
36486                  <bitRange>[31:0]</bitRange>
36487                  <access>read-only</access>
36488                </field>
36489              </fields>
36490            </register>
36491            <register>
36492              <name>LNK_LTSSM_TIMEOUT</name>
36493              <description>LTSSM Timeout Observability Register</description>
36494              <addressOffset>0xEC</addressOffset>
36495              <size>32</size>
36496              <access>read-write</access>
36497              <resetValue>0x0</resetValue>
36498              <resetMask>0x3FFF</resetMask>
36499              <fields>
36500                <field>
36501                  <name>POLLING_LFPS</name>
36502                  <description>LTSSM Polling LFPS Timeout</description>
36503                  <bitRange>[0:0]</bitRange>
36504                  <access>read-write</access>
36505                </field>
36506                <field>
36507                  <name>POLLING_ACTIVE</name>
36508                  <description>LTSSM Polling Active Timeout</description>
36509                  <bitRange>[1:1]</bitRange>
36510                  <access>read-write</access>
36511                </field>
36512                <field>
36513                  <name>POLLING_IDLE</name>
36514                  <description>LTSSM Polling Idle Timeout</description>
36515                  <bitRange>[2:2]</bitRange>
36516                  <access>read-write</access>
36517                </field>
36518                <field>
36519                  <name>U1_EXIT</name>
36520                  <description>LTSSM U1 Exit Timeout</description>
36521                  <bitRange>[3:3]</bitRange>
36522                  <access>read-write</access>
36523                </field>
36524                <field>
36525                  <name>U2_EXIT</name>
36526                  <description>LTSSM U2 Exit Timeout</description>
36527                  <bitRange>[4:4]</bitRange>
36528                  <access>read-write</access>
36529                </field>
36530                <field>
36531                  <name>U3_EXIT</name>
36532                  <description>LTSSM U3 Exit Timeout</description>
36533                  <bitRange>[5:5]</bitRange>
36534                  <access>read-write</access>
36535                </field>
36536                <field>
36537                  <name>HOT_RESET_ACTIVE</name>
36538                  <description>LTSSM Hot Reset Active Timeout</description>
36539                  <bitRange>[6:6]</bitRange>
36540                  <access>read-write</access>
36541                </field>
36542                <field>
36543                  <name>HOT_RESET_EXIT</name>
36544                  <description>LTSSM Hot Reset Exit Timeout</description>
36545                  <bitRange>[7:7]</bitRange>
36546                  <access>read-write</access>
36547                </field>
36548                <field>
36549                  <name>LOOPBACK_EXIT</name>
36550                  <description>LTSSM Loopback Exit Timeout</description>
36551                  <bitRange>[8:8]</bitRange>
36552                  <access>read-write</access>
36553                </field>
36554                <field>
36555                  <name>RECOVERY_IDLE</name>
36556                  <description>LTSSM Recovery Idle Timeout</description>
36557                  <bitRange>[9:9]</bitRange>
36558                  <access>read-write</access>
36559                </field>
36560                <field>
36561                  <name>RECOVERY_ACTIVE</name>
36562                  <description>LTSSM Recovery Active Timeout</description>
36563                  <bitRange>[10:10]</bitRange>
36564                  <access>read-write</access>
36565                </field>
36566                <field>
36567                  <name>RECOVERY_CONFIG</name>
36568                  <description>LTSSM Recovery Configuration Timeout</description>
36569                  <bitRange>[11:11]</bitRange>
36570                  <access>read-write</access>
36571                </field>
36572                <field>
36573                  <name>POLLING_SCD_LFPS</name>
36574                  <description>LTSSM Polling SCD LFPS Timeout</description>
36575                  <bitRange>[12:12]</bitRange>
36576                  <access>read-write</access>
36577                </field>
36578                <field>
36579                  <name>POLLING_LBPM_LFPS</name>
36580                  <description>LTSSM Polling LBPM Timeout</description>
36581                  <bitRange>[13:13]</bitRange>
36582                  <access>read-write</access>
36583                </field>
36584              </fields>
36585            </register>
36586            <register>
36587              <name>LNK_LTSSM_U2_TERM_DET_PERIOD</name>
36588              <description>LTSSM U2 Termination Detect Period</description>
36589              <addressOffset>0xF0</addressOffset>
36590              <size>32</size>
36591              <access>read-write</access>
36592              <resetValue>0x0</resetValue>
36593              <resetMask>0xFFFFFF</resetMask>
36594              <fields>
36595                <field>
36596                  <name>PERIOD24</name>
36597                  <description>Time between far-end receiver termination detection sequences in the U2 State (default:  off)
36598(0= Timer Disabled)</description>
36599                  <bitRange>[23:0]</bitRange>
36600                  <access>read-write</access>
36601                </field>
36602              </fields>
36603            </register>
36604            <register>
36605              <name>LNK_LTSSM_U3_TERM_DET_PERIOD</name>
36606              <description>LTSSM U3 Termination Detect Period</description>
36607              <addressOffset>0xF4</addressOffset>
36608              <size>32</size>
36609              <access>read-write</access>
36610              <resetValue>0x0</resetValue>
36611              <resetMask>0xFFFFFF</resetMask>
36612              <fields>
36613                <field>
36614                  <name>PERIOD24</name>
36615                  <description>Time between far-end receiver termination detection sequences in the U3 State (default:  off)
36616(0= Timer Disabled)</description>
36617                  <bitRange>[23:0]</bitRange>
36618                  <access>read-write</access>
36619                </field>
36620              </fields>
36621            </register>
36622            <register>
36623              <name>LNK_LTSSM_RX_DETECT_PERIOD</name>
36624              <description>LTSSM RxDetect Period</description>
36625              <addressOffset>0xF8</addressOffset>
36626              <size>32</size>
36627              <access>read-write</access>
36628              <resetValue>0x16E360</resetValue>
36629              <resetMask>0xFFFFFF</resetMask>
36630              <fields>
36631                <field>
36632                  <name>PERIOD24</name>
36633                  <description>LTSSM RxDetect.Quiet Period (default: 12 ms)  [default:  table 7-12, p 7-36]
36634(0= Timer Disabled)</description>
36635                  <bitRange>[23:0]</bitRange>
36636                  <access>read-write</access>
36637                </field>
36638              </fields>
36639            </register>
36640            <register>
36641              <name>LNK_LTSSM_LUP_PERIOD</name>
36642              <description>LTSSM LUP Period</description>
36643              <addressOffset>0xFC</addressOffset>
36644              <size>32</size>
36645              <access>read-write</access>
36646              <resetValue>0x4E2</resetValue>
36647              <resetMask>0xFFFFFF</resetMask>
36648              <fields>
36649                <field>
36650                  <name>PERIOD24</name>
36651                  <description>LTSSM U0 LUP Transmision Interval (default: 10 us)  [default:  table7.5.6.1, p 7-48]
36652(0= Timer Disabled)</description>
36653                  <bitRange>[23:0]</bitRange>
36654                  <access>read-write</access>
36655                </field>
36656              </fields>
36657            </register>
36658            <register>
36659              <name>LNK_LTSSM_SS_INACTIVE_PERIOD</name>
36660              <description>LTSSM SS.Inactive Timeout</description>
36661              <addressOffset>0x100</addressOffset>
36662              <size>32</size>
36663              <access>read-write</access>
36664              <resetValue>0x16E360</resetValue>
36665              <resetMask>0xFFFFFF</resetMask>
36666              <fields>
36667                <field>
36668                  <name>PERIOD24</name>
36669                  <description>LTSSM SS.Inactive.Quiet timeout (default: 12ms)
36670(0= Timer Disabled)</description>
36671                  <bitRange>[23:0]</bitRange>
36672                  <access>read-write</access>
36673                </field>
36674              </fields>
36675            </register>
36676            <register>
36677              <name>LNK_LTSSM_POLLING_LFPS_TIMEOUT</name>
36678              <description>LTSSM Polling LFPS Timeout</description>
36679              <addressOffset>0x104</addressOffset>
36680              <size>32</size>
36681              <access>read-write</access>
36682              <resetValue>0x2AEA540</resetValue>
36683              <resetMask>0xFFFFFFFF</resetMask>
36684              <fields>
36685                <field>
36686                  <name>TIMEOUT</name>
36687                  <description>LTSSM Polling.LFPS Timeout (default: 360 ms)  [default:  table 7-12, p 7-36]
36688(0= Timer Disabled)</description>
36689                  <bitRange>[31:0]</bitRange>
36690                  <access>read-write</access>
36691                </field>
36692              </fields>
36693            </register>
36694            <register>
36695              <name>LNK_LTSSM_POLLING_ACTIVE_TIMEOUT</name>
36696              <description>LTSSM Polling Active Timeout</description>
36697              <addressOffset>0x108</addressOffset>
36698              <size>32</size>
36699              <access>read-write</access>
36700              <resetValue>0x16E360</resetValue>
36701              <resetMask>0xFFFFFF</resetMask>
36702              <fields>
36703                <field>
36704                  <name>TIMEOUT24</name>
36705                  <description>LTSSM Polling.Active Timeout (default: 12 ms)  [default:  table 7-12, p 7-36]
36706(0= Timer Disabled)</description>
36707                  <bitRange>[23:0]</bitRange>
36708                  <access>read-write</access>
36709                </field>
36710              </fields>
36711            </register>
36712            <register>
36713              <name>LNK_LTSSM_POLLING_CONFIG_TIMEOUT</name>
36714              <description>LTSSM Polling Configuration Timeout</description>
36715              <addressOffset>0x10C</addressOffset>
36716              <size>32</size>
36717              <access>read-write</access>
36718              <resetValue>0x16E360</resetValue>
36719              <resetMask>0xFFFFFF</resetMask>
36720              <fields>
36721                <field>
36722                  <name>TIMEOUT24</name>
36723                  <description>LTSSM Polling.Configuration Timeout (default: 12 ms)  [default:  table 7-12, p 7-36]
36724(0= Timer Disabled)</description>
36725                  <bitRange>[23:0]</bitRange>
36726                  <access>read-write</access>
36727                </field>
36728              </fields>
36729            </register>
36730            <register>
36731              <name>LNK_LTSSM_POLLING_IDLE_TIMEOUT</name>
36732              <description>LTSSM Polling Idle Timeout</description>
36733              <addressOffset>0x110</addressOffset>
36734              <size>32</size>
36735              <access>read-write</access>
36736              <resetValue>0x3D090</resetValue>
36737              <resetMask>0xFFFFFF</resetMask>
36738              <fields>
36739                <field>
36740                  <name>TIMEOUT24</name>
36741                  <description>LTSSM Polling.Idle Timeout (default: 2 ms)  [default:  table 7-12, p 7-36]
36742(0= Timer Disabled)</description>
36743                  <bitRange>[23:0]</bitRange>
36744                  <access>read-write</access>
36745                </field>
36746              </fields>
36747            </register>
36748            <register>
36749              <name>LNK_LTSSM_U1_EXIT_TIMEOUT</name>
36750              <description>LTSSM U1 Exit Timeout</description>
36751              <addressOffset>0x114</addressOffset>
36752              <size>32</size>
36753              <access>read-write</access>
36754              <resetValue>0x3D090</resetValue>
36755              <resetMask>0xFFFFFF</resetMask>
36756              <fields>
36757                <field>
36758                  <name>TIMEOUT24</name>
36759                  <description>LTSSM U1 Timeout (default: 2 ms) for LFPS Handshake  [default:  table 7-12, p 7-36]
36760(0= Timer Disabled)</description>
36761                  <bitRange>[23:0]</bitRange>
36762                  <access>read-write</access>
36763                </field>
36764              </fields>
36765            </register>
36766            <register>
36767              <name>LNK_LTSSM_U2_EXIT_TIMEOUT</name>
36768              <description>LTSSM U2 Exit Timeout</description>
36769              <addressOffset>0x118</addressOffset>
36770              <size>32</size>
36771              <access>read-write</access>
36772              <resetValue>0x3D090</resetValue>
36773              <resetMask>0xFFFFFF</resetMask>
36774              <fields>
36775                <field>
36776                  <name>TIMEOUT24</name>
36777                  <description>LTSSM U2 Timeout (default: 2 ms) for LFPS Handshake  [default:  table 7-12, p 7-36]
36778(0= Timer Disabled)</description>
36779                  <bitRange>[23:0]</bitRange>
36780                  <access>read-write</access>
36781                </field>
36782              </fields>
36783            </register>
36784            <register>
36785              <name>LNK_LTSSM_U3_EXIT_TIMEOUT</name>
36786              <description>LTSSM U3 Exit Timeout</description>
36787              <addressOffset>0x11C</addressOffset>
36788              <size>32</size>
36789              <access>read-write</access>
36790              <resetValue>0x1E848</resetValue>
36791              <resetMask>0xFFFFFF</resetMask>
36792              <fields>
36793                <field>
36794                  <name>TIMEOUT24</name>
36795                  <description>LTSSM U3 Timeout (default: 10 ms) for LFPS Handshake  [default:  table 7-12, p 7-36]
36796(0= Timer Disabled)</description>
36797                  <bitRange>[23:0]</bitRange>
36798                  <access>read-write</access>
36799                </field>
36800              </fields>
36801            </register>
36802            <register>
36803              <name>LNK_LTSSM_HOT_RESET_ACTIVE_TIMEOUT</name>
36804              <description>LTSSM Hot Reset Active Timeout</description>
36805              <addressOffset>0x120</addressOffset>
36806              <size>32</size>
36807              <access>read-write</access>
36808              <resetValue>0x16E360</resetValue>
36809              <resetMask>0xFFFFFF</resetMask>
36810              <fields>
36811                <field>
36812                  <name>TIMEOUT24</name>
36813                  <description>LTSSM Hot Reset Acitve Timeout (default: 12 ms)  [default:  table 7-12, p 7-36]
36814(0= Timer Disabled)</description>
36815                  <bitRange>[23:0]</bitRange>
36816                  <access>read-write</access>
36817                </field>
36818              </fields>
36819            </register>
36820            <register>
36821              <name>LNK_LTSSM_HOT_RESET_EXIT_TIMEOUT</name>
36822              <description>LTSSM Hot Reset Exit Timeout</description>
36823              <addressOffset>0x124</addressOffset>
36824              <size>32</size>
36825              <access>read-write</access>
36826              <resetValue>0x3D090</resetValue>
36827              <resetMask>0xFFFFFF</resetMask>
36828              <fields>
36829                <field>
36830                  <name>TIMEOUT24</name>
36831                  <description>LTSSM Hot Reset Exit Timeout (default: 2 ms)  [default:  table 7-12, p 7-36]
36832(0= Timer Disabled)</description>
36833                  <bitRange>[23:0]</bitRange>
36834                  <access>read-write</access>
36835                </field>
36836              </fields>
36837            </register>
36838            <register>
36839              <name>LNK_LTSSM_LOOPBACK_EXIT_TIMEOUT</name>
36840              <description>LTSSM Loopback Exit Timeout</description>
36841              <addressOffset>0x128</addressOffset>
36842              <size>32</size>
36843              <access>read-write</access>
36844              <resetValue>0x3D090</resetValue>
36845              <resetMask>0xFFFFFFFF</resetMask>
36846              <fields>
36847                <field>
36848                  <name>TIMEOUT</name>
36849                  <description>LTSSM Loopback Exit Timeout (default: 2 ms)  [default:  table 7-12, p 7-36]
36850(0= Timer Disabled)</description>
36851                  <bitRange>[31:0]</bitRange>
36852                  <access>read-write</access>
36853                </field>
36854              </fields>
36855            </register>
36856            <register>
36857              <name>LNK_LTSSM_RECOVERY_IDLE_TIMEOUT</name>
36858              <description>LTSSM Recovery Idle Timeout</description>
36859              <addressOffset>0x12C</addressOffset>
36860              <size>32</size>
36861              <access>read-write</access>
36862              <resetValue>0x3D090</resetValue>
36863              <resetMask>0xFFFFFF</resetMask>
36864              <fields>
36865                <field>
36866                  <name>TIMEOUT24</name>
36867                  <description>LTSSM Recovery Idle Timeout (default: 2 ms)  [default:  table 7-12, p 7-36]
36868(0= Timer Disabled)</description>
36869                  <bitRange>[23:0]</bitRange>
36870                  <access>read-write</access>
36871                </field>
36872              </fields>
36873            </register>
36874            <register>
36875              <name>LNK_LTSSM_RECOVERY_ACTIVE_TIMEOUT</name>
36876              <description>LTSSM Recovery Active Timeout</description>
36877              <addressOffset>0x130</addressOffset>
36878              <size>32</size>
36879              <access>read-write</access>
36880              <resetValue>0x16E360</resetValue>
36881              <resetMask>0xFFFFFF</resetMask>
36882              <fields>
36883                <field>
36884                  <name>TIMEOUT24</name>
36885                  <description>LTSSM Recovery Active Timeout (default: 12 ms)  [default:  table 7-12, p 7-36]
36886(0= Timer Disabled)</description>
36887                  <bitRange>[23:0]</bitRange>
36888                  <access>read-write</access>
36889                </field>
36890              </fields>
36891            </register>
36892            <register>
36893              <name>LNK_LTSSM_RECOVERY_CONFIG_TIMEOUT</name>
36894              <description>LTSSM Recovery.Configuration Timeout</description>
36895              <addressOffset>0x134</addressOffset>
36896              <size>32</size>
36897              <access>read-write</access>
36898              <resetValue>0xB71B0</resetValue>
36899              <resetMask>0xFFFFFF</resetMask>
36900              <fields>
36901                <field>
36902                  <name>TIMEOUT24</name>
36903                  <description>LTSSM Recovery Configuration Timeout (default: 6 ms)  [default:  table 7-12, p 7-36]
36904(0= Timer Disabled)</description>
36905                  <bitRange>[23:0]</bitRange>
36906                  <access>read-write</access>
36907                </field>
36908              </fields>
36909            </register>
36910            <register>
36911              <name>LNK_LTSSM_LDN_TIMEOUT</name>
36912              <description>LTSSM LDN Received Timeout</description>
36913              <addressOffset>0x138</addressOffset>
36914              <size>32</size>
36915              <access>read-write</access>
36916              <resetValue>0x1E848</resetValue>
36917              <resetMask>0xFFFFFF</resetMask>
36918              <fields>
36919                <field>
36920                  <name>TIMEOUT24</name>
36921                  <description>LTSSM LDN Received Timeout (default: 1 ms)
36922(0= Timer Disabled)</description>
36923                  <bitRange>[23:0]</bitRange>
36924                  <access>read-write</access>
36925                </field>
36926              </fields>
36927            </register>
36928            <register>
36929              <name>LNK_LTSSM_LDN_TIMER</name>
36930              <description>LTSSM LDN Received Timer</description>
36931              <addressOffset>0x13C</addressOffset>
36932              <size>32</size>
36933              <access>read-only</access>
36934              <resetValue>0x0</resetValue>
36935              <resetMask>0xFFFFFF</resetMask>
36936              <fields>
36937                <field>
36938                  <name>TIMER24</name>
36939                  <description>LTSSM Recovery Configuration Timeout (default: 6 ms)  [default:  table 7-12, p 7-36]
36940(0= Timer Disabled)</description>
36941                  <bitRange>[23:0]</bitRange>
36942                  <access>read-only</access>
36943                </field>
36944              </fields>
36945            </register>
36946            <register>
36947              <name>LNK_COMPLIANCE_PATTERN_0</name>
36948              <description>Compliance Pattern CP0</description>
36949              <addressOffset>0x140</addressOffset>
36950              <size>32</size>
36951              <access>read-write</access>
36952              <resetValue>0x600</resetValue>
36953              <resetMask>0x1FFF</resetMask>
36954              <fields>
36955                <field>
36956                  <name>CP</name>
36957                  <description>Compliance Pattern</description>
36958                  <bitRange>[7:0]</bitRange>
36959                  <access>read-write</access>
36960                </field>
36961                <field>
36962                  <name>K_D</name>
36963                  <description>Symbol Type - 0: Data (D), 1: Symbol (K)</description>
36964                  <bitRange>[8:8]</bitRange>
36965                  <access>read-write</access>
36966                </field>
36967                <field>
36968                  <name>SCRAMBLED</name>
36969                  <description>Scramble On/Off</description>
36970                  <bitRange>[9:9]</bitRange>
36971                  <access>read-write</access>
36972                </field>
36973                <field>
36974                  <name>DEEMPHASIS</name>
36975                  <description>De-emphasis On/Off</description>
36976                  <bitRange>[10:10]</bitRange>
36977                  <access>read-write</access>
36978                </field>
36979                <field>
36980                  <name>LFPS</name>
36981                  <description>LFPS On/Off</description>
36982                  <bitRange>[11:11]</bitRange>
36983                  <access>read-write</access>
36984                </field>
36985                <field>
36986                  <name>TXONESZEROS</name>
36987                  <description>Enable TXONESZEROS (PIPE PHY Transmit Signal)</description>
36988                  <bitRange>[12:12]</bitRange>
36989                  <access>read-write</access>
36990                </field>
36991              </fields>
36992            </register>
36993            <register>
36994              <name>LNK_COMPLIANCE_PATTERN_1</name>
36995              <description>Compliance Pattern CP1</description>
36996              <addressOffset>0x144</addressOffset>
36997              <size>32</size>
36998              <access>read-write</access>
36999              <resetValue>0x44A</resetValue>
37000              <resetMask>0x1FFF</resetMask>
37001              <fields>
37002                <field>
37003                  <name>CP</name>
37004                  <description>Compliance Pattern</description>
37005                  <bitRange>[7:0]</bitRange>
37006                  <access>read-write</access>
37007                </field>
37008                <field>
37009                  <name>K_D</name>
37010                  <description>Symbol Type - 0: Data (D), 1: Symbol (K)</description>
37011                  <bitRange>[8:8]</bitRange>
37012                  <access>read-write</access>
37013                </field>
37014                <field>
37015                  <name>SCRAMBLED</name>
37016                  <description>Scramble On/Off</description>
37017                  <bitRange>[9:9]</bitRange>
37018                  <access>read-write</access>
37019                </field>
37020                <field>
37021                  <name>DEEMPHASIS</name>
37022                  <description>De-emphasis On/Off</description>
37023                  <bitRange>[10:10]</bitRange>
37024                  <access>read-write</access>
37025                </field>
37026                <field>
37027                  <name>LFPS</name>
37028                  <description>LFPS On/Off</description>
37029                  <bitRange>[11:11]</bitRange>
37030                  <access>read-write</access>
37031                </field>
37032                <field>
37033                  <name>TXONESZEROS</name>
37034                  <description>Enable TXONESZEROS (PIPE PHY Transmit Signal)</description>
37035                  <bitRange>[12:12]</bitRange>
37036                  <access>read-write</access>
37037                </field>
37038              </fields>
37039            </register>
37040            <register>
37041              <name>LNK_COMPLIANCE_PATTERN_2</name>
37042              <description>Compliance Pattern CP2</description>
37043              <addressOffset>0x148</addressOffset>
37044              <size>32</size>
37045              <access>read-write</access>
37046              <resetValue>0x478</resetValue>
37047              <resetMask>0x1FFF</resetMask>
37048              <fields>
37049                <field>
37050                  <name>CP</name>
37051                  <description>Compliance Pattern</description>
37052                  <bitRange>[7:0]</bitRange>
37053                  <access>read-write</access>
37054                </field>
37055                <field>
37056                  <name>K_D</name>
37057                  <description>Symbol Type - 0: Data (D), 1: Symbol (K)</description>
37058                  <bitRange>[8:8]</bitRange>
37059                  <access>read-write</access>
37060                </field>
37061                <field>
37062                  <name>SCRAMBLED</name>
37063                  <description>Scramble On/Off</description>
37064                  <bitRange>[9:9]</bitRange>
37065                  <access>read-write</access>
37066                </field>
37067                <field>
37068                  <name>DEEMPHASIS</name>
37069                  <description>De-emphasis On/Off</description>
37070                  <bitRange>[10:10]</bitRange>
37071                  <access>read-write</access>
37072                </field>
37073                <field>
37074                  <name>LFPS</name>
37075                  <description>LFPS On/Off</description>
37076                  <bitRange>[11:11]</bitRange>
37077                  <access>read-write</access>
37078                </field>
37079                <field>
37080                  <name>TXONESZEROS</name>
37081                  <description>Enable TXONESZEROS (PIPE PHY Transmit Signal)</description>
37082                  <bitRange>[12:12]</bitRange>
37083                  <access>read-write</access>
37084                </field>
37085              </fields>
37086            </register>
37087            <register>
37088              <name>LNK_COMPLIANCE_PATTERN_3</name>
37089              <description>Compliance Pattern CP3</description>
37090              <addressOffset>0x14C</addressOffset>
37091              <size>32</size>
37092              <access>read-write</access>
37093              <resetValue>0x5BC</resetValue>
37094              <resetMask>0x1FFF</resetMask>
37095              <fields>
37096                <field>
37097                  <name>CP</name>
37098                  <description>Compliance Pattern</description>
37099                  <bitRange>[7:0]</bitRange>
37100                  <access>read-write</access>
37101                </field>
37102                <field>
37103                  <name>K_D</name>
37104                  <description>Symbol Type - 0: Data (D), 1: Symbol (K)</description>
37105                  <bitRange>[8:8]</bitRange>
37106                  <access>read-write</access>
37107                </field>
37108                <field>
37109                  <name>SCRAMBLED</name>
37110                  <description>Scramble On/Off</description>
37111                  <bitRange>[9:9]</bitRange>
37112                  <access>read-write</access>
37113                </field>
37114                <field>
37115                  <name>DEEMPHASIS</name>
37116                  <description>De-emphasis On/Off</description>
37117                  <bitRange>[10:10]</bitRange>
37118                  <access>read-write</access>
37119                </field>
37120                <field>
37121                  <name>LFPS</name>
37122                  <description>LFPS On/Off</description>
37123                  <bitRange>[11:11]</bitRange>
37124                  <access>read-write</access>
37125                </field>
37126                <field>
37127                  <name>TXONESZEROS</name>
37128                  <description>Enable TXONESZEROS (PIPE PHY Transmit Signal)</description>
37129                  <bitRange>[12:12]</bitRange>
37130                  <access>read-write</access>
37131                </field>
37132              </fields>
37133            </register>
37134            <register>
37135              <name>LNK_COMPLIANCE_PATTERN_4</name>
37136              <description>Compliance Pattern CP4</description>
37137              <addressOffset>0x150</addressOffset>
37138              <size>32</size>
37139              <access>read-write</access>
37140              <resetValue>0xC00</resetValue>
37141              <resetMask>0x1FFF</resetMask>
37142              <fields>
37143                <field>
37144                  <name>CP</name>
37145                  <description>Compliance Pattern</description>
37146                  <bitRange>[7:0]</bitRange>
37147                  <access>read-write</access>
37148                </field>
37149                <field>
37150                  <name>K_D</name>
37151                  <description>Symbol Type - 0: Data (D), 1: Symbol (K)</description>
37152                  <bitRange>[8:8]</bitRange>
37153                  <access>read-write</access>
37154                </field>
37155                <field>
37156                  <name>SCRAMBLED</name>
37157                  <description>Scramble On/Off</description>
37158                  <bitRange>[9:9]</bitRange>
37159                  <access>read-write</access>
37160                </field>
37161                <field>
37162                  <name>DEEMPHASIS</name>
37163                  <description>De-emphasis On/Off</description>
37164                  <bitRange>[10:10]</bitRange>
37165                  <access>read-write</access>
37166                </field>
37167                <field>
37168                  <name>LFPS</name>
37169                  <description>LFPS On/Off</description>
37170                  <bitRange>[11:11]</bitRange>
37171                  <access>read-write</access>
37172                </field>
37173                <field>
37174                  <name>TXONESZEROS</name>
37175                  <description>Enable TXONESZEROS (PIPE PHY Transmit Signal)</description>
37176                  <bitRange>[12:12]</bitRange>
37177                  <access>read-write</access>
37178                </field>
37179              </fields>
37180            </register>
37181            <register>
37182              <name>LNK_COMPLIANCE_PATTERN_5</name>
37183              <description>Compliance Pattern CP5</description>
37184              <addressOffset>0x154</addressOffset>
37185              <size>32</size>
37186              <access>read-write</access>
37187              <resetValue>0x5FC</resetValue>
37188              <resetMask>0x1FFF</resetMask>
37189              <fields>
37190                <field>
37191                  <name>CP</name>
37192                  <description>Compliance Pattern</description>
37193                  <bitRange>[7:0]</bitRange>
37194                  <access>read-write</access>
37195                </field>
37196                <field>
37197                  <name>K_D</name>
37198                  <description>Symbol Type - 0: Data (D), 1: Symbol (K)</description>
37199                  <bitRange>[8:8]</bitRange>
37200                  <access>read-write</access>
37201                </field>
37202                <field>
37203                  <name>SCRAMBLED</name>
37204                  <description>Scramble On/Off</description>
37205                  <bitRange>[9:9]</bitRange>
37206                  <access>read-write</access>
37207                </field>
37208                <field>
37209                  <name>DEEMPHASIS</name>
37210                  <description>De-emphasis On/Off</description>
37211                  <bitRange>[10:10]</bitRange>
37212                  <access>read-write</access>
37213                </field>
37214                <field>
37215                  <name>LFPS</name>
37216                  <description>LFPS On/Off</description>
37217                  <bitRange>[11:11]</bitRange>
37218                  <access>read-write</access>
37219                </field>
37220                <field>
37221                  <name>TXONESZEROS</name>
37222                  <description>Enable TXONESZEROS (PIPE PHY Transmit Signal)</description>
37223                  <bitRange>[12:12]</bitRange>
37224                  <access>read-write</access>
37225                </field>
37226              </fields>
37227            </register>
37228            <register>
37229              <name>LNK_COMPLIANCE_PATTERN_6</name>
37230              <description>Compliance Pattern CP6</description>
37231              <addressOffset>0x158</addressOffset>
37232              <size>32</size>
37233              <access>read-write</access>
37234              <resetValue>0x1FC</resetValue>
37235              <resetMask>0x1FFF</resetMask>
37236              <fields>
37237                <field>
37238                  <name>CP</name>
37239                  <description>Compliance Pattern</description>
37240                  <bitRange>[7:0]</bitRange>
37241                  <access>read-write</access>
37242                </field>
37243                <field>
37244                  <name>K_D</name>
37245                  <description>Symbol Type - 0: Data (D), 1: Symbol (K)</description>
37246                  <bitRange>[8:8]</bitRange>
37247                  <access>read-write</access>
37248                </field>
37249                <field>
37250                  <name>SCRAMBLED</name>
37251                  <description>Scramble On/Off</description>
37252                  <bitRange>[9:9]</bitRange>
37253                  <access>read-write</access>
37254                </field>
37255                <field>
37256                  <name>DEEMPHASIS</name>
37257                  <description>De-emphasis On/Off</description>
37258                  <bitRange>[10:10]</bitRange>
37259                  <access>read-write</access>
37260                </field>
37261                <field>
37262                  <name>LFPS</name>
37263                  <description>LFPS On/Off</description>
37264                  <bitRange>[11:11]</bitRange>
37265                  <access>read-write</access>
37266                </field>
37267                <field>
37268                  <name>TXONESZEROS</name>
37269                  <description>Enable TXONESZEROS (PIPE PHY Transmit Signal)</description>
37270                  <bitRange>[12:12]</bitRange>
37271                  <access>read-write</access>
37272                </field>
37273              </fields>
37274            </register>
37275            <register>
37276              <name>LNK_COMPLIANCE_PATTERN_7</name>
37277              <description>Compliance Pattern CP7</description>
37278              <addressOffset>0x15C</addressOffset>
37279              <size>32</size>
37280              <access>read-write</access>
37281              <resetValue>0x1400</resetValue>
37282              <resetMask>0x1FFF</resetMask>
37283              <fields>
37284                <field>
37285                  <name>CP</name>
37286                  <description>Compliance Pattern</description>
37287                  <bitRange>[7:0]</bitRange>
37288                  <access>read-write</access>
37289                </field>
37290                <field>
37291                  <name>K_D</name>
37292                  <description>Symbol Type - 0: Data (D), 1: Symbol (K)</description>
37293                  <bitRange>[8:8]</bitRange>
37294                  <access>read-write</access>
37295                </field>
37296                <field>
37297                  <name>SCRAMBLED</name>
37298                  <description>Scramble On/Off</description>
37299                  <bitRange>[9:9]</bitRange>
37300                  <access>read-write</access>
37301                </field>
37302                <field>
37303                  <name>DEEMPHASIS</name>
37304                  <description>De-emphasis On/Off</description>
37305                  <bitRange>[10:10]</bitRange>
37306                  <access>read-write</access>
37307                </field>
37308                <field>
37309                  <name>LFPS</name>
37310                  <description>LFPS On/Off</description>
37311                  <bitRange>[11:11]</bitRange>
37312                  <access>read-write</access>
37313                </field>
37314                <field>
37315                  <name>TXONESZEROS</name>
37316                  <description>Enable TXONESZEROS (PIPE PHY Transmit Signal)</description>
37317                  <bitRange>[12:12]</bitRange>
37318                  <access>read-write</access>
37319                </field>
37320              </fields>
37321            </register>
37322            <register>
37323              <name>LNK_COMPLIANCE_PATTERN_8</name>
37324              <description>Compliance Pattern CP8</description>
37325              <addressOffset>0x160</addressOffset>
37326              <size>32</size>
37327              <access>read-write</access>
37328              <resetValue>0x1000</resetValue>
37329              <resetMask>0x1FFF</resetMask>
37330              <fields>
37331                <field>
37332                  <name>CP</name>
37333                  <description>Compliance Pattern</description>
37334                  <bitRange>[7:0]</bitRange>
37335                  <access>read-write</access>
37336                </field>
37337                <field>
37338                  <name>K_D</name>
37339                  <description>Symbol Type - 0: Data (D), 1: Symbol (K)</description>
37340                  <bitRange>[8:8]</bitRange>
37341                  <access>read-write</access>
37342                </field>
37343                <field>
37344                  <name>SCRAMBLED</name>
37345                  <description>Scramble On/Off</description>
37346                  <bitRange>[9:9]</bitRange>
37347                  <access>read-write</access>
37348                </field>
37349                <field>
37350                  <name>DEEMPHASIS</name>
37351                  <description>De-emphasis On/Off</description>
37352                  <bitRange>[10:10]</bitRange>
37353                  <access>read-write</access>
37354                </field>
37355                <field>
37356                  <name>LFPS</name>
37357                  <description>LFPS On/Off</description>
37358                  <bitRange>[11:11]</bitRange>
37359                  <access>read-write</access>
37360                </field>
37361                <field>
37362                  <name>TXONESZEROS</name>
37363                  <description>Enable TXONESZEROS (PIPE PHY Transmit Signal)</description>
37364                  <bitRange>[12:12]</bitRange>
37365                  <access>read-write</access>
37366                </field>
37367              </fields>
37368            </register>
37369            <register>
37370              <name>LNK_DEBUG_BUFFER_CTRL</name>
37371              <description>Buffer direct access control</description>
37372              <addressOffset>0x164</addressOffset>
37373              <size>32</size>
37374              <access>read-write</access>
37375              <resetValue>0x0</resetValue>
37376              <resetMask>0x7</resetMask>
37377              <fields>
37378                <field>
37379                  <name>MEM_PTR</name>
37380                  <description>0: Retry buffer locations 0x00-0xFF
373811: Retry buffer locations 0x100-0x1FF
373822: Retry buffer locations 0x200-0x2FF
373833: Retry buffer locations 0x300-0x3FF
373844: Debug features 0x00-0xFF</description>
37385                  <bitRange>[2:0]</bitRange>
37386                  <access>read-write</access>
37387                </field>
37388              </fields>
37389            </register>
37390            <register>
37391              <name>LNK_DATARATE_CHG_OBSERVE</name>
37392              <description>Dtat Rate Observability</description>
37393              <addressOffset>0x168</addressOffset>
37394              <size>32</size>
37395              <access>read-write</access>
37396              <resetValue>0x0</resetValue>
37397              <resetMask>0x1F</resetMask>
37398              <fields>
37399                <field>
37400                  <name>DATA_RATE_CHG_DET</name>
37401                  <description>Data rate change event detected since last cleared by CPU:
374020: PHY initialized in Gen2 (10G)
374031: PHY initialized in Gen1 (5G )
374042: G2-&gt;G1 switch due Polling.LFPS -&gt;Polling.RxEq
374053: G2-&gt;G1 switch due to Polling.LFPSPlus -&gt;Polling.RxEq
374064: G2-&gt;G1 switch due to receiving 5G-PHY capabiltiy LBPMs from partner in Polling.PortMatch state
374075: G2-&gt;G1 switch due to Gen2-12ms timeout in Polling.Active
37408(Polling.Active -&gt;Polling.PortMatch -&gt;Polling.PortConfig -&gt;Polling.RxEq)
374096: G2-&gt;G1 switch due to Gen2-12ms timeout in Polling.Configuration
37410(Polling.Configuration -&gt;Polling.PortMatch -&gt;Polling.PortConfig -&gt;Polling.RxEq)
374117: G2-&gt;G1 switch due to Gen2-2ms timeout in Polling.Idle
37412(Polling.Idle -&gt;Polling.PortMatch -&gt;Polling.PortConfig -&gt;Polling.RxEq)
374138: G1G2 swithching in Compliance (CP pattern swithces to Gen2)
374149: G2G1 swithching in Compliance (CP pattern swithces to Gen1)
3741510: G1G2 swithching in Compliance  due to receiving warm reset when the Gen2 link is transmitting Gen1 patterns
3741611: G1G2 swithcing  Upon  RX_DETECT_ACTIVE -&gt; Polling States  ( e.g. Gen2 Link settled in 5G data rate and then moves to SS.Inactive. Upon warm reset, HW switches to G1G2  )</description>
37417                  <bitRange>[4:0]</bitRange>
37418                  <access>read-write</access>
37419                </field>
37420              </fields>
37421            </register>
37422            <register>
37423              <name>LNK_LFPS_TX_POLLING_BURST_GEN2</name>
37424              <description>LFPS Polling Transmit Gen2 Configuration</description>
37425              <addressOffset>0x16C</addressOffset>
37426              <size>32</size>
37427              <access>read-write</access>
37428              <resetValue>0x139</resetValue>
37429              <resetMask>0xFFFF</resetMask>
37430              <fields>
37431                <field>
37432                  <name>BURST16</name>
37433                  <description>Clock periods for LFPS Burst, when LFPS signalling is transmitted  (default:  ~1.0us)</description>
37434                  <bitRange>[15:0]</bitRange>
37435                  <access>read-write</access>
37436                </field>
37437              </fields>
37438            </register>
37439            <register>
37440              <name>LNK_LFPS_TX_POLLING_REPEAT_GEN2</name>
37441              <description>LFPS Polling Transmit Gen2 Configuration</description>
37442              <addressOffset>0x170</addressOffset>
37443              <size>32</size>
37444              <access>read-write</access>
37445              <resetValue>0xC35</resetValue>
37446              <resetMask>0xFFFF</resetMask>
37447              <fields>
37448                <field>
37449                  <name>REPEAT16</name>
37450                  <description>Clock periods for LFPS Repeat, the time between LFPS Bursts  (default:  10.0 us)</description>
37451                  <bitRange>[15:0]</bitRange>
37452                  <access>read-write</access>
37453                </field>
37454              </fields>
37455            </register>
37456            <register>
37457              <name>LNK_LFPS_TX_PING_BURST_GEN2</name>
37458              <description>LFPS Ping Transmit Gen2 Configuration</description>
37459              <addressOffset>0x174</addressOffset>
37460              <size>32</size>
37461              <access>read-write</access>
37462              <resetValue>0x20</resetValue>
37463              <resetMask>0xFFFF</resetMask>
37464              <fields>
37465                <field>
37466                  <name>BURST16</name>
37467                  <description>Clock periods for Ping.LFPS Burst signalling transmission  (default:  ~100 ns)
37468SSP: range of (40ns, 160ns)</description>
37469                  <bitRange>[15:0]</bitRange>
37470                  <access>read-write</access>
37471                </field>
37472              </fields>
37473            </register>
37474            <register>
37475              <name>LNK_LFPS_TX_PING_REPEAT_GEN2</name>
37476              <description>LFPS Ping Transmit Gen2 Configuration</description>
37477              <addressOffset>0x178</addressOffset>
37478              <size>32</size>
37479              <access>read-write</access>
37480              <resetValue>0x3B9ACA0</resetValue>
37481              <resetMask>0xFFFFFFFF</resetMask>
37482              <fields>
37483                <field>
37484                  <name>REPEAT32</name>
37485                  <description>Clock periods for LFPS Repeat (default: 200 ms)</description>
37486                  <bitRange>[31:0]</bitRange>
37487                  <access>read-write</access>
37488                </field>
37489              </fields>
37490            </register>
37491            <register>
37492              <name>LNK_LFPS_TX_U1_EXIT_GEN2</name>
37493              <description>LFPS U1_EXIT Transmit Gen2 Configuration</description>
37494              <addressOffset>0x17C</addressOffset>
37495              <size>32</size>
37496              <access>read-write</access>
37497              <resetValue>0x11B</resetValue>
37498              <resetMask>0xFFFF</resetMask>
37499              <fields>
37500                <field>
37501                  <name>BURST16</name>
37502                  <description>Number of clock periods for LFPS Burst transmission  (default:  905.6 ns)
37503It is in the range of (900ns,2ms).</description>
37504                  <bitRange>[15:0]</bitRange>
37505                  <access>read-write</access>
37506                </field>
37507              </fields>
37508            </register>
37509            <register>
37510              <name>LNK_LFPS_TX_U2_EXIT_GEN2</name>
37511              <description>LFPS U2_EXIT Transmit Gen2 Configuration</description>
37512              <addressOffset>0x180</addressOffset>
37513              <size>32</size>
37514              <access>read-write</access>
37515              <resetValue>0x61A8</resetValue>
37516              <resetMask>0xFFFFFF</resetMask>
37517              <fields>
37518                <field>
37519                  <name>BURST24</name>
37520                  <description>Minimum number of clock periods for LFPS Burst transmission  (default:  80 us)</description>
37521                  <bitRange>[23:0]</bitRange>
37522                  <access>read-write</access>
37523                </field>
37524              </fields>
37525            </register>
37526            <register>
37527              <name>LNK_LFPS_TX_U3_EXIT_GEN2</name>
37528              <description>LFPS U3 Exit Transmit Gen2 Configuration</description>
37529              <addressOffset>0x184</addressOffset>
37530              <size>32</size>
37531              <access>read-write</access>
37532              <resetValue>0x3D090</resetValue>
37533              <resetMask>0xFFFFFF</resetMask>
37534              <fields>
37535                <field>
37536                  <name>BURST24</name>
37537                  <description>Minimum number of clock periods for LFPS Burst transmission (default: 80 us)</description>
37538                  <bitRange>[23:0]</bitRange>
37539                  <access>read-write</access>
37540                </field>
37541              </fields>
37542            </register>
37543            <register>
37544              <name>LNK_LFPS_RX_POLLING_BURST_GEN2</name>
37545              <description>LFPS Polling Detect Gen2 Configuration</description>
37546              <addressOffset>0x188</addressOffset>
37547              <size>32</size>
37548              <access>read-write</access>
37549              <resetValue>0x1B500BC</resetValue>
37550              <resetMask>0xFFFFFFFF</resetMask>
37551              <fields>
37552                <field>
37553                  <name>BURST_MIN</name>
37554                  <description>Minimum number of clock periods for detection of Polling.LFPS Burst  (default:  ~0.6 us)</description>
37555                  <bitRange>[15:0]</bitRange>
37556                  <access>read-write</access>
37557                </field>
37558                <field>
37559                  <name>BURST_MAX</name>
37560                  <description>Maximum number of clock periods for detection of Polling.LFPS Burst  (default:  ~1.4 us)</description>
37561                  <bitRange>[31:16]</bitRange>
37562                  <access>read-write</access>
37563                </field>
37564              </fields>
37565            </register>
37566            <register>
37567              <name>LNK_LFPS_RX_POLLING_REPEAT_GEN2</name>
37568              <description>LFPS Polling Detect Gen2 Configuration</description>
37569              <addressOffset>0x18C</addressOffset>
37570              <size>32</size>
37571              <access>read-write</access>
37572              <resetValue>0x11170753</resetValue>
37573              <resetMask>0xFFFFFFFF</resetMask>
37574              <fields>
37575                <field>
37576                  <name>REPEAT_MIN</name>
37577                  <description>Minimum number of clock periods of idle (non-LFPS) time between LFPS Bursts for detection of Polling.LFPS signalling  (default:  6 us)</description>
37578                  <bitRange>[15:0]</bitRange>
37579                  <access>read-write</access>
37580                </field>
37581                <field>
37582                  <name>REPEAT_MAX</name>
37583                  <description>Maximum number of clock periods of idle (non-LFPS) time between LFPS Bursts for detection of Polling.LFPS signalling  (default:  14 us)</description>
37584                  <bitRange>[31:16]</bitRange>
37585                  <access>read-write</access>
37586                </field>
37587              </fields>
37588            </register>
37589            <register>
37590              <name>LNK_LFPS_RX_PING_GEN2</name>
37591              <description>LFPS Ping Detect Gen2 Configuration</description>
37592              <addressOffset>0x190</addressOffset>
37593              <size>32</size>
37594              <access>read-write</access>
37595              <resetValue>0x32000D</resetValue>
37596              <resetMask>0xFFFFFFFF</resetMask>
37597              <fields>
37598                <field>
37599                  <name>BURST_MIN</name>
37600                  <description>Minimum number of clock periods for detection of Ping.LFPS Burst  (default: ~40 ns)</description>
37601                  <bitRange>[15:0]</bitRange>
37602                  <access>read-write</access>
37603                </field>
37604                <field>
37605                  <name>BURST_MAX</name>
37606                  <description>Maximum number of clock periods for detection of Ping.LFPS Burst  (default:  160 ns)</description>
37607                  <bitRange>[31:16]</bitRange>
37608                  <access>read-write</access>
37609                </field>
37610              </fields>
37611            </register>
37612            <register>
37613              <name>LNK_LFPS_RX_RESET_GEN2</name>
37614              <description>LFPS Reset Detect Gen2 Configuration</description>
37615              <addressOffset>0x194</addressOffset>
37616              <size>32</size>
37617              <access>read-write</access>
37618              <resetValue>0x3E800</resetValue>
37619              <resetMask>0xFFFFFF</resetMask>
37620              <fields>
37621                <field>
37622                  <name>BURST24</name>
37623                  <description>Minimum number of clock periods for detection
37624(default: 80 ms)</description>
37625                  <bitRange>[23:0]</bitRange>
37626                  <access>read-write</access>
37627                </field>
37628              </fields>
37629            </register>
37630            <register>
37631              <name>LNK_LFPS_RX_U1_EXIT_GEN2</name>
37632              <description>LFPS U1 Exit Detect Gen2 Configuration</description>
37633              <addressOffset>0x198</addressOffset>
37634              <size>32</size>
37635              <access>read-write</access>
37636              <resetValue>0x5E</resetValue>
37637              <resetMask>0xFFFF</resetMask>
37638              <fields>
37639                <field>
37640                  <name>BURST16</name>
37641                  <description>Minimum number of clock periods for U1 Exit Burst detection
37642A port is still required to detect U1 LFPS exit signal at a minimum of 300ns. The extra 300ns is provided as the guard band for successful U1 LFPS exit handshake.
37643(default: 300 ns)</description>
37644                  <bitRange>[15:0]</bitRange>
37645                  <access>read-write</access>
37646                </field>
37647              </fields>
37648            </register>
37649            <register>
37650              <name>LNK_LFPS_RX_U2_EXIT_GEN2</name>
37651              <description>LFPS U2 Exit Detect Gen2 Configuration</description>
37652              <addressOffset>0x19C</addressOffset>
37653              <size>32</size>
37654              <access>read-write</access>
37655              <resetValue>0x61A8</resetValue>
37656              <resetMask>0xFFFFFF</resetMask>
37657              <fields>
37658                <field>
37659                  <name>BURST24</name>
37660                  <description>Minimum number of clock periods for U2 Exit Burst detection  (default:  80 us)</description>
37661                  <bitRange>[23:0]</bitRange>
37662                  <access>read-write</access>
37663                </field>
37664              </fields>
37665            </register>
37666            <register>
37667              <name>LNK_LFPS_RX_U1_HANDSHAKE_GEN2</name>
37668              <description>LFPS U1 Exit Handshake Gen2 Configuration</description>
37669              <addressOffset>0x1A0</addressOffset>
37670              <size>32</size>
37671              <access>read-write</access>
37672              <resetValue>0x5E</resetValue>
37673              <resetMask>0xFFFF</resetMask>
37674              <fields>
37675                <field>
37676                  <name>BURST16</name>
37677                  <description>Minimum number of clock periods for LFPS handshake detection (default: 301 ns)</description>
37678                  <bitRange>[15:0]</bitRange>
37679                  <access>read-write</access>
37680                </field>
37681              </fields>
37682            </register>
37683            <register>
37684              <name>LNK_LFPS_RX_U2_HANDSHAKE_GEN2</name>
37685              <description>LFPS U2 Exit Handshake Gen 2 Configuration</description>
37686              <addressOffset>0x1A4</addressOffset>
37687              <size>32</size>
37688              <access>read-write</access>
37689              <resetValue>0x61A8</resetValue>
37690              <resetMask>0xFFFFFF</resetMask>
37691              <fields>
37692                <field>
37693                  <name>BURST24</name>
37694                  <description>Minimum number of clock periods for LFPS handshake detection (default: 80 us)</description>
37695                  <bitRange>[23:0]</bitRange>
37696                  <access>read-write</access>
37697                </field>
37698              </fields>
37699            </register>
37700            <register>
37701              <name>LNK_LFPS_RX_U3_HANDSHAKE_GEN2</name>
37702              <description>LFPS U3 Exit Handshake Gen 2 Configuration</description>
37703              <addressOffset>0x1A8</addressOffset>
37704              <size>32</size>
37705              <access>read-write</access>
37706              <resetValue>0x61A8</resetValue>
37707              <resetMask>0xFFFFFF</resetMask>
37708              <fields>
37709                <field>
37710                  <name>BURST24</name>
37711                  <description>Minimum number of clock periods for LFPS handshake detection (default: 80 us)</description>
37712                  <bitRange>[23:0]</bitRange>
37713                  <access>read-write</access>
37714                </field>
37715              </fields>
37716            </register>
37717            <register>
37718              <name>LNK_LFPS_RX_LOOPBACK_EXIT_GEN2</name>
37719              <description>LFPS Loopback Exit Detect Gen2 Configuration</description>
37720              <addressOffset>0x1AC</addressOffset>
37721              <size>32</size>
37722              <access>read-write</access>
37723              <resetValue>0x61A8</resetValue>
37724              <resetMask>0xFFFFFF</resetMask>
37725              <fields>
37726                <field>
37727                  <name>BURST24</name>
37728                  <description>Minimum number of clock periods for detection
37729(default: 80us)</description>
37730                  <bitRange>[23:0]</bitRange>
37731                  <access>read-write</access>
37732                </field>
37733              </fields>
37734            </register>
37735            <register>
37736              <name>LNK_LFPS_RX_LOOPBACK_HANDSHAKE_GEN2</name>
37737              <description>LFPS Loopback Exit Handshake Gen2 Configuration</description>
37738              <addressOffset>0x1B0</addressOffset>
37739              <size>32</size>
37740              <access>read-write</access>
37741              <resetValue>0x61A8</resetValue>
37742              <resetMask>0xFFFFFF</resetMask>
37743              <fields>
37744                <field>
37745                  <name>BURST24</name>
37746                  <description>Minimum number of clock periods for LFPS handshake detection (default: 80 us)</description>
37747                  <bitRange>[23:0]</bitRange>
37748                  <access>read-write</access>
37749                </field>
37750              </fields>
37751            </register>
37752            <register>
37753              <name>LNK_PENDING_HP_TIMEOUT_GEN2</name>
37754              <description>Header Packet LGOOD/LBAD Gen2 Timeout</description>
37755              <addressOffset>0x1B4</addressOffset>
37756              <size>32</size>
37757              <access>read-write</access>
37758              <resetValue>0xC35</resetValue>
37759              <resetMask>0xFFFF</resetMask>
37760              <fields>
37761                <field>
37762                  <name>TIMEOUT16</name>
37763                  <description>PENDING_HP_TIMER Timeout (default: 10 us)
37764(0= Timer Disabled)</description>
37765                  <bitRange>[15:0]</bitRange>
37766                  <access>read-write</access>
37767                </field>
37768              </fields>
37769            </register>
37770            <register>
37771              <name>LNK_CREDIT_HP_TIMEOUT_GEN2</name>
37772              <description>Header Packet LCRD_x Gen2 Timeout</description>
37773              <addressOffset>0x1C4</addressOffset>
37774              <size>32</size>
37775              <access>read-write</access>
37776              <resetValue>0xEE6B28</resetValue>
37777              <resetMask>0xFFFFFFFF</resetMask>
37778              <fields>
37779                <field>
37780                  <name>TIMEOUT</name>
37781                  <description>CREDIT_HP_TIMER Timeout (default: 5 ms)
37782(0= Timer Disabled)</description>
37783                  <bitRange>[31:0]</bitRange>
37784                  <access>read-write</access>
37785                </field>
37786              </fields>
37787            </register>
37788            <register>
37789              <name>LNK_PM_LC_X2_TIMEOUT_GEN1</name>
37790              <description>Power Mode PM_LC_X2_TIMER Gen1 Timeout</description>
37791              <addressOffset>0x1C8</addressOffset>
37792              <size>32</size>
37793              <access>read-write</access>
37794              <resetValue>0x3E8</resetValue>
37795              <resetMask>0xFFFF</resetMask>
37796              <fields>
37797                <field>
37798                  <name>TIMEOUT16</name>
37799                  <description>PM_LC_TIMER Timeout (default: 8 us)
37800(0= Timer Disabled)
37801It is used by initiating port.</description>
37802                  <bitRange>[15:0]</bitRange>
37803                  <access>read-write</access>
37804                </field>
37805              </fields>
37806            </register>
37807            <register>
37808              <name>LNK_PM_LC_X1_TIMEOUT_GEN2</name>
37809              <description>Power Mode PM_LC_X1_TIMER Gen2 Timeout</description>
37810              <addressOffset>0x1CC</addressOffset>
37811              <size>32</size>
37812              <access>read-write</access>
37813              <resetValue>0x4E2</resetValue>
37814              <resetMask>0xFFFF</resetMask>
37815              <fields>
37816                <field>
37817                  <name>TIMEOUT16</name>
37818                  <description>PM_LC_TIMER Timeout (default: 4 us)
37819(0= Timer Disabled)
37820It is used by initiating port.</description>
37821                  <bitRange>[15:0]</bitRange>
37822                  <access>read-write</access>
37823                </field>
37824              </fields>
37825            </register>
37826            <register>
37827              <name>LNK_PM_LC_X2_TIMEOUT_GEN2</name>
37828              <description>Power Mode PM_LC_X2_TIMER Gen2 Timeout</description>
37829              <addressOffset>0x1D0</addressOffset>
37830              <size>32</size>
37831              <access>read-write</access>
37832              <resetValue>0x9C4</resetValue>
37833              <resetMask>0xFFFF</resetMask>
37834              <fields>
37835                <field>
37836                  <name>TIMEOUT16</name>
37837                  <description>PM_LC_TIMER Timeout (default: 8 us)
37838(0= Timer Disabled)
37839It is used by initiating port.</description>
37840                  <bitRange>[15:0]</bitRange>
37841                  <access>read-write</access>
37842                </field>
37843              </fields>
37844            </register>
37845            <register>
37846              <name>LNK_PM_ENTRY_X2_TIMEOUT_GEN1</name>
37847              <description>Power Mode PM_ENTRY_X2_TIMER Gen1 Timeout</description>
37848              <addressOffset>0x1D4</addressOffset>
37849              <size>32</size>
37850              <access>read-write</access>
37851              <resetValue>0x7D0</resetValue>
37852              <resetMask>0xFFFF</resetMask>
37853              <fields>
37854                <field>
37855                  <name>TIMEOUT16</name>
37856                  <description>PM_ENTRY_TIMER Timeout (default: 16 us)
37857(0= Timer Disabled)
37858It is used by the port receiving the request to enter the low power state.</description>
37859                  <bitRange>[15:0]</bitRange>
37860                  <access>read-write</access>
37861                </field>
37862              </fields>
37863            </register>
37864            <register>
37865              <name>LNK_PM_ENTRY_X1_TIMEOUT_GEN2</name>
37866              <description>Power Mode PM_ENTRY_X1_TIMER Gen2 Timeout</description>
37867              <addressOffset>0x1D8</addressOffset>
37868              <size>32</size>
37869              <access>read-write</access>
37870              <resetValue>0x9C4</resetValue>
37871              <resetMask>0xFFFF</resetMask>
37872              <fields>
37873                <field>
37874                  <name>TIMEOUT16</name>
37875                  <description>PM_ENTRY_TIMER Timeout (default: 8 us)
37876(0= Timer Disabled)
37877It is used by the port receiving the request to enter the low power state.</description>
37878                  <bitRange>[15:0]</bitRange>
37879                  <access>read-write</access>
37880                </field>
37881              </fields>
37882            </register>
37883            <register>
37884              <name>LNK_PM_ENTRY_X2_TIMEOUT_GEN2</name>
37885              <description>Power Mode PM_ENTRY_X2_TIMER Gen2 Timeout</description>
37886              <addressOffset>0x1DC</addressOffset>
37887              <size>32</size>
37888              <access>read-write</access>
37889              <resetValue>0x1388</resetValue>
37890              <resetMask>0xFFFF</resetMask>
37891              <fields>
37892                <field>
37893                  <name>TIMEOUT16</name>
37894                  <description>PM_ENTRY_TIMER Timeout (default: 16 us)
37895(0= Timer Disabled)
37896It is used by the port receiving the request to enter the low power state.</description>
37897                  <bitRange>[15:0]</bitRange>
37898                  <access>read-write</access>
37899                </field>
37900              </fields>
37901            </register>
37902            <register>
37903              <name>LNK_PM_UX_EXIT_TIMEOUT_GEN2</name>
37904              <description>Power Mode Ux_EXIT_TIMER Gen2 Timeout</description>
37905              <addressOffset>0x1E0</addressOffset>
37906              <size>32</size>
37907              <access>read-write</access>
37908              <resetValue>0x1C9C38</resetValue>
37909              <resetMask>0xFFFFFFFF</resetMask>
37910              <fields>
37911                <field>
37912                  <name>TIMEOUT</name>
37913                  <description>Ux_EXIT_TIMER Timeout (default: 6 ms)
37914(0= Timer Disabled)
37915It is used by the resume initiator.</description>
37916                  <bitRange>[31:0]</bitRange>
37917                  <access>read-write</access>
37918                </field>
37919              </fields>
37920            </register>
37921            <register>
37922              <name>LNK_U1_MIN_RESIDENCY_TIMEOUT_GEN1</name>
37923              <description>Power Mode U1_MIN_RESIDENCY_TIMER Gen1 Timeout</description>
37924              <addressOffset>0x1E4</addressOffset>
37925              <size>32</size>
37926              <access>read-write</access>
37927              <resetValue>0x177</resetValue>
37928              <resetMask>0xFFFF</resetMask>
37929              <fields>
37930                <field>
37931                  <name>TIMEOUT16</name>
37932                  <description>U1_MIN_RESIDENCY_TIMER Timeout (default: 3 us)
37933(0= Timer Disabled)</description>
37934                  <bitRange>[15:0]</bitRange>
37935                  <access>read-write</access>
37936                </field>
37937              </fields>
37938            </register>
37939            <register>
37940              <name>LNK_U1_MIN_RESIDENCY_TIMEOUT_GEN2</name>
37941              <description>Power Mode U1_MIN_RESIDENCY_TIMER Gen2 Timeout</description>
37942              <addressOffset>0x1E8</addressOffset>
37943              <size>32</size>
37944              <access>read-write</access>
37945              <resetValue>0x3AA</resetValue>
37946              <resetMask>0xFFFF</resetMask>
37947              <fields>
37948                <field>
37949                  <name>TIMEOUT16</name>
37950                  <description>U1_MIN_RESIDENCY_TIMER Timeout (default: 3 us)
37951(0= Timer Disabled)</description>
37952                  <bitRange>[15:0]</bitRange>
37953                  <access>read-write</access>
37954                </field>
37955              </fields>
37956            </register>
37957            <register>
37958              <name>LNK_LFPS_TX_SCD_LOGIC0_REPEAT_GEN1</name>
37959              <description>LFPS SCD Transmit Logic 0 Gen1 Configuration</description>
37960              <addressOffset>0x1EC</addressOffset>
37961              <size>32</size>
37962              <access>read-write</access>
37963              <resetValue>0x3AA</resetValue>
37964              <resetMask>0xFFFF</resetMask>
37965              <fields>
37966                <field>
37967                  <name>REPEAT16</name>
37968                  <description>tRepeat duration of SCD Logic-0 LFPS transmission in 8 ns
37969(default 7.5 us)  tBURST+ElecIdle = 6 us - 9 us</description>
37970                  <bitRange>[15:0]</bitRange>
37971                  <access>read-write</access>
37972                </field>
37973              </fields>
37974            </register>
37975            <register>
37976              <name>LNK_LFPS_TX_SCD_LOGIC1_REPEAT_GEN1</name>
37977              <description>LFPS SCD Transmit Logic 1 Gen1 Configuration</description>
37978              <addressOffset>0x1F0</addressOffset>
37979              <size>32</size>
37980              <access>read-write</access>
37981              <resetValue>0x61B</resetValue>
37982              <resetMask>0xFFFF</resetMask>
37983              <fields>
37984                <field>
37985                  <name>REPEAT16</name>
37986                  <description>tRepeat duration of SCD Logic-0 LFPS transmission in 8 ns
37987(default 12.5 us)  tBURST+ElecIdle = 11 us - 14 us</description>
37988                  <bitRange>[15:0]</bitRange>
37989                  <access>read-write</access>
37990                </field>
37991              </fields>
37992            </register>
37993            <register>
37994              <name>LNK_LFPS_TX_SCD_END_REPEAT_GEN1</name>
37995              <description>LFPS SCD Transmit End Gen1 Configuration</description>
37996              <addressOffset>0x1F4</addressOffset>
37997              <size>32</size>
37998              <access>read-write</access>
37999              <resetValue>0xEA6</resetValue>
38000              <resetMask>0xFFFF</resetMask>
38001              <fields>
38002                <field>
38003                  <name>REPEAT16</name>
38004                  <description>tRepeat duration of SCD Logic-0 LFPS transmission in 8 ns
38005(default 30 us)  tBURST (0.6us ~1.4us) + ElecIdle (&gt;28 us)</description>
38006                  <bitRange>[15:0]</bitRange>
38007                  <access>read-write</access>
38008                </field>
38009              </fields>
38010            </register>
38011            <register>
38012              <name>LNK_LFPS_RX_SCD_LOGIC0_REPEAT_GEN1</name>
38013              <description>LFPS SCD Receive Logic 0 Gen1 Gen1 Configuration</description>
38014              <addressOffset>0x1F8</addressOffset>
38015              <size>32</size>
38016              <access>read-write</access>
38017              <resetValue>0x46502EE</resetValue>
38018              <resetMask>0xFFFFFFFF</resetMask>
38019              <fields>
38020                <field>
38021                  <name>REPEAT_MIN</name>
38022                  <description>Minimum number of clock periods for detection of Polling.LFPS based SCD Logic 0  (default:  6 us)</description>
38023                  <bitRange>[15:0]</bitRange>
38024                  <access>read-write</access>
38025                </field>
38026                <field>
38027                  <name>REPEAT_MAX</name>
38028                  <description>Maximum number of clock periods for detection of Polling.LFPS based SCD Logic 0 (default:  9 us)</description>
38029                  <bitRange>[31:16]</bitRange>
38030                  <access>read-write</access>
38031                </field>
38032              </fields>
38033            </register>
38034            <register>
38035              <name>LNK_LFPS_RX_SCD_LOGIC1_REPEAT_GEN1</name>
38036              <description>LFPS SCD Receive Logic 1 Gen1 Configuration</description>
38037              <addressOffset>0x1FC</addressOffset>
38038              <size>32</size>
38039              <access>read-write</access>
38040              <resetValue>0x6D6055F</resetValue>
38041              <resetMask>0xFFFFFFFF</resetMask>
38042              <fields>
38043                <field>
38044                  <name>REPEAT_MIN</name>
38045                  <description>Minimum number of clock periods for detection of Polling.LFPS based SCD Logic 1  (default:  11 us)</description>
38046                  <bitRange>[15:0]</bitRange>
38047                  <access>read-write</access>
38048                </field>
38049                <field>
38050                  <name>REPEAT_MAX</name>
38051                  <description>Maximum number of clock periods for detection of Polling.LFPS based SCD Logic 1 (default:  14 us)</description>
38052                  <bitRange>[31:16]</bitRange>
38053                  <access>read-write</access>
38054                </field>
38055              </fields>
38056            </register>
38057            <register>
38058              <name>LNK_LFPS_RX_SCD_END_REPEAT_GEN1</name>
38059              <description>LFPS SCD Receive End Gen1 Configuration</description>
38060              <addressOffset>0x200</addressOffset>
38061              <size>32</size>
38062              <access>read-write</access>
38063              <resetValue>0x22EA</resetValue>
38064              <resetMask>0xFFFF</resetMask>
38065              <fields>
38066                <field>
38067                  <name>REPEAT_MIN</name>
38068                  <description>Minimum number of clock periods for detection of Polling.LFPS based SCD End  (default:  28.6 us)</description>
38069                  <bitRange>[15:0]</bitRange>
38070                  <access>read-write</access>
38071                </field>
38072              </fields>
38073            </register>
38074            <register>
38075              <name>LNK_LFPS_TX_SCD_LOGIC0_REPEAT_GEN2</name>
38076              <description>LFPS SCD Transmit Logic 0 Gen2 Configuration</description>
38077              <addressOffset>0x204</addressOffset>
38078              <size>32</size>
38079              <access>read-write</access>
38080              <resetValue>0x930</resetValue>
38081              <resetMask>0xFFFF</resetMask>
38082              <fields>
38083                <field>
38084                  <name>REPEAT16</name>
38085                  <description>tRepeat duration of SCD Logic-0 LFPS transmission in 3.2 ns
38086(default 7.5 us)  tBURST+ElecIdle = 6 us - 9 us</description>
38087                  <bitRange>[15:0]</bitRange>
38088                  <access>read-write</access>
38089                </field>
38090              </fields>
38091            </register>
38092            <register>
38093              <name>LNK_LFPS_TX_SCD_LOGIC1_REPEAT_GEN2</name>
38094              <description>LFPS SCD Transmit Logic 1 Gen2 Configuration</description>
38095              <addressOffset>0x208</addressOffset>
38096              <size>32</size>
38097              <access>read-write</access>
38098              <resetValue>0xF42</resetValue>
38099              <resetMask>0xFFFF</resetMask>
38100              <fields>
38101                <field>
38102                  <name>REPEAT16</name>
38103                  <description>tRepeat duration of SCD Logic-0 LFPS transmission in 3.2 ns
38104(default 12.5 us)  tBURST+ElecIdle = 11 us - 14 us</description>
38105                  <bitRange>[15:0]</bitRange>
38106                  <access>read-write</access>
38107                </field>
38108              </fields>
38109            </register>
38110            <register>
38111              <name>LNK_LFPS_TX_SCD_END_REPEAT_GEN2</name>
38112              <description>LFPS SCD Transmit End Gen2 Configuration</description>
38113              <addressOffset>0x20C</addressOffset>
38114              <size>32</size>
38115              <access>read-write</access>
38116              <resetValue>0x249F</resetValue>
38117              <resetMask>0xFFFF</resetMask>
38118              <fields>
38119                <field>
38120                  <name>REPEAT16</name>
38121                  <description>tRepeat duration of SCD Logic-0 LFPS transmission in 3.2ns
38122(default 30 us)  tBURST (0.6us ~1.4us) + ElecIdle (&gt;28 us)</description>
38123                  <bitRange>[15:0]</bitRange>
38124                  <access>read-write</access>
38125                </field>
38126              </fields>
38127            </register>
38128            <register>
38129              <name>LNK_LFPS_RX_SCD_LOGIC0_REPEAT_GEN2</name>
38130              <description>LFPS SCD Receive Logic 0 Gen2 Configuration</description>
38131              <addressOffset>0x210</addressOffset>
38132              <size>32</size>
38133              <access>read-write</access>
38134              <resetValue>0xAFC0753</resetValue>
38135              <resetMask>0xFFFFFFFF</resetMask>
38136              <fields>
38137                <field>
38138                  <name>REPEAT_MIN</name>
38139                  <description>Minimum number of clock periods for detection of Polling.LFPS based SCD Logic 0  (default:  6 us)</description>
38140                  <bitRange>[15:0]</bitRange>
38141                  <access>read-write</access>
38142                </field>
38143                <field>
38144                  <name>REPEAT_MAX</name>
38145                  <description>Maximum number of clock periods for detection of Polling.LFPS based SCD Logic 0 (default:  9 us)</description>
38146                  <bitRange>[31:16]</bitRange>
38147                  <access>read-write</access>
38148                </field>
38149              </fields>
38150            </register>
38151            <register>
38152              <name>LNK_LFPS_RX_SCD_LOGIC1_REPEAT_GEN2</name>
38153              <description>LFPS SCD Receive Logic 1 Gen2 Configuration</description>
38154              <addressOffset>0x220</addressOffset>
38155              <size>32</size>
38156              <access>read-write</access>
38157              <resetValue>0x11170D6E</resetValue>
38158              <resetMask>0xFFFFFFFF</resetMask>
38159              <fields>
38160                <field>
38161                  <name>REPEAT_MIN</name>
38162                  <description>Minimum number of clock periods for detection of Polling.LFPS based SCD Logic 1  (default:  11 us)</description>
38163                  <bitRange>[15:0]</bitRange>
38164                  <access>read-write</access>
38165                </field>
38166                <field>
38167                  <name>REPEAT_MAX</name>
38168                  <description>Maximum number of clock periods for detection of Polling.LFPS based SCD Logic 1 (default:  14 us)</description>
38169                  <bitRange>[31:16]</bitRange>
38170                  <access>read-write</access>
38171                </field>
38172              </fields>
38173            </register>
38174            <register>
38175              <name>LNK_LFPS_RX_SCD_END_REPEAT_GEN2</name>
38176              <description>LFPS SCD Receive End Gen2 Configuration</description>
38177              <addressOffset>0x224</addressOffset>
38178              <size>32</size>
38179              <access>read-write</access>
38180              <resetValue>0x22EA</resetValue>
38181              <resetMask>0xFFFF</resetMask>
38182              <fields>
38183                <field>
38184                  <name>REPEAT_MIN</name>
38185                  <description>Minimum number of clock periods for detection of Polling.LFPS based SCD End  (default:  28.6 us)</description>
38186                  <bitRange>[15:0]</bitRange>
38187                  <access>read-write</access>
38188                </field>
38189              </fields>
38190            </register>
38191            <register>
38192              <name>LNK_LFPS_TX_LBPS_TPWM_GEN1</name>
38193              <description>LFPS LBPS Transmit tPWM Gen1 Configuration</description>
38194              <addressOffset>0x228</addressOffset>
38195              <size>32</size>
38196              <access>read-write</access>
38197              <resetValue>0x113</resetValue>
38198              <resetMask>0xFFFF</resetMask>
38199              <fields>
38200                <field>
38201                  <name>REPEAT16</name>
38202                  <description>tPWM duration of LFPS transmission in 8 ns
38203(default 2.2 us)</description>
38204                  <bitRange>[15:0]</bitRange>
38205                  <access>read-write</access>
38206                </field>
38207              </fields>
38208            </register>
38209            <register>
38210              <name>LNK_LFPS_TX_LBPS_TLFPS0_GEN1</name>
38211              <description>LFPS LBPS Transmit tLFPS-0 Gen1 Configuration</description>
38212              <addressOffset>0x238</addressOffset>
38213              <size>32</size>
38214              <access>read-write</access>
38215              <resetValue>0x52</resetValue>
38216              <resetMask>0xFFFF</resetMask>
38217              <fields>
38218                <field>
38219                  <name>BURST16</name>
38220                  <description>tLFPS-0 duration of LFPS transmission in 8 ns
38221(default 0.65 us)</description>
38222                  <bitRange>[15:0]</bitRange>
38223                  <access>read-write</access>
38224                </field>
38225              </fields>
38226            </register>
38227            <register>
38228              <name>LNK_LFPS_TX_LBPS_TLFPS1_GEN1</name>
38229              <description>LFPS LBPS Transmit tLFPS-1 Gen1 Configuration</description>
38230              <addressOffset>0x23C</addressOffset>
38231              <size>32</size>
38232              <access>read-write</access>
38233              <resetValue>0xC4</resetValue>
38234              <resetMask>0xFFFF</resetMask>
38235              <fields>
38236                <field>
38237                  <name>BURST16</name>
38238                  <description>tLFPS-1 duration of LFPS transmission in 8 ns
38239(default 1.565 us)</description>
38240                  <bitRange>[15:0]</bitRange>
38241                  <access>read-write</access>
38242                </field>
38243              </fields>
38244            </register>
38245            <register>
38246              <name>LNK_LFPS_RX_LBPS_TPWM_GEN1</name>
38247              <description>LFPS LBPS Receive tPWM Gen1 Configuration</description>
38248              <addressOffset>0x240</addressOffset>
38249              <size>32</size>
38250              <access>read-write</access>
38251              <resetValue>0x12C00FA</resetValue>
38252              <resetMask>0xFFFFFFFF</resetMask>
38253              <fields>
38254                <field>
38255                  <name>REPEAT_MIN</name>
38256                  <description>Minimum number of clock periods for detection of tPWM of LFPS Based PWM Signaling (LBPS)  (default:  2.0 us)</description>
38257                  <bitRange>[15:0]</bitRange>
38258                  <access>read-write</access>
38259                </field>
38260                <field>
38261                  <name>REPEAT_MAX</name>
38262                  <description>Maximum number of clock periods for detection of tPWM of LFPS Based PWM Signaling (LBPS)  (default:  2.4 us)</description>
38263                  <bitRange>[31:16]</bitRange>
38264                  <access>read-write</access>
38265                </field>
38266              </fields>
38267            </register>
38268            <register>
38269              <name>LNK_LFPS_RX_LBPS_TLFPS0_GEN1</name>
38270              <description>LFPS LBPS Receive tLFPS-0 Gen1 Configuration</description>
38271              <addressOffset>0x244</addressOffset>
38272              <size>32</size>
38273              <access>read-write</access>
38274              <resetValue>0x6A0039</resetValue>
38275              <resetMask>0xFFFFFFFF</resetMask>
38276              <fields>
38277                <field>
38278                  <name>BURST_MIN</name>
38279                  <description>Minimum number of clock periods for detection of tLFPS-0 of LFPS Based PWM Signaling (LBPS)  (default:  0.45 us)</description>
38280                  <bitRange>[15:0]</bitRange>
38281                  <access>read-write</access>
38282                </field>
38283                <field>
38284                  <name>BURST_MAX</name>
38285                  <description>Maximum number of clock periods for detection of tLFPS-0 of LFPS Based PWM Signaling (LBPS)  (default:  0.85 us)</description>
38286                  <bitRange>[31:16]</bitRange>
38287                  <access>read-write</access>
38288                </field>
38289              </fields>
38290            </register>
38291            <register>
38292              <name>LNK_LFPS_RX_LBPS_TLFPS1_GEN1</name>
38293              <description>LFPS LBPS Receive tLFPS-1 Gen1 Configuration</description>
38294              <addressOffset>0x248</addressOffset>
38295              <size>32</size>
38296              <access>read-write</access>
38297              <resetValue>0xE700A0</resetValue>
38298              <resetMask>0xFFFFFFFF</resetMask>
38299              <fields>
38300                <field>
38301                  <name>BURST_MIN</name>
38302                  <description>Minimum number of clock periods for detection of tLFPS-1 of LFPS Based PWM Signaling (LBPS)  (default:  1.28 us)</description>
38303                  <bitRange>[15:0]</bitRange>
38304                  <access>read-write</access>
38305                </field>
38306                <field>
38307                  <name>BURST_MAX</name>
38308                  <description>Maximum number of clock periods for detection of tLFPS-1 of LFPS Based PWM Signaling (LBPS)  (default:  1.85 us)</description>
38309                  <bitRange>[31:16]</bitRange>
38310                  <access>read-write</access>
38311                </field>
38312              </fields>
38313            </register>
38314            <register>
38315              <name>LNK_LFPS_TX_LBPS_TPWM_GEN2</name>
38316              <description>LFPS LBPS Transmit tPWM Gen2 Configuration</description>
38317              <addressOffset>0x24C</addressOffset>
38318              <size>32</size>
38319              <access>read-write</access>
38320              <resetValue>0x2AF</resetValue>
38321              <resetMask>0xFFFF</resetMask>
38322              <fields>
38323                <field>
38324                  <name>REPEAT16</name>
38325                  <description>tPWM duration of LFPS transmission in 3.2 ns
38326(default 2.2 us)</description>
38327                  <bitRange>[15:0]</bitRange>
38328                  <access>read-write</access>
38329                </field>
38330              </fields>
38331            </register>
38332            <register>
38333              <name>LNK_LFPS_TX_LBPS_TLFPS0_GEN2</name>
38334              <description>LFPS LBPS Transmit tLFPS-0 Gen2 Configuration</description>
38335              <addressOffset>0x250</addressOffset>
38336              <size>32</size>
38337              <access>read-write</access>
38338              <resetValue>0xCB</resetValue>
38339              <resetMask>0xFFFF</resetMask>
38340              <fields>
38341                <field>
38342                  <name>BURST16</name>
38343                  <description>tLFPS-0 duration of LFPS transmission in 3.2 ns
38344(default 0.65 us)</description>
38345                  <bitRange>[15:0]</bitRange>
38346                  <access>read-write</access>
38347                </field>
38348              </fields>
38349            </register>
38350            <register>
38351              <name>LNK_LFPS_TX_LBPS_TLFPS1_GEN2</name>
38352              <description>LFPS LBPS Transmit tLFPS-1 Gen2 Configuration</description>
38353              <addressOffset>0x254</addressOffset>
38354              <size>32</size>
38355              <access>read-write</access>
38356              <resetValue>0x1E9</resetValue>
38357              <resetMask>0xFFFF</resetMask>
38358              <fields>
38359                <field>
38360                  <name>BURST16</name>
38361                  <description>tLFPS-1 duration of LFPS transmission in 3.2 ns
38362(default 1.565 us)</description>
38363                  <bitRange>[15:0]</bitRange>
38364                  <access>read-write</access>
38365                </field>
38366              </fields>
38367            </register>
38368            <register>
38369              <name>LNK_LFPS_RX_LBPS_TPWM_GEN2</name>
38370              <description>LFPS LBPS Receive tPWM Gen2 Configuration</description>
38371              <addressOffset>0x258</addressOffset>
38372              <size>32</size>
38373              <access>read-write</access>
38374              <resetValue>0x2EE0271</resetValue>
38375              <resetMask>0xFFFFFFFF</resetMask>
38376              <fields>
38377                <field>
38378                  <name>REPEAT_MIN</name>
38379                  <description>Minimum number of clock periods for detection of tPWM of LFPS Based PWM Signaling (LBPS)  (default:  2.0 us)</description>
38380                  <bitRange>[15:0]</bitRange>
38381                  <access>read-write</access>
38382                </field>
38383                <field>
38384                  <name>REPEAT_MAX</name>
38385                  <description>Maximum number of clock periods for detection of tPWM of LFPS Based PWM Signaling (LBPS)  (default:  2.4 us)</description>
38386                  <bitRange>[31:16]</bitRange>
38387                  <access>read-write</access>
38388                </field>
38389              </fields>
38390            </register>
38391            <register>
38392              <name>LNK_LFPS_RX_LBPS_TLFPS0_GEN2</name>
38393              <description>LFPS LBPS Receive tLFPS-0 Gen2 Configuration</description>
38394              <addressOffset>0x25C</addressOffset>
38395              <size>32</size>
38396              <access>read-write</access>
38397              <resetValue>0x109008D</resetValue>
38398              <resetMask>0xFFFFFFFF</resetMask>
38399              <fields>
38400                <field>
38401                  <name>BURST_MIN</name>
38402                  <description>Minimum number of clock periods for detection of tLFPS-0 of LFPS Based PWM Signaling (LBPS)  (default:  0.45 us)</description>
38403                  <bitRange>[15:0]</bitRange>
38404                  <access>read-write</access>
38405                </field>
38406                <field>
38407                  <name>BURST_MAX</name>
38408                  <description>Maximum number of clock periods for detection of tLFPS-0 of LFPS Based PWM Signaling (LBPS)  (default:  0.85 us)</description>
38409                  <bitRange>[31:16]</bitRange>
38410                  <access>read-write</access>
38411                </field>
38412              </fields>
38413            </register>
38414            <register>
38415              <name>LNK_LFPS_RX_LBPS_TLFPS1_GEN2</name>
38416              <description>LFPS LBPS Receive tLFPS-1 Gen2 Configuration</description>
38417              <addressOffset>0x260</addressOffset>
38418              <size>32</size>
38419              <access>read-write</access>
38420              <resetValue>0x2420190</resetValue>
38421              <resetMask>0xFFFFFFFF</resetMask>
38422              <fields>
38423                <field>
38424                  <name>BURST_MIN</name>
38425                  <description>Minimum number of clock periods for detection of tLFPS-1 of LFPS Based PWM Signaling (LBPS)  (default:  1.28 us)</description>
38426                  <bitRange>[15:0]</bitRange>
38427                  <access>read-write</access>
38428                </field>
38429                <field>
38430                  <name>BURST_MAX</name>
38431                  <description>Maximum number of clock periods for detection of tLFPS-1 of LFPS Based PWM Signaling (LBPS)  (default:  1.85 us)</description>
38432                  <bitRange>[31:16]</bitRange>
38433                  <access>read-write</access>
38434                </field>
38435              </fields>
38436            </register>
38437            <register>
38438              <name>LNK_LFPS_SCD_PATTERN</name>
38439              <description>LFPS SCD Pattern Configuration</description>
38440              <addressOffset>0x264</addressOffset>
38441              <size>32</size>
38442              <access>read-write</access>
38443              <resetValue>0xD2</resetValue>
38444              <resetMask>0xFF</resetMask>
38445              <fields>
38446                <field>
38447                  <name>SCD1_PATTERN</name>
38448                  <description>SCD1 pattern (default: b0010)
38449Only for Debug purpose and FW is not expected to modify</description>
38450                  <bitRange>[3:0]</bitRange>
38451                  <access>read-write</access>
38452                </field>
38453                <field>
38454                  <name>SCD2_PATTERN</name>
38455                  <description>SCD2 pattern (default: b1101)
38456Only for Debug purpose and FW is not expected to modify</description>
38457                  <bitRange>[7:4]</bitRange>
38458                  <access>read-write</access>
38459                </field>
38460              </fields>
38461            </register>
38462            <register>
38463              <name>LNK_TSEQ_COUNT_GEN1</name>
38464              <description>TSEQ Count Gen1 Configuration</description>
38465              <addressOffset>0x268</addressOffset>
38466              <size>32</size>
38467              <access>read-write</access>
38468              <resetValue>0x10000</resetValue>
38469              <resetMask>0xFFFFFF</resetMask>
38470              <fields>
38471                <field>
38472                  <name>COUNT24</name>
38473                  <description>The port in Gen 1 operation shall transition to Polling.Active after 65,536 consecutive TSEQ ordered sets
38474(default 65536)</description>
38475                  <bitRange>[23:0]</bitRange>
38476                  <access>read-write</access>
38477                </field>
38478              </fields>
38479            </register>
38480            <register>
38481              <name>LNK_TSEQ_COUNT_GEN2</name>
38482              <description>TSEQ Count Gen2 Configuration</description>
38483              <addressOffset>0x26C</addressOffset>
38484              <size>32</size>
38485              <access>read-write</access>
38486              <resetValue>0x80000</resetValue>
38487              <resetMask>0xFFFFFF</resetMask>
38488              <fields>
38489                <field>
38490                  <name>COUNT24</name>
38491                  <description>The port in Gen 2 operation shall transition to Polling.Active after 65,536 consecutive TSEQ ordered sets
38492(default 524288)</description>
38493                  <bitRange>[23:0]</bitRange>
38494                  <access>read-write</access>
38495                </field>
38496              </fields>
38497            </register>
38498            <register>
38499              <name>LNK_SCD1_GEN2_HSK</name>
38500              <description>SCD1 Handshake Gen2 Configuration</description>
38501              <addressOffset>0x270</addressOffset>
38502              <size>32</size>
38503              <access>read-write</access>
38504              <resetValue>0x2101</resetValue>
38505              <resetMask>0x7307</resetMask>
38506              <fields>
38507                <field>
38508                  <name>RX_SCDX_CNT</name>
38509                  <description>The port in SuperSpeedPlus operation shall transition to Polling.LFPSPlus if two SCD1 are transmitted after one SCD1 or SCD2 as defined in Section 6.9.4.2 is received.</description>
38510                  <bitRange>[2:0]</bitRange>
38511                  <access>read-write</access>
38512                </field>
38513                <field>
38514                  <name>ARX_SCDX_LIMIT</name>
38515                  <description>N/A</description>
38516                  <bitRange>[9:8]</bitRange>
38517                  <access>read-write</access>
38518                </field>
38519                <field>
38520                  <name>TX_ARX_SCD1_CNT</name>
38521                  <description>N/A</description>
38522                  <bitRange>[14:12]</bitRange>
38523                  <access>read-write</access>
38524                </field>
38525              </fields>
38526            </register>
38527            <register>
38528              <name>LNK_SCD1_GEN2_TO_GEN1_HSK</name>
38529              <description>SCD1 Handshake Gen2_to_Gen1 Configuration</description>
38530              <addressOffset>0x274</addressOffset>
38531              <size>32</size>
38532              <access>read-write</access>
38533              <resetValue>0x10112410</resetValue>
38534              <resetMask>0x1F777F7F</resetMask>
38535              <fields>
38536                <field>
38537                  <name>SCDXCHK_RX_LFPS_CNT</name>
38538                  <description>If it has received sixteen or more consecutive Polling.LFPS bursts and the tPollingSCDLFPSTimeout timer has not expired, it shall switch to SuperSpeed operation and transmit Polling.LFPS with non-varying tRepeat after four  SCD1 are transmitted.</description>
38539                  <bitRange>[6:0]</bitRange>
38540                  <access>read-write</access>
38541                </field>
38542                <field>
38543                  <name>G2G1_TX_SCD1_CNT</name>
38544                  <description>N/A</description>
38545                  <bitRange>[11:8]</bitRange>
38546                  <access>read-write</access>
38547                </field>
38548                <field>
38549                  <name>G2G1_RX_LFPS_CNT</name>
38550                  <description>The completion of SS Polling.LFPS with two consecutive Polling.LFPS bursts received and one SCD1 or four consecutive Polling.LFPS bursts transmitted after receiving one Polling.LFPS burst.</description>
38551                  <bitRange>[14:12]</bitRange>
38552                  <access>read-write</access>
38553                </field>
38554                <field>
38555                  <name>G2G1_ARX_LFPS_LIMIT</name>
38556                  <description>N/A</description>
38557                  <bitRange>[18:16]</bitRange>
38558                  <access>read-write</access>
38559                </field>
38560                <field>
38561                  <name>G2G1_TX_ARX_SCD1_CNT</name>
38562                  <description>N/A</description>
38563                  <bitRange>[22:20]</bitRange>
38564                  <access>read-write</access>
38565                </field>
38566                <field>
38567                  <name>G2G1_TX_LFPS_CNT</name>
38568                  <description>At least 16 consecutive Polling.LFPS bursts meeting the Polling.LFPS specification defined in Section 6.9 are sent.</description>
38569                  <bitRange>[28:24]</bitRange>
38570                  <access>read-write</access>
38571                </field>
38572              </fields>
38573            </register>
38574            <register>
38575              <name>LNK_SCD1_OBSERVE</name>
38576              <description>Polling.LFPS SCD1 Observability</description>
38577              <addressOffset>0x278</addressOffset>
38578              <size>32</size>
38579              <access>read-write</access>
38580              <resetValue>0x0</resetValue>
38581              <resetMask>0xC0707077</resetMask>
38582              <fields>
38583                <field>
38584                  <name>RCVD_SCD2_CNT</name>
38585                  <description>N/A</description>
38586                  <bitRange>[2:0]</bitRange>
38587                  <access>read-only</access>
38588                </field>
38589                <field>
38590                  <name>RCVD_SCD1_CNT</name>
38591                  <description>N/A</description>
38592                  <bitRange>[6:4]</bitRange>
38593                  <access>read-only</access>
38594                </field>
38595                <field>
38596                  <name>SENT_SCD1_CNT_G2_ARX</name>
38597                  <description>N/A</description>
38598                  <bitRange>[14:12]</bitRange>
38599                  <access>read-only</access>
38600                </field>
38601                <field>
38602                  <name>SENT_SCD1_CNT_G2G1_ARX</name>
38603                  <description>N/A</description>
38604                  <bitRange>[22:20]</bitRange>
38605                  <access>read-only</access>
38606                </field>
38607                <field>
38608                  <name>G2G1_LFPS_HSK_DONE</name>
38609                  <description>Gen2 to Gen1 LFPS Handshake Done since last cleared by CPU</description>
38610                  <bitRange>[30:30]</bitRange>
38611                  <access>read-write</access>
38612                </field>
38613                <field>
38614                  <name>SCD1_HSK_DONE</name>
38615                  <description>SCD1 handshake Done since last cleared by CPU</description>
38616                  <bitRange>[31:31]</bitRange>
38617                  <access>read-write</access>
38618                </field>
38619              </fields>
38620            </register>
38621            <register>
38622              <name>LNK_SCD2_GEN2_HSK</name>
38623              <description>SCD2 Handshake Gen2 Configuration</description>
38624              <addressOffset>0x27C</addressOffset>
38625              <size>32</size>
38626              <access>read-write</access>
38627              <resetValue>0x2101</resetValue>
38628              <resetMask>0x7307</resetMask>
38629              <fields>
38630                <field>
38631                  <name>RX_SCD2_CNT</name>
38632                  <description>The port in SuperSpeedPlus operation shall transition to Polling.PortMatch if two SCD2 are transmitted after one SCD2 as defined in Section 6.9.4.2 is received.</description>
38633                  <bitRange>[2:0]</bitRange>
38634                  <access>read-write</access>
38635                </field>
38636                <field>
38637                  <name>ARX_SCD2_LIMIT</name>
38638                  <description>N/A</description>
38639                  <bitRange>[9:8]</bitRange>
38640                  <access>read-write</access>
38641                </field>
38642                <field>
38643                  <name>TX_ARX_SCD2_CNT</name>
38644                  <description>N/A</description>
38645                  <bitRange>[14:12]</bitRange>
38646                  <access>read-write</access>
38647                </field>
38648              </fields>
38649            </register>
38650            <register>
38651              <name>LNK_SCD2_GEN2_TO_GEN1_HSK</name>
38652              <description>SCD2 Handshake Gen2_to_Gen1 Configuration</description>
38653              <addressOffset>0x280</addressOffset>
38654              <size>32</size>
38655              <access>read-write</access>
38656              <resetValue>0x14000040</resetValue>
38657              <resetMask>0x1F00007F</resetMask>
38658              <fields>
38659                <field>
38660                  <name>SCD2CHK_RX_LFPS_CNT</name>
38661                  <description>The port in SuperSpeedPlus operation shall transmit SCD2 defined in Table 6-33. If SCD2 cannot be found in 64 consecutive Polling.LFPS received, it shall transmit Polling.LFPS with non-varying tRepeat instead of SCD2.</description>
38662                  <bitRange>[6:0]</bitRange>
38663                  <access>read-write</access>
38664                </field>
38665                <field>
38666                  <name>G2G1_TX_LFPS_CNT</name>
38667                  <description>Twenty Polling.LFPS bursts with non-varying tRepeat are transmitted, after finding no SCD2 is detected.</description>
38668                  <bitRange>[28:24]</bitRange>
38669                  <access>read-write</access>
38670                </field>
38671              </fields>
38672            </register>
38673            <register>
38674              <name>LNK_SCD2_OBSERVE</name>
38675              <description>Polling.LFPSPlus SCD2 Observability</description>
38676              <addressOffset>0x284</addressOffset>
38677              <size>32</size>
38678              <access>read-write</access>
38679              <resetValue>0x0</resetValue>
38680              <resetMask>0xC0000707</resetMask>
38681              <fields>
38682                <field>
38683                  <name>RCVD_SCD2_CNT</name>
38684                  <description>The port in SuperSpeedPlus operation shall transition to Polling.PortMatch if two SCD2 are transmitted after one SCD2 as defined in Section 6.9.4.2 is received.</description>
38685                  <bitRange>[2:0]</bitRange>
38686                  <access>read-only</access>
38687                </field>
38688                <field>
38689                  <name>SENT_SCD2_CNT_G2_ARX</name>
38690                  <description>N/A</description>
38691                  <bitRange>[10:8]</bitRange>
38692                  <access>read-only</access>
38693                </field>
38694                <field>
38695                  <name>G2G1_LFPS_HSK_DONE</name>
38696                  <description>Gen2 to Gen1 LFPS Handshake Done since last cleared by CPU</description>
38697                  <bitRange>[30:30]</bitRange>
38698                  <access>read-write</access>
38699                </field>
38700                <field>
38701                  <name>SCD2_HSK_DONE</name>
38702                  <description>SCD2 handshake Done since last cleared by CPU
38703Note: This asserts before SCD_END  transmitting. After SCD_END transmitting completion, LTSSM moves to PORT_MATCH state.</description>
38704                  <bitRange>[31:31]</bitRange>
38705                  <access>read-write</access>
38706                </field>
38707              </fields>
38708            </register>
38709            <register>
38710              <name>LNK_CAP_LBPM_HSK</name>
38711              <description>Polling.PortMatch LBPM Handshake Configuration</description>
38712              <addressOffset>0x288</addressOffset>
38713              <size>32</size>
38714              <access>read-write</access>
38715              <resetValue>0x5220</resetValue>
38716              <resetMask>0xF770</resetMask>
38717              <fields>
38718                <field>
38719                  <name>RX_CAP_LBPM_CNT</name>
38720                  <description>The port shall transition to Polling.PortConfig when four consecutive and matched PHY Capability LBPMs are sent after two consecutive and matched PHY Capability LBPMs or PHY Ready LBPMs are received.</description>
38721                  <bitRange>[6:4]</bitRange>
38722                  <access>read-write</access>
38723                </field>
38724                <field>
38725                  <name>ARX_LBPM_LIMIT</name>
38726                  <description>N/A</description>
38727                  <bitRange>[10:8]</bitRange>
38728                  <access>read-write</access>
38729                </field>
38730                <field>
38731                  <name>TX_ARX_CAP_LBPM_CNT</name>
38732                  <description>N/A</description>
38733                  <bitRange>[15:12]</bitRange>
38734                  <access>read-write</access>
38735                </field>
38736              </fields>
38737            </register>
38738            <register>
38739              <name>LNK_CAP_LBPM_OBSERVE</name>
38740              <description>Polling.PortMatch LBPM Observability</description>
38741              <addressOffset>0x28C</addressOffset>
38742              <size>32</size>
38743              <access>read-write</access>
38744              <resetValue>0x0</resetValue>
38745              <resetMask>0x80777777</resetMask>
38746              <fields>
38747                <field>
38748                  <name>RCVD_10GX1_CAP_LBPM_CNT</name>
38749                  <description>N/A</description>
38750                  <bitRange>[2:0]</bitRange>
38751                  <access>read-only</access>
38752                </field>
38753                <field>
38754                  <name>RCVD_5GX1_CAP_LBPM_CNT</name>
38755                  <description>N/A</description>
38756                  <bitRange>[6:4]</bitRange>
38757                  <access>read-only</access>
38758                </field>
38759                <field>
38760                  <name>RCVD_10GX2_CAP_LBPM_CNT</name>
38761                  <description>N/A</description>
38762                  <bitRange>[10:8]</bitRange>
38763                  <access>read-only</access>
38764                </field>
38765                <field>
38766                  <name>RCVD_5GX2_CAP_LBPM_CNT</name>
38767                  <description>N/A</description>
38768                  <bitRange>[14:12]</bitRange>
38769                  <access>read-only</access>
38770                </field>
38771                <field>
38772                  <name>RCVD_READY_LBPM_CNT</name>
38773                  <description>N/A</description>
38774                  <bitRange>[18:16]</bitRange>
38775                  <access>read-only</access>
38776                </field>
38777                <field>
38778                  <name>SENT_CAP_LBPM_CNT_ARX</name>
38779                  <description>N/A</description>
38780                  <bitRange>[22:20]</bitRange>
38781                  <access>read-only</access>
38782                </field>
38783                <field>
38784                  <name>CAP_LBPM_HSK_DONE</name>
38785                  <description>Capability LBPM handshake Done since last cleared by CPU</description>
38786                  <bitRange>[31:31]</bitRange>
38787                  <access>read-write</access>
38788                </field>
38789              </fields>
38790            </register>
38791            <register>
38792              <name>LNK_READY_LBPM_HSK</name>
38793              <description>Polling.PortConfig LBPM Handshake Configuration</description>
38794              <addressOffset>0x290</addressOffset>
38795              <size>32</size>
38796              <access>read-write</access>
38797              <resetValue>0x422</resetValue>
38798              <resetMask>0xFF0F77</resetMask>
38799              <fields>
38800                <field>
38801                  <name>RX_RDY_LBPM_CNT</name>
38802                  <description>The port shall transition to Polling.PortConfig when four consecutive and matched PHY Capability LBPMs are sent after two consecutive and matched PHY Capability LBPMs or PHY Ready LBPMs are received.</description>
38803                  <bitRange>[2:0]</bitRange>
38804                  <access>read-write</access>
38805                </field>
38806                <field>
38807                  <name>ARX_RDY_LBPM_LIMIT</name>
38808                  <description>N/A</description>
38809                  <bitRange>[6:4]</bitRange>
38810                  <access>read-write</access>
38811                </field>
38812                <field>
38813                  <name>TX_ARX_RDY_LBPM_CNT</name>
38814                  <description>N/A</description>
38815                  <bitRange>[11:8]</bitRange>
38816                  <access>read-write</access>
38817                </field>
38818                <field>
38819                  <name>ENTRY_TO_TX_DELAY</name>
38820                  <description>Start-up delay to transmit Ready.LBPMs once LTSSM enters the Polling.PortConfig state if PHY re-configuration required.
38821Note that the delay value is counted in the unit of 8 ns.</description>
38822                  <bitRange>[23:16]</bitRange>
38823                  <access>read-write</access>
38824                </field>
38825              </fields>
38826            </register>
38827            <register>
38828              <name>LNK_READY_LBPM_OBSERVE</name>
38829              <description>Polling.PortConfig LBPM Observability</description>
38830              <addressOffset>0x294</addressOffset>
38831              <size>32</size>
38832              <access>read-write</access>
38833              <resetValue>0x0</resetValue>
38834              <resetMask>0x800000F7</resetMask>
38835              <fields>
38836                <field>
38837                  <name>RCVD_RDY_LBPM_CNT</name>
38838                  <description>The port shall transition to Polling.PortConfig when four consecutive and matched PHY Capability LBPMs are sent after two consecutive and matched PHY Capability LBPMs or PHY Ready LBPMs are received.</description>
38839                  <bitRange>[2:0]</bitRange>
38840                  <access>read-only</access>
38841                </field>
38842                <field>
38843                  <name>SENT_RDY_LBPM_CNT_ARX</name>
38844                  <description>N/A</description>
38845                  <bitRange>[7:4]</bitRange>
38846                  <access>read-only</access>
38847                </field>
38848                <field>
38849                  <name>RDY_LBPM_HSK_DONE</name>
38850                  <description>ReadyLBPM handshake Done since last cleared by CPU</description>
38851                  <bitRange>[31:31]</bitRange>
38852                  <access>read-write</access>
38853                </field>
38854              </fields>
38855            </register>
38856            <register>
38857              <name>LNK_RCVD_LBPM_OBSERVE</name>
38858              <description>Received LBPM Observability</description>
38859              <addressOffset>0x298</addressOffset>
38860              <size>32</size>
38861              <access>read-only</access>
38862              <resetValue>0x0</resetValue>
38863              <resetMask>0xFF</resetMask>
38864              <fields>
38865                <field>
38866                  <name>LBPM</name>
38867                  <description>Reveived LBPM</description>
38868                  <bitRange>[7:0]</bitRange>
38869                  <access>read-only</access>
38870                </field>
38871              </fields>
38872            </register>
38873            <register>
38874              <name>LNK_LTSSM_SCD_LFPS_TIMEOUT</name>
38875              <description>LTSSM SCD LFPS Timeout (SuperSpeedPlus Only)</description>
38876              <addressOffset>0x29C</addressOffset>
38877              <size>32</size>
38878              <access>read-write</access>
38879              <resetValue>0x1D4C</resetValue>
38880              <resetMask>0xFFFF</resetMask>
38881              <fields>
38882                <field>
38883                  <name>TIMEOUT16</name>
38884                  <description>LTSSM Polling.LFPS/Polling.LFPSPlus Timeout (default: 60 us in 8 ns)
38885(0= Timer Disabled)</description>
38886                  <bitRange>[15:0]</bitRange>
38887                  <access>read-write</access>
38888                </field>
38889              </fields>
38890            </register>
38891            <register>
38892              <name>LNK_LTSSM_LBPM_LFPS_TIMEOUT</name>
38893              <description>LTSSM LBPM LFPS Timeout (SuperSpeedPlus Only)</description>
38894              <addressOffset>0x2A0</addressOffset>
38895              <size>32</size>
38896              <access>read-write</access>
38897              <resetValue>0x16E360</resetValue>
38898              <resetMask>0xFFFFFF</resetMask>
38899              <fields>
38900                <field>
38901                  <name>TIMEOUT24</name>
38902                  <description>LTSSM PollingPortMatch/Polling.PortConfig Timeout (default: 12 ms in 8ns)
38903(0= Timer Disabled)</description>
38904                  <bitRange>[23:0]</bitRange>
38905                  <access>read-write</access>
38906                </field>
38907              </fields>
38908            </register>
38909            <register>
38910              <name>LNK_COMPLIANCE_PATTERN_9_TO_12</name>
38911              <description>Compliance Pattern CP9 to CP12</description>
38912              <addressOffset>0x2A4</addressOffset>
38913              <size>32</size>
38914              <access>read-write</access>
38915              <resetValue>0x2</resetValue>
38916              <resetMask>0x3FFFF</resetMask>
38917              <fields>
38918                <field>
38919                  <name>DEEMPH_COEFF</name>
38920                  <description>N/A</description>
38921                  <bitRange>[17:0]</bitRange>
38922                  <access>read-write</access>
38923                </field>
38924              </fields>
38925            </register>
38926            <register>
38927              <name>LNK_COMPLIANCE_PATTERN_13</name>
38928              <description>Compliance Pattern CP13</description>
38929              <addressOffset>0x2A8</addressOffset>
38930              <size>32</size>
38931              <access>read-write</access>
38932              <resetValue>0x2</resetValue>
38933              <resetMask>0x3FFFF</resetMask>
38934              <fields>
38935                <field>
38936                  <name>DEEMPH_COEFF</name>
38937                  <description>N/A</description>
38938                  <bitRange>[17:0]</bitRange>
38939                  <access>read-write</access>
38940                </field>
38941              </fields>
38942            </register>
38943            <register>
38944              <name>LNK_COMPLIANCE_PATTERN_14</name>
38945              <description>Compliance Pattern CP14</description>
38946              <addressOffset>0x2AC</addressOffset>
38947              <size>32</size>
38948              <access>read-write</access>
38949              <resetValue>0x2</resetValue>
38950              <resetMask>0x3FFFF</resetMask>
38951              <fields>
38952                <field>
38953                  <name>DEEMPH_COEFF</name>
38954                  <description>N/A</description>
38955                  <bitRange>[17:0]</bitRange>
38956                  <access>read-write</access>
38957                </field>
38958              </fields>
38959            </register>
38960            <register>
38961              <name>LNK_COMPLIANCE_PATTERN_15</name>
38962              <description>Compliance Pattern CP15</description>
38963              <addressOffset>0x2B0</addressOffset>
38964              <size>32</size>
38965              <access>read-write</access>
38966              <resetValue>0x2</resetValue>
38967              <resetMask>0x3FFFF</resetMask>
38968              <fields>
38969                <field>
38970                  <name>DEEMPH_COEFF</name>
38971                  <description>N/A</description>
38972                  <bitRange>[17:0]</bitRange>
38973                  <access>read-write</access>
38974                </field>
38975              </fields>
38976            </register>
38977            <register>
38978              <name>LNK_COMPLIANCE_PATTERN_16</name>
38979              <description>Compliance Pattern CP16</description>
38980              <addressOffset>0x2B4</addressOffset>
38981              <size>32</size>
38982              <access>read-write</access>
38983              <resetValue>0x2</resetValue>
38984              <resetMask>0x3FFFF</resetMask>
38985              <fields>
38986                <field>
38987                  <name>DEEMPH_COEFF</name>
38988                  <description>N/A</description>
38989                  <bitRange>[17:0]</bitRange>
38990                  <access>read-write</access>
38991                </field>
38992              </fields>
38993            </register>
38994            <register>
38995              <dim>21</dim>
38996              <dimIncrement>4</dimIncrement>
38997              <name>LNK_RX_TYPE1_HEADER_BUFFER[%s]</name>
38998              <description>Receive Type1 Packet Header Buffer</description>
38999              <addressOffset>0x300</addressOffset>
39000              <size>32</size>
39001              <access>read-only</access>
39002              <resetValue>0x0</resetValue>
39003              <resetMask>0xFFFFFFFF</resetMask>
39004              <fields>
39005                <field>
39006                  <name>HEADER</name>
39007                  <description>Rx Header Packet(SS)/Type1 Rx Header Packet(SSP)</description>
39008                  <bitRange>[31:0]</bitRange>
39009                  <access>read-only</access>
39010                </field>
39011              </fields>
39012            </register>
39013            <register>
39014              <name>LNK_RX_TYPE1_HEADER_BUFFER_STATE_0</name>
39015              <description>Receive Type1 Packet Header Buffer Status 0</description>
39016              <addressOffset>0x380</addressOffset>
39017              <size>32</size>
39018              <access>read-only</access>
39019              <resetValue>0x0</resetValue>
39020              <resetMask>0x3F3F3F3F</resetMask>
39021              <fields>
39022                <field>
39023                  <name>SEQUENCE0</name>
39024                  <description>Packet Sequence Number</description>
39025                  <bitRange>[3:0]</bitRange>
39026                  <access>read-only</access>
39027                </field>
39028                <field>
39029                  <name>VALID0</name>
39030                  <description>Packet Valid. Set on transmission of LGOOD_n, cleared on transmission of LCRD_x/LCRD1_x</description>
39031                  <bitRange>[4:4]</bitRange>
39032                  <access>read-only</access>
39033                </field>
39034                <field>
39035                  <name>RCVD0</name>
39036                  <description>Packet Received. Set when packet received (good or bad), cleared on transmission of LCRD_x/LCRD1_x</description>
39037                  <bitRange>[5:5]</bitRange>
39038                  <access>read-only</access>
39039                </field>
39040                <field>
39041                  <name>SEQUENCE1</name>
39042                  <description>Packet Sequence Number</description>
39043                  <bitRange>[11:8]</bitRange>
39044                  <access>read-only</access>
39045                </field>
39046                <field>
39047                  <name>VALID1</name>
39048                  <description>Packet Valid. Set on transmission of LGOOD_n, cleared on transmission of LCRD_x/LCRD1_x</description>
39049                  <bitRange>[12:12]</bitRange>
39050                  <access>read-only</access>
39051                </field>
39052                <field>
39053                  <name>RCVD1</name>
39054                  <description>Packet Received. Set when packet received (good or bad), cleared on transmission of LCRD_x/LCRD1_x</description>
39055                  <bitRange>[13:13]</bitRange>
39056                  <access>read-only</access>
39057                </field>
39058                <field>
39059                  <name>SEQUENCE2</name>
39060                  <description>Packet Sequence Number</description>
39061                  <bitRange>[19:16]</bitRange>
39062                  <access>read-only</access>
39063                </field>
39064                <field>
39065                  <name>VALID2</name>
39066                  <description>Packet Valid. Set on transmission of LGOOD_n, cleared on transmission of LCRD_x/LCRD1_x</description>
39067                  <bitRange>[20:20]</bitRange>
39068                  <access>read-only</access>
39069                </field>
39070                <field>
39071                  <name>RCVD2</name>
39072                  <description>Packet Received. Set when packet received (good or bad), cleared on transmission of LCRD_x/LCRD1_x</description>
39073                  <bitRange>[21:21]</bitRange>
39074                  <access>read-only</access>
39075                </field>
39076                <field>
39077                  <name>SEQUENCE3</name>
39078                  <description>Packet Sequence Number</description>
39079                  <bitRange>[27:24]</bitRange>
39080                  <access>read-only</access>
39081                </field>
39082                <field>
39083                  <name>VALID3</name>
39084                  <description>Packet Valid. Set on transmission of LGOOD_n, cleared on transmission of LCRD_x/LCRD1_x</description>
39085                  <bitRange>[28:28]</bitRange>
39086                  <access>read-only</access>
39087                </field>
39088                <field>
39089                  <name>RCVD3</name>
39090                  <description>Packet Received. Set when packet received (good or bad), cleared on transmission of LCRD_x/LCRD1_x</description>
39091                  <bitRange>[29:29]</bitRange>
39092                  <access>read-only</access>
39093                </field>
39094              </fields>
39095            </register>
39096            <register>
39097              <name>LNK_RX_TYPE1_HEADER_BUFFER_STATE_1</name>
39098              <description>Receive Type1 Packet Header Buffer Status 1</description>
39099              <addressOffset>0x384</addressOffset>
39100              <size>32</size>
39101              <access>read-only</access>
39102              <resetValue>0x0</resetValue>
39103              <resetMask>0x3F3F3F</resetMask>
39104              <fields>
39105                <field>
39106                  <name>SEQUENCE4</name>
39107                  <description>Packet Sequence Number</description>
39108                  <bitRange>[3:0]</bitRange>
39109                  <access>read-only</access>
39110                </field>
39111                <field>
39112                  <name>VALID4</name>
39113                  <description>Packet Valid. Set on transmission of LGOOD_n, cleared on transmission of LCRD_x/LCRD1_x</description>
39114                  <bitRange>[4:4]</bitRange>
39115                  <access>read-only</access>
39116                </field>
39117                <field>
39118                  <name>RCVD4</name>
39119                  <description>Packet Received. Set when packet received (good or bad), cleared on transmission of LCRD_x/LCRD1_x</description>
39120                  <bitRange>[5:5]</bitRange>
39121                  <access>read-only</access>
39122                </field>
39123                <field>
39124                  <name>SEQUENCE5</name>
39125                  <description>Packet Sequence Number</description>
39126                  <bitRange>[11:8]</bitRange>
39127                  <access>read-only</access>
39128                </field>
39129                <field>
39130                  <name>VALID5</name>
39131                  <description>Packet Valid. Set on transmission of LGOOD_n, cleared on transmission of LCRD_x/LCRD1_x</description>
39132                  <bitRange>[12:12]</bitRange>
39133                  <access>read-only</access>
39134                </field>
39135                <field>
39136                  <name>RCVD5</name>
39137                  <description>Packet Received. Set when packet received (good or bad), cleared on transmission of LCRD_x/LCRD1_x</description>
39138                  <bitRange>[13:13]</bitRange>
39139                  <access>read-only</access>
39140                </field>
39141                <field>
39142                  <name>SEQUENCE6</name>
39143                  <description>Packet Sequence Number</description>
39144                  <bitRange>[19:16]</bitRange>
39145                  <access>read-only</access>
39146                </field>
39147                <field>
39148                  <name>VALID6</name>
39149                  <description>Packet Valid. Set on transmission of LGOOD_n, cleared on transmission of LCRD_x/LCRD1_x</description>
39150                  <bitRange>[20:20]</bitRange>
39151                  <access>read-only</access>
39152                </field>
39153                <field>
39154                  <name>RCVD6</name>
39155                  <description>Packet Received. Set when packet received (good or bad), cleared on transmission of LCRD_x/LCRD1_x</description>
39156                  <bitRange>[21:21]</bitRange>
39157                  <access>read-only</access>
39158                </field>
39159              </fields>
39160            </register>
39161            <register>
39162              <dim>21</dim>
39163              <dimIncrement>4</dimIncrement>
39164              <name>LNK_RX_TYPE2_HEADER_BUFFER[%s]</name>
39165              <description>Receive Type2 Packet Header Buffer</description>
39166              <addressOffset>0x400</addressOffset>
39167              <size>32</size>
39168              <access>read-only</access>
39169              <resetValue>0x0</resetValue>
39170              <resetMask>0xFFFFFFFF</resetMask>
39171              <fields>
39172                <field>
39173                  <name>HEADER</name>
39174                  <description>Type2 Rx Header Packet(SSP)</description>
39175                  <bitRange>[31:0]</bitRange>
39176                  <access>read-only</access>
39177                </field>
39178              </fields>
39179            </register>
39180            <register>
39181              <name>LNK_RX_TYPE2_HEADER_BUFFER_STATE_0</name>
39182              <description>Receive Type2 Packet Header Buffer Status 0</description>
39183              <addressOffset>0x480</addressOffset>
39184              <size>32</size>
39185              <access>read-only</access>
39186              <resetValue>0x0</resetValue>
39187              <resetMask>0x3F3F3F3F</resetMask>
39188              <fields>
39189                <field>
39190                  <name>SEQUENCE0</name>
39191                  <description>Packet Sequence Number</description>
39192                  <bitRange>[3:0]</bitRange>
39193                  <access>read-only</access>
39194                </field>
39195                <field>
39196                  <name>VALID0</name>
39197                  <description>Packet Valid. Set on transmission of LGOOD_n, cleared on transmission of LCRD2_x</description>
39198                  <bitRange>[4:4]</bitRange>
39199                  <access>read-only</access>
39200                </field>
39201                <field>
39202                  <name>RCVD0</name>
39203                  <description>Packet Received. Set when packet received (good or bad), cleared on transmission of LCRD2_x</description>
39204                  <bitRange>[5:5]</bitRange>
39205                  <access>read-only</access>
39206                </field>
39207                <field>
39208                  <name>SEQUENCE1</name>
39209                  <description>Packet Sequence Number</description>
39210                  <bitRange>[11:8]</bitRange>
39211                  <access>read-only</access>
39212                </field>
39213                <field>
39214                  <name>VALID1</name>
39215                  <description>Packet Valid. Set on transmission of LGOOD_n, cleared on transmission of LCRD2_x</description>
39216                  <bitRange>[12:12]</bitRange>
39217                  <access>read-only</access>
39218                </field>
39219                <field>
39220                  <name>RCVD1</name>
39221                  <description>Packet Received. Set when packet received (good or bad), cleared on transmission of LCRD2_x</description>
39222                  <bitRange>[13:13]</bitRange>
39223                  <access>read-only</access>
39224                </field>
39225                <field>
39226                  <name>SEQUENCE2</name>
39227                  <description>Packet Sequence Number</description>
39228                  <bitRange>[19:16]</bitRange>
39229                  <access>read-only</access>
39230                </field>
39231                <field>
39232                  <name>VALID2</name>
39233                  <description>Packet Valid. Set on transmission of LGOOD_n, cleared on transmission of LCRD2_x</description>
39234                  <bitRange>[20:20]</bitRange>
39235                  <access>read-only</access>
39236                </field>
39237                <field>
39238                  <name>RCVD2</name>
39239                  <description>Packet Received. Set when packet received (good or bad), cleared on transmission of LCRD2_x</description>
39240                  <bitRange>[21:21]</bitRange>
39241                  <access>read-only</access>
39242                </field>
39243                <field>
39244                  <name>SEQUENCE3</name>
39245                  <description>Packet Sequence Number</description>
39246                  <bitRange>[27:24]</bitRange>
39247                  <access>read-only</access>
39248                </field>
39249                <field>
39250                  <name>VALID3</name>
39251                  <description>Packet Valid. Set on transmission of LGOOD_n, cleared on transmission of LCRD2_x</description>
39252                  <bitRange>[28:28]</bitRange>
39253                  <access>read-only</access>
39254                </field>
39255                <field>
39256                  <name>RCVD3</name>
39257                  <description>Packet Received. Set when packet received (good or bad), cleared on transmission of LCRD2_x</description>
39258                  <bitRange>[29:29]</bitRange>
39259                  <access>read-only</access>
39260                </field>
39261              </fields>
39262            </register>
39263            <register>
39264              <name>LNK_RX_TYPE2_HEADER_BUFFER_STATE_1</name>
39265              <description>Receive Type2 Packet Header Buffer Status 1</description>
39266              <addressOffset>0x484</addressOffset>
39267              <size>32</size>
39268              <access>read-only</access>
39269              <resetValue>0x0</resetValue>
39270              <resetMask>0x3F3F3F</resetMask>
39271              <fields>
39272                <field>
39273                  <name>SEQUENCE4</name>
39274                  <description>Packet Sequence Number</description>
39275                  <bitRange>[3:0]</bitRange>
39276                  <access>read-only</access>
39277                </field>
39278                <field>
39279                  <name>VALID4</name>
39280                  <description>Packet Valid. Set on transmission of LGOOD_n, cleared on transmission of LCRD2_x</description>
39281                  <bitRange>[4:4]</bitRange>
39282                  <access>read-only</access>
39283                </field>
39284                <field>
39285                  <name>RCVD4</name>
39286                  <description>Packet Received. Set when packet received (good or bad), cleared on transmission of LCRD2_x</description>
39287                  <bitRange>[5:5]</bitRange>
39288                  <access>read-only</access>
39289                </field>
39290                <field>
39291                  <name>SEQUENCE5</name>
39292                  <description>Packet Sequence Number</description>
39293                  <bitRange>[11:8]</bitRange>
39294                  <access>read-only</access>
39295                </field>
39296                <field>
39297                  <name>VALID5</name>
39298                  <description>Packet Valid. Set on transmission of LGOOD_n, cleared on transmission of LCRD2_x</description>
39299                  <bitRange>[12:12]</bitRange>
39300                  <access>read-only</access>
39301                </field>
39302                <field>
39303                  <name>RCVD5</name>
39304                  <description>Packet Received. Set when packet received (good or bad), cleared on transmission of LCRD2_x</description>
39305                  <bitRange>[13:13]</bitRange>
39306                  <access>read-only</access>
39307                </field>
39308                <field>
39309                  <name>SEQUENCE6</name>
39310                  <description>Packet Sequence Number</description>
39311                  <bitRange>[19:16]</bitRange>
39312                  <access>read-only</access>
39313                </field>
39314                <field>
39315                  <name>VALID6</name>
39316                  <description>Packet Valid. Set on transmission of LGOOD_n, cleared on transmission of LCRD2_x</description>
39317                  <bitRange>[20:20]</bitRange>
39318                  <access>read-only</access>
39319                </field>
39320                <field>
39321                  <name>RCVD6</name>
39322                  <description>Packet Received. Set when packet received (good or bad), cleared on transmission of LCRD2_x</description>
39323                  <bitRange>[21:21]</bitRange>
39324                  <access>read-only</access>
39325                </field>
39326              </fields>
39327            </register>
39328            <register>
39329              <dim>21</dim>
39330              <dimIncrement>4</dimIncrement>
39331              <name>LNK_TX_TYPE1_HEADER_BUFFER[%s]</name>
39332              <description>Transmit Type1 Packet Header Buffer</description>
39333              <addressOffset>0x500</addressOffset>
39334              <size>32</size>
39335              <access>read-only</access>
39336              <resetValue>0x0</resetValue>
39337              <resetMask>0xFFFFFFFF</resetMask>
39338              <fields>
39339                <field>
39340                  <name>HEADER</name>
39341                  <description>Tx Header Packet(SS)/Type1 Rx Header Packet(SSP)</description>
39342                  <bitRange>[31:0]</bitRange>
39343                  <access>read-only</access>
39344                </field>
39345              </fields>
39346            </register>
39347            <register>
39348              <name>LNK_TX_TYPE1_HEADER_BUFFER_STATE_0</name>
39349              <description>Transmit Type1 Packet Header Buffer Status 0</description>
39350              <addressOffset>0x580</addressOffset>
39351              <size>32</size>
39352              <access>read-only</access>
39353              <resetValue>0x0</resetValue>
39354              <resetMask>0x3F3F3F3F</resetMask>
39355              <fields>
39356                <field>
39357                  <name>SEQUENCE0</name>
39358                  <description>Packet Sequence Number</description>
39359                  <bitRange>[3:0]</bitRange>
39360                  <access>read-only</access>
39361                </field>
39362                <field>
39363                  <name>VALID0</name>
39364                  <description>Packet Valid. Set on receipt of buffer from Protocol Layer; cleared on receipt of LGOOD_n</description>
39365                  <bitRange>[4:4]</bitRange>
39366                  <access>read-only</access>
39367                </field>
39368                <field>
39369                  <name>SENT0</name>
39370                  <description>Packet Sent. Set on receipt of buffer from Protocol Layer; cleared when sent out for first time</description>
39371                  <bitRange>[5:5]</bitRange>
39372                  <access>read-only</access>
39373                </field>
39374                <field>
39375                  <name>SEQUENCE1</name>
39376                  <description>Packet Sequence Number</description>
39377                  <bitRange>[11:8]</bitRange>
39378                  <access>read-only</access>
39379                </field>
39380                <field>
39381                  <name>VALID1</name>
39382                  <description>Packet Valid. Set on receipt of buffer from Protocol Layer; cleared on receipt of LGOOD_n</description>
39383                  <bitRange>[12:12]</bitRange>
39384                  <access>read-only</access>
39385                </field>
39386                <field>
39387                  <name>SENT1</name>
39388                  <description>Packet Sent. Set on receipt of buffer from Protocol Layer; cleared when sent out for first time</description>
39389                  <bitRange>[13:13]</bitRange>
39390                  <access>read-only</access>
39391                </field>
39392                <field>
39393                  <name>SEQUENCE2</name>
39394                  <description>Packet Sequence Number</description>
39395                  <bitRange>[19:16]</bitRange>
39396                  <access>read-only</access>
39397                </field>
39398                <field>
39399                  <name>VALID2</name>
39400                  <description>Packet Valid. Set on receipt of buffer from Protocol Layer; cleared on receipt of LGOOD_n</description>
39401                  <bitRange>[20:20]</bitRange>
39402                  <access>read-only</access>
39403                </field>
39404                <field>
39405                  <name>SENT2</name>
39406                  <description>Packet Sent. Set on receipt of buffer from Protocol Layer; cleared when sent out for first time</description>
39407                  <bitRange>[21:21]</bitRange>
39408                  <access>read-only</access>
39409                </field>
39410                <field>
39411                  <name>SEQUENCE3</name>
39412                  <description>Packet Sequence Number</description>
39413                  <bitRange>[27:24]</bitRange>
39414                  <access>read-only</access>
39415                </field>
39416                <field>
39417                  <name>VALID3</name>
39418                  <description>Packet Valid. Set on receipt of buffer from Protocol Layer; cleared on receipt of LGOOD_n</description>
39419                  <bitRange>[28:28]</bitRange>
39420                  <access>read-only</access>
39421                </field>
39422                <field>
39423                  <name>SENT3</name>
39424                  <description>Packet Sent. Set on receipt of buffer from Protocol Layer; cleared when sent out for first time</description>
39425                  <bitRange>[29:29]</bitRange>
39426                  <access>read-only</access>
39427                </field>
39428              </fields>
39429            </register>
39430            <register>
39431              <name>LNK_TX_TYPE1_HEADER_BUFFER_STATE_1</name>
39432              <description>Transmit Type1 Packet Header Buffer Status 1</description>
39433              <addressOffset>0x584</addressOffset>
39434              <size>32</size>
39435              <access>read-only</access>
39436              <resetValue>0x0</resetValue>
39437              <resetMask>0xE03F3F3F</resetMask>
39438              <fields>
39439                <field>
39440                  <name>SEQUENCE4</name>
39441                  <description>Packet Sequence Number</description>
39442                  <bitRange>[3:0]</bitRange>
39443                  <access>read-only</access>
39444                </field>
39445                <field>
39446                  <name>VALID4</name>
39447                  <description>Packet Valid. Set on receipt of buffer from Protocol Layer; cleared on receipt of LGOOD_n</description>
39448                  <bitRange>[4:4]</bitRange>
39449                  <access>read-only</access>
39450                </field>
39451                <field>
39452                  <name>SENT4</name>
39453                  <description>Packet Sent. Set on receipt of buffer from Protocol Layer; cleared when sent out for first time</description>
39454                  <bitRange>[5:5]</bitRange>
39455                  <access>read-only</access>
39456                </field>
39457                <field>
39458                  <name>SEQUENCE5</name>
39459                  <description>Packet Sequence Number</description>
39460                  <bitRange>[11:8]</bitRange>
39461                  <access>read-only</access>
39462                </field>
39463                <field>
39464                  <name>VALID5</name>
39465                  <description>Packet Valid. Set on receipt of buffer from Protocol Layer; cleared on receipt of LGOOD_n</description>
39466                  <bitRange>[12:12]</bitRange>
39467                  <access>read-only</access>
39468                </field>
39469                <field>
39470                  <name>SENT5</name>
39471                  <description>Packet Sent. Set on receipt of buffer from Protocol Layer; cleared when sent out for first time</description>
39472                  <bitRange>[13:13]</bitRange>
39473                  <access>read-only</access>
39474                </field>
39475                <field>
39476                  <name>SEQUENCE6</name>
39477                  <description>Packet Sequence Number</description>
39478                  <bitRange>[19:16]</bitRange>
39479                  <access>read-only</access>
39480                </field>
39481                <field>
39482                  <name>VALID6</name>
39483                  <description>Packet Valid. Set on receipt of buffer from Protocol Layer; cleared on receipt of LGOOD_n</description>
39484                  <bitRange>[20:20]</bitRange>
39485                  <access>read-only</access>
39486                </field>
39487                <field>
39488                  <name>SENT6</name>
39489                  <description>Packet Sent. Set on receipt of buffer from Protocol Layer; cleared when sent out for first time</description>
39490                  <bitRange>[21:21]</bitRange>
39491                  <access>read-only</access>
39492                </field>
39493                <field>
39494                  <name>REMOTE_CREDITS</name>
39495                  <description>Remote Rx (Type1) Header Buffer Credit Count. The number of free entries in the Link Partner's Receive Header Packet Buffer.</description>
39496                  <bitRange>[31:29]</bitRange>
39497                  <access>read-only</access>
39498                </field>
39499              </fields>
39500            </register>
39501            <register>
39502              <dim>21</dim>
39503              <dimIncrement>4</dimIncrement>
39504              <name>LNK_TX_TYPE2_HEADER_BUFFER[%s]</name>
39505              <description>Transmit Type2 Packet Header Buffer</description>
39506              <addressOffset>0x600</addressOffset>
39507              <size>32</size>
39508              <access>read-only</access>
39509              <resetValue>0x0</resetValue>
39510              <resetMask>0xFFFFFFFF</resetMask>
39511              <fields>
39512                <field>
39513                  <name>HEADER</name>
39514                  <description>Type2 Rx Header Packet(SSP)</description>
39515                  <bitRange>[31:0]</bitRange>
39516                  <access>read-only</access>
39517                </field>
39518              </fields>
39519            </register>
39520            <register>
39521              <name>LNK_TX_TYPE2_HEADER_BUFFER_STATE_0</name>
39522              <description>Transmit Type2 Packet Header Buffer Status 0</description>
39523              <addressOffset>0x680</addressOffset>
39524              <size>32</size>
39525              <access>read-only</access>
39526              <resetValue>0x0</resetValue>
39527              <resetMask>0x3F3F3F3F</resetMask>
39528              <fields>
39529                <field>
39530                  <name>SEQUENCE0</name>
39531                  <description>Packet Sequence Number</description>
39532                  <bitRange>[3:0]</bitRange>
39533                  <access>read-only</access>
39534                </field>
39535                <field>
39536                  <name>VALID0</name>
39537                  <description>Packet Valid. Set on receipt of buffer from Protocol Layer; cleared on receipt of LGOOD_n</description>
39538                  <bitRange>[4:4]</bitRange>
39539                  <access>read-only</access>
39540                </field>
39541                <field>
39542                  <name>SENT0</name>
39543                  <description>Packet Sent. Set on receipt of buffer from Protocol Layer; cleared when sent out for first time</description>
39544                  <bitRange>[5:5]</bitRange>
39545                  <access>read-only</access>
39546                </field>
39547                <field>
39548                  <name>SEQUENCE1</name>
39549                  <description>Packet Sequence Number</description>
39550                  <bitRange>[11:8]</bitRange>
39551                  <access>read-only</access>
39552                </field>
39553                <field>
39554                  <name>VALID1</name>
39555                  <description>Packet Valid. Set on receipt of buffer from Protocol Layer; cleared on receipt of LGOOD_n</description>
39556                  <bitRange>[12:12]</bitRange>
39557                  <access>read-only</access>
39558                </field>
39559                <field>
39560                  <name>SENT1</name>
39561                  <description>Packet Sent. Set on receipt of buffer from Protocol Layer; cleared when sent out for first time</description>
39562                  <bitRange>[13:13]</bitRange>
39563                  <access>read-only</access>
39564                </field>
39565                <field>
39566                  <name>SEQUENCE2</name>
39567                  <description>Packet Sequence Number</description>
39568                  <bitRange>[19:16]</bitRange>
39569                  <access>read-only</access>
39570                </field>
39571                <field>
39572                  <name>VALID2</name>
39573                  <description>Packet Valid. Set on receipt of buffer from Protocol Layer; cleared on receipt of LGOOD_n</description>
39574                  <bitRange>[20:20]</bitRange>
39575                  <access>read-only</access>
39576                </field>
39577                <field>
39578                  <name>SENT2</name>
39579                  <description>Packet Sent. Set on receipt of buffer from Protocol Layer; cleared when sent out for first time</description>
39580                  <bitRange>[21:21]</bitRange>
39581                  <access>read-only</access>
39582                </field>
39583                <field>
39584                  <name>SEQUENCE3</name>
39585                  <description>Packet Sequence Number</description>
39586                  <bitRange>[27:24]</bitRange>
39587                  <access>read-only</access>
39588                </field>
39589                <field>
39590                  <name>VALID3</name>
39591                  <description>Packet Valid. Set on receipt of buffer from Protocol Layer; cleared on receipt of LGOOD_n</description>
39592                  <bitRange>[28:28]</bitRange>
39593                  <access>read-only</access>
39594                </field>
39595                <field>
39596                  <name>SENT3</name>
39597                  <description>Packet Sent. Set on receipt of buffer from Protocol Layer; cleared when sent out for first time</description>
39598                  <bitRange>[29:29]</bitRange>
39599                  <access>read-only</access>
39600                </field>
39601              </fields>
39602            </register>
39603            <register>
39604              <name>LNK_TX_TYPE2_HEADER_BUFFER_STATE_1</name>
39605              <description>Transmit Type2 Packet Header Buffer Status 1</description>
39606              <addressOffset>0x684</addressOffset>
39607              <size>32</size>
39608              <access>read-only</access>
39609              <resetValue>0x0</resetValue>
39610              <resetMask>0xE03F3F3F</resetMask>
39611              <fields>
39612                <field>
39613                  <name>SEQUENCE4</name>
39614                  <description>Packet Sequence Number</description>
39615                  <bitRange>[3:0]</bitRange>
39616                  <access>read-only</access>
39617                </field>
39618                <field>
39619                  <name>VALID4</name>
39620                  <description>Packet Valid. Set on receipt of buffer from Protocol Layer; cleared on receipt of LGOOD_n</description>
39621                  <bitRange>[4:4]</bitRange>
39622                  <access>read-only</access>
39623                </field>
39624                <field>
39625                  <name>SENT4</name>
39626                  <description>Packet Sent. Set on receipt of buffer from Protocol Layer; cleared when sent out for first time</description>
39627                  <bitRange>[5:5]</bitRange>
39628                  <access>read-only</access>
39629                </field>
39630                <field>
39631                  <name>SEQUENCE5</name>
39632                  <description>Packet Sequence Number</description>
39633                  <bitRange>[11:8]</bitRange>
39634                  <access>read-only</access>
39635                </field>
39636                <field>
39637                  <name>VALID5</name>
39638                  <description>Packet Valid. Set on receipt of buffer from Protocol Layer; cleared on receipt of LGOOD_n</description>
39639                  <bitRange>[12:12]</bitRange>
39640                  <access>read-only</access>
39641                </field>
39642                <field>
39643                  <name>SENT5</name>
39644                  <description>Packet Sent. Set on receipt of buffer from Protocol Layer; cleared when sent out for first time</description>
39645                  <bitRange>[13:13]</bitRange>
39646                  <access>read-only</access>
39647                </field>
39648                <field>
39649                  <name>SEQUENCE6</name>
39650                  <description>Packet Sequence Number</description>
39651                  <bitRange>[19:16]</bitRange>
39652                  <access>read-only</access>
39653                </field>
39654                <field>
39655                  <name>VALID6</name>
39656                  <description>Packet Valid. Set on receipt of buffer from Protocol Layer; cleared on receipt of LGOOD_n</description>
39657                  <bitRange>[20:20]</bitRange>
39658                  <access>read-only</access>
39659                </field>
39660                <field>
39661                  <name>SENT6</name>
39662                  <description>Packet Sent. Set on receipt of buffer from Protocol Layer; cleared when sent out for first time</description>
39663                  <bitRange>[21:21]</bitRange>
39664                  <access>read-only</access>
39665                </field>
39666                <field>
39667                  <name>REMOTE_CREDITS</name>
39668                  <description>Remote Rx Type2 Header Buffer Credit Count. The number of free entries in the Link Partner's Receive Header Packet Buffer.</description>
39669                  <bitRange>[31:29]</bitRange>
39670                  <access>read-only</access>
39671                </field>
39672              </fields>
39673            </register>
39674          </cluster>
39675          <cluster>
39676            <name>PROT</name>
39677            <description>USB32 SuperSpeedPlus Device Controller Protocol Layer Registers</description>
39678            <addressOffset>0x00003000</addressOffset>
39679            <register>
39680              <name>PROT_CS</name>
39681              <description>Protocol Control and Status</description>
39682              <addressOffset>0x0</addressOffset>
39683              <size>32</size>
39684              <access>read-write</access>
39685              <resetValue>0xC0E80000</resetValue>
39686              <resetMask>0xFFFFFFFF</resetMask>
39687              <fields>
39688                <field>
39689                  <name>DEVICEADDR</name>
39690                  <description>During the USB enumeration process, the host sends a device a unique 7-bit address, which the USB core copies into this register. The USB Core will automatically respond only to its assigned address.  During the USB RESET, this register will be cleared to zero.</description>
39691                  <bitRange>[6:0]</bitRange>
39692                  <access>read-only</access>
39693                </field>
39694                <field>
39695                  <name>DISABLE_INGRS_SEQ_MATCH</name>
39696                  <description>Disable the Ingress Sequence match detection</description>
39697                  <bitRange>[7:7]</bitRange>
39698                  <access>read-write</access>
39699                </field>
39700                <field>
39701                  <name>DISABLE_EGRS_SEQ_MATCH</name>
39702                  <description>Disable the egress Sequence match detection</description>
39703                  <bitRange>[8:8]</bitRange>
39704                  <access>read-write</access>
39705                </field>
39706                <field>
39707                  <name>SPARE</name>
39708                  <description>Spare</description>
39709                  <bitRange>[12:9]</bitRange>
39710                  <access>read-write</access>
39711                </field>
39712                <field>
39713                  <name>EN_STATUS_CONTROL</name>
39714                  <description>To control the respond to the HOST-STATUS token.</description>
39715                  <bitRange>[13:13]</bitRange>
39716                  <access>read-write</access>
39717                </field>
39718                <field>
39719                  <name>STATUS_RESPONSE</name>
39720                  <description>This is valid only for none Set_Address_Command. The Status phase of theSet_Address_Command is always ACKED.
397210: NRDY is sent for the STATUS response
39722    If EN_STATUS_CONTROL is '1' and STATUS_CLR_BUSY is '1' before STATUS phase.
397231: STALL is sent for the STATUS response
39724    If EN_STATUS_CONTROL is '1' and STATUS_CLR_BUSY is '0' before STATUS phase.</description>
39725                  <bitRange>[14:14]</bitRange>
39726                  <access>read-write</access>
39727                </field>
39728                <field>
39729                  <name>STATUS_CLR_BUSY</name>
39730                  <description>This is valid only for none Set_Address_Command.
39731This register is used only when EN_STATUS_CONTROL is set.
39732This register is used for control the status phase.
39733This gets set by HW once a valid setup token is received.
39734If this bit is not cleared before status phase, A NRDY/STALL(based on STATUS_RESPONSE) is issued when a STATUS token is received.
39735If this bit is cleared before status phase, an ACK is issued when a STATUS token is received.
39736If this bit is cleared after status phase, an ERDY is issued to the HOST to continue the STATUS phase.</description>
39737                  <bitRange>[15:15]</bitRange>
39738                  <access>read-write</access>
39739                </field>
39740                <field>
39741                  <name>SETUP_CLR_BUSY</name>
39742                  <description>Hardware set this bit to '1' once a valid Setup packet is detected.
39743The 8-byte data port of the SETUP packet is in PROT_SETUPDAT0/PROT_SETUPDAT.
39744This register bit used by Hardware to see if FW has finished processing the 8-bytes data.
39745If this regsiter is NOT cleared by FW, HW will isssue NRDY for the data-phase if any.
39746If this regsiter is          cleared by FW, HW will response like other End-point transaction</description>
39747                  <bitRange>[16:16]</bitRange>
39748                  <access>read-write</access>
39749                </field>
39750                <field>
39751                  <name>NRDY_ALL</name>
39752                  <description>Set '1' to this bit, the HW will send NRDY all transfers from the host in all endpoint1-31.</description>
39753                  <bitRange>[17:17]</bitRange>
39754                  <access>read-write</access>
39755                </field>
39756                <field>
39757                  <name>TP_THRESHOLD</name>
39758                  <description>Ingress TP response transmit buffer threshold for almost full flag.  When buffer contains TP_THRESHOLD items or more, controller will stop issuing credits to host.  This field must be larger than 0.  The transmit buffer can hold up to 64 responses.</description>
39759                  <bitRange>[23:18]</bitRange>
39760                  <access>read-write</access>
39761                </field>
39762                <field>
39763                  <name>PROT_HOST_RESET_RESP</name>
39764                  <description>This bit is used to infom the protocol of what the response to incoming TP/DPH should be after warm/host reset. This register will be used by Protocol until the LINK_INTR.LTSSM_RESET is cleared by CPU.
397650: Issue NRDY
397661: Ignore TP</description>
39767                  <bitRange>[24:24]</bitRange>
39768                  <access>read-write</access>
39769                </field>
39770                <field>
39771                  <name>SEQ_NUM_CONFIG</name>
39772                  <description>This bit indicates if the seq numbers are EP based or Stream ID(Socket) based
397730: EP based
397741: Stream ID(Socket) based</description>
39775                  <bitRange>[25:25]</bitRange>
39776                  <access>read-write</access>
39777                </field>
39778                <field>
39779                  <name>DISABLE_IDLE_DET</name>
39780                  <description>This bit will control the idle detection logic in the protocol.
397810: Logic is not disabled.
397821: Logic is disabled.</description>
39783                  <bitRange>[26:26]</bitRange>
39784                  <access>read-write</access>
39785                </field>
39786                <field>
39787                  <name>MULT_TIMER</name>
39788                  <description>This timer indicates how long protocol should wait for data (MULT is enabled) to be available by EPM before terminating a burst.
39789Protocol will multiply the value programmed by 4.</description>
39790                  <bitRange>[31:27]</bitRange>
39791                  <access>read-write</access>
39792                </field>
39793              </fields>
39794            </register>
39795            <register>
39796              <name>PROT_INTR</name>
39797              <description>Protocol Interrupts</description>
39798              <addressOffset>0x4</addressOffset>
39799              <size>32</size>
39800              <access>read-write</access>
39801              <resetValue>0x0</resetValue>
39802              <resetMask>0xFF7F</resetMask>
39803              <fields>
39804                <field>
39805                  <name>LMP_RCV_EV</name>
39806                  <description>A LMP was received and placed in PROT_LMP_PACKET_RX.  The LMP may have been recognized and processed as well (leading to other interrupts in this register).</description>
39807                  <bitRange>[0:0]</bitRange>
39808                  <access>read-write</access>
39809                </field>
39810                <field>
39811                  <name>LMP_UNKNOWN_EV</name>
39812                  <description>An unkown LMP was received and placed in PROT_LMP_PACKET_RX.  The LMP was not recognized and no response LMP was sent back.</description>
39813                  <bitRange>[1:1]</bitRange>
39814                  <access>read-write</access>
39815                </field>
39816                <field>
39817                  <name>LMP_PORT_CAP_EV</name>
39818                  <description>A Port Capabilities LMP was received.  A response may have been sent automatically depending on settings for PROT_LMP_PORT_CAPABILITIES_TIMER.</description>
39819                  <bitRange>[2:2]</bitRange>
39820                  <access>read-write</access>
39821                </field>
39822                <field>
39823                  <name>LMP_PORT_CFG_EV</name>
39824                  <description>A Port Configuration LMP was received.  A response may have been sent automatically depending on settings for PROT_LMP_PORT_CONFIGURATION_TIMER.</description>
39825                  <bitRange>[3:3]</bitRange>
39826                  <access>read-write</access>
39827                </field>
39828                <field>
39829                  <name>TIMEOUT_PORT_CAP_EV</name>
39830                  <description>The Port Capabilities LMP Timer expired</description>
39831                  <bitRange>[4:4]</bitRange>
39832                  <access>read-write</access>
39833                </field>
39834                <field>
39835                  <name>TIMEOUT_PORT_CFG_EV</name>
39836                  <description>The Port Configuraiton LMP Timer expired</description>
39837                  <bitRange>[5:5]</bitRange>
39838                  <access>read-write</access>
39839                </field>
39840                <field>
39841                  <name>TIMEOUT_PING_EV</name>
39842                  <description>The Ping Timer expired</description>
39843                  <bitRange>[6:6]</bitRange>
39844                  <access>read-write</access>
39845                </field>
39846                <field>
39847                  <name>ITP_EV</name>
39848                  <description>Set whenever a ITP(SOF) occurrs</description>
39849                  <bitRange>[8:8]</bitRange>
39850                  <access>read-write</access>
39851                </field>
39852                <field>
39853                  <name>SUTOK_EV</name>
39854                  <description>Set whenever a (valid of invalid) SETUP DPP is received that is not a set_address.  The set_address DPP is handled entirely in hardware and does not require any firmware intervention.</description>
39855                  <bitRange>[9:9]</bitRange>
39856                  <access>read-write</access>
39857                </field>
39858                <field>
39859                  <name>HOST_ERR_EV</name>
39860                  <description>Set whenever an ACK TP is received with HE=1
39861[USB 3.0:  section 8.5.1, Table 8-12, p 8-13]</description>
39862                  <bitRange>[10:10]</bitRange>
39863                  <access>read-write</access>
39864                </field>
39865                <field>
39866                  <name>STATUS_STAGE</name>
39867                  <description>Set when host completes Status Stage of a Control Transfer</description>
39868                  <bitRange>[11:11]</bitRange>
39869                  <access>read-write</access>
39870                </field>
39871                <field>
39872                  <name>LMP_INVALID_PORT_CAP_EV</name>
39873                  <description>Set whenever a LMP port capability is received but the Link Speed is not '1' or
39874Num HP buffer is not '4' or bit zero of the Direction is not '1'.</description>
39875                  <bitRange>[12:12]</bitRange>
39876                  <access>read-write</access>
39877                </field>
39878                <field>
39879                  <name>LMP_INVALID_PORT_CFG_EV</name>
39880                  <description>Set whenever a LMP port configuration is received but the Link Speed is not '1'.</description>
39881                  <bitRange>[13:13]</bitRange>
39882                  <access>read-write</access>
39883                </field>
39884                <field>
39885                  <name>EP0_STALLED_EV</name>
39886                  <description>Device sets this interrupt based on the following conditions:
398871: When Host sends more data than it is suppose to in ingress.
398882: When Device sends more data that it suppose to in egress.
398893: During STATUS Stage, host sends/asks to/for data from device.
39890Device will come out of stall condition when it receives a valid SETUP(SUTOK_EV
39891interrupt will be generated).</description>
39892                  <bitRange>[14:14]</bitRange>
39893                  <access>read-write</access>
39894                </field>
39895                <field>
39896                  <name>SET_ADDR0_EV</name>
39897                  <description>Device sets this interrupt when it receives a set address 0 command.</description>
39898                  <bitRange>[15:15]</bitRange>
39899                  <access>read-write</access>
39900                </field>
39901              </fields>
39902            </register>
39903            <register>
39904              <name>PROT_INTR_SET</name>
39905              <description>Protocol Interrupts Set</description>
39906              <addressOffset>0x8</addressOffset>
39907              <size>32</size>
39908              <access>read-write</access>
39909              <resetValue>0x0</resetValue>
39910              <resetMask>0xFF7F</resetMask>
39911              <fields>
39912                <field>
39913                  <name>LMP_RCV_EV</name>
39914                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
39915                  <bitRange>[0:0]</bitRange>
39916                  <access>read-write</access>
39917                </field>
39918                <field>
39919                  <name>LMP_UNKNOWN_EV</name>
39920                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
39921                  <bitRange>[1:1]</bitRange>
39922                  <access>read-write</access>
39923                </field>
39924                <field>
39925                  <name>LMP_PORT_CAP_EV</name>
39926                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
39927                  <bitRange>[2:2]</bitRange>
39928                  <access>read-write</access>
39929                </field>
39930                <field>
39931                  <name>LMP_PORT_CFG_EV</name>
39932                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
39933                  <bitRange>[3:3]</bitRange>
39934                  <access>read-write</access>
39935                </field>
39936                <field>
39937                  <name>TIMEOUT_PORT_CAP_EV</name>
39938                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
39939                  <bitRange>[4:4]</bitRange>
39940                  <access>read-write</access>
39941                </field>
39942                <field>
39943                  <name>TIMEOUT_PORT_CFG_EV</name>
39944                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
39945                  <bitRange>[5:5]</bitRange>
39946                  <access>read-write</access>
39947                </field>
39948                <field>
39949                  <name>TIMEOUT_PING_EV</name>
39950                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
39951                  <bitRange>[6:6]</bitRange>
39952                  <access>read-write</access>
39953                </field>
39954                <field>
39955                  <name>ITP_EV</name>
39956                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
39957                  <bitRange>[8:8]</bitRange>
39958                  <access>read-write</access>
39959                </field>
39960                <field>
39961                  <name>SUTOK_EV</name>
39962                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
39963                  <bitRange>[9:9]</bitRange>
39964                  <access>read-write</access>
39965                </field>
39966                <field>
39967                  <name>HOST_ERR_EV</name>
39968                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
39969                  <bitRange>[10:10]</bitRange>
39970                  <access>read-write</access>
39971                </field>
39972                <field>
39973                  <name>STATUS_STAGE</name>
39974                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
39975                  <bitRange>[11:11]</bitRange>
39976                  <access>read-write</access>
39977                </field>
39978                <field>
39979                  <name>LMP_INVALID_PORT_CAP_EV</name>
39980                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
39981                  <bitRange>[12:12]</bitRange>
39982                  <access>read-write</access>
39983                </field>
39984                <field>
39985                  <name>LMP_INVALID_PORT_CFG_EV</name>
39986                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
39987                  <bitRange>[13:13]</bitRange>
39988                  <access>read-write</access>
39989                </field>
39990                <field>
39991                  <name>EP0_STALLED_EV</name>
39992                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
39993                  <bitRange>[14:14]</bitRange>
39994                  <access>read-write</access>
39995                </field>
39996                <field>
39997                  <name>SET_ADDR0_EV</name>
39998                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
39999                  <bitRange>[15:15]</bitRange>
40000                  <access>read-write</access>
40001                </field>
40002              </fields>
40003            </register>
40004            <register>
40005              <name>PROT_INTR_MASK</name>
40006              <description>Protocol Interrupts Mask</description>
40007              <addressOffset>0xC</addressOffset>
40008              <size>32</size>
40009              <access>read-write</access>
40010              <resetValue>0x0</resetValue>
40011              <resetMask>0xFF7F</resetMask>
40012              <fields>
40013                <field>
40014                  <name>LMP_RCV_MASK</name>
40015                  <description>Mask bit for corresponding bit in interrupt request register.</description>
40016                  <bitRange>[0:0]</bitRange>
40017                  <access>read-write</access>
40018                </field>
40019                <field>
40020                  <name>LMP_UNKNOWN_MASK</name>
40021                  <description>Mask bit for corresponding bit in interrupt request register.</description>
40022                  <bitRange>[1:1]</bitRange>
40023                  <access>read-write</access>
40024                </field>
40025                <field>
40026                  <name>LMP_PORT_CAP_MASK</name>
40027                  <description>Mask bit for corresponding bit in interrupt request register.</description>
40028                  <bitRange>[2:2]</bitRange>
40029                  <access>read-write</access>
40030                </field>
40031                <field>
40032                  <name>LMP_PORT_CFG_MASK</name>
40033                  <description>Mask bit for corresponding bit in interrupt request register.</description>
40034                  <bitRange>[3:3]</bitRange>
40035                  <access>read-write</access>
40036                </field>
40037                <field>
40038                  <name>TIMEOUT_PORT_CAP_MASK</name>
40039                  <description>Mask bit for corresponding bit in interrupt request register.</description>
40040                  <bitRange>[4:4]</bitRange>
40041                  <access>read-write</access>
40042                </field>
40043                <field>
40044                  <name>TIMEOUT_PORT_CFG_MASK</name>
40045                  <description>Mask bit for corresponding bit in interrupt request register.</description>
40046                  <bitRange>[5:5]</bitRange>
40047                  <access>read-write</access>
40048                </field>
40049                <field>
40050                  <name>TIMEOUT_PING_MASK</name>
40051                  <description>Mask bit for corresponding bit in interrupt request register.</description>
40052                  <bitRange>[6:6]</bitRange>
40053                  <access>read-write</access>
40054                </field>
40055                <field>
40056                  <name>ITP_MASK</name>
40057                  <description>Mask bit for corresponding bit in interrupt request register.</description>
40058                  <bitRange>[8:8]</bitRange>
40059                  <access>read-write</access>
40060                </field>
40061                <field>
40062                  <name>SUTOK_MASK</name>
40063                  <description>Mask bit for corresponding bit in interrupt request register.</description>
40064                  <bitRange>[9:9]</bitRange>
40065                  <access>read-write</access>
40066                </field>
40067                <field>
40068                  <name>HOST_ERR_MASK</name>
40069                  <description>Mask bit for corresponding bit in interrupt request register.</description>
40070                  <bitRange>[10:10]</bitRange>
40071                  <access>read-write</access>
40072                </field>
40073                <field>
40074                  <name>STATUS_STAGE_MASK</name>
40075                  <description>Mask bit for corresponding bit in interrupt request register.</description>
40076                  <bitRange>[11:11]</bitRange>
40077                  <access>read-write</access>
40078                </field>
40079                <field>
40080                  <name>LMP_INVALID_PORT_CAP_MASK</name>
40081                  <description>Mask bit for corresponding bit in interrupt request register.</description>
40082                  <bitRange>[12:12]</bitRange>
40083                  <access>read-write</access>
40084                </field>
40085                <field>
40086                  <name>LMP_INVALID_PORT_CFG_MASK</name>
40087                  <description>Mask bit for corresponding bit in interrupt request register.</description>
40088                  <bitRange>[13:13]</bitRange>
40089                  <access>read-write</access>
40090                </field>
40091                <field>
40092                  <name>EP0_STALLED_MASK</name>
40093                  <description>Mask bit for corresponding bit in interrupt request register.</description>
40094                  <bitRange>[14:14]</bitRange>
40095                  <access>read-write</access>
40096                </field>
40097                <field>
40098                  <name>SET_ADDR0_MASK</name>
40099                  <description>Mask bit for corresponding bit in interrupt request register.</description>
40100                  <bitRange>[15:15]</bitRange>
40101                  <access>read-write</access>
40102                </field>
40103              </fields>
40104            </register>
40105            <register>
40106              <name>PROT_INTR_MASKED</name>
40107              <description>Protocol Interrupts Masked</description>
40108              <addressOffset>0x10</addressOffset>
40109              <size>32</size>
40110              <access>read-only</access>
40111              <resetValue>0x0</resetValue>
40112              <resetMask>0xFF7F</resetMask>
40113              <fields>
40114                <field>
40115                  <name>LMP_RCV_MASKED</name>
40116                  <description>Logical and of corresponding request and mask bits.</description>
40117                  <bitRange>[0:0]</bitRange>
40118                  <access>read-only</access>
40119                </field>
40120                <field>
40121                  <name>LMP_UNKNOWN_MASKED</name>
40122                  <description>Logical and of corresponding request and mask bits.</description>
40123                  <bitRange>[1:1]</bitRange>
40124                  <access>read-only</access>
40125                </field>
40126                <field>
40127                  <name>LMP_PORT_CAP_MASKED</name>
40128                  <description>Logical and of corresponding request and mask bits.</description>
40129                  <bitRange>[2:2]</bitRange>
40130                  <access>read-only</access>
40131                </field>
40132                <field>
40133                  <name>LMP_PORT_CFG_MASKED</name>
40134                  <description>Logical and of corresponding request and mask bits.</description>
40135                  <bitRange>[3:3]</bitRange>
40136                  <access>read-only</access>
40137                </field>
40138                <field>
40139                  <name>TIMEOUT_PORT_CAP_MASKED</name>
40140                  <description>Logical and of corresponding request and mask bits.</description>
40141                  <bitRange>[4:4]</bitRange>
40142                  <access>read-only</access>
40143                </field>
40144                <field>
40145                  <name>TIMEOUT_PORT_CFG_MASKED</name>
40146                  <description>Logical and of corresponding request and mask bits.</description>
40147                  <bitRange>[5:5]</bitRange>
40148                  <access>read-only</access>
40149                </field>
40150                <field>
40151                  <name>TIMEOUT_PING_MASKED</name>
40152                  <description>Logical and of corresponding request and mask bits.</description>
40153                  <bitRange>[6:6]</bitRange>
40154                  <access>read-only</access>
40155                </field>
40156                <field>
40157                  <name>ITP_MASKED</name>
40158                  <description>Logical and of corresponding request and mask bits.</description>
40159                  <bitRange>[8:8]</bitRange>
40160                  <access>read-only</access>
40161                </field>
40162                <field>
40163                  <name>SUTOK_MASKED</name>
40164                  <description>Logical and of corresponding request and mask bits.</description>
40165                  <bitRange>[9:9]</bitRange>
40166                  <access>read-only</access>
40167                </field>
40168                <field>
40169                  <name>HOST_ERR_MASKED</name>
40170                  <description>Logical and of corresponding request and mask bits.</description>
40171                  <bitRange>[10:10]</bitRange>
40172                  <access>read-only</access>
40173                </field>
40174                <field>
40175                  <name>STATUS_STAGE_MASKED</name>
40176                  <description>Logical and of corresponding request and mask bits.</description>
40177                  <bitRange>[11:11]</bitRange>
40178                  <access>read-only</access>
40179                </field>
40180                <field>
40181                  <name>LMP_INVALID_PORT_CAP_MASKED</name>
40182                  <description>Logical and of corresponding request and mask bits.</description>
40183                  <bitRange>[12:12]</bitRange>
40184                  <access>read-only</access>
40185                </field>
40186                <field>
40187                  <name>LMP_INVALID_PORT_CFG_MASKED</name>
40188                  <description>Logical and of corresponding request and mask bits.</description>
40189                  <bitRange>[13:13]</bitRange>
40190                  <access>read-only</access>
40191                </field>
40192                <field>
40193                  <name>EP0_STALLED_MASKED</name>
40194                  <description>Logical and of corresponding request and mask bits.</description>
40195                  <bitRange>[14:14]</bitRange>
40196                  <access>read-only</access>
40197                </field>
40198                <field>
40199                  <name>SET_ADDR0_MASKED</name>
40200                  <description>Logical and of corresponding request and mask bits.</description>
40201                  <bitRange>[15:15]</bitRange>
40202                  <access>read-only</access>
40203                </field>
40204              </fields>
40205            </register>
40206            <register>
40207              <name>PROT_EP_INTR</name>
40208              <description>Endpoint Interrupts</description>
40209              <addressOffset>0x14</addressOffset>
40210              <size>32</size>
40211              <access>read-write</access>
40212              <resetValue>0x0</resetValue>
40213              <resetMask>0xFFFFFFFF</resetMask>
40214              <fields>
40215                <field>
40216                  <name>EP_IN</name>
40217                  <description>Bit &lt;x&gt; indicates an interrupt from EPI_CS[x]</description>
40218                  <bitRange>[15:0]</bitRange>
40219                  <access>read-write</access>
40220                </field>
40221                <field>
40222                  <name>EP_OUT</name>
40223                  <description>Bit &lt;16+x&gt; indicates an interrupt from EPO_CS[x]</description>
40224                  <bitRange>[31:16]</bitRange>
40225                  <access>read-write</access>
40226                </field>
40227              </fields>
40228            </register>
40229            <register>
40230              <name>PROT_EP_INTR_SET</name>
40231              <description>Endpoint Interrupts set</description>
40232              <addressOffset>0x18</addressOffset>
40233              <size>32</size>
40234              <access>read-write</access>
40235              <resetValue>0x0</resetValue>
40236              <resetMask>0xFFFFFFFF</resetMask>
40237              <fields>
40238                <field>
40239                  <name>EP_IN</name>
40240                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
40241                  <bitRange>[15:0]</bitRange>
40242                  <access>read-write</access>
40243                </field>
40244                <field>
40245                  <name>EP_OUT</name>
40246                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
40247                  <bitRange>[31:16]</bitRange>
40248                  <access>read-write</access>
40249                </field>
40250              </fields>
40251            </register>
40252            <register>
40253              <name>PROT_EP_INTR_MASK</name>
40254              <description>Endpoint Interrupts Mask</description>
40255              <addressOffset>0x1C</addressOffset>
40256              <size>32</size>
40257              <access>read-write</access>
40258              <resetValue>0x0</resetValue>
40259              <resetMask>0xFFFFFFFF</resetMask>
40260              <fields>
40261                <field>
40262                  <name>EP_IN_MASK</name>
40263                  <description>Bit &lt;x&gt; masks any interrupt from EPI_CS[x]</description>
40264                  <bitRange>[15:0]</bitRange>
40265                  <access>read-write</access>
40266                </field>
40267                <field>
40268                  <name>EP_OUT_MASK</name>
40269                  <description>Bit &lt;16+x&gt; masks any interrupt from EPO_CS[x]</description>
40270                  <bitRange>[31:16]</bitRange>
40271                  <access>read-write</access>
40272                </field>
40273              </fields>
40274            </register>
40275            <register>
40276              <name>PROT_EP_INTR_MASKED</name>
40277              <description>Endpoint Interrupts Masked</description>
40278              <addressOffset>0x20</addressOffset>
40279              <size>32</size>
40280              <access>read-only</access>
40281              <resetValue>0x0</resetValue>
40282              <resetMask>0xFFFFFFFF</resetMask>
40283              <fields>
40284                <field>
40285                  <name>EP_IN_MASKED</name>
40286                  <description>Logical and of corresponding request and mask bits.</description>
40287                  <bitRange>[15:0]</bitRange>
40288                  <access>read-only</access>
40289                </field>
40290                <field>
40291                  <name>EP_OUT_MASKED</name>
40292                  <description>Logical and of corresponding request and mask bits.</description>
40293                  <bitRange>[31:16]</bitRange>
40294                  <access>read-only</access>
40295                </field>
40296              </fields>
40297            </register>
40298            <register>
40299              <name>PROT_DEVICE_NOTIF_FUNC_WAKE</name>
40300              <description>Device Notification Remote Wake up TP</description>
40301              <addressOffset>0x24</addressOffset>
40302              <size>32</size>
40303              <access>read-write</access>
40304              <resetValue>0x0</resetValue>
40305              <resetMask>0x800000FF</resetMask>
40306              <fields>
40307                <field>
40308                  <name>INTERFACE</name>
40309                  <description>Interface.  This  field  identifies  the  first  interface  in  the  function  that  caused  the device  to  perform  a  remote  wake  operation.</description>
40310                  <bitRange>[7:0]</bitRange>
40311                  <access>read-write</access>
40312                </field>
40313                <field>
40314                  <name>REQUEST</name>
40315                  <description>Firmware writes 1 to enable it and hardware clears this bit after device notification TP service request has been completed</description>
40316                  <bitRange>[31:31]</bitRange>
40317                  <access>read-write</access>
40318                </field>
40319              </fields>
40320            </register>
40321            <register>
40322              <name>PROT_DEVICE_NOTIF_LTM</name>
40323              <description>Device Notification Latency Tolerance Message TP</description>
40324              <addressOffset>0x28</addressOffset>
40325              <size>32</size>
40326              <access>read-write</access>
40327              <resetValue>0xC00</resetValue>
40328              <resetMask>0x80000FFF</resetMask>
40329              <fields>
40330                <field>
40331                  <name>BELT_LATENCY</name>
40332                  <description>BELT.  This  field  describes  the  Best  Effort  Latency  Tolerance  value, representing  the  time  in nanoseconds  that  a  device  can  wait  for  service  before  experiencing  unintended  operational  side effects.
40333[9:0]: LatencyValue in nano-seconds (ns)</description>
40334                  <bitRange>[9:0]</bitRange>
40335                  <access>read-write</access>
40336                </field>
40337                <field>
40338                  <name>BELT_SCALE</name>
40339                  <description>N/A</description>
40340                  <bitRange>[11:10]</bitRange>
40341                  <access>read-write</access>
40342                </field>
40343                <field>
40344                  <name>REQUEST</name>
40345                  <description>Firmware writes 1 to enable it and hardware clears this bit after servicing the request</description>
40346                  <bitRange>[31:31]</bitRange>
40347                  <access>read-write</access>
40348                </field>
40349              </fields>
40350            </register>
40351            <register>
40352              <name>PROT_DEVICE_NOTIF_BIAM</name>
40353              <description>Device Notification Bus Interval Adjustment TP</description>
40354              <addressOffset>0x2C</addressOffset>
40355              <size>32</size>
40356              <access>read-write</access>
40357              <resetValue>0x0</resetValue>
40358              <resetMask>0x8000FFFF</resetMask>
40359              <fields>
40360                <field>
40361                  <name>BIA</name>
40362                  <description>Bus  Interval  Adjustment.  This  field  is  a  two's  complement  value  ranging  from  -32768  to  +32767 expressed  in  BusIntervalAdjustmentGranularity units.</description>
40363                  <bitRange>[15:0]</bitRange>
40364                  <access>read-write</access>
40365                </field>
40366                <field>
40367                  <name>REQUEST</name>
40368                  <description>Firmware writes 1 to enable it and hardware clears this bit after servicing the request</description>
40369                  <bitRange>[31:31]</bitRange>
40370                  <access>read-write</access>
40371                </field>
40372              </fields>
40373            </register>
40374            <register>
40375              <name>PROT_LMP_PORT_CAPABILITY_TIMER</name>
40376              <description>Port Capabilites LMP Timeout Configuration</description>
40377              <addressOffset>0x30</addressOffset>
40378              <size>32</size>
40379              <access>read-write</access>
40380              <resetValue>0x9C4</resetValue>
40381              <resetMask>0xFFFFFFFF</resetMask>
40382              <fields>
40383                <field>
40384                  <name>RX_TIMEOUT</name>
40385                  <description>Maximum  time  after  a  successful  warm  reset  or  a power  on  reset  that  the  device should wait for port  capability LMP on its RX link. Default is 20us (2500 cycles using 125 mhz clock)</description>
40386                  <bitRange>[14:0]</bitRange>
40387                  <access>read-write</access>
40388                </field>
40389                <field>
40390                  <name>RX_DISABLE</name>
40391                  <description>Disables the protocol layer to wait for port capabilities LMP</description>
40392                  <bitRange>[15:15]</bitRange>
40393                  <access>read-write</access>
40394                </field>
40395                <field>
40396                  <name>TX_TIMEOUT</name>
40397                  <description>This for TX lane, device should send port capability within 20us of link initialization done. Firmware can load a timer and ask device to wait for that much time before sending port Capability LMP</description>
40398                  <bitRange>[30:16]</bitRange>
40399                  <access>read-write</access>
40400                </field>
40401                <field>
40402                  <name>TX_DISABLE</name>
40403                  <description>Disables the protocol layer to send port capabilities LMP</description>
40404                  <bitRange>[31:31]</bitRange>
40405                  <access>read-write</access>
40406                </field>
40407              </fields>
40408            </register>
40409            <register>
40410              <name>PROT_LMP_PORT_CONFIGURATION_TIMER</name>
40411              <description>Port Configuration LMP Timeout Configuration</description>
40412              <addressOffset>0x34</addressOffset>
40413              <size>32</size>
40414              <access>read-write</access>
40415              <resetValue>0x9C4</resetValue>
40416              <resetMask>0xFFFFFFFF</resetMask>
40417              <fields>
40418                <field>
40419                  <name>RX_TIMEOUT</name>
40420                  <description>Maximum  time  after  a  successful  warm  reset  or  a power  on  reset  that  the  link  partners  should  send  the  port  configuration LMP.  Default is 20us (2500 cycles using 125 mhz clock)</description>
40421                  <bitRange>[14:0]</bitRange>
40422                  <access>read-write</access>
40423                </field>
40424                <field>
40425                  <name>RX_DISABLE</name>
40426                  <description>Disables the protocol layer to wait for port configuration LMP</description>
40427                  <bitRange>[15:15]</bitRange>
40428                  <access>read-write</access>
40429                </field>
40430                <field>
40431                  <name>TX_TIMEOUT</name>
40432                  <description>Maximum time device protocol layer will wait after receiving Port Configuration LMP.</description>
40433                  <bitRange>[30:16]</bitRange>
40434                  <access>read-write</access>
40435                </field>
40436                <field>
40437                  <name>TX_DISABLE</name>
40438                  <description>Disables the protocol layer to send Port configuration response LMP</description>
40439                  <bitRange>[31:31]</bitRange>
40440                  <access>read-write</access>
40441                </field>
40442              </fields>
40443            </register>
40444            <register>
40445              <name>PROT_PING_TIMEOUT</name>
40446              <description>Ping Timeout Configuration</description>
40447              <addressOffset>0x38</addressOffset>
40448              <size>32</size>
40449              <access>read-write</access>
40450              <resetValue>0x7A12</resetValue>
40451              <resetMask>0x80FFFFFF</resetMask>
40452              <fields>
40453                <field>
40454                  <name>PING_TIMEOUT</name>
40455                  <description>Timeout  after  a  device  receives  a  ping  from  the host  and  when  it  can  initiate  U1  or  U2.   This parameter  is  measured  in  terms  of  the  maximum
40456of  all  the  service  intervals  for  all  isochronous endpoints  within  the  device. Default is 2 service intervals (1 service interval = 1 bus interval in this case)
40457Default we are taking 250 us = 31250 clock cycles of 125Mhz)</description>
40458                  <bitRange>[23:0]</bitRange>
40459                  <access>read-write</access>
40460                </field>
40461                <field>
40462                  <name>PING_DISABLE</name>
40463                  <description>Directs the protocol layer to disable ping timer</description>
40464                  <bitRange>[31:31]</bitRange>
40465                  <access>read-write</access>
40466                </field>
40467              </fields>
40468            </register>
40469            <register>
40470              <name>PROT_FRAMECNT</name>
40471              <description>Frame Counter Register</description>
40472              <addressOffset>0x44</addressOffset>
40473              <size>32</size>
40474              <access>read-only</access>
40475              <resetValue>0x0</resetValue>
40476              <resetMask>0x7FFFFFF</resetMask>
40477              <fields>
40478                <field>
40479                  <name>SS_MICROFRAME</name>
40480                  <description>MICROFRAME counter which indicates which of the 8 125-microsecond micro-frames last occurred... This is based on ITPs recieved from Host</description>
40481                  <bitRange>[13:0]</bitRange>
40482                  <access>read-only</access>
40483                </field>
40484                <field>
40485                  <name>DELTA</name>
40486                  <description>The delta value in the last ITP received</description>
40487                  <bitRange>[26:14]</bitRange>
40488                  <access>read-only</access>
40489                </field>
40490              </fields>
40491            </register>
40492            <register>
40493              <name>PROT_BIAC</name>
40494              <description>Bus Interval Adjustment Addres</description>
40495              <addressOffset>0x48</addressOffset>
40496              <size>32</size>
40497              <access>read-only</access>
40498              <resetValue>0x0</resetValue>
40499              <resetMask>0x7F</resetMask>
40500              <fields>
40501                <field>
40502                  <name>BIAC</name>
40503                  <description>Bus Interval Adjustment control: This  field  specifies  the  address  of  the  device  that  controls  the bus  interval  adjustment  mechanism.   Upon  reset,  power-up,  or  if  the  device  is  disconnected,  the host  shall  set  this  field  to  zero.</description>
40504                  <bitRange>[6:0]</bitRange>
40505                  <access>read-only</access>
40506                </field>
40507              </fields>
40508            </register>
40509            <register>
40510              <name>PROT_ITP_TIME</name>
40511              <description>ITP Time Free Running Counter</description>
40512              <addressOffset>0x4C</addressOffset>
40513              <size>32</size>
40514              <access>read-only</access>
40515              <resetValue>0x0</resetValue>
40516              <resetMask>0xFFFFFF</resetMask>
40517              <fields>
40518                <field>
40519                  <name>COUNTER24</name>
40520                  <description>Current counter value.</description>
40521                  <bitRange>[23:0]</bitRange>
40522                  <access>read-only</access>
40523                </field>
40524              </fields>
40525            </register>
40526            <register>
40527              <name>PROT_ITP_TIMESTAMP</name>
40528              <description>ITP Time Stamp Register</description>
40529              <addressOffset>0x50</addressOffset>
40530              <size>32</size>
40531              <access>read-only</access>
40532              <resetValue>0x0</resetValue>
40533              <resetMask>0xFFFFFFFF</resetMask>
40534              <fields>
40535                <field>
40536                  <name>TIMESTAMP</name>
40537                  <description>Timestamp from a free running counter at 125MHz of the last ITP reception.</description>
40538                  <bitRange>[23:0]</bitRange>
40539                  <access>read-only</access>
40540                </field>
40541                <field>
40542                  <name>MICROFRAME_LSB</name>
40543                  <description>LSBs of MICROFRAME field of ITP when timestamp was taken.</description>
40544                  <bitRange>[31:24]</bitRange>
40545                  <access>read-only</access>
40546                </field>
40547              </fields>
40548            </register>
40549            <register>
40550              <name>PROT_SETUPDAT0</name>
40551              <description>Received SETUP Packet Data</description>
40552              <addressOffset>0x54</addressOffset>
40553              <size>32</size>
40554              <access>read-only</access>
40555              <resetValue>0x0</resetValue>
40556              <resetMask>0xFFFFFFFF</resetMask>
40557              <fields>
40558                <field>
40559                  <name>SETUP_REQUEST_TYPE</name>
40560                  <description>Setup data field</description>
40561                  <bitRange>[7:0]</bitRange>
40562                  <access>read-only</access>
40563                </field>
40564                <field>
40565                  <name>SETUP_REQUEST</name>
40566                  <description>Setup data field</description>
40567                  <bitRange>[15:8]</bitRange>
40568                  <access>read-only</access>
40569                </field>
40570                <field>
40571                  <name>SETUP_VALUE</name>
40572                  <description>Setup data field</description>
40573                  <bitRange>[31:16]</bitRange>
40574                  <access>read-only</access>
40575                </field>
40576              </fields>
40577            </register>
40578            <register>
40579              <name>PROT_SETUPDAT1</name>
40580              <description>Received SETUP Packet Data</description>
40581              <addressOffset>0x58</addressOffset>
40582              <size>32</size>
40583              <access>read-only</access>
40584              <resetValue>0x0</resetValue>
40585              <resetMask>0xFFFFFFFF</resetMask>
40586              <fields>
40587                <field>
40588                  <name>SETUP_INDEX</name>
40589                  <description>Setup data field</description>
40590                  <bitRange>[15:0]</bitRange>
40591                  <access>read-only</access>
40592                </field>
40593                <field>
40594                  <name>SETUP_LENGTH</name>
40595                  <description>Setup data field</description>
40596                  <bitRange>[31:16]</bitRange>
40597                  <access>read-only</access>
40598                </field>
40599              </fields>
40600            </register>
40601            <register>
40602              <name>PROT_SEQ_NUM</name>
40603              <description>Sequence Number</description>
40604              <addressOffset>0x5C</addressOffset>
40605              <size>32</size>
40606              <access>read-write</access>
40607              <resetValue>0x80000000</resetValue>
40608              <resetMask>0xC01F1F1F</resetMask>
40609              <fields>
40610                <field>
40611                  <name>ENDPOINT</name>
40612                  <description>Endpoint Number</description>
40613                  <bitRange>[3:0]</bitRange>
40614                  <access>read-write</access>
40615                </field>
40616                <field>
40617                  <name>DIR</name>
40618                  <description>0: OUT
406191: IN</description>
40620                  <bitRange>[4:4]</bitRange>
40621                  <access>read-write</access>
40622                </field>
40623                <field>
40624                  <name>SEQUENCE_NUMBER</name>
40625                  <description>Packet sequence number of next packet to receive/transmit.  Set by hardware if COMMAND=0, set by software when COMMAND=1.</description>
40626                  <bitRange>[12:8]</bitRange>
40627                  <access>read-write</access>
40628                </field>
40629                <field>
40630                  <name>LAST_COMMITTED</name>
40631                  <description>Sequence number of last packet that was transmitted (can be higher than SEQUENCE NUMBER).  Returned as part of a read operation.</description>
40632                  <bitRange>[20:16]</bitRange>
40633                  <access>read-only</access>
40634                </field>
40635                <field>
40636                  <name>COMMAND</name>
40637                  <description>0: Read
406381: Write</description>
40639                  <bitRange>[30:30]</bitRange>
40640                  <access>read-write</access>
40641                </field>
40642                <field>
40643                  <name>SEQ_VALID</name>
40644                  <description>Set by hardware when read/write operation has completed.  Must be cleared by software to initiate a read/write operation.</description>
40645                  <bitRange>[31:31]</bitRange>
40646                  <access>read-write</access>
40647                </field>
40648              </fields>
40649            </register>
40650            <register>
40651              <name>PROT_LMP_RECEIVED</name>
40652              <description>Link Management Packet Received Value</description>
40653              <addressOffset>0x80</addressOffset>
40654              <size>32</size>
40655              <access>read-only</access>
40656              <resetValue>0x0</resetValue>
40657              <resetMask>0x1FF</resetMask>
40658              <fields>
40659                <field>
40660                  <name>U2_INACTIVITY_TIMEOUT</name>
40661                  <description>U2 Inactivity Timeout Value</description>
40662                  <bitRange>[7:0]</bitRange>
40663                  <access>read-only</access>
40664                </field>
40665                <field>
40666                  <name>FORCE_LINKPM_ACCEPT</name>
40667                  <description>Force Link to accept LGO_Ux Link Commands</description>
40668                  <bitRange>[8:8]</bitRange>
40669                  <access>read-only</access>
40670                </field>
40671              </fields>
40672            </register>
40673            <register>
40674              <name>PROT_LMP_OVERRIDE</name>
40675              <description>Link Management Packet Override Values</description>
40676              <addressOffset>0x84</addressOffset>
40677              <size>32</size>
40678              <access>read-write</access>
40679              <resetValue>0x0</resetValue>
40680              <resetMask>0xE00001FF</resetMask>
40681              <fields>
40682                <field>
40683                  <name>U2_INACTIVITY_TIMEOUT</name>
40684                  <description>U2 Inactivity Timeout Value</description>
40685                  <bitRange>[7:0]</bitRange>
40686                  <access>read-write</access>
40687                </field>
40688                <field>
40689                  <name>FORCE_LINKPM_ACCEPT</name>
40690                  <description>Force Link to accept LGO_Ux Link Commands</description>
40691                  <bitRange>[8:8]</bitRange>
40692                  <access>read-write</access>
40693                </field>
40694                <field>
40695                  <name>INACITIVITY_TIMEOUT_OVR</name>
40696                  <description>Enable U2 Inactivity Timeout Setting Override</description>
40697                  <bitRange>[29:29]</bitRange>
40698                  <access>read-write</access>
40699                </field>
40700                <field>
40701                  <name>LINKPM_ACCEPT_OVR</name>
40702                  <description>Enable Force_LINKPM_Accept Setting Override</description>
40703                  <bitRange>[30:30]</bitRange>
40704                  <access>read-write</access>
40705                </field>
40706                <field>
40707                  <name>LMP_SEND</name>
40708                  <description>Initiates sending of the Port Configuration Response LMP</description>
40709                  <bitRange>[31:31]</bitRange>
40710                  <access>read-write</access>
40711                </field>
40712              </fields>
40713            </register>
40714            <register>
40715              <name>PROT_LMP_PORT_CAPABILITIES_RX</name>
40716              <description>Port Capabilities LMP Received</description>
40717              <addressOffset>0x88</addressOffset>
40718              <size>32</size>
40719              <access>read-only</access>
40720              <resetValue>0x0</resetValue>
40721              <resetMask>0x1FFFFF</resetMask>
40722              <fields>
40723                <field>
40724                  <name>LINK_SPEED</name>
40725                  <description>The Link Speed supported by device</description>
40726                  <bitRange>[6:0]</bitRange>
40727                  <access>read-only</access>
40728                </field>
40729                <field>
40730                  <name>NUM_HP_BUFFERS</name>
40731                  <description>This field specifies the number of header  packet  buffers
40732(in each direction Transmit or Receive)  this  device  supports.</description>
40733                  <bitRange>[14:7]</bitRange>
40734                  <access>read-only</access>
40735                </field>
40736                <field>
40737                  <name>DIRECTION</name>
40738                  <description>This field is used to identify the upstream or downstream capabilities of the port</description>
40739                  <bitRange>[16:15]</bitRange>
40740                  <access>read-only</access>
40741                </field>
40742                <field>
40743                  <name>TIEBREAKER</name>
40744                  <description>This  field  is  used  to  determine  the  port  type  when  two  devices  with  both  upstream  and  downstream capability are connected to each other</description>
40745                  <bitRange>[20:17]</bitRange>
40746                  <access>read-only</access>
40747                </field>
40748              </fields>
40749            </register>
40750            <register>
40751              <name>PROT_LMP_PORT_CAPABILITIES_TX</name>
40752              <description>Port Capabilities LMP Transmitted</description>
40753              <addressOffset>0x8C</addressOffset>
40754              <size>32</size>
40755              <access>read-write</access>
40756              <resetValue>0x10201</resetValue>
40757              <resetMask>0x801FFFFF</resetMask>
40758              <fields>
40759                <field>
40760                  <name>LINK_SPEED</name>
40761                  <description>Only used for Gen1x1. HW will use this only for Gen1x1 for others HW send a value '0'.
40762The Link Speed supported by device</description>
40763                  <bitRange>[6:0]</bitRange>
40764                  <access>read-write</access>
40765                </field>
40766                <field>
40767                  <name>NUM_HP_BUFFERS</name>
40768                  <description>Only used for Gen1x1. HW will use this only for Gen1x1 for others HW send a value '0'.
40769This field specifies the number of header  packet  buffers
40770(in each direction Transmit or Receive)  this  device  supports.</description>
40771                  <bitRange>[14:7]</bitRange>
40772                  <access>read-write</access>
40773                </field>
40774                <field>
40775                  <name>DIRECTION</name>
40776                  <description>This field is used to identify the upstream or downstream capabilities of the port</description>
40777                  <bitRange>[16:15]</bitRange>
40778                  <access>read-write</access>
40779                </field>
40780                <field>
40781                  <name>TIEBREAKER</name>
40782                  <description>This  field  is  used  to  determine  the  port  type  when  two  devices  with  both  upstream  and  downstream capability are connected to each other</description>
40783                  <bitRange>[20:17]</bitRange>
40784                  <access>read-write</access>
40785                </field>
40786                <field>
40787                  <name>LMP_SEND</name>
40788                  <description>Initiates sending of the Port Configuration Response LMP</description>
40789                  <bitRange>[31:31]</bitRange>
40790                  <access>read-write</access>
40791                </field>
40792              </fields>
40793            </register>
40794            <register>
40795              <name>PROT_LMP_PORT_CONFIGURATION_RX</name>
40796              <description>Port Configuration LMP Received</description>
40797              <addressOffset>0x90</addressOffset>
40798              <size>32</size>
40799              <access>read-only</access>
40800              <resetValue>0x0</resetValue>
40801              <resetMask>0x7F</resetMask>
40802              <fields>
40803                <field>
40804                  <name>LINK_SPEED</name>
40805                  <description>This  field  describes  the  link  speed  at  which  the  upstream  port  shall  operate.</description>
40806                  <bitRange>[6:0]</bitRange>
40807                  <access>read-only</access>
40808                </field>
40809              </fields>
40810            </register>
40811            <register>
40812              <name>PROT_LMP_PORT_CONFIGURATION_TX</name>
40813              <description>Port Configuration Response LMP</description>
40814              <addressOffset>0x94</addressOffset>
40815              <size>32</size>
40816              <access>read-write</access>
40817              <resetValue>0x1</resetValue>
40818              <resetMask>0x8000007F</resetMask>
40819              <fields>
40820                <field>
40821                  <name>LINK_SPEED</name>
40822                  <description>This  field  indicates  the  settings  that  were  accepted  in  the  Port  Configuration LMP  that  was  sent  to  a  device.</description>
40823                  <bitRange>[6:0]</bitRange>
40824                  <access>read-write</access>
40825                </field>
40826                <field>
40827                  <name>LMP_SEND</name>
40828                  <description>Initiates sending of the Port Configuration Response LMP</description>
40829                  <bitRange>[31:31]</bitRange>
40830                  <access>read-write</access>
40831                </field>
40832              </fields>
40833            </register>
40834            <register>
40835              <name>PROT_STREAM_ERROR_DISABLE</name>
40836              <description>Streams Error Disable Type Registers</description>
40837              <addressOffset>0x98</addressOffset>
40838              <size>32</size>
40839              <access>read-write</access>
40840              <resetValue>0x0</resetValue>
40841              <resetMask>0x3F</resetMask>
40842              <fields>
40843                <field>
40844                  <name>TYPE</name>
40845                  <description>This register controls the type of Stream Error that would cause the ERROR_DETECTED bit in the PROT_STREAM_ERROR_STATUS register to bet set.
40846Setting any bit will disable an specific error type.
40847[0]: Stream ID changed while in MOVE DATA stage.
40848[1]:  ACK/DP PRIMEP PP is '1'
40849[2]: ACK/DP NoStream PP is '1'
40850[3]: ACK PRIME NumP is '0'
40851[4]: ACK NoStream NumP is NOT '0'</description>
40852                  <bitRange>[5:0]</bitRange>
40853                  <access>read-write</access>
40854                </field>
40855              </fields>
40856            </register>
40857            <register>
40858              <name>PROT_STREAM_ERROR_STATUS</name>
40859              <description>Streams Error STATUS Registers</description>
40860              <addressOffset>0x9C</addressOffset>
40861              <size>32</size>
40862              <access>read-write</access>
40863              <resetValue>0x0</resetValue>
40864              <resetMask>0xBFFFFFFF</resetMask>
40865              <fields>
40866                <field>
40867                  <name>ID</name>
40868                  <description>The stream id when the error occurred.</description>
40869                  <bitRange>[15:0]</bitRange>
40870                  <access>read-only</access>
40871                </field>
40872                <field>
40873                  <name>EP_NUM</name>
40874                  <description>The End Point number when the error occurred.</description>
40875                  <bitRange>[19:16]</bitRange>
40876                  <access>read-only</access>
40877                </field>
40878                <field>
40879                  <name>EP_IO</name>
40880                  <description>1: IN EP, 0: OUT EP</description>
40881                  <bitRange>[20:20]</bitRange>
40882                  <access>read-only</access>
40883                </field>
40884                <field>
40885                  <name>ERROR_TYPE</name>
40886                  <description>The type of the stream error that was detected.
40887[1]: Stream ID changed while in MOVE DATA stage.
40888[2]:  ACK/DP PRIMEP PP is '1'
40889[3]: ACK/DP NoStream PP is '1'
40890[4]: ACK PRIME NumP is '0'
40891[5]: ACK NoStream NumP is NOT '0'</description>
40892                  <bitRange>[26:21]</bitRange>
40893                  <access>read-only</access>
40894                </field>
40895                <field>
40896                  <name>ERROR_STATE</name>
40897                  <description>The stream state when the error occurred.
408981: Disabled
408992: Prime Pipe
409003: DFR Prime Pipe
409014: Idle
409025: Start Stream
409036: Move Data
409047: End</description>
40905                  <bitRange>[29:27]</bitRange>
40906                  <access>read-only</access>
40907                </field>
40908                <field>
40909                  <name>ERROR_DETECTED</name>
40910                  <description>An Stream Error was detected.</description>
40911                  <bitRange>[31:31]</bitRange>
40912                  <access>read-write</access>
40913                </field>
40914              </fields>
40915            </register>
40916            <register>
40917              <dim>3</dim>
40918              <dimIncrement>4</dimIncrement>
40919              <name>PROT_LMP_PACKET_RX[%s]</name>
40920              <description>Link Management Packet Received</description>
40921              <addressOffset>0x100</addressOffset>
40922              <size>32</size>
40923              <access>read-only</access>
40924              <resetValue>0x0</resetValue>
40925              <resetMask>0xFFFFFFFF</resetMask>
40926              <fields>
40927                <field>
40928                  <name>RX_LMP_PACKET</name>
40929                  <description>Link Management Packet</description>
40930                  <bitRange>[31:0]</bitRange>
40931                  <access>read-only</access>
40932                </field>
40933              </fields>
40934            </register>
40935            <register>
40936              <dim>3</dim>
40937              <dimIncrement>4</dimIncrement>
40938              <name>PROT_LMP_PACKET_TX[%s]</name>
40939              <description>Link Management Packet to be sent</description>
40940              <addressOffset>0x110</addressOffset>
40941              <size>32</size>
40942              <access>read-write</access>
40943              <resetValue>0x0</resetValue>
40944              <resetMask>0xFFFFFFFF</resetMask>
40945              <fields>
40946                <field>
40947                  <name>TX_LMP_PACKET</name>
40948                  <description>Link Management Packet</description>
40949                  <bitRange>[31:0]</bitRange>
40950                  <access>read-write</access>
40951                </field>
40952              </fields>
40953            </register>
40954            <register>
40955              <dim>16</dim>
40956              <dimIncrement>4</dimIncrement>
40957              <name>PROT_EPI_INTR[%s]</name>
40958              <description>Per IN-Endpoint Interrupt</description>
40959              <addressOffset>0x140</addressOffset>
40960              <size>32</size>
40961              <access>read-write</access>
40962              <resetValue>0x0</resetValue>
40963              <resetMask>0x7FF</resetMask>
40964              <fields>
40965                <field>
40966                  <name>COMMIT</name>
40967                  <description>Set whenever an IN token was ACKed by the host.</description>
40968                  <bitRange>[0:0]</bitRange>
40969                  <access>read-write</access>
40970                </field>
40971                <field>
40972                  <name>RETRY</name>
40973                  <description>Whenever the USB3.0 does a retry it will asserts this interrupt.</description>
40974                  <bitRange>[1:1]</bitRange>
40975                  <access>read-write</access>
40976                </field>
40977                <field>
40978                  <name>FLOWCONTROL</name>
40979                  <description>EP in flow control due to EPM not being available.</description>
40980                  <bitRange>[2:2]</bitRange>
40981                  <access>read-write</access>
40982                </field>
40983                <field>
40984                  <name>STREAMNRDY</name>
40985                  <description>Nrdy was sent for a bulk stream request because of EP-stream not present in the mapper.</description>
40986                  <bitRange>[3:3]</bitRange>
40987                  <access>read-write</access>
40988                </field>
40989                <field>
40990                  <name>ZERO</name>
40991                  <description>Indicates a zero length packet was returned to the host in an IN transaction.  Must be cleared by s/w.</description>
40992                  <bitRange>[4:4]</bitRange>
40993                  <access>read-write</access>
40994                </field>
40995                <field>
40996                  <name>SHORT</name>
40997                  <description>Indicates a shorter-than-maxsize packet was received, but UIB_EPI_XFER_CNT did not reach 0).</description>
40998                  <bitRange>[5:5]</bitRange>
40999                  <access>read-write</access>
41000                </field>
41001                <field>
41002                  <name>OOSERR</name>
41003                  <description>Out Of Sequence Error. Anytime an ACK is received with unexpected sequence number request, the ACK will be dropped and intr will be raised</description>
41004                  <bitRange>[6:6]</bitRange>
41005                  <access>read-write</access>
41006                </field>
41007                <field>
41008                  <name>HBTERM</name>
41009                  <description>The Burst Was terminated by the host.</description>
41010                  <bitRange>[7:7]</bitRange>
41011                  <access>read-write</access>
41012                </field>
41013                <field>
41014                  <name>DBTERM</name>
41015                  <description>The Burst was terminated by the device when the MULT_TIMER expires.</description>
41016                  <bitRange>[8:8]</bitRange>
41017                  <access>read-write</access>
41018                </field>
41019                <field>
41020                  <name>STREAM_ERROR</name>
41021                  <description>Stream Error occurred.</description>
41022                  <bitRange>[9:9]</bitRange>
41023                  <access>read-write</access>
41024                </field>
41025                <field>
41026                  <name>FIRST_ACK_NUMP_0</name>
41027                  <description>The NumP for the first ACK is zero.</description>
41028                  <bitRange>[10:10]</bitRange>
41029                  <access>read-write</access>
41030                </field>
41031              </fields>
41032            </register>
41033            <register>
41034              <dim>16</dim>
41035              <dimIncrement>4</dimIncrement>
41036              <name>PROT_EPI_INTR_SET[%s]</name>
41037              <description>Per IN-Endpoint Interrupt set</description>
41038              <addressOffset>0x180</addressOffset>
41039              <size>32</size>
41040              <access>read-write</access>
41041              <resetValue>0x0</resetValue>
41042              <resetMask>0x7FF</resetMask>
41043              <fields>
41044                <field>
41045                  <name>COMMIT</name>
41046                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
41047                  <bitRange>[0:0]</bitRange>
41048                  <access>read-write</access>
41049                </field>
41050                <field>
41051                  <name>RETRY</name>
41052                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
41053                  <bitRange>[1:1]</bitRange>
41054                  <access>read-write</access>
41055                </field>
41056                <field>
41057                  <name>FLOWCONTROL</name>
41058                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
41059                  <bitRange>[2:2]</bitRange>
41060                  <access>read-write</access>
41061                </field>
41062                <field>
41063                  <name>STREAMNRDY</name>
41064                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
41065                  <bitRange>[3:3]</bitRange>
41066                  <access>read-write</access>
41067                </field>
41068                <field>
41069                  <name>ZERO</name>
41070                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
41071                  <bitRange>[4:4]</bitRange>
41072                  <access>read-write</access>
41073                </field>
41074                <field>
41075                  <name>SHORT</name>
41076                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
41077                  <bitRange>[5:5]</bitRange>
41078                  <access>read-write</access>
41079                </field>
41080                <field>
41081                  <name>OOSERR</name>
41082                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
41083                  <bitRange>[6:6]</bitRange>
41084                  <access>read-write</access>
41085                </field>
41086                <field>
41087                  <name>HBTERM</name>
41088                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
41089                  <bitRange>[7:7]</bitRange>
41090                  <access>read-write</access>
41091                </field>
41092                <field>
41093                  <name>DBTERM</name>
41094                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
41095                  <bitRange>[8:8]</bitRange>
41096                  <access>read-write</access>
41097                </field>
41098                <field>
41099                  <name>STREAM_ERROR</name>
41100                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
41101                  <bitRange>[9:9]</bitRange>
41102                  <access>read-write</access>
41103                </field>
41104                <field>
41105                  <name>FIRST_ACK_NUMP_0</name>
41106                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
41107                  <bitRange>[10:10]</bitRange>
41108                  <access>read-write</access>
41109                </field>
41110              </fields>
41111            </register>
41112            <register>
41113              <dim>16</dim>
41114              <dimIncrement>4</dimIncrement>
41115              <name>PROT_EPI_INTR_MASK[%s]</name>
41116              <description>Per IN-Endpoint Interrupt Mask</description>
41117              <addressOffset>0x1C0</addressOffset>
41118              <size>32</size>
41119              <access>read-write</access>
41120              <resetValue>0x0</resetValue>
41121              <resetMask>0x7FF</resetMask>
41122              <fields>
41123                <field>
41124                  <name>COMMIT_MASK</name>
41125                  <description>Mask bit for corresponding bit in interrupt request register.</description>
41126                  <bitRange>[0:0]</bitRange>
41127                  <access>read-write</access>
41128                </field>
41129                <field>
41130                  <name>RETRY_MASK</name>
41131                  <description>Mask bit for corresponding bit in interrupt request register.</description>
41132                  <bitRange>[1:1]</bitRange>
41133                  <access>read-write</access>
41134                </field>
41135                <field>
41136                  <name>FLOWCONTROL_MASK</name>
41137                  <description>Mask bit for corresponding bit in interrupt request register.</description>
41138                  <bitRange>[2:2]</bitRange>
41139                  <access>read-write</access>
41140                </field>
41141                <field>
41142                  <name>STREAMNRDY_MASK</name>
41143                  <description>Mask bit for corresponding bit in interrupt request register.</description>
41144                  <bitRange>[3:3]</bitRange>
41145                  <access>read-write</access>
41146                </field>
41147                <field>
41148                  <name>ZERO_MASK</name>
41149                  <description>Mask bit for corresponding bit in interrupt request register.</description>
41150                  <bitRange>[4:4]</bitRange>
41151                  <access>read-write</access>
41152                </field>
41153                <field>
41154                  <name>SHORT_MASK</name>
41155                  <description>Mask bit for corresponding bit in interrupt request register.</description>
41156                  <bitRange>[5:5]</bitRange>
41157                  <access>read-write</access>
41158                </field>
41159                <field>
41160                  <name>OOSERR_MASK</name>
41161                  <description>Mask bit for corresponding bit in interrupt request register.</description>
41162                  <bitRange>[6:6]</bitRange>
41163                  <access>read-write</access>
41164                </field>
41165                <field>
41166                  <name>HBTERM_MASK</name>
41167                  <description>Mask bit for corresponding bit in interrupt request register.</description>
41168                  <bitRange>[7:7]</bitRange>
41169                  <access>read-write</access>
41170                </field>
41171                <field>
41172                  <name>DBTERM_MASK</name>
41173                  <description>Mask bit for corresponding bit in interrupt request register.</description>
41174                  <bitRange>[8:8]</bitRange>
41175                  <access>read-write</access>
41176                </field>
41177                <field>
41178                  <name>STREAM_ERROR_MASK</name>
41179                  <description>Mask bit for corresponding bit in interrupt request register.</description>
41180                  <bitRange>[9:9]</bitRange>
41181                  <access>read-write</access>
41182                </field>
41183                <field>
41184                  <name>FIRST_ACK_NUMP_0_MASK</name>
41185                  <description>Mask bit for corresponding bit in interrupt request register.</description>
41186                  <bitRange>[10:10]</bitRange>
41187                  <access>read-write</access>
41188                </field>
41189              </fields>
41190            </register>
41191            <register>
41192              <dim>16</dim>
41193              <dimIncrement>4</dimIncrement>
41194              <name>PROT_EPI_INTR_MASKED[%s]</name>
41195              <description>Per IN-Endpoint Interrupt Masked</description>
41196              <addressOffset>0x200</addressOffset>
41197              <size>32</size>
41198              <access>read-only</access>
41199              <resetValue>0x0</resetValue>
41200              <resetMask>0x7FF</resetMask>
41201              <fields>
41202                <field>
41203                  <name>COMMIT_MASKED</name>
41204                  <description>Logical and of corresponding request and mask bits.</description>
41205                  <bitRange>[0:0]</bitRange>
41206                  <access>read-only</access>
41207                </field>
41208                <field>
41209                  <name>RETRY_MASKED</name>
41210                  <description>Logical and of corresponding request and mask bits.</description>
41211                  <bitRange>[1:1]</bitRange>
41212                  <access>read-only</access>
41213                </field>
41214                <field>
41215                  <name>FLOWCONTROL_MASKED</name>
41216                  <description>Logical and of corresponding request and mask bits.</description>
41217                  <bitRange>[2:2]</bitRange>
41218                  <access>read-only</access>
41219                </field>
41220                <field>
41221                  <name>STREAMNRDY_MASKED</name>
41222                  <description>Logical and of corresponding request and mask bits.</description>
41223                  <bitRange>[3:3]</bitRange>
41224                  <access>read-only</access>
41225                </field>
41226                <field>
41227                  <name>ZERO_MASKED</name>
41228                  <description>Logical and of corresponding request and mask bits.</description>
41229                  <bitRange>[4:4]</bitRange>
41230                  <access>read-only</access>
41231                </field>
41232                <field>
41233                  <name>SHORT_MASKED</name>
41234                  <description>Logical and of corresponding request and mask bits.</description>
41235                  <bitRange>[5:5]</bitRange>
41236                  <access>read-only</access>
41237                </field>
41238                <field>
41239                  <name>OOSERR_MASKED</name>
41240                  <description>Logical and of corresponding request and mask bits.</description>
41241                  <bitRange>[6:6]</bitRange>
41242                  <access>read-only</access>
41243                </field>
41244                <field>
41245                  <name>HBTERM_MASKED</name>
41246                  <description>Logical and of corresponding request and mask bits.</description>
41247                  <bitRange>[7:7]</bitRange>
41248                  <access>read-only</access>
41249                </field>
41250                <field>
41251                  <name>DBTERM_MASKED</name>
41252                  <description>Logical and of corresponding request and mask bits.</description>
41253                  <bitRange>[8:8]</bitRange>
41254                  <access>read-only</access>
41255                </field>
41256                <field>
41257                  <name>STREAM_ERROR_MASKED</name>
41258                  <description>Logical and of corresponding request and mask bits.</description>
41259                  <bitRange>[9:9]</bitRange>
41260                  <access>read-only</access>
41261                </field>
41262                <field>
41263                  <name>FIRST_ACK_NUMP_0_MASKED</name>
41264                  <description>Logical and of corresponding request and mask bits.</description>
41265                  <bitRange>[10:10]</bitRange>
41266                  <access>read-only</access>
41267                </field>
41268              </fields>
41269            </register>
41270            <register>
41271              <dim>16</dim>
41272              <dimIncrement>4</dimIncrement>
41273              <name>PROT_EPI_CS1[%s]</name>
41274              <description>SuperSpeed IN Endpoint Control and Status</description>
41275              <addressOffset>0x240</addressOffset>
41276              <size>32</size>
41277              <access>read-write</access>
41278              <resetValue>0x20</resetValue>
41279              <resetMask>0x8000003F</resetMask>
41280              <fields>
41281                <field>
41282                  <name>VALID</name>
41283                  <description>Set VALID=1 to activate an endpoint, and VALID=0 to de-activate it. All USB endpoints default to invalid. An endpoint whose VALID bit is 0 does not respond to any USB traffic.</description>
41284                  <bitRange>[0:0]</bitRange>
41285                  <access>read-write</access>
41286                </field>
41287                <field>
41288                  <name>NRDY</name>
41289                  <description>Setting this bit causes NRDY on IN transactions.</description>
41290                  <bitRange>[1:1]</bitRange>
41291                  <access>read-write</access>
41292                </field>
41293                <field>
41294                  <name>STALL</name>
41295                  <description>Set this bit to '1' to stall an endpoint, and to '0' to clear a stall.</description>
41296                  <bitRange>[2:2]</bitRange>
41297                  <access>read-write</access>
41298                </field>
41299                <field>
41300                  <name>STREAM_EN</name>
41301                  <description>Enables bulk stream protocol handling for this EP</description>
41302                  <bitRange>[3:3]</bitRange>
41303                  <access>read-write</access>
41304                </field>
41305                <field>
41306                  <name>EP_RESET</name>
41307                  <description>Per End Point Reset.</description>
41308                  <bitRange>[4:4]</bitRange>
41309                  <access>read-write</access>
41310                </field>
41311                <field>
41312                  <name>STREAM_ERROR_STALL_EN</name>
41313                  <description>Issue STALL whenever Stream error occurs.</description>
41314                  <bitRange>[5:5]</bitRange>
41315                  <access>read-write</access>
41316                </field>
41317                <field>
41318                  <name>DISABLE_EOB_ON_SHORT</name>
41319                  <description>0: EOB is '1' for short packet
413201: EOB is '0' for short packet</description>
41321                  <bitRange>[31:31]</bitRange>
41322                  <access>read-write</access>
41323                </field>
41324              </fields>
41325            </register>
41326            <register>
41327              <dim>16</dim>
41328              <dimIncrement>4</dimIncrement>
41329              <name>PROT_EPI_CS2[%s]</name>
41330              <description>SuperSpeed IN Endpoint Control and Status</description>
41331              <addressOffset>0x280</addressOffset>
41332              <size>32</size>
41333              <access>read-write</access>
41334              <resetValue>0x40</resetValue>
41335              <resetMask>0x1FFFF</resetMask>
41336              <fields>
41337                <field>
41338                  <name>EPI_TYPE</name>
41339                  <description>Endpoint type (EP0 suports CONTROL only)
413400: ISO
413411: INT
413422: BULK
413433: CONTROL (only valid for EP0)</description>
41344                  <bitRange>[1:0]</bitRange>
41345                  <access>read-write</access>
41346                </field>
41347                <field>
41348                  <name>ISOINPKS</name>
41349                  <description>Number of packets to be sent per service interval .  Maximum can be 48 ( Max burst size* Mult field)</description>
41350                  <bitRange>[7:2]</bitRange>
41351                  <access>read-write</access>
41352                </field>
41353                <field>
41354                  <name>MAXBURST</name>
41355                  <description>Maximum number of packets the endpoint can send.
41356(truncated to 4b, 0 means 16)</description>
41357                  <bitRange>[11:8]</bitRange>
41358                  <access>read-write</access>
41359                </field>
41360                <field>
41361                  <name>BTERM_NUMP</name>
41362                  <description>Number of packets that need to be cleaned up by CPU whenever there is a BTERM interrupt.</description>
41363                  <bitRange>[16:12]</bitRange>
41364                  <access>read-only</access>
41365                </field>
41366              </fields>
41367            </register>
41368            <register>
41369              <dim>16</dim>
41370              <dimIncrement>4</dimIncrement>
41371              <name>PROT_EPI_UNMAPPED_STREAM[%s]</name>
41372              <description>Unmapped Stream Request</description>
41373              <addressOffset>0x2C0</addressOffset>
41374              <size>32</size>
41375              <access>read-only</access>
41376              <resetValue>0x0</resetValue>
41377              <resetMask>0xFFFFF</resetMask>
41378              <fields>
41379                <field>
41380                  <name>STREAM_ID</name>
41381                  <description>The StreamID of the current stream activated (or requested to be activated) by the protocol layer.</description>
41382                  <bitRange>[15:0]</bitRange>
41383                  <access>read-only</access>
41384                </field>
41385                <field>
41386                  <name>SPSM_STATE</name>
41387                  <description>Stream Protocol State Machine (SPSM) State for this EndPoint:
41388
413890: Not Configured
413901: Disabled
413912: Prime Pipe
413923: DFR Prime Pipe
413934: Idle
413945: Start Stream
413956: Move Data
413967: End
413978: Error</description>
41398                  <bitRange>[19:16]</bitRange>
41399                  <access>read-only</access>
41400                </field>
41401              </fields>
41402            </register>
41403            <register>
41404              <dim>16</dim>
41405              <dimIncrement>4</dimIncrement>
41406              <name>PROT_EPI_MAPPED_STREAM[%s]</name>
41407              <description>Mapped Streams Registers</description>
41408              <addressOffset>0x300</addressOffset>
41409              <size>32</size>
41410              <access>read-write</access>
41411              <resetValue>0x0</resetValue>
41412              <resetMask>0xE00FFFFF</resetMask>
41413              <fields>
41414                <field>
41415                  <name>STREAM_ID</name>
41416                  <description>The StreamID of the stream connected to the corresponding socket by firmware.</description>
41417                  <bitRange>[15:0]</bitRange>
41418                  <access>read-write</access>
41419                </field>
41420                <field>
41421                  <name>EP_NUMBER</name>
41422                  <description>The Endpoint number of the stream connected to the corresponding socket by firmware.</description>
41423                  <bitRange>[19:16]</bitRange>
41424                  <access>read-write</access>
41425                </field>
41426                <field>
41427                  <name>UNMAPPED</name>
41428                  <description>Stream is unmapped (not in use by the corresponding EP's SPSM).</description>
41429                  <bitRange>[29:29]</bitRange>
41430                  <access>read-only</access>
41431                </field>
41432                <field>
41433                  <name>UNMAP</name>
41434                  <description>Request to unmap this stream.  May be cleared to revert/withdaw request.</description>
41435                  <bitRange>[30:30]</bitRange>
41436                  <access>read-write</access>
41437                </field>
41438                <field>
41439                  <name>ENABLE</name>
41440                  <description>Set by firmware if a stream is mapped to the corresponding socket. If this bit is set, the endpoint number corresponding to this socket number can no longer be used in non-streaming mode (that would create a conflict of two endpoints wanting to use the same socket).</description>
41441                  <bitRange>[31:31]</bitRange>
41442                  <access>read-write</access>
41443                </field>
41444              </fields>
41445            </register>
41446            <register>
41447              <dim>16</dim>
41448              <dimIncrement>4</dimIncrement>
41449              <name>PROT_EPO_INTR[%s]</name>
41450              <description>Per OUT-Endpoint Interrupt</description>
41451              <addressOffset>0x340</addressOffset>
41452              <size>32</size>
41453              <access>read-write</access>
41454              <resetValue>0x0</resetValue>
41455              <resetMask>0x7FF</resetMask>
41456              <fields>
41457                <field>
41458                  <name>COMMIT</name>
41459                  <description>Set whenever an OUT DATA was commited into the EPM.</description>
41460                  <bitRange>[0:0]</bitRange>
41461                  <access>read-write</access>
41462                </field>
41463                <field>
41464                  <name>RETRY</name>
41465                  <description>Whenever the USB3.0 device does a retry it will asserts this interrupt.</description>
41466                  <bitRange>[1:1]</bitRange>
41467                  <access>read-write</access>
41468                </field>
41469                <field>
41470                  <name>FLOWCONTROL</name>
41471                  <description>EP in flow control due to EPM not being available.</description>
41472                  <bitRange>[2:2]</bitRange>
41473                  <access>read-write</access>
41474                </field>
41475                <field>
41476                  <name>STREAMNRDY</name>
41477                  <description>Nrdy was sent for a bulk stream request because of EP-stream not present in the mapper.</description>
41478                  <bitRange>[3:3]</bitRange>
41479                  <access>read-write</access>
41480                </field>
41481                <field>
41482                  <name>ZERO</name>
41483                  <description>Indicates a zero length packet was received by the device in an OUT transaction.  Must be cleared by s/w.</description>
41484                  <bitRange>[4:4]</bitRange>
41485                  <access>read-write</access>
41486                </field>
41487                <field>
41488                  <name>SHORT</name>
41489                  <description>Indicates a shorter-than-maxsize packet was received.</description>
41490                  <bitRange>[5:5]</bitRange>
41491                  <access>read-write</access>
41492                </field>
41493                <field>
41494                  <name>OOSERR</name>
41495                  <description>Out Of Sequence Error. Anytime an OUT-DATA is received with unexpected sequence number request, the data will be dropped and intr will be raised</description>
41496                  <bitRange>[6:6]</bitRange>
41497                  <access>read-write</access>
41498                </field>
41499                <field>
41500                  <name>HBTERM</name>
41501                  <description>The Burst Was terminated by the host.</description>
41502                  <bitRange>[7:7]</bitRange>
41503                  <access>read-write</access>
41504                </field>
41505                <field>
41506                  <name>DBTERM</name>
41507                  <description>The Burst was terminated by the device when the MULT_TIMER expires.</description>
41508                  <bitRange>[8:8]</bitRange>
41509                  <access>read-write</access>
41510                </field>
41511                <field>
41512                  <name>STREAM_ERROR</name>
41513                  <description>Stream Error occurred.</description>
41514                  <bitRange>[9:9]</bitRange>
41515                  <access>read-write</access>
41516                </field>
41517                <field>
41518                  <name>FIRST_ACK_NUMP_0</name>
41519                  <description>The NumP for the first ACK is zero.</description>
41520                  <bitRange>[10:10]</bitRange>
41521                  <access>read-write</access>
41522                </field>
41523              </fields>
41524            </register>
41525            <register>
41526              <dim>16</dim>
41527              <dimIncrement>4</dimIncrement>
41528              <name>PROT_EPO_INTR_SET[%s]</name>
41529              <description>Per OUT-Endpoint Interrupt set</description>
41530              <addressOffset>0x380</addressOffset>
41531              <size>32</size>
41532              <access>read-write</access>
41533              <resetValue>0x0</resetValue>
41534              <resetMask>0x7FF</resetMask>
41535              <fields>
41536                <field>
41537                  <name>COMMIT</name>
41538                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
41539                  <bitRange>[0:0]</bitRange>
41540                  <access>read-write</access>
41541                </field>
41542                <field>
41543                  <name>RETRY</name>
41544                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
41545                  <bitRange>[1:1]</bitRange>
41546                  <access>read-write</access>
41547                </field>
41548                <field>
41549                  <name>FLOWCONTROL</name>
41550                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
41551                  <bitRange>[2:2]</bitRange>
41552                  <access>read-write</access>
41553                </field>
41554                <field>
41555                  <name>STREAMNRDY</name>
41556                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
41557                  <bitRange>[3:3]</bitRange>
41558                  <access>read-write</access>
41559                </field>
41560                <field>
41561                  <name>ZERO</name>
41562                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
41563                  <bitRange>[4:4]</bitRange>
41564                  <access>read-write</access>
41565                </field>
41566                <field>
41567                  <name>SHORT</name>
41568                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
41569                  <bitRange>[5:5]</bitRange>
41570                  <access>read-write</access>
41571                </field>
41572                <field>
41573                  <name>OOSERR</name>
41574                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
41575                  <bitRange>[6:6]</bitRange>
41576                  <access>read-write</access>
41577                </field>
41578                <field>
41579                  <name>HBTERM</name>
41580                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
41581                  <bitRange>[7:7]</bitRange>
41582                  <access>read-write</access>
41583                </field>
41584                <field>
41585                  <name>DBTERM</name>
41586                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
41587                  <bitRange>[8:8]</bitRange>
41588                  <access>read-write</access>
41589                </field>
41590                <field>
41591                  <name>STREAM_ERROR</name>
41592                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
41593                  <bitRange>[9:9]</bitRange>
41594                  <access>read-write</access>
41595                </field>
41596                <field>
41597                  <name>FIRST_ACK_NUMP_0</name>
41598                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
41599                  <bitRange>[10:10]</bitRange>
41600                  <access>read-write</access>
41601                </field>
41602              </fields>
41603            </register>
41604            <register>
41605              <dim>16</dim>
41606              <dimIncrement>4</dimIncrement>
41607              <name>PROT_EPO_INTR_MASK[%s]</name>
41608              <description>Per OUT-Endpoint Interrupt Mask</description>
41609              <addressOffset>0x3C0</addressOffset>
41610              <size>32</size>
41611              <access>read-write</access>
41612              <resetValue>0x0</resetValue>
41613              <resetMask>0x7FF</resetMask>
41614              <fields>
41615                <field>
41616                  <name>COMMIT_MASK</name>
41617                  <description>Mask bit for corresponding bit in interrupt request register.</description>
41618                  <bitRange>[0:0]</bitRange>
41619                  <access>read-write</access>
41620                </field>
41621                <field>
41622                  <name>RETRY_MASK</name>
41623                  <description>Mask bit for corresponding bit in interrupt request register.</description>
41624                  <bitRange>[1:1]</bitRange>
41625                  <access>read-write</access>
41626                </field>
41627                <field>
41628                  <name>FLOWCONTROL_MASK</name>
41629                  <description>Mask bit for corresponding bit in interrupt request register.</description>
41630                  <bitRange>[2:2]</bitRange>
41631                  <access>read-write</access>
41632                </field>
41633                <field>
41634                  <name>STREAMNRDY_MASK</name>
41635                  <description>Mask bit for corresponding bit in interrupt request register.</description>
41636                  <bitRange>[3:3]</bitRange>
41637                  <access>read-write</access>
41638                </field>
41639                <field>
41640                  <name>ZERO_MASK</name>
41641                  <description>Mask bit for corresponding bit in interrupt request register.</description>
41642                  <bitRange>[4:4]</bitRange>
41643                  <access>read-write</access>
41644                </field>
41645                <field>
41646                  <name>SHORT_MASK</name>
41647                  <description>Mask bit for corresponding bit in interrupt request register.</description>
41648                  <bitRange>[5:5]</bitRange>
41649                  <access>read-write</access>
41650                </field>
41651                <field>
41652                  <name>OOSERR_MASK</name>
41653                  <description>Mask bit for corresponding bit in interrupt request register.</description>
41654                  <bitRange>[6:6]</bitRange>
41655                  <access>read-write</access>
41656                </field>
41657                <field>
41658                  <name>HBTERM_MASK</name>
41659                  <description>Mask bit for corresponding bit in interrupt request register.</description>
41660                  <bitRange>[7:7]</bitRange>
41661                  <access>read-write</access>
41662                </field>
41663                <field>
41664                  <name>DBTERM_MASK</name>
41665                  <description>Mask bit for corresponding bit in interrupt request register.</description>
41666                  <bitRange>[8:8]</bitRange>
41667                  <access>read-write</access>
41668                </field>
41669                <field>
41670                  <name>STREAM_ERROR_MASK</name>
41671                  <description>Mask bit for corresponding bit in interrupt request register.</description>
41672                  <bitRange>[9:9]</bitRange>
41673                  <access>read-write</access>
41674                </field>
41675                <field>
41676                  <name>FIRST_ACK_NUMP_0_MASK</name>
41677                  <description>Mask bit for corresponding bit in interrupt request register.</description>
41678                  <bitRange>[10:10]</bitRange>
41679                  <access>read-write</access>
41680                </field>
41681              </fields>
41682            </register>
41683            <register>
41684              <dim>16</dim>
41685              <dimIncrement>4</dimIncrement>
41686              <name>PROT_EPO_INTR_MASKED[%s]</name>
41687              <description>Per OUT-Endpoint Interrupt Masked</description>
41688              <addressOffset>0x400</addressOffset>
41689              <size>32</size>
41690              <access>read-only</access>
41691              <resetValue>0x0</resetValue>
41692              <resetMask>0x7FF</resetMask>
41693              <fields>
41694                <field>
41695                  <name>COMMIT_MASKED</name>
41696                  <description>Mask bit for corresponding bit in interrupt request register.</description>
41697                  <bitRange>[0:0]</bitRange>
41698                  <access>read-only</access>
41699                </field>
41700                <field>
41701                  <name>RETRY_MASKED</name>
41702                  <description>Mask bit for corresponding bit in interrupt request register.</description>
41703                  <bitRange>[1:1]</bitRange>
41704                  <access>read-only</access>
41705                </field>
41706                <field>
41707                  <name>FLOWCONTROL_MASKED</name>
41708                  <description>Mask bit for corresponding bit in interrupt request register.</description>
41709                  <bitRange>[2:2]</bitRange>
41710                  <access>read-only</access>
41711                </field>
41712                <field>
41713                  <name>STREAMNRDY_MASKED</name>
41714                  <description>Mask bit for corresponding bit in interrupt request register.</description>
41715                  <bitRange>[3:3]</bitRange>
41716                  <access>read-only</access>
41717                </field>
41718                <field>
41719                  <name>ZERO_MASKED</name>
41720                  <description>Mask bit for corresponding bit in interrupt request register.</description>
41721                  <bitRange>[4:4]</bitRange>
41722                  <access>read-only</access>
41723                </field>
41724                <field>
41725                  <name>SHORT_MASKED</name>
41726                  <description>Mask bit for corresponding bit in interrupt request register.</description>
41727                  <bitRange>[5:5]</bitRange>
41728                  <access>read-only</access>
41729                </field>
41730                <field>
41731                  <name>OOSERR_MASKED</name>
41732                  <description>Mask bit for corresponding bit in interrupt request register.</description>
41733                  <bitRange>[6:6]</bitRange>
41734                  <access>read-only</access>
41735                </field>
41736                <field>
41737                  <name>HBTERM_MASKED</name>
41738                  <description>Mask bit for corresponding bit in interrupt request register.</description>
41739                  <bitRange>[7:7]</bitRange>
41740                  <access>read-only</access>
41741                </field>
41742                <field>
41743                  <name>DBTERM_MASKED</name>
41744                  <description>Mask bit for corresponding bit in interrupt request register.</description>
41745                  <bitRange>[8:8]</bitRange>
41746                  <access>read-only</access>
41747                </field>
41748                <field>
41749                  <name>STREAM_ERROR_MASKED</name>
41750                  <description>Mask bit for corresponding bit in interrupt request register.</description>
41751                  <bitRange>[9:9]</bitRange>
41752                  <access>read-only</access>
41753                </field>
41754                <field>
41755                  <name>FIRST_ACK_NUMP_0_MASKED</name>
41756                  <description>Mask bit for corresponding bit in interrupt request register.</description>
41757                  <bitRange>[10:10]</bitRange>
41758                  <access>read-only</access>
41759                </field>
41760              </fields>
41761            </register>
41762            <register>
41763              <dim>16</dim>
41764              <dimIncrement>4</dimIncrement>
41765              <name>PROT_EPO_CS1[%s]</name>
41766              <description>SuperSpeed OUT Endpoint Control and Status</description>
41767              <addressOffset>0x440</addressOffset>
41768              <size>32</size>
41769              <access>read-write</access>
41770              <resetValue>0x20</resetValue>
41771              <resetMask>0x3F</resetMask>
41772              <fields>
41773                <field>
41774                  <name>VALID</name>
41775                  <description>Set VALID=1 to activate an endpoint, and VALID=0 to de-activate it. All USB endpoints default to invalid. An endpoint whose VALID bit is 0 does not respond to any USB traffic.</description>
41776                  <bitRange>[0:0]</bitRange>
41777                  <access>read-write</access>
41778                </field>
41779                <field>
41780                  <name>NRDY</name>
41781                  <description>Setting this bit causes NRDY on IN transactions.</description>
41782                  <bitRange>[1:1]</bitRange>
41783                  <access>read-write</access>
41784                </field>
41785                <field>
41786                  <name>STALL</name>
41787                  <description>Set this bit to '1' to stall an endpoint, and to '0' to clear a stall.</description>
41788                  <bitRange>[2:2]</bitRange>
41789                  <access>read-write</access>
41790                </field>
41791                <field>
41792                  <name>STREAM_EN</name>
41793                  <description>Enables bulk stream protocol handling for this EP</description>
41794                  <bitRange>[3:3]</bitRange>
41795                  <access>read-write</access>
41796                </field>
41797                <field>
41798                  <name>EP_RESET</name>
41799                  <description>Per End Point Reset.</description>
41800                  <bitRange>[4:4]</bitRange>
41801                  <access>read-write</access>
41802                </field>
41803                <field>
41804                  <name>STREAM_ERROR_STALL_EN</name>
41805                  <description>Issue STALL whenever Stream error occurs.</description>
41806                  <bitRange>[5:5]</bitRange>
41807                  <access>read-write</access>
41808                </field>
41809              </fields>
41810            </register>
41811            <register>
41812              <dim>16</dim>
41813              <dimIncrement>4</dimIncrement>
41814              <name>PROT_EPO_CS2[%s]</name>
41815              <description>SuperSpeed IN Endpoint Control and Status</description>
41816              <addressOffset>0x480</addressOffset>
41817              <size>32</size>
41818              <access>read-write</access>
41819              <resetValue>0x40</resetValue>
41820              <resetMask>0xFFF</resetMask>
41821              <fields>
41822                <field>
41823                  <name>EPO_TYPE</name>
41824                  <description>Endpoint type (EP0 suports CONTROL only)
418250: ISO
418261: INT
418272: BULK
418283: CONTROL (only valid for EP0)</description>
41829                  <bitRange>[1:0]</bitRange>
41830                  <access>read-write</access>
41831                </field>
41832                <field>
41833                  <name>ISOINPKS</name>
41834                  <description>Number of packets to be sent per service interval .  Maximum can be 48 ( Max burst size* Mult field)</description>
41835                  <bitRange>[7:2]</bitRange>
41836                  <access>read-write</access>
41837                </field>
41838                <field>
41839                  <name>MAXBURST</name>
41840                  <description>Maximum number of packets the endpoint can receive
41841(truncated to 4b, 0 means 16)</description>
41842                  <bitRange>[11:8]</bitRange>
41843                  <access>read-write</access>
41844                </field>
41845              </fields>
41846            </register>
41847            <register>
41848              <dim>16</dim>
41849              <dimIncrement>4</dimIncrement>
41850              <name>PROT_EPO_UNMAPPED_STREAM[%s]</name>
41851              <description>Unmapped Stream Request</description>
41852              <addressOffset>0x4C0</addressOffset>
41853              <size>32</size>
41854              <access>read-only</access>
41855              <resetValue>0x0</resetValue>
41856              <resetMask>0xFFFFF</resetMask>
41857              <fields>
41858                <field>
41859                  <name>STREAM_ID</name>
41860                  <description>The StreamID of the current stream activated (or requested to be activated) by the protocol layer.</description>
41861                  <bitRange>[15:0]</bitRange>
41862                  <access>read-only</access>
41863                </field>
41864                <field>
41865                  <name>SPSM_STATE</name>
41866                  <description>Stream Protocol State Machine (SPSM) State for this EndPoint:
41867
418680: Not Configured
418691: Disabled
418702: Prime Pipe
418713: DFR Prime Pipe
418724: Idle
418735: Start Stream
418746: Move Data
418757: End
418768: Error</description>
41877                  <bitRange>[19:16]</bitRange>
41878                  <access>read-only</access>
41879                </field>
41880              </fields>
41881            </register>
41882            <register>
41883              <dim>16</dim>
41884              <dimIncrement>4</dimIncrement>
41885              <name>PROT_EPO_MAPPED_STREAM[%s]</name>
41886              <description>Mapped Streams Registers</description>
41887              <addressOffset>0x500</addressOffset>
41888              <size>32</size>
41889              <access>read-write</access>
41890              <resetValue>0x0</resetValue>
41891              <resetMask>0xE00FFFFF</resetMask>
41892              <fields>
41893                <field>
41894                  <name>STREAM_ID</name>
41895                  <description>The StreamID of the stream connected to the corresponding socket by firmware.</description>
41896                  <bitRange>[15:0]</bitRange>
41897                  <access>read-write</access>
41898                </field>
41899                <field>
41900                  <name>EP_NUMBER</name>
41901                  <description>The Endpoint number of the stream connected to the corresponding socket by firmware.</description>
41902                  <bitRange>[19:16]</bitRange>
41903                  <access>read-write</access>
41904                </field>
41905                <field>
41906                  <name>UNMAPPED</name>
41907                  <description>Stream is unmapped (not in use by the corresponding EP's SPSM).</description>
41908                  <bitRange>[29:29]</bitRange>
41909                  <access>read-only</access>
41910                </field>
41911                <field>
41912                  <name>UNMAP</name>
41913                  <description>Request to unmap this stream.  May be cleared to revert/withdaw request.</description>
41914                  <bitRange>[30:30]</bitRange>
41915                  <access>read-write</access>
41916                </field>
41917                <field>
41918                  <name>ENABLE</name>
41919                  <description>Set by firmware if a stream is mapped to the corresponding socket. If this bit is set, the endpoint number corresponding to this socket number can no longer be used in non-streaming mode (that would create a conflict of two endpoints wanting to use the same socket).</description>
41920                  <bitRange>[31:31]</bitRange>
41921                  <access>read-write</access>
41922                </field>
41923              </fields>
41924            </register>
41925            <register>
41926              <dim>16</dim>
41927              <dimIncrement>4</dimIncrement>
41928              <name>PROT_EPI_ARB_PKT[%s]</name>
41929              <description>Per IN-Endpoint # of packets per arbitration grant</description>
41930              <addressOffset>0x540</addressOffset>
41931              <size>32</size>
41932              <access>read-write</access>
41933              <resetValue>0x1</resetValue>
41934              <resetMask>0x1F</resetMask>
41935              <fields>
41936                <field>
41937                  <name>NUM_PKT_PER_ARB</name>
41938                  <description>The number of packets that can be sent for every arbitation grant for each EP</description>
41939                  <bitRange>[4:0]</bitRange>
41940                  <access>read-write</access>
41941                </field>
41942              </fields>
41943            </register>
41944          </cluster>
41945          <cluster>
41946            <name>PHYSS</name>
41947            <description>USB32 SuperSpeedPlus Physical Layer Registers</description>
41948            <addressOffset>0x00004000</addressOffset>
41949            <cluster>
41950              <dim>2</dim>
41951              <dimIncrement>4096</dimIncrement>
41952              <name>USB40PHY[%s]</name>
41953              <description>PHY Registers</description>
41954              <addressOffset>0x00000000</addressOffset>
41955              <cluster>
41956                <name>USB40PHY</name>
41957                <description>PHY TOP, PCS, Tx registers</description>
41958                <addressOffset>0x00000000</addressOffset>
41959                <register>
41960                  <name>USB40PHY_VERSION_CORE</name>
41961                  <description>USB40PHY Version core register</description>
41962                  <addressOffset>0x0</addressOffset>
41963                  <size>32</size>
41964                  <access>read-only</access>
41965                  <resetValue>0x11100000</resetValue>
41966                  <resetMask>0xFFF00FFF</resetMask>
41967                  <fields>
41968                    <field>
41969                      <name>REG_VERSION_AFE_PLL_SYS</name>
41970                      <description>USB40PHY PLL Soft_IP Version</description>
41971                      <bitRange>[3:0]</bitRange>
41972                      <access>read-only</access>
41973                    </field>
41974                    <field>
41975                      <name>REG_VERSION_AFE_RX</name>
41976                      <description>USB40PHY Rx Soft_IP Version</description>
41977                      <bitRange>[7:4]</bitRange>
41978                      <access>read-only</access>
41979                    </field>
41980                    <field>
41981                      <name>REG_VERSION_AFE_TX</name>
41982                      <description>USB40PHY Tx Soft_IP Version</description>
41983                      <bitRange>[11:8]</bitRange>
41984                      <access>read-only</access>
41985                    </field>
41986                    <field>
41987                      <name>REG_VERSION_PCS</name>
41988                      <description>USB40PHY Core Version</description>
41989                      <bitRange>[23:20]</bitRange>
41990                      <access>read-only</access>
41991                    </field>
41992                    <field>
41993                      <name>REG_VERSION_TX_DIGITAL_SERIALIZER</name>
41994                      <description>USB40PHY Core Version</description>
41995                      <bitRange>[27:24]</bitRange>
41996                      <access>read-only</access>
41997                    </field>
41998                    <field>
41999                      <name>REG_VERSION_CORE</name>
42000                      <description>USB40PHY Core Version</description>
42001                      <bitRange>[31:28]</bitRange>
42002                      <access>read-only</access>
42003                    </field>
42004                  </fields>
42005                </register>
42006                <register>
42007                  <name>TOP_CTRL_0</name>
42008                  <description>TOP control register</description>
42009                  <addressOffset>0x4</addressOffset>
42010                  <size>32</size>
42011                  <access>read-write</access>
42012                  <resetValue>0x20</resetValue>
42013                  <resetMask>0x7F</resetMask>
42014                  <fields>
42015                    <field>
42016                      <name>REG_PIPE_MODE</name>
42017                      <description>PIPE mode selection
420180: PIPE 4.4.1
420191: PIPE 5 for SerDes architecture</description>
42020                      <bitRange>[0:0]</bitRange>
42021                      <access>read-write</access>
42022                    </field>
42023                    <field>
42024                      <name>REG_PWR_GOOD_CORE_RX</name>
42025                      <description>Power Good Rx</description>
42026                      <bitRange>[1:1]</bitRange>
42027                      <access>read-write</access>
42028                    </field>
42029                    <field>
42030                      <name>REG_PWR_GOOD_CORE_PLL</name>
42031                      <description>Power Good PLL</description>
42032                      <bitRange>[2:2]</bitRange>
42033                      <access>read-write</access>
42034                    </field>
42035                    <field>
42036                      <name>REG_VBUS</name>
42037                      <description>VBUS indication register. It connects to PowerPresent on PIPE</description>
42038                      <bitRange>[3:3]</bitRange>
42039                      <access>read-write</access>
42040                    </field>
42041                    <field>
42042                      <name>REG_PLL_RSTB</name>
42043                      <description>PLL reset</description>
42044                      <bitRange>[4:4]</bitRange>
42045                      <access>read-write</access>
42046                    </field>
42047                    <field>
42048                      <name>REG_LFPS_CLK_DIV</name>
42049                      <description>LFPS clock divide nunber
420500: 100/(1+1) = 50MHz
420511: 100/(3+1) = 25MHz
420522: 100/(5+1) = 16MHz
420533: 100/(9+1) = 10MHz</description>
42054                      <bitRange>[6:5]</bitRange>
42055                      <access>read-write</access>
42056                    </field>
42057                  </fields>
42058                </register>
42059                <register>
42060                  <name>TOP_STATUS_0</name>
42061                  <description>TOP status register</description>
42062                  <addressOffset>0xC</addressOffset>
42063                  <size>32</size>
42064                  <access>read-only</access>
42065                  <resetValue>0x0</resetValue>
42066                  <resetMask>0x3</resetMask>
42067                  <fields>
42068                    <field>
42069                      <name>REG_TOP_RATE_CHANGE_DONE</name>
42070                      <description>Rate change configuration is done</description>
42071                      <bitRange>[0:0]</bitRange>
42072                      <access>read-only</access>
42073                    </field>
42074                    <field>
42075                      <name>REG_TOP_STATUS_TBD2</name>
42076                      <description>TBD</description>
42077                      <bitRange>[1:1]</bitRange>
42078                      <access>read-only</access>
42079                    </field>
42080                  </fields>
42081                </register>
42082                <register>
42083                  <name>PCS_CTRL_0</name>
42084                  <description>PCS control register</description>
42085                  <addressOffset>0x10</addressOffset>
42086                  <size>32</size>
42087                  <access>read-write</access>
42088                  <resetValue>0x22</resetValue>
42089                  <resetMask>0x73</resetMask>
42090                  <fields>
42091                    <field>
42092                      <name>REG_SEL_BIT_MODE</name>
42093                      <description>Data bitwidth mode selection (Not used. Replaced to the 'reg_pipe_rate_ovrd')
420940: 16bit
420951: 20bit, Gen1(5Gbps), (8b/10b), 125MHz PCLK, 250MHz PCS PCLK(internal)
420962: 32bit, Gen2(10Gbps), (128b/132b), 312.5MHz PCLK
420973: 40bit</description>
42098                      <bitRange>[1:0]</bitRange>
42099                      <access>read-write</access>
42100                    </field>
42101                    <field>
42102                      <name>REG_ONEZERO_CNT</name>
42103                      <description>USB 3.1 CP7/CP8 one_zero number selection (1clk = 40bit)
421040: 2clk -&gt; one*80, zero*80
421051: 3clk -&gt; one*120, zero*120
421062: 4clk -&gt; one*160, zero*160
421073: 5clk -&gt; one*200, zero*200
421084: 6clk -&gt; one*240, zero*240</description>
42109                      <bitRange>[6:4]</bitRange>
42110                      <access>read-write</access>
42111                    </field>
42112                  </fields>
42113                </register>
42114                <register>
42115                  <name>PCS_STATUS</name>
42116                  <description>PCS status register</description>
42117                  <addressOffset>0x18</addressOffset>
42118                  <size>32</size>
42119                  <access>read-only</access>
42120                  <resetValue>0x0</resetValue>
42121                  <resetMask>0x3</resetMask>
42122                  <fields>
42123                    <field>
42124                      <name>REG_PCS_STATUS</name>
42125                      <description>TBD</description>
42126                      <bitRange>[1:0]</bitRange>
42127                      <access>read-only</access>
42128                    </field>
42129                  </fields>
42130                </register>
42131                <register>
42132                  <name>PCS_SPARE</name>
42133                  <description>PCS spare</description>
42134                  <addressOffset>0x1C</addressOffset>
42135                  <size>32</size>
42136                  <access>read-write</access>
42137                  <resetValue>0xFF000000</resetValue>
42138                  <resetMask>0xFFFFFFFF</resetMask>
42139                  <fields>
42140                    <field>
42141                      <name>REG_DFT</name>
42142                      <description>Spare</description>
42143                      <bitRange>[11:0]</bitRange>
42144                      <access>read-write</access>
42145                    </field>
42146                    <field>
42147                      <name>REG_SPARE0</name>
42148                      <description>Spare with default 0</description>
42149                      <bitRange>[23:12]</bitRange>
42150                      <access>read-write</access>
42151                    </field>
42152                    <field>
42153                      <name>REG_SPARE1</name>
42154                      <description>Spare with default 1</description>
42155                      <bitRange>[31:24]</bitRange>
42156                      <access>read-write</access>
42157                    </field>
42158                  </fields>
42159                </register>
42160                <register>
42161                  <name>PIPE_OVERRIDE_0</name>
42162                  <description>PIPE interface control signals override register #0</description>
42163                  <addressOffset>0x30</addressOffset>
42164                  <size>32</size>
42165                  <access>read-write</access>
42166                  <resetValue>0x0</resetValue>
42167                  <resetMask>0x7FFFFFFF</resetMask>
42168                  <fields>
42169                    <field>
42170                      <name>REG_PIPE_PHY_MODE_OVRD_EN</name>
42171                      <description>PIPE - Selects PHY operating mode. (PCIe/USB/SATA/DP)</description>
42172                      <bitRange>[0:0]</bitRange>
42173                      <access>read-write</access>
42174                    </field>
42175                    <field>
42176                      <name>REG_PIPE_PHY_MODE_OVRD_VALUE</name>
42177                      <description>PIPE - Selects PHY operating mode. (PCIe/USB/SATA/DP)</description>
42178                      <bitRange>[4:1]</bitRange>
42179                      <access>read-write</access>
42180                    </field>
42181                    <field>
42182                      <name>REG_PIPE_EB_MODE_OVRD_EN</name>
42183                      <description>PIPE - Selects elastic buffer operating mode</description>
42184                      <bitRange>[5:5]</bitRange>
42185                      <access>read-write</access>
42186                    </field>
42187                    <field>
42188                      <name>REG_PIPE_EB_MODE_OVRD_VALUE</name>
42189                      <description>PIPE - Selects elastic buffer operating mode</description>
42190                      <bitRange>[6:6]</bitRange>
42191                      <access>read-write</access>
42192                    </field>
42193                    <field>
42194                      <name>REG_PIPE_TX_DETECTRX_OVRD_EN</name>
42195                      <description>PIPE - Controls receiver detection or loopback mode</description>
42196                      <bitRange>[7:7]</bitRange>
42197                      <access>read-write</access>
42198                    </field>
42199                    <field>
42200                      <name>REG_PIPE_TX_DETECTRX_OVRD_VALUE</name>
42201                      <description>PIPE - Controls receiver detection or loopback mode</description>
42202                      <bitRange>[8:8]</bitRange>
42203                      <access>read-write</access>
42204                    </field>
42205                    <field>
42206                      <name>REG_PIPE_TX_ELECTIDLE_OVRD_EN</name>
42207                      <description>PIPE - Tx Electric Idle - Forces Tx output to Electrical Idle when asserted</description>
42208                      <bitRange>[9:9]</bitRange>
42209                      <access>read-write</access>
42210                    </field>
42211                    <field>
42212                      <name>REG_PIPE_TX_ELECTIDLE_OVRD_VALUE</name>
42213                      <description>PIPE - Tx Electric Idle - Forces Tx output to Electrical Idle when asserted</description>
42214                      <bitRange>[10:10]</bitRange>
42215                      <access>read-write</access>
42216                    </field>
42217                    <field>
42218                      <name>REG_PIPE_TX_ONE_ZEROS_OVRD_EN</name>
42219                      <description>PIPE - Enables USB SS compliance pattern CP7 or CP8</description>
42220                      <bitRange>[11:11]</bitRange>
42221                      <access>read-write</access>
42222                    </field>
42223                    <field>
42224                      <name>REG_PIPE_TX_ONE_ZEROS_OVRD_VALUE</name>
42225                      <description>PIPE - Enables USB SS compliance pattern CP7 or CP8</description>
42226                      <bitRange>[12:12]</bitRange>
42227                      <access>read-write</access>
42228                    </field>
42229                    <field>
42230                      <name>REG_PIPE_RX_POLARITY_OVRD_EN</name>
42231                      <description>PIPE - Enables receiver polarity inversion</description>
42232                      <bitRange>[13:13]</bitRange>
42233                      <access>read-write</access>
42234                    </field>
42235                    <field>
42236                      <name>REG_PIPE_RX_POLARITY_OVRD_VALUE</name>
42237                      <description>PIPE - Enables receiver polarity inversion</description>
42238                      <bitRange>[14:14]</bitRange>
42239                      <access>read-write</access>
42240                    </field>
42241                    <field>
42242                      <name>REG_PIPE_RX_EQ_TRAINING_OVRD_EN</name>
42243                      <description>PIPE - Enables equalization training</description>
42244                      <bitRange>[15:15]</bitRange>
42245                      <access>read-write</access>
42246                    </field>
42247                    <field>
42248                      <name>REG_PIPE_RX_EQ_TRAINING_OVRD_VALUE</name>
42249                      <description>PIPE - Enables equalization training</description>
42250                      <bitRange>[16:16]</bitRange>
42251                      <access>read-write</access>
42252                    </field>
42253                    <field>
42254                      <name>REG_PIPE_POWER_DOWN_OVRD_EN</name>
42255                      <description>PIPE - Controls the transceiver power state</description>
42256                      <bitRange>[17:17]</bitRange>
42257                      <access>read-write</access>
42258                    </field>
42259                    <field>
42260                      <name>REG_PIPE_POWER_DOWN_OVRD_VALUE</name>
42261                      <description>PIPE - Controls the transceiver power state</description>
42262                      <bitRange>[20:18]</bitRange>
42263                      <access>read-write</access>
42264                    </field>
42265                    <field>
42266                      <name>REG_PIPE_RATE_OVRD_EN</name>
42267                      <description>PIPE - Control the link signlaing rate</description>
42268                      <bitRange>[21:21]</bitRange>
42269                      <access>read-write</access>
42270                    </field>
42271                    <field>
42272                      <name>REG_PIPE_RATE_OVRD_VALUE</name>
42273                      <description>PIPE - Control the link signlaing rate</description>
42274                      <bitRange>[23:22]</bitRange>
42275                      <access>read-write</access>
42276                    </field>
42277                    <field>
42278                      <name>REG_PIPE_WIDTH_OVRD_EN</name>
42279                      <description>PIPE - Control the PIPE data path width</description>
42280                      <bitRange>[24:24]</bitRange>
42281                      <access>read-write</access>
42282                    </field>
42283                    <field>
42284                      <name>REG_PIPE_WIDTH_OVRD_VALUE</name>
42285                      <description>PIPE - Control the PIPE data path width</description>
42286                      <bitRange>[26:25]</bitRange>
42287                      <access>read-write</access>
42288                    </field>
42289                    <field>
42290                      <name>REG_PIPE_PCLK_RATE_OVRD_EN</name>
42291                      <description>PIPE - Control the PIPE PCLK rate</description>
42292                      <bitRange>[27:27]</bitRange>
42293                      <access>read-write</access>
42294                    </field>
42295                    <field>
42296                      <name>REG_PIPE_PCLK_RATE_OVRD_VALUE</name>
42297                      <description>PIPE - Control the PIPE PCLK rate</description>
42298                      <bitRange>[30:28]</bitRange>
42299                      <access>read-write</access>
42300                    </field>
42301                  </fields>
42302                </register>
42303                <register>
42304                  <name>PIPE_OVERRIDE_1</name>
42305                  <description>PIPE interface control signals override register #1</description>
42306                  <addressOffset>0x34</addressOffset>
42307                  <size>32</size>
42308                  <access>read-write</access>
42309                  <resetValue>0x0</resetValue>
42310                  <resetMask>0x7FFFFFF</resetMask>
42311                  <fields>
42312                    <field>
42313                      <name>REG_PIPE_RX_TERMINATION_OVRD_EN</name>
42314                      <description>PIPE - Controls presence of receiver terminations</description>
42315                      <bitRange>[0:0]</bitRange>
42316                      <access>read-write</access>
42317                    </field>
42318                    <field>
42319                      <name>REG_PIPE_RX_TERMINATION_OVRD_VALUE</name>
42320                      <description>PIPE - Controls presence of receiver terminations</description>
42321                      <bitRange>[1:1]</bitRange>
42322                      <access>read-write</access>
42323                    </field>
42324                    <field>
42325                      <name>REG_PIPE_RX_STANDBY_OVRD_EN</name>
42326                      <description>PIPE - Controls whether the PHY RX is active when the PHY is in any power state with PCLK on</description>
42327                      <bitRange>[2:2]</bitRange>
42328                      <access>read-write</access>
42329                    </field>
42330                    <field>
42331                      <name>REG_PIPE_RX_STANDBY_OVRD_VALUE</name>
42332                      <description>PIPE - Controls whether the PHY RX is active when the PHY is in any power state with PCLK on</description>
42333                      <bitRange>[3:3]</bitRange>
42334                      <access>read-write</access>
42335                    </field>
42336                    <field>
42337                      <name>REG_PIPE_ENC_DEC_BYPASS_OVRD_EN</name>
42338                      <description>PIPE - Controls whether the PHY performs 8b/10b encode and decode</description>
42339                      <bitRange>[4:4]</bitRange>
42340                      <access>read-write</access>
42341                    </field>
42342                    <field>
42343                      <name>REG_PIPE_ENC_DEC_BYPASS_OVRD_VALUE</name>
42344                      <description>PIPE - Controls whether the PHY performs 8b/10b encode and decode</description>
42345                      <bitRange>[5:5]</bitRange>
42346                      <access>read-write</access>
42347                    </field>
42348                    <field>
42349                      <name>REG_PIPE_BLOCK_ALIGN_CONTROL_OVRD_EN</name>
42350                      <description>PIPE - Enables SYNC OS detection</description>
42351                      <bitRange>[6:6]</bitRange>
42352                      <access>read-write</access>
42353                    </field>
42354                    <field>
42355                      <name>REG_PIPE_BLOCK_ALIGN_CONTROL_OVRD_VALUE</name>
42356                      <description>PIPE - Enables SYNC OS detection</description>
42357                      <bitRange>[7:7]</bitRange>
42358                      <access>read-write</access>
42359                    </field>
42360                    <field>
42361                      <name>REG_PIPE_TX_DEEMPH_OVRD_EN</name>
42362                      <description>PIPE - Selects transmitter de-emphasis</description>
42363                      <bitRange>[8:8]</bitRange>
42364                      <access>read-write</access>
42365                    </field>
42366                    <field>
42367                      <name>REG_PIPE_TX_DEEMPH_OVRD_VALUE</name>
42368                      <description>PIPE - Selects transmitter de-emphasis</description>
42369                      <bitRange>[26:9]</bitRange>
42370                      <access>read-write</access>
42371                    </field>
42372                  </fields>
42373                </register>
42374                <register>
42375                  <name>PIPE_STATUS</name>
42376                  <description>PIPE interface status read register</description>
42377                  <addressOffset>0x38</addressOffset>
42378                  <size>32</size>
42379                  <access>read-only</access>
42380                  <resetValue>0x0</resetValue>
42381                  <resetMask>0x7F</resetMask>
42382                  <fields>
42383                    <field>
42384                      <name>REG_PIPE_RXVALID</name>
42385                      <description>PIPE - Indicates symbol lock and valid data</description>
42386                      <bitRange>[0:0]</bitRange>
42387                      <access>read-only</access>
42388                    </field>
42389                    <field>
42390                      <name>REG_PIPE_PHY_STATUS</name>
42391                      <description>PIPE - Indicates completion of PHY operations</description>
42392                      <bitRange>[1:1]</bitRange>
42393                      <access>read-only</access>
42394                    </field>
42395                    <field>
42396                      <name>REG_PIPE_RX_ELECIDLE</name>
42397                      <description>PIPE - Indicates receiver detection of electrical idle</description>
42398                      <bitRange>[2:2]</bitRange>
42399                      <access>read-only</access>
42400                    </field>
42401                    <field>
42402                      <name>REG_PIPE_RX_STATUS</name>
42403                      <description>PIPE - Indicates status of received data and receiver detection</description>
42404                      <bitRange>[5:3]</bitRange>
42405                      <access>read-only</access>
42406                    </field>
42407                    <field>
42408                      <name>REG_PIPE_POWER_PRESENT</name>
42409                      <description>PIPE - Indicates the presence of VBUS</description>
42410                      <bitRange>[6:6]</bitRange>
42411                      <access>read-only</access>
42412                    </field>
42413                  </fields>
42414                </register>
42415                <register>
42416                  <name>INTR0</name>
42417                  <description>INTR0 Cause.  These are the wakeup interrupts get reflected on interrupt_wakeup pin.</description>
42418                  <addressOffset>0x40</addressOffset>
42419                  <size>32</size>
42420                  <access>read-write</access>
42421                  <resetValue>0x0</resetValue>
42422                  <resetMask>0x7FFFF</resetMask>
42423                  <fields>
42424                    <field>
42425                      <name>REG_INT_RATE_CHANGE</name>
42426                      <description>Indicates RATE change to F/W. RATE information comes from MAC</description>
42427                      <bitRange>[0:0]</bitRange>
42428                      <access>read-write</access>
42429                    </field>
42430                    <field>
42431                      <name>REG_INT_P0_CHANGE</name>
42432                      <description>Indicates P0 change to F/W. PowerDown information comes from MAC</description>
42433                      <bitRange>[1:1]</bitRange>
42434                      <access>read-write</access>
42435                    </field>
42436                    <field>
42437                      <name>REG_INT_P1_CHANGE</name>
42438                      <description>Indicates P1 change to F/W. PowerDown information comes from MAC</description>
42439                      <bitRange>[2:2]</bitRange>
42440                      <access>read-write</access>
42441                    </field>
42442                    <field>
42443                      <name>REG_INT_P2_CHANGE</name>
42444                      <description>Indicates P2 change to F/W. PowerDown information comes from MAC</description>
42445                      <bitRange>[3:3]</bitRange>
42446                      <access>read-write</access>
42447                    </field>
42448                    <field>
42449                      <name>REG_INT_P3_CHANGE</name>
42450                      <description>Indicates P3 change to F/W. PowerDown information comes from MAC</description>
42451                      <bitRange>[4:4]</bitRange>
42452                      <access>read-write</access>
42453                    </field>
42454                    <field>
42455                      <name>REG_INT_TX_SFT_REG_WDONE</name>
42456                      <description>Indicates shift register write done</description>
42457                      <bitRange>[5:5]</bitRange>
42458                      <access>read-write</access>
42459                    </field>
42460                    <field>
42461                      <name>REG_INT_RX_PLL_LOCKED</name>
42462                      <description>Loss of RX PLL clock</description>
42463                      <bitRange>[6:6]</bitRange>
42464                      <access>read-write</access>
42465                    </field>
42466                    <field>
42467                      <name>REG_INT_RX_POWER_GOOD_RXA</name>
42468                      <description>RXA Regulator power good</description>
42469                      <bitRange>[7:7]</bitRange>
42470                      <access>read-write</access>
42471                    </field>
42472                    <field>
42473                      <name>REG_INT_RX_POWER_GOOD_RXCK</name>
42474                      <description>RXCK Regulator power good</description>
42475                      <bitRange>[8:8]</bitRange>
42476                      <access>read-write</access>
42477                    </field>
42478                    <field>
42479                      <name>REG_INT_RX_POWER_GOOD_RXD</name>
42480                      <description>RXD Regulator power good</description>
42481                      <bitRange>[9:9]</bitRange>
42482                      <access>read-write</access>
42483                    </field>
42484                    <field>
42485                      <name>REG_INT_RX_OSA_ERROR</name>
42486                      <description>Indicates failure of offset calibration</description>
42487                      <bitRange>[10:10]</bitRange>
42488                      <access>read-write</access>
42489                    </field>
42490                    <field>
42491                      <name>REG_INT_RX_OSA_ALL_DONE</name>
42492                      <description>Indicates all offset calibration complete</description>
42493                      <bitRange>[11:11]</bitRange>
42494                      <access>read-write</access>
42495                    </field>
42496                    <field>
42497                      <name>REG_INT_RX_LFPSDET_OUT</name>
42498                      <description>Indicates LFPS detected on RX pins</description>
42499                      <bitRange>[12:12]</bitRange>
42500                      <access>read-write</access>
42501                    </field>
42502                    <field>
42503                      <name>REG_INT_RX_EYE_HIGHT_DONE</name>
42504                      <description>Interrupt to controller indicating completation of eye height measurement</description>
42505                      <bitRange>[13:13]</bitRange>
42506                      <access>read-write</access>
42507                    </field>
42508                    <field>
42509                      <name>REG_INT_RX_EYE_MON_DONE</name>
42510                      <description>Interrupt to controller indicating completation of eye monitor measurement</description>
42511                      <bitRange>[14:14]</bitRange>
42512                      <access>read-write</access>
42513                    </field>
42514                    <field>
42515                      <name>REG_INT_PLL_LOCKED</name>
42516                      <description>Loss of PLL clock</description>
42517                      <bitRange>[15:15]</bitRange>
42518                      <access>read-write</access>
42519                    </field>
42520                    <field>
42521                      <name>REG_INT_PLL_PWR_GOOD_LCPLL</name>
42522                      <description>Indicates vreglcpll power good</description>
42523                      <bitRange>[16:16]</bitRange>
42524                      <access>read-write</access>
42525                    </field>
42526                    <field>
42527                      <name>REG_INT_PLL_PWR_GOOD_REF</name>
42528                      <description>Indicates vregref power good</description>
42529                      <bitRange>[17:17]</bitRange>
42530                      <access>read-write</access>
42531                    </field>
42532                    <field>
42533                      <name>REG_INT_PLL_PWR_GOOD_DIG</name>
42534                      <description>Indicates vregdig power good</description>
42535                      <bitRange>[18:18]</bitRange>
42536                      <access>read-write</access>
42537                    </field>
42538                  </fields>
42539                </register>
42540                <register>
42541                  <name>INTR0_SET</name>
42542                  <description>INTR0 Set</description>
42543                  <addressOffset>0x44</addressOffset>
42544                  <size>32</size>
42545                  <access>read-write</access>
42546                  <resetValue>0x0</resetValue>
42547                  <resetMask>0x7FFFF</resetMask>
42548                  <fields>
42549                    <field>
42550                      <name>REG_INT_RATE_CHANGE</name>
42551                      <description>Write with '1' to set corresponding bit in interrupt request register.</description>
42552                      <bitRange>[0:0]</bitRange>
42553                      <access>read-write</access>
42554                    </field>
42555                    <field>
42556                      <name>REG_INT_P0_CHANGE</name>
42557                      <description>Write with '1' to set corresponding bit in interrupt request register.</description>
42558                      <bitRange>[1:1]</bitRange>
42559                      <access>read-write</access>
42560                    </field>
42561                    <field>
42562                      <name>REG_INT_P1_CHANGE</name>
42563                      <description>Write with '1' to set corresponding bit in interrupt request register.</description>
42564                      <bitRange>[2:2]</bitRange>
42565                      <access>read-write</access>
42566                    </field>
42567                    <field>
42568                      <name>REG_INT_P2_CHANGE</name>
42569                      <description>Write with '1' to set corresponding bit in interrupt request register.</description>
42570                      <bitRange>[3:3]</bitRange>
42571                      <access>read-write</access>
42572                    </field>
42573                    <field>
42574                      <name>REG_INT_P3_CHANGE</name>
42575                      <description>Write with '1' to set corresponding bit in interrupt request register.</description>
42576                      <bitRange>[4:4]</bitRange>
42577                      <access>read-write</access>
42578                    </field>
42579                    <field>
42580                      <name>REG_INT_TX_SFT_REG_WDONE</name>
42581                      <description>Write with '1' to set corresponding bit in interrupt request register.</description>
42582                      <bitRange>[5:5]</bitRange>
42583                      <access>read-write</access>
42584                    </field>
42585                    <field>
42586                      <name>REG_INT_RX_PLL_LOCKED</name>
42587                      <description>Write with '1' to set corresponding bit in interrupt request register.</description>
42588                      <bitRange>[6:6]</bitRange>
42589                      <access>read-write</access>
42590                    </field>
42591                    <field>
42592                      <name>REG_INT_RX_POWER_GOOD_RXA</name>
42593                      <description>Write with '1' to set corresponding bit in interrupt request register.</description>
42594                      <bitRange>[7:7]</bitRange>
42595                      <access>read-write</access>
42596                    </field>
42597                    <field>
42598                      <name>REG_INT_RX_POWER_GOOD_RXCK</name>
42599                      <description>Write with '1' to set corresponding bit in interrupt request register.</description>
42600                      <bitRange>[8:8]</bitRange>
42601                      <access>read-write</access>
42602                    </field>
42603                    <field>
42604                      <name>REG_INT_RX_POWER_GOOD_RXD</name>
42605                      <description>Write with '1' to set corresponding bit in interrupt request register.</description>
42606                      <bitRange>[9:9]</bitRange>
42607                      <access>read-write</access>
42608                    </field>
42609                    <field>
42610                      <name>REG_INT_RX_OSA_ERROR</name>
42611                      <description>Write with '1' to set corresponding bit in interrupt request register.</description>
42612                      <bitRange>[10:10]</bitRange>
42613                      <access>read-write</access>
42614                    </field>
42615                    <field>
42616                      <name>REG_INT_RX_OSA_ALL_DONE</name>
42617                      <description>Write with '1' to set corresponding bit in interrupt request register.</description>
42618                      <bitRange>[11:11]</bitRange>
42619                      <access>read-write</access>
42620                    </field>
42621                    <field>
42622                      <name>REG_INT_RX_LFPSDET_OUT</name>
42623                      <description>Write with '1' to set corresponding bit in interrupt request register.</description>
42624                      <bitRange>[12:12]</bitRange>
42625                      <access>read-write</access>
42626                    </field>
42627                    <field>
42628                      <name>REG_INT_RX_EYE_HIGHT_DONE</name>
42629                      <description>Write with '1' to set corresponding bit in interrupt request register.</description>
42630                      <bitRange>[13:13]</bitRange>
42631                      <access>read-write</access>
42632                    </field>
42633                    <field>
42634                      <name>REG_INT_RX_EYE_MON_DONE</name>
42635                      <description>Write with '1' to set corresponding bit in interrupt request register.</description>
42636                      <bitRange>[14:14]</bitRange>
42637                      <access>read-write</access>
42638                    </field>
42639                    <field>
42640                      <name>REG_INT_PLL_LOCKED</name>
42641                      <description>Write with '1' to set corresponding bit in interrupt request register.</description>
42642                      <bitRange>[15:15]</bitRange>
42643                      <access>read-write</access>
42644                    </field>
42645                    <field>
42646                      <name>REG_INT_PLL_PWR_GOOD_LCPLL</name>
42647                      <description>Write with '1' to set corresponding bit in interrupt request register.</description>
42648                      <bitRange>[16:16]</bitRange>
42649                      <access>read-write</access>
42650                    </field>
42651                    <field>
42652                      <name>REG_INT_PLL_PWR_GOOD_REF</name>
42653                      <description>Write with '1' to set corresponding bit in interrupt request register.</description>
42654                      <bitRange>[17:17]</bitRange>
42655                      <access>read-write</access>
42656                    </field>
42657                    <field>
42658                      <name>REG_INT_PLL_PWR_GOOD_DIG</name>
42659                      <description>Write with '1' to set corresponding bit in interrupt request register.</description>
42660                      <bitRange>[18:18]</bitRange>
42661                      <access>read-write</access>
42662                    </field>
42663                  </fields>
42664                </register>
42665                <register>
42666                  <name>INTR0_MASK</name>
42667                  <description>INTR0 Mask</description>
42668                  <addressOffset>0x48</addressOffset>
42669                  <size>32</size>
42670                  <access>read-write</access>
42671                  <resetValue>0x0</resetValue>
42672                  <resetMask>0x7FFFF</resetMask>
42673                  <fields>
42674                    <field>
42675                      <name>REG_INT_RATE_CHANGE_MASK</name>
42676                      <description>Mask bit for corresponding bit in interrupt request register.</description>
42677                      <bitRange>[0:0]</bitRange>
42678                      <access>read-write</access>
42679                    </field>
42680                    <field>
42681                      <name>REG_INT_P0_CHANGE_MASK</name>
42682                      <description>Mask bit for corresponding bit in interrupt request register.</description>
42683                      <bitRange>[1:1]</bitRange>
42684                      <access>read-write</access>
42685                    </field>
42686                    <field>
42687                      <name>REG_INT_P1_CHANGE_MASK</name>
42688                      <description>Mask bit for corresponding bit in interrupt request register.</description>
42689                      <bitRange>[2:2]</bitRange>
42690                      <access>read-write</access>
42691                    </field>
42692                    <field>
42693                      <name>REG_INT_P2_CHANGE_MASK</name>
42694                      <description>Mask bit for corresponding bit in interrupt request register.</description>
42695                      <bitRange>[3:3]</bitRange>
42696                      <access>read-write</access>
42697                    </field>
42698                    <field>
42699                      <name>REG_INT_P3_CHANGE_MASK</name>
42700                      <description>Mask bit for corresponding bit in interrupt request register.</description>
42701                      <bitRange>[4:4]</bitRange>
42702                      <access>read-write</access>
42703                    </field>
42704                    <field>
42705                      <name>REG_INT_TX_SFT_REG_WDONE_MASK</name>
42706                      <description>Mask bit for corresponding bit in interrupt request register.</description>
42707                      <bitRange>[5:5]</bitRange>
42708                      <access>read-write</access>
42709                    </field>
42710                    <field>
42711                      <name>REG_INT_RX_PLL_LOCKED_MASK</name>
42712                      <description>Mask bit for corresponding bit in interrupt request register.</description>
42713                      <bitRange>[6:6]</bitRange>
42714                      <access>read-write</access>
42715                    </field>
42716                    <field>
42717                      <name>REG_INT_RX_POWER_GOOD_RXA_MASK</name>
42718                      <description>Mask bit for corresponding bit in interrupt request register.</description>
42719                      <bitRange>[7:7]</bitRange>
42720                      <access>read-write</access>
42721                    </field>
42722                    <field>
42723                      <name>REG_INT_RX_POWER_GOOD_RXCK_MASK</name>
42724                      <description>Mask bit for corresponding bit in interrupt request register.</description>
42725                      <bitRange>[8:8]</bitRange>
42726                      <access>read-write</access>
42727                    </field>
42728                    <field>
42729                      <name>REG_INT_RX_POWER_GOOD_RXD_MASK</name>
42730                      <description>Mask bit for corresponding bit in interrupt request register.</description>
42731                      <bitRange>[9:9]</bitRange>
42732                      <access>read-write</access>
42733                    </field>
42734                    <field>
42735                      <name>REG_INT_RX_OSA_ERROR_MASK</name>
42736                      <description>Mask bit for corresponding bit in interrupt request register.</description>
42737                      <bitRange>[10:10]</bitRange>
42738                      <access>read-write</access>
42739                    </field>
42740                    <field>
42741                      <name>REG_INT_RX_OSA_ALL_DONE_MASK</name>
42742                      <description>Mask bit for corresponding bit in interrupt request register.</description>
42743                      <bitRange>[11:11]</bitRange>
42744                      <access>read-write</access>
42745                    </field>
42746                    <field>
42747                      <name>REG_INT_RX_LFPSDET_OUT_MASK</name>
42748                      <description>Mask bit for corresponding bit in interrupt request register.</description>
42749                      <bitRange>[12:12]</bitRange>
42750                      <access>read-write</access>
42751                    </field>
42752                    <field>
42753                      <name>REG_INT_RX_EYE_HIGHT_DONE_MASK</name>
42754                      <description>Mask bit for corresponding bit in interrupt request register.</description>
42755                      <bitRange>[13:13]</bitRange>
42756                      <access>read-write</access>
42757                    </field>
42758                    <field>
42759                      <name>REG_INT_RX_EYE_MON_DONE_MASK</name>
42760                      <description>Mask bit for corresponding bit in interrupt request register.</description>
42761                      <bitRange>[14:14]</bitRange>
42762                      <access>read-write</access>
42763                    </field>
42764                    <field>
42765                      <name>REG_INT_PLL_LOCKED_MASK</name>
42766                      <description>Mask bit for corresponding bit in interrupt request register.</description>
42767                      <bitRange>[15:15]</bitRange>
42768                      <access>read-write</access>
42769                    </field>
42770                    <field>
42771                      <name>REG_INT_PLL_PWR_GOOD_LCPLL_MASK</name>
42772                      <description>Mask bit for corresponding bit in interrupt request register.</description>
42773                      <bitRange>[16:16]</bitRange>
42774                      <access>read-write</access>
42775                    </field>
42776                    <field>
42777                      <name>REG_INT_PLL_PWR_GOOD_REF_MASK</name>
42778                      <description>Mask bit for corresponding bit in interrupt request register.</description>
42779                      <bitRange>[17:17]</bitRange>
42780                      <access>read-write</access>
42781                    </field>
42782                    <field>
42783                      <name>REG_INT_PLL_PWR_GOOD_DIG_MASK</name>
42784                      <description>Mask bit for corresponding bit in interrupt request register.</description>
42785                      <bitRange>[18:18]</bitRange>
42786                      <access>read-write</access>
42787                    </field>
42788                  </fields>
42789                </register>
42790                <register>
42791                  <name>INTR0_MASKED</name>
42792                  <description>INTR0 Masked</description>
42793                  <addressOffset>0x4C</addressOffset>
42794                  <size>32</size>
42795                  <access>read-only</access>
42796                  <resetValue>0x0</resetValue>
42797                  <resetMask>0x7FFFF</resetMask>
42798                  <fields>
42799                    <field>
42800                      <name>REG_INT_RATE_CHANGE_MASKD</name>
42801                      <description>Logical and of corresponding request and mask bits.</description>
42802                      <bitRange>[0:0]</bitRange>
42803                      <access>read-only</access>
42804                    </field>
42805                    <field>
42806                      <name>REG_INT_P0_CHANGE_MASKD</name>
42807                      <description>Logical and of corresponding request and mask bits.</description>
42808                      <bitRange>[1:1]</bitRange>
42809                      <access>read-only</access>
42810                    </field>
42811                    <field>
42812                      <name>REG_INT_P1_CHANGE_MASKD</name>
42813                      <description>Logical and of corresponding request and mask bits.</description>
42814                      <bitRange>[2:2]</bitRange>
42815                      <access>read-only</access>
42816                    </field>
42817                    <field>
42818                      <name>REG_INT_P2_CHANGE_MASKD</name>
42819                      <description>Logical and of corresponding request and mask bits.</description>
42820                      <bitRange>[3:3]</bitRange>
42821                      <access>read-only</access>
42822                    </field>
42823                    <field>
42824                      <name>REG_INT_P3_CHANGE_MASKD</name>
42825                      <description>Logical and of corresponding request and mask bits.</description>
42826                      <bitRange>[4:4]</bitRange>
42827                      <access>read-only</access>
42828                    </field>
42829                    <field>
42830                      <name>REG_INT_TX_SFT_REG_WDONE_MASKD</name>
42831                      <description>Logical and of corresponding request and mask bits.</description>
42832                      <bitRange>[5:5]</bitRange>
42833                      <access>read-only</access>
42834                    </field>
42835                    <field>
42836                      <name>REG_INT_RX_PLL_LOCKED_MASKD</name>
42837                      <description>Logical and of corresponding request and mask bits.</description>
42838                      <bitRange>[6:6]</bitRange>
42839                      <access>read-only</access>
42840                    </field>
42841                    <field>
42842                      <name>REG_INT_RX_POWER_GOOD_RXA_MASKD</name>
42843                      <description>Logical and of corresponding request and mask bits.</description>
42844                      <bitRange>[7:7]</bitRange>
42845                      <access>read-only</access>
42846                    </field>
42847                    <field>
42848                      <name>REG_INT_RX_POWER_GOOD_RXCK_MASKD</name>
42849                      <description>Logical and of corresponding request and mask bits.</description>
42850                      <bitRange>[8:8]</bitRange>
42851                      <access>read-only</access>
42852                    </field>
42853                    <field>
42854                      <name>REG_INT_RX_POWER_GOOD_RXD_MASKD</name>
42855                      <description>Logical and of corresponding request and mask bits.</description>
42856                      <bitRange>[9:9]</bitRange>
42857                      <access>read-only</access>
42858                    </field>
42859                    <field>
42860                      <name>REG_INT_RX_OSA_ERROR_MASKD</name>
42861                      <description>Logical and of corresponding request and mask bits.</description>
42862                      <bitRange>[10:10]</bitRange>
42863                      <access>read-only</access>
42864                    </field>
42865                    <field>
42866                      <name>REG_INT_RX_OSA_ALL_DONE_MASKD</name>
42867                      <description>Logical and of corresponding request and mask bits.</description>
42868                      <bitRange>[11:11]</bitRange>
42869                      <access>read-only</access>
42870                    </field>
42871                    <field>
42872                      <name>REG_INT_RX_LFPSDET_OUT_MASKD</name>
42873                      <description>Logical and of corresponding request and mask bits.</description>
42874                      <bitRange>[12:12]</bitRange>
42875                      <access>read-only</access>
42876                    </field>
42877                    <field>
42878                      <name>REG_INT_RX_EYE_HIGHT_DONE_MASKD</name>
42879                      <description>Logical and of corresponding request and mask bits.</description>
42880                      <bitRange>[13:13]</bitRange>
42881                      <access>read-only</access>
42882                    </field>
42883                    <field>
42884                      <name>REG_INT_RX_EYE_MON_DONE_MASKD</name>
42885                      <description>Logical and of corresponding request and mask bits.</description>
42886                      <bitRange>[14:14]</bitRange>
42887                      <access>read-only</access>
42888                    </field>
42889                    <field>
42890                      <name>REG_INT_PLL_LOCKED_MASKD</name>
42891                      <description>Logical and of corresponding request and mask bits.</description>
42892                      <bitRange>[15:15]</bitRange>
42893                      <access>read-only</access>
42894                    </field>
42895                    <field>
42896                      <name>REG_INT_PLL_PWR_GOOD_LCPLL_MASKD</name>
42897                      <description>Logical and of corresponding request and mask bits.</description>
42898                      <bitRange>[16:16]</bitRange>
42899                      <access>read-only</access>
42900                    </field>
42901                    <field>
42902                      <name>REG_INT_PLL_PWR_GOOD_REF_MASKD</name>
42903                      <description>Logical and of corresponding request and mask bits.</description>
42904                      <bitRange>[17:17]</bitRange>
42905                      <access>read-only</access>
42906                    </field>
42907                    <field>
42908                      <name>REG_INT_PLL_PWR_GOOD_DIG_MASKD</name>
42909                      <description>Logical and of corresponding request and mask bits.</description>
42910                      <bitRange>[18:18]</bitRange>
42911                      <access>read-only</access>
42912                    </field>
42913                  </fields>
42914                </register>
42915                <register>
42916                  <name>TX_AFE_CTRL_0</name>
42917                  <description>Tx AFE control register #0</description>
42918                  <addressOffset>0x60</addressOffset>
42919                  <size>32</size>
42920                  <access>read-write</access>
42921                  <resetValue>0x10000000</resetValue>
42922                  <resetMask>0x3FFFFFF7</resetMask>
42923                  <fields>
42924                    <field>
42925                      <name>REG_TX_AFE_EN</name>
42926                      <description>Enable signal for Tx</description>
42927                      <bitRange>[0:0]</bitRange>
42928                      <access>read-write</access>
42929                    </field>
42930                    <field>
42931                      <name>REG_TX_AFE_DRV_EN</name>
42932                      <description>Enable signal for Tx driver</description>
42933                      <bitRange>[1:1]</bitRange>
42934                      <access>read-write</access>
42935                    </field>
42936                    <field>
42937                      <name>REG_TX_AFE_CML2CMOS_EN</name>
42938                      <description>Enable signal for CML2CMOS clock converter</description>
42939                      <bitRange>[2:2]</bitRange>
42940                      <access>read-write</access>
42941                    </field>
42942                    <field>
42943                      <name>REG_TX_AFE_VCPREG_EN</name>
42944                      <description>voltage regulator charge pump enable</description>
42945                      <bitRange>[4:4]</bitRange>
42946                      <access>read-write</access>
42947                    </field>
42948                    <field>
42949                      <name>REG_TX_AFE_VCPREG_SEL</name>
42950                      <description>charge pump output voltage selection</description>
42951                      <bitRange>[8:5]</bitRange>
42952                      <access>read-write</access>
42953                    </field>
42954                    <field>
42955                      <name>REG_TX_AFE_CPCLK_SEL</name>
42956                      <description>charge pump clock frequency selection</description>
42957                      <bitRange>[9:9]</bitRange>
42958                      <access>read-write</access>
42959                    </field>
42960                    <field>
42961                      <name>REG_TX_AFE_VREG_CLK_EN</name>
42962                      <description>clock regulator enable</description>
42963                      <bitRange>[10:10]</bitRange>
42964                      <access>read-write</access>
42965                    </field>
42966                    <field>
42967                      <name>REG_TX_AFE_VREG_CLK_SEL</name>
42968                      <description>clock regulator output voltage selection</description>
42969                      <bitRange>[14:11]</bitRange>
42970                      <access>read-write</access>
42971                    </field>
42972                    <field>
42973                      <name>REG_TX_AFE_VREG_DRV_EN</name>
42974                      <description>Driver regulator enable</description>
42975                      <bitRange>[15:15]</bitRange>
42976                      <access>read-write</access>
42977                    </field>
42978                    <field>
42979                      <name>REG_TX_AFE_VREG_DRV_SEL</name>
42980                      <description>Driver regulator output voltage selection</description>
42981                      <bitRange>[19:16]</bitRange>
42982                      <access>read-write</access>
42983                    </field>
42984                    <field>
42985                      <name>REG_TX_AFE_TX_PULL_DN</name>
42986                      <description>Control bit to make txp/n pads low</description>
42987                      <bitRange>[20:20]</bitRange>
42988                      <access>read-write</access>
42989                    </field>
42990                    <field>
42991                      <name>REG_TX_AFE_TX_LOOPBK_EN</name>
42992                      <description>Analog Serial Loopback Enable</description>
42993                      <bitRange>[21:21]</bitRange>
42994                      <access>read-write</access>
42995                    </field>
42996                    <field>
42997                      <name>REG_TX_AFE_TX_DCD_CTRL</name>
42998                      <description>Duty cycle control for internal high speed clock</description>
42999                      <bitRange>[25:22]</bitRange>
43000                      <access>read-write</access>
43001                    </field>
43002                    <field>
43003                      <name>REG_TX_AFE_TX_DETECTRX_TRIM</name>
43004                      <description>Enable receiver detection threshold selection</description>
43005                      <bitRange>[27:26]</bitRange>
43006                      <access>read-write</access>
43007                    </field>
43008                    <field>
43009                      <name>REG_TX_AFE_TX_ELECIDLE_DRV</name>
43010                      <description>Electricle idle driver stregnth control
4301100: Hi-Z
4301201: weak drive strength (default)
4301310: Moderate drive strength
4301411: strongest drive strength</description>
43015                      <bitRange>[29:28]</bitRange>
43016                      <access>read-write</access>
43017                    </field>
43018                  </fields>
43019                </register>
43020                <register>
43021                  <name>TX_AFE_CTRL_1</name>
43022                  <description>Tx AFE control register #1</description>
43023                  <addressOffset>0x64</addressOffset>
43024                  <size>32</size>
43025                  <access>read-write</access>
43026                  <resetValue>0x0</resetValue>
43027                  <resetMask>0x7FFBF</resetMask>
43028                  <fields>
43029                    <field>
43030                      <name>REG_TX_AFE_TX_ICAL_TRIM</name>
43031                      <description>Input current  trim for output Impedance calibration</description>
43032                      <bitRange>[5:0]</bitRange>
43033                      <access>read-write</access>
43034                    </field>
43035                    <field>
43036                      <name>REG_TX_AFE_BURNIN_EN</name>
43037                      <description>burnin enable for internal regulator</description>
43038                      <bitRange>[7:7]</bitRange>
43039                      <access>read-write</access>
43040                    </field>
43041                    <field>
43042                      <name>REG_TX_AFE_TX_ADFT_EN</name>
43043                      <description>ADFT enable</description>
43044                      <bitRange>[8:8]</bitRange>
43045                      <access>read-write</access>
43046                    </field>
43047                    <field>
43048                      <name>REG_TX_AFE_TX_ADFT</name>
43049                      <description>TX adft control</description>
43050                      <bitRange>[13:9]</bitRange>
43051                      <access>read-write</access>
43052                    </field>
43053                    <field>
43054                      <name>REG_TX_AFE_TX_DDFT</name>
43055                      <description>TX ddft control</description>
43056                      <bitRange>[18:14]</bitRange>
43057                      <access>read-write</access>
43058                    </field>
43059                  </fields>
43060                </register>
43061                <register>
43062                  <name>TX_AFE_PULL_UP_CNT</name>
43063                  <description>Tx AFE Tx pull-up wait counter</description>
43064                  <addressOffset>0x68</addressOffset>
43065                  <size>32</size>
43066                  <access>read-write</access>
43067                  <resetValue>0x9D3F</resetValue>
43068                  <resetMask>0xFFFF</resetMask>
43069                  <fields>
43070                    <field>
43071                      <name>REG_TX_AFE_TX_PULL_UP_CNT_GEN1</name>
43072                      <description>tx_pull_up wait counter (default is 63, 0x3F), 0.5us target</description>
43073                      <bitRange>[7:0]</bitRange>
43074                      <access>read-write</access>
43075                    </field>
43076                    <field>
43077                      <name>REG_TX_AFE_TX_PULL_UP_CNT_GEN2</name>
43078                      <description>tx_pull_up wait counter (default is 157, 0x9D), 0.5us target</description>
43079                      <bitRange>[15:8]</bitRange>
43080                      <access>read-write</access>
43081                    </field>
43082                  </fields>
43083                </register>
43084                <register>
43085                  <name>TX_AFE_RXDETECT_CNT</name>
43086                  <description>Tx AFE TxDetectRx wait counter</description>
43087                  <addressOffset>0x6C</addressOffset>
43088                  <size>32</size>
43089                  <access>read-write</access>
43090                  <resetValue>0x139007D</resetValue>
43091                  <resetMask>0xFFFFFFFF</resetMask>
43092                  <fields>
43093                    <field>
43094                      <name>REG_TX_AFE_TX_RXDETECT_CNT_GEN1</name>
43095                      <description>TxDetectRx wait counter (default is 125, 0x7D) , 1us target</description>
43096                      <bitRange>[15:0]</bitRange>
43097                      <access>read-write</access>
43098                    </field>
43099                    <field>
43100                      <name>REG_TX_AFE_TX_RXDETECT_CNT_GEN2</name>
43101                      <description>TxDetectRx wait counter (default is 313, 0x139), 1us target</description>
43102                      <bitRange>[31:16]</bitRange>
43103                      <access>read-write</access>
43104                    </field>
43105                  </fields>
43106                </register>
43107                <register>
43108                  <name>TX_AFE_OVERRIDE_0</name>
43109                  <description>Tx AFE override 0 register</description>
43110                  <addressOffset>0x70</addressOffset>
43111                  <size>32</size>
43112                  <access>read-write</access>
43113                  <resetValue>0x0</resetValue>
43114                  <resetMask>0x3FFF3F</resetMask>
43115                  <fields>
43116                    <field>
43117                      <name>REG_TX_AFE_TX_ENABLE_OVRD_EN</name>
43118                      <description>Transmit Enable control
43119    0 - Trnsmitter disabled
43120    1 - Trnsmitter enabled</description>
43121                      <bitRange>[0:0]</bitRange>
43122                      <access>read-write</access>
43123                    </field>
43124                    <field>
43125                      <name>REG_TX_AFE_TX_ENABLE_OVRD_VALUE</name>
43126                      <description>Transmit Enable control
43127    0 - Trnsmitter disabled
43128    1 - Trnsmitter enabled</description>
43129                      <bitRange>[1:1]</bitRange>
43130                      <access>read-write</access>
43131                    </field>
43132                    <field>
43133                      <name>REG_TX_AFE_TX_SER_EN_OVRD_EN</name>
43134                      <description>Serializer Enable control
43135    0 - Serializer disabled
43136    1 - Serilizer enabled</description>
43137                      <bitRange>[2:2]</bitRange>
43138                      <access>read-write</access>
43139                    </field>
43140                    <field>
43141                      <name>REG_TX_AFE_TX_SER_EN_OVRD_VALUE</name>
43142                      <description>Serializer Enable control
43143    0 - Serializer disabled
43144    1 - Serilizer enabled</description>
43145                      <bitRange>[3:3]</bitRange>
43146                      <access>read-write</access>
43147                    </field>
43148                    <field>
43149                      <name>REG_TX_AFE_TX_HSCLK_DRV_EN_OVRD_EN</name>
43150                      <description>Enable signal for high speed clock that drives the final driver</description>
43151                      <bitRange>[4:4]</bitRange>
43152                      <access>read-write</access>
43153                    </field>
43154                    <field>
43155                      <name>REG_TX_AFE_TX_HSCLK_DRV_EN_OVRD_VALUE</name>
43156                      <description>Enable signal for high speed clock that drives the final driver</description>
43157                      <bitRange>[5:5]</bitRange>
43158                      <access>read-write</access>
43159                    </field>
43160                    <field>
43161                      <name>REG_TX_AFE_TX_DETECTRX_OVRD_EN</name>
43162                      <description>Enable receiver detection</description>
43163                      <bitRange>[8:8]</bitRange>
43164                      <access>read-write</access>
43165                    </field>
43166                    <field>
43167                      <name>REG_TX_AFE_TX_DETECTRX_OVRD_VALUE</name>
43168                      <description>Enable receiver detection</description>
43169                      <bitRange>[9:9]</bitRange>
43170                      <access>read-write</access>
43171                    </field>
43172                    <field>
43173                      <name>REG_TX_AFE_TX_ELECIDLE_OVRD_EN</name>
43174                      <description>Enable TX electrical idle</description>
43175                      <bitRange>[10:10]</bitRange>
43176                      <access>read-write</access>
43177                    </field>
43178                    <field>
43179                      <name>REG_TX_AFE_TX_ELECIDLE_OVRD_VALUE</name>
43180                      <description>Enable TX electrical idle</description>
43181                      <bitRange>[11:11]</bitRange>
43182                      <access>read-write</access>
43183                    </field>
43184                    <field>
43185                      <name>REG_TX_AFE_TX_LFPS_OVRD_EN</name>
43186                      <description>Enable LFPS signaling</description>
43187                      <bitRange>[12:12]</bitRange>
43188                      <access>read-write</access>
43189                    </field>
43190                    <field>
43191                      <name>REG_TX_AFE_TX_LFPS_OVRD_VALUE</name>
43192                      <description>Enable LFPS signaling</description>
43193                      <bitRange>[13:13]</bitRange>
43194                      <access>read-write</access>
43195                    </field>
43196                    <field>
43197                      <name>REG_TX_AFE_TX_ZCAL_OVRD_EN</name>
43198                      <description>Automatic impedance calibration enable</description>
43199                      <bitRange>[14:14]</bitRange>
43200                      <access>read-write</access>
43201                    </field>
43202                    <field>
43203                      <name>REG_TX_AFE_TX_ZCAL_OVRD_VALUE</name>
43204                      <description>Automatic impedance calibration enable</description>
43205                      <bitRange>[15:15]</bitRange>
43206                      <access>read-write</access>
43207                    </field>
43208                    <field>
43209                      <name>REG_TX_AFE_TX_ZTRIM_OVRD_EN</name>
43210                      <description>Automatic impedance calibration trim bits</description>
43211                      <bitRange>[16:16]</bitRange>
43212                      <access>read-write</access>
43213                    </field>
43214                    <field>
43215                      <name>REG_TX_AFE_TX_ZTRIM_OVRD_VALUE</name>
43216                      <description>Automatic impedance calibration trim bits</description>
43217                      <bitRange>[21:17]</bitRange>
43218                      <access>read-write</access>
43219                    </field>
43220                  </fields>
43221                </register>
43222                <register>
43223                  <name>TX_AFE_OVERRIDE_1</name>
43224                  <description>Tx AFE override 0 register</description>
43225                  <addressOffset>0x74</addressOffset>
43226                  <size>32</size>
43227                  <access>read-write</access>
43228                  <resetValue>0x0</resetValue>
43229                  <resetMask>0x3FFF1</resetMask>
43230                  <fields>
43231                    <field>
43232                      <name>REG_TX_AFE_TX_CTRL_IN_OVRD_EN</name>
43233                      <description>Control bits to configure TX slices</description>
43234                      <bitRange>[0:0]</bitRange>
43235                      <access>read-write</access>
43236                    </field>
43237                    <field>
43238                      <name>REG_TX_AFE_TX_CTRL_IN_OVRD_VALUE</name>
43239                      <description>Control bits to configure TX slices</description>
43240                      <bitRange>[11:4]</bitRange>
43241                      <access>read-write</access>
43242                    </field>
43243                    <field>
43244                      <name>REG_TX_AFE_TX_SHIFT_CLK_OVRD_EN</name>
43245                      <description>shift clock input for tx_ctrl_in&lt;7:0&gt; input</description>
43246                      <bitRange>[12:12]</bitRange>
43247                      <access>read-write</access>
43248                    </field>
43249                    <field>
43250                      <name>REG_TX_AFE_TX_SHIFT_CLK_OVRD_VALUE</name>
43251                      <description>shift clock input for tx_ctrl_in&lt;7:0&gt; input</description>
43252                      <bitRange>[13:13]</bitRange>
43253                      <access>read-write</access>
43254                    </field>
43255                    <field>
43256                      <name>REG_TX_AFE_TX_LOAD_CLK_OVRD_EN</name>
43257                      <description>Load clock input for tx_ctrl_in&lt;7:0&gt; input</description>
43258                      <bitRange>[14:14]</bitRange>
43259                      <access>read-write</access>
43260                    </field>
43261                    <field>
43262                      <name>REG_TX_AFE_TX_LOAD_CLK_OVRD_VALUE</name>
43263                      <description>Load clock input for tx_ctrl_in&lt;7:0&gt; input</description>
43264                      <bitRange>[15:15]</bitRange>
43265                      <access>read-write</access>
43266                    </field>
43267                    <field>
43268                      <name>REG_TX_AFE_TX_PULL_UP_OVRD_EN</name>
43269                      <description>Control bit to make txp/n pads high</description>
43270                      <bitRange>[16:16]</bitRange>
43271                      <access>read-write</access>
43272                    </field>
43273                    <field>
43274                      <name>REG_TX_AFE_TX_PULL_UP_OVRD_VALUE</name>
43275                      <description>Control bit to make txp/n pads high</description>
43276                      <bitRange>[17:17]</bitRange>
43277                      <access>read-write</access>
43278                    </field>
43279                  </fields>
43280                </register>
43281                <register>
43282                  <name>TX_AFE_DEBUG</name>
43283                  <description>Tx AFE debug register</description>
43284                  <addressOffset>0x78</addressOffset>
43285                  <size>32</size>
43286                  <access>read-only</access>
43287                  <resetValue>0x0</resetValue>
43288                  <resetMask>0x3</resetMask>
43289                  <fields>
43290                    <field>
43291                      <name>REG_TX_AFE_DDFT_OUT1</name>
43292                      <description>DDFT output</description>
43293                      <bitRange>[0:0]</bitRange>
43294                      <access>read-only</access>
43295                    </field>
43296                    <field>
43297                      <name>REG_TX_AFE_DDFT_OUT2</name>
43298                      <description>DDFT output</description>
43299                      <bitRange>[1:1]</bitRange>
43300                      <access>read-only</access>
43301                    </field>
43302                  </fields>
43303                </register>
43304                <register>
43305                  <name>TX_AFE_STATUS</name>
43306                  <description>Tx AFE status register</description>
43307                  <addressOffset>0x7C</addressOffset>
43308                  <size>32</size>
43309                  <access>read-only</access>
43310                  <resetValue>0x0</resetValue>
43311                  <resetMask>0x600F</resetMask>
43312                  <fields>
43313                    <field>
43314                      <name>REG_TX_ZCAL_EXCEED_INC</name>
43315                      <description>impedance calibration comperator exceed indicate when increment mode</description>
43316                      <bitRange>[0:0]</bitRange>
43317                      <access>read-only</access>
43318                    </field>
43319                    <field>
43320                      <name>REG_TX_ZCAL_EXCEED_DEC</name>
43321                      <description>impedance calibration comperator exceed indicate when decrement mode</description>
43322                      <bitRange>[1:1]</bitRange>
43323                      <access>read-only</access>
43324                    </field>
43325                    <field>
43326                      <name>REG_TX_ZCAL_COMP_OUT</name>
43327                      <description>Automatic impedance calibration comparator output (stuck check for debug)</description>
43328                      <bitRange>[2:2]</bitRange>
43329                      <access>read-only</access>
43330                    </field>
43331                    <field>
43332                      <name>REG_TX_DETECTRX_OUT</name>
43333                      <description>Exteranl Rx detect output</description>
43334                      <bitRange>[3:3]</bitRange>
43335                      <access>read-only</access>
43336                    </field>
43337                    <field>
43338                      <name>REG_TX_STATUS_TBD</name>
43339                      <description>TBD</description>
43340                      <bitRange>[14:13]</bitRange>
43341                      <access>read-only</access>
43342                    </field>
43343                  </fields>
43344                </register>
43345                <register>
43346                  <name>TX_AFE_ZTRIM</name>
43347                  <description>Tx AFE impedance calibration register</description>
43348                  <addressOffset>0x84</addressOffset>
43349                  <size>32</size>
43350                  <access>read-write</access>
43351                  <resetValue>0x0</resetValue>
43352                  <resetMask>0x1F1F</resetMask>
43353                  <fields>
43354                    <field>
43355                      <name>REG_TX_ZCAL_EN</name>
43356                      <description>Impedance calibration enable</description>
43357                      <bitRange>[0:0]</bitRange>
43358                      <access>read-write</access>
43359                    </field>
43360                    <field>
43361                      <name>REG_TX_ZCAL_MODE</name>
43362                      <description>Impedance calibration mode, TBD</description>
43363                      <bitRange>[1:1]</bitRange>
43364                      <access>read-write</access>
43365                    </field>
43366                    <field>
43367                      <name>REG_TX_COMP_WAIT</name>
43368                      <description>impedance calibration comperator wait delay
433690: 10ns (default)
433701: 20ns
433712: 30ns
433723: 40ns</description>
43373                      <bitRange>[3:2]</bitRange>
43374                      <access>read-write</access>
43375                    </field>
43376                    <field>
43377                      <name>REG_TX_ZCAL_FORCE_EN</name>
43378                      <description>Impedance calibration trim force enable</description>
43379                      <bitRange>[4:4]</bitRange>
43380                      <access>read-write</access>
43381                    </field>
43382                    <field>
43383                      <name>REG_TX_ZCAL_FORCE</name>
43384                      <description>Impedance calibration trim force</description>
43385                      <bitRange>[12:8]</bitRange>
43386                      <access>read-write</access>
43387                    </field>
43388                  </fields>
43389                </register>
43390                <register>
43391                  <name>TX_AFE_ZTRIM_RESULT</name>
43392                  <description>Tx AFE impedance calibration result register</description>
43393                  <addressOffset>0x88</addressOffset>
43394                  <size>32</size>
43395                  <access>read-only</access>
43396                  <resetValue>0x0</resetValue>
43397                  <resetMask>0x1F</resetMask>
43398                  <fields>
43399                    <field>
43400                      <name>REG_TX_ZTRIM</name>
43401                      <description>Impedance calibration trim result</description>
43402                      <bitRange>[4:0]</bitRange>
43403                      <access>read-only</access>
43404                    </field>
43405                  </fields>
43406                </register>
43407                <register>
43408                  <name>TX_AFE_ZTRIM_NVALUES</name>
43409                  <description>Tx AFE impedance calibration Nmain, Npre, Npost, Nvswing register</description>
43410                  <addressOffset>0x8C</addressOffset>
43411                  <size>32</size>
43412                  <access>read-write</access>
43413                  <resetValue>0x0</resetValue>
43414                  <resetMask>0x3F3F3F3F</resetMask>
43415                  <fields>
43416                    <field>
43417                      <name>REG_TX_ZCAL_NMAIN</name>
43418                      <description>Impedance calibration Nmain[5:0] for debug</description>
43419                      <bitRange>[5:0]</bitRange>
43420                      <access>read-write</access>
43421                    </field>
43422                    <field>
43423                      <name>REG_TX_ZCAL_NPRE</name>
43424                      <description>Impedance calibration Npre[5:0] for debug</description>
43425                      <bitRange>[13:8]</bitRange>
43426                      <access>read-write</access>
43427                    </field>
43428                    <field>
43429                      <name>REG_TX_ZCAL_NPOST</name>
43430                      <description>Impedance calibration Npost[5:0] for debug</description>
43431                      <bitRange>[21:16]</bitRange>
43432                      <access>read-write</access>
43433                    </field>
43434                    <field>
43435                      <name>REG_TX_ZCAL_NVSWING</name>
43436                      <description>Impedance calibration Nvswing[5:0] for debug</description>
43437                      <bitRange>[29:24]</bitRange>
43438                      <access>read-write</access>
43439                    </field>
43440                  </fields>
43441                </register>
43442                <register>
43443                  <name>TX_AFE_CFG</name>
43444                  <description>Tx AFE configuration control register</description>
43445                  <addressOffset>0x90</addressOffset>
43446                  <size>32</size>
43447                  <access>read-write</access>
43448                  <resetValue>0x0</resetValue>
43449                  <resetMask>0x1</resetMask>
43450                  <fields>
43451                    <field>
43452                      <name>REG_TX_CFG_WRITE_DONE</name>
43453                      <description>Tx AFE config shift register write done.</description>
43454                      <bitRange>[0:0]</bitRange>
43455                      <access>read-write</access>
43456                    </field>
43457                  </fields>
43458                </register>
43459                <register>
43460                  <name>TX_AFE_CFG_SFT_W_0</name>
43461                  <description>Tx AFE configuration control shift write register #0</description>
43462                  <addressOffset>0x94</addressOffset>
43463                  <size>32</size>
43464                  <access>read-write</access>
43465                  <resetValue>0x3FFFFF</resetValue>
43466                  <resetMask>0x3FFFFF</resetMask>
43467                  <fields>
43468                    <field>
43469                      <name>REG_TX_CFG_SFT_W_0</name>
43470                      <description>Tx AFE config shift register write</description>
43471                      <bitRange>[21:0]</bitRange>
43472                      <access>read-write</access>
43473                    </field>
43474                  </fields>
43475                </register>
43476                <register>
43477                  <name>TX_AFE_CFG_SFT_W_1</name>
43478                  <description>Tx AFE configuration control shift write register #1</description>
43479                  <addressOffset>0x98</addressOffset>
43480                  <size>32</size>
43481                  <access>read-write</access>
43482                  <resetValue>0x3FFFFF</resetValue>
43483                  <resetMask>0x3FFFFF</resetMask>
43484                  <fields>
43485                    <field>
43486                      <name>REG_TX_CFG_SFT_W_1</name>
43487                      <description>Tx AFE config shift register write</description>
43488                      <bitRange>[21:0]</bitRange>
43489                      <access>read-write</access>
43490                    </field>
43491                  </fields>
43492                </register>
43493                <register>
43494                  <name>TX_AFE_CFG_SFT_W_2</name>
43495                  <description>Tx AFE configuration control shift write register #2</description>
43496                  <addressOffset>0x9C</addressOffset>
43497                  <size>32</size>
43498                  <access>read-write</access>
43499                  <resetValue>0x3FFFFF</resetValue>
43500                  <resetMask>0x3FFFFF</resetMask>
43501                  <fields>
43502                    <field>
43503                      <name>REG_TX_CFG_SFT_W_2</name>
43504                      <description>Tx AFE config shift register write</description>
43505                      <bitRange>[21:0]</bitRange>
43506                      <access>read-write</access>
43507                    </field>
43508                  </fields>
43509                </register>
43510                <register>
43511                  <name>TX_AFE_CFG_SFT_W_3</name>
43512                  <description>Tx AFE configuration control shift write register #3</description>
43513                  <addressOffset>0xA0</addressOffset>
43514                  <size>32</size>
43515                  <access>read-write</access>
43516                  <resetValue>0x3FFFFF</resetValue>
43517                  <resetMask>0x3FFFFF</resetMask>
43518                  <fields>
43519                    <field>
43520                      <name>REG_TX_CFG_SFT_W_3</name>
43521                      <description>Tx AFE config shift register write</description>
43522                      <bitRange>[21:0]</bitRange>
43523                      <access>read-write</access>
43524                    </field>
43525                  </fields>
43526                </register>
43527                <register>
43528                  <name>TX_AFE_CFG_SFT_W_4</name>
43529                  <description>Tx AFE configuration control shift write register #4</description>
43530                  <addressOffset>0xA4</addressOffset>
43531                  <size>32</size>
43532                  <access>read-write</access>
43533                  <resetValue>0x3FFFFF</resetValue>
43534                  <resetMask>0x3FFFFF</resetMask>
43535                  <fields>
43536                    <field>
43537                      <name>REG_TX_CFG_SFT_W_4</name>
43538                      <description>Tx AFE config shift register write</description>
43539                      <bitRange>[21:0]</bitRange>
43540                      <access>read-write</access>
43541                    </field>
43542                  </fields>
43543                </register>
43544                <register>
43545                  <name>TX_AFE_CFG_SFT_W_5</name>
43546                  <description>Tx AFE configuration control shift write register #5</description>
43547                  <addressOffset>0xA8</addressOffset>
43548                  <size>32</size>
43549                  <access>read-write</access>
43550                  <resetValue>0x3FFFFF</resetValue>
43551                  <resetMask>0x3FFFFF</resetMask>
43552                  <fields>
43553                    <field>
43554                      <name>REG_TX_CFG_SFT_W_5</name>
43555                      <description>Tx AFE config shift register write</description>
43556                      <bitRange>[21:0]</bitRange>
43557                      <access>read-write</access>
43558                    </field>
43559                  </fields>
43560                </register>
43561                <register>
43562                  <name>TX_AFE_CFG_SFT_W_6</name>
43563                  <description>Tx AFE configuration control shift write register #6</description>
43564                  <addressOffset>0xAC</addressOffset>
43565                  <size>32</size>
43566                  <access>read-write</access>
43567                  <resetValue>0x3FFFFF</resetValue>
43568                  <resetMask>0x3FFFFF</resetMask>
43569                  <fields>
43570                    <field>
43571                      <name>REG_TX_CFG_SFT_W_6</name>
43572                      <description>Tx AFE config shift register write</description>
43573                      <bitRange>[21:0]</bitRange>
43574                      <access>read-write</access>
43575                    </field>
43576                  </fields>
43577                </register>
43578                <register>
43579                  <name>TX_AFE_CFG_SFT_W_7</name>
43580                  <description>Tx AFE configuration control shift write register #7</description>
43581                  <addressOffset>0xB0</addressOffset>
43582                  <size>32</size>
43583                  <access>read-write</access>
43584                  <resetValue>0x3FFFFF</resetValue>
43585                  <resetMask>0x3FFFFF</resetMask>
43586                  <fields>
43587                    <field>
43588                      <name>REG_TX_CFG_SFT_W_7</name>
43589                      <description>Tx AFE config shift register write</description>
43590                      <bitRange>[21:0]</bitRange>
43591                      <access>read-write</access>
43592                    </field>
43593                  </fields>
43594                </register>
43595                <register>
43596                  <name>ADC_0</name>
43597                  <description>Analog to Digital Converter register #0</description>
43598                  <addressOffset>0xC0</addressOffset>
43599                  <size>32</size>
43600                  <access>read-write</access>
43601                  <resetValue>0x0</resetValue>
43602                  <resetMask>0xF37FFF</resetMask>
43603                  <fields>
43604                    <field>
43605                      <name>REG_ADC_FUNC_ADC_DAC_CNTRL</name>
43606                      <description>ADC function control, This can be controlled via SAR Logic (SAR_EN) or via direct config register.</description>
43607                      <bitRange>[7:0]</bitRange>
43608                      <access>read-write</access>
43609                    </field>
43610                    <field>
43611                      <name>REG_ADC_TRIMS_TRIM_VREG_SEL</name>
43612                      <description>ADC Trim</description>
43613                      <bitRange>[11:8]</bitRange>
43614                      <access>read-write</access>
43615                    </field>
43616                    <field>
43617                      <name>REG_ADC_CTRL_ADC_VSEL</name>
43618                      <description>ADC</description>
43619                      <bitRange>[14:12]</bitRange>
43620                      <access>read-write</access>
43621                    </field>
43622                    <field>
43623                      <name>REG_ADC_CTRL_ADC_VREF_DAC_SEL</name>
43624                      <description>ADC</description>
43625                      <bitRange>[17:16]</bitRange>
43626                      <access>read-write</access>
43627                    </field>
43628                    <field>
43629                      <name>REG_ADC_CTRL_ADC_ISO_N</name>
43630                      <description>ADC</description>
43631                      <bitRange>[20:20]</bitRange>
43632                      <access>read-write</access>
43633                    </field>
43634                    <field>
43635                      <name>REG_ADC_CTRL_ADC_PD_LV</name>
43636                      <description>ADC</description>
43637                      <bitRange>[21:21]</bitRange>
43638                      <access>read-write</access>
43639                    </field>
43640                    <field>
43641                      <name>REG_ADC_CTRL_ADC_DFT_MUXSEL</name>
43642                      <description>ADC</description>
43643                      <bitRange>[22:22]</bitRange>
43644                      <access>read-write</access>
43645                    </field>
43646                    <field>
43647                      <name>REG_ADC_CTRL_ADC_EN_LDO</name>
43648                      <description>ADC</description>
43649                      <bitRange>[23:23]</bitRange>
43650                      <access>read-write</access>
43651                    </field>
43652                  </fields>
43653                </register>
43654                <register>
43655                  <name>ADC_STATUS</name>
43656                  <description>Analog to Digital Converter status register</description>
43657                  <addressOffset>0xC4</addressOffset>
43658                  <size>32</size>
43659                  <access>read-only</access>
43660                  <resetValue>0x0</resetValue>
43661                  <resetMask>0x1</resetMask>
43662                  <fields>
43663                    <field>
43664                      <name>REG_ADC_COMP_OUT_FX</name>
43665                      <description>ADC status</description>
43666                      <bitRange>[0:0]</bitRange>
43667                      <access>read-only</access>
43668                    </field>
43669                  </fields>
43670                </register>
43671              </cluster>
43672              <cluster>
43673                <name>USB40PHY_RX</name>
43674                <description>PHY Rx registers</description>
43675                <addressOffset>0x00000800</addressOffset>
43676                <register>
43677                  <name>RX_SDM_CFG0</name>
43678                  <description>Sigma-Delta Modulator (SDM) Configuration</description>
43679                  <addressOffset>0x0</addressOffset>
43680                  <size>16</size>
43681                  <access>read-write</access>
43682                  <resetValue>0x0</resetValue>
43683                  <resetMask>0xFF</resetMask>
43684                  <fields>
43685                    <field>
43686                      <name>DIVF_INTEGER</name>
43687                      <description>Feedback Divider Ratio integer vlaue (not required if SSM is present)</description>
43688                      <bitRange>[7:0]</bitRange>
43689                      <access>read-write</access>
43690                    </field>
43691                  </fields>
43692                </register>
43693                <register>
43694                  <name>RX_SDM_CFG1</name>
43695                  <description>Sigma-Delta Modulator (SDM) Configuration</description>
43696                  <addressOffset>0x4</addressOffset>
43697                  <size>16</size>
43698                  <access>read-write</access>
43699                  <resetValue>0x0</resetValue>
43700                  <resetMask>0xFFFF</resetMask>
43701                  <fields>
43702                    <field>
43703                      <name>DIVF_FRAC_MSB</name>
43704                      <description>Feedback Divider Ratio fractional vlaue (not required if SSM is used)</description>
43705                      <bitRange>[15:0]</bitRange>
43706                      <access>read-write</access>
43707                    </field>
43708                  </fields>
43709                </register>
43710                <register>
43711                  <name>RX_SDM_CFG2</name>
43712                  <description>Sigma-Delta Modulator (SDM) Configuration</description>
43713                  <addressOffset>0x8</addressOffset>
43714                  <size>16</size>
43715                  <access>read-write</access>
43716                  <resetValue>0x0</resetValue>
43717                  <resetMask>0x3</resetMask>
43718                  <fields>
43719                    <field>
43720                      <name>DIVF_FRAC_LSB</name>
43721                      <description>Feedback Divider Ratio fractional vlaue (not required if SSM is used)</description>
43722                      <bitRange>[1:0]</bitRange>
43723                      <access>read-write</access>
43724                    </field>
43725                  </fields>
43726                </register>
43727                <register>
43728                  <name>RX_SDM_CFG3</name>
43729                  <description>Sigma-Delta Modulator (SDM) Configuration</description>
43730                  <addressOffset>0xC</addressOffset>
43731                  <size>16</size>
43732                  <access>read-write</access>
43733                  <resetValue>0x0</resetValue>
43734                  <resetMask>0x1F</resetMask>
43735                  <fields>
43736                    <field>
43737                      <name>SDM_ENABLE</name>
43738                      <description>Sigma-Delta modulator enable, (active low power down), SSM will be down too</description>
43739                      <bitRange>[0:0]</bitRange>
43740                      <access>read-write</access>
43741                    </field>
43742                    <field>
43743                      <name>DITHER_EN</name>
43744                      <description>Sigma-Delta Modulator dither enable</description>
43745                      <bitRange>[1:1]</bitRange>
43746                      <access>read-write</access>
43747                    </field>
43748                    <field>
43749                      <name>DITHER_GAIN</name>
43750                      <description>Sigma-Delta Modulator dither gain, specifies number of dither bits</description>
43751                      <bitRange>[4:2]</bitRange>
43752                      <access>read-write</access>
43753                    </field>
43754                  </fields>
43755                </register>
43756                <register>
43757                  <name>RX_DFE_CFG0</name>
43758                  <description>DFE FSM (DFE) Configuration</description>
43759                  <addressOffset>0x10</addressOffset>
43760                  <size>16</size>
43761                  <access>read-write</access>
43762                  <resetValue>0x0</resetValue>
43763                  <resetMask>0xFF9F</resetMask>
43764                  <fields>
43765                    <field>
43766                      <name>OVRD_VGATAP</name>
43767                      <description>VGA tap Coefficient setting for override</description>
43768                      <bitRange>[4:0]</bitRange>
43769                      <access>read-write</access>
43770                    </field>
43771                    <field>
43772                      <name>OVRD_VGATAP_EN</name>
43773                      <description>VGA tap override enable</description>
43774                      <bitRange>[7:7]</bitRange>
43775                      <access>read-write</access>
43776                    </field>
43777                    <field>
43778                      <name>OVRD_DFETAP1</name>
43779                      <description>DFE tap 1 Coefficient setting for overrid</description>
43780                      <bitRange>[14:8]</bitRange>
43781                      <access>read-write</access>
43782                    </field>
43783                    <field>
43784                      <name>OVRD_DFETAP1_EN</name>
43785                      <description>DFE tap 1 override enable</description>
43786                      <bitRange>[15:15]</bitRange>
43787                      <access>read-write</access>
43788                    </field>
43789                  </fields>
43790                </register>
43791                <register>
43792                  <name>RX_DFE_CFG1</name>
43793                  <description>DFE FSM (DFE) Configuration</description>
43794                  <addressOffset>0x14</addressOffset>
43795                  <size>16</size>
43796                  <access>read-write</access>
43797                  <resetValue>0x0</resetValue>
43798                  <resetMask>0xFFFF</resetMask>
43799                  <fields>
43800                    <field>
43801                      <name>OVRD_DFETAP2</name>
43802                      <description>DFE tap 2 Coefficient setting for overrid</description>
43803                      <bitRange>[6:0]</bitRange>
43804                      <access>read-write</access>
43805                    </field>
43806                    <field>
43807                      <name>OVRD_DFETAP2_EN</name>
43808                      <description>DFE tap 2 override enable</description>
43809                      <bitRange>[7:7]</bitRange>
43810                      <access>read-write</access>
43811                    </field>
43812                    <field>
43813                      <name>OVRD_DFETAP3</name>
43814                      <description>DFE tap 3 Coefficient setting for overrid</description>
43815                      <bitRange>[14:8]</bitRange>
43816                      <access>read-write</access>
43817                    </field>
43818                    <field>
43819                      <name>OVRD_DFETAP3_EN</name>
43820                      <description>DFE tap 3 override enable</description>
43821                      <bitRange>[15:15]</bitRange>
43822                      <access>read-write</access>
43823                    </field>
43824                  </fields>
43825                </register>
43826                <register>
43827                  <name>RX_DFE_CFG2</name>
43828                  <description>DFE FSM (DFE) Configuration</description>
43829                  <addressOffset>0x18</addressOffset>
43830                  <size>16</size>
43831                  <access>read-write</access>
43832                  <resetValue>0x0</resetValue>
43833                  <resetMask>0xFFFF</resetMask>
43834                  <fields>
43835                    <field>
43836                      <name>DFE_SLICEPOINTVALUE</name>
43837                      <description>slice point value in error slicers, positive</description>
43838                      <bitRange>[5:0]</bitRange>
43839                      <access>read-write</access>
43840                    </field>
43841                    <field>
43842                      <name>DFE_SLICEPOINTSIGN1</name>
43843                      <description>1: error slicer 1 has positive slice point; 0: negative</description>
43844                      <bitRange>[6:6]</bitRange>
43845                      <access>read-write</access>
43846                    </field>
43847                    <field>
43848                      <name>DFE_SLICEPOINTSIGN2</name>
43849                      <description>1: error slicer 2 has positive slice point; 0: negative</description>
43850                      <bitRange>[7:7]</bitRange>
43851                      <access>read-write</access>
43852                    </field>
43853                    <field>
43854                      <name>VGA_MU</name>
43855                      <description>mu/16 multiplier for VGA tap0 adaptation</description>
43856                      <bitRange>[11:8]</bitRange>
43857                      <access>read-write</access>
43858                    </field>
43859                    <field>
43860                      <name>DFE_MU</name>
43861                      <description>mu/16 multiplier for DFE taps adaptation</description>
43862                      <bitRange>[15:12]</bitRange>
43863                      <access>read-write</access>
43864                    </field>
43865                  </fields>
43866                </register>
43867                <register>
43868                  <name>RX_DFE_CFG3</name>
43869                  <description>DFE FSM (DFE) Configuration</description>
43870                  <addressOffset>0x1C</addressOffset>
43871                  <size>16</size>
43872                  <access>read-write</access>
43873                  <resetValue>0x0</resetValue>
43874                  <resetMask>0x7FF</resetMask>
43875                  <fields>
43876                    <field>
43877                      <name>DFE_BAL_AVRG</name>
43878                      <description># of cycles averaging tap updates</description>
43879                      <bitRange>[2:0]</bitRange>
43880                      <access>read-write</access>
43881                    </field>
43882                    <field>
43883                      <name>DFE_BALANCE_SCALE</name>
43884                      <description>Scaling for DFE balances when subtracting error/non_error</description>
43885                      <bitRange>[4:3]</bitRange>
43886                      <access>read-write</access>
43887                    </field>
43888                    <field>
43889                      <name>VGA_POLARITY</name>
43890                      <description>VGA tap polarity swapping, default 0</description>
43891                      <bitRange>[5:5]</bitRange>
43892                      <access>read-write</access>
43893                    </field>
43894                    <field>
43895                      <name>DFE_POLARITY</name>
43896                      <description>DFE taps polarity swapping, default 0</description>
43897                      <bitRange>[6:6]</bitRange>
43898                      <access>read-write</access>
43899                    </field>
43900                    <field>
43901                      <name>VGA_ADAPT_EN</name>
43902                      <description>VGA adaptation enable, active high</description>
43903                      <bitRange>[7:7]</bitRange>
43904                      <access>read-write</access>
43905                    </field>
43906                    <field>
43907                      <name>DFE_ENABLE</name>
43908                      <description>DFE adaptation enable, active high</description>
43909                      <bitRange>[8:8]</bitRange>
43910                      <access>read-write</access>
43911                    </field>
43912                    <field>
43913                      <name>VGA_FREEZE</name>
43914                      <description>freeze VGA adaptation with present values</description>
43915                      <bitRange>[9:9]</bitRange>
43916                      <access>read-write</access>
43917                    </field>
43918                    <field>
43919                      <name>DFE_FREEZE</name>
43920                      <description>freeze DFE adaptation with all present values</description>
43921                      <bitRange>[10:10]</bitRange>
43922                      <access>read-write</access>
43923                    </field>
43924                  </fields>
43925                </register>
43926                <register>
43927                  <name>RX_DFE_STAT0</name>
43928                  <description>DFE FSM (DFE) status</description>
43929                  <addressOffset>0x20</addressOffset>
43930                  <size>16</size>
43931                  <access>read-only</access>
43932                  <resetValue>0x0</resetValue>
43933                  <resetMask>0x7F1F</resetMask>
43934                  <fields>
43935                    <field>
43936                      <name>VGATAP</name>
43937                      <description>VGA tap, gain control (Note, Dynamic async to CSR clock, need sync or being frozen for read)</description>
43938                      <bitRange>[4:0]</bitRange>
43939                      <access>read-only</access>
43940                    </field>
43941                    <field>
43942                      <name>DFETAP1</name>
43943                      <description>DFE tap 1 DAC input (Note, Dynamic async to CSR clock, need sync or being frozen for read)</description>
43944                      <bitRange>[14:8]</bitRange>
43945                      <access>read-only</access>
43946                    </field>
43947                  </fields>
43948                </register>
43949                <register>
43950                  <name>RX_DFE_STAT1</name>
43951                  <description>DFE FSM (DFE) status</description>
43952                  <addressOffset>0x24</addressOffset>
43953                  <size>16</size>
43954                  <access>read-only</access>
43955                  <resetValue>0x0</resetValue>
43956                  <resetMask>0x7F7F</resetMask>
43957                  <fields>
43958                    <field>
43959                      <name>DFETAP2</name>
43960                      <description>DFE tap 2 DAC input (Note, Dynamic async to CSR clock, need sync or being frozen for read)</description>
43961                      <bitRange>[6:0]</bitRange>
43962                      <access>read-only</access>
43963                    </field>
43964                    <field>
43965                      <name>DFETAP3</name>
43966                      <description>DFE tap 3 DAC input (Note, Dynamic async to CSR clock, need sync or being frozen for read)</description>
43967                      <bitRange>[14:8]</bitRange>
43968                      <access>read-only</access>
43969                    </field>
43970                  </fields>
43971                </register>
43972                <register>
43973                  <name>RX_DFE_STAT2</name>
43974                  <description>DFE FSM (DFE) status</description>
43975                  <addressOffset>0x28</addressOffset>
43976                  <size>16</size>
43977                  <access>read-only</access>
43978                  <resetValue>0x0</resetValue>
43979                  <resetMask>0x7F7F</resetMask>
43980                  <fields>
43981                    <field>
43982                      <name>ERRSLIC1DELTA</name>
43983                      <description>Error slicer 1 offset+(sign)delta</description>
43984                      <bitRange>[6:0]</bitRange>
43985                      <access>read-only</access>
43986                    </field>
43987                    <field>
43988                      <name>ERRSLIC2DELTA</name>
43989                      <description>Error slicer 2 offset+(sign)delta</description>
43990                      <bitRange>[14:8]</bitRange>
43991                      <access>read-only</access>
43992                    </field>
43993                  </fields>
43994                </register>
43995                <register>
43996                  <name>RX_OSA_CFG0</name>
43997                  <description>Offset Calibration FSM (OSA) Configuration</description>
43998                  <addressOffset>0x2C</addressOffset>
43999                  <size>16</size>
44000                  <access>read-write</access>
44001                  <resetValue>0x0</resetValue>
44002                  <resetMask>0xFFFF</resetMask>
44003                  <fields>
44004                    <field>
44005                      <name>OVRD_EDGSLICE1OS</name>
44006                      <description>Edge slicer 1 offset adjustment override</description>
44007                      <bitRange>[6:0]</bitRange>
44008                      <access>read-write</access>
44009                    </field>
44010                    <field>
44011                      <name>OVRD_EDGSLICE1OS_EN</name>
44012                      <description>Edge slicer 1 offset adjustment override enable</description>
44013                      <bitRange>[7:7]</bitRange>
44014                      <access>read-write</access>
44015                    </field>
44016                    <field>
44017                      <name>OVRD_EDGSLICE2OS</name>
44018                      <description>Edge slicer 2 offset adjustment override</description>
44019                      <bitRange>[14:8]</bitRange>
44020                      <access>read-write</access>
44021                    </field>
44022                    <field>
44023                      <name>OVRD_EDGSLICE2OS_EN</name>
44024                      <description>Edge slicer 2 offset adjustment override enable</description>
44025                      <bitRange>[15:15]</bitRange>
44026                      <access>read-write</access>
44027                    </field>
44028                  </fields>
44029                </register>
44030                <register>
44031                  <name>RX_OSA_CFG1</name>
44032                  <description>Offset Calibration FSM (OSA) Configuration</description>
44033                  <addressOffset>0x30</addressOffset>
44034                  <size>16</size>
44035                  <access>read-write</access>
44036                  <resetValue>0x0</resetValue>
44037                  <resetMask>0xFFFF</resetMask>
44038                  <fields>
44039                    <field>
44040                      <name>OVRD_DATSLICE1OS</name>
44041                      <description>Data slicer 1 offset adjustment override</description>
44042                      <bitRange>[6:0]</bitRange>
44043                      <access>read-write</access>
44044                    </field>
44045                    <field>
44046                      <name>OVRD_DATSLICE1OS_EN</name>
44047                      <description>Data slicer 1 offset adjustment override enable</description>
44048                      <bitRange>[7:7]</bitRange>
44049                      <access>read-write</access>
44050                    </field>
44051                    <field>
44052                      <name>OVRD_DATSLICE2OS</name>
44053                      <description>Data slicer 2 offset adjustment override</description>
44054                      <bitRange>[14:8]</bitRange>
44055                      <access>read-write</access>
44056                    </field>
44057                    <field>
44058                      <name>OVRD_DATSLICE2OS_EN</name>
44059                      <description>Data slicer 2 offset adjustment override enable</description>
44060                      <bitRange>[15:15]</bitRange>
44061                      <access>read-write</access>
44062                    </field>
44063                  </fields>
44064                </register>
44065                <register>
44066                  <name>RX_OSA_CFG2</name>
44067                  <description>Offset Calibration FSM (OSA) Configuration</description>
44068                  <addressOffset>0x34</addressOffset>
44069                  <size>16</size>
44070                  <access>read-write</access>
44071                  <resetValue>0x0</resetValue>
44072                  <resetMask>0xFFFF</resetMask>
44073                  <fields>
44074                    <field>
44075                      <name>OVRD_ERRSLICE1OS</name>
44076                      <description>Error slicer 1 offset adjustment override</description>
44077                      <bitRange>[6:0]</bitRange>
44078                      <access>read-write</access>
44079                    </field>
44080                    <field>
44081                      <name>OVRD_ERRSLICE1OS_EN</name>
44082                      <description>Error slicer 1 offset adjustment override enable</description>
44083                      <bitRange>[7:7]</bitRange>
44084                      <access>read-write</access>
44085                    </field>
44086                    <field>
44087                      <name>OVRD_ERRSLICE2OS</name>
44088                      <description>Error slicer 2 offset adjustment override</description>
44089                      <bitRange>[14:8]</bitRange>
44090                      <access>read-write</access>
44091                    </field>
44092                    <field>
44093                      <name>OVRD_ERRSLICE2OS_EN</name>
44094                      <description>Error slicer 2 offset adjustment override enable</description>
44095                      <bitRange>[15:15]</bitRange>
44096                      <access>read-write</access>
44097                    </field>
44098                  </fields>
44099                </register>
44100                <register>
44101                  <name>RX_OSA_CFG3</name>
44102                  <description>Offset Calibration FSM (OSA) Configuration</description>
44103                  <addressOffset>0x38</addressOffset>
44104                  <size>16</size>
44105                  <access>read-write</access>
44106                  <resetValue>0x0</resetValue>
44107                  <resetMask>0xFFFF</resetMask>
44108                  <fields>
44109                    <field>
44110                      <name>OVRD_ROAMSLICE1OS</name>
44111                      <description>Roam slicer 1 offset adjustment override</description>
44112                      <bitRange>[6:0]</bitRange>
44113                      <access>read-write</access>
44114                    </field>
44115                    <field>
44116                      <name>OVRD_ROAMSLICE1OS_EN</name>
44117                      <description>Roam slicer 1 offset adjustment override enable</description>
44118                      <bitRange>[7:7]</bitRange>
44119                      <access>read-write</access>
44120                    </field>
44121                    <field>
44122                      <name>OVRD_ROAMSLICE2OS</name>
44123                      <description>Roam slicer 2 offset adjustment override</description>
44124                      <bitRange>[14:8]</bitRange>
44125                      <access>read-write</access>
44126                    </field>
44127                    <field>
44128                      <name>OVRD_ROAMSLICE2OS_EN</name>
44129                      <description>Roam slicer 2 offset adjustment override enable</description>
44130                      <bitRange>[15:15]</bitRange>
44131                      <access>read-write</access>
44132                    </field>
44133                  </fields>
44134                </register>
44135                <register>
44136                  <name>RX_OSA_CFG4</name>
44137                  <description>Offset Calibration FSM (OSA) Configuration</description>
44138                  <addressOffset>0x3C</addressOffset>
44139                  <size>16</size>
44140                  <access>read-write</access>
44141                  <resetValue>0x0</resetValue>
44142                  <resetMask>0xFF</resetMask>
44143                  <fields>
44144                    <field>
44145                      <name>OVRD_AFEOSDAC</name>
44146                      <description>AFE offset adjustment override</description>
44147                      <bitRange>[6:0]</bitRange>
44148                      <access>read-write</access>
44149                    </field>
44150                    <field>
44151                      <name>OVRD_AFEOSDAC_EN</name>
44152                      <description>AFE offset adjustment override enable</description>
44153                      <bitRange>[7:7]</bitRange>
44154                      <access>read-write</access>
44155                    </field>
44156                  </fields>
44157                </register>
44158                <register>
44159                  <name>RX_OSA_CFG5</name>
44160                  <description>Offset Calibration FSM (OSA) Configuration</description>
44161                  <addressOffset>0x40</addressOffset>
44162                  <size>16</size>
44163                  <access>read-write</access>
44164                  <resetValue>0x0</resetValue>
44165                  <resetMask>0x7</resetMask>
44166                  <fields>
44167                    <field>
44168                      <name>OSA_DFE_START</name>
44169                      <description>DFE offset calibration start, AFE calibration will follow</description>
44170                      <bitRange>[0:0]</bitRange>
44171                      <access>read-write</access>
44172                    </field>
44173                    <field>
44174                      <name>OSA_AFE_START</name>
44175                      <description>AFE offset calibration on demand start</description>
44176                      <bitRange>[1:1]</bitRange>
44177                      <access>read-write</access>
44178                    </field>
44179                    <field>
44180                      <name>OSA_RESETB</name>
44181                      <description>AFE offset calibration block reset, active low</description>
44182                      <bitRange>[2:2]</bitRange>
44183                      <access>read-write</access>
44184                    </field>
44185                  </fields>
44186                </register>
44187                <register>
44188                  <name>RX_OSA_STAT0</name>
44189                  <description>Offset Calibration FSM (OSA) status</description>
44190                  <addressOffset>0x44</addressOffset>
44191                  <size>16</size>
44192                  <access>read-only</access>
44193                  <resetValue>0x0</resetValue>
44194                  <resetMask>0x7F7F</resetMask>
44195                  <fields>
44196                    <field>
44197                      <name>EDGSLICE1OS</name>
44198                      <description>Edge slicer 1 adjusted offset</description>
44199                      <bitRange>[6:0]</bitRange>
44200                      <access>read-only</access>
44201                    </field>
44202                    <field>
44203                      <name>EDGSLICE2OS</name>
44204                      <description>Edge slicer 2 adjusted offset</description>
44205                      <bitRange>[14:8]</bitRange>
44206                      <access>read-only</access>
44207                    </field>
44208                  </fields>
44209                </register>
44210                <register>
44211                  <name>RX_OSA_STAT1</name>
44212                  <description>Offset Calibration FSM (OSA) status</description>
44213                  <addressOffset>0x48</addressOffset>
44214                  <size>16</size>
44215                  <access>read-only</access>
44216                  <resetValue>0x0</resetValue>
44217                  <resetMask>0x7F7F</resetMask>
44218                  <fields>
44219                    <field>
44220                      <name>DATSLICE1OS</name>
44221                      <description>Edge slicer 1 adjusted offset</description>
44222                      <bitRange>[6:0]</bitRange>
44223                      <access>read-only</access>
44224                    </field>
44225                    <field>
44226                      <name>DATSLICE2OS</name>
44227                      <description>Edge slicer 2 adjusted offset</description>
44228                      <bitRange>[14:8]</bitRange>
44229                      <access>read-only</access>
44230                    </field>
44231                  </fields>
44232                </register>
44233                <register>
44234                  <name>RX_OSA_STAT2</name>
44235                  <description>Offset Calibration FSM (OSA) status</description>
44236                  <addressOffset>0x4C</addressOffset>
44237                  <size>16</size>
44238                  <access>read-only</access>
44239                  <resetValue>0x0</resetValue>
44240                  <resetMask>0x7F7F</resetMask>
44241                  <fields>
44242                    <field>
44243                      <name>ERRSLICE1OS</name>
44244                      <description>Error slicer 1 adjusted offset</description>
44245                      <bitRange>[6:0]</bitRange>
44246                      <access>read-only</access>
44247                    </field>
44248                    <field>
44249                      <name>ERRSLICE2OS</name>
44250                      <description>Error slicer 2 adjusted offset</description>
44251                      <bitRange>[14:8]</bitRange>
44252                      <access>read-only</access>
44253                    </field>
44254                  </fields>
44255                </register>
44256                <register>
44257                  <name>RX_OSA_STAT3</name>
44258                  <description>Offset Calibration FSM (OSA) status</description>
44259                  <addressOffset>0x50</addressOffset>
44260                  <size>16</size>
44261                  <access>read-only</access>
44262                  <resetValue>0x0</resetValue>
44263                  <resetMask>0x7F7F</resetMask>
44264                  <fields>
44265                    <field>
44266                      <name>ROAMSLICE1OS</name>
44267                      <description>Roam slicer 1 adjusted offset</description>
44268                      <bitRange>[6:0]</bitRange>
44269                      <access>read-only</access>
44270                    </field>
44271                    <field>
44272                      <name>ROAMSLICE2OS</name>
44273                      <description>Roam slicer 2 adjusted offset</description>
44274                      <bitRange>[14:8]</bitRange>
44275                      <access>read-only</access>
44276                    </field>
44277                  </fields>
44278                </register>
44279                <register>
44280                  <name>RX_OSA_STAT4</name>
44281                  <description>Offset Calibration FSM (OSA) status</description>
44282                  <addressOffset>0x54</addressOffset>
44283                  <size>16</size>
44284                  <access>read-only</access>
44285                  <resetValue>0x0</resetValue>
44286                  <resetMask>0x7F</resetMask>
44287                  <fields>
44288                    <field>
44289                      <name>AFEOSDAC</name>
44290                      <description>AFE adjusted offset</description>
44291                      <bitRange>[6:0]</bitRange>
44292                      <access>read-only</access>
44293                    </field>
44294                  </fields>
44295                </register>
44296                <register>
44297                  <name>RX_OSA_STAT5</name>
44298                  <description>Offset Calibration FSM (OSA) status</description>
44299                  <addressOffset>0x58</addressOffset>
44300                  <size>16</size>
44301                  <access>read-only</access>
44302                  <resetValue>0x0</resetValue>
44303                  <resetMask>0x77</resetMask>
44304                  <fields>
44305                    <field>
44306                      <name>OSA_DFE_DONE</name>
44307                      <description>Offset calibration for DFE blocks (summer+slicer) is completed</description>
44308                      <bitRange>[0:0]</bitRange>
44309                      <access>read-only</access>
44310                    </field>
44311                    <field>
44312                      <name>OSA_AFE_DONE</name>
44313                      <description>Offset calibration for AFE Blocks (AGC+CTLE) is completed</description>
44314                      <bitRange>[1:1]</bitRange>
44315                      <access>read-only</access>
44316                    </field>
44317                    <field>
44318                      <name>OSA_ALL_DONE</name>
44319                      <description>All offset calibrations are completed</description>
44320                      <bitRange>[2:2]</bitRange>
44321                      <access>read-only</access>
44322                    </field>
44323                    <field>
44324                      <name>OSA_DFE_ERROR</name>
44325                      <description>There has been some error during offset calibration for DFE blocks</description>
44326                      <bitRange>[4:4]</bitRange>
44327                      <access>read-only</access>
44328                    </field>
44329                    <field>
44330                      <name>OSA_AFE_ERROR</name>
44331                      <description>There has been some error during offset calibration for AFE blocks</description>
44332                      <bitRange>[5:5]</bitRange>
44333                      <access>read-only</access>
44334                    </field>
44335                    <field>
44336                      <name>OSA_ERROR</name>
44337                      <description>There has been some error during offset calibration for one the blocks, output as interupt, read specific error at osa_err_bits#.</description>
44338                      <bitRange>[6:6]</bitRange>
44339                      <access>read-only</access>
44340                    </field>
44341                  </fields>
44342                </register>
44343                <register>
44344                  <name>RX_OSA_STAT6</name>
44345                  <description>Offset Calibration FSM (OSA) status</description>
44346                  <addressOffset>0x5C</addressOffset>
44347                  <size>16</size>
44348                  <access>read-only</access>
44349                  <resetValue>0x0</resetValue>
44350                  <resetMask>0xFFFF</resetMask>
44351                  <fields>
44352                    <field>
44353                      <name>OSA_ERR_BITS0</name>
44354                      <description>Error bits indicating what went wrong in which block,bits 15:0</description>
44355                      <bitRange>[15:0]</bitRange>
44356                      <access>read-only</access>
44357                    </field>
44358                  </fields>
44359                </register>
44360                <register>
44361                  <name>RX_OSA_STAT7</name>
44362                  <description>Offset Calibration FSM (OSA) status</description>
44363                  <addressOffset>0x60</addressOffset>
44364                  <size>16</size>
44365                  <access>read-only</access>
44366                  <resetValue>0x0</resetValue>
44367                  <resetMask>0xFFFF</resetMask>
44368                  <fields>
44369                    <field>
44370                      <name>OSA_ERR_BITS1</name>
44371                      <description>Error bits indicating what went wrong in which block, bits 31:16</description>
44372                      <bitRange>[15:0]</bitRange>
44373                      <access>read-only</access>
44374                    </field>
44375                  </fields>
44376                </register>
44377                <register>
44378                  <name>RX_OSA_STAT8</name>
44379                  <description>Offset Calibration FSM (OSA) status</description>
44380                  <addressOffset>0x64</addressOffset>
44381                  <size>16</size>
44382                  <access>read-only</access>
44383                  <resetValue>0x0</resetValue>
44384                  <resetMask>0xF</resetMask>
44385                  <fields>
44386                    <field>
44387                      <name>OSA_ERR_BITS2</name>
44388                      <description>Error bits indicating what went wrong in which block, bits 39:32</description>
44389                      <bitRange>[3:0]</bitRange>
44390                      <access>read-only</access>
44391                    </field>
44392                  </fields>
44393                </register>
44394                <register>
44395                  <name>RX_CTLE_CFG0</name>
44396                  <description>CTLE controls Configuration</description>
44397                  <addressOffset>0x68</addressOffset>
44398                  <size>16</size>
44399                  <access>read-write</access>
44400                  <resetValue>0x0</resetValue>
44401                  <resetMask>0x1F03</resetMask>
44402                  <fields>
44403                    <field>
44404                      <name>CTLE_EYEHT_EN</name>
44405                      <description>Enable eye hieght measurement for CTLE adaptation</description>
44406                      <bitRange>[0:0]</bitRange>
44407                      <access>read-write</access>
44408                    </field>
44409                    <field>
44410                      <name>EYEHT_START_CNT</name>
44411                      <description>Start error count for CTLE adaptation</description>
44412                      <bitRange>[1:1]</bitRange>
44413                      <access>read-write</access>
44414                    </field>
44415                    <field>
44416                      <name>CTLE_STG1_CMADJ</name>
44417                      <description>Adjust CTLE cap values for desired EQ</description>
44418                      <bitRange>[10:8]</bitRange>
44419                      <access>read-write</access>
44420                    </field>
44421                    <field>
44422                      <name>CTLE_CAP_FZERO_EN</name>
44423                      <description>Adjust CTLE resistor values for desired EQ</description>
44424                      <bitRange>[11:11]</bitRange>
44425                      <access>read-write</access>
44426                    </field>
44427                    <field>
44428                      <name>CTLE_CAP_GAIN_ADJ</name>
44429                      <description>Strobe/update CTLE EQ settings</description>
44430                      <bitRange>[12:12]</bitRange>
44431                      <access>read-write</access>
44432                    </field>
44433                  </fields>
44434                </register>
44435                <register>
44436                  <name>RX_CTLE_CFG1</name>
44437                  <description>CTLE controls Configuration</description>
44438                  <addressOffset>0x6C</addressOffset>
44439                  <size>16</size>
44440                  <access>read-write</access>
44441                  <resetValue>0x0</resetValue>
44442                  <resetMask>0xFFFF</resetMask>
44443                  <fields>
44444                    <field>
44445                      <name>CTLE_STG1RES</name>
44446                      <description>Adjust CTLE stage 1 resistor value</description>
44447                      <bitRange>[3:0]</bitRange>
44448                      <access>read-write</access>
44449                    </field>
44450                    <field>
44451                      <name>CTLE_STG1CAP</name>
44452                      <description>Adjust CTLE stage 1 cap value</description>
44453                      <bitRange>[6:4]</bitRange>
44454                      <access>read-write</access>
44455                    </field>
44456                    <field>
44457                      <name>CTLE_STG1BOOST</name>
44458                      <description>CTLE stage 1 boost</description>
44459                      <bitRange>[7:7]</bitRange>
44460                      <access>read-write</access>
44461                    </field>
44462                    <field>
44463                      <name>CTLE_STG2RES</name>
44464                      <description>Adjust CTLE stage 2 resistor value</description>
44465                      <bitRange>[11:8]</bitRange>
44466                      <access>read-write</access>
44467                    </field>
44468                    <field>
44469                      <name>CTLE_STG2CAP</name>
44470                      <description>Adjust CTLE stage 2 cap value</description>
44471                      <bitRange>[14:12]</bitRange>
44472                      <access>read-write</access>
44473                    </field>
44474                    <field>
44475                      <name>CTLE_STG2BOOST</name>
44476                      <description>CTLE stage 2 boost</description>
44477                      <bitRange>[15:15]</bitRange>
44478                      <access>read-write</access>
44479                    </field>
44480                  </fields>
44481                </register>
44482                <register>
44483                  <name>RX_CTLE_STAT0</name>
44484                  <description>CTLE controls status</description>
44485                  <addressOffset>0x70</addressOffset>
44486                  <size>16</size>
44487                  <access>read-only</access>
44488                  <resetValue>0x0</resetValue>
44489                  <resetMask>0xFFFF</resetMask>
44490                  <fields>
44491                    <field>
44492                      <name>EYEHT_ERR_CNT</name>
44493                      <description>Error count for CTLE adaptation</description>
44494                      <bitRange>[15:0]</bitRange>
44495                      <access>read-only</access>
44496                    </field>
44497                  </fields>
44498                </register>
44499                <register>
44500                  <name>RX_CTLE_STAT1</name>
44501                  <description>CTLE controls status</description>
44502                  <addressOffset>0x74</addressOffset>
44503                  <size>16</size>
44504                  <access>read-only</access>
44505                  <resetValue>0x0</resetValue>
44506                  <resetMask>0x1</resetMask>
44507                  <fields>
44508                    <field>
44509                      <name>EYEHT_CNT_DONE</name>
44510                      <description>Error count for CTLE adaptation is done</description>
44511                      <bitRange>[0:0]</bitRange>
44512                      <access>read-only</access>
44513                    </field>
44514                  </fields>
44515                </register>
44516                <register>
44517                  <name>RX_EM_CFG0</name>
44518                  <description>Eye monitor FSM (EM) Configuration</description>
44519                  <addressOffset>0x78</addressOffset>
44520                  <size>16</size>
44521                  <access>read-write</access>
44522                  <resetValue>0x0</resetValue>
44523                  <resetMask>0xFFFF</resetMask>
44524                  <fields>
44525                    <field>
44526                      <name>EYE_WORD_CNT</name>
44527                      <description>eye word count</description>
44528                      <bitRange>[2:0]</bitRange>
44529                      <access>read-write</access>
44530                    </field>
44531                    <field>
44532                      <name>DATA_SAMPLE_DELAY</name>
44533                      <description>data sample delay</description>
44534                      <bitRange>[5:3]</bitRange>
44535                      <access>read-write</access>
44536                    </field>
44537                    <field>
44538                      <name>ROAM_SAMPLE_DELAY</name>
44539                      <description>roam sample delay</description>
44540                      <bitRange>[8:6]</bitRange>
44541                      <access>read-write</access>
44542                    </field>
44543                    <field>
44544                      <name>EM_CTRL_UNUSED</name>
44545                      <description>unused control bits</description>
44546                      <bitRange>[11:9]</bitRange>
44547                      <access>read-write</access>
44548                    </field>
44549                    <field>
44550                      <name>EN_EYE_ODD</name>
44551                      <description>enable odd eye</description>
44552                      <bitRange>[12:12]</bitRange>
44553                      <access>read-write</access>
44554                    </field>
44555                    <field>
44556                      <name>EN_EYE_EVEN</name>
44557                      <description>enable even eye</description>
44558                      <bitRange>[13:13]</bitRange>
44559                      <access>read-write</access>
44560                    </field>
44561                    <field>
44562                      <name>START_COUNT</name>
44563                      <description>Eye monitor control and settings (place holder if required)</description>
44564                      <bitRange>[14:14]</bitRange>
44565                      <access>read-write</access>
44566                    </field>
44567                    <field>
44568                      <name>EN_EYEMON</name>
44569                      <description>Enable eye monotor controller</description>
44570                      <bitRange>[15:15]</bitRange>
44571                      <access>read-write</access>
44572                    </field>
44573                  </fields>
44574                </register>
44575                <register>
44576                  <name>RX_EM_CFG1</name>
44577                  <description>Eye monitor FSM (EM) Configuration</description>
44578                  <addressOffset>0x7C</addressOffset>
44579                  <size>16</size>
44580                  <access>read-write</access>
44581                  <resetValue>0x0</resetValue>
44582                  <resetMask>0xFFFF</resetMask>
44583                  <fields>
44584                    <field>
44585                      <name>ROAM_SLICEPOINT</name>
44586                      <description>roam slicer 1 &amp; 2 slice point amplitude</description>
44587                      <bitRange>[5:0]</bitRange>
44588                      <access>read-write</access>
44589                    </field>
44590                    <field>
44591                      <name>ROAM_SLICEPOINTSIGN1</name>
44592                      <description>roam slicer 1 slicepoint, 1:positive, 0:negative</description>
44593                      <bitRange>[6:6]</bitRange>
44594                      <access>read-write</access>
44595                    </field>
44596                    <field>
44597                      <name>ROAM_SLICEPOINTSIGN2</name>
44598                      <description>roam slicer 2 slicepoint, 1:positive, 0:negative</description>
44599                      <bitRange>[7:7]</bitRange>
44600                      <access>read-write</access>
44601                    </field>
44602                    <field>
44603                      <name>PIROAMPSEL</name>
44604                      <description>roam phase interpolator value</description>
44605                      <bitRange>[14:8]</bitRange>
44606                      <access>read-write</access>
44607                    </field>
44608                    <field>
44609                      <name>PIROAMPSEL_EN</name>
44610                      <description>roam phase interpolator enable</description>
44611                      <bitRange>[15:15]</bitRange>
44612                      <access>read-write</access>
44613                    </field>
44614                  </fields>
44615                </register>
44616                <register>
44617                  <name>RX_EM_STAT0</name>
44618                  <description>Eye monitor FSM (EM) status</description>
44619                  <addressOffset>0x80</addressOffset>
44620                  <size>16</size>
44621                  <access>read-only</access>
44622                  <resetValue>0x0</resetValue>
44623                  <resetMask>0xFFFF</resetMask>
44624                  <fields>
44625                    <field>
44626                      <name>EYE_ERROR</name>
44627                      <description>Eye information output (place holder if required)</description>
44628                      <bitRange>[15:0]</bitRange>
44629                      <access>read-only</access>
44630                    </field>
44631                  </fields>
44632                </register>
44633                <register>
44634                  <name>RX_EM_STAT1</name>
44635                  <description>Eye monitor FSM (EM) status</description>
44636                  <addressOffset>0x84</addressOffset>
44637                  <size>16</size>
44638                  <access>read-only</access>
44639                  <resetValue>0x0</resetValue>
44640                  <resetMask>0xFFFD</resetMask>
44641                  <fields>
44642                    <field>
44643                      <name>EYE_DONE</name>
44644                      <description>eye monitor done</description>
44645                      <bitRange>[0:0]</bitRange>
44646                      <access>read-only</access>
44647                    </field>
44648                    <field>
44649                      <name>RX_ROAMSLIC1OS</name>
44650                      <description>roam slicer 1 offset (offset null + slicepoint)</description>
44651                      <bitRange>[8:2]</bitRange>
44652                      <access>read-only</access>
44653                    </field>
44654                    <field>
44655                      <name>RX_ROAMSLIC2OS</name>
44656                      <description>roam slicer 2 offset (offset null + slicepoint)</description>
44657                      <bitRange>[15:9]</bitRange>
44658                      <access>read-only</access>
44659                    </field>
44660                  </fields>
44661                </register>
44662                <register>
44663                  <name>RX_DFEA_CFG0</name>
44664                  <description>DFE Analog Configuration</description>
44665                  <addressOffset>0x88</addressOffset>
44666                  <size>16</size>
44667                  <access>read-write</access>
44668                  <resetValue>0x0</resetValue>
44669                  <resetMask>0xFFFF</resetMask>
44670                  <fields>
44671                    <field>
44672                      <name>DFEMAINADJ</name>
44673                      <description>Adjust summer tail current</description>
44674                      <bitRange>[2:0]</bitRange>
44675                      <access>read-write</access>
44676                    </field>
44677                    <field>
44678                      <name>DFE_PDB</name>
44679                      <description>DFE main power down, active low</description>
44680                      <bitRange>[3:3]</bitRange>
44681                      <access>read-write</access>
44682                    </field>
44683                    <field>
44684                      <name>DFETAP1ADJ</name>
44685                      <description>Adjust DFE tap1 weight</description>
44686                      <bitRange>[6:4]</bitRange>
44687                      <access>read-write</access>
44688                    </field>
44689                    <field>
44690                      <name>DFETAP1_PDB</name>
44691                      <description>DFE tap1 power down, active low</description>
44692                      <bitRange>[7:7]</bitRange>
44693                      <access>read-write</access>
44694                    </field>
44695                    <field>
44696                      <name>DFETAP2ADJ</name>
44697                      <description>Adjust DFE tap2 weight</description>
44698                      <bitRange>[10:8]</bitRange>
44699                      <access>read-write</access>
44700                    </field>
44701                    <field>
44702                      <name>DFETAP2_PDB</name>
44703                      <description>DFE tap1 power down, active low</description>
44704                      <bitRange>[11:11]</bitRange>
44705                      <access>read-write</access>
44706                    </field>
44707                    <field>
44708                      <name>DFETAP3ADJ</name>
44709                      <description>Adjust DFE tap3 weight</description>
44710                      <bitRange>[14:12]</bitRange>
44711                      <access>read-write</access>
44712                    </field>
44713                    <field>
44714                      <name>DFETAP3_PDB</name>
44715                      <description>DFE tap1 power down, active low</description>
44716                      <bitRange>[15:15]</bitRange>
44717                      <access>read-write</access>
44718                    </field>
44719                  </fields>
44720                </register>
44721                <register>
44722                  <name>RX_OSAA_CFG0</name>
44723                  <description>Offset Calibration Analog Configuration</description>
44724                  <addressOffset>0x8C</addressOffset>
44725                  <size>16</size>
44726                  <access>read-write</access>
44727                  <resetValue>0x0</resetValue>
44728                  <resetMask>0x7FFF</resetMask>
44729                  <fields>
44730                    <field>
44731                      <name>ADJEDGESLIC1</name>
44732                      <description>Adjust edge slicer 1 offset DAC full scale range</description>
44733                      <bitRange>[2:0]</bitRange>
44734                      <access>read-write</access>
44735                    </field>
44736                    <field>
44737                      <name>ADJEDGESLIC2</name>
44738                      <description>Adjust edge slicer 2 offset DAC full scale range</description>
44739                      <bitRange>[5:3]</bitRange>
44740                      <access>read-write</access>
44741                    </field>
44742                    <field>
44743                      <name>ADJDATSLIC1</name>
44744                      <description>Adjust data slicer 1 offset DAC full scale range</description>
44745                      <bitRange>[8:6]</bitRange>
44746                      <access>read-write</access>
44747                    </field>
44748                    <field>
44749                      <name>ADJDATSLIC2</name>
44750                      <description>Adjust dara slicer 2 offset DAC full scale range</description>
44751                      <bitRange>[11:9]</bitRange>
44752                      <access>read-write</access>
44753                    </field>
44754                    <field>
44755                      <name>ADJERRSLIC1</name>
44756                      <description>Adjust error slicer 1 offset DAC full scale range</description>
44757                      <bitRange>[14:12]</bitRange>
44758                      <access>read-write</access>
44759                    </field>
44760                  </fields>
44761                </register>
44762                <register>
44763                  <name>RX_OSAA_CFG1</name>
44764                  <description>Offset Calibration Analog Configuration</description>
44765                  <addressOffset>0x90</addressOffset>
44766                  <size>16</size>
44767                  <access>read-write</access>
44768                  <resetValue>0x0</resetValue>
44769                  <resetMask>0xFFF</resetMask>
44770                  <fields>
44771                    <field>
44772                      <name>ADJERRSLIC2</name>
44773                      <description>Adjust error slicer 2 offset DAC full scale range</description>
44774                      <bitRange>[2:0]</bitRange>
44775                      <access>read-write</access>
44776                    </field>
44777                    <field>
44778                      <name>ADJROAMSLIC1</name>
44779                      <description>Adjust roam slicer 1 offset DAC full scale range</description>
44780                      <bitRange>[5:3]</bitRange>
44781                      <access>read-write</access>
44782                    </field>
44783                    <field>
44784                      <name>ADJROAMSLIC2</name>
44785                      <description>Adjust roam slicer 2 offset DAC full scale range</description>
44786                      <bitRange>[8:6]</bitRange>
44787                      <access>read-write</access>
44788                    </field>
44789                    <field>
44790                      <name>AFEOSBIASADJ</name>
44791                      <description>Adjust AFE offset DAC full scale range</description>
44792                      <bitRange>[11:9]</bitRange>
44793                      <access>read-write</access>
44794                    </field>
44795                  </fields>
44796                </register>
44797                <register>
44798                  <name>RX_AFE_CFG</name>
44799                  <description>Analog Front End (AFE) Configuration</description>
44800                  <addressOffset>0x94</addressOffset>
44801                  <size>16</size>
44802                  <access>read-write</access>
44803                  <resetValue>0x0</resetValue>
44804                  <resetMask>0x3FF</resetMask>
44805                  <fields>
44806                    <field>
44807                      <name>CMADJ</name>
44808                      <description>Adjusts input common-mode voltage</description>
44809                      <bitRange>[2:0]</bitRange>
44810                      <access>read-write</access>
44811                    </field>
44812                    <field>
44813                      <name>TERM_EN</name>
44814                      <description>Enable for 50 Ohm (nominal) termination</description>
44815                      <bitRange>[3:3]</bitRange>
44816                      <access>read-write</access>
44817                    </field>
44818                    <field>
44819                      <name>TERM_TRIM_CFG</name>
44820                      <description>value of term_trim input from processor</description>
44821                      <bitRange>[8:4]</bitRange>
44822                      <access>read-write</access>
44823                    </field>
44824                    <field>
44825                      <name>LPBK_EN</name>
44826                      <description>Loopback path enable</description>
44827                      <bitRange>[9:9]</bitRange>
44828                      <access>read-write</access>
44829                    </field>
44830                  </fields>
44831                </register>
44832                <register>
44833                  <name>RX_EMA_CFG</name>
44834                  <description>Eye Monitor Analog Configuration</description>
44835                  <addressOffset>0x98</addressOffset>
44836                  <size>16</size>
44837                  <access>read-write</access>
44838                  <resetValue>0x0</resetValue>
44839                  <resetMask>0x17</resetMask>
44840                  <fields>
44841                    <field>
44842                      <name>PICAPSEL</name>
44843                      <description>Phase Interpolator cap select</description>
44844                      <bitRange>[2:0]</bitRange>
44845                      <access>read-write</access>
44846                    </field>
44847                    <field>
44848                      <name>PI_PDB</name>
44849                      <description>Eye monitor phase interpolator powe down</description>
44850                      <bitRange>[4:4]</bitRange>
44851                      <access>read-write</access>
44852                    </field>
44853                  </fields>
44854                </register>
44855                <register>
44856                  <name>RX_REFCKSEL_CFG</name>
44857                  <description>Reference Clock Select (REFCLKSEL) Configuration</description>
44858                  <addressOffset>0x9C</addressOffset>
44859                  <size>16</size>
44860                  <access>read-write</access>
44861                  <resetValue>0x0</resetValue>
44862                  <resetMask>0x1</resetMask>
44863                  <fields>
44864                    <field>
44865                      <name>LOCK2REF_SEL</name>
44866                      <description>Reference Clock MUX Select between 25 or 100 MHz</description>
44867                      <bitRange>[0:0]</bitRange>
44868                      <access>read-write</access>
44869                    </field>
44870                  </fields>
44871                </register>
44872                <register>
44873                  <name>RX_DIVH_CFG</name>
44874                  <description>HS Divider (DIVH) Configuration</description>
44875                  <addressOffset>0xA0</addressOffset>
44876                  <size>16</size>
44877                  <access>read-write</access>
44878                  <resetValue>0x0</resetValue>
44879                  <resetMask>0x11F</resetMask>
44880                  <fields>
44881                    <field>
44882                      <name>RECCLK_DIVH</name>
44883                      <description>DIVH Divider Ratio, HSREF Clock</description>
44884                      <bitRange>[4:0]</bitRange>
44885                      <access>read-write</access>
44886                    </field>
44887                    <field>
44888                      <name>RECCLK_EN</name>
44889                      <description>High-Speed Ref Clk Output Enable</description>
44890                      <bitRange>[8:8]</bitRange>
44891                      <access>read-write</access>
44892                    </field>
44893                  </fields>
44894                </register>
44895                <register>
44896                  <name>RX_PFD_CFG</name>
44897                  <description>Phase/Frequency Detector (PFD) Configuration</description>
44898                  <addressOffset>0xA4</addressOffset>
44899                  <size>16</size>
44900                  <access>read-write</access>
44901                  <resetValue>0x0</resetValue>
44902                  <resetMask>0xF</resetMask>
44903                  <fields>
44904                    <field>
44905                      <name>PFDDELAY</name>
44906                      <description>Adjust dead-zone feedback delay</description>
44907                      <bitRange>[3:0]</bitRange>
44908                      <access>read-write</access>
44909                    </field>
44910                  </fields>
44911                </register>
44912                <register>
44913                  <name>RX_CP_CFG</name>
44914                  <description>Charge Pump (CP) Configuration</description>
44915                  <addressOffset>0xA8</addressOffset>
44916                  <size>16</size>
44917                  <access>read-write</access>
44918                  <resetValue>0x0</resetValue>
44919                  <resetMask>0x77</resetMask>
44920                  <fields>
44921                    <field>
44922                      <name>IPUP_ADJ</name>
44923                      <description>Charge pump up current adjustment</description>
44924                      <bitRange>[2:0]</bitRange>
44925                      <access>read-write</access>
44926                    </field>
44927                    <field>
44928                      <name>IPDN_ADJ</name>
44929                      <description>Charge pump down current adjustment</description>
44930                      <bitRange>[6:4]</bitRange>
44931                      <access>read-write</access>
44932                    </field>
44933                  </fields>
44934                </register>
44935                <register>
44936                  <name>RX_LF_CFG</name>
44937                  <description>Loop Filter (LF) Configuration</description>
44938                  <addressOffset>0xAC</addressOffset>
44939                  <size>16</size>
44940                  <access>read-write</access>
44941                  <resetValue>0x0</resetValue>
44942                  <resetMask>0x3</resetMask>
44943                  <fields>
44944                    <field>
44945                      <name>LPF_ADJ</name>
44946                      <description>Loop filter adjustment</description>
44947                      <bitRange>[1:0]</bitRange>
44948                      <access>read-write</access>
44949                    </field>
44950                  </fields>
44951                </register>
44952                <register>
44953                  <name>RX_BIASGEN_CFG0</name>
44954                  <description>Bias Generator (BIASGEN) Configuration</description>
44955                  <addressOffset>0xB0</addressOffset>
44956                  <size>16</size>
44957                  <access>read-write</access>
44958                  <resetValue>0x0</resetValue>
44959                  <resetMask>0xFFF</resetMask>
44960                  <fields>
44961                    <field>
44962                      <name>AFEBIASSET0</name>
44963                      <description>Adjust bias for stages of AFE/CTLE  - LSb</description>
44964                      <bitRange>[11:0]</bitRange>
44965                      <access>read-write</access>
44966                    </field>
44967                  </fields>
44968                </register>
44969                <register>
44970                  <name>RX_BIASGEN_CFG1</name>
44971                  <description>Bias Generator (BIASGEN) Configuration</description>
44972                  <addressOffset>0xB4</addressOffset>
44973                  <size>16</size>
44974                  <access>read-write</access>
44975                  <resetValue>0x0</resetValue>
44976                  <resetMask>0x7F3F</resetMask>
44977                  <fields>
44978                    <field>
44979                      <name>AFEBIASSET1</name>
44980                      <description>Adjust bias for stages of AFE/CTLE - Msb</description>
44981                      <bitRange>[5:0]</bitRange>
44982                      <access>read-write</access>
44983                    </field>
44984                    <field>
44985                      <name>CFG_BIAS</name>
44986                      <description>Adjust bias currents</description>
44987                      <bitRange>[13:8]</bitRange>
44988                      <access>read-write</access>
44989                    </field>
44990                    <field>
44991                      <name>BIAS_PDB</name>
44992                      <description>Bias power down, active low</description>
44993                      <bitRange>[14:14]</bitRange>
44994                      <access>read-write</access>
44995                    </field>
44996                  </fields>
44997                </register>
44998                <register>
44999                  <name>RX_GNRL_CFG</name>
45000                  <description>General Controls Configuration</description>
45001                  <addressOffset>0xB8</addressOffset>
45002                  <size>16</size>
45003                  <access>read-write</access>
45004                  <resetValue>0x0</resetValue>
45005                  <resetMask>0xFFF</resetMask>
45006                  <fields>
45007                    <field>
45008                      <name>BUS_BIT_MODE</name>
45009                      <description>RX output data bus width mose, 0:16, 1:20, 2:32, 3:40</description>
45010                      <bitRange>[1:0]</bitRange>
45011                      <access>read-write</access>
45012                    </field>
45013                    <field>
45014                      <name>DESERRESETB</name>
45015                      <description>De-serializer reset, active low</description>
45016                      <bitRange>[2:2]</bitRange>
45017                      <access>read-write</access>
45018                    </field>
45019                    <field>
45020                      <name>DATA_RATE</name>
45021                      <description>0: 10G half rate, 1:5G full rate</description>
45022                      <bitRange>[3:3]</bitRange>
45023                      <access>read-write</access>
45024                    </field>
45025                    <field>
45026                      <name>CLKGEN_PDB</name>
45027                      <description>Clock generation loop (PD+CP+VCO,etc.) powerdown, active low</description>
45028                      <bitRange>[4:4]</bitRange>
45029                      <access>read-write</access>
45030                    </field>
45031                    <field>
45032                      <name>LOWPWR</name>
45033                      <description>AFE low power mode for 5 Gb/s data rate</description>
45034                      <bitRange>[5:5]</bitRange>
45035                      <access>read-write</access>
45036                    </field>
45037                    <field>
45038                      <name>ERR_PATH_EN</name>
45039                      <description>DFE error path power down</description>
45040                      <bitRange>[6:6]</bitRange>
45041                      <access>read-write</access>
45042                    </field>
45043                    <field>
45044                      <name>EDGE_DESER_EN</name>
45045                      <description>Edge deserializer power down</description>
45046                      <bitRange>[7:7]</bitRange>
45047                      <access>read-write</access>
45048                    </field>
45049                    <field>
45050                      <name>SUMEVN_PDB</name>
45051                      <description>DFE even path summer power down</description>
45052                      <bitRange>[8:8]</bitRange>
45053                      <access>read-write</access>
45054                    </field>
45055                    <field>
45056                      <name>SUMODD_PDB</name>
45057                      <description>DFE odd path summer power down</description>
45058                      <bitRange>[9:9]</bitRange>
45059                      <access>read-write</access>
45060                    </field>
45061                    <field>
45062                      <name>SUMVDD_PULLDOWN</name>
45063                      <description>Summers output pull down</description>
45064                      <bitRange>[10:10]</bitRange>
45065                      <access>read-write</access>
45066                    </field>
45067                    <field>
45068                      <name>CLKINV</name>
45069                      <description>Invert phase of pclk</description>
45070                      <bitRange>[11:11]</bitRange>
45071                      <access>read-write</access>
45072                    </field>
45073                  </fields>
45074                </register>
45075                <register>
45076                  <name>RX_VREG_CFG0</name>
45077                  <description>Regulators Configuration</description>
45078                  <addressOffset>0xBC</addressOffset>
45079                  <size>16</size>
45080                  <access>read-write</access>
45081                  <resetValue>0x0</resetValue>
45082                  <resetMask>0xFFFF</resetMask>
45083                  <fields>
45084                    <field>
45085                      <name>VCPREGSEL</name>
45086                      <description>RX CP regulated supply voltage select</description>
45087                      <bitRange>[3:0]</bitRange>
45088                      <access>read-write</access>
45089                    </field>
45090                    <field>
45091                      <name>VREGRXASEL</name>
45092                      <description>RX analog regulated supply voltage select</description>
45093                      <bitRange>[7:4]</bitRange>
45094                      <access>read-write</access>
45095                    </field>
45096                    <field>
45097                      <name>VREGRXCKSEL</name>
45098                      <description>RX clock regulated supply voltage select</description>
45099                      <bitRange>[11:8]</bitRange>
45100                      <access>read-write</access>
45101                    </field>
45102                    <field>
45103                      <name>VREGRXDSEL</name>
45104                      <description>RX digital regulated supply voltage select</description>
45105                      <bitRange>[15:12]</bitRange>
45106                      <access>read-write</access>
45107                    </field>
45108                  </fields>
45109                </register>
45110                <register>
45111                  <name>RX_VREG_CFG1</name>
45112                  <description>Regulators Configuration</description>
45113                  <addressOffset>0xC0</addressOffset>
45114                  <size>16</size>
45115                  <access>read-write</access>
45116                  <resetValue>0x0</resetValue>
45117                  <resetMask>0xF1FF</resetMask>
45118                  <fields>
45119                    <field>
45120                      <name>VCPREG_BPB</name>
45121                      <description>RX regulator charge pump bypass, active low</description>
45122                      <bitRange>[0:0]</bitRange>
45123                      <access>read-write</access>
45124                    </field>
45125                    <field>
45126                      <name>VREGRXA_PDB</name>
45127                      <description>RX analog regulated supply power down, active low</description>
45128                      <bitRange>[1:1]</bitRange>
45129                      <access>read-write</access>
45130                    </field>
45131                    <field>
45132                      <name>VREGRXCK_PDB</name>
45133                      <description>RX clock regulated supply power down, active low</description>
45134                      <bitRange>[2:2]</bitRange>
45135                      <access>read-write</access>
45136                    </field>
45137                    <field>
45138                      <name>VREGRXD_PDB</name>
45139                      <description>RX digital regulated supply power down, active low</description>
45140                      <bitRange>[3:3]</bitRange>
45141                      <access>read-write</access>
45142                    </field>
45143                    <field>
45144                      <name>VCPREG_PDB</name>
45145                      <description>charg-pump voltage supply power down, active low</description>
45146                      <bitRange>[4:4]</bitRange>
45147                      <access>read-write</access>
45148                    </field>
45149                    <field>
45150                      <name>VREG1P4BIASSEL</name>
45151                      <description>Adjust vreg1p4 bias for best CDR PSRR</description>
45152                      <bitRange>[5:5]</bitRange>
45153                      <access>read-write</access>
45154                    </field>
45155                    <field>
45156                      <name>VREG1P4_BPB</name>
45157                      <description>Power-down vreg1p4 and bypass output to vdd1p8</description>
45158                      <bitRange>[6:6]</bitRange>
45159                      <access>read-write</access>
45160                    </field>
45161                    <field>
45162                      <name>CPCLK_SEL</name>
45163                      <description>Clock select for Charge pump</description>
45164                      <bitRange>[7:7]</bitRange>
45165                      <access>read-write</access>
45166                    </field>
45167                    <field>
45168                      <name>BURNIN_EN</name>
45169                      <description>Enable Burn-In mode</description>
45170                      <bitRange>[8:8]</bitRange>
45171                      <access>read-write</access>
45172                    </field>
45173                    <field>
45174                      <name>VREG1P4SEL</name>
45175                      <description>Adjust vreg1p4  for best CDR PSRR</description>
45176                      <bitRange>[15:12]</bitRange>
45177                      <access>read-write</access>
45178                    </field>
45179                  </fields>
45180                </register>
45181                <register>
45182                  <name>RX_VREG_STAT</name>
45183                  <description>Regulators Status</description>
45184                  <addressOffset>0xC4</addressOffset>
45185                  <size>16</size>
45186                  <access>read-only</access>
45187                  <resetValue>0x0</resetValue>
45188                  <resetMask>0x7</resetMask>
45189                  <fields>
45190                    <field>
45191                      <name>POWER_GOOD_RXA</name>
45192                      <description>pwr_good_rxa for read as status</description>
45193                      <bitRange>[0:0]</bitRange>
45194                      <access>read-only</access>
45195                    </field>
45196                    <field>
45197                      <name>POWER_GOOD_RXCK</name>
45198                      <description>pwr_good_rxck for read as status</description>
45199                      <bitRange>[1:1]</bitRange>
45200                      <access>read-only</access>
45201                    </field>
45202                    <field>
45203                      <name>POWER_GOOD_RXD</name>
45204                      <description>pwr_good_rxd for read as status</description>
45205                      <bitRange>[2:2]</bitRange>
45206                      <access>read-only</access>
45207                    </field>
45208                  </fields>
45209                </register>
45210                <register>
45211                  <name>RX_SD_CFG</name>
45212                  <description>Signal detect/LFPS Configuration</description>
45213                  <addressOffset>0xC8</addressOffset>
45214                  <size>16</size>
45215                  <access>read-write</access>
45216                  <resetValue>0x0</resetValue>
45217                  <resetMask>0xF</resetMask>
45218                  <fields>
45219                    <field>
45220                      <name>LFPS_VTH</name>
45221                      <description>LFPS threshold levels setting</description>
45222                      <bitRange>[2:0]</bitRange>
45223                      <access>read-write</access>
45224                    </field>
45225                    <field>
45226                      <name>LFPSDET_PDB</name>
45227                      <description>LFPS detect power down (active low)</description>
45228                      <bitRange>[3:3]</bitRange>
45229                      <access>read-write</access>
45230                    </field>
45231                  </fields>
45232                </register>
45233                <register>
45234                  <name>RX_SD_STAT</name>
45235                  <description>Signal detect/LFPS Status</description>
45236                  <addressOffset>0xCC</addressOffset>
45237                  <size>16</size>
45238                  <access>read-only</access>
45239                  <resetValue>0x0</resetValue>
45240                  <resetMask>0x1</resetMask>
45241                  <fields>
45242                    <field>
45243                      <name>LFPSDET_OUT</name>
45244                      <description>LFPS output detected for read as status</description>
45245                      <bitRange>[0:0]</bitRange>
45246                      <access>read-only</access>
45247                    </field>
45248                  </fields>
45249                </register>
45250                <register>
45251                  <name>RX_LD_CFG</name>
45252                  <description>Lock Detect Configuration</description>
45253                  <addressOffset>0xD0</addressOffset>
45254                  <size>16</size>
45255                  <access>read-write</access>
45256                  <resetValue>0x0</resetValue>
45257                  <resetMask>0xFF7</resetMask>
45258                  <fields>
45259                    <field>
45260                      <name>LOCKIN</name>
45261                      <description>Frequency detect tolerance = +/- 0.025 percent*2^lockin</description>
45262                      <bitRange>[2:0]</bitRange>
45263                      <access>read-write</access>
45264                    </field>
45265                    <field>
45266                      <name>FLOCKSEL</name>
45267                      <description>Filtered lock, #of refcklk cycles flock generated after lock  [2^(flocksel+8)]</description>
45268                      <bitRange>[5:4]</bitRange>
45269                      <access>read-write</access>
45270                    </field>
45271                    <field>
45272                      <name>LOCKOUTSEL</name>
45273                      <description>Lockup detect timer setting, cycles of refclk, 256 or 512</description>
45274                      <bitRange>[6:6]</bitRange>
45275                      <access>read-write</access>
45276                    </field>
45277                    <field>
45278                      <name>LUDDISABLE</name>
45279                      <description>Lockup detect disable</description>
45280                      <bitRange>[7:7]</bitRange>
45281                      <access>read-write</access>
45282                    </field>
45283                    <field>
45284                      <name>FD_OVRD</name>
45285                      <description>Force combinations of freq detect and ph detect en</description>
45286                      <bitRange>[9:8]</bitRange>
45287                      <access>read-write</access>
45288                    </field>
45289                    <field>
45290                      <name>RESETLOCKB</name>
45291                      <description>lock detect lock output reset, active low, will not activate lockup detect</description>
45292                      <bitRange>[10:10]</bitRange>
45293                      <access>read-write</access>
45294                    </field>
45295                    <field>
45296                      <name>LD_RESETB</name>
45297                      <description>lock detect main reset, active low</description>
45298                      <bitRange>[11:11]</bitRange>
45299                      <access>read-write</access>
45300                    </field>
45301                  </fields>
45302                </register>
45303                <register>
45304                  <name>RX_LD_STAT</name>
45305                  <description>Lock Detect Status</description>
45306                  <addressOffset>0xD4</addressOffset>
45307                  <size>16</size>
45308                  <access>read-only</access>
45309                  <resetValue>0x0</resetValue>
45310                  <resetMask>0x1</resetMask>
45311                  <fields>
45312                    <field>
45313                      <name>PLL_LOCKED</name>
45314                      <description>flock for read as status</description>
45315                      <bitRange>[0:0]</bitRange>
45316                      <access>read-only</access>
45317                    </field>
45318                  </fields>
45319                </register>
45320                <register>
45321                  <name>RX_ATEST_CFG</name>
45322                  <description>Analog Test Mux (ATEST) Configuration</description>
45323                  <addressOffset>0xD8</addressOffset>
45324                  <size>16</size>
45325                  <access>read-write</access>
45326                  <resetValue>0x0</resetValue>
45327                  <resetMask>0xFFF</resetMask>
45328                  <fields>
45329                    <field>
45330                      <name>ADFT_CNTL</name>
45331                      <description>Analog test MUX Select</description>
45332                      <bitRange>[3:0]</bitRange>
45333                      <access>read-write</access>
45334                    </field>
45335                    <field>
45336                      <name>ADFT_ENABLE</name>
45337                      <description>Analog test MUX Enable</description>
45338                      <bitRange>[4:4]</bitRange>
45339                      <access>read-write</access>
45340                    </field>
45341                    <field>
45342                      <name>DAC_TEST</name>
45343                      <description>Analog test DAC current measurment</description>
45344                      <bitRange>[8:5]</bitRange>
45345                      <access>read-write</access>
45346                    </field>
45347                    <field>
45348                      <name>DFE_TEST</name>
45349                      <description>Analog test DFE taps current measurment</description>
45350                      <bitRange>[11:9]</bitRange>
45351                      <access>read-write</access>
45352                    </field>
45353                  </fields>
45354                </register>
45355                <register>
45356                  <name>RX_DTEST_CFG</name>
45357                  <description>Digital Test Mux (DTEST) Configuration</description>
45358                  <addressOffset>0xDC</addressOffset>
45359                  <size>16</size>
45360                  <access>read-write</access>
45361                  <resetValue>0x0</resetValue>
45362                  <resetMask>0x1F</resetMask>
45363                  <fields>
45364                    <field>
45365                      <name>DDFT_SEL</name>
45366                      <description>Digital test MUX Select</description>
45367                      <bitRange>[3:0]</bitRange>
45368                      <access>read-write</access>
45369                    </field>
45370                    <field>
45371                      <name>DDFT_ENABLE</name>
45372                      <description>Digital test MUX Enable</description>
45373                      <bitRange>[4:4]</bitRange>
45374                      <access>read-write</access>
45375                    </field>
45376                  </fields>
45377                </register>
45378                <register>
45379                  <name>SPARE_CFG</name>
45380                  <description>Spare Configuration</description>
45381                  <addressOffset>0xE0</addressOffset>
45382                  <size>16</size>
45383                  <access>read-write</access>
45384                  <resetValue>0x0</resetValue>
45385                  <resetMask>0xFFFF</resetMask>
45386                  <fields>
45387                    <field>
45388                      <name>SPARE_OUT</name>
45389                      <description>spare output pins</description>
45390                      <bitRange>[2:0]</bitRange>
45391                      <access>read-write</access>
45392                    </field>
45393                    <field>
45394                      <name>SPARE_FT_OUT</name>
45395                      <description>spare feedthrough outputs</description>
45396                      <bitRange>[15:3]</bitRange>
45397                      <access>read-write</access>
45398                    </field>
45399                  </fields>
45400                </register>
45401                <register>
45402                  <name>SPARE_STAT</name>
45403                  <description>Spare Status</description>
45404                  <addressOffset>0xE4</addressOffset>
45405                  <size>16</size>
45406                  <access>read-only</access>
45407                  <resetValue>0x0</resetValue>
45408                  <resetMask>0xFFFF</resetMask>
45409                  <fields>
45410                    <field>
45411                      <name>SPARE_INPUTS</name>
45412                      <description>spare input pints</description>
45413                      <bitRange>[2:0]</bitRange>
45414                      <access>read-only</access>
45415                    </field>
45416                    <field>
45417                      <name>SPARE_FT_IN</name>
45418                      <description>spare feedthrough inputs</description>
45419                      <bitRange>[15:3]</bitRange>
45420                      <access>read-only</access>
45421                    </field>
45422                  </fields>
45423                </register>
45424              </cluster>
45425              <cluster>
45426                <name>USB40PHY_PLL_SYS</name>
45427                <description>PHY PLL SYS registers</description>
45428                <addressOffset>0x00000900</addressOffset>
45429                <register>
45430                  <name>PLL_SDM_CFG</name>
45431                  <description>Sigma-Delta Modulator (SDM) Configuration</description>
45432                  <addressOffset>0x0</addressOffset>
45433                  <size>16</size>
45434                  <access>read-write</access>
45435                  <resetValue>0x0</resetValue>
45436                  <resetMask>0x1F</resetMask>
45437                  <fields>
45438                    <field>
45439                      <name>SDM_ENABLE</name>
45440                      <description>Sigma-Delta modulator enable, (active low power down), SSM will be down too</description>
45441                      <bitRange>[0:0]</bitRange>
45442                      <access>read-write</access>
45443                    </field>
45444                    <field>
45445                      <name>DITHER_EN</name>
45446                      <description>Sigma-Delta Modulator dither enable</description>
45447                      <bitRange>[1:1]</bitRange>
45448                      <access>read-write</access>
45449                    </field>
45450                    <field>
45451                      <name>DITHER_GAIN</name>
45452                      <description>dither gain value</description>
45453                      <bitRange>[4:2]</bitRange>
45454                      <access>read-write</access>
45455                    </field>
45456                  </fields>
45457                </register>
45458                <register>
45459                  <name>PLL_SSM_CFG0</name>
45460                  <description>Spread Spectrun Modulator (SSM) Configuration</description>
45461                  <addressOffset>0x4</addressOffset>
45462                  <size>16</size>
45463                  <access>read-write</access>
45464                  <resetValue>0x0</resetValue>
45465                  <resetMask>0xFFFF</resetMask>
45466                  <fields>
45467                    <field>
45468                      <name>DIVF_FRAC_MSB</name>
45469                      <description>Feedback Divider Ratio fractional vlaue (if SSM is not enabled these input goes to SDM)</description>
45470                      <bitRange>[7:0]</bitRange>
45471                      <access>read-write</access>
45472                    </field>
45473                    <field>
45474                      <name>DIVF_INTEGER</name>
45475                      <description>Feedback Divider Ratio integer vlaue (if SSM is not enabled these input goes to SDM)</description>
45476                      <bitRange>[15:8]</bitRange>
45477                      <access>read-write</access>
45478                    </field>
45479                  </fields>
45480                </register>
45481                <register>
45482                  <name>PLL_SSM_CFG1</name>
45483                  <description>Spread Spectrun Modulator (SSM) Configuration</description>
45484                  <addressOffset>0x8</addressOffset>
45485                  <size>16</size>
45486                  <access>read-write</access>
45487                  <resetValue>0x0</resetValue>
45488                  <resetMask>0xE3FF</resetMask>
45489                  <fields>
45490                    <field>
45491                      <name>DIVF_FRAC_LSB</name>
45492                      <description>Feedback Divider Ratio fractional vlaue (if SSM is not enabled these input goes to SDM)</description>
45493                      <bitRange>[9:0]</bitRange>
45494                      <access>read-write</access>
45495                    </field>
45496                    <field>
45497                      <name>SPREAD</name>
45498                      <description>SSM modulation depth setting</description>
45499                      <bitRange>[15:13]</bitRange>
45500                      <access>read-write</access>
45501                    </field>
45502                  </fields>
45503                </register>
45504                <register>
45505                  <name>PLL_SSM_CFG2</name>
45506                  <description>Spread Spectrun Modulator (SSM) Configuration</description>
45507                  <addressOffset>0xC</addressOffset>
45508                  <size>16</size>
45509                  <access>read-write</access>
45510                  <resetValue>0x0</resetValue>
45511                  <resetMask>0x7FFF</resetMask>
45512                  <fields>
45513                    <field>
45514                      <name>SSM_STEP_CNT</name>
45515                      <description>SSM modulation triangle new value update count</description>
45516                      <bitRange>[8:0]</bitRange>
45517                      <access>read-write</access>
45518                    </field>
45519                    <field>
45520                      <name>SSM_UPDATE_CNT</name>
45521                      <description>SSM modulation triangle number of steps count</description>
45522                      <bitRange>[13:9]</bitRange>
45523                      <access>read-write</access>
45524                    </field>
45525                    <field>
45526                      <name>SSM_ENABLE</name>
45527                      <description>Spread spectrum modulator enable, (active low power down), SDM can be active</description>
45528                      <bitRange>[14:14]</bitRange>
45529                      <access>read-write</access>
45530                    </field>
45531                  </fields>
45532                </register>
45533                <register>
45534                  <name>PLL_AFC_CFG0</name>
45535                  <description>Automatic Frequency Control (AFC) Configuration</description>
45536                  <addressOffset>0x10</addressOffset>
45537                  <size>16</size>
45538                  <access>read-write</access>
45539                  <resetValue>0x0</resetValue>
45540                  <resetMask>0xFFFF</resetMask>
45541                  <fields>
45542                    <field>
45543                      <name>AFC_VCTL_SET</name>
45544                      <description>N/A</description>
45545                      <bitRange>[2:0]</bitRange>
45546                      <access>read-write</access>
45547                    </field>
45548                    <field>
45549                      <name>AFC_VCMP_PDB</name>
45550                      <description>N/A</description>
45551                      <bitRange>[3:3]</bitRange>
45552                      <access>read-write</access>
45553                    </field>
45554                    <field>
45555                      <name>AFC_VCMP_SEL</name>
45556                      <description>N/A</description>
45557                      <bitRange>[7:4]</bitRange>
45558                      <access>read-write</access>
45559                    </field>
45560                    <field>
45561                      <name>AFC_OVRD_CAPSEL</name>
45562                      <description>Override value for capsel</description>
45563                      <bitRange>[14:8]</bitRange>
45564                      <access>read-write</access>
45565                    </field>
45566                    <field>
45567                      <name>AFC_OVRRIDEN</name>
45568                      <description>Override for capsel</description>
45569                      <bitRange>[15:15]</bitRange>
45570                      <access>read-write</access>
45571                    </field>
45572                  </fields>
45573                </register>
45574                <register>
45575                  <name>PLL_AFC_CFG1</name>
45576                  <description>Automatic Frequency Control (AFC) Configuration</description>
45577                  <addressOffset>0x14</addressOffset>
45578                  <size>16</size>
45579                  <access>read-write</access>
45580                  <resetValue>0x0</resetValue>
45581                  <resetMask>0x3FFF</resetMask>
45582                  <fields>
45583                    <field>
45584                      <name>AFC_VCTL_HI_CNT</name>
45585                      <description>AFC vcontrol reset timer count</description>
45586                      <bitRange>[4:0]</bitRange>
45587                      <access>read-write</access>
45588                    </field>
45589                    <field>
45590                      <name>AFC_VCTL_LO_CNT</name>
45591                      <description>AFC vcontrol release timer count</description>
45592                      <bitRange>[9:5]</bitRange>
45593                      <access>read-write</access>
45594                    </field>
45595                    <field>
45596                      <name>AFC_VCTL_ENABLE_OVERRIDE</name>
45597                      <description>Override for afc_vctl_enable</description>
45598                      <bitRange>[10:10]</bitRange>
45599                      <access>read-write</access>
45600                    </field>
45601                    <field>
45602                      <name>AFC_VCTL_ENABLE_OVERRIDE_VALUE</name>
45603                      <description>Override value  for afc_vctl_enable</description>
45604                      <bitRange>[11:11]</bitRange>
45605                      <access>read-write</access>
45606                    </field>
45607                    <field>
45608                      <name>AFC_SEL_MIN</name>
45609                      <description>Capsel min value select</description>
45610                      <bitRange>[12:12]</bitRange>
45611                      <access>read-write</access>
45612                    </field>
45613                    <field>
45614                      <name>AFC_SEL_MAX</name>
45615                      <description>Capsel max value select</description>
45616                      <bitRange>[13:13]</bitRange>
45617                      <access>read-write</access>
45618                    </field>
45619                  </fields>
45620                </register>
45621                <register>
45622                  <name>PLL_AFC_CFG2</name>
45623                  <description>Automatic Frequency Control (AFC) Configuration</description>
45624                  <addressOffset>0x18</addressOffset>
45625                  <size>16</size>
45626                  <access>read-write</access>
45627                  <resetValue>0x0</resetValue>
45628                  <resetMask>0x7F</resetMask>
45629                  <fields>
45630                    <field>
45631                      <name>AFC_CLKDIVSEL</name>
45632                      <description>Refclk to FSM clk divide select</description>
45633                      <bitRange>[5:0]</bitRange>
45634                      <access>read-write</access>
45635                    </field>
45636                    <field>
45637                      <name>AFC_PDB</name>
45638                      <description>AFC active low power-down</description>
45639                      <bitRange>[6:6]</bitRange>
45640                      <access>read-write</access>
45641                    </field>
45642                  </fields>
45643                </register>
45644                <register>
45645                  <name>PLL_AFC_STAT</name>
45646                  <description>Automatic Frequency Control (AFC) Status</description>
45647                  <addressOffset>0x1C</addressOffset>
45648                  <size>16</size>
45649                  <access>read-only</access>
45650                  <resetValue>0x0</resetValue>
45651                  <resetMask>0x7F</resetMask>
45652                  <fields>
45653                    <field>
45654                      <name>CAPSEL</name>
45655                      <description>'capsel' value for read</description>
45656                      <bitRange>[6:0]</bitRange>
45657                      <access>read-only</access>
45658                    </field>
45659                  </fields>
45660                </register>
45661                <register>
45662                  <name>PLL_AAC_CFG0</name>
45663                  <description>Automatic Amplitude Control (AAC) Configuration</description>
45664                  <addressOffset>0x20</addressOffset>
45665                  <size>16</size>
45666                  <access>read-write</access>
45667                  <resetValue>0x0</resetValue>
45668                  <resetMask>0x3FF</resetMask>
45669                  <fields>
45670                    <field>
45671                      <name>AACREFSEL</name>
45672                      <description>Amplitude reference voltage select</description>
45673                      <bitRange>[3:0]</bitRange>
45674                      <access>read-write</access>
45675                    </field>
45676                    <field>
45677                      <name>AAC_OVRD_AACSEL</name>
45678                      <description>Override value for aacout</description>
45679                      <bitRange>[8:4]</bitRange>
45680                      <access>read-write</access>
45681                    </field>
45682                    <field>
45683                      <name>AAC_OVRRIDEN</name>
45684                      <description>AAC active low power-down</description>
45685                      <bitRange>[9:9]</bitRange>
45686                      <access>read-write</access>
45687                    </field>
45688                  </fields>
45689                </register>
45690                <register>
45691                  <name>PLL_AAC_CFG1</name>
45692                  <description>Automatic Amplitude Control (AAC) Configuration</description>
45693                  <addressOffset>0x24</addressOffset>
45694                  <size>16</size>
45695                  <access>read-write</access>
45696                  <resetValue>0x0</resetValue>
45697                  <resetMask>0x1FF</resetMask>
45698                  <fields>
45699                    <field>
45700                      <name>AAC_CLKDIVSEL</name>
45701                      <description>Refclk to FSM clk divide select</description>
45702                      <bitRange>[5:0]</bitRange>
45703                      <access>read-write</access>
45704                    </field>
45705                    <field>
45706                      <name>AAC_FRZCNT</name>
45707                      <description>Freeze the counter output (aacout)</description>
45708                      <bitRange>[6:6]</bitRange>
45709                      <access>read-write</access>
45710                    </field>
45711                    <field>
45712                      <name>AAC_NORECAL</name>
45713                      <description>No recalibration after 1st lock</description>
45714                      <bitRange>[7:7]</bitRange>
45715                      <access>read-write</access>
45716                    </field>
45717                    <field>
45718                      <name>AAC_PDB</name>
45719                      <description>No recalibration after 1st lock</description>
45720                      <bitRange>[8:8]</bitRange>
45721                      <access>read-write</access>
45722                    </field>
45723                  </fields>
45724                </register>
45725                <register>
45726                  <name>PLL_AAC_STAT</name>
45727                  <description>Automatic Amplitude Control (AAC) Status</description>
45728                  <addressOffset>0x28</addressOffset>
45729                  <size>16</size>
45730                  <access>read-only</access>
45731                  <resetValue>0x0</resetValue>
45732                  <resetMask>0x1F</resetMask>
45733                  <fields>
45734                    <field>
45735                      <name>AACSEL</name>
45736                      <description>'aacout' for read</description>
45737                      <bitRange>[4:0]</bitRange>
45738                      <access>read-only</access>
45739                    </field>
45740                  </fields>
45741                </register>
45742                <register>
45743                  <name>PLL_REFCKSEL_CFG</name>
45744                  <description>Reference Clock Select (REFCLKSEL) Configuration</description>
45745                  <addressOffset>0x2C</addressOffset>
45746                  <size>16</size>
45747                  <access>read-write</access>
45748                  <resetValue>0x0</resetValue>
45749                  <resetMask>0x7</resetMask>
45750                  <fields>
45751                    <field>
45752                      <name>REFCLKSEL</name>
45753                      <description>Reference Clock MUX Select</description>
45754                      <bitRange>[2:0]</bitRange>
45755                      <access>read-write</access>
45756                    </field>
45757                  </fields>
45758                </register>
45759                <register>
45760                  <name>PLL_DIVR_CFG</name>
45761                  <description>Reference Clock Divider (DIVR) Configuration</description>
45762                  <addressOffset>0x30</addressOffset>
45763                  <size>16</size>
45764                  <access>read-write</access>
45765                  <resetValue>0x0</resetValue>
45766                  <resetMask>0xF</resetMask>
45767                  <fields>
45768                    <field>
45769                      <name>LCDIVR</name>
45770                      <description>DIVR Divider Ratio</description>
45771                      <bitRange>[3:0]</bitRange>
45772                      <access>read-write</access>
45773                    </field>
45774                  </fields>
45775                </register>
45776                <register>
45777                  <name>PLL_DIVP_CFG</name>
45778                  <description>Post Divider (DIVP) Configuration</description>
45779                  <addressOffset>0x34</addressOffset>
45780                  <size>16</size>
45781                  <access>read-write</access>
45782                  <resetValue>0x0</resetValue>
45783                  <resetMask>0xFF</resetMask>
45784                  <fields>
45785                    <field>
45786                      <name>LCDIVP</name>
45787                      <description>DIVP Divider Ratio, TX Clk</description>
45788                      <bitRange>[3:0]</bitRange>
45789                      <access>read-write</access>
45790                    </field>
45791                    <field>
45792                      <name>LCBYPASS</name>
45793                      <description>DIVP Divider Ratio, TX Clk</description>
45794                      <bitRange>[4:4]</bitRange>
45795                      <access>read-write</access>
45796                    </field>
45797                    <field>
45798                      <name>TX0_DIVP_PDB</name>
45799                      <description>DIVP Divider, power down, active low for output 0</description>
45800                      <bitRange>[5:5]</bitRange>
45801                      <access>read-write</access>
45802                    </field>
45803                    <field>
45804                      <name>TX1_DIVP_PDB</name>
45805                      <description>DIVP Divider, power down, active low for output 1</description>
45806                      <bitRange>[6:6]</bitRange>
45807                      <access>read-write</access>
45808                    </field>
45809                    <field>
45810                      <name>PLL_SYNC_ENABLE</name>
45811                      <description>pll_rstb synchronization enable, can be disable after sync is done</description>
45812                      <bitRange>[7:7]</bitRange>
45813                      <access>read-write</access>
45814                    </field>
45815                  </fields>
45816                </register>
45817                <register>
45818                  <name>PLL_DIVH_CFG</name>
45819                  <description>HS Divider (DIVH) Configuration</description>
45820                  <addressOffset>0x38</addressOffset>
45821                  <size>16</size>
45822                  <access>read-write</access>
45823                  <resetValue>0x0</resetValue>
45824                  <resetMask>0x3F</resetMask>
45825                  <fields>
45826                    <field>
45827                      <name>HSREF_DIVH</name>
45828                      <description>DIVH Divider Ratio, HSREF Clock</description>
45829                      <bitRange>[4:0]</bitRange>
45830                      <access>read-write</access>
45831                    </field>
45832                    <field>
45833                      <name>HSREF_EN</name>
45834                      <description>High-Speed Ref Clk Output Enable</description>
45835                      <bitRange>[5:5]</bitRange>
45836                      <access>read-write</access>
45837                    </field>
45838                  </fields>
45839                </register>
45840                <register>
45841                  <name>PLL_PFD_CFG</name>
45842                  <description>Phase/Frequency Detector (PFD) Configuration</description>
45843                  <addressOffset>0x3C</addressOffset>
45844                  <size>16</size>
45845                  <access>read-write</access>
45846                  <resetValue>0x0</resetValue>
45847                  <resetMask>0xF</resetMask>
45848                  <fields>
45849                    <field>
45850                      <name>PFDDELAY</name>
45851                      <description>Adjust dead-zone feedback delay</description>
45852                      <bitRange>[3:0]</bitRange>
45853                      <access>read-write</access>
45854                    </field>
45855                  </fields>
45856                </register>
45857                <register>
45858                  <name>PLL_CP_CFG</name>
45859                  <description>Charge Pump (CP) Configuration</description>
45860                  <addressOffset>0x40</addressOffset>
45861                  <size>16</size>
45862                  <access>read-write</access>
45863                  <resetValue>0x0</resetValue>
45864                  <resetMask>0x1FF</resetMask>
45865                  <fields>
45866                    <field>
45867                      <name>CFGRCP</name>
45868                      <description>Charge pump bias resistor adjustment</description>
45869                      <bitRange>[3:0]</bitRange>
45870                      <access>read-write</access>
45871                    </field>
45872                    <field>
45873                      <name>ICPDAC</name>
45874                      <description>Charge pump current adjustment</description>
45875                      <bitRange>[7:4]</bitRange>
45876                      <access>read-write</access>
45877                    </field>
45878                    <field>
45879                      <name>CP_PDB</name>
45880                      <description>Charge pump power down, active low</description>
45881                      <bitRange>[8:8]</bitRange>
45882                      <access>read-write</access>
45883                    </field>
45884                  </fields>
45885                </register>
45886                <register>
45887                  <name>PLL_LF_CFG</name>
45888                  <description>Loop Filter (LF) Configuration</description>
45889                  <addressOffset>0x44</addressOffset>
45890                  <size>16</size>
45891                  <access>read-write</access>
45892                  <resetValue>0x0</resetValue>
45893                  <resetMask>0x1F</resetMask>
45894                  <fields>
45895                    <field>
45896                      <name>LF_RTUNE</name>
45897                      <description>N/A</description>
45898                      <bitRange>[2:0]</bitRange>
45899                      <access>read-write</access>
45900                    </field>
45901                    <field>
45902                      <name>LF_CTUNE</name>
45903                      <description>N/A</description>
45904                      <bitRange>[4:3]</bitRange>
45905                      <access>read-write</access>
45906                    </field>
45907                  </fields>
45908                </register>
45909                <register>
45910                  <name>PLL_VCO_CFG</name>
45911                  <description>Voltage-Controlled Oscillator (VCO) Configuration</description>
45912                  <addressOffset>0x48</addressOffset>
45913                  <size>16</size>
45914                  <access>read-write</access>
45915                  <resetValue>0x0</resetValue>
45916                  <resetMask>0xFFF</resetMask>
45917                  <fields>
45918                    <field>
45919                      <name>DCVARMODE</name>
45920                      <description>VCO fix varactors DC bias voltage setting</description>
45921                      <bitRange>[3:0]</bitRange>
45922                      <access>read-write</access>
45923                    </field>
45924                    <field>
45925                      <name>VCOVARCM1</name>
45926                      <description>VCO varactor#1 common mode voltage trimming</description>
45927                      <bitRange>[7:4]</bitRange>
45928                      <access>read-write</access>
45929                    </field>
45930                    <field>
45931                      <name>VCOVARCM2</name>
45932                      <description>VCO varactor#2 common mode voltage trimming</description>
45933                      <bitRange>[11:8]</bitRange>
45934                      <access>read-write</access>
45935                    </field>
45936                  </fields>
45937                </register>
45938                <register>
45939                  <name>PLL_BIASGEN_CFG</name>
45940                  <description>Bias Generator (BIASGEN) Configuration</description>
45941                  <addressOffset>0x4C</addressOffset>
45942                  <size>16</size>
45943                  <access>read-write</access>
45944                  <resetValue>0x0</resetValue>
45945                  <resetMask>0x1F3F</resetMask>
45946                  <fields>
45947                    <field>
45948                      <name>CFG_BIAS</name>
45949                      <description>Adjust bias currents</description>
45950                      <bitRange>[5:0]</bitRange>
45951                      <access>read-write</access>
45952                    </field>
45953                    <field>
45954                      <name>TERM_TRIM</name>
45955                      <description>value for termination trim</description>
45956                      <bitRange>[12:8]</bitRange>
45957                      <access>read-write</access>
45958                    </field>
45959                  </fields>
45960                </register>
45961                <register>
45962                  <name>PLL_GNRL_CFG</name>
45963                  <description>General Controls Configuration</description>
45964                  <addressOffset>0x50</addressOffset>
45965                  <size>16</size>
45966                  <access>read-write</access>
45967                  <resetValue>0x0</resetValue>
45968                  <resetMask>0x7</resetMask>
45969                  <fields>
45970                    <field>
45971                      <name>PLL_PDB</name>
45972                      <description>Global PLL active low power-down</description>
45973                      <bitRange>[0:0]</bitRange>
45974                      <access>read-write</access>
45975                    </field>
45976                    <field>
45977                      <name>LKDT_RESETB</name>
45978                      <description>main lock detect reset, active low</description>
45979                      <bitRange>[1:1]</bitRange>
45980                      <access>read-write</access>
45981                    </field>
45982                    <field>
45983                      <name>RESETLOCKB</name>
45984                      <description>lock detect, lock output reset, used for re-locking, active low</description>
45985                      <bitRange>[2:2]</bitRange>
45986                      <access>read-write</access>
45987                    </field>
45988                  </fields>
45989                </register>
45990                <register>
45991                  <name>PLL_VREG_CFG1</name>
45992                  <description>Regulators Configuration</description>
45993                  <addressOffset>0x54</addressOffset>
45994                  <size>16</size>
45995                  <access>read-write</access>
45996                  <resetValue>0x0</resetValue>
45997                  <resetMask>0xFFFF</resetMask>
45998                  <fields>
45999                    <field>
46000                      <name>VCPREGSEL</name>
46001                      <description>Adjust voltage for charg-pump regulator</description>
46002                      <bitRange>[3:0]</bitRange>
46003                      <access>read-write</access>
46004                    </field>
46005                    <field>
46006                      <name>VREGLCPLLSEL</name>
46007                      <description>Adjust voltage for VCO Clock rate cells</description>
46008                      <bitRange>[7:4]</bitRange>
46009                      <access>read-write</access>
46010                    </field>
46011                    <field>
46012                      <name>VREGREFSEL</name>
46013                      <description>Adjust voltage for REFCK rate cells</description>
46014                      <bitRange>[11:8]</bitRange>
46015                      <access>read-write</access>
46016                    </field>
46017                    <field>
46018                      <name>VREGDIGSEL</name>
46019                      <description>Adjust voltage for async. Cells</description>
46020                      <bitRange>[15:12]</bitRange>
46021                      <access>read-write</access>
46022                    </field>
46023                  </fields>
46024                </register>
46025                <register>
46026                  <name>PLL_VREG_CFG2</name>
46027                  <description>Regulators Configuration</description>
46028                  <addressOffset>0x58</addressOffset>
46029                  <size>16</size>
46030                  <access>read-write</access>
46031                  <resetValue>0x0</resetValue>
46032                  <resetMask>0x7F</resetMask>
46033                  <fields>
46034                    <field>
46035                      <name>VCPREG_PDB</name>
46036                      <description>charge-pump regulator powr down, active low</description>
46037                      <bitRange>[0:0]</bitRange>
46038                      <access>read-write</access>
46039                    </field>
46040                    <field>
46041                      <name>VREGLCPLL_PDB</name>
46042                      <description>LCPLL Regulator Power-Down</description>
46043                      <bitRange>[1:1]</bitRange>
46044                      <access>read-write</access>
46045                    </field>
46046                    <field>
46047                      <name>VREGREF_PDB</name>
46048                      <description>REF Regulator Power-Down</description>
46049                      <bitRange>[2:2]</bitRange>
46050                      <access>read-write</access>
46051                    </field>
46052                    <field>
46053                      <name>VREGDIG_PDB</name>
46054                      <description>DIG Regulator Power-Down</description>
46055                      <bitRange>[3:3]</bitRange>
46056                      <access>read-write</access>
46057                    </field>
46058                    <field>
46059                      <name>VCPREG_BPB</name>
46060                      <description>CP regulator bypass</description>
46061                      <bitRange>[4:4]</bitRange>
46062                      <access>read-write</access>
46063                    </field>
46064                    <field>
46065                      <name>CPCLK_SEL</name>
46066                      <description>CP regulator clock frequency select</description>
46067                      <bitRange>[5:5]</bitRange>
46068                      <access>read-write</access>
46069                    </field>
46070                    <field>
46071                      <name>BURNIN</name>
46072                      <description>Enable Burn-In mode</description>
46073                      <bitRange>[6:6]</bitRange>
46074                      <access>read-write</access>
46075                    </field>
46076                  </fields>
46077                </register>
46078                <register>
46079                  <name>PLL_VREG_STAT</name>
46080                  <description>Regulators Status</description>
46081                  <addressOffset>0x5C</addressOffset>
46082                  <size>16</size>
46083                  <access>read-only</access>
46084                  <resetValue>0x0</resetValue>
46085                  <resetMask>0x7</resetMask>
46086                  <fields>
46087                    <field>
46088                      <name>PWR_GOOD_LCPLL</name>
46089                      <description>pwr_good_lcpll for read as status</description>
46090                      <bitRange>[0:0]</bitRange>
46091                      <access>read-only</access>
46092                    </field>
46093                    <field>
46094                      <name>PWR_GOOD_REF</name>
46095                      <description>pwr_good_ref for read as status</description>
46096                      <bitRange>[1:1]</bitRange>
46097                      <access>read-only</access>
46098                    </field>
46099                    <field>
46100                      <name>PWR_GOOD_DIG</name>
46101                      <description>pwr_good_dig for read as status</description>
46102                      <bitRange>[2:2]</bitRange>
46103                      <access>read-only</access>
46104                    </field>
46105                  </fields>
46106                </register>
46107                <register>
46108                  <name>PLL_LD_CFG</name>
46109                  <description>Lock Detect Configuration</description>
46110                  <addressOffset>0x60</addressOffset>
46111                  <size>16</size>
46112                  <access>read-write</access>
46113                  <resetValue>0x0</resetValue>
46114                  <resetMask>0x3F7</resetMask>
46115                  <fields>
46116                    <field>
46117                      <name>LOCKOS</name>
46118                      <description>Frequency detect tolerance = +/- 0.025 percent*2^lockin</description>
46119                      <bitRange>[2:0]</bitRange>
46120                      <access>read-write</access>
46121                    </field>
46122                    <field>
46123                      <name>DLFCNTSEL</name>
46124                      <description>Filtered lock, #of refcklk cycles flock generated after lock  [2^(flocksel+8)]</description>
46125                      <bitRange>[5:4]</bitRange>
46126                      <access>read-write</access>
46127                    </field>
46128                    <field>
46129                      <name>LUDDIVSEL</name>
46130                      <description>Lockup detect timer setting, cycles of refclk, 256 or 512</description>
46131                      <bitRange>[6:6]</bitRange>
46132                      <access>read-write</access>
46133                    </field>
46134                    <field>
46135                      <name>LUDDISABLE</name>
46136                      <description>Lockup detect disable</description>
46137                      <bitRange>[7:7]</bitRange>
46138                      <access>read-write</access>
46139                    </field>
46140                    <field>
46141                      <name>CRS_FD_AUXCLK_SEL</name>
46142                      <description>Coarse frequency detect aux clock select</description>
46143                      <bitRange>[8:8]</bitRange>
46144                      <access>read-write</access>
46145                    </field>
46146                    <field>
46147                      <name>CRS_FD_DISABLE</name>
46148                      <description>Coarse frequency detect disable</description>
46149                      <bitRange>[9:9]</bitRange>
46150                      <access>read-write</access>
46151                    </field>
46152                  </fields>
46153                </register>
46154                <register>
46155                  <name>PLL_LD_STAT</name>
46156                  <description>Lock Detect Status</description>
46157                  <addressOffset>0x64</addressOffset>
46158                  <size>16</size>
46159                  <access>read-only</access>
46160                  <resetValue>0x0</resetValue>
46161                  <resetMask>0x1</resetMask>
46162                  <fields>
46163                    <field>
46164                      <name>FLOCK</name>
46165                      <description>flock for read as status</description>
46166                      <bitRange>[0:0]</bitRange>
46167                      <access>read-only</access>
46168                    </field>
46169                  </fields>
46170                </register>
46171                <register>
46172                  <name>PLL_ATEST</name>
46173                  <description>Analog Test Mux (ATEST) Configuration</description>
46174                  <addressOffset>0x68</addressOffset>
46175                  <size>16</size>
46176                  <access>read-write</access>
46177                  <resetValue>0x0</resetValue>
46178                  <resetMask>0x1F</resetMask>
46179                  <fields>
46180                    <field>
46181                      <name>ADFT_SEL</name>
46182                      <description>Analog test MUX Select</description>
46183                      <bitRange>[3:0]</bitRange>
46184                      <access>read-write</access>
46185                    </field>
46186                    <field>
46187                      <name>ADFT_ENABLE</name>
46188                      <description>Analog test MUX Enable</description>
46189                      <bitRange>[4:4]</bitRange>
46190                      <access>read-write</access>
46191                    </field>
46192                  </fields>
46193                </register>
46194                <register>
46195                  <name>PLL_DTEST</name>
46196                  <description>Digital Test Mux (DTEST) Configuration</description>
46197                  <addressOffset>0x6C</addressOffset>
46198                  <size>16</size>
46199                  <access>read-write</access>
46200                  <resetValue>0x0</resetValue>
46201                  <resetMask>0x1F</resetMask>
46202                  <fields>
46203                    <field>
46204                      <name>DDFT_SEL</name>
46205                      <description>Digital test MUX Select</description>
46206                      <bitRange>[3:0]</bitRange>
46207                      <access>read-write</access>
46208                    </field>
46209                    <field>
46210                      <name>DDFT_ENABLE</name>
46211                      <description>Digital test MUX Enable</description>
46212                      <bitRange>[4:4]</bitRange>
46213                      <access>read-write</access>
46214                    </field>
46215                  </fields>
46216                </register>
46217                <register>
46218                  <name>SPARE_CFG</name>
46219                  <description>Spare Configuration</description>
46220                  <addressOffset>0x70</addressOffset>
46221                  <size>16</size>
46222                  <access>read-write</access>
46223                  <resetValue>0x0</resetValue>
46224                  <resetMask>0xFFFF</resetMask>
46225                  <fields>
46226                    <field>
46227                      <name>SPARE_OUT</name>
46228                      <description>spare output pins</description>
46229                      <bitRange>[2:0]</bitRange>
46230                      <access>read-write</access>
46231                    </field>
46232                    <field>
46233                      <name>SPARE_FT_OUT</name>
46234                      <description>spare feedthrough outputs</description>
46235                      <bitRange>[15:3]</bitRange>
46236                      <access>read-write</access>
46237                    </field>
46238                  </fields>
46239                </register>
46240                <register>
46241                  <name>SPARE_STAT</name>
46242                  <description>Spare Status</description>
46243                  <addressOffset>0x74</addressOffset>
46244                  <size>16</size>
46245                  <access>read-only</access>
46246                  <resetValue>0x0</resetValue>
46247                  <resetMask>0xFFFF</resetMask>
46248                  <fields>
46249                    <field>
46250                      <name>SPARE_INPUTS</name>
46251                      <description>spare input pins</description>
46252                      <bitRange>[2:0]</bitRange>
46253                      <access>read-only</access>
46254                    </field>
46255                    <field>
46256                      <name>SPARE_FT_IN</name>
46257                      <description>spare feedthrough inputs</description>
46258                      <bitRange>[15:3]</bitRange>
46259                      <access>read-only</access>
46260                    </field>
46261                  </fields>
46262                </register>
46263              </cluster>
46264            </cluster>
46265          </cluster>
46266          <cluster>
46267            <name>ADAPTER</name>
46268            <description>USB32 Adapter registers.
462690x10000 is for Ingress and 0x20000 for egress Adapter</description>
46270            <addressOffset>0x00010000</addressOffset>
46271            <cluster>
46272              <dim>2</dim>
46273              <dimIncrement>65536</dimIncrement>
46274              <name>DMA[%s]</name>
46275              <description>DMA Configuration Register</description>
46276              <addressOffset>0x00000000</addressOffset>
46277              <cluster>
46278                <dim>16</dim>
46279                <dimIncrement>128</dimIncrement>
46280                <name>SCK[%s]</name>
46281                <description>Socket Registers</description>
46282                <addressOffset>0x00008000</addressOffset>
46283                <register>
46284                  <name>SCK_DSCR</name>
46285                  <description>Descriptor Chain Pointer</description>
46286                  <addressOffset>0x0</addressOffset>
46287                  <size>32</size>
46288                  <access>read-write</access>
46289                  <resetValue>0x0</resetValue>
46290                  <resetMask>0xFFFFFFFF</resetMask>
46291                  <fields>
46292                    <field>
46293                      <name>DSCR_NUMBER</name>
46294                      <description>Descriptor number of currently active descriptor.  A value of 0xFFFF designates no (more) active descriptors available.  When activating a socket CPU shall write number of first descriptor in here. Only modify this field when go_suspend=1 or go_enable=0</description>
46295                      <bitRange>[15:0]</bitRange>
46296                      <access>read-write</access>
46297                    </field>
46298                    <field>
46299                      <name>DSCR_COUNT</name>
46300                      <description>Number of descriptors still left to process.  This value is unrelated to actual number of descriptors in the list.  It is used only to generate an interrupt to the CPU when the value goes low or zero (or both).  When this value reaches 0 it will wrap around to 255.  The socket will not suspend or be otherwise affected unless the descriptor chains ends with 0xFFFF descriptor number.</description>
46301                      <bitRange>[23:16]</bitRange>
46302                      <access>read-write</access>
46303                    </field>
46304                    <field>
46305                      <name>DSCR_LOW</name>
46306                      <description>The low watermark for dscr_count.  When dscr_count is equal or less than dscr_low the status bit dscr_is_low is set and an interrupt can be generated (depending on int mask).</description>
46307                      <bitRange>[31:24]</bitRange>
46308                      <access>read-write</access>
46309                    </field>
46310                  </fields>
46311                </register>
46312                <register>
46313                  <name>SCK_SIZE</name>
46314                  <description>Transfer Size Register</description>
46315                  <addressOffset>0x4</addressOffset>
46316                  <size>32</size>
46317                  <access>read-write</access>
46318                  <resetValue>0x0</resetValue>
46319                  <resetMask>0xFFFFFFFF</resetMask>
46320                  <fields>
46321                    <field>
46322                      <name>TRANS_SIZE</name>
46323                      <description>The number of bytes or buffers (depends on unit bit in SCK_STATUS) that are part of this transfer.  A value of 0 signals an infinite/undetermined transaction size.
46324Valid data bytes remaining in the last buffer beyond the transfer size will be read by socket and passed on to the core. FW must ensure that no additional bytes beyond the transfer size are present in the last buffer.</description>
46325                      <bitRange>[31:0]</bitRange>
46326                      <access>read-write</access>
46327                    </field>
46328                  </fields>
46329                </register>
46330                <register>
46331                  <name>SCK_COUNT</name>
46332                  <description>Transfer Count Register</description>
46333                  <addressOffset>0x8</addressOffset>
46334                  <size>32</size>
46335                  <access>read-write</access>
46336                  <resetValue>0x0</resetValue>
46337                  <resetMask>0xFFFFFFFF</resetMask>
46338                  <fields>
46339                    <field>
46340                      <name>TRANS_COUNT</name>
46341                      <description>The number of bytes or buffers (depends on unit bit in SCK_STATUS) that have been transferred through this socket so far.  If trans_size is &gt;0 and trans_count&gt;=trans_size the  'trans_done' bits in SCK_STATUS is both set.  If SCK_STATUS.susp_trans=1 the socket is also suspended and the 'suspend' bit set. This count is updated only when a descriptor is completed and the socket proceeds to the next one.
46342Exception: When socket suspends with PARTIAL_BUF=1, this value has been (incorrectly) incremented by 1 (UNIT=1) or DSCR_SIZE.BYTE_COUNT (UNIT=0).  Firmware must correct this before resuming the socket.</description>
46343                      <bitRange>[31:0]</bitRange>
46344                      <access>read-write</access>
46345                    </field>
46346                  </fields>
46347                </register>
46348                <register>
46349                  <name>SCK_STATUS</name>
46350                  <description>Socket Status Register</description>
46351                  <addressOffset>0xC</addressOffset>
46352                  <size>32</size>
46353                  <access>read-write</access>
46354                  <resetValue>0x4E00000</resetValue>
46355                  <resetMask>0xFFFF87FF</resetMask>
46356                  <fields>
46357                    <field>
46358                      <name>AVL_COUNT</name>
46359                      <description>Number of available (free for ingress, occupied for egress) descriptors beyond the current one.  This number is incremented by the adapter whenever an event is received on this socket and decremented whenever it activates a new descriptor. This value is used to create a signal to the IP Cores that indicates at least one buffer is available beyond the current one (sck_more_buf_avl).</description>
46360                      <bitRange>[4:0]</bitRange>
46361                      <access>read-write</access>
46362                    </field>
46363                    <field>
46364                      <name>AVL_MIN</name>
46365                      <description>Minimum number of available buffers required by the adapter before activating a new one.  This can be used to guarantee a minimum number of buffers available with old data to implement rollback.  If AVL_ENABLE, the socket will remain in STALL state until AVL_COUNT&gt;=AVL_MIN.</description>
46366                      <bitRange>[9:5]</bitRange>
46367                      <access>read-write</access>
46368                    </field>
46369                    <field>
46370                      <name>AVL_ENABLE</name>
46371                      <description>Enables the functioning of AVL_COUNT and AVL_MIN. When 0, it will disable both stalling on AVL_MIN and generation of the sck_more_buf_avl signal described above.</description>
46372                      <bitRange>[10:10]</bitRange>
46373                      <access>read-write</access>
46374                    </field>
46375                    <field>
46376                      <name>STATE</name>
46377                      <description>Internal operating state of the socket.  This field is used for debugging and to safely modify active sockets (see go_suspend).</description>
46378                      <bitRange>[17:15]</bitRange>
46379                      <access>read-only</access>
46380                      <enumeratedValues>
46381                        <enumeratedValue>
46382                          <name>DESCR</name>
46383                          <description>Descriptor state. This is the default initial state indicating the descriptor registers are NOT valid in the Adapter. The Adapter will start loading the descriptor from memory if the socket becomes enabled and not suspended. Suspend has no effect on any other state.</description>
46384                          <value>0</value>
46385                        </enumeratedValue>
46386                        <enumeratedValue>
46387                          <name>STALL</name>
46388                          <description>Stall state. Socket is stalled waiting for data to be loaded into the Fetch Queue or waiting for an event.</description>
46389                          <value>1</value>
46390                        </enumeratedValue>
46391                        <enumeratedValue>
46392                          <name>ACTIVE</name>
46393                          <description>Active state. Socket is available for core data transfers.</description>
46394                          <value>2</value>
46395                        </enumeratedValue>
46396                        <enumeratedValue>
46397                          <name>EVENT</name>
46398                          <description>Event state. Core transfer is done. Descriptor is being written back to memory and an event is being generated if enabled.</description>
46399                          <value>3</value>
46400                        </enumeratedValue>
46401                        <enumeratedValue>
46402                          <name>CHECK1</name>
46403                          <description>Check states. An active socket gets here based on the core's EOP request to check the Transfer size and determine whether the buffer should be wrapped up. Depending on result, socket will either go back to Active state or move to the Event state.</description>
46404                          <value>4</value>
46405                        </enumeratedValue>
46406                        <enumeratedValue>
46407                          <name>SUSPENDED</name>
46408                          <description>Socket is suspended</description>
46409                          <value>5</value>
46410                        </enumeratedValue>
46411                        <enumeratedValue>
46412                          <name>CHECK2</name>
46413                          <description>Check states. An active socket gets here based on the core's EOP request to check the Transfer size and determine whether the buffer should be wrapped up. Depending on result, socket will either go back to Active state or move to the Event state.</description>
46414                          <value>6</value>
46415                        </enumeratedValue>
46416                        <enumeratedValue>
46417                          <name>WAITING</name>
46418                          <description>Waiting for confirmation that event was sent.</description>
46419                          <value>7</value>
46420                        </enumeratedValue>
46421                      </enumeratedValues>
46422                    </field>
46423                    <field>
46424                      <name>ZLP_RCVD</name>
46425                      <description>Indicates the socket received a ZLP</description>
46426                      <bitRange>[18:18]</bitRange>
46427                      <access>read-only</access>
46428                    </field>
46429                    <field>
46430                      <name>SUSPENDED</name>
46431                      <description>Indicates the socket is currently in suspend state.  In suspend mode there is no active descriptor; any previously active descriptor has been wrapped up, copied back to memory and SCK_DSCR.dscr_number has been updated using DSCR_CHAIN as needed.  If the next descriptor is known (SCK_DSCR.dscr_number!=0xFFFF), this descriptor will be loaded after the socket resumes from suspend state.
46432A socket can only be resumed by changing go_suspend from 1 to 0.  If the socket is suspended while go_suspend=0, it must first be set and then again cleared.</description>
46433                      <bitRange>[19:19]</bitRange>
46434                      <access>read-only</access>
46435                    </field>
46436                    <field>
46437                      <name>ENABLED</name>
46438                      <description>Indicates the socket is currently enabled when asserted.  After go_enable is changed, it may take some time for enabled to make the same change.  This value can be polled to determine this fact.</description>
46439                      <bitRange>[20:20]</bitRange>
46440                      <access>read-only</access>
46441                    </field>
46442                    <field>
46443                      <name>TRUNCATE</name>
46444                      <description>Enable (1) or disable (0) truncating of BYTE_COUNT when TRANS_COUNT+BYTE_COUNT&gt;=TRANS_SIZE.  When enabled, ensures that an ingress transfer never contains more bytes then allowed.  This function is needed to implement burst-based prototocols that can only transmit full bursts of more than 1 byte.</description>
46445                      <bitRange>[21:21]</bitRange>
46446                      <access>read-write</access>
46447                    </field>
46448                    <field>
46449                      <name>EN_PROD_EVENTS</name>
46450                      <description>Enable (1) or disable (0) sending of produce events from any descriptor in this socket.  If 0, events will be suppressed, and the descriptor will not be copied back into memory when completed.</description>
46451                      <bitRange>[22:22]</bitRange>
46452                      <access>read-write</access>
46453                    </field>
46454                    <field>
46455                      <name>EN_CONS_EVENTS</name>
46456                      <description>Enable (1) or disable (0) sending of consume events from any descriptor in this socket.  If 0, events will be suppressed, and the descriptor will not be copied back into memory when completed.</description>
46457                      <bitRange>[23:23]</bitRange>
46458                      <access>read-write</access>
46459                    </field>
46460                    <field>
46461                      <name>SUSP_PARTIAL</name>
46462                      <description>When set, the socket will suspend before activating a descriptor with BYTE_COUNT&lt;BUFFER_SIZE.
46463This is relevant for egress sockets only.</description>
46464                      <bitRange>[24:24]</bitRange>
46465                      <access>read-write</access>
46466                    </field>
46467                    <field>
46468                      <name>SUSP_LAST</name>
46469                      <description>When set, the socket will suspend before activating a descriptor with TRANS_COUNT+BUFFER_SIZE&gt;=TRANS_SIZE.  This is relevant for both ingress and egress sockets.</description>
46470                      <bitRange>[25:25]</bitRange>
46471                      <access>read-write</access>
46472                    </field>
46473                    <field>
46474                      <name>SUSP_TRANS</name>
46475                      <description>When set, the socket will suspend when trans_count &gt;= trans_size.  This equation is checked (and hence the socket will suspend) only at the boundary of buffers and packets (ie. buffer wrapup or EOP assertion).</description>
46476                      <bitRange>[26:26]</bitRange>
46477                      <access>read-write</access>
46478                    </field>
46479                    <field>
46480                      <name>SUSP_EOP</name>
46481                      <description>When set, the socket will suspend after wrapping up the first buffer with dscr.eop=1.  Note that this function will work the same for both ingress and egress sockets.</description>
46482                      <bitRange>[27:27]</bitRange>
46483                      <access>read-write</access>
46484                    </field>
46485                    <field>
46486                      <name>WRAPUP</name>
46487                      <description>Setting this bit will forcibly wrap-up a socket, whether it is out of data or not.  This option is intended mainly for ingress sockets, but works also for egress sockets.  Any remaining data in fetch buffers is ignored, in write buffers is flushed.  Transaction and buffer counts are updated normally, and suspend behavior also happens normally (depending on various other settings in this register).G45</description>
46488                      <bitRange>[28:28]</bitRange>
46489                      <access>read-write</access>
46490                    </field>
46491                    <field>
46492                      <name>UNIT</name>
46493                      <description>Indicates whether descriptors (1) or bytes (0) are counted by trans_count and trans_size.  Descriptors are counting regardless of whether they contain any data or have eop set.</description>
46494                      <bitRange>[29:29]</bitRange>
46495                      <access>read-write</access>
46496                    </field>
46497                    <field>
46498                      <name>GO_SUSPEND</name>
46499                      <description>Directs a socket to go into suspend mode when the current descriptor completes.  The main use of this bit is to safely append descriptors to an active socket without actually suspending it (in most cases). The process is outlined in more detail in the architecture spec, and looks as follows:
465001: GO_SUSPEND=1
465012: modify the chain in memory
465023: check if active descriptor is 0xFFFF or last in chain
465034: if so, make corrections as neccessary (complicated)
465045: clear any pending suspend interrupts (SCK_INTR[9:5])
465056: GO_SUSPEND=0
46506Note that the socket resumes only when SCK_INTR[9:5]=0 and GO_SUSPEND=0.</description>
46507                      <bitRange>[30:30]</bitRange>
46508                      <access>read-write</access>
46509                    </field>
46510                    <field>
46511                      <name>GO_ENABLE</name>
46512                      <description>Indicates whether socket is enabled.  When go_enable is cleared while socket is active, ongoing transfers are aborted after an unspecified amount of time.  No update occurs from the descriptor registers back into memory.  When go_enable is changed from 0 to 1, the socket will reload the active descriptor from memory regardless of the contents of DSCR_ registers. The socket will not wait for an EVENT to become active if the descriptor is available and ready for transfer (has space or data).
46513The 'enabled' bit indicates whether the socket is actually enabled or not.  This field lags go_enable by an short but unspecificied of time.</description>
46514                      <bitRange>[31:31]</bitRange>
46515                      <access>read-write</access>
46516                    </field>
46517                  </fields>
46518                </register>
46519                <register>
46520                  <name>SCK_INTR</name>
46521                  <description>Socket Interrupt Request Register</description>
46522                  <addressOffset>0x10</addressOffset>
46523                  <size>32</size>
46524                  <access>read-write</access>
46525                  <resetValue>0x0</resetValue>
46526                  <resetMask>0x3FF</resetMask>
46527                  <fields>
46528                    <field>
46529                      <name>PRODUCE_EVENT</name>
46530                      <description>Indicates that a produce event has been received or transmitted since last cleared.</description>
46531                      <bitRange>[0:0]</bitRange>
46532                      <access>read-write</access>
46533                    </field>
46534                    <field>
46535                      <name>CONSUME_EVENT</name>
46536                      <description>Indicates that a consume event has been received or transmitted since last cleared.</description>
46537                      <bitRange>[1:1]</bitRange>
46538                      <access>read-write</access>
46539                    </field>
46540                    <field>
46541                      <name>DSCR_IS_LOW</name>
46542                      <description>Indicates that dscr_count has fallen below its watermark dscr_low.  If dscr_count wraps around to 255 dscr_is_low will remain asserted until cleared by s/w</description>
46543                      <bitRange>[2:2]</bitRange>
46544                      <access>read-write</access>
46545                    </field>
46546                    <field>
46547                      <name>DSCR_NOT_AVL</name>
46548                      <description>Indicates the no descriptor is available.  Not available means that the current descriptor number is 0xFFFF.  Note that this bit will remain asserted until cleared by s/w, regardless of whether a new descriptor number is loaded.</description>
46549                      <bitRange>[3:3]</bitRange>
46550                      <access>read-write</access>
46551                    </field>
46552                    <field>
46553                      <name>STALL</name>
46554                      <description>Indicates the socket has stalled, waiting for an event signaling its descriptor has become available. Note that this bit will remain asserted until cleared by s/w, regardless of whether the socket resumes.</description>
46555                      <bitRange>[4:4]</bitRange>
46556                      <access>read-write</access>
46557                    </field>
46558                    <field>
46559                      <name>SUSPEND</name>
46560                      <description>Indicates the socket has gone into suspend mode.  This may be caused by any hardware initiated condition (e.g. DSCR_NOT_AVL, any of the SUSP_*) or by setting GO_SUSPEND=1.  Note that this bit will remain asserted until cleared by s/w, regardless of whether the suspend condition is resolved.
46561Note that the socket resumes only when SCK_INTR[9:5]=0 and GO_SUSPEND=0.</description>
46562                      <bitRange>[5:5]</bitRange>
46563                      <access>read-write</access>
46564                    </field>
46565                    <field>
46566                      <name>ERROR</name>
46567                      <description>Indicates the socket is suspended because of an error condition (internal to the adapter) - if error=1 then suspend=1 as well.  Possible error causes are:
46568- dscr_size.buffer_error bit already set in the descriptor.
46569- dscr_size.byte_count &gt; dscr_size.buffer_size
46570- core writes into an inactive socket.
46571- core did not consume all the data in the buffer.
46572Note that the socket resumes only when SCK_INTR[9:5]=0 and GO_SUSPEND=0.</description>
46573                      <bitRange>[6:6]</bitRange>
46574                      <access>read-write</access>
46575                    </field>
46576                    <field>
46577                      <name>TRANS_DONE</name>
46578                      <description>Indicates that TRANS_COUNT has reached the limit TRANS_SIZE.  This flag is only set when SUSP_TRANS=1.  Note that because TRANS_COUNT is updated only at the granularity of entire buffers, it is possible that TRANS_COUNT exceeds TRANS_SIZE before the socket suspends.  Software must detect and deal with these situations.  When asserting EOP to the adapter on ingress, the trans_count is not updated unless the socket actually suspends (see SUSP_TRANS).
46579Note that the socket resumes only when SCK_INTR[9:5]=0 and GO_SUSPEND=0.</description>
46580                      <bitRange>[7:7]</bitRange>
46581                      <access>read-write</access>
46582                    </field>
46583                    <field>
46584                      <name>PARTIAL_BUF</name>
46585                      <description>Indicates that the (egress) socket was suspended because of SUSP_PARTIAL condition.  Note that the socket resumes only when SCK_INTR[9:5]=0 and GO_SUSPEND=0.</description>
46586                      <bitRange>[8:8]</bitRange>
46587                      <access>read-write</access>
46588                    </field>
46589                    <field>
46590                      <name>LAST_BUF</name>
46591                      <description>Indicates that the socket was suspended because of SUSP_LAST condition.  Note that the socket resumes only when SCK_INTR[9:5]=0 and GO_SUSPEND=0.</description>
46592                      <bitRange>[9:9]</bitRange>
46593                      <access>read-write</access>
46594                    </field>
46595                  </fields>
46596                </register>
46597                <register>
46598                  <name>SCK_INTR_MASK</name>
46599                  <description>Socket Interrupt Mask Register</description>
46600                  <addressOffset>0x14</addressOffset>
46601                  <size>32</size>
46602                  <access>read-write</access>
46603                  <resetValue>0x0</resetValue>
46604                  <resetMask>0x3FF</resetMask>
46605                  <fields>
46606                    <field>
46607                      <name>PRODUCE_EVENT</name>
46608                      <description>1: Report interrupt to CPU</description>
46609                      <bitRange>[0:0]</bitRange>
46610                      <access>read-write</access>
46611                    </field>
46612                    <field>
46613                      <name>CONSUME_EVENT</name>
46614                      <description>1: Report interrupt to CPU</description>
46615                      <bitRange>[1:1]</bitRange>
46616                      <access>read-write</access>
46617                    </field>
46618                    <field>
46619                      <name>DSCR_IS_LOW</name>
46620                      <description>1: Report interrupt to CPU</description>
46621                      <bitRange>[2:2]</bitRange>
46622                      <access>read-write</access>
46623                    </field>
46624                    <field>
46625                      <name>DSCR_NOT_AVL</name>
46626                      <description>1: Report interrupt to CPU</description>
46627                      <bitRange>[3:3]</bitRange>
46628                      <access>read-write</access>
46629                    </field>
46630                    <field>
46631                      <name>STALL</name>
46632                      <description>1: Report interrupt to CPU</description>
46633                      <bitRange>[4:4]</bitRange>
46634                      <access>read-write</access>
46635                    </field>
46636                    <field>
46637                      <name>SUSPEND</name>
46638                      <description>1: Report interrupt to CPU</description>
46639                      <bitRange>[5:5]</bitRange>
46640                      <access>read-write</access>
46641                    </field>
46642                    <field>
46643                      <name>ERROR</name>
46644                      <description>1: Report interrupt to CPU</description>
46645                      <bitRange>[6:6]</bitRange>
46646                      <access>read-write</access>
46647                    </field>
46648                    <field>
46649                      <name>TRANS_DONE</name>
46650                      <description>1: Report interrupt to CPU</description>
46651                      <bitRange>[7:7]</bitRange>
46652                      <access>read-write</access>
46653                    </field>
46654                    <field>
46655                      <name>PARTIAL_BUF</name>
46656                      <description>1: Report interrupt to CPU</description>
46657                      <bitRange>[8:8]</bitRange>
46658                      <access>read-write</access>
46659                    </field>
46660                    <field>
46661                      <name>LAST_BUF</name>
46662                      <description>1: Report interrupt to CPU</description>
46663                      <bitRange>[9:9]</bitRange>
46664                      <access>read-write</access>
46665                    </field>
46666                  </fields>
46667                </register>
46668                <register>
46669                  <name>DSCR_BUFFER</name>
46670                  <description>Descriptor buffer base address register</description>
46671                  <addressOffset>0x20</addressOffset>
46672                  <size>32</size>
46673                  <access>read-write</access>
46674                  <resetValue>0x0</resetValue>
46675                  <resetMask>0xFFFFFFFF</resetMask>
46676                  <fields>
46677                    <field>
46678                      <name>BUFFER_ADDR</name>
46679                      <description>The base address of the buffer where data is written.  This address is not necessarily word-aligned to allow for header/trailer/length modification.</description>
46680                      <bitRange>[31:0]</bitRange>
46681                      <access>read-write</access>
46682                    </field>
46683                  </fields>
46684                </register>
46685                <register>
46686                  <name>DSCR_SYNC</name>
46687                  <description>Descriptor synchronization pointers register</description>
46688                  <addressOffset>0x24</addressOffset>
46689                  <size>32</size>
46690                  <access>read-write</access>
46691                  <resetValue>0x0</resetValue>
46692                  <resetMask>0xFFFFFFFF</resetMask>
46693                  <fields>
46694                    <field>
46695                      <name>CONS_SCK</name>
46696                      <description>The socket number of the consuming socket to which the produce event shall be sent.
46697If cons_ip and cons_sck matches the socket's IP and socket number then the matching socket becomes consuming socket.</description>
46698                      <bitRange>[7:0]</bitRange>
46699                      <access>read-write</access>
46700                    </field>
46701                    <field>
46702                      <name>CONS_IP</name>
46703                      <description>The IP number of the consuming socket to which the produce event shall be sent.  Use 0x3F to designate ARM CPU (so software) as consumer; the event will be lost in this case and an interrupt should also be generated to observe this condition.</description>
46704                      <bitRange>[13:8]</bitRange>
46705                      <access>read-write</access>
46706                    </field>
46707                    <field>
46708                      <name>EN_CONS_EVENT</name>
46709                      <description>Enable sending of a consume events from this descriptor only.  Events are sent only if SCK_STATUS.en_consume_ev=1.  When events are disabled, the adapter also does not update the descriptor in memory to clear its occupied bit.</description>
46710                      <bitRange>[14:14]</bitRange>
46711                      <access>read-write</access>
46712                    </field>
46713                    <field>
46714                      <name>EN_CONS_INT</name>
46715                      <description>Enable generation of a consume event interrupt for this descriptor only.  This interrupt will only be seen by the CPU if SCK_STATUS.int_mask has this interrupt enabled as well.  Note that this flag influences the logging of the interrupt in SCK_STATUS; it has no effect on the reporting of the interrupt to the CPU like SCK_STATUS.int_mask does.</description>
46716                      <bitRange>[15:15]</bitRange>
46717                      <access>read-write</access>
46718                    </field>
46719                    <field>
46720                      <name>PROD_SCK</name>
46721                      <description>The socket number of the producing socket to which the consume event shall be sent. If prod_ip and prod_sck matches the socket's IP and socket number then the matching socket becomes consuming socket.</description>
46722                      <bitRange>[23:16]</bitRange>
46723                      <access>read-write</access>
46724                    </field>
46725                    <field>
46726                      <name>PROD_IP</name>
46727                      <description>The IP number of the producing socket to which the consume event shall be sent. Use 0x3F to designate ARM CPU (so software) as producer; the event will be lost in this case and an interrupt should also be generated to observe this condition.</description>
46728                      <bitRange>[29:24]</bitRange>
46729                      <access>read-write</access>
46730                    </field>
46731                    <field>
46732                      <name>EN_PROD_EVENT</name>
46733                      <description>Enable sending of a produce events from this descriptor only.  Events are sent only if SCK_STATUS.en_produce_ev=1.  If 0, events will be suppressed, and the descriptor will not be copied back into memory when completed.</description>
46734                      <bitRange>[30:30]</bitRange>
46735                      <access>read-write</access>
46736                    </field>
46737                    <field>
46738                      <name>EN_PROD_INT</name>
46739                      <description>Enable generation of a produce event interrupt for this descriptor only. This interrupt will only be seen by the CPU if SCK_STATUS. int_mask has this interrupt enabled as well.  Note that this flag influences the logging of the interrupt in SCK_STATUS; it has no effect on the reporting of the interrupt to the CPU like SCK_STATUS.int_mask does.</description>
46740                      <bitRange>[31:31]</bitRange>
46741                      <access>read-write</access>
46742                    </field>
46743                  </fields>
46744                </register>
46745                <register>
46746                  <name>DSCR_CHAIN</name>
46747                  <description>Descriptor Chain Pointers Register</description>
46748                  <addressOffset>0x28</addressOffset>
46749                  <size>32</size>
46750                  <access>read-write</access>
46751                  <resetValue>0x0</resetValue>
46752                  <resetMask>0xFFFFFFFF</resetMask>
46753                  <fields>
46754                    <field>
46755                      <name>RD_NEXT_DSCR</name>
46756                      <description>Descriptor number of the next task for consumer. A value of 0xFFFF signals end of this list.</description>
46757                      <bitRange>[15:0]</bitRange>
46758                      <access>read-write</access>
46759                    </field>
46760                    <field>
46761                      <name>WR_NEXT_DSCR</name>
46762                      <description>Descriptor number of the next task for producer. A value of 0xFFFF signals end of this list.</description>
46763                      <bitRange>[31:16]</bitRange>
46764                      <access>read-write</access>
46765                    </field>
46766                  </fields>
46767                </register>
46768                <register>
46769                  <name>DSCR_SIZE</name>
46770                  <description>Descriptor Size Register</description>
46771                  <addressOffset>0x2C</addressOffset>
46772                  <size>32</size>
46773                  <access>read-write</access>
46774                  <resetValue>0x0</resetValue>
46775                  <resetMask>0xFFFFFFFF</resetMask>
46776                  <fields>
46777                    <field>
46778                      <name>MARKER</name>
46779                      <description>A marker that is provided by s/w and can be observed by the IP.  It's meaning is defined by the IP that uses it.  This bit has no effect on the other DMA mechanisms.</description>
46780                      <bitRange>[0:0]</bitRange>
46781                      <access>read-write</access>
46782                    </field>
46783                    <field>
46784                      <name>EOP</name>
46785                      <description>A marker indicating this descriptor refers to the last buffer of a packet or transfer. Packets/transfers may span more than one buffer.  The producing IP provides this marker by providing the EOP signal to its DMA adapter.  The consuming IP observes this marker by inspecting its EOP return signal from its own DMA adapter. For more information see section on packets, buffers and transfers in DMA chapter.</description>
46786                      <bitRange>[1:1]</bitRange>
46787                      <access>read-write</access>
46788                    </field>
46789                    <field>
46790                      <name>BUFFER_ERROR</name>
46791                      <description>Indicates the buffer data is valid (0) or in error (1).</description>
46792                      <bitRange>[2:2]</bitRange>
46793                      <access>read-write</access>
46794                    </field>
46795                    <field>
46796                      <name>BUFFER_OCCUPIED</name>
46797                      <description>Indicates the buffer is in use (1) or empty (0).  A consumer will interpret this as:
467980: Buffer is empty, wait until filled.
467991: Buffer has data that can be consumed
46800A produce will interpret this as:
468010: Buffer is ready to be filled
468021: Buffer is occupied, wait until empty</description>
46803                      <bitRange>[3:3]</bitRange>
46804                      <access>read-write</access>
46805                    </field>
46806                    <field>
46807                      <name>BUFFER_SIZE</name>
46808                      <description>The size of the buffer in multiples of 16 bytes</description>
46809                      <bitRange>[15:4]</bitRange>
46810                      <access>read-write</access>
46811                    </field>
46812                    <field>
46813                      <name>BYTE_COUNT</name>
46814                      <description>The number of data bytes present in the buffer.  An occupied buffer is not always full, in particular when variable length packets are transferred.</description>
46815                      <bitRange>[31:16]</bitRange>
46816                      <access>read-write</access>
46817                    </field>
46818                  </fields>
46819                </register>
46820                <register>
46821                  <name>EVENT</name>
46822                  <description>Event Communication Register</description>
46823                  <addressOffset>0x7C</addressOffset>
46824                  <size>32</size>
46825                  <access>write-only</access>
46826                  <resetValue>0x0</resetValue>
46827                  <resetMask>0x1FFFF</resetMask>
46828                  <fields>
46829                    <field>
46830                      <name>ACTIVE_DSCR</name>
46831                      <description>The active descriptor number for which the event is sent.</description>
46832                      <bitRange>[15:0]</bitRange>
46833                      <access>write-only</access>
46834                    </field>
46835                    <field>
46836                      <name>EVENT_TYPE</name>
46837                      <description>Type of event
468380: Consume event descriptor is marked empty - BUFFER_OCCUPIED=0)
468391: Produce event descriptor is marked full = BUFFER_OCCUPIED=1)</description>
46840                      <bitRange>[16:16]</bitRange>
46841                      <access>write-only</access>
46842                    </field>
46843                  </fields>
46844                </register>
46845              </cluster>
46846              <cluster>
46847                <name>SCK_GBL</name>
46848                <description>General DMA Registers</description>
46849                <addressOffset>0x0000FF00</addressOffset>
46850                <register>
46851                  <name>SCK_INTR</name>
46852                  <description>Socket Interrupt Request Register</description>
46853                  <addressOffset>0x0</addressOffset>
46854                  <size>32</size>
46855                  <access>read-only</access>
46856                  <resetValue>0x0</resetValue>
46857                  <resetMask>0xFFFFFFFF</resetMask>
46858                  <fields>
46859                    <field>
46860                      <name>SCKINTR</name>
46861                      <description>Socket &lt;x&gt; asserts interrupt when bit &lt;x&gt; is set in this vector.  Multiple bits may be set to 1 simultaneously.
46862This register is only as wide as the number of socket in the adapter; 256 is just the maximum width.  All other bits always return 0.</description>
46863                      <bitRange>[31:0]</bitRange>
46864                      <access>read-only</access>
46865                    </field>
46866                  </fields>
46867                </register>
46868                <register>
46869                  <name>ADAPTER_DEBUG</name>
46870                  <description>Adapter Debug Observation Register</description>
46871                  <addressOffset>0xF4</addressOffset>
46872                  <size>32</size>
46873                  <access>read-only</access>
46874                  <resetValue>0x0</resetValue>
46875                  <resetMask>0xFFFFFFFF</resetMask>
46876                  <fields>
46877                    <field>
46878                      <name>TS_COUNT</name>
46879                      <description>Internal adapter state for debug observation</description>
46880                      <bitRange>[3:0]</bitRange>
46881                      <access>read-only</access>
46882                    </field>
46883                    <field>
46884                      <name>TS_STATE</name>
46885                      <description>Internal adapter state for debug observation</description>
46886                      <bitRange>[6:4]</bitRange>
46887                      <access>read-only</access>
46888                    </field>
46889                    <field>
46890                      <name>TS_ID</name>
46891                      <description>Internal adapter state for debug observation</description>
46892                      <bitRange>[12:7]</bitRange>
46893                      <access>read-only</access>
46894                    </field>
46895                    <field>
46896                      <name>SS_COUNT</name>
46897                      <description>Internal adapter state for debug observation</description>
46898                      <bitRange>[21:13]</bitRange>
46899                      <access>read-only</access>
46900                    </field>
46901                    <field>
46902                      <name>SS_STATE</name>
46903                      <description>Internal adapter state for debug observation</description>
46904                      <bitRange>[22:22]</bitRange>
46905                      <access>read-only</access>
46906                    </field>
46907                    <field>
46908                      <name>SS_ID</name>
46909                      <description>Internal adapter state for debug observation</description>
46910                      <bitRange>[28:23]</bitRange>
46911                      <access>read-only</access>
46912                    </field>
46913                    <field>
46914                      <name>TS_ABORT</name>
46915                      <description>Internal adapter state for debug observation</description>
46916                      <bitRange>[29:29]</bitRange>
46917                      <access>read-only</access>
46918                    </field>
46919                    <field>
46920                      <name>BS_STATE</name>
46921                      <description>Internal adapter state for debug observation</description>
46922                      <bitRange>[31:30]</bitRange>
46923                      <access>read-only</access>
46924                    </field>
46925                  </fields>
46926                </register>
46927                <register>
46928                  <name>ADAPTER_CONF</name>
46929                  <description>Adapter Configuration Register</description>
46930                  <addressOffset>0xF8</addressOffset>
46931                  <size>32</size>
46932                  <access>read-write</access>
46933                  <resetValue>0x0</resetValue>
46934                  <resetMask>0x7FFFFFFF</resetMask>
46935                  <fields>
46936                    <field>
46937                      <name>FQ_THRESHOLD</name>
46938                      <description>Number of words in a socket fetch queue (FQ) that must be present before sck_active asserts.  Default value is FQ_SIZE, which means the entire FQ must fill up before sck_active asserts.
46939NOTE: The default value for this field is FQ_DEPTH which
46940are different for Egress/Ingress.</description>
46941                      <bitRange>[5:0]</bitRange>
46942                      <access>read-write</access>
46943                    </field>
46944                    <field>
46945                      <name>STREAM_COUNT</name>
46946                      <description>Number of burst requests to issue without examining the FQ depth (because IP Core can guarantee immediate consumption).</description>
46947                      <bitRange>[14:6]</bitRange>
46948                      <access>read-write</access>
46949                    </field>
46950                    <field>
46951                      <name>STREAMING_MODE</name>
46952                      <description>0: Do not make fetch requests unless fetch queue has space to hold response (default).
469531: Assume IP Core will drain all data as it comes in.  Place fetch requests on bus as fast as possible (DO NOT USE UNLESS YOU KNOW WHAT YOU ARE DOING).</description>
46954                      <bitRange>[15:15]</bitRange>
46955                      <access>read-write</access>
46956                    </field>
46957                    <field>
46958                      <name>TS_CYCLES</name>
46959                      <description>Minimum cycles between prefetch requests to the bus.  The adapter will wait for this number of cycles in between prefetch burst requests when activating a descriptor on a socket.  If TS_CYCLES=0, the requests will be sent back-to-back (assuming queues are not full).</description>
46960                      <bitRange>[19:16]</bitRange>
46961                      <access>read-write</access>
46962                    </field>
46963                    <field>
46964                      <name>ES_CYCLES</name>
46965                      <description>Minimum cycles between fetch requests to the bus under normal operation.  The adapter will wait for this number of cycles in between burst requests when refilling a fetch queue for a desriptor  If ES_CYCLES=0, the requests may be sent back-to-back (assuming queues are not full).</description>
46966                      <bitRange>[23:20]</bitRange>
46967                      <access>read-write</access>
46968                    </field>
46969                    <field>
46970                      <name>GBL_CYCLES</name>
46971                      <description>Minimum cycles between any fetch requests to the bus.  The adapter will wait for this number of cycles in between any fetch or prefetch burst requests when activating a descriptor on a socket.  If GBL_CYCLES=0, the requests may be sent back-to-back (assuming queues are not full).</description>
46972                      <bitRange>[27:24]</bitRange>
46973                      <access>read-write</access>
46974                    </field>
46975                    <field>
46976                      <name>MMIO_LOW_PRIORITY</name>
46977                      <description>Sets priority between MMIO and Core requests:
469780: fair arbitration. MMIO is guaranteed to win the next cycle if there was a collision with the core request in the first cycle.
469791: low priority. MMIO will never win if the core has a request.</description>
46980                      <bitRange>[28:28]</bitRange>
46981                      <access>read-write</access>
46982                    </field>
46983                    <field>
46984                      <name>SWITCH_HIGH_PRIORITY</name>
46985                      <description>Socket swicth higher priority than interconnect</description>
46986                      <bitRange>[29:29]</bitRange>
46987                      <access>read-write</access>
46988                    </field>
46989                    <field>
46990                      <name>TS_ABORT_EN</name>
46991                      <description>Allow TS to be aborted</description>
46992                      <bitRange>[30:30]</bitRange>
46993                      <access>read-write</access>
46994                    </field>
46995                  </fields>
46996                </register>
46997                <register>
46998                  <name>ADAPTER_STATUS</name>
46999                  <description>Adapter Global Status Fields</description>
47000                  <addressOffset>0xFC</addressOffset>
47001                  <size>32</size>
47002                  <access>read-only</access>
47003                  <resetValue>0x0</resetValue>
47004                  <resetMask>0xFFFFFF</resetMask>
47005                  <fields>
47006                    <field>
47007                      <name>TTL_SOCKETS</name>
47008                      <description>Total number of sockets in this adapter.  This number is different for each instance of the adapter and varies with the core IP needs.</description>
47009                      <bitRange>[7:0]</bitRange>
47010                      <access>read-only</access>
47011                    </field>
47012                    <field>
47013                      <name>IG_ONLY</name>
47014                      <description>First socket number that is ingress only.
470150..IG_ONLY-1:   Sockets capable of both in and egress
47016IG_ONLY..TTL_SOCKETS-1:  Ingress sockets only</description>
47017                      <bitRange>[15:8]</bitRange>
47018                      <access>read-only</access>
47019                    </field>
47020                    <field>
47021                      <name>FQ_SIZE</name>
47022                      <description>Number of words in a socket fetch queue (FQ).  The total buffer space in the adapter is EG_SOCKETS*FQ_SIZE words of size WORD_SIZE.</description>
47023                      <bitRange>[21:16]</bitRange>
47024                      <access>read-only</access>
47025                    </field>
47026                    <field>
47027                      <name>WORD_SIZE</name>
47028                      <description>Internal word size of the prefetch queue (FQ); not the same as bus width of AHB bus or thread interface to the IP.
470290: 32b
470301: 64b
470312: 128b
470323: 256b</description>
47033                      <bitRange>[23:22]</bitRange>
47034                      <access>read-only</access>
47035                    </field>
47036                  </fields>
47037                </register>
47038              </cluster>
47039            </cluster>
47040          </cluster>
47041        </cluster>
47042      </registers>
47043    </peripheral>
47044    <peripheral>
47045      <name>LVDSSS</name>
47046      <description>LVDS IP Registers</description>
47047      <baseAddress>0x404C0000</baseAddress>
47048      <addressBlock>
47049        <offset>0</offset>
47050        <size>65536</size>
47051        <usage>registers</usage>
47052      </addressBlock>
47053      <registers>
47054        <cluster>
47055          <name>LVDS</name>
47056          <description>LVDS IP register map</description>
47057          <addressOffset>0x00000000</addressOffset>
47058          <register>
47059            <name>CTL</name>
47060            <description>IP Control Register</description>
47061            <addressOffset>0x0</addressOffset>
47062            <size>32</size>
47063            <access>read-write</access>
47064            <resetValue>0x0</resetValue>
47065            <resetMask>0x80000003</resetMask>
47066            <fields>
47067              <field>
47068                <name>PHY_ENABLED</name>
47069                <description>0 - PHY is under reset(excluding non-retention config registers) untill re-enabled again
470701 - PHY is enabled and out of reset</description>
47071                <bitRange>[0:0]</bitRange>
47072                <access>read-write</access>
47073              </field>
47074              <field>
47075                <name>LINK_ENABLED</name>
47076                <description>0 - LINK_LAYER is under reset(excluding non-retention config registers) untill re-enabled again
470771 - LINK_LAYER is enabled and out of reset</description>
47078                <bitRange>[1:1]</bitRange>
47079                <access>read-write</access>
47080              </field>
47081              <field>
47082                <name>IP_ENABLED</name>
47083                <description>0 - IP is held under reset(excluding non-retention config registers) untill re-enabled again.
470841 - IP is enabled and out of reset.</description>
47085                <bitRange>[31:31]</bitRange>
47086                <access>read-write</access>
47087              </field>
47088            </fields>
47089          </register>
47090          <register>
47091            <dim>2</dim>
47092            <dimIncrement>4</dimIncrement>
47093            <name>LINK_CONFIG[%s]</name>
47094            <description>Link Configuration Register</description>
47095            <addressOffset>0x4</addressOffset>
47096            <size>32</size>
47097            <access>read-write</access>
47098            <resetValue>0x0</resetValue>
47099            <resetMask>0x17F</resetMask>
47100            <fields>
47101              <field>
47102                <name>LVDS_MODE</name>
47103                <description>Controls if link in configured as LVCMOS or LVDS link.
471040 - LVCMOS
471051 - LVDS</description>
47106                <bitRange>[0:0]</bitRange>
47107                <access>read-write</access>
47108              </field>
47109              <field>
47110                <name>GEARING_RATIO</name>
47111                <description>Indicates geraing ratio used by lanes of the link
471120 - 1:1
471131 - 2:1
471142 - 4:1
471153 - 8:1
47116
47117In case of LVCMOS, Max gearing ratio to be used is 2:1</description>
47118                <bitRange>[2:1]</bitRange>
47119                <access>read-write</access>
47120              </field>
47121              <field>
47122                <name>WIDE_LINK</name>
47123                <description>If set to 1, it implies both links are combined to form a wide link.
47124This should be set only for link-0.
47125Link-1 should always have this bit programmed to 0.</description>
47126                <bitRange>[3:3]</bitRange>
47127                <access>read-write</access>
47128              </field>
47129              <field>
47130                <name>NUM_LANES</name>
47131                <description>Indicates number of differential Lanes active for LVDS port. In case of LVCMOS indicates number of singled-ended Lanes active per port.
47132
47133For LVDS:
471340 - 1x lane active. Ie Lane[0]
471351 -  2x Lanes active. Ie Lane[1:0]
471362 -  4x lanes active. Ie Lane[3:0]
471373 -  8x lanes active ie Lane[7:0]
471384 -  16x lanes active ie { Lane1[7:0], Lane0[7:0] }
47139
47140For LVCMOS,
471410 - 8-lines active. ie Lane[7:0]
471421 - 16-lines active. ie Lane[15:0]
471432 - 24-lines active. ie { Lane1[7:0], Lane0[15:0] }
471443 - 32-lines active. ie { Lane1[15:0], Lane0[15:0] }
47145
47146If 2-ports/links are combined to form a wider link, then GPIF-0 will serve this wider link and SW shouldn't enable GPIF-1</description>
47147                <bitRange>[6:4]</bitRange>
47148                <access>read-write</access>
47149              </field>
47150              <field>
47151                <name>LINK_ENABLE</name>
47152                <description>When set Link is enabled</description>
47153                <bitRange>[8:8]</bitRange>
47154                <access>read-write</access>
47155              </field>
47156            </fields>
47157          </register>
47158          <register>
47159            <name>THREAD_INTLV_CTL</name>
47160            <description>Thread interleave control register</description>
47161            <addressOffset>0xC</addressOffset>
47162            <size>32</size>
47163            <access>read-write</access>
47164            <resetValue>0x0</resetValue>
47165            <resetMask>0x3</resetMask>
47166            <fields>
47167              <field>
47168                <name>TH0_TH1_INTERLEAVED</name>
47169                <description>Each thread has dedicated resources like payload count, event count, flags etc.  And in general, only  resources of a thread, specified by FPGA driven commands are updated.
47170
47171When this bit is set Thread 0 resources only are used for both 0 &amp; 1 threads.
47172
47173Sockets/buffers are still maintained separately for both thread 0 &amp; 1, irrespective of the value of this bit field.</description>
47174                <bitRange>[0:0]</bitRange>
47175                <access>read-write</access>
47176              </field>
47177              <field>
47178                <name>TH2_TH3_INTERLEAVED</name>
47179                <description>Each thread has dedicated resources like payload count, event count, flags etc.  And in general, only  resources of a thread, specified by FPGA driven commands are updated.
47180
47181When this bit is set Thread 0 resources only are used for both 2 &amp; 3 threads.
47182
47183Sockets/buffers are still maintained separately for both thread 2 &amp; 3, irrespective of the value of this bit field.</description>
47184                <bitRange>[1:1]</bitRange>
47185                <access>read-write</access>
47186              </field>
47187            </fields>
47188          </register>
47189          <register>
47190            <name>LVDS_INTR</name>
47191            <description>LVDS Interrupt Request Register</description>
47192            <addressOffset>0x10</addressOffset>
47193            <size>32</size>
47194            <access>read-write</access>
47195            <resetValue>0x0</resetValue>
47196            <resetMask>0xFFFF00F7</resetMask>
47197            <fields>
47198              <field>
47199                <name>GPIF0_INTERRUPT</name>
47200                <description>Indicates that the interrupt is from GPIF block. Consult GPIF_INTR register</description>
47201                <bitRange>[0:0]</bitRange>
47202                <access>read-only</access>
47203              </field>
47204              <field>
47205                <name>GPIF1_INTERRUPT</name>
47206                <description>Indicates that the interrupt is from GPIF block. Consult GPIF_INTR register</description>
47207                <bitRange>[1:1]</bitRange>
47208                <access>read-only</access>
47209              </field>
47210              <field>
47211                <name>PHY_INTERRUPT</name>
47212                <description>Indicates that the interrupt is from PHY block. Consult PHY_INTR register</description>
47213                <bitRange>[2:2]</bitRange>
47214                <access>read-only</access>
47215              </field>
47216              <field>
47217                <name>THREAD0_ERR</name>
47218                <description>Thread controller encountered an error and needs attention.  FW clears this bit after handling the error.  The error code is indicated in PIB_ERROR.PIB_ERR_CODE</description>
47219                <bitRange>[4:4]</bitRange>
47220                <access>read-write</access>
47221              </field>
47222              <field>
47223                <name>THREAD1_ERR</name>
47224                <description>Thread controller encountered an error and needs attention.  FW clears this bit after handling the error.  The error code is indicated in PIB_ERROR.PIB_ERR_CODE</description>
47225                <bitRange>[5:5]</bitRange>
47226                <access>read-write</access>
47227              </field>
47228              <field>
47229                <name>THREAD2_ERR</name>
47230                <description>Thread controller encountered an error and needs attention.  FW clears this bit after handling the error.  The error code is indicated in PIB_ERROR.PIB_ERR_CODE</description>
47231                <bitRange>[6:6]</bitRange>
47232                <access>read-write</access>
47233              </field>
47234              <field>
47235                <name>THREAD3_ERR</name>
47236                <description>Thread controller encountered an error and needs attention.  FW clears this bit after handling the error.  The error code is indicated in PIB_ERROR.PIB_ERR_CODE</description>
47237                <bitRange>[7:7]</bitRange>
47238                <access>read-write</access>
47239              </field>
47240              <field>
47241                <name>TH0_HDR_FLGS</name>
47242                <description>Flags which are set by LVDS commands to indicate frame/packet header/footer etc</description>
47243                <bitRange>[19:16]</bitRange>
47244                <access>read-write</access>
47245              </field>
47246              <field>
47247                <name>TH1_HDR_FLGS</name>
47248                <description>Flags which are set by LVDS commands to indicate frame/packet header/footer etc</description>
47249                <bitRange>[23:20]</bitRange>
47250                <access>read-write</access>
47251              </field>
47252              <field>
47253                <name>TH2_HDR_FLGS</name>
47254                <description>Flags which are set by LVDS commands to indicate frame/packet header/footer etc</description>
47255                <bitRange>[27:24]</bitRange>
47256                <access>read-write</access>
47257              </field>
47258              <field>
47259                <name>TH3_HDR_FLGS</name>
47260                <description>Flags which are set by LVDS commands to indicate frame/packet header/footer etc</description>
47261                <bitRange>[31:28]</bitRange>
47262                <access>read-write</access>
47263              </field>
47264            </fields>
47265          </register>
47266          <register>
47267            <name>LVDS_INTR_MASK</name>
47268            <description>LVDS Interrupt Mask Register</description>
47269            <addressOffset>0x14</addressOffset>
47270            <size>32</size>
47271            <access>read-write</access>
47272            <resetValue>0x0</resetValue>
47273            <resetMask>0xFFFF00F7</resetMask>
47274            <fields>
47275              <field>
47276                <name>GPIF0_INTERRUPT</name>
47277                <description>Mask for corresponding interrupt in LVDS_INTR</description>
47278                <bitRange>[0:0]</bitRange>
47279                <access>read-write</access>
47280              </field>
47281              <field>
47282                <name>GPIF1_INTERRUPT</name>
47283                <description>Mask for corresponding interrupt in LVDS_INTR</description>
47284                <bitRange>[1:1]</bitRange>
47285                <access>read-write</access>
47286              </field>
47287              <field>
47288                <name>PHY_INTERRUPT</name>
47289                <description>Mask for corresponding interrupt in LVDS_INTR</description>
47290                <bitRange>[2:2]</bitRange>
47291                <access>read-write</access>
47292              </field>
47293              <field>
47294                <name>THREAD0_ERR</name>
47295                <description>Mask for corresponding interrupt in LVDS_INTR</description>
47296                <bitRange>[4:4]</bitRange>
47297                <access>read-write</access>
47298              </field>
47299              <field>
47300                <name>THREAD1_ERR</name>
47301                <description>Mask for corresponding interrupt in LVDS_INTR</description>
47302                <bitRange>[5:5]</bitRange>
47303                <access>read-write</access>
47304              </field>
47305              <field>
47306                <name>THREAD2_ERR</name>
47307                <description>Mask for corresponding interrupt in LVDS_INTR</description>
47308                <bitRange>[6:6]</bitRange>
47309                <access>read-write</access>
47310              </field>
47311              <field>
47312                <name>THREAD3_ERR</name>
47313                <description>Mask for corresponding interrupt in LVDS_INTR</description>
47314                <bitRange>[7:7]</bitRange>
47315                <access>read-write</access>
47316              </field>
47317              <field>
47318                <name>TH0_HDR_FLGS</name>
47319                <description>Mask for corresponding interrupt in LVDS_INTR</description>
47320                <bitRange>[19:16]</bitRange>
47321                <access>read-write</access>
47322              </field>
47323              <field>
47324                <name>TH1_HDR_FLGS</name>
47325                <description>Mask for corresponding interrupt in LVDS_INTR</description>
47326                <bitRange>[23:20]</bitRange>
47327                <access>read-write</access>
47328              </field>
47329              <field>
47330                <name>TH2_HDR_FLGS</name>
47331                <description>Mask for corresponding interrupt in LVDS_INTR</description>
47332                <bitRange>[27:24]</bitRange>
47333                <access>read-write</access>
47334              </field>
47335              <field>
47336                <name>TH3_HDR_FLGS</name>
47337                <description>Mask for corresponding interrupt in LVDS_INTR</description>
47338                <bitRange>[31:28]</bitRange>
47339                <access>read-write</access>
47340              </field>
47341            </fields>
47342          </register>
47343          <register>
47344            <name>LVDS_ERROR</name>
47345            <description>LVDS Error Indicator Register</description>
47346            <addressOffset>0x20</addressOffset>
47347            <size>32</size>
47348            <access>read-only</access>
47349            <resetValue>0x0</resetValue>
47350            <resetMask>0xFFFFF</resetMask>
47351            <fields>
47352              <field>
47353                <name>THREAD0_ERR_CODE</name>
47354                <description>The socket based link controller encountered an error and needs attention. Error codes are further described in BROS.  Corresponds to interrupt bit THREAD_ERROR.</description>
47355                <bitRange>[4:0]</bitRange>
47356                <access>read-only</access>
47357                <enumeratedValues>
47358                  <enumeratedValue>
47359                    <name>TH0_DIR_ERROR</name>
47360                    <description>Write being done to a Read Socket or Read being done to a write skt</description>
47361                    <value>0</value>
47362                  </enumeratedValue>
47363                </enumeratedValues>
47364              </field>
47365              <field>
47366                <name>THREAD1_ERR_CODE</name>
47367                <description>The socket based link controller encountered an error and needs attention. Error codes are further described in BROS.  Corresponds to interrupt bit THREAD_ERROR.</description>
47368                <bitRange>[9:5]</bitRange>
47369                <access>read-only</access>
47370                <enumeratedValues>
47371                  <enumeratedValue>
47372                    <name>TH1_DIR_ERROR</name>
47373                    <description>Write being done to a Read Socket or Read being done to a write skt</description>
47374                    <value>0</value>
47375                  </enumeratedValue>
47376                </enumeratedValues>
47377              </field>
47378              <field>
47379                <name>THREAD2_ERR_CODE</name>
47380                <description>The socket based link controller encountered an error and needs attention. Error codes are further described in BROS.  Corresponds to interrupt bit THREAD_ERROR.</description>
47381                <bitRange>[14:10]</bitRange>
47382                <access>read-only</access>
47383                <enumeratedValues>
47384                  <enumeratedValue>
47385                    <name>TH2_DIR_ERROR</name>
47386                    <description>Write being done to a Read Socket or Read being done to a write skt</description>
47387                    <value>0</value>
47388                  </enumeratedValue>
47389                </enumeratedValues>
47390              </field>
47391              <field>
47392                <name>THREAD3_ERR_CODE</name>
47393                <description>The socket based link controller encountered an error and needs attention. Error codes are further described in BROS.  Corresponds to interrupt bit THREAD_ERROR.</description>
47394                <bitRange>[19:15]</bitRange>
47395                <access>read-only</access>
47396                <enumeratedValues>
47397                  <enumeratedValue>
47398                    <name>TH3_DIR_ERROR</name>
47399                    <description>Write being done to a Read Socket or Read being done to a write skt</description>
47400                    <value>0</value>
47401                  </enumeratedValue>
47402                </enumeratedValues>
47403              </field>
47404            </fields>
47405          </register>
47406          <register>
47407            <name>LVDS_EOP_EOT</name>
47408            <description>LVDS EOP/EOT configuration</description>
47409            <addressOffset>0x24</addressOffset>
47410            <size>32</size>
47411            <access>read-write</access>
47412            <resetValue>0x1</resetValue>
47413            <resetMask>0xFFFFFFFF</resetMask>
47414            <fields>
47415              <field>
47416                <name>EOP_EOT_CFG</name>
47417                <description>This register specifies how EOP bits are set or interpretted for Ingress and Egress sockets respectively.
474181: Packet mode behavior
474190: Stream mode behavior
47420See Architecture Spec for details.</description>
47421                <bitRange>[31:0]</bitRange>
47422                <access>read-write</access>
47423              </field>
47424            </fields>
47425          </register>
47426          <register>
47427            <name>GPIF_DATA_CTRL</name>
47428            <description>Data Control Register</description>
47429            <addressOffset>0x30</addressOffset>
47430            <size>32</size>
47431            <access>read-write</access>
47432            <resetValue>0x0</resetValue>
47433            <resetMask>0xFFFF</resetMask>
47434            <fields>
47435              <field>
47436                <name>ING_DATA_VALID</name>
47437                <description>Indicates data available in INGRESS_DATA.  Cleared by s/w when data processed.</description>
47438                <bitRange>[3:0]</bitRange>
47439                <access>read-write</access>
47440              </field>
47441              <field>
47442                <name>EG_DATA_VALID</name>
47443                <description>Software writes 1 to indicate a valid word is present in the address register.  Hardware writes 0 to indicate that the data is used and new word can be written.</description>
47444                <bitRange>[7:4]</bitRange>
47445                <access>read-write</access>
47446              </field>
47447              <field>
47448                <name>IN_ADDR_VALID</name>
47449                <description>Indicates address available in INGRESS_ADDRESS.  Cleared by s/w when address processed.</description>
47450                <bitRange>[11:8]</bitRange>
47451                <access>read-write</access>
47452              </field>
47453              <field>
47454                <name>EG_ADDR_VALID</name>
47455                <description>Software writes 1 to indicate a valid word is present in the address register.  Hardware writes 0 to indicate that the data is used and new word can be written.</description>
47456                <bitRange>[15:12]</bitRange>
47457                <access>read-write</access>
47458              </field>
47459            </fields>
47460          </register>
47461          <register>
47462            <dim>2</dim>
47463            <dimIncrement>4</dimIncrement>
47464            <name>GPIF_CLK_SEL[%s]</name>
47465            <description>GPIF Clock selection Register</description>
47466            <addressOffset>0x34</addressOffset>
47467            <size>32</size>
47468            <access>read-write</access>
47469            <resetValue>0x4</resetValue>
47470            <resetMask>0xD</resetMask>
47471            <fields>
47472              <field>
47473                <name>GPIC_CLK_SRC</name>
47474                <description>GPIF runs on clock which has different sources. This register field selects the clock sources.
474750 - usb 480 MHz clock source
474761 - peri clock</description>
47477                <bitRange>[0:0]</bitRange>
47478                <access>read-write</access>
47479              </field>
47480              <field>
47481                <name>USB_CLK_DIV_VAL</name>
47482                <description>This register field is valid only when GPIF clock source is USB 480MHz clock.
474830 - Invalid
474841 - Div by 2
474852 - Div by 3
474863 - Div by 4</description>
47487                <bitRange>[3:2]</bitRange>
47488                <access>read-write</access>
47489              </field>
47490            </fields>
47491          </register>
47492          <register>
47493            <name>TIME_STAMP_CLK_DW0</name>
47494            <description>Timestamp counter</description>
47495            <addressOffset>0x50</addressOffset>
47496            <size>32</size>
47497            <access>read-only</access>
47498            <resetValue>0x0</resetValue>
47499            <resetMask>0xFFFFFFFF</resetMask>
47500            <fields>
47501              <field>
47502                <name>TS_WD0</name>
47503                <description>LSB 2-bytes of free running timestamp counter.</description>
47504                <bitRange>[15:0]</bitRange>
47505                <access>read-only</access>
47506              </field>
47507              <field>
47508                <name>TS_WD1</name>
47509                <description>Middle 2-bytes of free running timestamp counter.</description>
47510                <bitRange>[31:16]</bitRange>
47511                <access>read-only</access>
47512              </field>
47513            </fields>
47514          </register>
47515          <register>
47516            <name>TIME_STAMP_CLK_DW1</name>
47517            <description>Timestamp counter</description>
47518            <addressOffset>0x54</addressOffset>
47519            <size>32</size>
47520            <access>read-only</access>
47521            <resetValue>0x0</resetValue>
47522            <resetMask>0xFFFFFFFF</resetMask>
47523            <fields>
47524              <field>
47525                <name>TS_WD2</name>
47526                <description>Middle 2-bytes of free running timestamp counter.</description>
47527                <bitRange>[15:0]</bitRange>
47528                <access>read-only</access>
47529              </field>
47530              <field>
47531                <name>TS_WD3</name>
47532                <description>MSB 2-bytes of free running timestamp counter.</description>
47533                <bitRange>[31:16]</bitRange>
47534                <access>read-only</access>
47535              </field>
47536            </fields>
47537          </register>
47538          <register>
47539            <dim>64</dim>
47540            <dimIncrement>4</dimIncrement>
47541            <name>TH0_TH1_METADATA_RAM[%s]</name>
47542            <description>Metadata Memory</description>
47543            <addressOffset>0x100</addressOffset>
47544            <size>32</size>
47545            <access>read-write</access>
47546            <resetValue>0x0</resetValue>
47547            <resetMask>0xFFFFFFFF</resetMask>
47548            <fields>
47549              <field>
47550                <name>METADATA</name>
47551                <description>Metadata</description>
47552                <bitRange>[31:0]</bitRange>
47553                <access>read-write</access>
47554              </field>
47555            </fields>
47556          </register>
47557          <register>
47558            <dim>64</dim>
47559            <dimIncrement>4</dimIncrement>
47560            <name>TH2_TH3_METADATA_RAM[%s]</name>
47561            <description>Metadata Memory</description>
47562            <addressOffset>0x200</addressOffset>
47563            <size>32</size>
47564            <access>read-write</access>
47565            <resetValue>0x0</resetValue>
47566            <resetMask>0xFFFFFFFF</resetMask>
47567            <fields>
47568              <field>
47569                <name>METADATA</name>
47570                <description>Metadata</description>
47571                <bitRange>[31:0]</bitRange>
47572                <access>read-write</access>
47573              </field>
47574            </fields>
47575          </register>
47576          <cluster>
47577            <dim>4</dim>
47578            <dimIncrement>128</dimIncrement>
47579            <name>THREAD[%s]</name>
47580            <description>Set of registers for a thread</description>
47581            <addressOffset>0x00000400</addressOffset>
47582            <register>
47583              <name>GPIF_INGRESS_DATA_WORD0</name>
47584              <description>Socket Ingress Data</description>
47585              <addressOffset>0x0</addressOffset>
47586              <size>32</size>
47587              <access>read-only</access>
47588              <resetValue>0x0</resetValue>
47589              <resetMask>0xFFFFFFFF</resetMask>
47590              <fields>
47591                <field>
47592                  <name>DATA</name>
47593                  <description>Ingress Data.  4 registers together will hold 128-bits of GPIF_BUS_CONFIG.BUS_WIDTH.  No packing/unpacking is done.  MSB's of combined value {WORD3, WORD2, WORD1, WORD0} will be 0s</description>
47594                  <bitRange>[31:0]</bitRange>
47595                  <access>read-only</access>
47596                </field>
47597              </fields>
47598            </register>
47599            <register>
47600              <name>GPIF_INGRESS_DATA_WORD1</name>
47601              <description>Socket Ingress Data</description>
47602              <addressOffset>0x4</addressOffset>
47603              <size>32</size>
47604              <access>read-only</access>
47605              <resetValue>0x0</resetValue>
47606              <resetMask>0xFFFFFFFF</resetMask>
47607              <fields>
47608                <field>
47609                  <name>DATA</name>
47610                  <description>Ingress Data.  4 registers together will hold 128-bits of GPIF_BUS_CONFIG.BUS_WIDTH.  No packing/unpacking is done.  MSB's of combined value {WORD3, WORD2, WORD1, WORD0} will be 0s</description>
47611                  <bitRange>[31:0]</bitRange>
47612                  <access>read-only</access>
47613                </field>
47614              </fields>
47615            </register>
47616            <register>
47617              <name>GPIF_INGRESS_DATA_WORD2</name>
47618              <description>Socket Ingress Data</description>
47619              <addressOffset>0x8</addressOffset>
47620              <size>32</size>
47621              <access>read-only</access>
47622              <resetValue>0x0</resetValue>
47623              <resetMask>0xFFFFFFFF</resetMask>
47624              <fields>
47625                <field>
47626                  <name>DATA</name>
47627                  <description>Ingress Data.  4 registers together will hold 128-bits of GPIF_BUS_CONFIG.BUS_WIDTH.  No packing/unpacking is done.  MSB's of combined value {WORD3, WORD2, WORD1, WORD0} will be 0s</description>
47628                  <bitRange>[31:0]</bitRange>
47629                  <access>read-only</access>
47630                </field>
47631              </fields>
47632            </register>
47633            <register>
47634              <name>GPIF_INGRESS_DATA_WORD3</name>
47635              <description>Socket Ingress Data</description>
47636              <addressOffset>0xC</addressOffset>
47637              <size>32</size>
47638              <access>read-only</access>
47639              <resetValue>0x0</resetValue>
47640              <resetMask>0xFFFFFFFF</resetMask>
47641              <fields>
47642                <field>
47643                  <name>DATA</name>
47644                  <description>Ingress Data.  4 registers together will hold 128-bits of GPIF_BUS_CONFIG.BUS_WIDTH.  No packing/unpacking is done.  MSB's of combined value {WORD3, WORD2, WORD1, WORD0} will be 0s</description>
47645                  <bitRange>[31:0]</bitRange>
47646                  <access>read-only</access>
47647                </field>
47648              </fields>
47649            </register>
47650            <register>
47651              <name>GPIF_EGRESS_DATA_WORD0</name>
47652              <description>Socket Egress Data</description>
47653              <addressOffset>0x10</addressOffset>
47654              <size>32</size>
47655              <access>read-write</access>
47656              <resetValue>0x0</resetValue>
47657              <resetMask>0xFFFFFFFF</resetMask>
47658              <fields>
47659                <field>
47660                  <name>DATA</name>
47661                  <description>Egress Data.  Both WORD1 and WORD0 will old only 64-bits of GPIF_BUS_CONFIG.BUS_WIDTH.  No packing/unpacking is done.  MSB's of combined value {WORD1, WORD0} is ignored.</description>
47662                  <bitRange>[31:0]</bitRange>
47663                  <access>read-write</access>
47664                </field>
47665              </fields>
47666            </register>
47667            <register>
47668              <name>GPIF_EGRESS_DATA_WORD1</name>
47669              <description>Socket Egress Data</description>
47670              <addressOffset>0x14</addressOffset>
47671              <size>32</size>
47672              <access>read-write</access>
47673              <resetValue>0x0</resetValue>
47674              <resetMask>0xFFFFFFFF</resetMask>
47675              <fields>
47676                <field>
47677                  <name>DATA</name>
47678                  <description>Egress Data.  Both WORD1 and WORD0 will old only 64-bits of GPIF_BUS_CONFIG.BUS_WIDTH.  No packing/unpacking is done.  MSB's of combined value {WORD1, WORD0} is ignored.</description>
47679                  <bitRange>[31:0]</bitRange>
47680                  <access>read-write</access>
47681                </field>
47682              </fields>
47683            </register>
47684            <register>
47685              <name>GPIF_INGRESS_ADDRESS</name>
47686              <description>Thread Ingress Address</description>
47687              <addressOffset>0x18</addressOffset>
47688              <size>32</size>
47689              <access>read-only</access>
47690              <resetValue>0x0</resetValue>
47691              <resetMask>0xFFFFFFFF</resetMask>
47692              <fields>
47693                <field>
47694                  <name>ADDRESS</name>
47695                  <description>Ingress Address</description>
47696                  <bitRange>[31:0]</bitRange>
47697                  <access>read-only</access>
47698                </field>
47699              </fields>
47700            </register>
47701            <register>
47702              <name>GPIF_EGRESS_ADDRESS</name>
47703              <description>Thread Egress Address</description>
47704              <addressOffset>0x1C</addressOffset>
47705              <size>32</size>
47706              <access>read-write</access>
47707              <resetValue>0x0</resetValue>
47708              <resetMask>0xFFFFFFFF</resetMask>
47709              <fields>
47710                <field>
47711                  <name>ADDRESS</name>
47712                  <description>Egress Address</description>
47713                  <bitRange>[31:0]</bitRange>
47714                  <access>read-write</access>
47715                </field>
47716              </fields>
47717            </register>
47718            <register>
47719              <name>GPIF_THREAD_CONFIG</name>
47720              <description>Thread Configuration Register</description>
47721              <addressOffset>0x20</addressOffset>
47722              <size>32</size>
47723              <access>read-write</access>
47724              <resetValue>0x10400</resetValue>
47725              <resetMask>0xBFFF0F9F</resetMask>
47726              <fields>
47727                <field>
47728                  <name>THREAD_SOCK</name>
47729                  <description>Active Socket Number for this thread.
47730Can be written by software for fixed socket assignment.(all threads)
47731Can be modified by h/w as result of PP_DMA_XFER accesses (only for thread 0)
47732Can be modified by h/w as result of alpha 'sample AIN' (all threads. HW can only modify bits [4:2] of this field)</description>
47733                  <bitRange>[4:0]</bitRange>
47734                  <access>read-write</access>
47735                </field>
47736                <field>
47737                  <name>WM_CFG</name>
47738                  <description>0: Assert partial flag when number of samples (remaining available for reading/writing) is less than or equal to the watermark.
477391: Assert when samples are more than the watermark.</description>
47740                  <bitRange>[7:7]</bitRange>
47741                  <access>read-write</access>
47742                </field>
47743                <field>
47744                  <name>BURST_SIZE</name>
47745                  <description>Log2 of burst size ( 1: 2 words, 2: 4 words, etc). Programmed to support systems that work with fixed burst sizes. A burst is defined as a portion of transfer that  unconditionally completes once initiated. The system must always transfer an entire burst before responding to a change in a partial flag . In transfers that involve short packet, the PIB HW will automatically append zeros/truncate data to do its part  in preserving the above mentioned definition of burst. Burst size is a power of 2 and must be programmed to a value greater than watermark when partial flag is used.Buffer sizes used should be integral multiple of the burst size. Maximum value is 14.  When value is &gt;0, any socket switching must occur on 8 byte boundaries.Besides, this field needs to be programmed to a non-zero value to support bandwidth&gt;200MBps on P-Port.</description>
47746                  <bitRange>[11:8]</bitRange>
47747                  <access>read-write</access>
47748                </field>
47749                <field>
47750                  <name>WATERMARK</name>
47751                  <description>Watermark position. Indicates number words that would be subtracted from the end of usable space/data. Watermark needs to be programmed to a value greater than the round trip flag latency of the system.
47752
47753This latency is a sum of three quantities namely  (1) Benicia latency between seeing the end of the last burst that completely fills the buffer to the time the full/empty flag updates (can be calculated from generic gpif params), (2). Expected time of arrival of a flow control signal that would prevent the AP from issuing the next burst (as measured from the end of the burst) (3). Any additional group latency between the APs dma controller logic and the interface pins in both directions.
47754
47755 'end of usable space/data' is calculated using one of the equations depending on the context. (1) For normal write transfers in either PP modes,  this is the size of the buffer to be produced into.  (2) For normal read transfers in either PP modes, this is the byte count of the buffer to be consumed. (3) For partial buffer read or write transfers in PP mode 1, this is the value of written by AP into the PP_DMA_SIZE register rounded up to an integral number of BURSTSIZE quanta.</description>
47756                  <bitRange>[29:16]</bitRange>
47757                  <access>read-write</access>
47758                </field>
47759                <field>
47760                  <name>ENABLE_THREAD_CTLR</name>
47761                  <description>Enables the threadcontroller for operation.  Can be set by firmware after initializing THEAD_SOCK and other fields.  Will be set by h/w when THREAD_SOCK is written to by h/w.</description>
47762                  <bitRange>[31:31]</bitRange>
47763                  <access>read-write</access>
47764                </field>
47765              </fields>
47766            </register>
47767            <register>
47768              <name>VARW</name>
47769              <description>Variable Register</description>
47770              <addressOffset>0x30</addressOffset>
47771              <size>32</size>
47772              <access>read-only</access>
47773              <resetValue>0x0</resetValue>
47774              <resetMask>0xFFFFFFFF</resetMask>
47775              <fields>
47776                <field>
47777                  <name>VARW_WD0</name>
47778                  <description>Variable Word 0</description>
47779                  <bitRange>[15:0]</bitRange>
47780                  <access>read-only</access>
47781                </field>
47782                <field>
47783                  <name>VARW_WD1</name>
47784                  <description>Variable Word 1</description>
47785                  <bitRange>[31:16]</bitRange>
47786                  <access>read-only</access>
47787                </field>
47788              </fields>
47789            </register>
47790            <register>
47791              <name>PTSSS</name>
47792              <description>PTS snapshot register</description>
47793              <addressOffset>0x34</addressOffset>
47794              <size>32</size>
47795              <access>read-only</access>
47796              <resetValue>0x0</resetValue>
47797              <resetMask>0xFFFFFFFF</resetMask>
47798              <fields>
47799                <field>
47800                  <name>PTSSS_WD0</name>
47801                  <description>PTS timer value</description>
47802                  <bitRange>[15:0]</bitRange>
47803                  <access>read-only</access>
47804                </field>
47805                <field>
47806                  <name>PTSSS_WD1</name>
47807                  <description>PTS timer value</description>
47808                  <bitRange>[31:16]</bitRange>
47809                  <access>read-only</access>
47810                </field>
47811              </fields>
47812            </register>
47813            <register>
47814              <name>SCRSS_DW0</name>
47815              <description>SCR snapshot register</description>
47816              <addressOffset>0x38</addressOffset>
47817              <size>32</size>
47818              <access>read-only</access>
47819              <resetValue>0x0</resetValue>
47820              <resetMask>0xFFFFFFFF</resetMask>
47821              <fields>
47822                <field>
47823                  <name>SCRSS_WD0</name>
47824                  <description>LSB 2-bytes of SCR timer value</description>
47825                  <bitRange>[15:0]</bitRange>
47826                  <access>read-only</access>
47827                </field>
47828                <field>
47829                  <name>SCRSS_WD1</name>
47830                  <description>Middle 2-bytes of SCR timer value</description>
47831                  <bitRange>[31:16]</bitRange>
47832                  <access>read-only</access>
47833                </field>
47834              </fields>
47835            </register>
47836            <register>
47837              <name>SCRSS_DW1</name>
47838              <description>SCR snapshot register</description>
47839              <addressOffset>0x3C</addressOffset>
47840              <size>32</size>
47841              <access>read-only</access>
47842              <resetValue>0x0</resetValue>
47843              <resetMask>0xFFFF</resetMask>
47844              <fields>
47845                <field>
47846                  <name>SCRSS_WD2</name>
47847                  <description>MSB 2-bytes of SCR timer, which is nothing but frame number</description>
47848                  <bitRange>[15:0]</bitRange>
47849                  <access>read-only</access>
47850                </field>
47851              </fields>
47852            </register>
47853            <register>
47854              <name>HDR_FLGS</name>
47855              <description>Header Flags</description>
47856              <addressOffset>0x40</addressOffset>
47857              <size>32</size>
47858              <access>read-only</access>
47859              <resetValue>0x0</resetValue>
47860              <resetMask>0xF</resetMask>
47861              <fields>
47862                <field>
47863                  <name>FLG</name>
47864                  <description>Flags for indicating frame/line/packet header, footer etc.
47865These flags will be set or clear by FPGA. Setting/Clearing of these flags will raise an interrupt to CPU.</description>
47866                  <bitRange>[3:0]</bitRange>
47867                  <access>read-only</access>
47868                </field>
47869              </fields>
47870            </register>
47871            <register>
47872              <name>EVC_VAR0_DW0</name>
47873              <description>Event Count Variable0</description>
47874              <addressOffset>0x50</addressOffset>
47875              <size>32</size>
47876              <access>read-only</access>
47877              <resetValue>0x0</resetValue>
47878              <resetMask>0xFFFFFFFF</resetMask>
47879              <fields>
47880                <field>
47881                  <name>EVC_V0_WD0</name>
47882                  <description>Bytes 1 and 0 of 8-byte event counter</description>
47883                  <bitRange>[15:0]</bitRange>
47884                  <access>read-only</access>
47885                </field>
47886                <field>
47887                  <name>EVC_V0_WD1</name>
47888                  <description>Bytes 2 and 3 of 8-byte event counter</description>
47889                  <bitRange>[31:16]</bitRange>
47890                  <access>read-only</access>
47891                </field>
47892              </fields>
47893            </register>
47894            <register>
47895              <name>EVC_VAR0_DW1</name>
47896              <description>Event Count Variable0</description>
47897              <addressOffset>0x54</addressOffset>
47898              <size>32</size>
47899              <access>read-only</access>
47900              <resetValue>0x0</resetValue>
47901              <resetMask>0xFFFFFFFF</resetMask>
47902              <fields>
47903                <field>
47904                  <name>EVC_V0_WD2</name>
47905                  <description>Bytes 5 and 4 of 8-byte event counter</description>
47906                  <bitRange>[15:0]</bitRange>
47907                  <access>read-only</access>
47908                </field>
47909                <field>
47910                  <name>EVC_V0_WD3</name>
47911                  <description>Bytes 7 and 6 of 8-byte event counter</description>
47912                  <bitRange>[31:16]</bitRange>
47913                  <access>read-only</access>
47914                </field>
47915              </fields>
47916            </register>
47917            <register>
47918              <name>EVC_VAR1_DW0</name>
47919              <description>Event Count Variable1</description>
47920              <addressOffset>0x58</addressOffset>
47921              <size>32</size>
47922              <access>read-only</access>
47923              <resetValue>0x0</resetValue>
47924              <resetMask>0xFFFFFFFF</resetMask>
47925              <fields>
47926                <field>
47927                  <name>EVC_V1_WD0</name>
47928                  <description>Bytes 1 and 0 of 8-byte event counter</description>
47929                  <bitRange>[15:0]</bitRange>
47930                  <access>read-only</access>
47931                </field>
47932                <field>
47933                  <name>EVC_V1_WD1</name>
47934                  <description>Bytes 2 and 3 of 8-byte event counter</description>
47935                  <bitRange>[31:16]</bitRange>
47936                  <access>read-only</access>
47937                </field>
47938              </fields>
47939            </register>
47940            <register>
47941              <name>EVC_VAR1_DW1</name>
47942              <description>Event Count Variable1</description>
47943              <addressOffset>0x5C</addressOffset>
47944              <size>32</size>
47945              <access>read-only</access>
47946              <resetValue>0x0</resetValue>
47947              <resetMask>0xFFFFFFFF</resetMask>
47948              <fields>
47949                <field>
47950                  <name>EVC_V1_WD2</name>
47951                  <description>Bytes 5 and 4 of 8-byte event counter</description>
47952                  <bitRange>[15:0]</bitRange>
47953                  <access>read-only</access>
47954                </field>
47955                <field>
47956                  <name>EVC_V1_WD3</name>
47957                  <description>Bytes 7 and 6 of 8-byte event counter</description>
47958                  <bitRange>[31:16]</bitRange>
47959                  <access>read-only</access>
47960                </field>
47961              </fields>
47962            </register>
47963            <register>
47964              <name>PLC_DW0</name>
47965              <description>Payload Count register</description>
47966              <addressOffset>0x60</addressOffset>
47967              <size>32</size>
47968              <access>read-only</access>
47969              <resetValue>0x0</resetValue>
47970              <resetMask>0xFFFFFFFF</resetMask>
47971              <fields>
47972                <field>
47973                  <name>PLC_WD0</name>
47974                  <description>Bytes 1 and 0 of 8-byte data payload counter. Gets incremented during data transfers if EPC (Enable Payload Count), command was sent on LVDS control lane previously</description>
47975                  <bitRange>[15:0]</bitRange>
47976                  <access>read-only</access>
47977                </field>
47978                <field>
47979                  <name>PLC_WD1</name>
47980                  <description>Bytes 3 and 2 of 8-byte of data payload counter. Gets incremented during data transfers if EPC (Enable Payload Count), command was sent on LVDS control lane previously</description>
47981                  <bitRange>[31:16]</bitRange>
47982                  <access>read-only</access>
47983                </field>
47984              </fields>
47985            </register>
47986            <register>
47987              <name>PLC_DW1</name>
47988              <description>Payload Count register</description>
47989              <addressOffset>0x64</addressOffset>
47990              <size>32</size>
47991              <access>read-only</access>
47992              <resetValue>0x0</resetValue>
47993              <resetMask>0xFFFFFFFF</resetMask>
47994              <fields>
47995                <field>
47996                  <name>PLC_WD2</name>
47997                  <description>Bytes 5 and 4 of 8-byte data payload counter. Gets incremented during data transfers if EPC (Enable Payload Count), command was sent on LVDS control lane previously</description>
47998                  <bitRange>[15:0]</bitRange>
47999                  <access>read-only</access>
48000                </field>
48001                <field>
48002                  <name>PLC_WD3</name>
48003                  <description>Bytes 7 and 6 of 8-byte of data payload counter. Gets incremented during data transfers if EPC (Enable Payload Count), command was sent on LVDS control lane previously</description>
48004                  <bitRange>[31:16]</bitRange>
48005                  <access>read-only</access>
48006                </field>
48007              </fields>
48008            </register>
48009            <register>
48010              <name>PAYLOAD_CFG</name>
48011              <description>Payload Config register</description>
48012              <addressOffset>0x68</addressOffset>
48013              <size>32</size>
48014              <access>read-write</access>
48015              <resetValue>0x0</resetValue>
48016              <resetMask>0x3</resetMask>
48017              <fields>
48018                <field>
48019                  <name>CNT_MDATA_AS_PAYLOAD</name>
48020                  <description>Include metadata as part of payload count</description>
48021                  <bitRange>[0:0]</bitRange>
48022                  <access>read-write</access>
48023                </field>
48024                <field>
48025                  <name>CNT_CRC_AS_PAYLOAD</name>
48026                  <description>Include CRC  as part of payload count</description>
48027                  <bitRange>[1:1]</bitRange>
48028                  <access>read-write</access>
48029                </field>
48030              </fields>
48031            </register>
48032            <register>
48033              <name>CRC</name>
48034              <description>CRC</description>
48035              <addressOffset>0x6C</addressOffset>
48036              <size>32</size>
48037              <access>read-write</access>
48038              <resetValue>0x0</resetValue>
48039              <resetMask>0xFFFFFFFF</resetMask>
48040              <fields>
48041                <field>
48042                  <name>INITIAL_VALUE</name>
48043                  <description>Initial CRC value. Whenever CLRCRC command is received, CRC calculator will be loaded with this initial value.</description>
48044                  <bitRange>[15:0]</bitRange>
48045                  <access>read-write</access>
48046                </field>
48047                <field>
48048                  <name>CRC_VALUE</name>
48049                  <description>Holds 16-bit CRC calculated on received payload data. Polynomila used is X16 + X12 + X5 + 1</description>
48050                  <bitRange>[31:16]</bitRange>
48051                  <access>read-only</access>
48052                </field>
48053              </fields>
48054            </register>
48055            <register>
48056              <name>MD0_CTRL</name>
48057              <description>Metadata-0 Control word</description>
48058              <addressOffset>0x70</addressOffset>
48059              <size>32</size>
48060              <access>read-write</access>
48061              <resetValue>0x0</resetValue>
48062              <resetMask>0xFFFFFFFF</resetMask>
48063              <fields>
48064                <field>
48065                  <name>MD_REF_CTL</name>
48066                  <description>Each bit of this field controls whether value present in Metadata ram is a constant or reference to a register, whose value should be used as Metadata.
480670 - Metadata constant value
480681 - Reference to Register Variable whose address is specified in Metadata</description>
48069                  <bitRange>[26:0]</bitRange>
48070                  <access>read-write</access>
48071                </field>
48072                <field>
48073                  <name>MD_SIZE</name>
48074                  <description>Holds the size in bytes of metadata to be inserted.
48075Should be programmed to even number only (ie multiple of 2 bytes). Allowed values are 0, 2, 4, 6, 8......30.
480760 - indicates 32 bytes
48077If Odd value is programmed, then it'll be converted to immediate lower even value and used(ie if programmed to 9, it'll be used as 8)</description>
48078                  <bitRange>[31:27]</bitRange>
48079                  <access>read-write</access>
48080                </field>
48081              </fields>
48082            </register>
48083            <register>
48084              <name>MD1_CTRL</name>
48085              <description>Metadata-1 Control word</description>
48086              <addressOffset>0x74</addressOffset>
48087              <size>32</size>
48088              <access>read-write</access>
48089              <resetValue>0x0</resetValue>
48090              <resetMask>0xFFFFFFFF</resetMask>
48091              <fields>
48092                <field>
48093                  <name>MD_REF_CTL</name>
48094                  <description>Each bit of this field controls whether value present in Metadata ram is a constant or reference to a register, whose value should be used as Metadata.
480950 - Metadata constant value
480961 - Reference to Register Variable whose address is specified in Metadata</description>
48097                  <bitRange>[26:0]</bitRange>
48098                  <access>read-write</access>
48099                </field>
48100                <field>
48101                  <name>MD_SIZE</name>
48102                  <description>Holds the size in bytes of metadata to be inserted.
48103Should be programmed to even number only (ie multiple of 2 bytes). Allowed values are 0, 2, 4, 6, 8......30.
481040 - indicates 32 bytes
48105If Odd value is programmed, then it'll be converted to immediate lower even value and used(ie if programmed to 9, it'll be used as 8)</description>
48106                  <bitRange>[31:27]</bitRange>
48107                  <access>read-write</access>
48108                </field>
48109              </fields>
48110            </register>
48111            <register>
48112              <name>MD2_CTRL</name>
48113              <description>Metadata-2 Control word</description>
48114              <addressOffset>0x78</addressOffset>
48115              <size>32</size>
48116              <access>read-write</access>
48117              <resetValue>0x0</resetValue>
48118              <resetMask>0xFFFFFFFF</resetMask>
48119              <fields>
48120                <field>
48121                  <name>MD_REF_CTL</name>
48122                  <description>Each bit of this field controls whether value present in Metadata ram is a constant or reference to a register, whose value should be used as Metadata.
481230 - Metadata constant value
481241 - Reference to Register Variable whose address is specified in Metadata</description>
48125                  <bitRange>[26:0]</bitRange>
48126                  <access>read-write</access>
48127                </field>
48128                <field>
48129                  <name>MD_SIZE</name>
48130                  <description>Holds the size in bytes of metadata to be inserted.
48131Should be programmed to even number only (ie multiple of 2 bytes). Allowed values are 0, 2, 4, 6, 8......30.
481320 - indicates 32 bytes
48133If Odd value is programmed, then it'll be converted to immediate lower even value and used(ie if programmed to 9, it'll be used as 8)</description>
48134                  <bitRange>[31:27]</bitRange>
48135                  <access>read-write</access>
48136                </field>
48137              </fields>
48138            </register>
48139            <register>
48140              <name>MD3_CTRL</name>
48141              <description>Metadata-3 Control word</description>
48142              <addressOffset>0x7C</addressOffset>
48143              <size>32</size>
48144              <access>read-write</access>
48145              <resetValue>0x0</resetValue>
48146              <resetMask>0xFFFFFFFF</resetMask>
48147              <fields>
48148                <field>
48149                  <name>MD_REF_CTL</name>
48150                  <description>Each bit of this field controls whether value present in Metadata ram is a constant or reference to a register, whose value should be used as Metadata.
481510 - Metadata constant value
481521 - Reference to Register Variable whose address is specified in Metadata</description>
48153                  <bitRange>[26:0]</bitRange>
48154                  <access>read-write</access>
48155                </field>
48156                <field>
48157                  <name>MD_SIZE</name>
48158                  <description>Holds the size in bytes of metadata to be inserted.
48159Should be programmed to even number only (ie multiple of 2 bytes). Allowed values are 0, 2, 4, 6, 8......30.
481600 - indicates 32 bytes
48161If Odd value is programmed, then it'll be converted to immediate lower even value and used(ie if programmed to 9, it'll be used as 8)</description>
48162                  <bitRange>[31:27]</bitRange>
48163                  <access>read-write</access>
48164                </field>
48165              </fields>
48166            </register>
48167          </cluster>
48168          <cluster>
48169            <dim>2</dim>
48170            <dimIncrement>12288</dimIncrement>
48171            <name>GPIF[%s]</name>
48172            <description>GPIF-II Configuration Registers</description>
48173            <addressOffset>0x00001000</addressOffset>
48174            <register>
48175              <name>GPIF_CONFIG</name>
48176              <description>GPIF Configuration Register</description>
48177              <addressOffset>0x0</addressOffset>
48178              <size>32</size>
48179              <access>read-write</access>
48180              <resetValue>0x0</resetValue>
48181              <resetMask>0x8BC87</resetMask>
48182              <fields>
48183                <field>
48184                  <name>CTRL_COMP_ENABLE</name>
48185                  <description>1: Enable the control Comparator
481860: Disable it.</description>
48187                  <bitRange>[0:0]</bitRange>
48188                  <access>read-write</access>
48189                </field>
48190                <field>
48191                  <name>ADDR_COMP_ENABLE</name>
48192                  <description>1: Enable the address Comparator
481930: Disable it.</description>
48194                  <bitRange>[1:1]</bitRange>
48195                  <access>read-write</access>
48196                </field>
48197                <field>
48198                  <name>DATA_COMP_ENABLE</name>
48199                  <description>1: Enable the data Comparator
482000: Disable it.</description>
48201                  <bitRange>[2:2]</bitRange>
48202                  <access>read-write</access>
48203                </field>
48204                <field>
48205                  <name>DOUT_POP_EN</name>
48206                  <description>1: Use update_dout (alpha) to also trigger rq_pop (which is normally beta)
482070: rq_pop is a separate beta</description>
48208                  <bitRange>[7:7]</bitRange>
48209                  <access>read-write</access>
48210                </field>
48211                <field>
48212                  <name>ENDIAN</name>
48213                  <description>Endianness of interface when PP_MODE==0
482140: Little Endian
482151: Big Endian</description>
48216                  <bitRange>[10:10]</bitRange>
48217                  <access>read-write</access>
48218                </field>
48219                <field>
48220                  <name>ADDR_COMP_TOGGLE</name>
48221                  <description>1: Comparator outputs true when any of the unmasked bits change value.
482220: Comparator outputs true when bits match a target value.</description>
48223                  <bitRange>[11:11]</bitRange>
48224                  <access>read-write</access>
48225                </field>
48226                <field>
48227                  <name>CTRL_COMP_TOGGLE</name>
48228                  <description>1: Comparator outputs true when any of the unmasked bits change value.
482290: Comparator outputs true when bits match a target value.</description>
48230                  <bitRange>[12:12]</bitRange>
48231                  <access>read-write</access>
48232                </field>
48233                <field>
48234                  <name>DATA_COMP_TOGGLE</name>
48235                  <description>1: Comparator outputs true when any of the unmasked bits change value.
482360: Comparator outputs true when bits match a target value.</description>
48237                  <bitRange>[13:13]</bitRange>
48238                  <access>read-write</access>
48239                </field>
48240                <field>
48241                  <name>THREAD_IN_STATE</name>
48242                  <description>0: Normal operation
482431: The thread number for an operation comes from the state description rather than the THREAD_CONFIG register (see GPIF_Modes for more information)</description>
48244                  <bitRange>[15:15]</bitRange>
48245                  <access>read-write</access>
48246                </field>
48247                <field>
48248                  <name>A7OVERRIDE</name>
48249                  <description>Overrides the use of AIN[7] to enable selection of register versus DMA access on different pins in PP_MODE=1.  If A7OVERRIDE=1, register accesses are determined by beta(pp_access) instead.</description>
48250                  <bitRange>[19:19]</bitRange>
48251                  <access>read-write</access>
48252                </field>
48253              </fields>
48254            </register>
48255            <register>
48256              <name>GPIF_BUS_CONFIG</name>
48257              <description>Bus Configuration Register</description>
48258              <addressOffset>0x4</addressOffset>
48259              <size>32</size>
48260              <access>read-write</access>
48261              <resetValue>0x0</resetValue>
48262              <resetMask>0xFF1DFFF0</resetMask>
48263              <fields>
48264                <field>
48265                  <name>ADR_CTRL</name>
48266                  <description>Number of control lines overridden by address lines.  Control signals CTRL[15] to CTRL[16-ADR_CTRL] are not connected to pins.  Instead those pins are designated as address signals. Which address signals depends on the other mode fields above; see architecture spec for details.  In other words:  if ADR_CTRL=0 all CTRL lines are connected to pins, if ADR_CTRL=1, CTRL[15] is not connected and so on.</description>
48267                  <bitRange>[8:4]</bitRange>
48268                  <access>read-write</access>
48269                </field>
48270                <field>
48271                  <name>CE_PRESENT</name>
48272                  <description>CTRL[0] is CE and should be used to disable DQ drivers</description>
48273                  <bitRange>[9:9]</bitRange>
48274                  <access>read-write</access>
48275                </field>
48276                <field>
48277                  <name>WE_PRESENT</name>
48278                  <description>CTRL[1] is WE and should be used to disable DQ drivers
48279Can be used together with DLE_PRESENT</description>
48280                  <bitRange>[10:10]</bitRange>
48281                  <access>read-write</access>
48282                </field>
48283                <field>
48284                  <name>DATA_VLD_PRESENT</name>
48285                  <description>When this bit is set to 1, CTRL[5] pin value will decide if DQ[7:0] will carry data or control byte information in LVCMOS mode.
482861: CTRL[5] = 0, then DQ[7:0] is carrying control_byte
482871: CTRL[5] = 1, then DQ[7:0] is carrying data byte</description>
48288                  <bitRange>[11:11]</bitRange>
48289                  <access>read-write</access>
48290                </field>
48291                <field>
48292                  <name>OE_PRESENT</name>
48293                  <description>CTRL[2] is OE and should be used to tri-state DQ lines.
48294If WE_PRESENT=1 also, then OE will take precedence over WE.  In other words, when WE is asserted, then output drivers are off, regardless of value of OE input.</description>
48295                  <bitRange>[12:12]</bitRange>
48296                  <access>read-write</access>
48297                </field>
48298                <field>
48299                  <name>DRQ_PRESENT</name>
48300                  <description>CTRL[4] is directly influenced by CTRL[3]/DACK as defined by DRQ_MODE
48301This setting also overrides the CTRL_BUS_SELECT selection for this pin, in favor of betas 'assert drq' and 'deassert_drq'</description>
48302                  <bitRange>[13:13]</bitRange>
48303                  <access>read-write</access>
48304                </field>
48305                <field>
48306                  <name>FIO0_PRESENT</name>
48307                  <description>CTRL[7] is to be treated as IO that is driven out when the alpha specified in FIO0_CONF is asserted (ignore CTRL_BUS_DIRECTION)</description>
48308                  <bitRange>[14:14]</bitRange>
48309                  <access>read-write</access>
48310                </field>
48311                <field>
48312                  <name>FIO1_PRESENT</name>
48313                  <description>CTRL[8] is to be treated as IO that is driven out when the alpha specified in FIO1_CONF is asserted (ignore CTRL_BUS_DIRECTION)</description>
48314                  <bitRange>[15:15]</bitRange>
48315                  <access>read-write</access>
48316                </field>
48317                <field>
48318                  <name>CNTR_PRESENT</name>
48319                  <description>CTRL[9] is connected to the selected control counter bit instead of a control signal</description>
48320                  <bitRange>[16:16]</bitRange>
48321                  <access>read-write</access>
48322                </field>
48323                <field>
48324                  <name>DRQ_MODE</name>
48325                  <description>0: Assert DRQ on deassertion of DACK
483261: Assert DRQ on assertion of DACK
483272: Deassert DRQ on deassertion of DACK
483283: Deassert DRQ on assertion of DACK</description>
48329                  <bitRange>[19:18]</bitRange>
48330                  <access>read-write</access>
48331                </field>
48332                <field>
48333                  <name>DRQ_ASSERT_MODE</name>
48334                  <description>1: Assert DRQ on rising edge of DMA_READY. Typical case, DRQ_MODE=2, this bit 1.
483350: Do nothing</description>
48336                  <bitRange>[20:20]</bitRange>
48337                  <access>read-write</access>
48338                </field>
48339                <field>
48340                  <name>FIO0_CONF</name>
48341                  <description>Designates control to be used to enable output drivers of FIO0 (CTRL[7])
483420 to 3: Use the alpha 4 to 7 to switch FIO0 direction.
483438-11: Use beta 0-3.</description>
48344                  <bitRange>[27:24]</bitRange>
48345                  <access>read-write</access>
48346                </field>
48347                <field>
48348                  <name>FIO1_CONF</name>
48349                  <description>Designates control to be used to enable output drivers of FIO1 (CTRL[8])
483500 to 3: Use the alpha  4-7 to switch FIO1 direction.
483518-11: Use beta 0-3.</description>
48352                  <bitRange>[31:28]</bitRange>
48353                  <access>read-write</access>
48354                </field>
48355              </fields>
48356            </register>
48357            <register>
48358              <name>GPIF_BUS_CONFIG2</name>
48359              <description>Bus Configuration Register #2</description>
48360              <addressOffset>0x8</addressOffset>
48361              <size>32</size>
48362              <access>read-write</access>
48363              <resetValue>0x0</resetValue>
48364              <resetMask>0x3F3F3F07</resetMask>
48365              <fields>
48366                <field>
48367                  <name>STATE_FROM_CTRL</name>
48368                  <description>0: Normal operation
483691,2,3: STATE7 indicates Lambda number to be used for state number bit 7
483702,3: STATE6 indicates Lambda number to be used for state number bit 6
483713: STATE5 indicates Lambda number to be used for state number bit 5</description>
48372                  <bitRange>[2:0]</bitRange>
48373                  <access>read-write</access>
48374                </field>
48375                <field>
48376                  <name>STATE5</name>
48377                  <description>Lambda number to be used for state number bit 5</description>
48378                  <bitRange>[13:8]</bitRange>
48379                  <access>read-write</access>
48380                </field>
48381                <field>
48382                  <name>STATE6</name>
48383                  <description>Lambda number to be used for state number bit 6</description>
48384                  <bitRange>[21:16]</bitRange>
48385                  <access>read-write</access>
48386                </field>
48387                <field>
48388                  <name>STATE7</name>
48389                  <description>Lambda number to be used for state number bit 7</description>
48390                  <bitRange>[29:24]</bitRange>
48391                  <access>read-write</access>
48392                </field>
48393              </fields>
48394            </register>
48395            <register>
48396              <name>GPIF_AD_CONFIG</name>
48397              <description>Address/Data configuration register</description>
48398              <addressOffset>0xC</addressOffset>
48399              <size>32</size>
48400              <access>read-write</access>
48401              <resetValue>0x0</resetValue>
48402              <resetMask>0xF03FF</resetMask>
48403              <fields>
48404                <field>
48405                  <name>DQ_OEN_CFG</name>
48406                  <description>N/A</description>
48407                  <bitRange>[1:0]</bitRange>
48408                  <access>read-write</access>
48409                </field>
48410                <field>
48411                  <name>A_OEN_CFG</name>
48412                  <description>N/A</description>
48413                  <bitRange>[3:2]</bitRange>
48414                  <access>read-write</access>
48415                </field>
48416                <field>
48417                  <name>AIN_SELECT</name>
48418                  <description>0: Connect AIN to the active socket number of thread specified by AIN_DATA
484191: Connect AIN to INGRESS_ADDRESS register
484202: Connect AIN to the socket pointed to by ADDRESS_THREAD register</description>
48421                  <bitRange>[5:4]</bitRange>
48422                  <access>read-write</access>
48423                </field>
48424                <field>
48425                  <name>AOUT_SELECT</name>
48426                  <description>0:  Connect AOUT to ADDR_COUNTER
484271: Connect AOUT to EGRESS_ADDRESS register
484282: Connect AOUT to the socket pointed to by ADDRESS_THREAD register</description>
48429                  <bitRange>[7:6]</bitRange>
48430                  <access>read-write</access>
48431                </field>
48432                <field>
48433                  <name>DOUT_SELECT</name>
48434                  <description>0: Connect DOUT to the socket pointed to by AIN_DATA or EGRESS_DATA register (as determined by beta 'register_access')
484351: Connect DOUT to DATA_COUNTER</description>
48436                  <bitRange>[8:8]</bitRange>
48437                  <access>read-write</access>
48438                </field>
48439                <field>
48440                  <name>AIN_DATA</name>
48441                  <description>This field determines which thread number to use for data accesses:
484420: specified by A1:A0.
484431: specified by DATA_THREAD
48444If AIN_SELECT=0 this field also determines the thread number for which to change the active socket on awq_push:
484450: The active socket of thread A1:A0 is changed (3 bits only)
484461: The active socket of thread DATA_THREAD is changed (full 5 bits)</description>
48447                  <bitRange>[9:9]</bitRange>
48448                  <access>read-write</access>
48449                </field>
48450                <field>
48451                  <name>ADDRESS_THREAD</name>
48452                  <description>Thread number to be used for addresses;only relevant when AIN_SELECT!=0
48453When this register is used to select the thread it must have been initialized by firmware.  When both are used, ADDRESS_THREAD must be different from DATA_THREAD.</description>
48454                  <bitRange>[17:16]</bitRange>
48455                  <access>read-write</access>
48456                </field>
48457                <field>
48458                  <name>DATA_THREAD</name>
48459                  <description>Thread number to be used for data; only relevant when AIN_DATA=1
48460When this register is used to select the thread it must have been initialized by firmware.   When both are used, ADDRESS_THREAD must be different from DATA_THREAD.</description>
48461                  <bitRange>[19:18]</bitRange>
48462                  <access>read-write</access>
48463                </field>
48464              </fields>
48465            </register>
48466            <register>
48467              <name>GPIF_STATUS</name>
48468              <description>GPIF Status Register</description>
48469              <addressOffset>0x10</addressOffset>
48470              <size>32</size>
48471              <access>read-only</access>
48472              <resetValue>0xF0000</resetValue>
48473              <resetMask>0xFFFF07FF</resetMask>
48474              <fields>
48475                <field>
48476                  <name>GPIF_DONE</name>
48477                  <description>1: GPIF has reached the DONE state.  Non sticky.</description>
48478                  <bitRange>[0:0]</bitRange>
48479                  <access>read-only</access>
48480                </field>
48481                <field>
48482                  <name>GPIF_INTR</name>
48483                  <description>Indicates that GPIF state machine has raised an interrupt.</description>
48484                  <bitRange>[1:1]</bitRange>
48485                  <access>read-only</access>
48486                </field>
48487                <field>
48488                  <name>SWITCH_TIMEOUT</name>
48489                  <description>Indicates that the SWITCH_TIMEOUT was reached (see WAVEFORM_SWITCH).
48490This bit clears when a new WAVEFORM_SWTICH is initiated.</description>
48491                  <bitRange>[2:2]</bitRange>
48492                  <access>read-only</access>
48493                </field>
48494                <field>
48495                  <name>CRC_ERROR</name>
48496                  <description>Indicates that an incorrect CRC was received</description>
48497                  <bitRange>[3:3]</bitRange>
48498                  <access>read-only</access>
48499                </field>
48500                <field>
48501                  <name>ADDR_COUNT_HIT</name>
48502                  <description>Address counter is at limit</description>
48503                  <bitRange>[4:4]</bitRange>
48504                  <access>read-only</access>
48505                </field>
48506                <field>
48507                  <name>DATA_COUNT_HIT</name>
48508                  <description>Data counter is at limit</description>
48509                  <bitRange>[5:5]</bitRange>
48510                  <access>read-only</access>
48511                </field>
48512                <field>
48513                  <name>CTRL_COUNT_HIT</name>
48514                  <description>Control counter is at limit</description>
48515                  <bitRange>[6:6]</bitRange>
48516                  <access>read-only</access>
48517                </field>
48518                <field>
48519                  <name>ADDR_COMP_HIT</name>
48520                  <description>Address comparator hits</description>
48521                  <bitRange>[7:7]</bitRange>
48522                  <access>read-only</access>
48523                </field>
48524                <field>
48525                  <name>DATA_COMP_HIT</name>
48526                  <description>Data comparator hits</description>
48527                  <bitRange>[8:8]</bitRange>
48528                  <access>read-only</access>
48529                </field>
48530                <field>
48531                  <name>CTRL_COMP_HIT</name>
48532                  <description>Control comparator hits</description>
48533                  <bitRange>[9:9]</bitRange>
48534                  <access>read-only</access>
48535                </field>
48536                <field>
48537                  <name>WAVEFORM_BUSY</name>
48538                  <description>CPU tried to access waveform memory w/o clearing WAVEFORM_VALID</description>
48539                  <bitRange>[10:10]</bitRange>
48540                  <access>read-only</access>
48541                </field>
48542                <field>
48543                  <name>EG_DATA_EMPTY</name>
48544                  <description>Indicates corresponding EGRESS_DATA register is empty</description>
48545                  <bitRange>[19:16]</bitRange>
48546                  <access>read-only</access>
48547                </field>
48548                <field>
48549                  <name>IN_DATA_VALID</name>
48550                  <description>Indicates corresponding INGRESS_DATA register is full.</description>
48551                  <bitRange>[23:20]</bitRange>
48552                  <access>read-only</access>
48553                </field>
48554                <field>
48555                  <name>INTERRUPT_STATE</name>
48556                  <description>State that raised the interrupt through GPIF_INTR. Pl. note that these bits do not have individual interrupt and mask bits in GPIF_INTR and GPIF_MASK</description>
48557                  <bitRange>[31:24]</bitRange>
48558                  <access>read-only</access>
48559                </field>
48560              </fields>
48561            </register>
48562            <register>
48563              <name>GPIF_INTR</name>
48564              <description>GPIF Interrupt Request Register</description>
48565              <addressOffset>0x14</addressOffset>
48566              <size>32</size>
48567              <access>read-write</access>
48568              <resetValue>0x0</resetValue>
48569              <resetMask>0x7FFF07FF</resetMask>
48570              <fields>
48571                <field>
48572                  <name>GPIF_DONE</name>
48573                  <description>Interrupt request corresponding to same bit in GPIF_STATUS</description>
48574                  <bitRange>[0:0]</bitRange>
48575                  <access>read-write</access>
48576                </field>
48577                <field>
48578                  <name>GPIF_INTR</name>
48579                  <description>Interrupt request corresponding to same bit in GPIF_STATUS</description>
48580                  <bitRange>[1:1]</bitRange>
48581                  <access>read-write</access>
48582                </field>
48583                <field>
48584                  <name>SWITCH_TIMEOUT</name>
48585                  <description>Interrupt request corresponding to same bit in GPIF_STATUS</description>
48586                  <bitRange>[2:2]</bitRange>
48587                  <access>read-write</access>
48588                </field>
48589                <field>
48590                  <name>CRC_ERROR</name>
48591                  <description>Interrupt request corresponding to same bit in GPIF_STATUS</description>
48592                  <bitRange>[3:3]</bitRange>
48593                  <access>read-write</access>
48594                </field>
48595                <field>
48596                  <name>ADDR_COUNT_HIT</name>
48597                  <description>Interrupt request corresponding to same bit in GPIF_STATUS</description>
48598                  <bitRange>[4:4]</bitRange>
48599                  <access>read-write</access>
48600                </field>
48601                <field>
48602                  <name>DATA_COUNT_HIT</name>
48603                  <description>Interrupt request corresponding to same bit in GPIF_STATUS</description>
48604                  <bitRange>[5:5]</bitRange>
48605                  <access>read-write</access>
48606                </field>
48607                <field>
48608                  <name>CTRL_COUNT_HIT</name>
48609                  <description>Interrupt request corresponding to same bit in GPIF_STATUS</description>
48610                  <bitRange>[6:6]</bitRange>
48611                  <access>read-write</access>
48612                </field>
48613                <field>
48614                  <name>ADDR_COMP_HIT</name>
48615                  <description>Interrupt request corresponding to same bit in GPIF_STATUS</description>
48616                  <bitRange>[7:7]</bitRange>
48617                  <access>read-write</access>
48618                </field>
48619                <field>
48620                  <name>DATA_COMP_HIT</name>
48621                  <description>Interrupt request corresponding to same bit in GPIF_STATUS</description>
48622                  <bitRange>[8:8]</bitRange>
48623                  <access>read-write</access>
48624                </field>
48625                <field>
48626                  <name>CTRL_COMP_HIT</name>
48627                  <description>Interrupt request corresponding to same bit in GPIF_STATUS</description>
48628                  <bitRange>[9:9]</bitRange>
48629                  <access>read-write</access>
48630                </field>
48631                <field>
48632                  <name>WAVEFORM_BUSY</name>
48633                  <description>Interrupt request corresponding to same bit in GPIF_STATUS</description>
48634                  <bitRange>[10:10]</bitRange>
48635                  <access>read-write</access>
48636                </field>
48637                <field>
48638                  <name>EG_DATA_EMPTY</name>
48639                  <description>Interrupt request corresponding to same bit in GPIF_STATUS</description>
48640                  <bitRange>[19:16]</bitRange>
48641                  <access>read-write</access>
48642                </field>
48643                <field>
48644                  <name>IN_DATA_VALID</name>
48645                  <description>Interrupt request corresponding to same bit in GPIF_STATUS</description>
48646                  <bitRange>[23:20]</bitRange>
48647                  <access>read-write</access>
48648                </field>
48649                <field>
48650                  <name>GPIF_ERR</name>
48651                  <description>An error occurred in the GPIF.  FW clears this bit after handling the error.  The error code is indicated in GPIF_ERR_CODE</description>
48652                  <bitRange>[24:24]</bitRange>
48653                  <access>read-write</access>
48654                </field>
48655                <field>
48656                  <name>INVLD_CMD_DET</name>
48657                  <description>Unspecified command identified on LVDS Control Byte</description>
48658                  <bitRange>[25:25]</bitRange>
48659                  <access>read-write</access>
48660                </field>
48661                <field>
48662                  <name>IDLE_CMD_DET</name>
48663                  <description>Unspecified command identified on LVDS Control Byte</description>
48664                  <bitRange>[26:26]</bitRange>
48665                  <access>read-write</access>
48666                </field>
48667                <field>
48668                  <name>LINK_IDLE_INTF_CLK_OFF</name>
48669                  <description>Interface clock is off for programmable duration</description>
48670                  <bitRange>[27:27]</bitRange>
48671                  <access>read-write</access>
48672                </field>
48673                <field>
48674                  <name>LINK_IDLE</name>
48675                  <description>Continuous IDLE commands are received for programmable duration</description>
48676                  <bitRange>[28:28]</bitRange>
48677                  <access>read-write</access>
48678                </field>
48679                <field>
48680                  <name>TRAINING_DONE</name>
48681                  <description>Training is done and link is locked</description>
48682                  <bitRange>[29:29]</bitRange>
48683                  <access>read-write</access>
48684                </field>
48685                <field>
48686                  <name>PHY_LINK_FF_OVERLOW</name>
48687                  <description>N/A</description>
48688                  <bitRange>[30:30]</bitRange>
48689                  <access>read-write</access>
48690                </field>
48691              </fields>
48692            </register>
48693            <register>
48694              <name>GPIF_INTR_MASK</name>
48695              <description>GPIF Interrupt Mask Register</description>
48696              <addressOffset>0x18</addressOffset>
48697              <size>32</size>
48698              <access>read-write</access>
48699              <resetValue>0x0</resetValue>
48700              <resetMask>0x7FFF07FF</resetMask>
48701              <fields>
48702                <field>
48703                  <name>GPIF_DONE</name>
48704                  <description>Mask bit that controls reporting of corresponding bit in GPIF_INTR</description>
48705                  <bitRange>[0:0]</bitRange>
48706                  <access>read-write</access>
48707                </field>
48708                <field>
48709                  <name>GPIF_INTR</name>
48710                  <description>Mask bit that controls reporting of corresponding bit in GPIF_INTR</description>
48711                  <bitRange>[1:1]</bitRange>
48712                  <access>read-write</access>
48713                </field>
48714                <field>
48715                  <name>SWITCH_TIMEOUT</name>
48716                  <description>Mask bit that controls reporting of corresponding bit in GPIF_INTR</description>
48717                  <bitRange>[2:2]</bitRange>
48718                  <access>read-write</access>
48719                </field>
48720                <field>
48721                  <name>CRC_ERROR</name>
48722                  <description>Mask bit that controls reporting of corresponding bit in GPIF_INTR</description>
48723                  <bitRange>[3:3]</bitRange>
48724                  <access>read-write</access>
48725                </field>
48726                <field>
48727                  <name>ADDR_COUNT_HIT</name>
48728                  <description>Mask bit that controls reporting of corresponding bit in GPIF_INTR</description>
48729                  <bitRange>[4:4]</bitRange>
48730                  <access>read-write</access>
48731                </field>
48732                <field>
48733                  <name>DATA_COUNT_HIT</name>
48734                  <description>Mask bit that controls reporting of corresponding bit in GPIF_INTR</description>
48735                  <bitRange>[5:5]</bitRange>
48736                  <access>read-write</access>
48737                </field>
48738                <field>
48739                  <name>CTRL_COUNT_HIT</name>
48740                  <description>Mask bit that controls reporting of corresponding bit in GPIF_INTR</description>
48741                  <bitRange>[6:6]</bitRange>
48742                  <access>read-write</access>
48743                </field>
48744                <field>
48745                  <name>ADDR_COMP_HIT</name>
48746                  <description>Mask bit that controls reporting of corresponding bit in GPIF_INTR</description>
48747                  <bitRange>[7:7]</bitRange>
48748                  <access>read-write</access>
48749                </field>
48750                <field>
48751                  <name>DATA_COMP_HIT</name>
48752                  <description>Mask bit that controls reporting of corresponding bit in GPIF_INTR</description>
48753                  <bitRange>[8:8]</bitRange>
48754                  <access>read-write</access>
48755                </field>
48756                <field>
48757                  <name>CTRL_COMP_HIT</name>
48758                  <description>Mask bit that controls reporting of corresponding bit in GPIF_INTR</description>
48759                  <bitRange>[9:9]</bitRange>
48760                  <access>read-write</access>
48761                </field>
48762                <field>
48763                  <name>WAVEFORM_BUSY</name>
48764                  <description>Mask bit that controls reporting of corresponding bit in GPIF_INTR</description>
48765                  <bitRange>[10:10]</bitRange>
48766                  <access>read-write</access>
48767                </field>
48768                <field>
48769                  <name>EG_DATA_EMPTY</name>
48770                  <description>Mask bit that controls reporting of corresponding bit in GPIF_INTR</description>
48771                  <bitRange>[19:16]</bitRange>
48772                  <access>read-write</access>
48773                </field>
48774                <field>
48775                  <name>IN_DATA_VALID</name>
48776                  <description>Mask bit that controls reporting of corresponding bit in GPIF_INTR</description>
48777                  <bitRange>[23:20]</bitRange>
48778                  <access>read-write</access>
48779                </field>
48780                <field>
48781                  <name>GPIF_ERR</name>
48782                  <description>N/A</description>
48783                  <bitRange>[24:24]</bitRange>
48784                  <access>read-write</access>
48785                </field>
48786                <field>
48787                  <name>INVLD_CMD_DET</name>
48788                  <description>N/A</description>
48789                  <bitRange>[25:25]</bitRange>
48790                  <access>read-write</access>
48791                </field>
48792                <field>
48793                  <name>IDLE_CMD_DET</name>
48794                  <description>N/A</description>
48795                  <bitRange>[26:26]</bitRange>
48796                  <access>read-write</access>
48797                </field>
48798                <field>
48799                  <name>LINK_IDLE_INTF_CLK_OFF</name>
48800                  <description>N/A</description>
48801                  <bitRange>[27:27]</bitRange>
48802                  <access>read-write</access>
48803                </field>
48804                <field>
48805                  <name>LINK_IDLE</name>
48806                  <description>N/A</description>
48807                  <bitRange>[28:28]</bitRange>
48808                  <access>read-write</access>
48809                </field>
48810                <field>
48811                  <name>TRAINING_DONE</name>
48812                  <description>N/A</description>
48813                  <bitRange>[29:29]</bitRange>
48814                  <access>read-write</access>
48815                </field>
48816                <field>
48817                  <name>PHY_LINK_FF_OVERLOW</name>
48818                  <description>N/A</description>
48819                  <bitRange>[30:30]</bitRange>
48820                  <access>read-write</access>
48821                </field>
48822              </fields>
48823            </register>
48824            <register>
48825              <name>GPIF_INTR_MASKED</name>
48826              <description>GPIF Interrupt Generator</description>
48827              <addressOffset>0x1C</addressOffset>
48828              <size>32</size>
48829              <access>read-only</access>
48830              <resetValue>0x0</resetValue>
48831              <resetMask>0x7FFF07FF</resetMask>
48832              <fields>
48833                <field>
48834                  <name>GPIF_DONE</name>
48835                  <description>N/A</description>
48836                  <bitRange>[0:0]</bitRange>
48837                  <access>read-only</access>
48838                </field>
48839                <field>
48840                  <name>GPIF_INTR</name>
48841                  <description>N/A</description>
48842                  <bitRange>[1:1]</bitRange>
48843                  <access>read-only</access>
48844                </field>
48845                <field>
48846                  <name>SWITCH_TIMEOUT</name>
48847                  <description>N/A</description>
48848                  <bitRange>[2:2]</bitRange>
48849                  <access>read-only</access>
48850                </field>
48851                <field>
48852                  <name>CRC_ERROR</name>
48853                  <description>N/A</description>
48854                  <bitRange>[3:3]</bitRange>
48855                  <access>read-only</access>
48856                </field>
48857                <field>
48858                  <name>ADDR_COUNT_HIT</name>
48859                  <description>N/A</description>
48860                  <bitRange>[4:4]</bitRange>
48861                  <access>read-only</access>
48862                </field>
48863                <field>
48864                  <name>DATA_COUNT_HIT</name>
48865                  <description>N/A</description>
48866                  <bitRange>[5:5]</bitRange>
48867                  <access>read-only</access>
48868                </field>
48869                <field>
48870                  <name>CTRL_COUNT_HIT</name>
48871                  <description>N/A</description>
48872                  <bitRange>[6:6]</bitRange>
48873                  <access>read-only</access>
48874                </field>
48875                <field>
48876                  <name>ADDR_COMP_HIT</name>
48877                  <description>N/A</description>
48878                  <bitRange>[7:7]</bitRange>
48879                  <access>read-only</access>
48880                </field>
48881                <field>
48882                  <name>DATA_COMP_HIT</name>
48883                  <description>N/A</description>
48884                  <bitRange>[8:8]</bitRange>
48885                  <access>read-only</access>
48886                </field>
48887                <field>
48888                  <name>CTRL_COMP_HIT</name>
48889                  <description>N/A</description>
48890                  <bitRange>[9:9]</bitRange>
48891                  <access>read-only</access>
48892                </field>
48893                <field>
48894                  <name>WAVEFORM_BUSY</name>
48895                  <description>N/A</description>
48896                  <bitRange>[10:10]</bitRange>
48897                  <access>read-only</access>
48898                </field>
48899                <field>
48900                  <name>EG_DATA_EMPTY</name>
48901                  <description>N/A</description>
48902                  <bitRange>[19:16]</bitRange>
48903                  <access>read-only</access>
48904                </field>
48905                <field>
48906                  <name>IN_DATA_VALID</name>
48907                  <description>N/A</description>
48908                  <bitRange>[23:20]</bitRange>
48909                  <access>read-only</access>
48910                </field>
48911                <field>
48912                  <name>GPIF_ERR</name>
48913                  <description>N/A</description>
48914                  <bitRange>[24:24]</bitRange>
48915                  <access>read-only</access>
48916                </field>
48917                <field>
48918                  <name>INVLD_CMD_DET</name>
48919                  <description>N/A</description>
48920                  <bitRange>[25:25]</bitRange>
48921                  <access>read-only</access>
48922                </field>
48923                <field>
48924                  <name>IDLE_CMD_DET</name>
48925                  <description>N/A</description>
48926                  <bitRange>[26:26]</bitRange>
48927                  <access>read-only</access>
48928                </field>
48929                <field>
48930                  <name>LINK_IDLE_INTF_CLK_OFF</name>
48931                  <description>N/A</description>
48932                  <bitRange>[27:27]</bitRange>
48933                  <access>read-only</access>
48934                </field>
48935                <field>
48936                  <name>LINK_IDLE</name>
48937                  <description>N/A</description>
48938                  <bitRange>[28:28]</bitRange>
48939                  <access>read-only</access>
48940                </field>
48941                <field>
48942                  <name>TRAINING_DONE</name>
48943                  <description>N/A</description>
48944                  <bitRange>[29:29]</bitRange>
48945                  <access>read-only</access>
48946                </field>
48947                <field>
48948                  <name>PHY_LINK_FF_OVERLOW</name>
48949                  <description>N/A</description>
48950                  <bitRange>[30:30]</bitRange>
48951                  <access>read-only</access>
48952                </field>
48953              </fields>
48954            </register>
48955            <register>
48956              <name>GPIF_INTR_SET</name>
48957              <description>GPIF Interrupt Set Register</description>
48958              <addressOffset>0x20</addressOffset>
48959              <size>32</size>
48960              <access>read-write</access>
48961              <resetValue>0x0</resetValue>
48962              <resetMask>0x7FFF07FF</resetMask>
48963              <fields>
48964                <field>
48965                  <name>GPIF_DONE</name>
48966                  <description>N/A</description>
48967                  <bitRange>[0:0]</bitRange>
48968                  <access>read-write</access>
48969                </field>
48970                <field>
48971                  <name>GPIF_INTR</name>
48972                  <description>N/A</description>
48973                  <bitRange>[1:1]</bitRange>
48974                  <access>read-write</access>
48975                </field>
48976                <field>
48977                  <name>SWITCH_TIMEOUT</name>
48978                  <description>N/A</description>
48979                  <bitRange>[2:2]</bitRange>
48980                  <access>read-write</access>
48981                </field>
48982                <field>
48983                  <name>CRC_ERROR</name>
48984                  <description>N/A</description>
48985                  <bitRange>[3:3]</bitRange>
48986                  <access>read-write</access>
48987                </field>
48988                <field>
48989                  <name>ADDR_COUNT_HIT</name>
48990                  <description>N/A</description>
48991                  <bitRange>[4:4]</bitRange>
48992                  <access>read-write</access>
48993                </field>
48994                <field>
48995                  <name>DATA_COUNT_HIT</name>
48996                  <description>N/A</description>
48997                  <bitRange>[5:5]</bitRange>
48998                  <access>read-write</access>
48999                </field>
49000                <field>
49001                  <name>CTRL_COUNT_HIT</name>
49002                  <description>N/A</description>
49003                  <bitRange>[6:6]</bitRange>
49004                  <access>read-write</access>
49005                </field>
49006                <field>
49007                  <name>ADDR_COMP_HIT</name>
49008                  <description>N/A</description>
49009                  <bitRange>[7:7]</bitRange>
49010                  <access>read-write</access>
49011                </field>
49012                <field>
49013                  <name>DATA_COMP_HIT</name>
49014                  <description>N/A</description>
49015                  <bitRange>[8:8]</bitRange>
49016                  <access>read-write</access>
49017                </field>
49018                <field>
49019                  <name>CTRL_COMP_HIT</name>
49020                  <description>N/A</description>
49021                  <bitRange>[9:9]</bitRange>
49022                  <access>read-write</access>
49023                </field>
49024                <field>
49025                  <name>WAVEFORM_BUSY</name>
49026                  <description>N/A</description>
49027                  <bitRange>[10:10]</bitRange>
49028                  <access>read-write</access>
49029                </field>
49030                <field>
49031                  <name>EG_DATA_EMPTY</name>
49032                  <description>N/A</description>
49033                  <bitRange>[19:16]</bitRange>
49034                  <access>read-write</access>
49035                </field>
49036                <field>
49037                  <name>IN_DATA_VALID</name>
49038                  <description>N/A</description>
49039                  <bitRange>[23:20]</bitRange>
49040                  <access>read-write</access>
49041                </field>
49042                <field>
49043                  <name>GPIF_ERR</name>
49044                  <description>N/A</description>
49045                  <bitRange>[24:24]</bitRange>
49046                  <access>read-write</access>
49047                </field>
49048                <field>
49049                  <name>INVLD_CMD_DET</name>
49050                  <description>N/A</description>
49051                  <bitRange>[25:25]</bitRange>
49052                  <access>read-write</access>
49053                </field>
49054                <field>
49055                  <name>IDLE_CMD_DET</name>
49056                  <description>N/A</description>
49057                  <bitRange>[26:26]</bitRange>
49058                  <access>read-write</access>
49059                </field>
49060                <field>
49061                  <name>LINK_IDLE_INTF_CLK_OFF</name>
49062                  <description>N/A</description>
49063                  <bitRange>[27:27]</bitRange>
49064                  <access>read-write</access>
49065                </field>
49066                <field>
49067                  <name>LINK_IDLE</name>
49068                  <description>N/A</description>
49069                  <bitRange>[28:28]</bitRange>
49070                  <access>read-write</access>
49071                </field>
49072                <field>
49073                  <name>TRAINING_DONE</name>
49074                  <description>N/A</description>
49075                  <bitRange>[29:29]</bitRange>
49076                  <access>read-write</access>
49077                </field>
49078                <field>
49079                  <name>PHY_LINK_FF_OVERLOW</name>
49080                  <description>N/A</description>
49081                  <bitRange>[30:30]</bitRange>
49082                  <access>read-write</access>
49083                </field>
49084              </fields>
49085            </register>
49086            <register>
49087              <name>GPIF_ERROR</name>
49088              <description>GPIF Error Register</description>
49089              <addressOffset>0x24</addressOffset>
49090              <size>32</size>
49091              <access>read-only</access>
49092              <resetValue>0x0</resetValue>
49093              <resetMask>0x1F</resetMask>
49094              <fields>
49095                <field>
49096                  <name>GPIF_ERR_CODE</name>
49097                  <description>Error code for the first error code since ERROR=1
49098Error codes are specified in detail the USB30PIB BROS.</description>
49099                  <bitRange>[4:0]</bitRange>
49100                  <access>read-only</access>
49101                  <enumeratedValues>
49102                    <enumeratedValue>
49103                      <name>IN_ADDR_OVER_WRITE</name>
49104                      <description>Attempt to push to the active address thread which is not dma_ready</description>
49105                      <value>1</value>
49106                    </enumeratedValue>
49107                    <enumeratedValue>
49108                      <name>EG_ADDR_NOT_VALID</name>
49109                      <description>Attempt to push to the active address thread which is not dma_ready</description>
49110                      <value>2</value>
49111                    </enumeratedValue>
49112                    <enumeratedValue>
49113                      <name>DMA_DATA_RD_ERROR</name>
49114                      <description>Attempt to push to the active address thread which is not dma_ready</description>
49115                      <value>3</value>
49116                    </enumeratedValue>
49117                    <enumeratedValue>
49118                      <name>DMA_DATA_WR_ERROR</name>
49119                      <description>Attempt to push to the active address thread which is not dma_ready</description>
49120                      <value>4</value>
49121                    </enumeratedValue>
49122                    <enumeratedValue>
49123                      <name>DMA_ADDR_RD_ERROR</name>
49124                      <description>Attempt to push to the active address thread which is not dma_ready</description>
49125                      <value>5</value>
49126                    </enumeratedValue>
49127                    <enumeratedValue>
49128                      <name>DMA_ADDR_WR_ERROR</name>
49129                      <description>Attempt to push to the active address thread which is not dma_ready</description>
49130                      <value>6</value>
49131                    </enumeratedValue>
49132                    <enumeratedValue>
49133                      <name>INVALID_STATE_ERROR</name>
49134                      <description>statemachine has transitioned to an invalid state</description>
49135                      <value>8</value>
49136                    </enumeratedValue>
49137                  </enumeratedValues>
49138                </field>
49139              </fields>
49140            </register>
49141            <register>
49142              <name>GPIF_CTRL_BUS_DIRECTION_0</name>
49143              <description>Control Bus in/out direction</description>
49144              <addressOffset>0x28</addressOffset>
49145              <size>32</size>
49146              <access>read-write</access>
49147              <resetValue>0x0</resetValue>
49148              <resetMask>0xFFFFFFFF</resetMask>
49149              <fields>
49150                <field>
49151                  <name>DIRECTION</name>
49152                  <description>Bit at (bit_number/2) has following direction:
4915300: Input
4915401:Output
4915510: Bidirectional IO.
4915611: Open drain IO.</description>
49157                  <bitRange>[31:0]</bitRange>
49158                  <access>read-write</access>
49159                </field>
49160              </fields>
49161            </register>
49162            <register>
49163              <name>GPIF_CTRL_BUS_DIRECTION_1</name>
49164              <description>Control Bus in/out direction</description>
49165              <addressOffset>0x2C</addressOffset>
49166              <size>32</size>
49167              <access>read-write</access>
49168              <resetValue>0x0</resetValue>
49169              <resetMask>0xFFFFFFFF</resetMask>
49170              <fields>
49171                <field>
49172                  <name>DIRECTION</name>
49173                  <description>Bit at (bit_number/2) has following direction:
4917400: Input
4917501:Output
4917610: Bidirectional IO.
4917711: Open drain IO.</description>
49178                  <bitRange>[31:0]</bitRange>
49179                  <access>read-write</access>
49180                </field>
49181              </fields>
49182            </register>
49183            <register>
49184              <name>GPIF_CTRL_BUS_DEFAULT</name>
49185              <description>Control bus default values</description>
49186              <addressOffset>0x30</addressOffset>
49187              <size>32</size>
49188              <access>read-write</access>
49189              <resetValue>0x0</resetValue>
49190              <resetMask>0xFFFFF</resetMask>
49191              <fields>
49192                <field>
49193                  <name>DEFAULT</name>
49194                  <description>One bit for each CTRL signal indicating default value
491950:  Asserted (see POLARITY)
491961:  De-asserted (see POLARITY)</description>
49197                  <bitRange>[19:0]</bitRange>
49198                  <access>read-write</access>
49199                </field>
49200              </fields>
49201            </register>
49202            <register>
49203              <name>GPIF_CTRL_BUS_POLARITY</name>
49204              <description>Control bus signal polarity</description>
49205              <addressOffset>0x34</addressOffset>
49206              <size>32</size>
49207              <access>read-write</access>
49208              <resetValue>0x0</resetValue>
49209              <resetMask>0xFFFFF</resetMask>
49210              <fields>
49211                <field>
49212                  <name>POLARITY</name>
49213                  <description>One bit for each CTRL signal indicating polarity
492140: Asserted when 1
492151: Asserted when 0</description>
49216                  <bitRange>[19:0]</bitRange>
49217                  <access>read-write</access>
49218                </field>
49219              </fields>
49220            </register>
49221            <register>
49222              <name>GPIF_CTRL_BUS_TOGGLE</name>
49223              <description>Control bus output toggle mode</description>
49224              <addressOffset>0x38</addressOffset>
49225              <size>32</size>
49226              <access>read-write</access>
49227              <resetValue>0x0</resetValue>
49228              <resetMask>0xFFFFF</resetMask>
49229              <fields>
49230                <field>
49231                  <name>TOGGLE</name>
49232                  <description>One bit for each CTRL signal indicating toggle mode
492330: Normal mode, set value from alpha/beta
492341: Toggle mode, toggle value when alpha/beta is 1, do nothing when 0</description>
49235                  <bitRange>[19:0]</bitRange>
49236                  <access>read-write</access>
49237                </field>
49238              </fields>
49239            </register>
49240            <register>
49241              <dim>20</dim>
49242              <dimIncrement>4</dimIncrement>
49243              <name>GPIF_CTRL_BUS_SELECT[%s]</name>
49244              <description>Control bus connection matrix register</description>
49245              <addressOffset>0x40</addressOffset>
49246              <size>32</size>
49247              <access>read-write</access>
49248              <resetValue>0x0</resetValue>
49249              <resetMask>0x1F</resetMask>
49250              <fields>
49251                <field>
49252                  <name>OMEGA_INDEX</name>
49253                  <description>For each omega, 5-bits specify what is driven at to the output:
492540-3: Connect to alpha 4-7
492558-11: Connect to beta 0-3
4925616-19: Empty/Full flags for thread 0-3
4925720-23: Partial Flag for thread 0-3
4925824: Empty/Full flag for current thread
4925925: Partial Flag for current thread
4926026-31: Connected to logic 0 (cannot be used together with CTRL_BUS_TOGGLE)</description>
49261                  <bitRange>[4:0]</bitRange>
49262                  <access>read-write</access>
49263                </field>
49264              </fields>
49265            </register>
49266            <register>
49267              <name>GPIF_CTRL_COUNT_CONFIG</name>
49268              <description>Control counter configuration</description>
49269              <addressOffset>0x160</addressOffset>
49270              <size>32</size>
49271              <access>read-write</access>
49272              <resetValue>0x6</resetValue>
49273              <resetMask>0xFF</resetMask>
49274              <fields>
49275                <field>
49276                  <name>ENABLE</name>
49277                  <description>0: This counter is not used.
492781: This counter is used.</description>
49279                  <bitRange>[0:0]</bitRange>
49280                  <access>read-write</access>
49281                </field>
49282                <field>
49283                  <name>DOWN_UP_CNTR</name>
49284                  <description>0: Down Count
492851: Up Count</description>
49286                  <bitRange>[1:1]</bitRange>
49287                  <access>read-write</access>
49288                </field>
49289                <field>
49290                  <name>RELOAD_CNTR</name>
49291                  <description>0: Saturate on reaching the limit
492921: Reload on reaching the limit</description>
49293                  <bitRange>[2:2]</bitRange>
49294                  <access>read-write</access>
49295                </field>
49296                <field>
49297                  <name>SW_RESET_CNTR</name>
49298                  <description>1: SW writes one to reset/load the counter
492990: HW write 0 to signal that counter has reset</description>
49300                  <bitRange>[3:3]</bitRange>
49301                  <access>read-write</access>
49302                </field>
49303                <field>
49304                  <name>CONNECT</name>
49305                  <description>Connect the specified bit of this counter to CTRL[9]</description>
49306                  <bitRange>[7:4]</bitRange>
49307                  <access>read-write</access>
49308                </field>
49309              </fields>
49310            </register>
49311            <register>
49312              <name>GPIF_CTRL_COUNT_RESET</name>
49313              <description>Control counter reset register</description>
49314              <addressOffset>0x164</addressOffset>
49315              <size>32</size>
49316              <access>read-write</access>
49317              <resetValue>0x0</resetValue>
49318              <resetMask>0xFFFF</resetMask>
49319              <fields>
49320                <field>
49321                  <name>RESET_LOAD_VAL</name>
49322                  <description>Reset counter to this value. Reload to this value when limit is reached if specified.</description>
49323                  <bitRange>[15:0]</bitRange>
49324                  <access>read-write</access>
49325                </field>
49326              </fields>
49327            </register>
49328            <register>
49329              <name>GPIF_CTRL_COUNT_LIMIT</name>
49330              <description>Control counter limit register</description>
49331              <addressOffset>0x168</addressOffset>
49332              <size>32</size>
49333              <access>read-write</access>
49334              <resetValue>0xFFFF</resetValue>
49335              <resetMask>0xFFFF</resetMask>
49336              <fields>
49337                <field>
49338                  <name>LIMIT_VAL</name>
49339                  <description>Stop counting when counter reaches this value</description>
49340                  <bitRange>[15:0]</bitRange>
49341                  <access>read-write</access>
49342                </field>
49343              </fields>
49344            </register>
49345            <register>
49346              <name>GPIF_ADDR_COUNT_CONFIG</name>
49347              <description>Address counter configuration</description>
49348              <addressOffset>0x170</addressOffset>
49349              <size>32</size>
49350              <access>read-write</access>
49351              <resetValue>0x10A</resetValue>
49352              <resetMask>0xFF0F</resetMask>
49353              <fields>
49354                <field>
49355                  <name>ENABLE</name>
49356                  <description>0: This counter is not used.
493571: This counter is used.</description>
49358                  <bitRange>[0:0]</bitRange>
49359                  <access>read-write</access>
49360                </field>
49361                <field>
49362                  <name>RELOAD</name>
49363                  <description>0: Saturate on reaching the limit
493641: Reload on reaching the limit</description>
49365                  <bitRange>[1:1]</bitRange>
49366                  <access>read-write</access>
49367                </field>
49368                <field>
49369                  <name>SW_RESET</name>
49370                  <description>1: SW writes one to reset/load the counter
493710: HW write 0 to signal that counter has reset</description>
49372                  <bitRange>[2:2]</bitRange>
49373                  <access>read-write</access>
49374                </field>
49375                <field>
49376                  <name>DOWN_UP</name>
49377                  <description>0: Down Count
493781: Up Count</description>
49379                  <bitRange>[3:3]</bitRange>
49380                  <access>read-write</access>
49381                </field>
49382                <field>
49383                  <name>INCREMENT</name>
49384                  <description>8-bit quantity to be added/subtracted to the counter on each clock</description>
49385                  <bitRange>[15:8]</bitRange>
49386                  <access>read-write</access>
49387                </field>
49388              </fields>
49389            </register>
49390            <register>
49391              <name>GPIF_ADDR_COUNT_RESET</name>
49392              <description>Address counter reset register</description>
49393              <addressOffset>0x174</addressOffset>
49394              <size>32</size>
49395              <access>read-write</access>
49396              <resetValue>0x0</resetValue>
49397              <resetMask>0xFFFFFFFF</resetMask>
49398              <fields>
49399                <field>
49400                  <name>RESET_LOAD</name>
49401                  <description>Reset counter to this value. Reload to this value when limit is reached if specified.</description>
49402                  <bitRange>[31:0]</bitRange>
49403                  <access>read-write</access>
49404                </field>
49405              </fields>
49406            </register>
49407            <register>
49408              <name>GPIF_ADDR_COUNT_LIMIT</name>
49409              <description>Address counter limit register</description>
49410              <addressOffset>0x178</addressOffset>
49411              <size>32</size>
49412              <access>read-write</access>
49413              <resetValue>0xFFFF</resetValue>
49414              <resetMask>0xFFFFFFFF</resetMask>
49415              <fields>
49416                <field>
49417                  <name>LIMIT</name>
49418                  <description>Stop counting when counter reaches this value</description>
49419                  <bitRange>[31:0]</bitRange>
49420                  <access>read-write</access>
49421                </field>
49422              </fields>
49423            </register>
49424            <register>
49425              <name>GPIF_STATE_COUNT_CONFIG</name>
49426              <description>State counter configuration</description>
49427              <addressOffset>0x180</addressOffset>
49428              <size>32</size>
49429              <access>read-write</access>
49430              <resetValue>0x0</resetValue>
49431              <resetMask>0x3</resetMask>
49432              <fields>
49433                <field>
49434                  <name>ENABLE</name>
49435                  <description>0: This counter is not used.
494361: This counter is used.</description>
49437                  <bitRange>[0:0]</bitRange>
49438                  <access>read-write</access>
49439                </field>
49440                <field>
49441                  <name>SW_RESET_STATE_CNT</name>
49442                  <description>1: SW writes one to reset/load the counter
494430: HW write 0 to signal that counter has reset</description>
49444                  <bitRange>[1:1]</bitRange>
49445                  <access>read-write</access>
49446                </field>
49447              </fields>
49448            </register>
49449            <register>
49450              <name>GPIF_STATE_COUNT_LIMIT</name>
49451              <description>State counter limit register</description>
49452              <addressOffset>0x184</addressOffset>
49453              <size>32</size>
49454              <access>read-write</access>
49455              <resetValue>0xFFFF</resetValue>
49456              <resetMask>0xFFFF</resetMask>
49457              <fields>
49458                <field>
49459                  <name>LIMIT_VAL</name>
49460                  <description>Generate an output tick, reset and start counting again if enabled when this limit is reached..</description>
49461                  <bitRange>[15:0]</bitRange>
49462                  <access>read-write</access>
49463                </field>
49464              </fields>
49465            </register>
49466            <register>
49467              <name>GPIF_DATA_COUNT_CONFIG</name>
49468              <description>Data counter configuration</description>
49469              <addressOffset>0x190</addressOffset>
49470              <size>32</size>
49471              <access>read-write</access>
49472              <resetValue>0x10A</resetValue>
49473              <resetMask>0xFF0F</resetMask>
49474              <fields>
49475                <field>
49476                  <name>ENABLE</name>
49477                  <description>0: This counter is not used.
494781: This counter is used.</description>
49479                  <bitRange>[0:0]</bitRange>
49480                  <access>read-write</access>
49481                </field>
49482                <field>
49483                  <name>RELOAD</name>
49484                  <description>0: Saturate on reaching the limit
494851: Reload on reaching the limit</description>
49486                  <bitRange>[1:1]</bitRange>
49487                  <access>read-write</access>
49488                </field>
49489                <field>
49490                  <name>SW_RESET</name>
49491                  <description>1: SW writes one to reset/load the counter
494920: HW write 0 to signal that counter has reset</description>
49493                  <bitRange>[2:2]</bitRange>
49494                  <access>read-write</access>
49495                </field>
49496                <field>
49497                  <name>DOWN_UP</name>
49498                  <description>0: Down Count
494991: Up Count</description>
49500                  <bitRange>[3:3]</bitRange>
49501                  <access>read-write</access>
49502                </field>
49503                <field>
49504                  <name>INCREMENT</name>
49505                  <description>8-bit quantity to be added/subtracted to the counter on each clock</description>
49506                  <bitRange>[15:8]</bitRange>
49507                  <access>read-write</access>
49508                </field>
49509              </fields>
49510            </register>
49511            <register>
49512              <name>GPIF_DATA_COUNT_RESET_LSB</name>
49513              <description>Data counter reset register</description>
49514              <addressOffset>0x194</addressOffset>
49515              <size>32</size>
49516              <access>read-write</access>
49517              <resetValue>0x0</resetValue>
49518              <resetMask>0xFFFFFFFF</resetMask>
49519              <fields>
49520                <field>
49521                  <name>RESET_LOAD</name>
49522                  <description>Reset counter to this value. Relload to this value when limit it reached if specified. LSB bits of reset counter value.</description>
49523                  <bitRange>[31:0]</bitRange>
49524                  <access>read-write</access>
49525                </field>
49526              </fields>
49527            </register>
49528            <register>
49529              <name>GPIF_DATA_COUNT_RESET_MSB</name>
49530              <description>Data counter reset register</description>
49531              <addressOffset>0x19C</addressOffset>
49532              <size>32</size>
49533              <access>read-write</access>
49534              <resetValue>0x0</resetValue>
49535              <resetMask>0xFFFFFFFF</resetMask>
49536              <fields>
49537                <field>
49538                  <name>RESET_LOAD</name>
49539                  <description>Reset counter to this value. Relload to this value when limit it reached if specified. MSB bits of reset counter value.</description>
49540                  <bitRange>[31:0]</bitRange>
49541                  <access>read-write</access>
49542                </field>
49543              </fields>
49544            </register>
49545            <register>
49546              <name>GPIF_DATA_COUNT_LIMIT_LSB</name>
49547              <description>Data counter limit register</description>
49548              <addressOffset>0x1A0</addressOffset>
49549              <size>32</size>
49550              <access>read-write</access>
49551              <resetValue>0xFFFF</resetValue>
49552              <resetMask>0xFFFFFFFF</resetMask>
49553              <fields>
49554                <field>
49555                  <name>LIMIT</name>
49556                  <description>Reload data counter if this limit is reached and reload is enabled. LSB bits of limit value.</description>
49557                  <bitRange>[31:0]</bitRange>
49558                  <access>read-write</access>
49559                </field>
49560              </fields>
49561            </register>
49562            <register>
49563              <name>GPIF_DATA_COUNT_LIMIT_MSB</name>
49564              <description>Data counter limit register</description>
49565              <addressOffset>0x1A4</addressOffset>
49566              <size>32</size>
49567              <access>read-write</access>
49568              <resetValue>0xFFFF</resetValue>
49569              <resetMask>0xFFFFFFFF</resetMask>
49570              <fields>
49571                <field>
49572                  <name>LIMIT</name>
49573                  <description>Reload data counter if this limit is reached and reload is enabled. MSB bits of limit value.</description>
49574                  <bitRange>[31:0]</bitRange>
49575                  <access>read-write</access>
49576                </field>
49577              </fields>
49578            </register>
49579            <register>
49580              <name>GPIF_CTRL_COMP_VALUE</name>
49581              <description>Control comparator value</description>
49582              <addressOffset>0x1A8</addressOffset>
49583              <size>32</size>
49584              <access>read-write</access>
49585              <resetValue>0x0</resetValue>
49586              <resetMask>0xFFFFF</resetMask>
49587              <fields>
49588                <field>
49589                  <name>COMP_VALUE</name>
49590                  <description>Output true when CTRL bus matches this value</description>
49591                  <bitRange>[19:0]</bitRange>
49592                  <access>read-write</access>
49593                </field>
49594              </fields>
49595            </register>
49596            <register>
49597              <name>GPIF_CTRL_COMP_MASK</name>
49598              <description>Control comparator mask</description>
49599              <addressOffset>0x1AC</addressOffset>
49600              <size>32</size>
49601              <access>read-write</access>
49602              <resetValue>0x0</resetValue>
49603              <resetMask>0xFFFFF</resetMask>
49604              <fields>
49605                <field>
49606                  <name>CTRL_COMP_MASK</name>
49607                  <description>1: Bit at this bit position in the CTRL bus is to be used in comparison
496080: Bit at this bit position is a don't-care for comparison</description>
49609                  <bitRange>[19:0]</bitRange>
49610                  <access>read-write</access>
49611                </field>
49612              </fields>
49613            </register>
49614            <register>
49615              <name>GPIF_DATA_COMP_VALUE_WORD0</name>
49616              <description>Data comparator value</description>
49617              <addressOffset>0x1B0</addressOffset>
49618              <size>32</size>
49619              <access>read-write</access>
49620              <resetValue>0x0</resetValue>
49621              <resetMask>0xFFFFFFFF</resetMask>
49622              <fields>
49623                <field>
49624                  <name>VALUE</name>
49625                  <description>Output true when Data  bus matches this value. {WD3, WD2, WD1, WD0}</description>
49626                  <bitRange>[31:0]</bitRange>
49627                  <access>read-write</access>
49628                </field>
49629              </fields>
49630            </register>
49631            <register>
49632              <name>GPIF_DATA_COMP_VALUE_WORD1</name>
49633              <description>Data comparator value</description>
49634              <addressOffset>0x1B4</addressOffset>
49635              <size>32</size>
49636              <access>read-write</access>
49637              <resetValue>0x0</resetValue>
49638              <resetMask>0xFFFFFFFF</resetMask>
49639              <fields>
49640                <field>
49641                  <name>VALUE</name>
49642                  <description>Output true when Data  bus matches this value</description>
49643                  <bitRange>[31:0]</bitRange>
49644                  <access>read-write</access>
49645                </field>
49646              </fields>
49647            </register>
49648            <register>
49649              <name>GPIF_DATA_COMP_VALUE_WORD2</name>
49650              <description>Data comparator value</description>
49651              <addressOffset>0x1B8</addressOffset>
49652              <size>32</size>
49653              <access>read-write</access>
49654              <resetValue>0x0</resetValue>
49655              <resetMask>0xFFFFFFFF</resetMask>
49656              <fields>
49657                <field>
49658                  <name>VALUE</name>
49659                  <description>Output true when Data  bus matches this value</description>
49660                  <bitRange>[31:0]</bitRange>
49661                  <access>read-write</access>
49662                </field>
49663              </fields>
49664            </register>
49665            <register>
49666              <name>GPIF_DATA_COMP_VALUE_WORD3</name>
49667              <description>Data comparator value</description>
49668              <addressOffset>0x1BC</addressOffset>
49669              <size>32</size>
49670              <access>read-write</access>
49671              <resetValue>0x0</resetValue>
49672              <resetMask>0xFFFFFFFF</resetMask>
49673              <fields>
49674                <field>
49675                  <name>VALUE</name>
49676                  <description>Output true when Data  bus matches this value</description>
49677                  <bitRange>[31:0]</bitRange>
49678                  <access>read-write</access>
49679                </field>
49680              </fields>
49681            </register>
49682            <register>
49683              <name>GPIF_DATA_COMP_MASK_WORD0</name>
49684              <description>Data comparator mask</description>
49685              <addressOffset>0x1D0</addressOffset>
49686              <size>32</size>
49687              <access>read-write</access>
49688              <resetValue>0x0</resetValue>
49689              <resetMask>0xFFFFFFFF</resetMask>
49690              <fields>
49691                <field>
49692                  <name>MASK</name>
49693                  <description>1: Bit at this bit position in the Data bus is to be used in comparision
496940: Bit at this bit position is a don't-care for comparision</description>
49695                  <bitRange>[31:0]</bitRange>
49696                  <access>read-write</access>
49697                </field>
49698              </fields>
49699            </register>
49700            <register>
49701              <name>GPIF_DATA_COMP_MASK_WORD1</name>
49702              <description>Data comparator mask</description>
49703              <addressOffset>0x1D4</addressOffset>
49704              <size>32</size>
49705              <access>read-write</access>
49706              <resetValue>0x0</resetValue>
49707              <resetMask>0xFFFFFFFF</resetMask>
49708              <fields>
49709                <field>
49710                  <name>MASK</name>
49711                  <description>1: Bit at this bit position in the Data bus is to be used in comparision
497120: Bit at this bit position is a don't-care for comparision</description>
49713                  <bitRange>[31:0]</bitRange>
49714                  <access>read-write</access>
49715                </field>
49716              </fields>
49717            </register>
49718            <register>
49719              <name>GPIF_DATA_COMP_MASK_WORD2</name>
49720              <description>Data comparator mask</description>
49721              <addressOffset>0x1D8</addressOffset>
49722              <size>32</size>
49723              <access>read-write</access>
49724              <resetValue>0x0</resetValue>
49725              <resetMask>0xFFFFFFFF</resetMask>
49726              <fields>
49727                <field>
49728                  <name>MASK</name>
49729                  <description>1: Bit at this bit position in the Data bus is to be used in comparision
497300: Bit at this bit position is a don't-care for comparision</description>
49731                  <bitRange>[31:0]</bitRange>
49732                  <access>read-write</access>
49733                </field>
49734              </fields>
49735            </register>
49736            <register>
49737              <name>GPIF_DATA_COMP_MASK_WORD3</name>
49738              <description>Data comparator mask</description>
49739              <addressOffset>0x1DC</addressOffset>
49740              <size>32</size>
49741              <access>read-write</access>
49742              <resetValue>0x0</resetValue>
49743              <resetMask>0xFFFFFFFF</resetMask>
49744              <fields>
49745                <field>
49746                  <name>MASK</name>
49747                  <description>1: Bit at this bit position in the Data bus is to be used in comparision
497480: Bit at this bit position is a don't-care for comparision</description>
49749                  <bitRange>[31:0]</bitRange>
49750                  <access>read-write</access>
49751                </field>
49752              </fields>
49753            </register>
49754            <register>
49755              <name>GPIF_ADDR_COMP_VALUE</name>
49756              <description>Address comparator value</description>
49757              <addressOffset>0x1E0</addressOffset>
49758              <size>32</size>
49759              <access>read-write</access>
49760              <resetValue>0x0</resetValue>
49761              <resetMask>0xFFFFFFFF</resetMask>
49762              <fields>
49763                <field>
49764                  <name>VALUE</name>
49765                  <description>Output true when Data  bus matches this value</description>
49766                  <bitRange>[31:0]</bitRange>
49767                  <access>read-write</access>
49768                </field>
49769              </fields>
49770            </register>
49771            <register>
49772              <name>GPIF_ADDR_COMP_MASK</name>
49773              <description>Address comparator mask</description>
49774              <addressOffset>0x1E4</addressOffset>
49775              <size>32</size>
49776              <access>read-write</access>
49777              <resetValue>0x0</resetValue>
49778              <resetMask>0xFFFFFFFF</resetMask>
49779              <fields>
49780                <field>
49781                  <name>MASK</name>
49782                  <description>1: Bit at this bit position in the CTRL bus is to be used in comparison
497830: Bit at this bit position is a don't-care for comparison</description>
49784                  <bitRange>[31:0]</bitRange>
49785                  <access>read-write</access>
49786                </field>
49787              </fields>
49788            </register>
49789            <register>
49790              <name>GPIF_LAMBDA_STAT0</name>
49791              <description>Lambda Status Register</description>
49792              <addressOffset>0x1F0</addressOffset>
49793              <size>32</size>
49794              <access>read-only</access>
49795              <resetValue>0x10000000</resetValue>
49796              <resetMask>0xFFFFFFFF</resetMask>
49797              <fields>
49798                <field>
49799                  <name>LAMBDA</name>
49800                  <description>Current value of the Lambda Inputs</description>
49801                  <bitRange>[31:0]</bitRange>
49802                  <access>read-only</access>
49803                </field>
49804              </fields>
49805            </register>
49806            <register>
49807              <name>GPIF_LAMBDA_STAT1</name>
49808              <description>Lambda Status Register</description>
49809              <addressOffset>0x1F4</addressOffset>
49810              <size>32</size>
49811              <access>read-only</access>
49812              <resetValue>0x0</resetValue>
49813              <resetMask>0xFFFFFFFF</resetMask>
49814              <fields>
49815                <field>
49816                  <name>LAMBDA</name>
49817                  <description>Current value of the Lambda Inputs</description>
49818                  <bitRange>[31:0]</bitRange>
49819                  <access>read-only</access>
49820                </field>
49821              </fields>
49822            </register>
49823            <register>
49824              <name>GPIF_ALPHA_STAT</name>
49825              <description>Alpha Status Register</description>
49826              <addressOffset>0x1F8</addressOffset>
49827              <size>32</size>
49828              <access>read-only</access>
49829              <resetValue>0x0</resetValue>
49830              <resetMask>0xFF</resetMask>
49831              <fields>
49832                <field>
49833                  <name>ALPHA</name>
49834                  <description>Current value of the Alpha signals</description>
49835                  <bitRange>[7:0]</bitRange>
49836                  <access>read-only</access>
49837                </field>
49838              </fields>
49839            </register>
49840            <register>
49841              <name>GPIF_BETA_STAT</name>
49842              <description>Beta Status Register</description>
49843              <addressOffset>0x1FC</addressOffset>
49844              <size>32</size>
49845              <access>read-only</access>
49846              <resetValue>0x0</resetValue>
49847              <resetMask>0xFFFFFFFF</resetMask>
49848              <fields>
49849                <field>
49850                  <name>BETA_VAL</name>
49851                  <description>Current value of the Beta signals</description>
49852                  <bitRange>[31:0]</bitRange>
49853                  <access>read-only</access>
49854                </field>
49855              </fields>
49856            </register>
49857            <register>
49858              <name>GPIF_WAVEFORM_CTRL_STAT</name>
49859              <description>Waveform program control</description>
49860              <addressOffset>0x200</addressOffset>
49861              <size>32</size>
49862              <access>read-write</access>
49863              <resetValue>0x0</resetValue>
49864              <resetMask>0xFFFF0F03</resetMask>
49865              <fields>
49866                <field>
49867                  <name>WAVEFORM_VALID</name>
49868                  <description>1:  The waveform memory is consistent and valid.
498690: Waveforms are no longer valid, stop operation and return outputs to default state</description>
49870                  <bitRange>[0:0]</bitRange>
49871                  <access>read-write</access>
49872                </field>
49873                <field>
49874                  <name>PAUSE</name>
49875                  <description>Write 1 here to pause GPIF. 0 to resume where left off.</description>
49876                  <bitRange>[1:1]</bitRange>
49877                  <access>read-write</access>
49878                </field>
49879                <field>
49880                  <name>GPIF_STAT</name>
49881                  <description>0: Waveform is not valid (Initial state or WAVEFORM_VALID is cleared)
498821: &lt;unused&gt;
498832: GPIF is armed (WAVEFORM_VALID is set)
498843: GPIF is running (using WAVEFORM_SWITCH)
498854: GPIF is done (encountered DONE_STATE)
498865: GPIF is paused (PAUSE=0)
498876: GPIF is switching (waiting for timeout/terminal state)
498887: An error occurred</description>
49889                  <bitRange>[10:8]</bitRange>
49890                  <access>read-only</access>
49891                </field>
49892                <field>
49893                  <name>CPU_LAMBDA</name>
49894                  <description>Visible to the state machine as lambda 34.</description>
49895                  <bitRange>[11:11]</bitRange>
49896                  <access>read-write</access>
49897                </field>
49898                <field>
49899                  <name>ALPHA_INIT</name>
49900                  <description>Initial values for alpha outputs.  These are loaded into the alpha registers when GPIF execution starts (first WAVEFORM_SWITCH) is set.</description>
49901                  <bitRange>[23:16]</bitRange>
49902                  <access>read-write</access>
49903                </field>
49904                <field>
49905                  <name>CURRENT_STATE</name>
49906                  <description>Current state of GPIF. Always updated.</description>
49907                  <bitRange>[31:24]</bitRange>
49908                  <access>read-only</access>
49909                </field>
49910              </fields>
49911            </register>
49912            <register>
49913              <name>GPIF_WAVEFORM_SWITCH</name>
49914              <description>Waveform switch control</description>
49915              <addressOffset>0x204</addressOffset>
49916              <size>32</size>
49917              <access>read-write</access>
49918              <resetValue>0x0</resetValue>
49919              <resetMask>0xFFFFFFFF</resetMask>
49920              <fields>
49921                <field>
49922                  <name>WAVEFORM_SWITCH</name>
49923                  <description>SW sets this bit after programming the switch register. HW clears it after the switch is complete.</description>
49924                  <bitRange>[0:0]</bitRange>
49925                  <access>read-write</access>
49926                </field>
49927                <field>
49928                  <name>DONE_ENABLE</name>
49929                  <description>1: Enable checking for DONE_STATE and generation of GPIF_DONE.</description>
49930                  <bitRange>[1:1]</bitRange>
49931                  <access>read-write</access>
49932                </field>
49933                <field>
49934                  <name>SWITCH_NOW</name>
49935                  <description>1: Do not wait for TERMINAL_STATE, switch right away</description>
49936                  <bitRange>[2:2]</bitRange>
49937                  <access>read-write</access>
49938                </field>
49939                <field>
49940                  <name>TIMEOUT_MODE</name>
49941                  <description>0: Timeout disable
499421: Timeout for reaching TERMINAL_STATE.  Interrupt on timeout
499432: Timeout for reaching DONE_STATE.  Interrupt on timeout
499443: Timeout for reaching TERMINAL STATE.  Force switch on timeout.
499454: Timeout for hanging in current state. Timer resets on each transition.</description>
49946                  <bitRange>[5:3]</bitRange>
49947                  <access>read-write</access>
49948                </field>
49949                <field>
49950                  <name>TIMEOUT_REACHED</name>
49951                  <description>Indicates that timeout was reached since last WAVEFORM_SWITCH</description>
49952                  <bitRange>[6:6]</bitRange>
49953                  <access>read-only</access>
49954                </field>
49955                <field>
49956                  <name>TERMINATED</name>
49957                  <description>Indicates that the TERMINAL_STATE was reached since last WAVEFORM_SWITCH</description>
49958                  <bitRange>[7:7]</bitRange>
49959                  <access>read-only</access>
49960                </field>
49961                <field>
49962                  <name>TERMINAL_STATE</name>
49963                  <description>State from which to initiate the switch. Corresponds to idle states of waveforms.</description>
49964                  <bitRange>[15:8]</bitRange>
49965                  <access>read-write</access>
49966                </field>
49967                <field>
49968                  <name>DESTINATION_STATE</name>
49969                  <description>State to jump to, may be the initial state of the new wavform.</description>
49970                  <bitRange>[23:16]</bitRange>
49971                  <access>read-write</access>
49972                </field>
49973                <field>
49974                  <name>DONE_STATE</name>
49975                  <description>Signal GPIF_DONE upon reaching this state.</description>
49976                  <bitRange>[31:24]</bitRange>
49977                  <access>read-write</access>
49978                </field>
49979              </fields>
49980            </register>
49981            <register>
49982              <name>GPIF_WAVEFORM_SWITCH_TIMEOUT</name>
49983              <description>Waveform timeout register</description>
49984              <addressOffset>0x208</addressOffset>
49985              <size>32</size>
49986              <access>read-write</access>
49987              <resetValue>0x0</resetValue>
49988              <resetMask>0xFFFFFFFF</resetMask>
49989              <fields>
49990                <field>
49991                  <name>RESET_LOAD</name>
49992                  <description>Timeout value</description>
49993                  <bitRange>[31:0]</bitRange>
49994                  <access>read-write</access>
49995                </field>
49996              </fields>
49997            </register>
49998            <register>
49999              <name>GPIF_CRC_CONFIG</name>
50000              <description>CRC Configuration Register</description>
50001              <addressOffset>0x210</addressOffset>
50002              <size>32</size>
50003              <access>read-write</access>
50004              <resetValue>0x0</resetValue>
50005              <resetMask>0x8070FFFF</resetMask>
50006              <fields>
50007                <field>
50008                  <name>CRC_RECEIVED</name>
50009                  <description>A CRC value received on the data inputs by the state machine</description>
50010                  <bitRange>[15:0]</bitRange>
50011                  <access>read-only</access>
50012                </field>
50013                <field>
50014                  <name>BIT_ENDIAN</name>
50015                  <description>Indicates the order in which the bits in each byte are brought through the CRC shift register.
500160: LSb first
500171: MSb first</description>
50018                  <bitRange>[20:20]</bitRange>
50019                  <access>read-write</access>
50020                </field>
50021                <field>
50022                  <name>BYTE_ENDIAN</name>
50023                  <description>Indicates the order in which bytes in a 32b word are brought through the CRC shift register. This is independent from the endianness of the interface.
500240: LSB first
500251: MSB first</description>
50026                  <bitRange>[21:21]</bitRange>
50027                  <access>read-write</access>
50028                </field>
50029                <field>
50030                  <name>CRC_ERR</name>
50031                  <description>A CRC was loaded into CRC_RECEIVED that is different from CRC_VALUE</description>
50032                  <bitRange>[22:22]</bitRange>
50033                  <access>read-only</access>
50034                </field>
50035                <field>
50036                  <name>CRC_ENABLE</name>
50037                  <description>Enables CRC calulation</description>
50038                  <bitRange>[31:31]</bitRange>
50039                  <access>read-write</access>
50040                </field>
50041              </fields>
50042            </register>
50043            <register>
50044              <name>GPIF_BETA_DEASSERT</name>
50045              <description>Beta Deassert Register</description>
50046              <addressOffset>0x218</addressOffset>
50047              <size>32</size>
50048              <access>read-write</access>
50049              <resetValue>0x1</resetValue>
50050              <resetMask>0xFFFFFFFF</resetMask>
50051              <fields>
50052                <field>
50053                  <name>APPLY_DEASSERT</name>
50054                  <description>1: BETA_DEASSERT from the waveform descriptor applies to this beta. This is not honored for external betas which always behave as if apply_deassert=0
500550: BETA_DEASSERT does not apply. Betas remain asserted throughout the state.</description>
50056                  <bitRange>[31:0]</bitRange>
50057                  <access>read-write</access>
50058                </field>
50059              </fields>
50060            </register>
50061            <register>
50062              <dim>32</dim>
50063              <dimIncrement>4</dimIncrement>
50064              <name>GPIF_FUNCTION[%s]</name>
50065              <description>Transition Function Registers</description>
50066              <addressOffset>0x220</addressOffset>
50067              <size>32</size>
50068              <access>read-write</access>
50069              <resetValue>0x0</resetValue>
50070              <resetMask>0xFFFF</resetMask>
50071              <fields>
50072                <field>
50073                  <name>FUNCTION</name>
50074                  <description>Truth table for transition function. Bit position X contains output when the 4 inputs constitute the value X in binary. For example bit 2 = 1 means in3=0, in2=0, in1=1 and in0=0 will evaluate true for this function.</description>
50075                  <bitRange>[15:0]</bitRange>
50076                  <access>read-write</access>
50077                </field>
50078              </fields>
50079            </register>
50080            <register>
50081              <name>LINK_IDLE_CFG</name>
50082              <description>Link Idle Config register</description>
50083              <addressOffset>0x2B0</addressOffset>
50084              <size>32</size>
50085              <access>read-write</access>
50086              <resetValue>0x0</resetValue>
50087              <resetMask>0xFFFFFFFF</resetMask>
50088              <fields>
50089                <field>
50090                  <name>CLK_OFF_CNT</name>
50091                  <description>After reset if interface clock is off continuously for duration programmed in this field, then it is considered LINK is idle and interrupt is raised.
50092This counter runs on GPIF clock of 240MHz</description>
50093                  <bitRange>[15:0]</bitRange>
50094                  <access>read-write</access>
50095                </field>
50096                <field>
50097                  <name>IDLE_CMD_CNT</name>
50098                  <description>Link is considered idle, when it receives N number of continous IDLE commands on interface and interrupt is raised. N is value programmed in the register field</description>
50099                  <bitRange>[31:16]</bitRange>
50100                  <access>read-write</access>
50101                </field>
50102              </fields>
50103            </register>
50104            <cluster>
50105              <dim>512</dim>
50106              <dimIncrement>16</dimIncrement>
50107              <name>WAVEFORM[%s]</name>
50108              <description>GPIF State Machine Waveform memory. First 256 for Left and last 256 entries for right waveform</description>
50109              <addressOffset>0x00001000</addressOffset>
50110              <register>
50111                <name>WAVEFORM0</name>
50112                <description>GPIF state definition</description>
50113                <addressOffset>0x0</addressOffset>
50114                <size>32</size>
50115                <access>read-write</access>
50116                <resetValue>0x0</resetValue>
50117                <resetMask>0xFFFFFFFF</resetMask>
50118                <fields>
50119                  <field>
50120                    <name>NEXT_STATE</name>
50121                    <description>Next state on left transition</description>
50122                    <bitRange>[7:0]</bitRange>
50123                    <access>read-write</access>
50124                  </field>
50125                  <field>
50126                    <name>FA</name>
50127                    <description>Index to select the first input for transition fuctions out of 32 choices.</description>
50128                    <bitRange>[12:8]</bitRange>
50129                    <access>read-write</access>
50130                  </field>
50131                  <field>
50132                    <name>FB</name>
50133                    <description>Second input index.</description>
50134                    <bitRange>[17:13]</bitRange>
50135                    <access>read-write</access>
50136                  </field>
50137                  <field>
50138                    <name>FC</name>
50139                    <description>Third input index.</description>
50140                    <bitRange>[22:18]</bitRange>
50141                    <access>read-write</access>
50142                  </field>
50143                  <field>
50144                    <name>FD</name>
50145                    <description>Fourth input index</description>
50146                    <bitRange>[27:23]</bitRange>
50147                    <access>read-write</access>
50148                  </field>
50149                  <field>
50150                    <name>F0_L</name>
50151                    <description>Lower four bits of index to select the first transition function from a choice of 32 functions. Truth-tables for the 32 4-bit functions are defined using the GPIF_FUNCTION registers.</description>
50152                    <bitRange>[31:28]</bitRange>
50153                    <access>read-write</access>
50154                  </field>
50155                </fields>
50156              </register>
50157              <register>
50158                <name>WAVEFORM1</name>
50159                <description>GPIF state definition</description>
50160                <addressOffset>0x4</addressOffset>
50161                <size>32</size>
50162                <access>read-write</access>
50163                <resetValue>0x0</resetValue>
50164                <resetMask>0xFFFFFFFF</resetMask>
50165                <fields>
50166                  <field>
50167                    <name>F0_U</name>
50168                    <description>MSB of index to select the first transition function from a choice of 32 functions. Truth-tables for the 32 4-bit functions are defined using the GPIF_FUNCTION registers.</description>
50169                    <bitRange>[0:0]</bitRange>
50170                    <access>read-write</access>
50171                  </field>
50172                  <field>
50173                    <name>F1</name>
50174                    <description>Index to select the second transition function from a choice of 32 functions. Truth-tables for the 32 4-bit functions are defined using the GPIF_FUNCTION registers.</description>
50175                    <bitRange>[5:1]</bitRange>
50176                    <access>read-write</access>
50177                  </field>
50178                  <field>
50179                    <name>ALPHA_LEFT</name>
50180                    <description>Primary outputs for the left edge of the next state.</description>
50181                    <bitRange>[13:6]</bitRange>
50182                    <access>read-write</access>
50183                  </field>
50184                  <field>
50185                    <name>ALPHA_RIGHT</name>
50186                    <description>Primary outputs for the right edge of the next state</description>
50187                    <bitRange>[21:14]</bitRange>
50188                    <access>read-write</access>
50189                  </field>
50190                  <field>
50191                    <name>BETA_L</name>
50192                    <description>Values for the secondary outputs [9:0] associated with this state.</description>
50193                    <bitRange>[31:22]</bitRange>
50194                    <access>read-write</access>
50195                  </field>
50196                </fields>
50197              </register>
50198              <register>
50199                <name>WAVEFORM2</name>
50200                <description>GPIF state definition</description>
50201                <addressOffset>0x8</addressOffset>
50202                <size>32</size>
50203                <access>read-write</access>
50204                <resetValue>0x0</resetValue>
50205                <resetMask>0xFFFFFFFF</resetMask>
50206                <fields>
50207                  <field>
50208                    <name>BETA_U</name>
50209                    <description>Values for the secondary outputs [31:10] associated with this state.</description>
50210                    <bitRange>[21:0]</bitRange>
50211                    <access>read-write</access>
50212                  </field>
50213                  <field>
50214                    <name>REPEAT_COUNT</name>
50215                    <description>Number of times to stay in this state -1</description>
50216                    <bitRange>[29:22]</bitRange>
50217                    <access>read-write</access>
50218                  </field>
50219                  <field>
50220                    <name>BETA_DEASSERT</name>
50221                    <description>0: Keep betas asserted throughout the state
502221: De-assert after asserting for exactly one clock cycle, irrespective of how many cycles the state is active.
50223The normal (de-assert) state of user defined betas is defined in GPIF_CTRL_BUS_DEFAULT. The normal state of internal betas is fixed by hardware. This function is applied only to betas selected in GPIF_BETA_DEASSERT.</description>
50224                    <bitRange>[30:30]</bitRange>
50225                    <access>read-write</access>
50226                  </field>
50227                  <field>
50228                    <name>VALID</name>
50229                    <description>1: This entry is valid.
502300: Entry not valid. (Not programmed or edge does not exist)</description>
50231                    <bitRange>[31:31]</bitRange>
50232                    <access>read-write</access>
50233                  </field>
50234                </fields>
50235              </register>
50236              <register>
50237                <name>WAVEFORM3</name>
50238                <description>GPIF state definition</description>
50239                <addressOffset>0xC</addressOffset>
50240                <size>32</size>
50241                <access>read-write</access>
50242                <resetValue>0x0</resetValue>
50243                <resetMask>0xFFFFFFFF</resetMask>
50244                <fields>
50245                  <field>
50246                    <name>RSVD</name>
50247                    <description>N/A</description>
50248                    <bitRange>[31:0]</bitRange>
50249                    <access>read-write</access>
50250                  </field>
50251                </fields>
50252              </register>
50253            </cluster>
50254          </cluster>
50255          <cluster>
50256            <dim>2</dim>
50257            <dimIncrement>2048</dimIncrement>
50258            <name>AFE[%s]</name>
50259            <description>Phy Configuration Registers</description>
50260            <addressOffset>0x00007000</addressOffset>
50261            <register>
50262              <name>DLL_DFTLPF</name>
50263              <description>DLL Low-Pass Filter Config Register</description>
50264              <addressOffset>0x0</addressOffset>
50265              <size>32</size>
50266              <access>read-write</access>
50267              <resetValue>0x3F3</resetValue>
50268              <resetMask>0x1F</resetMask>
50269              <fields>
50270                <field>
50271                  <name>MUX_SEL</name>
50272                  <description>Selection Bits of Low-Pass Filter Multiplexer
502730000b: Data Channel 0 input (fixed DC expected, DC depends on learning pattern)
502740001b: Data Channel 1 input (fixed DC expected, DC depends on learning pattern)
502750010b: Data Channel 2 input (fixed DC expected, DC depends on learning pattern)
502760011b: Data Channel 3 input (fixed DC expected, DC depends on learning pattern)
502770100b: Data Channel 4 input (fixed DC expected, DC depends on learning pattern)
502780101b: Data Channel 5 input (fixed DC expected, DC depends on learning pattern)
502790110b: Data Channel 6 input (fixed DC expected, DC depends on learning pattern)
502800111b: Data Channel 7 input (fixed DC expected, DC depends on learning pattern)
502811000b: Frame Clock input (fixed DC expected, DC depends on learning pattern)
502821001b (default)-1011b: Ground input (0 percentDC expected)</description>
50283                  <bitRange>[3:0]</bitRange>
50284                  <access>read-write</access>
50285                </field>
50286                <field>
50287                  <name>FILT_SEL</name>
50288                  <description>Low-Pass Filter Charge Time Selection
502890 (default): lower RC filter time constant (faster charge/discharge)</description>
50290                  <bitRange>[4:4]</bitRange>
50291                  <access>read-write</access>
50292                </field>
50293              </fields>
50294            </register>
50295            <register>
50296              <name>DLL_CONFIG</name>
50297              <description>DLL Configuration Register</description>
50298              <addressOffset>0x4</addressOffset>
50299              <size>32</size>
50300              <access>read-write</access>
50301              <resetValue>0x0</resetValue>
50302              <resetMask>0x1</resetMask>
50303              <fields>
50304                <field>
50305                  <name>DFT_RINGO_RST</name>
50306                  <description>DLL Reset for DfT
503070 (default): Test Clock Disabled</description>
50308                  <bitRange>[0:0]</bitRange>
50309                  <access>read-write</access>
50310                </field>
50311              </fields>
50312            </register>
50313            <register>
50314              <name>DLL_STATUS</name>
50315              <description>DLL Status Register</description>
50316              <addressOffset>0x8</addressOffset>
50317              <size>32</size>
50318              <access>read-only</access>
50319              <resetValue>0x0</resetValue>
50320              <resetMask>0x3F</resetMask>
50321              <fields>
50322                <field>
50323                  <name>FT</name>
50324                  <description>DLL Fine Tuning controlled by digital FSM</description>
50325                  <bitRange>[5:0]</bitRange>
50326                  <access>read-only</access>
50327                </field>
50328              </fields>
50329            </register>
50330            <register>
50331              <name>DLL_M_CONFIG</name>
50332              <description>Master DLL Config Register</description>
50333              <addressOffset>0xC</addressOffset>
50334              <size>32</size>
50335              <access>read-write</access>
50336              <resetValue>0x0</resetValue>
50337              <resetMask>0x3FF</resetMask>
50338              <fields>
50339                <field>
50340                  <name>EN</name>
50341                  <description>DLL Enable
503420 (default): DLL disabled</description>
50343                  <bitRange>[0:0]</bitRange>
50344                  <access>read-write</access>
50345                </field>
50346                <field>
50347                  <name>CLK_SEL</name>
50348                  <description>DLL Input Clock Selection
503490b  RINGO PLL serial clock
503501b: external 100MHz</description>
50351                  <bitRange>[1:1]</bitRange>
50352                  <access>read-write</access>
50353                </field>
50354                <field>
50355                  <name>INV_CLK_MUX</name>
50356                  <description>DLL Clock MUX Inversion
503570 (default): DLL is oscillating when in RINGO configuration</description>
50358                  <bitRange>[2:2]</bitRange>
50359                  <access>read-write</access>
50360                </field>
50361                <field>
50362                  <name>DFT_EN</name>
50363                  <description>DLL BIST Enable
503640 (default): DLL BIST disabled</description>
50365                  <bitRange>[3:3]</bitRange>
50366                  <access>read-write</access>
50367                </field>
50368                <field>
50369                  <name>DFT_TEST_CLK_EN</name>
50370                  <description>DfT Clock Enable
503710 (default): Test Clock Disabled</description>
50372                  <bitRange>[4:4]</bitRange>
50373                  <access>read-write</access>
50374                </field>
50375                <field>
50376                  <name>DFT_BBPD_EN</name>
50377                  <description>Used to enable dft_bbpd_o
503780 (default): DFT outputs disabled</description>
50379                  <bitRange>[5:5]</bitRange>
50380                  <access>read-write</access>
50381                </field>
50382                <field>
50383                  <name>DFT_BBPD_SEL</name>
50384                  <description>Selection of dft_bbpd_o. Signal to be sent to DTB
5038500b (default): no signal
5038601b: BBPD sampling clock
5038710b: BBPD sampled data
5038811b: BBPD output</description>
50389                  <bitRange>[7:6]</bitRange>
50390                  <access>read-write</access>
50391                </field>
50392                <field>
50393                  <name>SPEED_MODE</name>
50394                  <description>Dll_m Speed Mode Selection
503950 (default): High Speed (24 delay elements)
503961: Low Speed (60 delay elements)</description>
50397                  <bitRange>[8:8]</bitRange>
50398                  <access>read-write</access>
50399                </field>
50400                <field>
50401                  <name>ADFT_EN_LV</name>
50402                  <description>Dll_m Connection to Analog Bus Enable
504030 (default): Connection Disabled
504041: Connection Enabled</description>
50405                  <bitRange>[9:9]</bitRange>
50406                  <access>read-write</access>
50407                </field>
50408              </fields>
50409            </register>
50410            <register>
50411              <name>DLL_M_STATUS</name>
50412              <description>Master DLL Status Register</description>
50413              <addressOffset>0x10</addressOffset>
50414              <size>32</size>
50415              <access>read-only</access>
50416              <resetValue>0x0</resetValue>
50417              <resetMask>0xFFF</resetMask>
50418              <fields>
50419                <field>
50420                  <name>SEL_PH</name>
50421                  <description>DLL BIST Phase Selection controlled by digital FSM
50422Default: 0000b</description>
50423                  <bitRange>[3:0]</bitRange>
50424                  <access>read-only</access>
50425                </field>
50426                <field>
50427                  <name>CT</name>
50428                  <description>DLL Coarse Tuning controlled by digital FSM</description>
50429                  <bitRange>[7:4]</bitRange>
50430                  <access>read-only</access>
50431                </field>
50432                <field>
50433                  <name>BBPD</name>
50434                  <description>DLL BBPD Output</description>
50435                  <bitRange>[8:8]</bitRange>
50436                  <access>read-only</access>
50437                </field>
50438                <field>
50439                  <name>DFT_BBPD</name>
50440                  <description>DLL BBPD or sampled clock or sampled data to be sent to DTB</description>
50441                  <bitRange>[9:9]</bitRange>
50442                  <access>read-only</access>
50443                </field>
50444                <field>
50445                  <name>CORRECT_PERIOD</name>
50446                  <description>False Lock Detection Output: DLL Period Check for digital FSM</description>
50447                  <bitRange>[10:10]</bitRange>
50448                  <access>read-only</access>
50449                </field>
50450                <field>
50451                  <name>DLL_LOCK</name>
50452                  <description>Lock Status Indication - 1 = DLL is locked; 0 - Not Locked</description>
50453                  <bitRange>[11:11]</bitRange>
50454                  <access>read-only</access>
50455                </field>
50456              </fields>
50457            </register>
50458            <register>
50459              <dim>12</dim>
50460              <dimIncrement>4</dimIncrement>
50461              <name>DLL_S_CONFIG[%s]</name>
50462              <description>Slave DLL Configuration</description>
50463              <addressOffset>0x14</addressOffset>
50464              <size>32</size>
50465              <access>read-write</access>
50466              <resetValue>0x0</resetValue>
50467              <resetMask>0x7</resetMask>
50468              <fields>
50469                <field>
50470                  <name>INV_CLK_MUXED</name>
50471                  <description>DLL Clock MUX Inversion
504720 (default): DLL is oscillating when in RINGO configuration</description>
50473                  <bitRange>[0:0]</bitRange>
50474                  <access>read-write</access>
50475                </field>
50476                <field>
50477                  <name>SDLL_DFT_EN</name>
50478                  <description>DLL BIST Enable
504790 (default): DLL BIST disabled</description>
50480                  <bitRange>[1:1]</bitRange>
50481                  <access>read-write</access>
50482                </field>
50483                <field>
50484                  <name>SDLL_EN</name>
50485                  <description>DLL Enable
504860 (default): DLL disabled</description>
50487                  <bitRange>[2:2]</bitRange>
50488                  <access>read-write</access>
50489                </field>
50490              </fields>
50491            </register>
50492            <register>
50493              <dim>12</dim>
50494              <dimIncrement>4</dimIncrement>
50495              <name>DLL_S_STATUS[%s]</name>
50496              <description>Slave DLL Status</description>
50497              <addressOffset>0x50</addressOffset>
50498              <size>32</size>
50499              <access>read-only</access>
50500              <resetValue>0x457</resetValue>
50501              <resetMask>0x1F</resetMask>
50502              <fields>
50503                <field>
50504                  <name>SEL_PH</name>
50505                  <description>DLL Replica Phase Selection
50506These bits select the phase to be output and are controlled by the digital skew compensation FSM. Default is 1111b.</description>
50507                  <bitRange>[3:0]</bitRange>
50508                  <access>read-only</access>
50509                </field>
50510                <field>
50511                  <name>CLK_DFT</name>
50512                  <description>DfT Output Signal of the DLL Replica</description>
50513                  <bitRange>[4:4]</bitRange>
50514                  <access>read-only</access>
50515                </field>
50516              </fields>
50517            </register>
50518            <register>
50519              <name>GENERAL_LICIO_CIO</name>
50520              <description>0</description>
50521              <addressOffset>0x80</addressOffset>
50522              <size>32</size>
50523              <access>read-write</access>
50524              <resetValue>0x0</resetValue>
50525              <resetMask>0x3</resetMask>
50526              <fields>
50527                <field>
50528                  <name>LVDS_RTERM_EN</name>
50529                  <description>Differential resistance enable in LVDS mode</description>
50530                  <bitRange>[0:0]</bitRange>
50531                  <access>read-write</access>
50532                </field>
50533                <field>
50534                  <name>LVCMOS_LB_EN</name>
50535                  <description>LVCMOS Core side loopback enable</description>
50536                  <bitRange>[1:1]</bitRange>
50537                  <access>read-write</access>
50538                </field>
50539              </fields>
50540            </register>
50541            <register>
50542              <dim>27</dim>
50543              <dimIncrement>4</dimIncrement>
50544              <name>LICIO_CIO[%s]</name>
50545              <description>0</description>
50546              <addressOffset>0x84</addressOffset>
50547              <size>32</size>
50548              <access>read-write</access>
50549              <resetValue>0x0</resetValue>
50550              <resetMask>0xFFF</resetMask>
50551              <fields>
50552                <field>
50553                  <name>LVCMOS_RX_EN</name>
50554                  <description>LVCMOS receiver enable</description>
50555                  <bitRange>[0:0]</bitRange>
50556                  <access>read-write</access>
50557                </field>
50558                <field>
50559                  <name>LVCMOS_TX_EN</name>
50560                  <description>LVCMOS output enable</description>
50561                  <bitRange>[1:1]</bitRange>
50562                  <access>read-write</access>
50563                </field>
50564                <field>
50565                  <name>DS</name>
50566                  <description>Impedance control select</description>
50567                  <bitRange>[6:2]</bitRange>
50568                  <access>read-write</access>
50569                </field>
50570                <field>
50571                  <name>ATST</name>
50572                  <description>Analog test control bits</description>
50573                  <bitRange>[9:7]</bitRange>
50574                  <access>read-write</access>
50575                </field>
50576                <field>
50577                  <name>SR</name>
50578                  <description>Slew rate select</description>
50579                  <bitRange>[11:10]</bitRange>
50580                  <access>read-write</access>
50581                </field>
50582              </fields>
50583            </register>
50584            <register>
50585              <name>GENERAL_LICIO_LI</name>
50586              <description>0</description>
50587              <addressOffset>0x100</addressOffset>
50588              <size>32</size>
50589              <access>read-write</access>
50590              <resetValue>0x0</resetValue>
50591              <resetMask>0x1</resetMask>
50592              <fields>
50593                <field>
50594                  <name>LVDS_LB_EN</name>
50595                  <description>LVDS Core side loopback enable</description>
50596                  <bitRange>[0:0]</bitRange>
50597                  <access>read-write</access>
50598                </field>
50599              </fields>
50600            </register>
50601            <register>
50602              <dim>10</dim>
50603              <dimIncrement>4</dimIncrement>
50604              <name>LICIO_LI[%s]</name>
50605              <description>0</description>
50606              <addressOffset>0x104</addressOffset>
50607              <size>32</size>
50608              <access>read-write</access>
50609              <resetValue>0x0</resetValue>
50610              <resetMask>0x381</resetMask>
50611              <fields>
50612                <field>
50613                  <name>LVDS_RX_EN</name>
50614                  <description>LVDS receiver enable</description>
50615                  <bitRange>[0:0]</bitRange>
50616                  <access>read-write</access>
50617                </field>
50618                <field>
50619                  <name>ATST</name>
50620                  <description>Analog test control bits</description>
50621                  <bitRange>[9:7]</bitRange>
50622                  <access>read-write</access>
50623                </field>
50624              </fields>
50625            </register>
50626            <register>
50627              <name>LICIO_VSSIO_IREF</name>
50628              <description>0</description>
50629              <addressOffset>0x130</addressOffset>
50630              <size>32</size>
50631              <access>read-write</access>
50632              <resetValue>0x0</resetValue>
50633              <resetMask>0xF</resetMask>
50634              <fields>
50635                <field>
50636                  <name>EN</name>
50637                  <description>Iref Enable</description>
50638                  <bitRange>[0:0]</bitRange>
50639                  <access>read-write</access>
50640                </field>
50641                <field>
50642                  <name>IN_SEL</name>
50643                  <description>Input iref select: 0=iref_in_10u, 1=iref_in_250n, 2=internal, 3=amuxbus_b</description>
50644                  <bitRange>[2:1]</bitRange>
50645                  <access>read-write</access>
50646                </field>
50647                <field>
50648                  <name>ATST_EN</name>
50649                  <description>Analog test enable</description>
50650                  <bitRange>[3:3]</bitRange>
50651                  <access>read-write</access>
50652                </field>
50653              </fields>
50654            </register>
50655            <register>
50656              <name>LICIO_VSSIO_VREF</name>
50657              <description>0</description>
50658              <addressOffset>0x134</addressOffset>
50659              <size>32</size>
50660              <access>read-write</access>
50661              <resetValue>0x0</resetValue>
50662              <resetMask>0x383</resetMask>
50663              <fields>
50664                <field>
50665                  <name>EN</name>
50666                  <description>Vref Enable</description>
50667                  <bitRange>[0:0]</bitRange>
50668                  <access>read-write</access>
50669                </field>
50670                <field>
50671                  <name>LEVEL_SEL</name>
50672                  <description>Selection between 0:50 percent and 1:45 percent of v(Vddio); 50 percent for 1.8V and 2.5V LVCMOS, 45 percent for 3.3V &amp; LVTTL</description>
50673                  <bitRange>[1:1]</bitRange>
50674                  <access>read-write</access>
50675                </field>
50676                <field>
50677                  <name>ATST</name>
50678                  <description>Analog test control bits</description>
50679                  <bitRange>[9:7]</bitRange>
50680                  <access>read-write</access>
50681                </field>
50682              </fields>
50683            </register>
50684            <register>
50685              <name>PLL_CONFIG</name>
50686              <description>PLL Configuration register</description>
50687              <addressOffset>0x138</addressOffset>
50688              <size>32</size>
50689              <access>read-write</access>
50690              <resetValue>0x0</resetValue>
50691              <resetMask>0x3FFFFFFF</resetMask>
50692              <fields>
50693                <field>
50694                  <name>PLL_CP_CUR_TRIM</name>
50695                  <description>trim option of analog charge pump (scan mode - can be '0' or '1' - not High Z)</description>
50696                  <bitRange>[1:0]</bitRange>
50697                  <access>read-write</access>
50698                </field>
50699                <field>
50700                  <name>PLL_LDO_VCO_TRIM</name>
50701                  <description>pll ldo vco voltage trim (scan mode - can be '0' or '1' - not High Z)</description>
50702                  <bitRange>[4:2]</bitRange>
50703                  <access>read-write</access>
50704                </field>
50705                <field>
50706                  <name>PLL_LD_DELAY</name>
50707                  <description>trim of phase error window (scan mode - can be '0' or '1' - not High Z)</description>
50708                  <bitRange>[6:5]</bitRange>
50709                  <access>read-write</access>
50710                </field>
50711                <field>
50712                  <name>PLL_EN</name>
50713                  <description>pll operation enable</description>
50714                  <bitRange>[7:7]</bitRange>
50715                  <access>read-write</access>
50716                </field>
50717                <field>
50718                  <name>PLL_LDO_VCO_BYPASS</name>
50719                  <description>periphery ldo bypass (scan mode - can be '0' or '1' - not High Z)</description>
50720                  <bitRange>[8:8]</bitRange>
50721                  <access>read-write</access>
50722                </field>
50723                <field>
50724                  <name>PLL_REF_SEL</name>
50725                  <description>Mux selection bit for input reference clock</description>
50726                  <bitRange>[10:9]</bitRange>
50727                  <access>read-write</access>
50728                </field>
50729                <field>
50730                  <name>PLL_SUPPLY_EN</name>
50731                  <description>pll enable signal (enable at '1') (scan mode - must be '1')</description>
50732                  <bitRange>[11:11]</bitRange>
50733                  <access>read-write</access>
50734                </field>
50735                <field>
50736                  <name>N_IN_DIV</name>
50737                  <description>Input clock divider setting</description>
50738                  <bitRange>[13:12]</bitRange>
50739                  <access>read-write</access>
50740                </field>
50741                <field>
50742                  <name>N_SERIAL_DIV</name>
50743                  <description>Serial output divider setting</description>
50744                  <bitRange>[15:14]</bitRange>
50745                  <access>read-write</access>
50746                </field>
50747                <field>
50748                  <name>N_FRAME_DIV</name>
50749                  <description>Frame output divider setting</description>
50750                  <bitRange>[16:16]</bitRange>
50751                  <access>read-write</access>
50752                </field>
50753                <field>
50754                  <name>N_FB_DIV</name>
50755                  <description>Feedback divider setting</description>
50756                  <bitRange>[19:17]</bitRange>
50757                  <access>read-write</access>
50758                </field>
50759                <field>
50760                  <name>PLL_ATST_SEL</name>
50761                  <description>testmode decoded pins</description>
50762                  <bitRange>[23:20]</bitRange>
50763                  <access>read-write</access>
50764                </field>
50765                <field>
50766                  <name>PLL_RUN_AWAY_DEL</name>
50767                  <description>delay from run away comparator flip - to start forcing pll</description>
50768                  <bitRange>[25:24]</bitRange>
50769                  <access>read-write</access>
50770                </field>
50771                <field>
50772                  <name>PLL_RUN_AWAY_DIS</name>
50773                  <description>'1' - disable run away operation</description>
50774                  <bitRange>[26:26]</bitRange>
50775                  <access>read-write</access>
50776                </field>
50777                <field>
50778                  <name>PLL_RUN_AWAY_TRIM</name>
50779                  <description>define run away level</description>
50780                  <bitRange>[28:27]</bitRange>
50781                  <access>read-write</access>
50782                </field>
50783                <field>
50784                  <name>PLL_VCO_INIT_DIS</name>
50785                  <description>disable initial condition of the ring</description>
50786                  <bitRange>[29:29]</bitRange>
50787                  <access>read-write</access>
50788                </field>
50789              </fields>
50790            </register>
50791            <register>
50792              <name>PLL_CONFIG_2</name>
50793              <description>PLL Configuration register2</description>
50794              <addressOffset>0x13C</addressOffset>
50795              <size>32</size>
50796              <access>read-write</access>
50797              <resetValue>0x0</resetValue>
50798              <resetMask>0x1FF</resetMask>
50799              <fields>
50800                <field>
50801                  <name>PLL_LDO_CORE_TRIM</name>
50802                  <description>Spare bits</description>
50803                  <bitRange>[2:0]</bitRange>
50804                  <access>read-write</access>
50805                </field>
50806                <field>
50807                  <name>PLL_CAL_UP_DN</name>
50808                  <description>up/dn calibration mismatch</description>
50809                  <bitRange>[6:3]</bitRange>
50810                  <access>read-write</access>
50811                </field>
50812                <field>
50813                  <name>PLL_RA_UP_TR</name>
50814                  <description>define run away upper level</description>
50815                  <bitRange>[8:7]</bitRange>
50816                  <access>read-write</access>
50817                </field>
50818              </fields>
50819            </register>
50820            <register>
50821              <name>PLL_STATUS</name>
50822              <description>PLL Status Register</description>
50823              <addressOffset>0x140</addressOffset>
50824              <size>32</size>
50825              <access>read-only</access>
50826              <resetValue>0x0</resetValue>
50827              <resetMask>0x7F</resetMask>
50828              <fields>
50829                <field>
50830                  <name>PLL_VCO_GAIN</name>
50831                  <description>Kvco trim change (scan mode - can be '0' or '1' - not High Z)</description>
50832                  <bitRange>[3:0]</bitRange>
50833                  <access>read-only</access>
50834                </field>
50835                <field>
50836                  <name>PLL_DFT</name>
50837                  <description>logic dft output</description>
50838                  <bitRange>[4:4]</bitRange>
50839                  <access>read-only</access>
50840                </field>
50841                <field>
50842                  <name>PLL_LOCK</name>
50843                  <description>pll lock signal (scan mode - forced to '0')</description>
50844                  <bitRange>[5:5]</bitRange>
50845                  <access>read-only</access>
50846                </field>
50847                <field>
50848                  <name>PLL_RUN_AWAY_STICKY</name>
50849                  <description>run away occur at the system (will be reset only when pll is disable)</description>
50850                  <bitRange>[6:6]</bitRange>
50851                  <access>read-only</access>
50852                </field>
50853              </fields>
50854            </register>
50855            <register>
50856              <name>REG_1P25</name>
50857              <description>0</description>
50858              <addressOffset>0x144</addressOffset>
50859              <size>32</size>
50860              <access>read-write</access>
50861              <resetValue>0x0</resetValue>
50862              <resetMask>0x7FFF</resetMask>
50863              <fields>
50864                <field>
50865                  <name>IREF_DLL_SEL</name>
50866                  <description>Selection Bits to tune DLL reference current</description>
50867                  <bitRange>[2:0]</bitRange>
50868                  <access>read-write</access>
50869                </field>
50870                <field>
50871                  <name>ENABLE</name>
50872                  <description>Enable of LDO from 3.3V to 1.2V
508730 (default): LDO disabled</description>
50874                  <bitRange>[3:3]</bitRange>
50875                  <access>read-write</access>
50876                </field>
50877                <field>
50878                  <name>USE_REG</name>
50879                  <description>Use of regulator of switch from vccd to vout_1p25
508800: Bypass regulator and connect vccd to vout_1p25
508811: Use regulator to generate vout_1p25</description>
50882                  <bitRange>[4:4]</bitRange>
50883                  <access>read-write</access>
50884                </field>
50885                <field>
50886                  <name>ADFT_CTRL</name>
50887                  <description>Selection of analog MUX connectivity to adft[1:0]</description>
50888                  <bitRange>[8:5]</bitRange>
50889                  <access>read-write</access>
50890                </field>
50891                <field>
50892                  <name>ADFT_EN</name>
50893                  <description>Enable of analog MUX for DfT
508940 (default): AMUX disabled</description>
50895                  <bitRange>[9:9]</bitRange>
50896                  <access>read-write</access>
50897                </field>
50898                <field>
50899                  <name>BURN_IN_EN</name>
50900                  <description>Enable of DLL Burn-in for 1.2V regulated domain
509010 (default): DLL Burn-In disabled</description>
50902                  <bitRange>[10:10]</bitRange>
50903                  <access>read-write</access>
50904                </field>
50905                <field>
50906                  <name>TRIM_VREG_1P25</name>
50907                  <description>Selection of feedback resistor for LDO output voltage
50908If DLL Burn-in Disabled
509090111b (default): 1.2V
50910
50911if DLL Burn-In Enabled
509120111b (default): 1.45V</description>
50913                  <bitRange>[14:11]</bitRange>
50914                  <access>read-write</access>
50915                </field>
50916              </fields>
50917            </register>
50918            <register>
50919              <dim>10</dim>
50920              <dimIncrement>4</dimIncrement>
50921              <name>RX[%s]</name>
50922              <description>0</description>
50923              <addressOffset>0x148</addressOffset>
50924              <size>32</size>
50925              <access>read-write</access>
50926              <resetValue>0x0</resetValue>
50927              <resetMask>0x1F</resetMask>
50928              <fields>
50929                <field>
50930                  <name>FIXTIME_FRAMECLK</name>
50931                  <description>Inversion of Data Channel X Frame Clock
50932This bit is used to invert the frame clock used inside Data Channel X Deserializer before the frame clock itself enters the STS. This is done to avoid setup time violations inside the STS.
509330 (default): Same edge is used for deserialization in analog and resampling the STS.</description>
50934                  <bitRange>[0:0]</bitRange>
50935                  <access>read-write</access>
50936                </field>
50937                <field>
50938                  <name>EN_DESER</name>
50939                  <description>Enable of Data Deserializer
509400 (default): Deserializer disabled
509411: Deserializer enabled</description>
50942                  <bitRange>[1:1]</bitRange>
50943                  <access>read-write</access>
50944                </field>
50945                <field>
50946                  <name>INV_CLK_FRAME</name>
50947                  <description>Invert Polarity of Frame Clock
509480 (default): rising edge of frame clock defines parallel data
509491: falling edge of frame clock defines parallel data</description>
50950                  <bitRange>[2:2]</bitRange>
50951                  <access>read-write</access>
50952                </field>
50953                <field>
50954                  <name>INV_CLK_SER</name>
50955                  <description>Invert Polarity of Serial Clock
509560 (default): select 0 degrees phase of serial clock
509571: select 180 degrees phase of serial clock</description>
50958                  <bitRange>[3:3]</bitRange>
50959                  <access>read-write</access>
50960                </field>
50961                <field>
50962                  <name>INV_DATA_SER</name>
50963                  <description>Polarity Inversion of Serial Data
509640 (default): select phase 0 of serial data
509651: select 180 degrees phase shift of serial data</description>
50966                  <bitRange>[4:4]</bitRange>
50967                  <access>read-write</access>
50968                </field>
50969              </fields>
50970            </register>
50971            <register>
50972              <name>GENERAL_RX</name>
50973              <description>General RX Configuration Registers</description>
50974              <addressOffset>0x170</addressOffset>
50975              <size>32</size>
50976              <access>read-write</access>
50977              <resetValue>0x0</resetValue>
50978              <resetMask>0x3</resetMask>
50979              <fields>
50980                <field>
50981                  <name>DR_MODE</name>
50982                  <description>MUX Selection Signal for 8 bits output
509830 (default): Double Data Rate
509841: Single Data Rate</description>
50985                  <bitRange>[0:0]</bitRange>
50986                  <access>read-write</access>
50987                </field>
50988                <field>
50989                  <name>BER_RSTN</name>
50990                  <description>BER reset, active LOW</description>
50991                  <bitRange>[1:1]</bitRange>
50992                  <access>read-write</access>
50993                </field>
50994              </fields>
50995            </register>
50996            <register>
50997              <name>GENERAL_RX_LVCMOS</name>
50998              <description>General LVCMOS RX Configuration Registers</description>
50999              <addressOffset>0x174</addressOffset>
51000              <size>32</size>
51001              <access>read-write</access>
51002              <resetValue>0x0</resetValue>
51003              <resetMask>0xE</resetMask>
51004              <fields>
51005                <field>
51006                  <name>CLK_MODE</name>
51007                  <description>Sampling Clock Inversion.
510080 (default): Rising and Falling Clock Edges are not inverted
510091: Rising and Falling Clock Edges are inverted (used in SDR reception)</description>
51010                  <bitRange>[1:1]</bitRange>
51011                  <access>read-write</access>
51012                </field>
51013                <field>
51014                  <name>EN_DDR</name>
51015                  <description>DDR Enable.
510160 (default): DDR Sampler is off.
510171: DDR Sampler is on.</description>
51018                  <bitRange>[2:2]</bitRange>
51019                  <access>read-write</access>
51020                </field>
51021                <field>
51022                  <name>BYPASS_SKEW_EN</name>
51023                  <description>Sampling Clock Selection.</description>
51024                  <bitRange>[3:3]</bitRange>
51025                  <access>read-write</access>
51026                </field>
51027              </fields>
51028            </register>
51029            <register>
51030              <dim>26</dim>
51031              <dimIncrement>4</dimIncrement>
51032              <name>RX_LVCMOS[%s]</name>
51033              <description>0</description>
51034              <addressOffset>0x178</addressOffset>
51035              <size>32</size>
51036              <access>read-write</access>
51037              <resetValue>0x0</resetValue>
51038              <resetMask>0x1</resetMask>
51039              <fields>
51040                <field>
51041                  <name>EN_LVCMOS</name>
51042                  <description>LVCMOS Enable.
510430 (default): LVCMOS receiver is off.
510441: SDR Sampler is on.
51045
51046Note: to enable LVCMOS DDR reception, both en_lvcmos and en_ddr are to be set to 1.</description>
51047                  <bitRange>[0:0]</bitRange>
51048                  <access>read-write</access>
51049                </field>
51050              </fields>
51051            </register>
51052            <register>
51053              <name>PRBS_GEN</name>
51054              <description>State counter limit register</description>
51055              <addressOffset>0x204</addressOffset>
51056              <size>32</size>
51057              <access>read-write</access>
51058              <resetValue>0x0</resetValue>
51059              <resetMask>0x7F</resetMask>
51060              <fields>
51061                <field>
51062                  <name>EN</name>
51063                  <description>Enable Signal</description>
51064                  <bitRange>[0:0]</bitRange>
51065                  <access>read-write</access>
51066                </field>
51067                <field>
51068                  <name>SEED</name>
51069                  <description>Input Seed for PRBS Generation. Note: 00000 is not a valid input seed.</description>
51070                  <bitRange>[5:1]</bitRange>
51071                  <access>read-write</access>
51072                </field>
51073                <field>
51074                  <name>DDR_EN</name>
51075                  <description>DDR Bit Stream Generation Enable.
51076
510770(default): DDR generation disabled.
510781: DDR generation enabled.</description>
51079                  <bitRange>[6:6]</bitRange>
51080                  <access>read-write</access>
51081                </field>
51082              </fields>
51083            </register>
51084            <register>
51085              <name>PHY_GENERAL_CONFIG</name>
51086              <description>Phy Configuration register</description>
51087              <addressOffset>0x208</addressOffset>
51088              <size>32</size>
51089              <access>read-write</access>
51090              <resetValue>0x0</resetValue>
51091              <resetMask>0x3F</resetMask>
51092              <fields>
51093                <field>
51094                  <name>DESKEW_ALGORITHM</name>
51095                  <description>Chosen deskew algorithm:
51096
510970(default): bypass
510981: slow
510992: SDR fast
511003: DDR fast</description>
51101                  <bitRange>[1:0]</bitRange>
51102                  <access>read-write</access>
51103                </field>
51104                <field>
51105                  <name>ENABLE_SCANON</name>
51106                  <description>Vddd related enable signal</description>
51107                  <bitRange>[2:2]</bitRange>
51108                  <access>read-write</access>
51109                </field>
51110                <field>
51111                  <name>ENABLE_V1P25_VCCD</name>
51112                  <description>Enable indicating v1p25 is powered</description>
51113                  <bitRange>[3:3]</bitRange>
51114                  <access>read-write</access>
51115                </field>
51116                <field>
51117                  <name>ENABLE_V1P1_VCCD</name>
51118                  <description>Enable indicating v1p1 is powered</description>
51119                  <bitRange>[4:4]</bitRange>
51120                  <access>read-write</access>
51121                </field>
51122                <field>
51123                  <name>ENABLE_VDDIO</name>
51124                  <description>Enable related to VDDIO</description>
51125                  <bitRange>[5:5]</bitRange>
51126                  <access>read-write</access>
51127                </field>
51128              </fields>
51129            </register>
51130            <register>
51131              <name>PHY_GENERAL_STATUS_1</name>
51132              <description>Phy Status register</description>
51133              <addressOffset>0x20C</addressOffset>
51134              <size>32</size>
51135              <access>read-only</access>
51136              <resetValue>0x0</resetValue>
51137              <resetMask>0x3FFFFF</resetMask>
51138              <fields>
51139                <field>
51140                  <name>PRBS_CHECKER_STATE</name>
51141                  <description>Status of the PRBS Checker
51142
511430: not activated
511441: link start-up
511452: locked to a detected sequence
511463: sequence once found, now lost, trying to lock-up again</description>
51147                  <bitRange>[1:0]</bitRange>
51148                  <access>read-only</access>
51149                </field>
51150                <field>
51151                  <name>BER_COUNTER</name>
51152                  <description>Error counter for PRBS Loopback.</description>
51153                  <bitRange>[21:2]</bitRange>
51154                  <access>read-only</access>
51155                </field>
51156              </fields>
51157            </register>
51158            <register>
51159              <name>PHY_GENERAL_STATUS_2</name>
51160              <description>Phy Status register</description>
51161              <addressOffset>0x210</addressOffset>
51162              <size>32</size>
51163              <access>read-only</access>
51164              <resetValue>0x0</resetValue>
51165              <resetMask>0x1FF</resetMask>
51166              <fields>
51167                <field>
51168                  <name>LVDS_LOOPBACK_FLAG</name>
51169                  <description>LVDS Loopback Test Flag
51170
511710(default): LVDS Loopback test not passed
511721: LVDS Loopback Test passed</description>
51173                  <bitRange>[0:0]</bitRange>
51174                  <access>read-only</access>
51175                </field>
51176                <field>
51177                  <name>LVCMOS_LOOPBACK_FLAG</name>
51178                  <description>LVCMOS Loopback Test Flag
51179
511800(default): LVCMOS Loopback test not passed
511811: LVCMOS Loopback Test passed</description>
51182                  <bitRange>[1:1]</bitRange>
51183                  <access>read-only</access>
51184                </field>
51185                <field>
51186                  <name>DESKEW_COMPLETE</name>
51187                  <description>Deskew Algorithm Flag
51188
511890(default): deskew not completed
511901: deskew completed</description>
51191                  <bitRange>[2:2]</bitRange>
51192                  <access>read-only</access>
51193                </field>
51194                <field>
51195                  <name>OK_DLL_V1P1</name>
51196                  <description>v1p1 related enable signal</description>
51197                  <bitRange>[3:3]</bitRange>
51198                  <access>read-only</access>
51199                </field>
51200                <field>
51201                  <name>OK_DLL_VCCD</name>
51202                  <description>Indicates all DLL power supplies are ready</description>
51203                  <bitRange>[4:4]</bitRange>
51204                  <access>read-only</access>
51205                </field>
51206                <field>
51207                  <name>OK_DLL_V1P25</name>
51208                  <description>Indicates all DLL power supplies are ready</description>
51209                  <bitRange>[5:5]</bitRange>
51210                  <access>read-only</access>
51211                </field>
51212                <field>
51213                  <name>OK_VCCD_V1P1</name>
51214                  <description>Indicates that the vccd supply is powered</description>
51215                  <bitRange>[6:6]</bitRange>
51216                  <access>read-only</access>
51217                </field>
51218                <field>
51219                  <name>OK_V1P25_VCCD</name>
51220                  <description>Indicates that the vout_1p25 supply is powered</description>
51221                  <bitRange>[7:7]</bitRange>
51222                  <access>read-only</access>
51223                </field>
51224                <field>
51225                  <name>OK_VCCD_V1P25</name>
51226                  <description>Indicates that the vccd supply is powered</description>
51227                  <bitRange>[8:8]</bitRange>
51228                  <access>read-only</access>
51229                </field>
51230              </fields>
51231            </register>
51232            <register>
51233              <name>PHY_INTR</name>
51234              <description>Phy Interrupt Register</description>
51235              <addressOffset>0x214</addressOffset>
51236              <size>32</size>
51237              <access>read-write</access>
51238              <resetValue>0x0</resetValue>
51239              <resetMask>0x1FF</resetMask>
51240              <fields>
51241                <field>
51242                  <name>LVDS_LOOPBACK_FLAG</name>
51243                  <description>N/A</description>
51244                  <bitRange>[0:0]</bitRange>
51245                  <access>read-write</access>
51246                </field>
51247                <field>
51248                  <name>LVCMOS_LOOPBACK_FLAG</name>
51249                  <description>N/A</description>
51250                  <bitRange>[1:1]</bitRange>
51251                  <access>read-write</access>
51252                </field>
51253                <field>
51254                  <name>DESKEW_COMPLETED</name>
51255                  <description>Set when deskew is completed</description>
51256                  <bitRange>[2:2]</bitRange>
51257                  <access>read-write</access>
51258                </field>
51259                <field>
51260                  <name>OK_DLL_V1P1</name>
51261                  <description>Set when power supply is stable</description>
51262                  <bitRange>[3:3]</bitRange>
51263                  <access>read-write</access>
51264                </field>
51265                <field>
51266                  <name>OK_DLL_VCCD</name>
51267                  <description>Set when power supply is stable</description>
51268                  <bitRange>[4:4]</bitRange>
51269                  <access>read-write</access>
51270                </field>
51271                <field>
51272                  <name>OK_DLL_V1P25</name>
51273                  <description>Set when power supply is stable</description>
51274                  <bitRange>[5:5]</bitRange>
51275                  <access>read-write</access>
51276                </field>
51277                <field>
51278                  <name>OK_VCCD_V1P1</name>
51279                  <description>Set when power supply is stable</description>
51280                  <bitRange>[6:6]</bitRange>
51281                  <access>read-write</access>
51282                </field>
51283                <field>
51284                  <name>OK_V1P25_VCCD</name>
51285                  <description>Set when power supply is stable</description>
51286                  <bitRange>[7:7]</bitRange>
51287                  <access>read-write</access>
51288                </field>
51289                <field>
51290                  <name>OK_VCCD_V1P25</name>
51291                  <description>Set when power supply is stable</description>
51292                  <bitRange>[8:8]</bitRange>
51293                  <access>read-write</access>
51294                </field>
51295              </fields>
51296            </register>
51297            <register>
51298              <name>PHY_INTR_MASK</name>
51299              <description>Phy Interrupt Mask Register</description>
51300              <addressOffset>0x218</addressOffset>
51301              <size>32</size>
51302              <access>read-write</access>
51303              <resetValue>0x0</resetValue>
51304              <resetMask>0x1FF</resetMask>
51305              <fields>
51306                <field>
51307                  <name>LVDS_LOOPBACK_FLAG</name>
51308                  <description>N/A</description>
51309                  <bitRange>[0:0]</bitRange>
51310                  <access>read-write</access>
51311                </field>
51312                <field>
51313                  <name>LVCMOS_LOOPBACK_FLAG</name>
51314                  <description>N/A</description>
51315                  <bitRange>[1:1]</bitRange>
51316                  <access>read-write</access>
51317                </field>
51318                <field>
51319                  <name>DESKEW_COMPLETED</name>
51320                  <description>Set when deskew is completed</description>
51321                  <bitRange>[2:2]</bitRange>
51322                  <access>read-write</access>
51323                </field>
51324                <field>
51325                  <name>OK_DLL_V1P1</name>
51326                  <description>Set when power supply is stable</description>
51327                  <bitRange>[3:3]</bitRange>
51328                  <access>read-write</access>
51329                </field>
51330                <field>
51331                  <name>OK_DLL_VCCD</name>
51332                  <description>Set when power supply is stable</description>
51333                  <bitRange>[4:4]</bitRange>
51334                  <access>read-write</access>
51335                </field>
51336                <field>
51337                  <name>OK_DLL_V1P25</name>
51338                  <description>Set when power supply is stable</description>
51339                  <bitRange>[5:5]</bitRange>
51340                  <access>read-write</access>
51341                </field>
51342                <field>
51343                  <name>OK_VCCD_V1P1</name>
51344                  <description>Set when power supply is stable</description>
51345                  <bitRange>[6:6]</bitRange>
51346                  <access>read-write</access>
51347                </field>
51348                <field>
51349                  <name>OK_V1P25_VCCD</name>
51350                  <description>Set when power supply is stable</description>
51351                  <bitRange>[7:7]</bitRange>
51352                  <access>read-write</access>
51353                </field>
51354                <field>
51355                  <name>OK_VCCD_V1P25</name>
51356                  <description>Set when power supply is stable</description>
51357                  <bitRange>[8:8]</bitRange>
51358                  <access>read-write</access>
51359                </field>
51360              </fields>
51361            </register>
51362            <register>
51363              <name>PHY_INTR_MASKED</name>
51364              <description>Phy Interrupt Masked Register</description>
51365              <addressOffset>0x21C</addressOffset>
51366              <size>32</size>
51367              <access>read-only</access>
51368              <resetValue>0x0</resetValue>
51369              <resetMask>0x1FF</resetMask>
51370              <fields>
51371                <field>
51372                  <name>LVDS_LOOPBACK_FLAG</name>
51373                  <description>N/A</description>
51374                  <bitRange>[0:0]</bitRange>
51375                  <access>read-only</access>
51376                </field>
51377                <field>
51378                  <name>LVCMOS_LOOPBACK_FLAG</name>
51379                  <description>N/A</description>
51380                  <bitRange>[1:1]</bitRange>
51381                  <access>read-only</access>
51382                </field>
51383                <field>
51384                  <name>DESKEW_COMPLETED</name>
51385                  <description>Set when deskew is completed</description>
51386                  <bitRange>[2:2]</bitRange>
51387                  <access>read-only</access>
51388                </field>
51389                <field>
51390                  <name>OK_DLL_V1P1</name>
51391                  <description>Set when power supply is stable</description>
51392                  <bitRange>[3:3]</bitRange>
51393                  <access>read-only</access>
51394                </field>
51395                <field>
51396                  <name>OK_DLL_VCCD</name>
51397                  <description>Set when power supply is stable</description>
51398                  <bitRange>[4:4]</bitRange>
51399                  <access>read-only</access>
51400                </field>
51401                <field>
51402                  <name>OK_DLL_V1P25</name>
51403                  <description>Set when power supply is stable</description>
51404                  <bitRange>[5:5]</bitRange>
51405                  <access>read-only</access>
51406                </field>
51407                <field>
51408                  <name>OK_VCCD_V1P1</name>
51409                  <description>Set when power supply is stable</description>
51410                  <bitRange>[6:6]</bitRange>
51411                  <access>read-only</access>
51412                </field>
51413                <field>
51414                  <name>OK_V1P25_VCCD</name>
51415                  <description>Set when power supply is stable</description>
51416                  <bitRange>[7:7]</bitRange>
51417                  <access>read-only</access>
51418                </field>
51419                <field>
51420                  <name>OK_VCCD_V1P25</name>
51421                  <description>Set when power supply is stable</description>
51422                  <bitRange>[8:8]</bitRange>
51423                  <access>read-only</access>
51424                </field>
51425              </fields>
51426            </register>
51427            <register>
51428              <name>PHY_INTR_SET</name>
51429              <description>Phy Interrupt Set Register</description>
51430              <addressOffset>0x220</addressOffset>
51431              <size>32</size>
51432              <access>read-write</access>
51433              <resetValue>0x0</resetValue>
51434              <resetMask>0x1FF</resetMask>
51435              <fields>
51436                <field>
51437                  <name>LVDS_LOOPBACK_FLAG</name>
51438                  <description>N/A</description>
51439                  <bitRange>[0:0]</bitRange>
51440                  <access>read-write</access>
51441                </field>
51442                <field>
51443                  <name>LVCMOS_LOOPBACK_FLAG</name>
51444                  <description>N/A</description>
51445                  <bitRange>[1:1]</bitRange>
51446                  <access>read-write</access>
51447                </field>
51448                <field>
51449                  <name>DESKEW_COMPLETED</name>
51450                  <description>Set when deskew is completed</description>
51451                  <bitRange>[2:2]</bitRange>
51452                  <access>read-write</access>
51453                </field>
51454                <field>
51455                  <name>OK_DLL_V1P1</name>
51456                  <description>Set when power supply is stable</description>
51457                  <bitRange>[3:3]</bitRange>
51458                  <access>read-write</access>
51459                </field>
51460                <field>
51461                  <name>OK_DLL_VCCD</name>
51462                  <description>Set when power supply is stable</description>
51463                  <bitRange>[4:4]</bitRange>
51464                  <access>read-write</access>
51465                </field>
51466                <field>
51467                  <name>OK_DLL_V1P25</name>
51468                  <description>Set when power supply is stable</description>
51469                  <bitRange>[5:5]</bitRange>
51470                  <access>read-write</access>
51471                </field>
51472                <field>
51473                  <name>OK_VCCD_V1P1</name>
51474                  <description>Set when power supply is stable</description>
51475                  <bitRange>[6:6]</bitRange>
51476                  <access>read-write</access>
51477                </field>
51478                <field>
51479                  <name>OK_V1P25_VCCD</name>
51480                  <description>Set when power supply is stable</description>
51481                  <bitRange>[7:7]</bitRange>
51482                  <access>read-write</access>
51483                </field>
51484                <field>
51485                  <name>OK_VCCD_V1P25</name>
51486                  <description>Set when power supply is stable</description>
51487                  <bitRange>[8:8]</bitRange>
51488                  <access>read-write</access>
51489                </field>
51490              </fields>
51491            </register>
51492          </cluster>
51493          <cluster>
51494            <dim>32</dim>
51495            <dimIncrement>128</dimIncrement>
51496            <name>SCK[%s]</name>
51497            <description>DMA Socket &amp; Descriptor Registers</description>
51498            <addressOffset>0x00008000</addressOffset>
51499            <register>
51500              <name>SCK_DSCR</name>
51501              <description>Descriptor Chain Pointer</description>
51502              <addressOffset>0x0</addressOffset>
51503              <size>32</size>
51504              <access>read-write</access>
51505              <resetValue>0x0</resetValue>
51506              <resetMask>0x0</resetMask>
51507              <fields>
51508                <field>
51509                  <name>DSCR_NUMBER</name>
51510                  <description>Descriptor number of currently active descriptor.  A value of 0xFFFF designates no (more) active descriptors available.  When activating a socket CPU shall write number of first descriptor in here. Only modify this field when go_suspend=1 or go_enable=0</description>
51511                  <bitRange>[15:0]</bitRange>
51512                  <access>read-write</access>
51513                </field>
51514                <field>
51515                  <name>DSCR_COUNT</name>
51516                  <description>Number of descriptors still left to process.  This value is unrelated to actual number of descriptors in the list.  It is used only to generate an interrupt to the CPU when the value goes low or zero (or both).  When this value reaches 0 it will wrap around to 255.  The socket will not suspend or be otherwise affected unless the descriptor chains ends with 0xFFFF descriptor number.</description>
51517                  <bitRange>[23:16]</bitRange>
51518                  <access>read-write</access>
51519                </field>
51520                <field>
51521                  <name>DSCR_LOW</name>
51522                  <description>The low watermark for dscr_count.  When dscr_count is equal or less than dscr_low the status bit dscr_is_low is set and an interrupt can be generated (depending on int mask).</description>
51523                  <bitRange>[31:24]</bitRange>
51524                  <access>read-write</access>
51525                </field>
51526              </fields>
51527            </register>
51528            <register>
51529              <name>SCK_SIZE</name>
51530              <description>Transfer Size Register</description>
51531              <addressOffset>0x4</addressOffset>
51532              <size>32</size>
51533              <access>read-write</access>
51534              <resetValue>0x0</resetValue>
51535              <resetMask>0x0</resetMask>
51536              <fields>
51537                <field>
51538                  <name>TRANS_SIZE</name>
51539                  <description>The number of bytes or buffers (depends on unit bit in SCK_STATUS) that are part of this transfer.  A value of 0 signals an infinite/undetermined transaction size.
51540Valid data bytes remaining in the last buffer beyond the transfer size will be read by socket and passed on to the core. FW must ensure that no additional bytes beyond the transfer size are present in the last buffer.</description>
51541                  <bitRange>[31:0]</bitRange>
51542                  <access>read-write</access>
51543                </field>
51544              </fields>
51545            </register>
51546            <register>
51547              <name>SCK_COUNT</name>
51548              <description>Transfer Count Register</description>
51549              <addressOffset>0x8</addressOffset>
51550              <size>32</size>
51551              <access>read-write</access>
51552              <resetValue>0x0</resetValue>
51553              <resetMask>0x0</resetMask>
51554              <fields>
51555                <field>
51556                  <name>TRANS_COUNT</name>
51557                  <description>The number of bytes or buffers (depends on unit bit in SCK_STATUS) that have been transferred through this socket so far.  If trans_size is &gt;0 and trans_count&gt;=trans_size the  'trans_done' bits in SCK_STATUS is both set.  If SCK_STATUS.susp_trans=1 the socket is also suspended and the 'suspend' bit set. This count is updated only when a descriptor is completed and the socket proceeds to the next one.
51558Exception: When socket suspends with PARTIAL_BUF=1, this value has been (incorrectly) incremented by 1 (UNIT=1) or DSCR_SIZE.BYTE_COUNT (UNIT=0).  Firmware must correct this before resuming the socket.</description>
51559                  <bitRange>[31:0]</bitRange>
51560                  <access>read-write</access>
51561                </field>
51562              </fields>
51563            </register>
51564            <register>
51565              <name>SCK_STATUS</name>
51566              <description>Socket Status Register</description>
51567              <addressOffset>0xC</addressOffset>
51568              <size>32</size>
51569              <access>read-write</access>
51570              <resetValue>0x4E00000</resetValue>
51571              <resetMask>0xFFFF87FF</resetMask>
51572              <fields>
51573                <field>
51574                  <name>AVL_COUNT</name>
51575                  <description>Number of available (free for ingress, occupied for egress) descriptors beyond the current one.  This number is incremented by the adapter whenever an event is received on this socket and decremented whenever it activates a new descriptor. This value is used to create a signal to the IP Cores that indicates at least one buffer is available beyond the current one (sck_more_buf_avl).</description>
51576                  <bitRange>[4:0]</bitRange>
51577                  <access>read-write</access>
51578                </field>
51579                <field>
51580                  <name>AVL_MIN</name>
51581                  <description>Minimum number of available buffers required by the adapter before activating a new one.  This can be used to guarantee a minimum number of buffers available with old data to implement rollback.  If AVL_ENABLE, the socket will remain in STALL state until AVL_COUNT&gt;=AVL_MIN.</description>
51582                  <bitRange>[9:5]</bitRange>
51583                  <access>read-write</access>
51584                </field>
51585                <field>
51586                  <name>AVL_ENABLE</name>
51587                  <description>Enables the functioning of AVL_COUNT and AVL_MIN. When 0, it will disable both stalling on AVL_MIN and generation of the sck_more_buf_avl signal described above.</description>
51588                  <bitRange>[10:10]</bitRange>
51589                  <access>read-write</access>
51590                </field>
51591                <field>
51592                  <name>STATE</name>
51593                  <description>Internal operating state of the socket.  This field is used for debugging and to safely modify active sockets (see go_suspend).</description>
51594                  <bitRange>[17:15]</bitRange>
51595                  <access>read-only</access>
51596                  <enumeratedValues>
51597                    <enumeratedValue>
51598                      <name>DESCR</name>
51599                      <description>Descriptor state. This is the default initial state indicating the descriptor registers are NOT valid in the Adapter. The Adapter will start loading the descriptor from memory if the socket becomes enabled and not suspended. Suspend has no effect on any other state.</description>
51600                      <value>0</value>
51601                    </enumeratedValue>
51602                    <enumeratedValue>
51603                      <name>STALL</name>
51604                      <description>Stall state. Socket is stalled waiting for data to be loaded into the Fetch Queue or waiting for an event.</description>
51605                      <value>1</value>
51606                    </enumeratedValue>
51607                    <enumeratedValue>
51608                      <name>ACTIVE</name>
51609                      <description>Active state. Socket is available for core data transfers.</description>
51610                      <value>2</value>
51611                    </enumeratedValue>
51612                    <enumeratedValue>
51613                      <name>EVENT</name>
51614                      <description>Event state. Core transfer is done. Descriptor is being written back to memory and an event is being generated if enabled.</description>
51615                      <value>3</value>
51616                    </enumeratedValue>
51617                    <enumeratedValue>
51618                      <name>CHECK1</name>
51619                      <description>Check states. An active socket gets here based on the core's EOP request to check the Transfer size and determine whether the buffer should be wrapped up. Depending on result, socket will either go back to Active state or move to the Event state.</description>
51620                      <value>4</value>
51621                    </enumeratedValue>
51622                    <enumeratedValue>
51623                      <name>SUSPENDED</name>
51624                      <description>Socket is suspended</description>
51625                      <value>5</value>
51626                    </enumeratedValue>
51627                    <enumeratedValue>
51628                      <name>CHECK2</name>
51629                      <description>Check states. An active socket gets here based on the core's EOP request to check the Transfer size and determine whether the buffer should be wrapped up. Depending on result, socket will either go back to Active state or move to the Event state.</description>
51630                      <value>6</value>
51631                    </enumeratedValue>
51632                    <enumeratedValue>
51633                      <name>WAITING</name>
51634                      <description>Waiting for confirmation that event was sent.</description>
51635                      <value>7</value>
51636                    </enumeratedValue>
51637                  </enumeratedValues>
51638                </field>
51639                <field>
51640                  <name>ZLP_RCVD</name>
51641                  <description>Indicates the socket received a ZLP</description>
51642                  <bitRange>[18:18]</bitRange>
51643                  <access>read-only</access>
51644                </field>
51645                <field>
51646                  <name>SUSPENDED</name>
51647                  <description>Indicates the socket is currently in suspend state.  In suspend mode there is no active descriptor; any previously active descriptor has been wrapped up, copied back to memory and SCK_DSCR.dscr_number has been updated using DSCR_CHAIN as needed.  If the next descriptor is known (SCK_DSCR.dscr_number!=0xFFFF), this descriptor will be loaded after the socket resumes from suspend state.
51648A socket can only be resumed by changing go_suspend from 1 to 0.  If the socket is suspended while go_suspend=0, it must first be set and then again cleared.</description>
51649                  <bitRange>[19:19]</bitRange>
51650                  <access>read-only</access>
51651                </field>
51652                <field>
51653                  <name>ENABLED</name>
51654                  <description>Indicates the socket is currently enabled when asserted.  After go_enable is changed, it may take some time for enabled to make the same change.  This value can be polled to determine this fact.</description>
51655                  <bitRange>[20:20]</bitRange>
51656                  <access>read-only</access>
51657                </field>
51658                <field>
51659                  <name>TRUNCATE</name>
51660                  <description>Enable (1) or disable (0) truncating of BYTE_COUNT when TRANS_COUNT+BYTE_COUNT&gt;=TRANS_SIZE.  When enabled, ensures that an ingress transfer never contains more bytes then allowed.  This function is needed to implement burst-based prototocols that can only transmit full bursts of more than 1 byte.</description>
51661                  <bitRange>[21:21]</bitRange>
51662                  <access>read-write</access>
51663                </field>
51664                <field>
51665                  <name>EN_PROD_EVENTS</name>
51666                  <description>Enable (1) or disable (0) sending of produce events from any descriptor in this socket.  If 0, events will be suppressed, and the descriptor will not be copied back into memory when completed.</description>
51667                  <bitRange>[22:22]</bitRange>
51668                  <access>read-write</access>
51669                </field>
51670                <field>
51671                  <name>EN_CONS_EVENTS</name>
51672                  <description>Enable (1) or disable (0) sending of consume events from any descriptor in this socket.  If 0, events will be suppressed, and the descriptor will not be copied back into memory when completed.</description>
51673                  <bitRange>[23:23]</bitRange>
51674                  <access>read-write</access>
51675                </field>
51676                <field>
51677                  <name>SUSP_PARTIAL</name>
51678                  <description>When set, the socket will suspend before activating a descriptor with BYTE_COUNT&lt;BUFFER_SIZE.
51679This is relevant for egress sockets only.</description>
51680                  <bitRange>[24:24]</bitRange>
51681                  <access>read-write</access>
51682                </field>
51683                <field>
51684                  <name>SUSP_LAST</name>
51685                  <description>When set, the socket will suspend before activating a descriptor with TRANS_COUNT+BUFFER_SIZE&gt;=TRANS_SIZE.  This is relevant for both ingress and egress sockets.</description>
51686                  <bitRange>[25:25]</bitRange>
51687                  <access>read-write</access>
51688                </field>
51689                <field>
51690                  <name>SUSP_TRANS</name>
51691                  <description>When set, the socket will suspend when trans_count &gt;= trans_size.  This equation is checked (and hence the socket will suspend) only at the boundary of buffers and packets (ie. buffer wrapup or EOP assertion).</description>
51692                  <bitRange>[26:26]</bitRange>
51693                  <access>read-write</access>
51694                </field>
51695                <field>
51696                  <name>SUSP_EOP</name>
51697                  <description>When set, the socket will suspend after wrapping up the first buffer with dscr.eop=1.  Note that this function will work the same for both ingress and egress sockets.</description>
51698                  <bitRange>[27:27]</bitRange>
51699                  <access>read-write</access>
51700                </field>
51701                <field>
51702                  <name>WRAPUP</name>
51703                  <description>Setting this bit will forcibly wrap-up a socket, whether it is out of data or not.  This option is intended mainly for ingress sockets, but works also for egress sockets.  Any remaining data in fetch buffers is ignored, in write buffers is flushed.  Transaction and buffer counts are updated normally, and suspend behavior also happens normally (depending on various other settings in this register).G45</description>
51704                  <bitRange>[28:28]</bitRange>
51705                  <access>read-write</access>
51706                </field>
51707                <field>
51708                  <name>UNIT</name>
51709                  <description>Indicates whether descriptors (1) or bytes (0) are counted by trans_count and trans_size.  Descriptors are counting regardless of whether they contain any data or have eop set.</description>
51710                  <bitRange>[29:29]</bitRange>
51711                  <access>read-write</access>
51712                </field>
51713                <field>
51714                  <name>GO_SUSPEND</name>
51715                  <description>Directs a socket to go into suspend mode when the current descriptor completes.  The main use of this bit is to safely append descriptors to an active socket without actually suspending it (in most cases). The process is outlined in more detail in the architecture spec, and looks as follows:
517161: GO_SUSPEND=1
517172: modify the chain in memory
517183: check if active descriptor is 0xFFFF or last in chain
517194: if so, make corrections as neccessary (complicated)
517205: clear any pending suspend interrupts (SCK_INTR[9:5])
517216: GO_SUSPEND=0
51722Note that the socket resumes only when SCK_INTR[9:5]=0 and GO_SUSPEND=0.</description>
51723                  <bitRange>[30:30]</bitRange>
51724                  <access>read-write</access>
51725                </field>
51726                <field>
51727                  <name>GO_ENABLE</name>
51728                  <description>Indicates whether socket is enabled.  When go_enable is cleared while socket is active, ongoing transfers are aborted after an unspecified amount of time.  No update occurs from the descriptor registers back into memory.  When go_enable is changed from 0 to 1, the socket will reload the active descriptor from memory regardless of the contents of DSCR_ registers. The socket will not wait for an EVENT to become active if the descriptor is available and ready for transfer (has space or data).
51729The 'enabled' bit indicates whether the socket is actually enabled or not.  This field lags go_enable by an short but unspecificied of time.</description>
51730                  <bitRange>[31:31]</bitRange>
51731                  <access>read-write</access>
51732                </field>
51733              </fields>
51734            </register>
51735            <register>
51736              <name>SCK_INTR</name>
51737              <description>Socket Interrupt Request Register</description>
51738              <addressOffset>0x10</addressOffset>
51739              <size>32</size>
51740              <access>read-write</access>
51741              <resetValue>0x0</resetValue>
51742              <resetMask>0x3FF</resetMask>
51743              <fields>
51744                <field>
51745                  <name>PRODUCE_EVENT</name>
51746                  <description>Indicates that a produce event has been received or transmitted since last cleared.</description>
51747                  <bitRange>[0:0]</bitRange>
51748                  <access>read-write</access>
51749                </field>
51750                <field>
51751                  <name>CONSUME_EVENT</name>
51752                  <description>Indicates that a consume event has been received or transmitted since last cleared.</description>
51753                  <bitRange>[1:1]</bitRange>
51754                  <access>read-write</access>
51755                </field>
51756                <field>
51757                  <name>DSCR_IS_LOW</name>
51758                  <description>Indicates that dscr_count has fallen below its watermark dscr_low.  If dscr_count wraps around to 255 dscr_is_low will remain asserted until cleared by s/w</description>
51759                  <bitRange>[2:2]</bitRange>
51760                  <access>read-write</access>
51761                </field>
51762                <field>
51763                  <name>DSCR_NOT_AVL</name>
51764                  <description>Indicates the no descriptor is available.  Not available means that the current descriptor number is 0xFFFF.  Note that this bit will remain asserted until cleared by s/w, regardless of whether a new descriptor number is loaded.</description>
51765                  <bitRange>[3:3]</bitRange>
51766                  <access>read-write</access>
51767                </field>
51768                <field>
51769                  <name>STALL</name>
51770                  <description>Indicates the socket has stalled, waiting for an event signaling its descriptor has become available. Note that this bit will remain asserted until cleared by s/w, regardless of whether the socket resumes.</description>
51771                  <bitRange>[4:4]</bitRange>
51772                  <access>read-write</access>
51773                </field>
51774                <field>
51775                  <name>SUSPEND</name>
51776                  <description>Indicates the socket has gone into suspend mode.  This may be caused by any hardware initiated condition (e.g. DSCR_NOT_AVL, any of the SUSP_*) or by setting GO_SUSPEND=1.  Note that this bit will remain asserted until cleared by s/w, regardless of whether the suspend condition is resolved.
51777Note that the socket resumes only when SCK_INTR[9:5]=0 and GO_SUSPEND=0.</description>
51778                  <bitRange>[5:5]</bitRange>
51779                  <access>read-write</access>
51780                </field>
51781                <field>
51782                  <name>ERROR</name>
51783                  <description>Indicates the socket is suspended because of an error condition (internal to the adapter) - if error=1 then suspend=1 as well.  Possible error causes are:
51784- dscr_size.buffer_error bit already set in the descriptor.
51785- dscr_size.byte_count &gt; dscr_size.buffer_size
51786- core writes into an inactive socket.
51787- core did not consume all the data in the buffer.
51788Note that the socket resumes only when SCK_INTR[9:5]=0 and GO_SUSPEND=0.</description>
51789                  <bitRange>[6:6]</bitRange>
51790                  <access>read-write</access>
51791                </field>
51792                <field>
51793                  <name>TRANS_DONE</name>
51794                  <description>Indicates that TRANS_COUNT has reached the limit TRANS_SIZE.  This flag is only set when SUSP_TRANS=1.  Note that because TRANS_COUNT is updated only at the granularity of entire buffers, it is possible that TRANS_COUNT exceeds TRANS_SIZE before the socket suspends.  Software must detect and deal with these situations.  When asserting EOP to the adapter on ingress, the trans_count is not updated unless the socket actually suspends (see SUSP_TRANS).
51795Note that the socket resumes only when SCK_INTR[9:5]=0 and GO_SUSPEND=0.</description>
51796                  <bitRange>[7:7]</bitRange>
51797                  <access>read-write</access>
51798                </field>
51799                <field>
51800                  <name>PARTIAL_BUF</name>
51801                  <description>Indicates that the (egress) socket was suspended because of SUSP_PARTIAL condition.  Note that the socket resumes only when SCK_INTR[9:5]=0 and GO_SUSPEND=0.</description>
51802                  <bitRange>[8:8]</bitRange>
51803                  <access>read-write</access>
51804                </field>
51805                <field>
51806                  <name>LAST_BUF</name>
51807                  <description>Indicates that the socket was suspended because of SUSP_LAST condition.  Note that the socket resumes only when SCK_INTR[9:5]=0 and GO_SUSPEND=0.</description>
51808                  <bitRange>[9:9]</bitRange>
51809                  <access>read-write</access>
51810                </field>
51811              </fields>
51812            </register>
51813            <register>
51814              <name>SCK_INTR_MASK</name>
51815              <description>Socket Interrupt Mask Register</description>
51816              <addressOffset>0x14</addressOffset>
51817              <size>32</size>
51818              <access>read-write</access>
51819              <resetValue>0x0</resetValue>
51820              <resetMask>0x3FF</resetMask>
51821              <fields>
51822                <field>
51823                  <name>PRODUCE_EVENT</name>
51824                  <description>1: Report interrupt to CPU</description>
51825                  <bitRange>[0:0]</bitRange>
51826                  <access>read-write</access>
51827                </field>
51828                <field>
51829                  <name>CONSUME_EVENT</name>
51830                  <description>1: Report interrupt to CPU</description>
51831                  <bitRange>[1:1]</bitRange>
51832                  <access>read-write</access>
51833                </field>
51834                <field>
51835                  <name>DSCR_IS_LOW</name>
51836                  <description>1: Report interrupt to CPU</description>
51837                  <bitRange>[2:2]</bitRange>
51838                  <access>read-write</access>
51839                </field>
51840                <field>
51841                  <name>DSCR_NOT_AVL</name>
51842                  <description>1: Report interrupt to CPU</description>
51843                  <bitRange>[3:3]</bitRange>
51844                  <access>read-write</access>
51845                </field>
51846                <field>
51847                  <name>STALL</name>
51848                  <description>1: Report interrupt to CPU</description>
51849                  <bitRange>[4:4]</bitRange>
51850                  <access>read-write</access>
51851                </field>
51852                <field>
51853                  <name>SUSPEND</name>
51854                  <description>1: Report interrupt to CPU</description>
51855                  <bitRange>[5:5]</bitRange>
51856                  <access>read-write</access>
51857                </field>
51858                <field>
51859                  <name>ERROR</name>
51860                  <description>1: Report interrupt to CPU</description>
51861                  <bitRange>[6:6]</bitRange>
51862                  <access>read-write</access>
51863                </field>
51864                <field>
51865                  <name>TRANS_DONE</name>
51866                  <description>1: Report interrupt to CPU</description>
51867                  <bitRange>[7:7]</bitRange>
51868                  <access>read-write</access>
51869                </field>
51870                <field>
51871                  <name>PARTIAL_BUF</name>
51872                  <description>1: Report interrupt to CPU</description>
51873                  <bitRange>[8:8]</bitRange>
51874                  <access>read-write</access>
51875                </field>
51876                <field>
51877                  <name>LAST_BUF</name>
51878                  <description>1: Report interrupt to CPU</description>
51879                  <bitRange>[9:9]</bitRange>
51880                  <access>read-write</access>
51881                </field>
51882              </fields>
51883            </register>
51884            <register>
51885              <name>DSCR_BUFFER</name>
51886              <description>Descriptor buffer base address register</description>
51887              <addressOffset>0x20</addressOffset>
51888              <size>32</size>
51889              <access>read-write</access>
51890              <resetValue>0x0</resetValue>
51891              <resetMask>0x0</resetMask>
51892              <fields>
51893                <field>
51894                  <name>BUFFER_ADDR</name>
51895                  <description>The base address of the buffer where data is written.  This address is not necessarily word-aligned to allow for header/trailer/length modification.</description>
51896                  <bitRange>[31:0]</bitRange>
51897                  <access>read-write</access>
51898                </field>
51899              </fields>
51900            </register>
51901            <register>
51902              <name>DSCR_SYNC</name>
51903              <description>Descriptor synchronization pointers register</description>
51904              <addressOffset>0x24</addressOffset>
51905              <size>32</size>
51906              <access>read-write</access>
51907              <resetValue>0x0</resetValue>
51908              <resetMask>0x0</resetMask>
51909              <fields>
51910                <field>
51911                  <name>CONS_SCK</name>
51912                  <description>The socket number of the consuming socket to which the produce event shall be sent.
51913If cons_ip and cons_sck matches the socket's IP and socket number then the matching socket becomes consuming socket.</description>
51914                  <bitRange>[7:0]</bitRange>
51915                  <access>read-write</access>
51916                </field>
51917                <field>
51918                  <name>CONS_IP</name>
51919                  <description>The IP number of the consuming socket to which the produce event shall be sent.  Use 0x3F to designate ARM CPU (so software) as consumer; the event will be lost in this case and an interrupt should also be generated to observe this condition.</description>
51920                  <bitRange>[13:8]</bitRange>
51921                  <access>read-write</access>
51922                </field>
51923                <field>
51924                  <name>EN_CONS_EVENT</name>
51925                  <description>Enable sending of a consume events from this descriptor only.  Events are sent only if SCK_STATUS.en_consume_ev=1.  When events are disabled, the adapter also does not update the descriptor in memory to clear its occupied bit.</description>
51926                  <bitRange>[14:14]</bitRange>
51927                  <access>read-write</access>
51928                </field>
51929                <field>
51930                  <name>EN_CONS_INT</name>
51931                  <description>Enable generation of a consume event interrupt for this descriptor only.  This interrupt will only be seen by the CPU if SCK_STATUS.int_mask has this interrupt enabled as well.  Note that this flag influences the logging of the interrupt in SCK_STATUS; it has no effect on the reporting of the interrupt to the CPU like SCK_STATUS.int_mask does.</description>
51932                  <bitRange>[15:15]</bitRange>
51933                  <access>read-write</access>
51934                </field>
51935                <field>
51936                  <name>PROD_SCK</name>
51937                  <description>The socket number of the producing socket to which the consume event shall be sent. If prod_ip and prod_sck matches the socket's IP and socket number then the matching socket becomes consuming socket.</description>
51938                  <bitRange>[23:16]</bitRange>
51939                  <access>read-write</access>
51940                </field>
51941                <field>
51942                  <name>PROD_IP</name>
51943                  <description>The IP number of the producing socket to which the consume event shall be sent. Use 0x3F to designate ARM CPU (so software) as producer; the event will be lost in this case and an interrupt should also be generated to observe this condition.</description>
51944                  <bitRange>[29:24]</bitRange>
51945                  <access>read-write</access>
51946                </field>
51947                <field>
51948                  <name>EN_PROD_EVENT</name>
51949                  <description>Enable sending of a produce events from this descriptor only.  Events are sent only if SCK_STATUS.en_produce_ev=1.  If 0, events will be suppressed, and the descriptor will not be copied back into memory when completed.</description>
51950                  <bitRange>[30:30]</bitRange>
51951                  <access>read-write</access>
51952                </field>
51953                <field>
51954                  <name>EN_PROD_INT</name>
51955                  <description>Enable generation of a produce event interrupt for this descriptor only. This interrupt will only be seen by the CPU if SCK_STATUS. int_mask has this interrupt enabled as well.  Note that this flag influences the logging of the interrupt in SCK_STATUS; it has no effect on the reporting of the interrupt to the CPU like SCK_STATUS.int_mask does.</description>
51956                  <bitRange>[31:31]</bitRange>
51957                  <access>read-write</access>
51958                </field>
51959              </fields>
51960            </register>
51961            <register>
51962              <name>DSCR_CHAIN</name>
51963              <description>Descriptor Chain Pointers Register</description>
51964              <addressOffset>0x28</addressOffset>
51965              <size>32</size>
51966              <access>read-write</access>
51967              <resetValue>0x0</resetValue>
51968              <resetMask>0x0</resetMask>
51969              <fields>
51970                <field>
51971                  <name>RD_NEXT_DSCR</name>
51972                  <description>Descriptor number of the next task for consumer. A value of 0xFFFF signals end of this list.</description>
51973                  <bitRange>[15:0]</bitRange>
51974                  <access>read-write</access>
51975                </field>
51976                <field>
51977                  <name>WR_NEXT_DSCR</name>
51978                  <description>Descriptor number of the next task for producer. A value of 0xFFFF signals end of this list.</description>
51979                  <bitRange>[31:16]</bitRange>
51980                  <access>read-write</access>
51981                </field>
51982              </fields>
51983            </register>
51984            <register>
51985              <name>DSCR_SIZE</name>
51986              <description>Descriptor Size Register</description>
51987              <addressOffset>0x2C</addressOffset>
51988              <size>32</size>
51989              <access>read-write</access>
51990              <resetValue>0x0</resetValue>
51991              <resetMask>0x0</resetMask>
51992              <fields>
51993                <field>
51994                  <name>MARKER</name>
51995                  <description>A marker that is provided by s/w and can be observed by the IP.  It's meaning is defined by the IP that uses it.  This bit has no effect on the other DMA mechanisms.</description>
51996                  <bitRange>[0:0]</bitRange>
51997                  <access>read-write</access>
51998                </field>
51999                <field>
52000                  <name>EOP</name>
52001                  <description>A marker indicating this descriptor refers to the last buffer of a packet or transfer. Packets/transfers may span more than one buffer.  The producing IP provides this marker by providing the EOP signal to its DMA adapter.  The consuming IP observes this marker by inspecting its EOP return signal from its own DMA adapter. For more information see section on packets, buffers and transfers in DMA chapter.</description>
52002                  <bitRange>[1:1]</bitRange>
52003                  <access>read-write</access>
52004                </field>
52005                <field>
52006                  <name>BUFFER_ERROR</name>
52007                  <description>Indicates the buffer data is valid (0) or in error (1).</description>
52008                  <bitRange>[2:2]</bitRange>
52009                  <access>read-write</access>
52010                </field>
52011                <field>
52012                  <name>BUFFER_OCCUPIED</name>
52013                  <description>Indicates the buffer is in use (1) or empty (0).  A consumer will interpret this as:
520140: Buffer is empty, wait until filled.
520151: Buffer has data that can be consumed
52016A produce will interpret this as:
520170: Buffer is ready to be filled
520181: Buffer is occupied, wait until empty</description>
52019                  <bitRange>[3:3]</bitRange>
52020                  <access>read-write</access>
52021                </field>
52022                <field>
52023                  <name>BUFFER_SIZE</name>
52024                  <description>The size of the buffer in multiples of 16 bytes</description>
52025                  <bitRange>[15:4]</bitRange>
52026                  <access>read-write</access>
52027                </field>
52028                <field>
52029                  <name>BYTE_COUNT</name>
52030                  <description>The number of data bytes present in the buffer.  An occupied buffer is not always full, in particular when variable length packets are transferred.</description>
52031                  <bitRange>[31:16]</bitRange>
52032                  <access>read-write</access>
52033                </field>
52034              </fields>
52035            </register>
52036            <register>
52037              <name>EVENT</name>
52038              <description>Event Communication Register</description>
52039              <addressOffset>0x7C</addressOffset>
52040              <size>32</size>
52041              <access>write-only</access>
52042              <resetValue>0x0</resetValue>
52043              <resetMask>0x1FFFF</resetMask>
52044              <fields>
52045                <field>
52046                  <name>ACTIVE_DSCR</name>
52047                  <description>The active descriptor number for which the event is sent.</description>
52048                  <bitRange>[15:0]</bitRange>
52049                  <access>write-only</access>
52050                </field>
52051                <field>
52052                  <name>EVENT_TYPE</name>
52053                  <description>Type of event
520540: Consume event descriptor is marked empty - BUFFER_OCCUPIED=0)
520551: Produce event descriptor is marked full = BUFFER_OCCUPIED=1)</description>
52056                  <bitRange>[16:16]</bitRange>
52057                  <access>write-only</access>
52058                </field>
52059              </fields>
52060            </register>
52061          </cluster>
52062          <cluster>
52063            <name>SCK_GBL</name>
52064            <description>DMA Adapter Global Registers</description>
52065            <addressOffset>0x0000FF00</addressOffset>
52066            <register>
52067              <name>SCK_INTR</name>
52068              <description>Socket Interrupt Request Register</description>
52069              <addressOffset>0x0</addressOffset>
52070              <size>32</size>
52071              <access>read-only</access>
52072              <resetValue>0x0</resetValue>
52073              <resetMask>0xFFFFFFFF</resetMask>
52074              <fields>
52075                <field>
52076                  <name>SCKINTR</name>
52077                  <description>Socket &lt;x&gt; asserts interrupt when bit &lt;x&gt; is set in this vector.  Multiple bits may be set to 1 simultaneously.
52078This register is only as wide as the number of socket in the adapter; 256 is just the maximum width.  All other bits always return 0.</description>
52079                  <bitRange>[31:0]</bitRange>
52080                  <access>read-only</access>
52081                </field>
52082              </fields>
52083            </register>
52084            <register>
52085              <name>ADAPTER_DEBUG</name>
52086              <description>Adapter Debug Observation Register</description>
52087              <addressOffset>0xF4</addressOffset>
52088              <size>32</size>
52089              <access>read-only</access>
52090              <resetValue>0x0</resetValue>
52091              <resetMask>0xFFFFFFFF</resetMask>
52092              <fields>
52093                <field>
52094                  <name>TS_COUNT</name>
52095                  <description>Internal adapter state for debug observation</description>
52096                  <bitRange>[3:0]</bitRange>
52097                  <access>read-only</access>
52098                </field>
52099                <field>
52100                  <name>TS_STATE</name>
52101                  <description>Internal adapter state for debug observation</description>
52102                  <bitRange>[6:4]</bitRange>
52103                  <access>read-only</access>
52104                </field>
52105                <field>
52106                  <name>TS_ID</name>
52107                  <description>Internal adapter state for debug observation</description>
52108                  <bitRange>[12:7]</bitRange>
52109                  <access>read-only</access>
52110                </field>
52111                <field>
52112                  <name>SS_COUNT</name>
52113                  <description>Internal adapter state for debug observation</description>
52114                  <bitRange>[21:13]</bitRange>
52115                  <access>read-only</access>
52116                </field>
52117                <field>
52118                  <name>SS_STATE</name>
52119                  <description>Internal adapter state for debug observation</description>
52120                  <bitRange>[22:22]</bitRange>
52121                  <access>read-only</access>
52122                </field>
52123                <field>
52124                  <name>SS_ID</name>
52125                  <description>Internal adapter state for debug observation</description>
52126                  <bitRange>[28:23]</bitRange>
52127                  <access>read-only</access>
52128                </field>
52129                <field>
52130                  <name>TS_ABORT</name>
52131                  <description>Internal adapter state for debug observation</description>
52132                  <bitRange>[29:29]</bitRange>
52133                  <access>read-only</access>
52134                </field>
52135                <field>
52136                  <name>BS_STATE</name>
52137                  <description>Internal adapter state for debug observation</description>
52138                  <bitRange>[31:30]</bitRange>
52139                  <access>read-only</access>
52140                </field>
52141              </fields>
52142            </register>
52143            <register>
52144              <name>ADAPTER_CONF</name>
52145              <description>Adapter Configuration Register</description>
52146              <addressOffset>0xF8</addressOffset>
52147              <size>32</size>
52148              <access>read-write</access>
52149              <resetValue>0x0</resetValue>
52150              <resetMask>0x7FFFFFFF</resetMask>
52151              <fields>
52152                <field>
52153                  <name>FQ_THRESHOLD</name>
52154                  <description>Number of words in a socket fetch queue (FQ) that must be present before sck_active asserts.  Default value is FQ_SIZE, which means the entire FQ must fill up before sck_active asserts.</description>
52155                  <bitRange>[5:0]</bitRange>
52156                  <access>read-write</access>
52157                </field>
52158                <field>
52159                  <name>STREAM_COUNT</name>
52160                  <description>Number of burst requests to issue without examining the FQ depth (because IP Core can guarantee immediate consumption).</description>
52161                  <bitRange>[14:6]</bitRange>
52162                  <access>read-write</access>
52163                </field>
52164                <field>
52165                  <name>STREAMING_MODE</name>
52166                  <description>0: Do not make fetch requests unless fetch queue has space to hold response (default).
521671: Assume IP Core will drain all data as it comes in.  Place fetch requests on bus as fast as possible (DO NOT USE UNLESS YOU KNOW WHAT YOU ARE DOING).</description>
52168                  <bitRange>[15:15]</bitRange>
52169                  <access>read-write</access>
52170                </field>
52171                <field>
52172                  <name>TS_CYCLES</name>
52173                  <description>Minimum cycles between prefetch requests to the bus.  The adapter will wait for this number of cycles in between prefetch burst requests when activating a descriptor on a socket.  If TS_CYCLES=0, the requests will be sent back-to-back (assuming queues are not full).</description>
52174                  <bitRange>[19:16]</bitRange>
52175                  <access>read-write</access>
52176                </field>
52177                <field>
52178                  <name>ES_CYCLES</name>
52179                  <description>Minimum cycles between fetch requests to the bus under normal operation.  The adapter will wait for this number of cycles in between burst requests when refilling a fetch queue for a desriptor  If ES_CYCLES=0, the requests may be sent back-to-back (assuming queues are not full).</description>
52180                  <bitRange>[23:20]</bitRange>
52181                  <access>read-write</access>
52182                </field>
52183                <field>
52184                  <name>GBL_CYCLES</name>
52185                  <description>Minimum cycles between any fetch requests to the bus.  The adapter will wait for this number of cycles in between any fetch or prefetch burst requests when activating a descriptor on a socket.  If GBL_CYCLES=0, the requests may be sent back-to-back (assuming queues are not full).</description>
52186                  <bitRange>[27:24]</bitRange>
52187                  <access>read-write</access>
52188                </field>
52189                <field>
52190                  <name>MMIO_LOW_PRIORITY</name>
52191                  <description>Sets priority between MMIO and Core requests:
521920: fair arbitration. MMIO is guaranteed to win the next cycle if there was a collision with the core request in the first cycle.
521931: low priority. MMIO will never win if the core has a request.</description>
52194                  <bitRange>[28:28]</bitRange>
52195                  <access>read-write</access>
52196                </field>
52197                <field>
52198                  <name>SWITCH_HIGH_PRIORITY</name>
52199                  <description>Socket swicth higher priority than interconnect</description>
52200                  <bitRange>[29:29]</bitRange>
52201                  <access>read-write</access>
52202                </field>
52203                <field>
52204                  <name>TS_ABORT_EN</name>
52205                  <description>Allow TS to be aborted</description>
52206                  <bitRange>[30:30]</bitRange>
52207                  <access>read-write</access>
52208                </field>
52209              </fields>
52210            </register>
52211            <register>
52212              <name>ADAPTER_STATUS</name>
52213              <description>Adapter Global Status Fields</description>
52214              <addressOffset>0xFC</addressOffset>
52215              <size>32</size>
52216              <access>read-only</access>
52217              <resetValue>0x0</resetValue>
52218              <resetMask>0xFFFFFF</resetMask>
52219              <fields>
52220                <field>
52221                  <name>TTL_SOCKETS</name>
52222                  <description>Total number of sockets in this adapter.  This number is different for each instance of the adapter and varies with the core IP needs.</description>
52223                  <bitRange>[7:0]</bitRange>
52224                  <access>read-only</access>
52225                </field>
52226                <field>
52227                  <name>IG_ONLY</name>
52228                  <description>First socket number that is ingress only.
522290..IG_ONLY-1:   Sockets capable of both in and egress
52230IG_ONLY..TTL_SOCKETS-1:  Ingress sockets only</description>
52231                  <bitRange>[15:8]</bitRange>
52232                  <access>read-only</access>
52233                </field>
52234                <field>
52235                  <name>FQ_SIZE</name>
52236                  <description>Number of words in a socket fetch queue (FQ).  The total buffer space in the adapter is EG_SOCKETS*FQ_SIZE words of size WORD_SIZE.</description>
52237                  <bitRange>[21:16]</bitRange>
52238                  <access>read-only</access>
52239                </field>
52240                <field>
52241                  <name>WORD_SIZE</name>
52242                  <description>Internal word size of the prefetch queue (FQ); not the same as bus width of AHB bus or thread interface to the IP.
522430: 32b
522441: 64b
522452: 128b
522463: 256b</description>
52247                  <bitRange>[23:22]</bitRange>
52248                  <access>read-only</access>
52249                </field>
52250              </fields>
52251            </register>
52252          </cluster>
52253        </cluster>
52254      </registers>
52255    </peripheral>
52256    <peripheral>
52257      <name>SCB0</name>
52258      <description>Serial Communications Block (SPI/UART/I2C)</description>
52259      <headerStructName>SCB</headerStructName>
52260      <baseAddress>0x40500000</baseAddress>
52261      <addressBlock>
52262        <offset>0</offset>
52263        <size>65536</size>
52264        <usage>registers</usage>
52265      </addressBlock>
52266      <registers>
52267        <register>
52268          <name>CTRL</name>
52269          <description>Generic control</description>
52270          <addressOffset>0x0</addressOffset>
52271          <size>32</size>
52272          <access>read-write</access>
52273          <resetValue>0x300000F</resetValue>
52274          <resetMask>0x83031F0F</resetMask>
52275          <fields>
52276            <field>
52277              <name>OVS</name>
52278              <description>N/A</description>
52279              <bitRange>[3:0]</bitRange>
52280              <access>read-write</access>
52281            </field>
52282            <field>
52283              <name>EC_AM_MODE</name>
52284              <description>Internally clocked mode ('0') or externally clocked mode ('1') address matching (I2C) or selection (SPI). In internally clocked mode, the serial interface protocols run off the peripheral clock. In externally clocked mode, the serial interface protocols run off the clock as provided by the serial interface. Externally clocked mode is only used for synchronous serial interface protocols (SPI and I2C) in slave mode. In SPI mode, only Motorola submode (all Motorola modes: 0, 1, 2, 3) is supported.
52285
52286In UART mode this field should be '0'.</description>
52287              <bitRange>[8:8]</bitRange>
52288              <access>read-write</access>
52289            </field>
52290            <field>
52291              <name>EC_OP_MODE</name>
52292              <description>Internally clocked mode ('0') or externally clocked mode ('1') operation. In internally clocked mode, the serial interface protocols run off the peripheral clock. In externally clocked mode, the serial interface protocols run off the clock as provided by the serial interface. Externally clocked operation mode is only used for synchronous serial interface protocols (SPI and I2C) in slave mode AND EZ mode. In SPI mode, only Motorola submode (all Motorola modes: 0, 1, 2, 3) is supported. The maximum SPI slave, EZ mode bitrate is 48 Mbps (transmission and IO delays outside the IP will degrade the effective bitrate).
52293
52294In UART mode this field should be '0'.</description>
52295              <bitRange>[9:9]</bitRange>
52296              <access>read-write</access>
52297            </field>
52298            <field>
52299              <name>EZ_MODE</name>
52300              <description>Non EZ mode ('0') or EZ mode ('1'). In EZ mode, a meta protocol is applied to the serial interface protocol. This meta protocol adds meaning to the data frames transferred by the serial interface protocol: a data frame can represent a memory address, a write memory data element or a read memory data element. EZ mode is only used for synchronous serial interface protocols: SPI and I2C. In SPI mode, only Motorola submode (all Motorola modes: 0, 1, 2, 3) is supported and the transmitter should use continuous data frames; i.e. data frames mot separated by slave deselection. This mode is only applicable to slave functionality. In EZ mode, the slave can read from and write to an addressable memory structure of up to 256 bytes. In EZ mode, data frames should 8-bit in size and should be transmitted and received with the Most Significant Bit (MSB) first.
52301
52302In UART mode this field should be '0'.</description>
52303              <bitRange>[10:10]</bitRange>
52304              <access>read-write</access>
52305            </field>
52306            <field>
52307              <name>BYTE_MODE</name>
52308              <description>Determines the number of bits per FIFO data element:
52309'0': 16-bit FIFO data elements.
52310'1': 8-bit FIFO data elements. This mode doubles the amount of FIFO entries, but  TX_CTRL.DATA_WIDTH and RX_CTRL.DATA_WIDTH are restricted to [0, 7].</description>
52311              <bitRange>[11:11]</bitRange>
52312              <access>read-write</access>
52313            </field>
52314            <field>
52315              <name>CMD_RESP_MODE</name>
52316              <description>Determines CMD_RESP mode of operation:
52317'0': CMD_RESP mode disabled.
52318'1': CMD_RESP mode enabled (also requires EC_AM_MODE and EC_OP_MODE to be set to '1').</description>
52319              <bitRange>[12:12]</bitRange>
52320              <access>read-write</access>
52321            </field>
52322            <field>
52323              <name>ADDR_ACCEPT</name>
52324              <description>Determines whether a received matching address is accepted in the RX FIFO ('1') or not ('0').
52325
52326In I2C mode, this field is used to allow the slave to put the received slave address or general call address in the RX FIFO. Note that a received matching address is put in the RX FIFO when ADDR_ACCEPT is '1' for both I2C read and write transfers.
52327
52328In multi-processor UART receiver mode, this field is used to allow the receiver to put the received address in the RX FIFO. Note: non-matching addresses are never put in the RX FIFO.</description>
52329              <bitRange>[16:16]</bitRange>
52330              <access>read-write</access>
52331            </field>
52332            <field>
52333              <name>BLOCK</name>
52334              <description>Only used in externally clocked mode. If the externally clocked logic and the MMIO SW accesses to EZ memory coincide/collide, this bit determines whether a SW access should block and result in bus wait states ('BLOCK is 1') or not (BLOCK is '0'). IF BLOCK is '0' and the accesses collide, MMIO read operations return 0xffff:ffff and MMIO write operations are ignored. Colliding accesses are registered as interrupt causes: field BLOCKED of MMIO registers INTR_TX and INTR_RX.</description>
52335              <bitRange>[17:17]</bitRange>
52336              <access>read-write</access>
52337            </field>
52338            <field>
52339              <name>MODE</name>
52340              <description>N/A</description>
52341              <bitRange>[25:24]</bitRange>
52342              <access>read-write</access>
52343              <enumeratedValues>
52344                <enumeratedValue>
52345                  <name>I2C</name>
52346                  <description>Inter-Integrated Circuits (I2C) mode.</description>
52347                  <value>0</value>
52348                </enumeratedValue>
52349                <enumeratedValue>
52350                  <name>SPI</name>
52351                  <description>Serial Peripheral Interface (SPI) mode.</description>
52352                  <value>1</value>
52353                </enumeratedValue>
52354                <enumeratedValue>
52355                  <name>UART</name>
52356                  <description>Universal Asynchronous Receiver/Transmitter (UART) mode.</description>
52357                  <value>2</value>
52358                </enumeratedValue>
52359              </enumeratedValues>
52360            </field>
52361            <field>
52362              <name>ENABLED</name>
52363              <description>IP enabled ('1') or not ('0'). The proper order in which to initialize the IP is as follows:
52364- Program protocol specific information using SPI_CTRL, UART_CTRL (and UART_TX_CTRL and UART_RX_CTRL) or I2C_CTRL. This includes selection of a submode, master/slave functionality and transmitter/receiver functionality when applicable.
52365- Program generic transmitter (TX_CTRL) and receiver (RX_CTRL) information. This includes enabling of the transmitter and receiver functionality.
52366- Program transmitter FIFO (TX_FIFO_CTRL) and receiver FIFO (RX_FIFO_CTRL) information.
52367- Program CTRL to enable IP, select the specific operation mode and oversampling factor.
52368When the IP is enabled, no control information should be changed. Changes should be made AFTER disabling the IP, e.g. to modify the operation mode (from I2C to SPI) or to go from externally to internally clocked. The change takes effect after the IP is re-enabled. Note that disabling the IP will cause re-initialization of the design and associated state is lost (e.g. FIFO content).</description>
52369              <bitRange>[31:31]</bitRange>
52370              <access>read-write</access>
52371            </field>
52372          </fields>
52373        </register>
52374        <register>
52375          <name>STATUS</name>
52376          <description>Generic status</description>
52377          <addressOffset>0x4</addressOffset>
52378          <size>32</size>
52379          <access>read-only</access>
52380          <resetValue>0x0</resetValue>
52381          <resetMask>0x0</resetMask>
52382          <fields>
52383            <field>
52384              <name>EC_BUSY</name>
52385              <description>Indicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ mode). This bit can be used by SW to determine whether it is safe to issue a SW access to the EZ memory (without bus wait states (a blocked SW access) or bus errors being generated). Note that the INTR_TX.BLOCKED and INTR_RX.BLOCKED interrupt causes are used to indicate whether a SW access was actually blocked by externally clocked logic.</description>
52386              <bitRange>[0:0]</bitRange>
52387              <access>read-only</access>
52388            </field>
52389          </fields>
52390        </register>
52391        <register>
52392          <name>CMD_RESP_CTRL</name>
52393          <description>Command/response control</description>
52394          <addressOffset>0x8</addressOffset>
52395          <size>32</size>
52396          <access>read-write</access>
52397          <resetValue>0x0</resetValue>
52398          <resetMask>0x1FF01FF</resetMask>
52399          <fields>
52400            <field>
52401              <name>BASE_RD_ADDR</name>
52402              <description>I2C/SPI read base address for CMD_RESP mode. Address is used by a I2C CMD_RESP mode read transfer (CTRL.MODE is I2C) or a SPI CMD_RESP mode read transfer (CTRL.MODE is SPI): at the start of a read transfer BASE_RD_ADDR is copied to CMD_RESP_STATUS.CURR_RD_ADDR. This field should not be modified during ongoing bus transfers.</description>
52403              <bitRange>[8:0]</bitRange>
52404              <access>read-write</access>
52405            </field>
52406            <field>
52407              <name>BASE_WR_ADDR</name>
52408              <description>I2C/SPI write base address for CMD_RESP mode. Address is used by a I2C CMD_RESP mode write transfer (CTRL.MODE is I2C) or a SPI CMD_RESP mode write transfer (CTRL.MODE is SPI): at the start of a write transfer BASE_WE_ADDR is copied to CMD_RESP_STATUS.CURR_WR_ADDR. This field should not be modified during ongoing bus transfers.</description>
52409              <bitRange>[24:16]</bitRange>
52410              <access>read-write</access>
52411            </field>
52412          </fields>
52413        </register>
52414        <register>
52415          <name>CMD_RESP_STATUS</name>
52416          <description>Command/response status</description>
52417          <addressOffset>0xC</addressOffset>
52418          <size>32</size>
52419          <access>read-only</access>
52420          <resetValue>0x0</resetValue>
52421          <resetMask>0x0</resetMask>
52422          <fields>
52423            <field>
52424              <name>CURR_RD_ADDR</name>
52425              <description>I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However, when the last memory buffer address is reached, the address is NOT incremented (but remains at the maximum memory buffer address).
52426
52427The field is used to determine how many bytes have been read (# bytes = CURR_RD_ADDR - CMD_RESP_CTRL.BASE_RD_ADDR).
52428
52429This field is reliable during when there is no bus transfer. This field is potentially unreliable when there is a bus transfer bus transfer: when CMD_RESP_EC_BUSY is '0', the field is reliable.</description>
52430              <bitRange>[8:0]</bitRange>
52431              <access>read-only</access>
52432            </field>
52433            <field>
52434              <name>CURR_WR_ADDR</name>
52435              <description>I2C/SPI write current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However, when the last memory buffer address is reached, the address is NOT incremented (but remains at the maximum memory buffer address).
52436
52437The field is used to determine how many bytes have been written (# bytes = CURR_WR_ADDR - CMD_RESP_CTRL.BASE_WR_ADDR).
52438
52439This field is reliable during when there is no bus transfer. This field is potentially unreliable when there is a bus transfer bus transfer: when CMD_RESP_EC_BUSY is '0', the field is reliable.</description>
52440              <bitRange>[24:16]</bitRange>
52441              <access>read-only</access>
52442            </field>
52443            <field>
52444              <name>CMD_RESP_EC_BUS_BUSY</name>
52445              <description>Indicates whether there is an ongoing bus transfer to the IP.
52446'0': no ongoing bus transfer.
52447'1': ongoing bus transfer.
52448
52449For SPI, the field is '1' when the slave is selected.
52450
52451For I2C, the field is set to '1' at a I2C START/RESTART. In case of an address match, the  field is set to '0' on a I2C STOP. In case of NO address match, the field is set to '0' after the failing address match.</description>
52452              <bitRange>[30:30]</bitRange>
52453              <access>read-only</access>
52454            </field>
52455            <field>
52456              <name>CMD_RESP_EC_BUSY</name>
52457              <description>Indicates whether the CURR_RD_ADDR and CURR_WR_ADDR fields in this register are reliable (when CMD_RESP_EC_BUSY is '0') or not reliable (when CMD_RESP_EC_BUSY is '1'). Note:
52458- When there is no ongoing bus transfer, CMD_RESP_EC_BUSY is '0' (reliable).
52459- When there is a ongoing bus transfer, CMD_RESP_EC_BUSY is '0' (reliable), when the CURR_RD_ADDR and CURR_WR_ADDR are not being updated by the HW.
52460- When there is a ongoing bus transfer, CMD_RESP_EC_BUSY is '1' (not reliable), when the CURR_RD_ADDR or CURR_WR_ADDR are being updated by the HW.
52461   Note that this update lasts one I2C clock cycle, or two SPI clock cycles.</description>
52462              <bitRange>[31:31]</bitRange>
52463              <access>read-only</access>
52464            </field>
52465          </fields>
52466        </register>
52467        <register>
52468          <name>SPI_CTRL</name>
52469          <description>SPI control</description>
52470          <addressOffset>0x20</addressOffset>
52471          <size>32</size>
52472          <access>read-write</access>
52473          <resetValue>0x3000000</resetValue>
52474          <resetMask>0x8F010F3F</resetMask>
52475          <fields>
52476            <field>
52477              <name>SSEL_CONTINUOUS</name>
52478              <description>Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode, both continuous and non-continuous SPI data transfers are supported independent of this field.
52479
52480When continuous transfers are enabled individual data frame transfers are not necessarily separated by slave deselection (as indicated by the level or pulse on the SELECT line): if the TX FIFO has multiple data frames, data frames are send out without slave deselection.
52481
52482When continuous transfers are not enabled individual data frame transfers are always separated by slave deselection: independent of the availability of TX FIFO data frames.</description>
52483              <bitRange>[0:0]</bitRange>
52484              <access>read-write</access>
52485            </field>
52486            <field>
52487              <name>SELECT_PRECEDE</name>
52488              <description>Only used in SPI Texas Instruments' submode.
52489
52490When '1', the data frame start indication is a pulse on the SELECT line that precedes the transfer of the first data frame bit.
52491
52492When '0', the data frame start indication is a pulse on the SELECT line that coincides with the transfer of the first data frame bit.</description>
52493              <bitRange>[1:1]</bitRange>
52494              <access>read-write</access>
52495            </field>
52496            <field>
52497              <name>CPHA</name>
52498              <description>Indicates the clock phase. This field, together with the CPOL field, indicates when MOSI data is driven and MISO data is captured:
52499- Motorola mode 0. CPOL is '0', CPHA is '0': MOSI  is driven on a falling edge of SCLK. MISO is captured on a rising edge of SCLK.
52500- Motorola mode 1. CPOL is '0', CPHA is '1': MOSI  is driven on a rising edge of SCLK. MISO is captured on a falling edge of SCLK.
52501- Motorola mode 2. CPOL is '1', CPHA is '0': MOSI  is driven on a rising edge of SCLK. MISO is captured on a falling edge of SCLK.
52502- Motorola mode 3. CPOL is '1', CPHA is '1': MOSI  is driven on a falling edge of SCLK. MISO is captured on a rising edge of SCLK.
52503
52504In SPI Motorola submode, all four CPOL/CPHA modes are valid.
52505in SPI NS submode, only CPOL=0 CPHA=0 mode is valid.
52506in SPI TI submode, only CPOL=0 CPHA=1 mode is valid.</description>
52507              <bitRange>[2:2]</bitRange>
52508              <access>read-write</access>
52509            </field>
52510            <field>
52511              <name>CPOL</name>
52512              <description>Indicates the clock polarity. This field, together with the CPHA field, indicates when MOSI data is driven and MISO data is captured:
52513- CPOL is '0': SCLK is '0' when not transmitting data.
52514- CPOL is '1': SCLK is '1' when not transmitting data.</description>
52515              <bitRange>[3:3]</bitRange>
52516              <access>read-write</access>
52517            </field>
52518            <field>
52519              <name>LATE_MISO_SAMPLE</name>
52520              <description>Changes the SCLK edge on which MISO is captured. Only used in master mode.
52521
52522When '0', the default applies (for Motorola as determined by CPOL and CPHA, for Texas Instruments on the falling edge of SCLK and for National Semiconductors on the rising edge of SCLK).
52523
52524When '1', the alternate clock edge is used (which comes half a SPI SCLK period later). Late sampling addresses the round trip delay associated with transmitting SCLK from the master to the slave and transmitting MISO from the slave to the master.</description>
52525              <bitRange>[4:4]</bitRange>
52526              <access>read-write</access>
52527            </field>
52528            <field>
52529              <name>SCLK_CONTINUOUS</name>
52530              <description>Only applicable in master mode.
52531'0': SCLK is generated, when the SPI master is enabled and data is transmitted.
52532'1': SCLK is generated, when the SPI master is enabled. This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality.</description>
52533              <bitRange>[5:5]</bitRange>
52534              <access>read-write</access>
52535            </field>
52536            <field>
52537              <name>SSEL_POLARITY0</name>
52538              <description>Slave select polarity. SSEL_POLARITY0 applies to the outgoing SPI slave select signal 0 (master mode) and to the incoming SPI slave select signal (slave mode). For Motorola and National Semiconductors submodes:
52539'0': slave select is low/'0' active.
52540'1': slave select is high/'1' active.
52541For Texas Instruments submode:
52542'0': high/'1' active precede/coincide pulse.
52543'1': low/'0' active precede/coincide pulse.</description>
52544              <bitRange>[8:8]</bitRange>
52545              <access>read-write</access>
52546            </field>
52547            <field>
52548              <name>SSEL_POLARITY1</name>
52549              <description>Slave select polarity.</description>
52550              <bitRange>[9:9]</bitRange>
52551              <access>read-write</access>
52552            </field>
52553            <field>
52554              <name>SSEL_POLARITY2</name>
52555              <description>Slave select polarity.</description>
52556              <bitRange>[10:10]</bitRange>
52557              <access>read-write</access>
52558            </field>
52559            <field>
52560              <name>SSEL_POLARITY3</name>
52561              <description>Slave select polarity.</description>
52562              <bitRange>[11:11]</bitRange>
52563              <access>read-write</access>
52564            </field>
52565            <field>
52566              <name>LOOPBACK</name>
52567              <description>Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode.
52568'0': the SPI master MISO line 'spi_miso_in' is connected to the SPI MISO pin.
52569'1': the SPI master MISO line 'spi_miso_in' is connected to the SPI master MOSI line 'spi_mosi_out'. In other words, in loopback mode the SPI master receives on MISO what it transmits on MOSI.</description>
52570              <bitRange>[16:16]</bitRange>
52571              <access>read-write</access>
52572            </field>
52573            <field>
52574              <name>MODE</name>
52575              <description>N/A</description>
52576              <bitRange>[25:24]</bitRange>
52577              <access>read-write</access>
52578              <enumeratedValues>
52579                <enumeratedValue>
52580                  <name>SPI_MOTOROLA</name>
52581                  <description>SPI Motorola submode. In master mode, when not transmitting data (SELECT is inactive), SCLK is stable at CPOL. In slave mode, when not selected, SCLK is ignored; i.e. it can be either stable or clocking. In master mode, when there is no data to transmit (TX FIFO is empty), SELECT is inactive.</description>
52582                  <value>0</value>
52583                </enumeratedValue>
52584                <enumeratedValue>
52585                  <name>SPI_TI</name>
52586                  <description>SPI Texas Instruments submode. In master mode, when not transmitting data, SCLK is stable at '0'. In slave mode, when not selected, SCLK is ignored; i.e. it can be either stable or clocking. In master mode, when there is no data to transmit (TX FIFO is empty), SELECT is inactive; i.e. no pulse is generated.</description>
52587                  <value>1</value>
52588                </enumeratedValue>
52589                <enumeratedValue>
52590                  <name>SPI_NS</name>
52591                  <description>SPI National Semiconductors submode. In master mode, when not transmitting data, SCLK is stable at '0'. In slave mode, when not selected, SCLK is ignored; i.e. it can be either stable or clocking. In master mode, when there is no data to transmit (TX FIFO is empty), SELECT is inactive.</description>
52592                  <value>2</value>
52593                </enumeratedValue>
52594              </enumeratedValues>
52595            </field>
52596            <field>
52597              <name>SSEL</name>
52598              <description>Selects one of the four incoming/outgoing SPI slave select signals:
52599- 0: Slave 0, SSEL[0].
52600- 1: Slave 1, SSEL[1].
52601- 2: Slave 2, SSEL[2].
52602- 3: Slave 3, SSEL[3].
52603The IP should be disabled when changes are made to this field.</description>
52604              <bitRange>[27:26]</bitRange>
52605              <access>read-write</access>
52606            </field>
52607            <field>
52608              <name>MASTER_MODE</name>
52609              <description>Master ('1') or slave ('0') mode. In master mode, transmission will commence on availability of data frames in the TX FIFO. In slave mode, when selected and there is no data frame in the TX FIFO, the slave will transmit all '1's. In both master and slave modes, received data frames will be lost if the RX FIFO is full.</description>
52610              <bitRange>[31:31]</bitRange>
52611              <access>read-write</access>
52612            </field>
52613          </fields>
52614        </register>
52615        <register>
52616          <name>SPI_STATUS</name>
52617          <description>SPI status</description>
52618          <addressOffset>0x24</addressOffset>
52619          <size>32</size>
52620          <access>read-only</access>
52621          <resetValue>0x0</resetValue>
52622          <resetMask>0x0</resetMask>
52623          <fields>
52624            <field>
52625              <name>BUS_BUSY</name>
52626              <description>SPI bus is busy. The bus is considered busy ('1') during an ongoing transaction. For Motorola and National submodes, the busy bit is '1', when the slave selection is activated. For TI submode, the busy bit is '1' from the time the preceding/coinciding slave select is activated for the first transmitted data frame, till the last MOSI/MISO bit of the last data frame is transmitted.</description>
52627              <bitRange>[0:0]</bitRange>
52628              <access>read-only</access>
52629            </field>
52630            <field>
52631              <name>SPI_EC_BUSY</name>
52632              <description>Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_ADDR and CURR_ADDR are reliable.</description>
52633              <bitRange>[1:1]</bitRange>
52634              <access>read-only</access>
52635            </field>
52636            <field>
52637              <name>CURR_EZ_ADDR</name>
52638              <description>SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1'), as clock domain synchronization is not performed in the design.</description>
52639              <bitRange>[15:8]</bitRange>
52640              <access>read-only</access>
52641            </field>
52642            <field>
52643              <name>BASE_EZ_ADDR</name>
52644              <description>SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable, as clock domain synchronization is not performed in the design.</description>
52645              <bitRange>[23:16]</bitRange>
52646              <access>read-only</access>
52647            </field>
52648          </fields>
52649        </register>
52650        <register>
52651          <name>UART_CTRL</name>
52652          <description>UART control</description>
52653          <addressOffset>0x40</addressOffset>
52654          <size>32</size>
52655          <access>read-write</access>
52656          <resetValue>0x3000000</resetValue>
52657          <resetMask>0x3010000</resetMask>
52658          <fields>
52659            <field>
52660              <name>LOOPBACK</name>
52661              <description>Local loopback control (does NOT affect the information on the pins). When '0', the transmitter TX line 'uart_tx_out' is connected to the TX pin and the receiver RX line 'uart_rx_in' is connected to the RX pin. When '1', the transmitter TX line 'uart_tx_out' is connected to the receiver RX line 'uart_rx_in'. A similar connections scheme is followed for 'uart_rts_out' and 'uart_cts_in'.
52662
52663This allows a SCB UART transmitter to communicate with its receiver counterpart.</description>
52664              <bitRange>[16:16]</bitRange>
52665              <access>read-write</access>
52666            </field>
52667            <field>
52668              <name>MODE</name>
52669              <description>N/A</description>
52670              <bitRange>[25:24]</bitRange>
52671              <access>read-write</access>
52672              <enumeratedValues>
52673                <enumeratedValue>
52674                  <name>UART_STD</name>
52675                  <description>Standard UART submode.</description>
52676                  <value>0</value>
52677                </enumeratedValue>
52678                <enumeratedValue>
52679                  <name>UART_SMARTCARD</name>
52680                  <description>SmartCard (ISO7816) submode. Support for negative acknowledgement (NACK) on the receiver side and retransmission on the transmitter side.</description>
52681                  <value>1</value>
52682                </enumeratedValue>
52683                <enumeratedValue>
52684                  <name>UART_IRDA</name>
52685                  <description>Infrared Data Association (IrDA) submode. Return to Zero modulation scheme.</description>
52686                  <value>2</value>
52687                </enumeratedValue>
52688              </enumeratedValues>
52689            </field>
52690          </fields>
52691        </register>
52692        <register>
52693          <name>UART_TX_CTRL</name>
52694          <description>UART transmitter control</description>
52695          <addressOffset>0x44</addressOffset>
52696          <size>32</size>
52697          <access>read-write</access>
52698          <resetValue>0x2</resetValue>
52699          <resetMask>0x137</resetMask>
52700          <fields>
52701            <field>
52702              <name>STOP_BITS</name>
52703              <description>Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1, 7]; i.e. a stop period should last at least one bit period.</description>
52704              <bitRange>[2:0]</bitRange>
52705              <access>read-write</access>
52706            </field>
52707            <field>
52708              <name>PARITY</name>
52709              <description>Parity bit. When '0', the transmitter generates an even parity. When '1', the transmitter generates an odd parity. Only applicable in standard UART and SmartCard submodes.</description>
52710              <bitRange>[4:4]</bitRange>
52711              <access>read-write</access>
52712            </field>
52713            <field>
52714              <name>PARITY_ENABLED</name>
52715              <description>Parity generation enabled ('1') or not ('0'). Only applicable in standard UART submodes. In SmartCard submode, parity generation is always enabled through hardware. In IrDA submode, parity generation is always disabled through hardware</description>
52716              <bitRange>[5:5]</bitRange>
52717              <access>read-write</access>
52718            </field>
52719            <field>
52720              <name>RETRY_ON_NACK</name>
52721              <description>When '1', a data frame is retransmitted when a negative acknowledgement is received. Only applicable to the SmartCard submode.</description>
52722              <bitRange>[8:8]</bitRange>
52723              <access>read-write</access>
52724            </field>
52725          </fields>
52726        </register>
52727        <register>
52728          <name>UART_RX_CTRL</name>
52729          <description>UART receiver control</description>
52730          <addressOffset>0x48</addressOffset>
52731          <size>32</size>
52732          <access>read-write</access>
52733          <resetValue>0xA0002</resetValue>
52734          <resetMask>0xF3777</resetMask>
52735          <fields>
52736            <field>
52737              <name>STOP_BITS</name>
52738              <description>Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1, 7]; i.e. a stop period should last at least one bit period.
52739
52740Note that in case of a stop bits error, the successive data frames may get lost as the receiver needs to resynchronize its start bit detection. The amount of lost data frames depends on both the amount of stop bits, the idle ('1') time between data frames and the data frame value.</description>
52741              <bitRange>[2:0]</bitRange>
52742              <access>read-write</access>
52743            </field>
52744            <field>
52745              <name>PARITY</name>
52746              <description>Parity bit. When '0', the receiver expects an even parity. When '1', the receiver expects an odd parity. Only applicable in standard UART and SmartCard submodes.</description>
52747              <bitRange>[4:4]</bitRange>
52748              <access>read-write</access>
52749            </field>
52750            <field>
52751              <name>PARITY_ENABLED</name>
52752              <description>Parity checking enabled ('1') or not ('0'). Only applicable in standard UART submode. In SmartCard submode, parity checking is always enabled through hardware. In IrDA submode, parity checking is always disabled through hardware.</description>
52753              <bitRange>[5:5]</bitRange>
52754              <access>read-write</access>
52755            </field>
52756            <field>
52757              <name>POLARITY</name>
52758              <description>Inverts incoming RX line signal 'uart_rx_in'. Inversion is after local loopback. This functionality is intended for IrDA receiver functionality.</description>
52759              <bitRange>[6:6]</bitRange>
52760              <access>read-write</access>
52761            </field>
52762            <field>
52763              <name>DROP_ON_PARITY_ERROR</name>
52764              <description>Behavior when a parity check fails. When '0', received data is send to the RX FIFO. When '1', received data is dropped and lost. Only applicable in standard UART and SmartCard submodes (negatively acknowledged SmartCard data frames may be dropped with this field).</description>
52765              <bitRange>[8:8]</bitRange>
52766              <access>read-write</access>
52767            </field>
52768            <field>
52769              <name>DROP_ON_FRAME_ERROR</name>
52770              <description>Behavior when an error is detected in a start or stop period. When '0', received data is send to the RX FIFO. When '1', received data is dropped and lost.</description>
52771              <bitRange>[9:9]</bitRange>
52772              <access>read-write</access>
52773            </field>
52774            <field>
52775              <name>MP_MODE</name>
52776              <description>Multi-processor mode. When '1', multi-processor mode is enabled. In this mode, RX_CTRL.DATA_WIDTH should indicate a 9-bit data frame. In multi-processor mode, the 9th received bit of a data frame separates addresses (bit is '1') from data (bit is '0'). A received address is matched with RX_MATCH.DATA and RX_MATCH.MASK. In the case of a match, subsequent received data are sent to the RX FIFO. In the case of NO match, subsequent received data are dropped.</description>
52777              <bitRange>[10:10]</bitRange>
52778              <access>read-write</access>
52779            </field>
52780            <field>
52781              <name>LIN_MODE</name>
52782              <description>Only applicable in standard UART submode. When '1', the receiver performs break detection and baud rate detection on the incoming data. First, break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies the minimum required amount of bit periods. Successful break detection sets the INTR_RX.BREAK_DETECT interrupt cause to '1'. Second, baud rate detection counts the amount of peripheral clock periods that are use to receive the synchronization byte (0x55; least significant bit first). The count is available through UART_RX_STATUS.BR_COUNTER. Successful baud rate detection sets the INTR_RX.BAUD_DETECT interrupt cause to '1' (BR_COUNTER is reliable). This functionality is used to synchronize/refine the receiver clock to the transmitter clock. The receiver software can use the BR_COUNTER value to set the right IP clock (from the programmable clock IP) to guarantee successful receipt of the first LIN data frame (Protected Identifier Field) after the synchronization byte.</description>
52783              <bitRange>[12:12]</bitRange>
52784              <access>read-write</access>
52785            </field>
52786            <field>
52787              <name>SKIP_START</name>
52788              <description>Only applicable in standard UART submode. When '1', the receiver skips start bit detection for the first received data frame. Instead, it synchronizes on the first received data frame bit, which should be a '1'. This functionality is intended for wake up from DeepSleep when receiving a data frame. The transition from idle ('1') to START ('0') on the RX line is used to wake up the CPU. The transition detection (and the associated wake up functionality) is performed by the GPIO2 IP. The woken up CPU will enable the SCB's UART receiver functionality. Once enabled, it is assumed that the START bit is ongoing (the CPU wakeup and SCB enable time should be less than the START bit period). The SCB will synchronize to a '0' to '1' transition, which indicates the first data frame bit is received (first data frame bit should be '1'). After synchronization to the first data frame bit, the SCB will resume normal UART functionality: subsequent data frames will be synchronized on the receipt of a START bit.</description>
52789              <bitRange>[13:13]</bitRange>
52790              <access>read-write</access>
52791            </field>
52792            <field>
52793              <name>BREAK_WIDTH</name>
52794              <description>Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once, the break is detected, the INTR_RX.BREAK_DETECT bit is set to '1'. Note that break detection precedes baud rate detection, which is used to synchronize/refine the receiver clock to the transmitter clock. As a result, break detection operates with an unsynchronized/unrefined receiver clock. Therefore, the receiver's definition of a bit period is imprecise and the setting of this field should take this imprecision into account. The LIN standard also accounts for this imprecision: a LIN start bit followed by 8 data bits allows for up to 9 consecutive '0' bit periods during regular transmission, whereas the LIN break detection should be at least 13 consecutive '0' bit periods. This provides for a margin of 4 bit periods. Therefore, the default value of this field is set to 10, representing a minimal break field with of 10+1 = 11 bit periods; a value in between the 9 consecutive bit periods of a regular transmission and the 13 consecutive bit periods of a break field. This provides for slight imprecisions of the receiver clock wrt. the transmitter clock. There should not be a need to program this field to any value other than its default value.</description>
52795              <bitRange>[19:16]</bitRange>
52796              <access>read-write</access>
52797            </field>
52798          </fields>
52799        </register>
52800        <register>
52801          <name>UART_RX_STATUS</name>
52802          <description>UART receiver status</description>
52803          <addressOffset>0x4C</addressOffset>
52804          <size>32</size>
52805          <access>read-only</access>
52806          <resetValue>0x0</resetValue>
52807          <resetMask>0x0</resetMask>
52808          <fields>
52809            <field>
52810              <name>BR_COUNTER</name>
52811              <description>Amount of peripheral clock periods that constitute the transmission of a 0x55 data frame (sent least significant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of peripheral clock periods that constitute a bit period. This field has valid data when INTR_RX.BAUD_DETECT is set to '1'.</description>
52812              <bitRange>[11:0]</bitRange>
52813              <access>read-only</access>
52814            </field>
52815          </fields>
52816        </register>
52817        <register>
52818          <name>UART_FLOW_CTRL</name>
52819          <description>UART flow control</description>
52820          <addressOffset>0x50</addressOffset>
52821          <size>32</size>
52822          <access>read-write</access>
52823          <resetValue>0x0</resetValue>
52824          <resetMask>0x30100FF</resetMask>
52825          <fields>
52826            <field>
52827              <name>TRIGGER_LEVEL</name>
52828              <description>Trigger level. When the receiver FIFO has less entries than the amount of this field, a Ready To Send (RTS) output signal 'uart_rts_out' is activated. By setting this field to '0', flow control is effectively SW disabled (may be useful for debug purposes).</description>
52829              <bitRange>[7:0]</bitRange>
52830              <access>read-write</access>
52831            </field>
52832            <field>
52833              <name>RTS_POLARITY</name>
52834              <description>Polarity of the RTS output signal 'uart_rts_out':
52835'0': RTS is low/'0' active; 'uart_rts_out' is '0' when active and 'uart_rts_out' is '1' when inactive.
52836'1': RTS is high/'1' active; 'uart_rts_out' is '1' when active and 'uart_rts_out' is '0' when inactive.
52837
52838During IP reset (Hibernate system power mode), 'uart_rts_out' is '1'. This represents an inactive state assuming a low/'0' active polarity.</description>
52839              <bitRange>[16:16]</bitRange>
52840              <access>read-write</access>
52841            </field>
52842            <field>
52843              <name>CTS_POLARITY</name>
52844              <description>Polarity of the CTS input signal 'uart_cts_in':
52845'0': CTS is low/'0' active; 'uart_cts_in' is '0' when active and 'uart_cts_in' is '1' when inactive.
52846'1': CTS is high/'1' active; 'uart_cts_in' is '1' when active and 'uart_cts_in' is '0' when inactive.</description>
52847              <bitRange>[24:24]</bitRange>
52848              <access>read-write</access>
52849            </field>
52850            <field>
52851              <name>CTS_ENABLED</name>
52852              <description>Enable use of CTS input signal 'uart_cts_in' by the UART transmitter:
52853'0': Disabled. The UART transmitter ignores 'uart_cts_in', and transmits when a data frame is available for transmission in the TX FIFO or the TX shift register.
52854'1': Enabled. The UART transmitter uses 'uart_cts_in' to qualify the transmission of data. It transmits when 'uart_cts_in' is active and a data frame is available for transmission in the TX FIFO or the TX shift register.
52855
52856If UART_CTRL.LOOPBACK is '1', 'uart_cts_in' is connected to 'uart_rts_out' in the IP (both signals are subjected to signal polarity changes as indicated by RTS_POLARITY and CTS_POLARITY).</description>
52857              <bitRange>[25:25]</bitRange>
52858              <access>read-write</access>
52859            </field>
52860          </fields>
52861        </register>
52862        <register>
52863          <name>I2C_CTRL</name>
52864          <description>I2C control</description>
52865          <addressOffset>0x60</addressOffset>
52866          <size>32</size>
52867          <access>read-write</access>
52868          <resetValue>0xFB88</resetValue>
52869          <resetMask>0xC001FBFF</resetMask>
52870          <fields>
52871            <field>
52872              <name>HIGH_PHASE_OVS</name>
52873              <description>Serial I2C interface high phase oversampling factor. HIGH_PHASE_OVS + 1 peripheral clock periods constitute the high phase of a bit period. The valid range is [5, 15] with input signal median filtering and [4, 15] without input signal median filtering.
52874
52875The field is only used in master mode. In slave mode, the field is NOT used. However, there is a frequency requirement for the IP clock wrt. the regular interface (IF) high time to guarantee functional correct behavior. With input signal median filtering, the IF high time should be &gt;= 6 IP clock cycles and &lt;= 16 IP clock cycles. Without input signal median filtering, the IF high time should be &gt;= 5 IP clock cycles and &lt;= 16 IP clock cycles.</description>
52876              <bitRange>[3:0]</bitRange>
52877              <access>read-write</access>
52878            </field>
52879            <field>
52880              <name>LOW_PHASE_OVS</name>
52881              <description>Serial I2C interface low phase oversampling factor. LOW_PHASE_OVS + 1 peripheral clock periods constitute the low phase of a bit period. The valid range is [7, 15] with input signal median filtering and [6, 15] without input signal median filtering.
52882
52883The field is only used in master mode. In slave mode, the field is NOT used. However, there is a frequency requirement for the IP clock wrt. the regular (no stretching) interface (IF) low time to guarantee functional correct behavior. With input signal median filtering, the IF low time should be &gt;= 8 IP clock cycles and &lt;= 16 IP clock cycles. Without input signal median filtering, the IF low time should be &gt;= 7 IP clock cycles and &lt;= 16 IP clock cycles.</description>
52884              <bitRange>[7:4]</bitRange>
52885              <access>read-write</access>
52886            </field>
52887            <field>
52888              <name>M_READY_DATA_ACK</name>
52889              <description>When '1', a received data element by the master is immediately ACK'd when the receiver FIFO is not full.</description>
52890              <bitRange>[8:8]</bitRange>
52891              <access>read-write</access>
52892            </field>
52893            <field>
52894              <name>M_NOT_READY_DATA_NACK</name>
52895              <description>When '1', a received data element byte the master is immediately NACK'd when the receiver FIFO is full. When '0', clock stretching is used instead (till the receiver FIFO is no longer full).</description>
52896              <bitRange>[9:9]</bitRange>
52897              <access>read-write</access>
52898            </field>
52899            <field>
52900              <name>S_GENERAL_IGNORE</name>
52901              <description>When '1', a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. This is useful for slaves that do not need any data supplied within the general call structure.</description>
52902              <bitRange>[11:11]</bitRange>
52903              <access>read-write</access>
52904            </field>
52905            <field>
52906              <name>S_READY_ADDR_ACK</name>
52907              <description>When '1', a received (matching) slave address is immediately ACK'd when the receiver FIFO is not full. In EZ mode, this field should be set to '1'.</description>
52908              <bitRange>[12:12]</bitRange>
52909              <access>read-write</access>
52910            </field>
52911            <field>
52912              <name>S_READY_DATA_ACK</name>
52913              <description>When '1', a received data element by the slave is immediately ACK'd when the receiver FIFO is not full. In EZ mode, this field should be set to '1'.</description>
52914              <bitRange>[13:13]</bitRange>
52915              <access>read-write</access>
52916            </field>
52917            <field>
52918              <name>S_NOT_READY_ADDR_NACK</name>
52919              <description>For internally clocked logic (EC_AM is '0' and EC_OP is '0') on an address match or general call address (and S_GENERAL_IGNORE is '0'). Only used when:
52920- EC_AM is '0', EC_OP is '0' and non EZ mode.
52921Functionality is as follows:
52922- 1: a received (matching) slave address is immediately NACK'd when the receiver FIFO is full.
52923- 0: clock stretching is performed (till the receiver FIFO is no longer full).
52924
52925For externally clocked logic (EC_AM is '1') on an address match or general call address (and S_GENERAL_IGNORE is '0'). Only used when (NOT used when EC_AM is '1' and EC_OP is '1' and address match and EZ mode):
52926- EC_AM is '1' and EC_OP is '0'.
52927- EC_AM is '1' and general call address match.
52928- EC_AM is '1' and non EZ mode.
52929Functionality is as follows:
52930- 1: a received (matching or general) slave address is always immediately NACK'd. There are two possibilities: 1). the internally clocked logic is enabled (we are in Active system power mode) and it handles the rest of the current transfer. In this case the I2C master will not observe the NACK. 2). the internally clocked logic is not enabled (we are in DeepSleep system power mode). In this case the I2C master will observe the NACK and may retry the transfer in the future (which gives the internally clocked logic the time to wake up from DeepSleep system power mode).
52931- 0: clock stretching is performed (till the internally clocked logic takes over). The internally clocked logic will handle the ongoing transfer as soon as it is enabled.</description>
52932              <bitRange>[14:14]</bitRange>
52933              <access>read-write</access>
52934            </field>
52935            <field>
52936              <name>S_NOT_READY_DATA_NACK</name>
52937              <description>For internally clocked logic only. Only used when:
52938- non EZ mode.
52939Functionality is as follows:
52940- 1: a received data element byte the slave is immediately NACK'd when the receiver FIFO is full.
52941- 0: clock stretching is performed (till the receiver FIFO is no longer full).</description>
52942              <bitRange>[15:15]</bitRange>
52943              <access>read-write</access>
52944            </field>
52945            <field>
52946              <name>LOOPBACK</name>
52947              <description>Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode. When '0', the I2C SCL and SDA lines are connected to the I2C SCL and SDA pins. When '1', I2C SCL and SDA lines are routed internally in the peripheral, and as a result unaffected by other I2C devices. This allows a SCB I2C peripheral to address itself.</description>
52948              <bitRange>[16:16]</bitRange>
52949              <access>read-write</access>
52950            </field>
52951            <field>
52952              <name>SLAVE_MODE</name>
52953              <description>Slave mode enabled ('1') or not ('0').</description>
52954              <bitRange>[30:30]</bitRange>
52955              <access>read-write</access>
52956            </field>
52957            <field>
52958              <name>MASTER_MODE</name>
52959              <description>Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the IP to address itself.</description>
52960              <bitRange>[31:31]</bitRange>
52961              <access>read-write</access>
52962            </field>
52963          </fields>
52964        </register>
52965        <register>
52966          <name>I2C_STATUS</name>
52967          <description>I2C status</description>
52968          <addressOffset>0x64</addressOffset>
52969          <size>32</size>
52970          <access>read-only</access>
52971          <resetValue>0x0</resetValue>
52972          <resetMask>0x31</resetMask>
52973          <fields>
52974            <field>
52975              <name>BUS_BUSY</name>
52976              <description>I2C bus is busy. The bus is considered busy ('1'), from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0'), from the time a STOP is detected. If the IP is disabled, BUS_BUSY is '0'. After enabling the IP, it takes time for the BUS_BUSY to detect a busy bus. This time is the maximum high time of the SCL line. For a 100 kHz interface frequency, this maximum high time may last roughly 5 us (half a bit period).
52977
52978For single master systems, BUS_BUSY does not have to be used to detect an idle bus before a master starts a transfer using I2C_M_CMD.M_START (no bus collisions).
52979
52980For multi-master systems, BUS_BUSY can be used to detect an idle bus before a master starts a transfer using I2C_M_CMD.M_START_ON_IDLE (to prevent bus collisions).</description>
52981              <bitRange>[0:0]</bitRange>
52982              <access>read-only</access>
52983            </field>
52984            <field>
52985              <name>I2C_EC_BUSY</name>
52986              <description>Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_EZ_ADDR and CURR_EZ_ADDR are reliable.</description>
52987              <bitRange>[1:1]</bitRange>
52988              <access>read-only</access>
52989            </field>
52990            <field>
52991              <name>S_READ</name>
52992              <description>I2C slave read transfer ('1') or I2C slave write transfer ('0'). When the I2C slave is inactive/idle or receiving START, REPEATED START, STOP or an address, this field is '0''.</description>
52993              <bitRange>[4:4]</bitRange>
52994              <access>read-only</access>
52995            </field>
52996            <field>
52997              <name>M_READ</name>
52998              <description>I2C master read transfer ('1') or I2C master write transfer ('0'). When the I2C master is inactive/idle or transmitting START, REPEATED START, STOP or an address, this field is '0''.</description>
52999              <bitRange>[5:5]</bitRange>
53000              <access>read-only</access>
53001            </field>
53002            <field>
53003              <name>CURR_EZ_ADDR</name>
53004              <description>I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1'), as clock domain synchronization is not performed in the design.</description>
53005              <bitRange>[15:8]</bitRange>
53006              <access>read-only</access>
53007            </field>
53008            <field>
53009              <name>BASE_EZ_ADDR</name>
53010              <description>I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable, as clock domain synchronization is not performed in the design.</description>
53011              <bitRange>[23:16]</bitRange>
53012              <access>read-only</access>
53013            </field>
53014          </fields>
53015        </register>
53016        <register>
53017          <name>I2C_M_CMD</name>
53018          <description>I2C master command</description>
53019          <addressOffset>0x68</addressOffset>
53020          <size>32</size>
53021          <access>read-write</access>
53022          <resetValue>0x0</resetValue>
53023          <resetMask>0x1F</resetMask>
53024          <fields>
53025            <field>
53026              <name>M_START</name>
53027              <description>When '1', transmit a START or REPEATED START. Whether a START or REPEATED START is transmitted depends on the state of the master state machine. A START is only transmitted when the master state machine is in the default state. A REPEATED START is transmitted when the master state machine is not in the default state, but is working on an ongoing transaction. The REPEATED START can only be transmitted after a NACK or ACK has been received for a transmitted data element or after a NACK has been transmitted for a received data element. When this action is performed, the hardware sets this field to '0'.</description>
53028              <bitRange>[0:0]</bitRange>
53029              <access>read-write</access>
53030            </field>
53031            <field>
53032              <name>M_START_ON_IDLE</name>
53033              <description>When '1', transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0', note that BUSY has a default value of '0'). For bus idle detection the hardware relies on STOP detection. As a result, bus idle detection is only functional after at least one I2C bus transfer has been detected on the bus (default/reset value of BUSY is '0') . A START is only transmitted when the master state machine is in the default state. When this action is performed, the hardware sets this field to '0'.</description>
53034              <bitRange>[1:1]</bitRange>
53035              <access>read-write</access>
53036            </field>
53037            <field>
53038              <name>M_ACK</name>
53039              <description>When '1', attempt to transmit an acknowledgement (ACK). When this action is performed, the hardware sets this field to '0'.</description>
53040              <bitRange>[2:2]</bitRange>
53041              <access>read-write</access>
53042            </field>
53043            <field>
53044              <name>M_NACK</name>
53045              <description>When '1', attempt to transmit a negative acknowledgement (NACK). When this action is performed, the hardware sets this field to '0'.</description>
53046              <bitRange>[3:3]</bitRange>
53047              <access>read-write</access>
53048            </field>
53049            <field>
53050              <name>M_STOP</name>
53051              <description>When '1', attempt to transmit a STOP. When this action is performed, the hardware sets this field to '0'.
53052 I2C_M_CMD.M_START has a higher priority than this command: in situations where both a STOP and a REPEATED START could be transmitted, M_START takes precedence over M_STOP.</description>
53053              <bitRange>[4:4]</bitRange>
53054              <access>read-write</access>
53055            </field>
53056          </fields>
53057        </register>
53058        <register>
53059          <name>I2C_S_CMD</name>
53060          <description>I2C slave command</description>
53061          <addressOffset>0x6C</addressOffset>
53062          <size>32</size>
53063          <access>read-write</access>
53064          <resetValue>0x0</resetValue>
53065          <resetMask>0x3</resetMask>
53066          <fields>
53067            <field>
53068              <name>S_ACK</name>
53069              <description>When '1', attempt to transmit an acknowledgement (ACK). When this action is performed, the hardware sets this field to '0'. In EZ mode, this field should be set to '0' (it is only to be used in non EZ mode).</description>
53070              <bitRange>[0:0]</bitRange>
53071              <access>read-write</access>
53072            </field>
53073            <field>
53074              <name>S_NACK</name>
53075              <description>When '1', attempt to transmit a negative acknowledgement (NACK). When this action is performed, the hardware sets this field to '0'.  In EZ mode, this field should be set to '0' (it is only to be used in non EZ mode). This command has a higher priority than I2C_S_CMD.S_ACK, I2C_CTRL.S_READY_ADDR_ACK or I2C_CTRL.S_READY_DATA_ACK.</description>
53076              <bitRange>[1:1]</bitRange>
53077              <access>read-write</access>
53078            </field>
53079          </fields>
53080        </register>
53081        <register>
53082          <name>I2C_CFG</name>
53083          <description>I2C configuration</description>
53084          <addressOffset>0x70</addressOffset>
53085          <size>32</size>
53086          <access>read-write</access>
53087          <resetValue>0x2A1013</resetValue>
53088          <resetMask>0x303F1313</resetMask>
53089          <fields>
53090            <field>
53091              <name>SDA_IN_FILT_TRIM</name>
53092              <description>Trim bits for 'i2c_sda_in' 50 ns filter. See s8i2cs BROS (001-59539) for more details on the trim bit values.
53093
53094SDA_IN_FILT_TRIM[1] is used to enable I2CS_EC or SPIS_EC access to internal SRAM memory.
530951: enable clock_scb_en, has no effect on ec_busy_pp
530960: disable clock_scb_en, enable ec_busy_pp (grant I2CS_EC or SPIS_EC access)</description>
53097              <bitRange>[1:0]</bitRange>
53098              <access>read-write</access>
53099            </field>
53100            <field>
53101              <name>SDA_IN_FILT_SEL</name>
53102              <description>Selection of 'i2c_sda_in' filter delay:
53103'0': 0 ns.
53104'1: 50 ns (filter enabled).</description>
53105              <bitRange>[4:4]</bitRange>
53106              <access>read-write</access>
53107            </field>
53108            <field>
53109              <name>SCL_IN_FILT_TRIM</name>
53110              <description>Trim bits for 'i2c_scl_in' 50 ns filter. See s8i2cs BROS (001-59539) for more details on the trim bit values.</description>
53111              <bitRange>[9:8]</bitRange>
53112              <access>read-write</access>
53113            </field>
53114            <field>
53115              <name>SCL_IN_FILT_SEL</name>
53116              <description>Selection of 'i2c_scl_in' filter delay:
53117'0': 0 ns.
53118'1: 50 ns (filter enabled).</description>
53119              <bitRange>[12:12]</bitRange>
53120              <access>read-write</access>
53121            </field>
53122            <field>
53123              <name>SDA_OUT_FILT0_TRIM</name>
53124              <description>Trim bits for 'i2c_sda_out' 50 ns filter 0. See s8i2cs BROS (001-59539) for more details on the trim bit values.</description>
53125              <bitRange>[17:16]</bitRange>
53126              <access>read-write</access>
53127            </field>
53128            <field>
53129              <name>SDA_OUT_FILT1_TRIM</name>
53130              <description>Trim bits for 'i2c_sda_out' 50 ns filter 1. See s8i2cs BROS (001-59539) for more details on the trim bit values.</description>
53131              <bitRange>[19:18]</bitRange>
53132              <access>read-write</access>
53133            </field>
53134            <field>
53135              <name>SDA_OUT_FILT2_TRIM</name>
53136              <description>Trim bits for 'i2c_sda_out' 50 ns filter 2. See s8i2cs BROS (001-59539) for more details on the trim bit values.</description>
53137              <bitRange>[21:20]</bitRange>
53138              <access>read-write</access>
53139            </field>
53140            <field>
53141              <name>SDA_OUT_FILT_SEL</name>
53142              <description>Selection of cumulative 'i2c_sda_out' filter delay:
53143'0': 0 ns.
53144'1': 50 ns (filter 0 enabled).
53145'2': 100 ns (filters 0 and 1 enabled).
53146'3': 150 ns (filters 0, 1 and 2 enabled).</description>
53147              <bitRange>[29:28]</bitRange>
53148              <access>read-write</access>
53149            </field>
53150          </fields>
53151        </register>
53152        <register>
53153          <name>TX_CTRL</name>
53154          <description>Transmitter control</description>
53155          <addressOffset>0x200</addressOffset>
53156          <size>32</size>
53157          <access>read-write</access>
53158          <resetValue>0x107</resetValue>
53159          <resetMask>0x1010F</resetMask>
53160          <fields>
53161            <field>
53162              <name>DATA_WIDTH</name>
53163              <description>Dataframe width. DATA_WIDTH + 1 is the amount of bits in a transmitted data frame. This number does not include start, parity and stop bits. For UART mode, the valid range is [3, 8]. For SPI, the valid range is [3, 15]. For I2C the only valid value is 7.</description>
53164              <bitRange>[3:0]</bitRange>
53165              <access>read-write</access>
53166            </field>
53167            <field>
53168              <name>MSB_FIRST</name>
53169              <description>Least significant bit first ('0') or most significant bit first ('1'). For I2C, this field should be '1'.</description>
53170              <bitRange>[8:8]</bitRange>
53171              <access>read-write</access>
53172            </field>
53173            <field>
53174              <name>OPEN_DRAIN</name>
53175              <description>Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'.
53176'0': Normal operation mode. Typically, this operation mode is used for IO cells that are connected to (board) wires/lines that are driven by a single IO cell. In this operation mode, for an IO cell 'xxx' that is used as an output, the 'xxx_out_en' output enable signal is typically constant '1' the 'xxx_out' output is the outputted value. In other words, in normal operation mode, the 'xxx_out' output is used to control the IO cell output value: 'xxx_out' is '0' to drive an IO cell output value of '0' and 'xxx_out' is '1' to drive an IO cell output value of '1'.
53177'1': Open drain operation mode. Typically this operation mode is used for IO cells that are connected to (board) wires/lines that are driven by multiple IO cells (possibly on multiple chips). In this operation mode, for and IO cell 'xxx' that is used as an output, the 'xxx_out_en' output controls the outputted value. Typically, open drain operation mode drives low/'0' and the 'xxx_out' output is constant '1'. In other words, in open drain operation mode, the 'xxx_out_en' output is used to control the IO cell output value: in drive low/'0' mode: 'xxx_out_en' is '1' (drive enabled) to drive an IO cell output value of '0' and 'xxx_out_en' is '1' (drive disabled) to not drive an IO cell output value (another IO cell can drive the wire/line or a pull up results in a wire/line value '1').
53178
53179The open drain mode is supported for:
53180- I2C mode, 'i2c_scl' and 'i2c_sda' IO cells.
53181- UART mode, 'uart_tx' IO cell.
53182- SPI mode, 'spi_miso' IO cell.</description>
53183              <bitRange>[16:16]</bitRange>
53184              <access>read-write</access>
53185            </field>
53186          </fields>
53187        </register>
53188        <register>
53189          <name>TX_FIFO_CTRL</name>
53190          <description>Transmitter FIFO control</description>
53191          <addressOffset>0x204</addressOffset>
53192          <size>32</size>
53193          <access>read-write</access>
53194          <resetValue>0x0</resetValue>
53195          <resetMask>0x300FF</resetMask>
53196          <fields>
53197            <field>
53198              <name>TRIGGER_LEVEL</name>
53199              <description>Trigger level. When the transmitter FIFO has less entries than the number of this field, a transmitter trigger event INTR_TX.TRIGGER is generated.</description>
53200              <bitRange>[7:0]</bitRange>
53201              <access>read-write</access>
53202            </field>
53203            <field>
53204              <name>CLEAR</name>
53205              <description>When '1', the transmitter FIFO and transmitter shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period.</description>
53206              <bitRange>[16:16]</bitRange>
53207              <access>read-write</access>
53208            </field>
53209            <field>
53210              <name>FREEZE</name>
53211              <description>When '1', hardware reads from the transmitter FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer.</description>
53212              <bitRange>[17:17]</bitRange>
53213              <access>read-write</access>
53214            </field>
53215          </fields>
53216        </register>
53217        <register>
53218          <name>TX_FIFO_STATUS</name>
53219          <description>Transmitter FIFO status</description>
53220          <addressOffset>0x208</addressOffset>
53221          <size>32</size>
53222          <access>read-only</access>
53223          <resetValue>0x0</resetValue>
53224          <resetMask>0xFFFF81FF</resetMask>
53225          <fields>
53226            <field>
53227              <name>USED</name>
53228              <description>Amount of entries in the transmitter FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2).</description>
53229              <bitRange>[8:0]</bitRange>
53230              <access>read-only</access>
53231            </field>
53232            <field>
53233              <name>SR_VALID</name>
53234              <description>Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0'). The shift register can be considered the top of the TX FIFO (the data frame is not included in the USED field of the TX FIFO). The shift register is a working register and holds the data frame that is currently transmitted (when the protocol state machine is transmitting a data frame) or the data frame that is transmitted next (when the protocol state machine is not transmitting a data frame).</description>
53235              <bitRange>[15:15]</bitRange>
53236              <access>read-only</access>
53237            </field>
53238            <field>
53239              <name>RD_PTR</name>
53240              <description>FIFO read pointer: FIFO location from which a data frame is read by the hardware.</description>
53241              <bitRange>[23:16]</bitRange>
53242              <access>read-only</access>
53243            </field>
53244            <field>
53245              <name>WR_PTR</name>
53246              <description>FIFO write pointer: FIFO location at which a new data frame is written.</description>
53247              <bitRange>[31:24]</bitRange>
53248              <access>read-only</access>
53249            </field>
53250          </fields>
53251        </register>
53252        <register>
53253          <name>TX_FIFO_WR</name>
53254          <description>Transmitter FIFO write</description>
53255          <addressOffset>0x240</addressOffset>
53256          <size>32</size>
53257          <access>write-only</access>
53258          <resetValue>0x0</resetValue>
53259          <resetMask>0xFFFF</resetMask>
53260          <fields>
53261            <field>
53262              <name>DATA</name>
53263              <description>Data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH operation. Note that when CTRL.BYTE_MODE is '1', only DATA[7:0] are used.
53264
53265A write to a full TX FIFO sets INTR_TX.OVERFLOW to '1'.</description>
53266              <bitRange>[15:0]</bitRange>
53267              <access>write-only</access>
53268            </field>
53269          </fields>
53270        </register>
53271        <register>
53272          <name>RX_CTRL</name>
53273          <description>Receiver control</description>
53274          <addressOffset>0x300</addressOffset>
53275          <size>32</size>
53276          <access>read-write</access>
53277          <resetValue>0x107</resetValue>
53278          <resetMask>0x30F</resetMask>
53279          <fields>
53280            <field>
53281              <name>DATA_WIDTH</name>
53282              <description>Dataframe width. DATA_WIDTH + 1 is the expected amount of bits in received data frame. This number does not include start, parity and stop bits. For UART mode, the valid range is [3, 8]. For SPI, the valid range is [3, 15]. For I2C the only valid value is 7. In EZ mode (for both SPI and I2C), the only valid value is 7.</description>
53283              <bitRange>[3:0]</bitRange>
53284              <access>read-write</access>
53285            </field>
53286            <field>
53287              <name>MSB_FIRST</name>
53288              <description>Least significant bit first ('0') or most significant bit first ('1'). For I2C, this field should be '1'.</description>
53289              <bitRange>[8:8]</bitRange>
53290              <access>read-write</access>
53291            </field>
53292            <field>
53293              <name>MEDIAN</name>
53294              <description>Median filter. When '1', a digital 3 taps median filter is performed on input interface lines. This filter should reduce the susceptibility to errors. However, its requires higher oversampling values. For UART IrDA submode, this field should always be '1'.</description>
53295              <bitRange>[9:9]</bitRange>
53296              <access>read-write</access>
53297            </field>
53298          </fields>
53299        </register>
53300        <register>
53301          <name>RX_FIFO_CTRL</name>
53302          <description>Receiver FIFO control</description>
53303          <addressOffset>0x304</addressOffset>
53304          <size>32</size>
53305          <access>read-write</access>
53306          <resetValue>0x0</resetValue>
53307          <resetMask>0x300FF</resetMask>
53308          <fields>
53309            <field>
53310              <name>TRIGGER_LEVEL</name>
53311              <description>Trigger level. When the receiver FIFO has more entries than the number of this field, a receiver trigger event INTR_RX.TRIGGER is generated.</description>
53312              <bitRange>[7:0]</bitRange>
53313              <access>read-write</access>
53314            </field>
53315            <field>
53316              <name>CLEAR</name>
53317              <description>When '1', the receiver FIFO and receiver shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period.</description>
53318              <bitRange>[16:16]</bitRange>
53319              <access>read-write</access>
53320            </field>
53321            <field>
53322              <name>FREEZE</name>
53323              <description>When '1', hardware writes to the receiver FIFO have no effect. Freeze will not advance the RX FIFO write pointer.</description>
53324              <bitRange>[17:17]</bitRange>
53325              <access>read-write</access>
53326            </field>
53327          </fields>
53328        </register>
53329        <register>
53330          <name>RX_FIFO_STATUS</name>
53331          <description>Receiver FIFO status</description>
53332          <addressOffset>0x308</addressOffset>
53333          <size>32</size>
53334          <access>read-only</access>
53335          <resetValue>0x0</resetValue>
53336          <resetMask>0xFFFF81FF</resetMask>
53337          <fields>
53338            <field>
53339              <name>USED</name>
53340              <description>Amount of entries in the receiver FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2).</description>
53341              <bitRange>[8:0]</bitRange>
53342              <access>read-only</access>
53343            </field>
53344            <field>
53345              <name>SR_VALID</name>
53346              <description>Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0'). The shift register can be considered the bottom of the RX FIFO (the data frame is not included in the USED field of the RX FIFO). The shift register is a working register and holds the data frame that is currently being received (when the protocol state machine is receiving a data frame).</description>
53347              <bitRange>[15:15]</bitRange>
53348              <access>read-only</access>
53349            </field>
53350            <field>
53351              <name>RD_PTR</name>
53352              <description>FIFO read pointer: FIFO location from which a data frame is read.</description>
53353              <bitRange>[23:16]</bitRange>
53354              <access>read-only</access>
53355            </field>
53356            <field>
53357              <name>WR_PTR</name>
53358              <description>FIFO write pointer: FIFO location at which a new data frame is written by the hardware.</description>
53359              <bitRange>[31:24]</bitRange>
53360              <access>read-only</access>
53361            </field>
53362          </fields>
53363        </register>
53364        <register>
53365          <name>RX_MATCH</name>
53366          <description>Slave address and mask</description>
53367          <addressOffset>0x310</addressOffset>
53368          <size>32</size>
53369          <access>read-write</access>
53370          <resetValue>0x0</resetValue>
53371          <resetMask>0xFF00FF</resetMask>
53372          <fields>
53373            <field>
53374              <name>ADDR</name>
53375              <description>Slave device address.
53376
53377In UART multi-processor mode, all 8 bits are used.
53378
53379In I2C slave mode, only bits 7 down to 1 are used. This reflects the organization of the first transmitted byte in a I2C transfer: the first 7 bits represent the address of the addressed slave, and the last 1 bit is a read/write indicator ('0': write, '1': read).</description>
53380              <bitRange>[7:0]</bitRange>
53381              <access>read-write</access>
53382            </field>
53383            <field>
53384              <name>MASK</name>
53385              <description>Slave device address mask. This field is a mask that specifies which of the ADDR field bits in the ADDR field take part in the matching of the slave address: MATCH = ((ADDR &amp; MASK) == ('slave address' &amp; MASK)).</description>
53386              <bitRange>[23:16]</bitRange>
53387              <access>read-write</access>
53388            </field>
53389          </fields>
53390        </register>
53391        <register>
53392          <name>RX_FIFO_RD</name>
53393          <description>Receiver FIFO read</description>
53394          <addressOffset>0x340</addressOffset>
53395          <size>32</size>
53396          <access>read-only</access>
53397          <resetValue>0x0</resetValue>
53398          <resetMask>0x0</resetMask>
53399          <fields>
53400            <field>
53401              <name>DATA</name>
53402              <description>Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.BYTE_MODE is '1', only DATA[7:0] are used.
53403
53404This register has a side effect when read by software: a data frame is removed from the FIFO. This may be undesirable during debug; i.e. a read during debug should NOT have a side effect. To this end, the IP uses the AHB-Lite 'hmaster[0]' input signal. When this signal is '1' in the address cycle of a bus transfer, a read transfer will not have a side effect. As a result, a read from this register will not remove a data frame from the FIFO. As a result, a read from this register behaves as a read from the SCB_RX_FIFO_RD_SILENT register.
53405
53406A read from an empty RX FIFO sets INTR_RX.UNDERFLOW to '1'.</description>
53407              <bitRange>[15:0]</bitRange>
53408              <access>read-only</access>
53409            </field>
53410          </fields>
53411        </register>
53412        <register>
53413          <name>RX_FIFO_RD_SILENT</name>
53414          <description>Receiver FIFO read silent</description>
53415          <addressOffset>0x344</addressOffset>
53416          <size>32</size>
53417          <access>read-only</access>
53418          <resetValue>0x0</resetValue>
53419          <resetMask>0x0</resetMask>
53420          <fields>
53421            <field>
53422              <name>DATA</name>
53423              <description>Data read from the receiver FIFO. Reading a data frame will NOT remove the data frame from the FIFO; i.e. behavior is similar to that of a PEEK operation. Note that when CTRL.BYTE_MODE is '1', only DATA[7:0] are used.
53424
53425A read from an empty RX FIFO sets INTR_RX.UNDERFLOW to '1'.</description>
53426              <bitRange>[15:0]</bitRange>
53427              <access>read-only</access>
53428            </field>
53429          </fields>
53430        </register>
53431        <register>
53432          <name>INTR_CAUSE</name>
53433          <description>Active clocked interrupt signal</description>
53434          <addressOffset>0xE00</addressOffset>
53435          <size>32</size>
53436          <access>read-only</access>
53437          <resetValue>0x0</resetValue>
53438          <resetMask>0x3F</resetMask>
53439          <fields>
53440            <field>
53441              <name>M</name>
53442              <description>Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0.</description>
53443              <bitRange>[0:0]</bitRange>
53444              <access>read-only</access>
53445            </field>
53446            <field>
53447              <name>S</name>
53448              <description>Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0.</description>
53449              <bitRange>[1:1]</bitRange>
53450              <access>read-only</access>
53451            </field>
53452            <field>
53453              <name>TX</name>
53454              <description>Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0.</description>
53455              <bitRange>[2:2]</bitRange>
53456              <access>read-only</access>
53457            </field>
53458            <field>
53459              <name>RX</name>
53460              <description>Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0.</description>
53461              <bitRange>[3:3]</bitRange>
53462              <access>read-only</access>
53463            </field>
53464            <field>
53465              <name>I2C_EC</name>
53466              <description>Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0.</description>
53467              <bitRange>[4:4]</bitRange>
53468              <access>read-only</access>
53469            </field>
53470            <field>
53471              <name>SPI_EC</name>
53472              <description>Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0.</description>
53473              <bitRange>[5:5]</bitRange>
53474              <access>read-only</access>
53475            </field>
53476          </fields>
53477        </register>
53478        <register>
53479          <name>INTR_I2C_EC</name>
53480          <description>Externally clocked I2C interrupt request</description>
53481          <addressOffset>0xE80</addressOffset>
53482          <size>32</size>
53483          <access>read-write</access>
53484          <resetValue>0x0</resetValue>
53485          <resetMask>0xF</resetMask>
53486          <fields>
53487            <field>
53488              <name>WAKE_UP</name>
53489              <description>Wake up request. Active on incoming slave request (with address match).
53490
53491Only used when EC_AM is '1'.</description>
53492              <bitRange>[0:0]</bitRange>
53493              <access>read-write</access>
53494            </field>
53495            <field>
53496              <name>EZ_STOP</name>
53497              <description>STOP detection. Activated on the end of a every transfer (I2C STOP).
53498
53499Only available for a slave request with an address match, in EZ and CMD_RESP modes, when EC_OP is '1'.</description>
53500              <bitRange>[1:1]</bitRange>
53501              <access>read-write</access>
53502            </field>
53503            <field>
53504              <name>EZ_WRITE_STOP</name>
53505              <description>STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a  transfer that only writes the base address does NOT activate this event.
53506
53507Only available for a slave request with an address match, in EZ and CMD_RESP modes, when EC_OP is '1'.</description>
53508              <bitRange>[2:2]</bitRange>
53509              <access>read-write</access>
53510            </field>
53511            <field>
53512              <name>EZ_READ_STOP</name>
53513              <description>STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from.
53514
53515Only available for a slave request with an address match, in EZ and CMD_RESP modes, when EC_OP is '1'.</description>
53516              <bitRange>[3:3]</bitRange>
53517              <access>read-write</access>
53518            </field>
53519          </fields>
53520        </register>
53521        <register>
53522          <name>INTR_I2C_EC_MASK</name>
53523          <description>Externally clocked I2C interrupt mask</description>
53524          <addressOffset>0xE88</addressOffset>
53525          <size>32</size>
53526          <access>read-write</access>
53527          <resetValue>0x0</resetValue>
53528          <resetMask>0xF</resetMask>
53529          <fields>
53530            <field>
53531              <name>WAKE_UP</name>
53532              <description>Mask bit for corresponding bit in interrupt request register.</description>
53533              <bitRange>[0:0]</bitRange>
53534              <access>read-write</access>
53535            </field>
53536            <field>
53537              <name>EZ_STOP</name>
53538              <description>Mask bit for corresponding bit in interrupt request register.</description>
53539              <bitRange>[1:1]</bitRange>
53540              <access>read-write</access>
53541            </field>
53542            <field>
53543              <name>EZ_WRITE_STOP</name>
53544              <description>Mask bit for corresponding bit in interrupt request register.</description>
53545              <bitRange>[2:2]</bitRange>
53546              <access>read-write</access>
53547            </field>
53548            <field>
53549              <name>EZ_READ_STOP</name>
53550              <description>Mask bit for corresponding bit in interrupt request register.</description>
53551              <bitRange>[3:3]</bitRange>
53552              <access>read-write</access>
53553            </field>
53554          </fields>
53555        </register>
53556        <register>
53557          <name>INTR_I2C_EC_MASKED</name>
53558          <description>Externally clocked I2C interrupt masked</description>
53559          <addressOffset>0xE8C</addressOffset>
53560          <size>32</size>
53561          <access>read-only</access>
53562          <resetValue>0x0</resetValue>
53563          <resetMask>0xF</resetMask>
53564          <fields>
53565            <field>
53566              <name>WAKE_UP</name>
53567              <description>Logical and of corresponding request and mask bits.</description>
53568              <bitRange>[0:0]</bitRange>
53569              <access>read-only</access>
53570            </field>
53571            <field>
53572              <name>EZ_STOP</name>
53573              <description>Logical and of corresponding request and mask bits.</description>
53574              <bitRange>[1:1]</bitRange>
53575              <access>read-only</access>
53576            </field>
53577            <field>
53578              <name>EZ_WRITE_STOP</name>
53579              <description>Logical and of corresponding request and mask bits.</description>
53580              <bitRange>[2:2]</bitRange>
53581              <access>read-only</access>
53582            </field>
53583            <field>
53584              <name>EZ_READ_STOP</name>
53585              <description>Logical and of corresponding request and mask bits.</description>
53586              <bitRange>[3:3]</bitRange>
53587              <access>read-only</access>
53588            </field>
53589          </fields>
53590        </register>
53591        <register>
53592          <name>INTR_SPI_EC</name>
53593          <description>Externally clocked SPI interrupt request</description>
53594          <addressOffset>0xEC0</addressOffset>
53595          <size>32</size>
53596          <access>read-write</access>
53597          <resetValue>0x0</resetValue>
53598          <resetMask>0xF</resetMask>
53599          <fields>
53600            <field>
53601              <name>WAKE_UP</name>
53602              <description>Wake up request. Active on incoming slave request when externally clocked selection is '1'.
53603
53604Only used when EC_AM is '1'.</description>
53605              <bitRange>[0:0]</bitRange>
53606              <access>read-write</access>
53607            </field>
53608            <field>
53609              <name>EZ_STOP</name>
53610              <description>STOP detection. Activated on the end of a every transfer (SPI deselection).
53611
53612Only available in EZ and CMD_RESP mode and when EC_OP is '1'.</description>
53613              <bitRange>[1:1]</bitRange>
53614              <access>read-write</access>
53615            </field>
53616            <field>
53617              <name>EZ_WRITE_STOP</name>
53618              <description>STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a  transfer that only writes the base address does NOT activate this event.
53619
53620Only used in EZ and CMD_RESP modes and when EC_OP is '1'.</description>
53621              <bitRange>[2:2]</bitRange>
53622              <access>read-write</access>
53623            </field>
53624            <field>
53625              <name>EZ_READ_STOP</name>
53626              <description>STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from.
53627
53628Only used in EZ and CMD_RESP modes and when EC_OP is '1'.</description>
53629              <bitRange>[3:3]</bitRange>
53630              <access>read-write</access>
53631            </field>
53632          </fields>
53633        </register>
53634        <register>
53635          <name>INTR_SPI_EC_MASK</name>
53636          <description>Externally clocked SPI interrupt mask</description>
53637          <addressOffset>0xEC8</addressOffset>
53638          <size>32</size>
53639          <access>read-write</access>
53640          <resetValue>0x0</resetValue>
53641          <resetMask>0xF</resetMask>
53642          <fields>
53643            <field>
53644              <name>WAKE_UP</name>
53645              <description>Mask bit for corresponding bit in interrupt request register.</description>
53646              <bitRange>[0:0]</bitRange>
53647              <access>read-write</access>
53648            </field>
53649            <field>
53650              <name>EZ_STOP</name>
53651              <description>Mask bit for corresponding bit in interrupt request register.</description>
53652              <bitRange>[1:1]</bitRange>
53653              <access>read-write</access>
53654            </field>
53655            <field>
53656              <name>EZ_WRITE_STOP</name>
53657              <description>Mask bit for corresponding bit in interrupt request register.</description>
53658              <bitRange>[2:2]</bitRange>
53659              <access>read-write</access>
53660            </field>
53661            <field>
53662              <name>EZ_READ_STOP</name>
53663              <description>Mask bit for corresponding bit in interrupt request register.</description>
53664              <bitRange>[3:3]</bitRange>
53665              <access>read-write</access>
53666            </field>
53667          </fields>
53668        </register>
53669        <register>
53670          <name>INTR_SPI_EC_MASKED</name>
53671          <description>Externally clocked SPI interrupt masked</description>
53672          <addressOffset>0xECC</addressOffset>
53673          <size>32</size>
53674          <access>read-only</access>
53675          <resetValue>0x0</resetValue>
53676          <resetMask>0xF</resetMask>
53677          <fields>
53678            <field>
53679              <name>WAKE_UP</name>
53680              <description>Logical and of corresponding request and mask bits.</description>
53681              <bitRange>[0:0]</bitRange>
53682              <access>read-only</access>
53683            </field>
53684            <field>
53685              <name>EZ_STOP</name>
53686              <description>Logical and of corresponding request and mask bits.</description>
53687              <bitRange>[1:1]</bitRange>
53688              <access>read-only</access>
53689            </field>
53690            <field>
53691              <name>EZ_WRITE_STOP</name>
53692              <description>Logical and of corresponding request and mask bits.</description>
53693              <bitRange>[2:2]</bitRange>
53694              <access>read-only</access>
53695            </field>
53696            <field>
53697              <name>EZ_READ_STOP</name>
53698              <description>Logical and of corresponding request and mask bits.</description>
53699              <bitRange>[3:3]</bitRange>
53700              <access>read-only</access>
53701            </field>
53702          </fields>
53703        </register>
53704        <register>
53705          <name>INTR_M</name>
53706          <description>Master interrupt request</description>
53707          <addressOffset>0xF00</addressOffset>
53708          <size>32</size>
53709          <access>read-write</access>
53710          <resetValue>0x0</resetValue>
53711          <resetMask>0x317</resetMask>
53712          <fields>
53713            <field>
53714              <name>I2C_ARB_LOST</name>
53715              <description>I2C master lost arbitration: the value driven by the master on the SDA line is not the same as the value observed on the SDA line.</description>
53716              <bitRange>[0:0]</bitRange>
53717              <access>read-write</access>
53718            </field>
53719            <field>
53720              <name>I2C_NACK</name>
53721              <description>I2C master negative acknowledgement. Set to '1', when the master receives a NACK (typically after the master transmitted the slave address or TX data).</description>
53722              <bitRange>[1:1]</bitRange>
53723              <access>read-write</access>
53724            </field>
53725            <field>
53726              <name>I2C_ACK</name>
53727              <description>I2C master acknowledgement. Set to '1', when the master receives a ACK (typically after the master transmitted the slave address or TX data).</description>
53728              <bitRange>[2:2]</bitRange>
53729              <access>read-write</access>
53730            </field>
53731            <field>
53732              <name>I2C_STOP</name>
53733              <description>I2C master STOP. Set to '1', when the master has transmitted a STOP.</description>
53734              <bitRange>[4:4]</bitRange>
53735              <access>read-write</access>
53736            </field>
53737            <field>
53738              <name>I2C_BUS_ERROR</name>
53739              <description>I2C master bus error (unexpected detection of START or STOP condition).</description>
53740              <bitRange>[8:8]</bitRange>
53741              <access>read-write</access>
53742            </field>
53743            <field>
53744              <name>SPI_DONE</name>
53745              <description>SPI master transfer done event: all data frames in the transmit FIFO are sent, the transmit FIFO is empty (both TX FIFO and transmit shifter register are empty), and SPI select output pin is deselected.</description>
53746              <bitRange>[9:9]</bitRange>
53747              <access>read-write</access>
53748            </field>
53749          </fields>
53750        </register>
53751        <register>
53752          <name>INTR_M_SET</name>
53753          <description>Master interrupt set request</description>
53754          <addressOffset>0xF04</addressOffset>
53755          <size>32</size>
53756          <access>read-write</access>
53757          <resetValue>0x0</resetValue>
53758          <resetMask>0x317</resetMask>
53759          <fields>
53760            <field>
53761              <name>I2C_ARB_LOST</name>
53762              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
53763              <bitRange>[0:0]</bitRange>
53764              <access>read-write</access>
53765            </field>
53766            <field>
53767              <name>I2C_NACK</name>
53768              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
53769              <bitRange>[1:1]</bitRange>
53770              <access>read-write</access>
53771            </field>
53772            <field>
53773              <name>I2C_ACK</name>
53774              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
53775              <bitRange>[2:2]</bitRange>
53776              <access>read-write</access>
53777            </field>
53778            <field>
53779              <name>I2C_STOP</name>
53780              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
53781              <bitRange>[4:4]</bitRange>
53782              <access>read-write</access>
53783            </field>
53784            <field>
53785              <name>I2C_BUS_ERROR</name>
53786              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
53787              <bitRange>[8:8]</bitRange>
53788              <access>read-write</access>
53789            </field>
53790            <field>
53791              <name>SPI_DONE</name>
53792              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
53793              <bitRange>[9:9]</bitRange>
53794              <access>read-write</access>
53795            </field>
53796          </fields>
53797        </register>
53798        <register>
53799          <name>INTR_M_MASK</name>
53800          <description>Master interrupt mask</description>
53801          <addressOffset>0xF08</addressOffset>
53802          <size>32</size>
53803          <access>read-write</access>
53804          <resetValue>0x0</resetValue>
53805          <resetMask>0x317</resetMask>
53806          <fields>
53807            <field>
53808              <name>I2C_ARB_LOST</name>
53809              <description>Mask bit for corresponding bit in interrupt request register.</description>
53810              <bitRange>[0:0]</bitRange>
53811              <access>read-write</access>
53812            </field>
53813            <field>
53814              <name>I2C_NACK</name>
53815              <description>Mask bit for corresponding bit in interrupt request register.</description>
53816              <bitRange>[1:1]</bitRange>
53817              <access>read-write</access>
53818            </field>
53819            <field>
53820              <name>I2C_ACK</name>
53821              <description>Mask bit for corresponding bit in interrupt request register.</description>
53822              <bitRange>[2:2]</bitRange>
53823              <access>read-write</access>
53824            </field>
53825            <field>
53826              <name>I2C_STOP</name>
53827              <description>Mask bit for corresponding bit in interrupt request register.</description>
53828              <bitRange>[4:4]</bitRange>
53829              <access>read-write</access>
53830            </field>
53831            <field>
53832              <name>I2C_BUS_ERROR</name>
53833              <description>Mask bit for corresponding bit in interrupt request register.</description>
53834              <bitRange>[8:8]</bitRange>
53835              <access>read-write</access>
53836            </field>
53837            <field>
53838              <name>SPI_DONE</name>
53839              <description>Mask bit for corresponding bit in interrupt request register.</description>
53840              <bitRange>[9:9]</bitRange>
53841              <access>read-write</access>
53842            </field>
53843          </fields>
53844        </register>
53845        <register>
53846          <name>INTR_M_MASKED</name>
53847          <description>Master interrupt masked request</description>
53848          <addressOffset>0xF0C</addressOffset>
53849          <size>32</size>
53850          <access>read-only</access>
53851          <resetValue>0x0</resetValue>
53852          <resetMask>0x317</resetMask>
53853          <fields>
53854            <field>
53855              <name>I2C_ARB_LOST</name>
53856              <description>Logical and of corresponding request and mask bits.</description>
53857              <bitRange>[0:0]</bitRange>
53858              <access>read-only</access>
53859            </field>
53860            <field>
53861              <name>I2C_NACK</name>
53862              <description>Logical and of corresponding request and mask bits.</description>
53863              <bitRange>[1:1]</bitRange>
53864              <access>read-only</access>
53865            </field>
53866            <field>
53867              <name>I2C_ACK</name>
53868              <description>Logical and of corresponding request and mask bits.</description>
53869              <bitRange>[2:2]</bitRange>
53870              <access>read-only</access>
53871            </field>
53872            <field>
53873              <name>I2C_STOP</name>
53874              <description>Logical and of corresponding request and mask bits.</description>
53875              <bitRange>[4:4]</bitRange>
53876              <access>read-only</access>
53877            </field>
53878            <field>
53879              <name>I2C_BUS_ERROR</name>
53880              <description>Logical and of corresponding request and mask bits.</description>
53881              <bitRange>[8:8]</bitRange>
53882              <access>read-only</access>
53883            </field>
53884            <field>
53885              <name>SPI_DONE</name>
53886              <description>Logical and of corresponding request and mask bits.</description>
53887              <bitRange>[9:9]</bitRange>
53888              <access>read-only</access>
53889            </field>
53890          </fields>
53891        </register>
53892        <register>
53893          <name>INTR_S</name>
53894          <description>Slave interrupt request</description>
53895          <addressOffset>0xF40</addressOffset>
53896          <size>32</size>
53897          <access>read-write</access>
53898          <resetValue>0x0</resetValue>
53899          <resetMask>0xFFF</resetMask>
53900          <fields>
53901            <field>
53902              <name>I2C_ARB_LOST</name>
53903              <description>I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur, it represents erroneous I2C bus behavior. In case of lost arbitration, the I2C slave state machine abort the ongoing transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error.</description>
53904              <bitRange>[0:0]</bitRange>
53905              <access>read-write</access>
53906            </field>
53907            <field>
53908              <name>I2C_NACK</name>
53909              <description>I2C slave negative acknowledgement received. Set to '1', when the slave receives a NACK (typically after the slave transmitted TX data).</description>
53910              <bitRange>[1:1]</bitRange>
53911              <access>read-write</access>
53912            </field>
53913            <field>
53914              <name>I2C_ACK</name>
53915              <description>I2C slave acknowledgement received. Set to '1', when the slave receives a ACK (typically after the slave transmitted TX data).</description>
53916              <bitRange>[2:2]</bitRange>
53917              <access>read-write</access>
53918            </field>
53919            <field>
53920              <name>I2C_WRITE_STOP</name>
53921              <description>I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1', when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C transfers separated by a REPEATED START can be distinguished and potentially treated separately by the Firmware. Note that the second I2C transfer (after a REPEATED START) may be to a different slave address.
53922
53923In non EZ mode, the event is detected on any I2C write transfer intended for this slave. Note that a I2C write address intended for the slave (address is matching and a it is a write transfer) will result in a I2C_WRITE_STOP event independent of whether the I2C address is ACK'd or NACK'd.
53924
53925In EZ mode, the event is detected only on I2C write transfers that have EZ data written to the memory structure (an I2C write transfer that only communicates an I2C address and EZ address, will not result in this event being detected).</description>
53926              <bitRange>[3:3]</bitRange>
53927              <access>read-write</access>
53928            </field>
53929            <field>
53930              <name>I2C_STOP</name>
53931              <description>I2C STOP event for I2C (read or write) transfer intended for this slave (address matching is performed). Set to '1', when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C transfers separated by a REPEATED START can be distinguished and potentially treated separately by the Firmware. Note that the second I2C transfer (after a REPEATED START) may be to a different slave address.
53932
53933The event is detected on any I2C transfer intended for this slave. Note that a I2C address intended for the slave (address is matching) will result in a I2C_STOP event independent of whether the I2C address is ACK'd or NACK'd.</description>
53934              <bitRange>[4:4]</bitRange>
53935              <access>read-write</access>
53936            </field>
53937            <field>
53938              <name>I2C_START</name>
53939              <description>I2C slave START received. Set to '1', when START or REPEATED START event is detected.
53940
53941In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') AND clock stretching is performed (till the internally clocked logic takes over) (I2C_CTRL.S_NOT_READY_ADDR_NACK is '0'), this field is NOT set. The Firmware should use INTR_S_EC.WAKE_UP, INTR_S.I2C_ADDR_MATCH and INTR_S.I2C_GENERAL.</description>
53942              <bitRange>[5:5]</bitRange>
53943              <access>read-write</access>
53944            </field>
53945            <field>
53946              <name>I2C_ADDR_MATCH</name>
53947              <description>I2C slave matching address received. If CTRL.ADDR_ACCEPT, the received address (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked operation (CTRL.EC_OP_MODE is '0'), this field is set when the event is detected.</description>
53948              <bitRange>[6:6]</bitRange>
53949              <access>read-write</access>
53950            </field>
53951            <field>
53952              <name>I2C_GENERAL</name>
53953              <description>I2C slave general call address received.  If CTRL.ADDR_ACCEPT, the received address 0x00 (including the R/W bit) is available in the RX FIFO.   In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked operation (CTRL.EC_OP_MODE is '0'), this field is set when the event is detected.</description>
53954              <bitRange>[7:7]</bitRange>
53955              <access>read-write</access>
53956            </field>
53957            <field>
53958              <name>I2C_BUS_ERROR</name>
53959              <description>I2C slave bus error (unexpected detection of START or STOP condition). This should not occur, it represents erroneous I2C bus behavior. In case of a bus error, the I2C slave state machine abort the ongoing transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error.</description>
53960              <bitRange>[8:8]</bitRange>
53961              <access>read-write</access>
53962            </field>
53963            <field>
53964              <name>SPI_EZ_WRITE_STOP</name>
53965              <description>SPI slave deselected after a write EZ SPI transfer occurred.</description>
53966              <bitRange>[9:9]</bitRange>
53967              <access>read-write</access>
53968            </field>
53969            <field>
53970              <name>SPI_EZ_STOP</name>
53971              <description>SPI slave deselected after any EZ SPI transfer occurred.</description>
53972              <bitRange>[10:10]</bitRange>
53973              <access>read-write</access>
53974            </field>
53975            <field>
53976              <name>SPI_BUS_ERROR</name>
53977              <description>SPI slave deselected at an unexpected time in the SPI transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error.</description>
53978              <bitRange>[11:11]</bitRange>
53979              <access>read-write</access>
53980            </field>
53981          </fields>
53982        </register>
53983        <register>
53984          <name>INTR_S_SET</name>
53985          <description>Slave interrupt set request</description>
53986          <addressOffset>0xF44</addressOffset>
53987          <size>32</size>
53988          <access>read-write</access>
53989          <resetValue>0x0</resetValue>
53990          <resetMask>0xFFF</resetMask>
53991          <fields>
53992            <field>
53993              <name>I2C_ARB_LOST</name>
53994              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
53995              <bitRange>[0:0]</bitRange>
53996              <access>read-write</access>
53997            </field>
53998            <field>
53999              <name>I2C_NACK</name>
54000              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
54001              <bitRange>[1:1]</bitRange>
54002              <access>read-write</access>
54003            </field>
54004            <field>
54005              <name>I2C_ACK</name>
54006              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
54007              <bitRange>[2:2]</bitRange>
54008              <access>read-write</access>
54009            </field>
54010            <field>
54011              <name>I2C_WRITE_STOP</name>
54012              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
54013              <bitRange>[3:3]</bitRange>
54014              <access>read-write</access>
54015            </field>
54016            <field>
54017              <name>I2C_STOP</name>
54018              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
54019              <bitRange>[4:4]</bitRange>
54020              <access>read-write</access>
54021            </field>
54022            <field>
54023              <name>I2C_START</name>
54024              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
54025              <bitRange>[5:5]</bitRange>
54026              <access>read-write</access>
54027            </field>
54028            <field>
54029              <name>I2C_ADDR_MATCH</name>
54030              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
54031              <bitRange>[6:6]</bitRange>
54032              <access>read-write</access>
54033            </field>
54034            <field>
54035              <name>I2C_GENERAL</name>
54036              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
54037              <bitRange>[7:7]</bitRange>
54038              <access>read-write</access>
54039            </field>
54040            <field>
54041              <name>I2C_BUS_ERROR</name>
54042              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
54043              <bitRange>[8:8]</bitRange>
54044              <access>read-write</access>
54045            </field>
54046            <field>
54047              <name>SPI_EZ_WRITE_STOP</name>
54048              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
54049              <bitRange>[9:9]</bitRange>
54050              <access>read-write</access>
54051            </field>
54052            <field>
54053              <name>SPI_EZ_STOP</name>
54054              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
54055              <bitRange>[10:10]</bitRange>
54056              <access>read-write</access>
54057            </field>
54058            <field>
54059              <name>SPI_BUS_ERROR</name>
54060              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
54061              <bitRange>[11:11]</bitRange>
54062              <access>read-write</access>
54063            </field>
54064          </fields>
54065        </register>
54066        <register>
54067          <name>INTR_S_MASK</name>
54068          <description>Slave interrupt mask</description>
54069          <addressOffset>0xF48</addressOffset>
54070          <size>32</size>
54071          <access>read-write</access>
54072          <resetValue>0x0</resetValue>
54073          <resetMask>0xFFF</resetMask>
54074          <fields>
54075            <field>
54076              <name>I2C_ARB_LOST</name>
54077              <description>Mask bit for corresponding bit in interrupt request register.</description>
54078              <bitRange>[0:0]</bitRange>
54079              <access>read-write</access>
54080            </field>
54081            <field>
54082              <name>I2C_NACK</name>
54083              <description>Mask bit for corresponding bit in interrupt request register.</description>
54084              <bitRange>[1:1]</bitRange>
54085              <access>read-write</access>
54086            </field>
54087            <field>
54088              <name>I2C_ACK</name>
54089              <description>Mask bit for corresponding bit in interrupt request register.</description>
54090              <bitRange>[2:2]</bitRange>
54091              <access>read-write</access>
54092            </field>
54093            <field>
54094              <name>I2C_WRITE_STOP</name>
54095              <description>Mask bit for corresponding bit in interrupt request register.</description>
54096              <bitRange>[3:3]</bitRange>
54097              <access>read-write</access>
54098            </field>
54099            <field>
54100              <name>I2C_STOP</name>
54101              <description>Mask bit for corresponding bit in interrupt request register.</description>
54102              <bitRange>[4:4]</bitRange>
54103              <access>read-write</access>
54104            </field>
54105            <field>
54106              <name>I2C_START</name>
54107              <description>Mask bit for corresponding bit in interrupt request register.</description>
54108              <bitRange>[5:5]</bitRange>
54109              <access>read-write</access>
54110            </field>
54111            <field>
54112              <name>I2C_ADDR_MATCH</name>
54113              <description>Mask bit for corresponding bit in interrupt request register.</description>
54114              <bitRange>[6:6]</bitRange>
54115              <access>read-write</access>
54116            </field>
54117            <field>
54118              <name>I2C_GENERAL</name>
54119              <description>Mask bit for corresponding bit in interrupt request register.</description>
54120              <bitRange>[7:7]</bitRange>
54121              <access>read-write</access>
54122            </field>
54123            <field>
54124              <name>I2C_BUS_ERROR</name>
54125              <description>Mask bit for corresponding bit in interrupt request register.</description>
54126              <bitRange>[8:8]</bitRange>
54127              <access>read-write</access>
54128            </field>
54129            <field>
54130              <name>SPI_EZ_WRITE_STOP</name>
54131              <description>Mask bit for corresponding bit in interrupt request register.</description>
54132              <bitRange>[9:9]</bitRange>
54133              <access>read-write</access>
54134            </field>
54135            <field>
54136              <name>SPI_EZ_STOP</name>
54137              <description>Mask bit for corresponding bit in interrupt request register.</description>
54138              <bitRange>[10:10]</bitRange>
54139              <access>read-write</access>
54140            </field>
54141            <field>
54142              <name>SPI_BUS_ERROR</name>
54143              <description>Mask bit for corresponding bit in interrupt request register.</description>
54144              <bitRange>[11:11]</bitRange>
54145              <access>read-write</access>
54146            </field>
54147          </fields>
54148        </register>
54149        <register>
54150          <name>INTR_S_MASKED</name>
54151          <description>Slave interrupt masked request</description>
54152          <addressOffset>0xF4C</addressOffset>
54153          <size>32</size>
54154          <access>read-only</access>
54155          <resetValue>0x0</resetValue>
54156          <resetMask>0xFFF</resetMask>
54157          <fields>
54158            <field>
54159              <name>I2C_ARB_LOST</name>
54160              <description>Logical and of corresponding request and mask bits.</description>
54161              <bitRange>[0:0]</bitRange>
54162              <access>read-only</access>
54163            </field>
54164            <field>
54165              <name>I2C_NACK</name>
54166              <description>Logical and of corresponding request and mask bits.</description>
54167              <bitRange>[1:1]</bitRange>
54168              <access>read-only</access>
54169            </field>
54170            <field>
54171              <name>I2C_ACK</name>
54172              <description>Logical and of corresponding request and mask bits.</description>
54173              <bitRange>[2:2]</bitRange>
54174              <access>read-only</access>
54175            </field>
54176            <field>
54177              <name>I2C_WRITE_STOP</name>
54178              <description>Logical and of corresponding request and mask bits.</description>
54179              <bitRange>[3:3]</bitRange>
54180              <access>read-only</access>
54181            </field>
54182            <field>
54183              <name>I2C_STOP</name>
54184              <description>Logical and of corresponding request and mask bits.</description>
54185              <bitRange>[4:4]</bitRange>
54186              <access>read-only</access>
54187            </field>
54188            <field>
54189              <name>I2C_START</name>
54190              <description>Logical and of corresponding request and mask bits.</description>
54191              <bitRange>[5:5]</bitRange>
54192              <access>read-only</access>
54193            </field>
54194            <field>
54195              <name>I2C_ADDR_MATCH</name>
54196              <description>Logical and of corresponding request and mask bits.</description>
54197              <bitRange>[6:6]</bitRange>
54198              <access>read-only</access>
54199            </field>
54200            <field>
54201              <name>I2C_GENERAL</name>
54202              <description>Logical and of corresponding request and mask bits.</description>
54203              <bitRange>[7:7]</bitRange>
54204              <access>read-only</access>
54205            </field>
54206            <field>
54207              <name>I2C_BUS_ERROR</name>
54208              <description>Logical and of corresponding request and mask bits.</description>
54209              <bitRange>[8:8]</bitRange>
54210              <access>read-only</access>
54211            </field>
54212            <field>
54213              <name>SPI_EZ_WRITE_STOP</name>
54214              <description>Logical and of corresponding request and mask bits.</description>
54215              <bitRange>[9:9]</bitRange>
54216              <access>read-only</access>
54217            </field>
54218            <field>
54219              <name>SPI_EZ_STOP</name>
54220              <description>Logical and of corresponding request and mask bits.</description>
54221              <bitRange>[10:10]</bitRange>
54222              <access>read-only</access>
54223            </field>
54224            <field>
54225              <name>SPI_BUS_ERROR</name>
54226              <description>Logical and of corresponding request and mask bits.</description>
54227              <bitRange>[11:11]</bitRange>
54228              <access>read-only</access>
54229            </field>
54230          </fields>
54231        </register>
54232        <register>
54233          <name>INTR_TX</name>
54234          <description>Transmitter interrupt request</description>
54235          <addressOffset>0xF80</addressOffset>
54236          <size>32</size>
54237          <access>read-write</access>
54238          <resetValue>0x0</resetValue>
54239          <resetMask>0x7F3</resetMask>
54240          <fields>
54241            <field>
54242              <name>TRIGGER</name>
54243              <description>Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL.TRIGGER_LEVEL.
54244
54245Only used in FIFO mode.</description>
54246              <bitRange>[0:0]</bitRange>
54247              <access>read-write</access>
54248            </field>
54249            <field>
54250              <name>NOT_FULL</name>
54251              <description>TX FIFO is not full. Dependent on CTRL.BYTE_MODE: (FF_DATA_NR = EZ_DATA_NR/2)
54252BYTE_MODE is '0': # entries != FF_DATA_NR/2.
54253BYTE_MODE is '1': # entries != FF_DATA_NR.
54254
54255Only used in FIFO mode.</description>
54256              <bitRange>[1:1]</bitRange>
54257              <access>read-write</access>
54258            </field>
54259            <field>
54260              <name>EMPTY</name>
54261              <description>TX FIFO is empty; i.e. it has 0 entries.
54262
54263Only used in FIFO mode.</description>
54264              <bitRange>[4:4]</bitRange>
54265              <access>read-write</access>
54266            </field>
54267            <field>
54268              <name>OVERFLOW</name>
54269              <description>Attempt to write to a full TX FIFO.
54270
54271Only used in FIFO mode.</description>
54272              <bitRange>[5:5]</bitRange>
54273              <access>read-write</access>
54274            </field>
54275            <field>
54276              <name>UNDERFLOW</name>
54277              <description>Attempt to read from an empty TX FIFO. This happens when the IP is ready to transfer data and EMPTY is '1'.
54278
54279Only used in FIFO mode.</description>
54280              <bitRange>[6:6]</bitRange>
54281              <access>read-write</access>
54282            </field>
54283            <field>
54284              <name>BLOCKED</name>
54285              <description>AHB-Lite write transfer can not get access to the EZ memory (EZ data access), due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'.</description>
54286              <bitRange>[7:7]</bitRange>
54287              <access>read-write</access>
54288            </field>
54289            <field>
54290              <name>UART_NACK</name>
54291              <description>UART transmitter received a negative acknowledgement in SmartCard mode. Set to '1', when event is detected. Write with '1' to clear bit.</description>
54292              <bitRange>[8:8]</bitRange>
54293              <access>read-write</access>
54294            </field>
54295            <field>
54296              <name>UART_DONE</name>
54297              <description>UART transmitter done event. This happens when the IP is done transferring all data in the TX FIFO, and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty). Set to '1', when event is detected. Write with '1' to clear bit.</description>
54298              <bitRange>[9:9]</bitRange>
54299              <access>read-write</access>
54300            </field>
54301            <field>
54302              <name>UART_ARB_LOST</name>
54303              <description>UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. This condition event is useful when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes. Set to '1', when event is detected. Write with '1' to clear bit.</description>
54304              <bitRange>[10:10]</bitRange>
54305              <access>read-write</access>
54306            </field>
54307          </fields>
54308        </register>
54309        <register>
54310          <name>INTR_TX_SET</name>
54311          <description>Transmitter interrupt set request</description>
54312          <addressOffset>0xF84</addressOffset>
54313          <size>32</size>
54314          <access>read-write</access>
54315          <resetValue>0x0</resetValue>
54316          <resetMask>0x7F3</resetMask>
54317          <fields>
54318            <field>
54319              <name>TRIGGER</name>
54320              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
54321              <bitRange>[0:0]</bitRange>
54322              <access>read-write</access>
54323            </field>
54324            <field>
54325              <name>NOT_FULL</name>
54326              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
54327              <bitRange>[1:1]</bitRange>
54328              <access>read-write</access>
54329            </field>
54330            <field>
54331              <name>EMPTY</name>
54332              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
54333              <bitRange>[4:4]</bitRange>
54334              <access>read-write</access>
54335            </field>
54336            <field>
54337              <name>OVERFLOW</name>
54338              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
54339              <bitRange>[5:5]</bitRange>
54340              <access>read-write</access>
54341            </field>
54342            <field>
54343              <name>UNDERFLOW</name>
54344              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
54345              <bitRange>[6:6]</bitRange>
54346              <access>read-write</access>
54347            </field>
54348            <field>
54349              <name>BLOCKED</name>
54350              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
54351              <bitRange>[7:7]</bitRange>
54352              <access>read-write</access>
54353            </field>
54354            <field>
54355              <name>UART_NACK</name>
54356              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
54357              <bitRange>[8:8]</bitRange>
54358              <access>read-write</access>
54359            </field>
54360            <field>
54361              <name>UART_DONE</name>
54362              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
54363              <bitRange>[9:9]</bitRange>
54364              <access>read-write</access>
54365            </field>
54366            <field>
54367              <name>UART_ARB_LOST</name>
54368              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
54369              <bitRange>[10:10]</bitRange>
54370              <access>read-write</access>
54371            </field>
54372          </fields>
54373        </register>
54374        <register>
54375          <name>INTR_TX_MASK</name>
54376          <description>Transmitter interrupt mask</description>
54377          <addressOffset>0xF88</addressOffset>
54378          <size>32</size>
54379          <access>read-write</access>
54380          <resetValue>0x0</resetValue>
54381          <resetMask>0x7F3</resetMask>
54382          <fields>
54383            <field>
54384              <name>TRIGGER</name>
54385              <description>Mask bit for corresponding bit in interrupt request register.</description>
54386              <bitRange>[0:0]</bitRange>
54387              <access>read-write</access>
54388            </field>
54389            <field>
54390              <name>NOT_FULL</name>
54391              <description>Mask bit for corresponding bit in interrupt request register.</description>
54392              <bitRange>[1:1]</bitRange>
54393              <access>read-write</access>
54394            </field>
54395            <field>
54396              <name>EMPTY</name>
54397              <description>Mask bit for corresponding bit in interrupt request register.</description>
54398              <bitRange>[4:4]</bitRange>
54399              <access>read-write</access>
54400            </field>
54401            <field>
54402              <name>OVERFLOW</name>
54403              <description>Mask bit for corresponding bit in interrupt request register.</description>
54404              <bitRange>[5:5]</bitRange>
54405              <access>read-write</access>
54406            </field>
54407            <field>
54408              <name>UNDERFLOW</name>
54409              <description>Mask bit for corresponding bit in interrupt request register.</description>
54410              <bitRange>[6:6]</bitRange>
54411              <access>read-write</access>
54412            </field>
54413            <field>
54414              <name>BLOCKED</name>
54415              <description>Mask bit for corresponding bit in interrupt request register.</description>
54416              <bitRange>[7:7]</bitRange>
54417              <access>read-write</access>
54418            </field>
54419            <field>
54420              <name>UART_NACK</name>
54421              <description>Mask bit for corresponding bit in interrupt request register.</description>
54422              <bitRange>[8:8]</bitRange>
54423              <access>read-write</access>
54424            </field>
54425            <field>
54426              <name>UART_DONE</name>
54427              <description>Mask bit for corresponding bit in interrupt request register.</description>
54428              <bitRange>[9:9]</bitRange>
54429              <access>read-write</access>
54430            </field>
54431            <field>
54432              <name>UART_ARB_LOST</name>
54433              <description>Mask bit for corresponding bit in interrupt request register.</description>
54434              <bitRange>[10:10]</bitRange>
54435              <access>read-write</access>
54436            </field>
54437          </fields>
54438        </register>
54439        <register>
54440          <name>INTR_TX_MASKED</name>
54441          <description>Transmitter interrupt masked request</description>
54442          <addressOffset>0xF8C</addressOffset>
54443          <size>32</size>
54444          <access>read-only</access>
54445          <resetValue>0x0</resetValue>
54446          <resetMask>0x7F3</resetMask>
54447          <fields>
54448            <field>
54449              <name>TRIGGER</name>
54450              <description>Logical and of corresponding request and mask bits.</description>
54451              <bitRange>[0:0]</bitRange>
54452              <access>read-only</access>
54453            </field>
54454            <field>
54455              <name>NOT_FULL</name>
54456              <description>Logical and of corresponding request and mask bits.</description>
54457              <bitRange>[1:1]</bitRange>
54458              <access>read-only</access>
54459            </field>
54460            <field>
54461              <name>EMPTY</name>
54462              <description>Logical and of corresponding request and mask bits.</description>
54463              <bitRange>[4:4]</bitRange>
54464              <access>read-only</access>
54465            </field>
54466            <field>
54467              <name>OVERFLOW</name>
54468              <description>Logical and of corresponding request and mask bits.</description>
54469              <bitRange>[5:5]</bitRange>
54470              <access>read-only</access>
54471            </field>
54472            <field>
54473              <name>UNDERFLOW</name>
54474              <description>Logical and of corresponding request and mask bits.</description>
54475              <bitRange>[6:6]</bitRange>
54476              <access>read-only</access>
54477            </field>
54478            <field>
54479              <name>BLOCKED</name>
54480              <description>Logical and of corresponding request and mask bits.</description>
54481              <bitRange>[7:7]</bitRange>
54482              <access>read-only</access>
54483            </field>
54484            <field>
54485              <name>UART_NACK</name>
54486              <description>Logical and of corresponding request and mask bits.</description>
54487              <bitRange>[8:8]</bitRange>
54488              <access>read-only</access>
54489            </field>
54490            <field>
54491              <name>UART_DONE</name>
54492              <description>Logical and of corresponding request and mask bits.</description>
54493              <bitRange>[9:9]</bitRange>
54494              <access>read-only</access>
54495            </field>
54496            <field>
54497              <name>UART_ARB_LOST</name>
54498              <description>Logical and of corresponding request and mask bits.</description>
54499              <bitRange>[10:10]</bitRange>
54500              <access>read-only</access>
54501            </field>
54502          </fields>
54503        </register>
54504        <register>
54505          <name>INTR_RX</name>
54506          <description>Receiver interrupt request</description>
54507          <addressOffset>0xFC0</addressOffset>
54508          <size>32</size>
54509          <access>read-write</access>
54510          <resetValue>0x0</resetValue>
54511          <resetMask>0xFED</resetMask>
54512          <fields>
54513            <field>
54514              <name>TRIGGER</name>
54515              <description>More entries in the RX FIFO than the value specified by RX_FIFO_CTRL.TRIGGER_LEVEL.
54516
54517Only used in FIFO mode.</description>
54518              <bitRange>[0:0]</bitRange>
54519              <access>read-write</access>
54520            </field>
54521            <field>
54522              <name>NOT_EMPTY</name>
54523              <description>RX FIFO is not empty.
54524
54525Only used in FIFO mode.</description>
54526              <bitRange>[2:2]</bitRange>
54527              <access>read-write</access>
54528            </field>
54529            <field>
54530              <name>FULL</name>
54531              <description>RX FIFO is full. Note that received data frames are lost when the RX FIFO is full. Dependent on CTRL.BYTE_MODE: (FF_DATA_NR = EZ_DATA_NR/2)
54532BYTE_MODE is '0': # entries == FF_DATA_NR/2.
54533BYTE_MODE is '1': # entries == FF_DATA_NR.
54534
54535Only used in FIFO mode.</description>
54536              <bitRange>[3:3]</bitRange>
54537              <access>read-write</access>
54538            </field>
54539            <field>
54540              <name>OVERFLOW</name>
54541              <description>Attempt to write to a full RX FIFO. Note: in I2C mode, the OVERFLOW is set when a data frame is received and the RX FIFO is full, independent of whether it is ACK'd or NACK'd.
54542
54543Only used in FIFO mode.</description>
54544              <bitRange>[5:5]</bitRange>
54545              <access>read-write</access>
54546            </field>
54547            <field>
54548              <name>UNDERFLOW</name>
54549              <description>Attempt to read from an empty RX FIFO.
54550
54551Only used in FIFO mode.</description>
54552              <bitRange>[6:6]</bitRange>
54553              <access>read-write</access>
54554            </field>
54555            <field>
54556              <name>BLOCKED</name>
54557              <description>AHB-Lite read transfer can not get access to the EZ memory (EZ_DATA accesses), due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'.</description>
54558              <bitRange>[7:7]</bitRange>
54559              <access>read-write</access>
54560            </field>
54561            <field>
54562              <name>FRAME_ERROR</name>
54563              <description>Frame error in received data frame. Set to '1', when event is detected. Write with '1' to clear bit. This can be either a start or stop bit(s) error:
54564Start bit error: after the detection of the beginning of a start bit period (RX line changes from '1' to '0'), the middle of the start bit period is sampled erroneously (RX line is '1').  Note: a start bit error is detected BEFORE a data frame is received.
54565Stop bit error: the RX line is sampled as '0', but a '1' was expected. Note: a stop bit error may result in failure to receive successive data frame(s). Note: a stop bit error is detected AFTER a data frame is received.
54566
54567A stop bit error is detected after a data frame is received, and the UART_RX_CTL.DROP_ON_FRAME_ERROR field specifies whether the received frame is dropped or send to the RX FIFO. If UART_RX_CTL.DROP_ON_FRAME_ERROR is '1', the received data frame is dropped. If UART_RX_CTL.DROP_ON_FRAME_ERROR is '0', the received data frame is send to the RX FIFO. Note that Firmware can only identify the erroneous data frame in the RX FIFO if it is fast enough to read the data frame before the hardware writes a next data frame into the RX FIFO; i.e. the RX FIFO does not have error flags to tag erroneous data frames.</description>
54568              <bitRange>[8:8]</bitRange>
54569              <access>read-write</access>
54570            </field>
54571            <field>
54572              <name>PARITY_ERROR</name>
54573              <description>Parity error in received data frame. Set to '1', when event is detected. Write with '1' to clear bit. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '1', the received frame is dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '0', the received frame is send to the RX FIFO. In SmartCard submode, negatively acknowledged data frames generate a parity error. Note that Firmware can only identify the erroneous data frame in the RX FIFO if it is fast enough to read the data frame before the hardware writes a next data frame into the RX FIFO.</description>
54574              <bitRange>[9:9]</bitRange>
54575              <access>read-write</access>
54576            </field>
54577            <field>
54578              <name>BAUD_DETECT</name>
54579              <description>LIN baudrate detection is completed.  The receiver software uses the UART_RX_STATUS.BR_COUNTER value to set the right IP clock (from the programmable clock IP) to guarantee successful receipt of the first LIN data frame (Protected Identifier Field) after the synchronization byte. Set to '1', when event is detected. Write with '1' to clear bit.</description>
54580              <bitRange>[10:10]</bitRange>
54581              <access>read-write</access>
54582            </field>
54583            <field>
54584              <name>BREAK_DETECT</name>
54585              <description>Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; i.e. 'break-in-data' is supported. This feature is supported for the UART standard and LIN submodes. For the UART standard submodes, ongoing receipt of data frames is NOT affected; i.e. Firmware is expected to take the proper action. For the LIN submode, possible ongoing receipt of a data frame is stopped and the (partially) received data frame is dropped and baud rate detection is started. Set to '1', when event is detected. Write with '1' to clear bit.</description>
54586              <bitRange>[11:11]</bitRange>
54587              <access>read-write</access>
54588            </field>
54589          </fields>
54590        </register>
54591        <register>
54592          <name>INTR_RX_SET</name>
54593          <description>Receiver interrupt set request</description>
54594          <addressOffset>0xFC4</addressOffset>
54595          <size>32</size>
54596          <access>read-write</access>
54597          <resetValue>0x0</resetValue>
54598          <resetMask>0xFED</resetMask>
54599          <fields>
54600            <field>
54601              <name>TRIGGER</name>
54602              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
54603              <bitRange>[0:0]</bitRange>
54604              <access>read-write</access>
54605            </field>
54606            <field>
54607              <name>NOT_EMPTY</name>
54608              <description>Write with '1' to set corresponding bit in interrupt status register.</description>
54609              <bitRange>[2:2]</bitRange>
54610              <access>read-write</access>
54611            </field>
54612            <field>
54613              <name>FULL</name>
54614              <description>Write with '1' to set corresponding bit in interrupt status register.</description>
54615              <bitRange>[3:3]</bitRange>
54616              <access>read-write</access>
54617            </field>
54618            <field>
54619              <name>OVERFLOW</name>
54620              <description>Write with '1' to set corresponding bit in interrupt status register.</description>
54621              <bitRange>[5:5]</bitRange>
54622              <access>read-write</access>
54623            </field>
54624            <field>
54625              <name>UNDERFLOW</name>
54626              <description>Write with '1' to set corresponding bit in interrupt status register.</description>
54627              <bitRange>[6:6]</bitRange>
54628              <access>read-write</access>
54629            </field>
54630            <field>
54631              <name>BLOCKED</name>
54632              <description>Write with '1' to set corresponding bit in interrupt status register.</description>
54633              <bitRange>[7:7]</bitRange>
54634              <access>read-write</access>
54635            </field>
54636            <field>
54637              <name>FRAME_ERROR</name>
54638              <description>Write with '1' to set corresponding bit in interrupt status register.</description>
54639              <bitRange>[8:8]</bitRange>
54640              <access>read-write</access>
54641            </field>
54642            <field>
54643              <name>PARITY_ERROR</name>
54644              <description>Write with '1' to set corresponding bit in interrupt status register.</description>
54645              <bitRange>[9:9]</bitRange>
54646              <access>read-write</access>
54647            </field>
54648            <field>
54649              <name>BAUD_DETECT</name>
54650              <description>Write with '1' to set corresponding bit in interrupt status register.</description>
54651              <bitRange>[10:10]</bitRange>
54652              <access>read-write</access>
54653            </field>
54654            <field>
54655              <name>BREAK_DETECT</name>
54656              <description>Write with '1' to set corresponding bit in interrupt status register.</description>
54657              <bitRange>[11:11]</bitRange>
54658              <access>read-write</access>
54659            </field>
54660          </fields>
54661        </register>
54662        <register>
54663          <name>INTR_RX_MASK</name>
54664          <description>Receiver interrupt mask</description>
54665          <addressOffset>0xFC8</addressOffset>
54666          <size>32</size>
54667          <access>read-write</access>
54668          <resetValue>0x0</resetValue>
54669          <resetMask>0xFED</resetMask>
54670          <fields>
54671            <field>
54672              <name>TRIGGER</name>
54673              <description>Mask bit for corresponding bit in interrupt request register.</description>
54674              <bitRange>[0:0]</bitRange>
54675              <access>read-write</access>
54676            </field>
54677            <field>
54678              <name>NOT_EMPTY</name>
54679              <description>Mask bit for corresponding bit in interrupt request register.</description>
54680              <bitRange>[2:2]</bitRange>
54681              <access>read-write</access>
54682            </field>
54683            <field>
54684              <name>FULL</name>
54685              <description>Mask bit for corresponding bit in interrupt request register.</description>
54686              <bitRange>[3:3]</bitRange>
54687              <access>read-write</access>
54688            </field>
54689            <field>
54690              <name>OVERFLOW</name>
54691              <description>Mask bit for corresponding bit in interrupt request register.</description>
54692              <bitRange>[5:5]</bitRange>
54693              <access>read-write</access>
54694            </field>
54695            <field>
54696              <name>UNDERFLOW</name>
54697              <description>Mask bit for corresponding bit in interrupt request register.</description>
54698              <bitRange>[6:6]</bitRange>
54699              <access>read-write</access>
54700            </field>
54701            <field>
54702              <name>BLOCKED</name>
54703              <description>Mask bit for corresponding bit in interrupt request register.</description>
54704              <bitRange>[7:7]</bitRange>
54705              <access>read-write</access>
54706            </field>
54707            <field>
54708              <name>FRAME_ERROR</name>
54709              <description>Mask bit for corresponding bit in interrupt request register.</description>
54710              <bitRange>[8:8]</bitRange>
54711              <access>read-write</access>
54712            </field>
54713            <field>
54714              <name>PARITY_ERROR</name>
54715              <description>Mask bit for corresponding bit in interrupt request register.</description>
54716              <bitRange>[9:9]</bitRange>
54717              <access>read-write</access>
54718            </field>
54719            <field>
54720              <name>BAUD_DETECT</name>
54721              <description>Mask bit for corresponding bit in interrupt request register.</description>
54722              <bitRange>[10:10]</bitRange>
54723              <access>read-write</access>
54724            </field>
54725            <field>
54726              <name>BREAK_DETECT</name>
54727              <description>Mask bit for corresponding bit in interrupt request register.</description>
54728              <bitRange>[11:11]</bitRange>
54729              <access>read-write</access>
54730            </field>
54731          </fields>
54732        </register>
54733        <register>
54734          <name>INTR_RX_MASKED</name>
54735          <description>Receiver interrupt masked request</description>
54736          <addressOffset>0xFCC</addressOffset>
54737          <size>32</size>
54738          <access>read-only</access>
54739          <resetValue>0x0</resetValue>
54740          <resetMask>0xFED</resetMask>
54741          <fields>
54742            <field>
54743              <name>TRIGGER</name>
54744              <description>Logical and of corresponding request and mask bits.</description>
54745              <bitRange>[0:0]</bitRange>
54746              <access>read-only</access>
54747            </field>
54748            <field>
54749              <name>NOT_EMPTY</name>
54750              <description>Logical and of corresponding request and mask bits.</description>
54751              <bitRange>[2:2]</bitRange>
54752              <access>read-only</access>
54753            </field>
54754            <field>
54755              <name>FULL</name>
54756              <description>Logical and of corresponding request and mask bits.</description>
54757              <bitRange>[3:3]</bitRange>
54758              <access>read-only</access>
54759            </field>
54760            <field>
54761              <name>OVERFLOW</name>
54762              <description>Logical and of corresponding request and mask bits.</description>
54763              <bitRange>[5:5]</bitRange>
54764              <access>read-only</access>
54765            </field>
54766            <field>
54767              <name>UNDERFLOW</name>
54768              <description>Logical and of corresponding request and mask bits.</description>
54769              <bitRange>[6:6]</bitRange>
54770              <access>read-only</access>
54771            </field>
54772            <field>
54773              <name>BLOCKED</name>
54774              <description>Logical and of corresponding request and mask bits.</description>
54775              <bitRange>[7:7]</bitRange>
54776              <access>read-only</access>
54777            </field>
54778            <field>
54779              <name>FRAME_ERROR</name>
54780              <description>Logical and of corresponding request and mask bits.</description>
54781              <bitRange>[8:8]</bitRange>
54782              <access>read-only</access>
54783            </field>
54784            <field>
54785              <name>PARITY_ERROR</name>
54786              <description>Logical and of corresponding request and mask bits.</description>
54787              <bitRange>[9:9]</bitRange>
54788              <access>read-only</access>
54789            </field>
54790            <field>
54791              <name>BAUD_DETECT</name>
54792              <description>Logical and of corresponding request and mask bits.</description>
54793              <bitRange>[10:10]</bitRange>
54794              <access>read-only</access>
54795            </field>
54796            <field>
54797              <name>BREAK_DETECT</name>
54798              <description>Logical and of corresponding request and mask bits.</description>
54799              <bitRange>[11:11]</bitRange>
54800              <access>read-only</access>
54801            </field>
54802          </fields>
54803        </register>
54804      </registers>
54805    </peripheral>
54806    <peripheral derivedFrom="SCB0">
54807      <name>SCB1</name>
54808      <baseAddress>0x40510000</baseAddress>
54809    </peripheral>
54810    <peripheral derivedFrom="SCB0">
54811      <name>SCB2</name>
54812      <baseAddress>0x40520000</baseAddress>
54813    </peripheral>
54814    <peripheral derivedFrom="SCB0">
54815      <name>SCB3</name>
54816      <baseAddress>0x40530000</baseAddress>
54817    </peripheral>
54818    <peripheral derivedFrom="SCB0">
54819      <name>SCB4</name>
54820      <baseAddress>0x40540000</baseAddress>
54821    </peripheral>
54822    <peripheral derivedFrom="SCB0">
54823      <name>SCB5</name>
54824      <baseAddress>0x40550000</baseAddress>
54825    </peripheral>
54826    <peripheral derivedFrom="SCB0">
54827      <name>SCB6</name>
54828      <baseAddress>0x40560000</baseAddress>
54829    </peripheral>
54830    <peripheral>
54831      <name>CANFD0</name>
54832      <description>CAN Controller</description>
54833      <headerStructName>CANFD</headerStructName>
54834      <baseAddress>0x40580000</baseAddress>
54835      <addressBlock>
54836        <offset>0</offset>
54837        <size>131072</size>
54838        <usage>registers</usage>
54839      </addressBlock>
54840      <registers>
54841        <cluster>
54842          <name>CH</name>
54843          <description>FIFO wrapper around M_TTCAN 3PIP, to enable DMA</description>
54844          <addressOffset>0x00000000</addressOffset>
54845          <cluster>
54846            <name>M_TTCAN</name>
54847            <description>TTCAN 3PIP, includes FD</description>
54848            <addressOffset>0x00000000</addressOffset>
54849            <register>
54850              <name>CREL</name>
54851              <description>Core Release Register</description>
54852              <addressOffset>0x0</addressOffset>
54853              <size>32</size>
54854              <access>read-only</access>
54855              <resetValue>0x0</resetValue>
54856              <resetMask>0xFFFFFFFF</resetMask>
54857              <fields>
54858                <field>
54859                  <name>DAY</name>
54860                  <description>Time Stamp Day
54861Two digits, BCD-coded. This field is set by generic parameter on M_TTCAN synthesis.</description>
54862                  <bitRange>[7:0]</bitRange>
54863                  <access>read-only</access>
54864                </field>
54865                <field>
54866                  <name>MON</name>
54867                  <description>Time Stamp Month
54868Two digits, BCD-coded. This field is set by generic parameter on M_TTCAN synthesis.</description>
54869                  <bitRange>[15:8]</bitRange>
54870                  <access>read-only</access>
54871                </field>
54872                <field>
54873                  <name>YEAR</name>
54874                  <description>Time Stamp Year
54875One digit, BCD-coded. This field is set by generic parameter on M_TTCAN synthesis.</description>
54876                  <bitRange>[19:16]</bitRange>
54877                  <access>read-only</access>
54878                </field>
54879                <field>
54880                  <name>SUBSTEP</name>
54881                  <description>Sub-step of Core Release
54882One digit, BCD-coded.</description>
54883                  <bitRange>[23:20]</bitRange>
54884                  <access>read-only</access>
54885                </field>
54886                <field>
54887                  <name>STEP</name>
54888                  <description>Step of Core Release
54889One digit, BCD-coded.</description>
54890                  <bitRange>[27:24]</bitRange>
54891                  <access>read-only</access>
54892                </field>
54893                <field>
54894                  <name>REL</name>
54895                  <description>Core Release
54896One digit, BCD-coded.</description>
54897                  <bitRange>[31:28]</bitRange>
54898                  <access>read-only</access>
54899                </field>
54900              </fields>
54901            </register>
54902            <register>
54903              <name>ENDN</name>
54904              <description>Endian Register</description>
54905              <addressOffset>0x4</addressOffset>
54906              <size>32</size>
54907              <access>read-only</access>
54908              <resetValue>0x87654321</resetValue>
54909              <resetMask>0xFFFFFFFF</resetMask>
54910              <fields>
54911                <field>
54912                  <name>ETV</name>
54913                  <description>Endianness Test Value
54914The endianness test value is 0x87654321.</description>
54915                  <bitRange>[31:0]</bitRange>
54916                  <access>read-only</access>
54917                </field>
54918              </fields>
54919            </register>
54920            <register>
54921              <name>DBTP</name>
54922              <description>Data Bit Timing &amp; Prescaler Register</description>
54923              <addressOffset>0xC</addressOffset>
54924              <size>32</size>
54925              <access>read-write</access>
54926              <resetValue>0xA33</resetValue>
54927              <resetMask>0x9F1FFF</resetMask>
54928              <fields>
54929                <field>
54930                  <name>DSJW</name>
54931                  <description>Data (Re)Synchronization Jump Width
549320x0-0xF Valid values are 0 to 15. The actual interpretation by the hardware of this value is
54933such that one more than the value programmed here is used.</description>
54934                  <bitRange>[3:0]</bitRange>
54935                  <access>read-write</access>
54936                </field>
54937                <field>
54938                  <name>DTSEG2</name>
54939                  <description>Data time segment after sample point
549400x0-0xF Valid values are 0 to 15. The actual interpretation by the hardware of this value is
54941such that one more than the programmed value is used.</description>
54942                  <bitRange>[7:4]</bitRange>
54943                  <access>read-write</access>
54944                </field>
54945                <field>
54946                  <name>DTSEG1</name>
54947                  <description>Data time segment before sample point
549480x00-0x1F Valid values are 0 to 31. The actual interpretation by the hardware of this value is
54949such that one more than the programmed value is used.</description>
54950                  <bitRange>[12:8]</bitRange>
54951                  <access>read-write</access>
54952                </field>
54953                <field>
54954                  <name>DBRP</name>
54955                  <description>Data Bit Rate Prescaler
549560x00-0x1F The value by which the oscillator frequency is divided for generating the bit time
54957quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit
54958Rate Prescaler are 0 to 31. The actual interpretation by the hardware of this value is
54959such that one more than the value programmed here is used.</description>
54960                  <bitRange>[20:16]</bitRange>
54961                  <access>read-write</access>
54962                </field>
54963                <field>
54964                  <name>TDC</name>
54965                  <description>Transmitter Delay Compensation
549660= Transmitter Delay Compensation disabled
549671= Transmitter Delay Compensation enabled</description>
54968                  <bitRange>[23:23]</bitRange>
54969                  <access>read-write</access>
54970                </field>
54971              </fields>
54972            </register>
54973            <register>
54974              <name>TEST</name>
54975              <description>Test Register</description>
54976              <addressOffset>0x10</addressOffset>
54977              <size>32</size>
54978              <access>read-write</access>
54979              <resetValue>0x0</resetValue>
54980              <resetMask>0x7F</resetMask>
54981              <fields>
54982                <field>
54983                  <name>TAM</name>
54984                  <description>ASC is not supported by M_TTCAN
54985Test ASC Multiplexer Control
54986Controls output pin m_ttcan_ascm in test mode, ORed with the signal from the FSE
549870= Level at pin m_ttcan_ascm controlled by FSE
549881= Level at pin m_ttcan_ascm = '1'</description>
54989                  <bitRange>[0:0]</bitRange>
54990                  <access>read-write</access>
54991                </field>
54992                <field>
54993                  <name>TAT</name>
54994                  <description>ASC is not supported by M_TTCAN
54995Test ASC Transmit Control
54996Controls output pin m_ttcan_asct in test mode, ORed with the signal from the FSE
549970= Level at pin m_ttcan_asct controlled by FSE
549981= Level at pin m_ttcan_asct = '1'</description>
54999                  <bitRange>[1:1]</bitRange>
55000                  <access>read-write</access>
55001                </field>
55002                <field>
55003                  <name>CAM</name>
55004                  <description>ASC is not supported by M_TTCAN
55005Check ASC Multiplexer Control
55006Monitors level at output pin m_ttcan_ascm.
550070= Output pin m_ttcan_ascm = '0'
550081= Output pin m_ttcan_ascm = '1'</description>
55009                  <bitRange>[2:2]</bitRange>
55010                  <access>read-write</access>
55011                </field>
55012                <field>
55013                  <name>CAT</name>
55014                  <description>ASC is not supported by M_TTCAN
55015Check ASC Transmit Control
55016Monitors level at output pin m_ttcan_asct.
550170= Output pin m_ttcan_asct = '0'</description>
55018                  <bitRange>[3:3]</bitRange>
55019                  <access>read-write</access>
55020                </field>
55021                <field>
55022                  <name>LBCK</name>
55023                  <description>Loop Back Mode
550240= Reset value, Loop Back Mode is disabled
550251= Loop Back Mode is enabled (see Section 3.1.9, Test Modes)</description>
55026                  <bitRange>[4:4]</bitRange>
55027                  <access>read-write</access>
55028                </field>
55029                <field>
55030                  <name>TX</name>
55031                  <description>Control of Transmit Pin
5503200 Reset value, m_ttcan_tx controlled by the CAN Core, updated at the end of the CAN bit time
5503301 Sample Point can be monitored at pin m_ttcan_tx
5503410 Dominant ('0') level at pin m_ttcan_tx
5503511 Recessive ('1') at pin m_ttcan_tx</description>
55036                  <bitRange>[6:5]</bitRange>
55037                  <access>read-write</access>
55038                </field>
55039                <field>
55040                  <name>RX</name>
55041                  <description>Receive Pin
55042Monitors the actual value of pin m_ttcan_rx
550430= The CAN bus is dominant (m_ttcan_rx = '0')
550441= The CAN bus is recessive (m_ttcan_rx = '1')</description>
55045                  <bitRange>[7:7]</bitRange>
55046                  <access>read-only</access>
55047                </field>
55048              </fields>
55049            </register>
55050            <register>
55051              <name>RWD</name>
55052              <description>RAM Watchdog</description>
55053              <addressOffset>0x14</addressOffset>
55054              <size>32</size>
55055              <access>read-write</access>
55056              <resetValue>0x0</resetValue>
55057              <resetMask>0xFFFF</resetMask>
55058              <fields>
55059                <field>
55060                  <name>WDC</name>
55061                  <description>Watchdog Configuration
55062Start value of the Message RAM Watchdog Counter. With the reset value of '00' the counter is
55063disabled.</description>
55064                  <bitRange>[7:0]</bitRange>
55065                  <access>read-write</access>
55066                </field>
55067                <field>
55068                  <name>WDV</name>
55069                  <description>Watchdog Value
55070Actual Message RAM Watchdog Counter Value.</description>
55071                  <bitRange>[15:8]</bitRange>
55072                  <access>read-only</access>
55073                </field>
55074              </fields>
55075            </register>
55076            <register>
55077              <name>CCCR</name>
55078              <description>CC Control Register</description>
55079              <addressOffset>0x18</addressOffset>
55080              <size>32</size>
55081              <access>read-write</access>
55082              <resetValue>0x1</resetValue>
55083              <resetMask>0xF3FF</resetMask>
55084              <fields>
55085                <field>
55086                  <name>INIT</name>
55087                  <description>Initialization
550880= Normal Operation
550891= Initialization is started</description>
55090                  <bitRange>[0:0]</bitRange>
55091                  <access>read-write</access>
55092                </field>
55093                <field>
55094                  <name>CCE</name>
55095                  <description>Configuration Change Enable
550960= The CPU has no write access to the protected configuration registers
550971= The CPU has write access to the protected configuration registers (while CCCR.INIT = '1')</description>
55098                  <bitRange>[1:1]</bitRange>
55099                  <access>read-write</access>
55100                </field>
55101                <field>
55102                  <name>ASM</name>
55103                  <description>Restricted Operation Mode
55104Bit ASM can only be set by the Host when both CCE and INIT are set to '1'. The bit can be reset by
55105the Host at any time. For a description of the Restricted Operation Mode see Section 3.1.5.
551060= Normal CAN operation
551071= Restricted Operation Mode active</description>
55108                  <bitRange>[2:2]</bitRange>
55109                  <access>read-write</access>
55110                </field>
55111                <field>
55112                  <name>CSA</name>
55113                  <description>Clock Stop Acknowledge
551140= No clock stop acknowledged
551151= M_TTCAN may be set in power down by stopping m_ttcan_hclk and m_ttcan_cclk</description>
55116                  <bitRange>[3:3]</bitRange>
55117                  <access>read-write</access>
55118                </field>
55119                <field>
55120                  <name>CSR</name>
55121                  <description>Clock Stop Request, not supported by M_TTCAN use CTL.STOP_REQ at the group level instead.
551220= No clock stop is requested
551231= Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after
55124all pending transfer requests have been completed and the CAN bus reached idle.</description>
55125                  <bitRange>[4:4]</bitRange>
55126                  <access>read-write</access>
55127                </field>
55128                <field>
55129                  <name>MON_</name>
55130                  <description>Bus Monitoring Mode
55131Bit MON can only be set by the Host when both CCE and INIT are set to '1'. The bit can be reset by
55132the Host at any time.
551330= Bus Monitoring Mode is disabled
551341= Bus Monitoring Mode is enabled</description>
55135                  <bitRange>[5:5]</bitRange>
55136                  <access>read-write</access>
55137                </field>
55138                <field>
55139                  <name>DAR</name>
55140                  <description>Disable Automatic Retransmission
551410= Automatic retransmission of messages not transmitted successfully enabled
551421= Automatic retransmission disabled</description>
55143                  <bitRange>[6:6]</bitRange>
55144                  <access>read-write</access>
55145                </field>
55146                <field>
55147                  <name>TEST</name>
55148                  <description>Test Mode Enable
551490= Normal operation, register TEST holds reset values
551501= Test Mode, write access to register TEST enabled</description>
55151                  <bitRange>[7:7]</bitRange>
55152                  <access>read-write</access>
55153                </field>
55154                <field>
55155                  <name>FDOE</name>
55156                  <description>FD Operation Enable
551570= FD operation disabled
551581= FD operation enabled</description>
55159                  <bitRange>[8:8]</bitRange>
55160                  <access>read-write</access>
55161                </field>
55162                <field>
55163                  <name>BRSE</name>
55164                  <description>Bit Rate Switch Enable
551650= Bit rate switching for transmissions disabled
551661= Bit rate switching for transmissions enabled</description>
55167                  <bitRange>[9:9]</bitRange>
55168                  <access>read-write</access>
55169                </field>
55170                <field>
55171                  <name>PXHD</name>
55172                  <description>Protocol Exception Handling Disable
551730= Protocol exception handling enabled
551741= Protocol exception handling disabled</description>
55175                  <bitRange>[12:12]</bitRange>
55176                  <access>read-write</access>
55177                </field>
55178                <field>
55179                  <name>EFBI</name>
55180                  <description>Edge Filtering during Bus Integration
551810= Edge filtering disabled
551821= Two consecutive dominant tq required to detect an edge for hard synchronization</description>
55183                  <bitRange>[13:13]</bitRange>
55184                  <access>read-write</access>
55185                </field>
55186                <field>
55187                  <name>TXP</name>
55188                  <description>Transmit Pause
55189If this bit is set, the M_TTCAN pauses for two CAN bit times before starting the next transmission
55190after itself has successfully transmitted a frame (see Section 3.5).
551910= Transmit pause disabled
551921= Transmit pause enabled</description>
55193                  <bitRange>[14:14]</bitRange>
55194                  <access>read-write</access>
55195                </field>
55196                <field>
55197                  <name>NISO</name>
55198                  <description>Non ISO Operation
55199If this bit is set, the M_TTCAN uses the CAN FD frame format as specified by the Bosch CAN FD
55200Specification V1.0.
552010= CAN FD frame format according to ISO 11898-1:2015
552021= CAN FD frame format according to Bosch CAN FD Specification V1.0 addressing the non-ISO CAN FD</description>
55203                  <bitRange>[15:15]</bitRange>
55204                  <access>read-write</access>
55205                </field>
55206              </fields>
55207            </register>
55208            <register>
55209              <name>NBTP</name>
55210              <description>Nominal Bit Timing &amp; Prescaler Register</description>
55211              <addressOffset>0x1C</addressOffset>
55212              <size>32</size>
55213              <access>read-write</access>
55214              <resetValue>0x6000A03</resetValue>
55215              <resetMask>0xFFFFFF7F</resetMask>
55216              <fields>
55217                <field>
55218                  <name>NTSEG2</name>
55219                  <description>Nominal Time segment after sample point
552200x01-0x7F Valid values are 1 to 127. The actual interpretation by the hardware of this value is
55221such that one more than the programmed value is used.</description>
55222                  <bitRange>[6:0]</bitRange>
55223                  <access>read-write</access>
55224                </field>
55225                <field>
55226                  <name>NTSEG1</name>
55227                  <description>Nominal Time segment before sample point
552280x01-0xFF Valid values are 1 to 255. The actual interpretation by the hardware of this value is
55229such that one more than the programmed value is used.</description>
55230                  <bitRange>[15:8]</bitRange>
55231                  <access>read-write</access>
55232                </field>
55233                <field>
55234                  <name>NBRP</name>
55235                  <description>Nominal Bit Rate Prescaler
552360x000-0x1FFThe value by which the oscillator frequency is divided for generating the bit time
55237quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit
55238Rate Prescaler are 0 to 511. The actual interpretation by the hardware of this value is
55239such that one more than the value programmed here is used.</description>
55240                  <bitRange>[24:16]</bitRange>
55241                  <access>read-write</access>
55242                </field>
55243                <field>
55244                  <name>NSJW</name>
55245                  <description>Nominal (Re)Synchronization Jump Width
552460x00-0x7F Valid values are 0 to 127. The actual interpretation by the hardware of this value is
55247such that one more than the value programmed here is used.</description>
55248                  <bitRange>[31:25]</bitRange>
55249                  <access>read-write</access>
55250                </field>
55251              </fields>
55252            </register>
55253            <register>
55254              <name>TSCC</name>
55255              <description>Timestamp Counter Configuration</description>
55256              <addressOffset>0x20</addressOffset>
55257              <size>32</size>
55258              <access>read-write</access>
55259              <resetValue>0x0</resetValue>
55260              <resetMask>0xF0003</resetMask>
55261              <fields>
55262                <field>
55263                  <name>TSS</name>
55264                  <description>Timestamp Select, should always be set to external timestamp counter
5526500= Timestamp counter value always 0x0000
5526601= Timestamp counter value incremented according to TCP
5526710= External timestamp counter value used
5526811= Same as '00'</description>
55269                  <bitRange>[1:0]</bitRange>
55270                  <access>read-write</access>
55271                </field>
55272                <field>
55273                  <name>TCP</name>
55274                  <description>Timestamp Counter Prescaler (still used for TOCC)
552750x0-0xF Configures the timestamp and timeout counters time unit in multiples of CAN bit times
55276[1...16]. The actual interpretation by the hardware of this value is such that one more
55277than the value programmed here is used.</description>
55278                  <bitRange>[19:16]</bitRange>
55279                  <access>read-write</access>
55280                </field>
55281              </fields>
55282            </register>
55283            <register>
55284              <name>TSCV</name>
55285              <description>Timestamp Counter Value</description>
55286              <addressOffset>0x24</addressOffset>
55287              <size>32</size>
55288              <access>read-write</access>
55289              <resetValue>0x0</resetValue>
55290              <resetMask>0xFFFF</resetMask>
55291              <fields>
55292                <field>
55293                  <name>TSC</name>
55294                  <description>Timestamp Counter, not used for M_TTCAN
55295The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx).
55296When TSCC.TSS = '01', the Timestamp Counter is incremented in multiples of CAN bit times
55297[1...16] depending on the configuration of TSCC.TCP. A wrap around sets interrupt flag IR.TSW.
55298Write access resets the counter to zero. When TSCC.TSS = '10', TSC reflects the external
55299Timestamp Counter value. A write access has no impact.</description>
55300                  <bitRange>[15:0]</bitRange>
55301                  <access>read-write</access>
55302                </field>
55303              </fields>
55304            </register>
55305            <register>
55306              <name>TOCC</name>
55307              <description>Timeout Counter Configuration</description>
55308              <addressOffset>0x28</addressOffset>
55309              <size>32</size>
55310              <access>read-write</access>
55311              <resetValue>0xFFFF0000</resetValue>
55312              <resetMask>0xFFFF0007</resetMask>
55313              <fields>
55314                <field>
55315                  <name>ETOC</name>
55316                  <description>Enable Timeout Counter
553170= Timeout Counter disabled
553181= Timeout Counter enabled</description>
55319                  <bitRange>[0:0]</bitRange>
55320                  <access>read-write</access>
55321                </field>
55322                <field>
55323                  <name>TOS</name>
55324                  <description>Timeout Select
55325When operating in Continuous mode, a write to TOCV presets the counter to the value configured
55326by TOCC.TOP and continues down-counting. When the Timeout Counter is controlled by one of the
55327FIFOs, an empty FIFO presets the counter to the value configured by TOCC.TOP. Down-counting
55328is started when the first FIFO element is stored.
5532900= Continuous operation
5533001= Timeout controlled by Tx Event FIFO
5533110= Timeout controlled by Rx FIFO 0
5533211= Timeout controlled by Rx FIFO 1</description>
55333                  <bitRange>[2:1]</bitRange>
55334                  <access>read-write</access>
55335                </field>
55336                <field>
55337                  <name>TOP</name>
55338                  <description>Timeout Period
55339Start value of the Timeout Counter (down-counter). Configures the Timeout Period.</description>
55340                  <bitRange>[31:16]</bitRange>
55341                  <access>read-write</access>
55342                </field>
55343              </fields>
55344            </register>
55345            <register>
55346              <name>TOCV</name>
55347              <description>Timeout Counter Value</description>
55348              <addressOffset>0x2C</addressOffset>
55349              <size>32</size>
55350              <access>read-write</access>
55351              <resetValue>0xFFFF</resetValue>
55352              <resetMask>0xFFFF</resetMask>
55353              <fields>
55354                <field>
55355                  <name>TOC</name>
55356                  <description>Timeout Counter
55357The Timeout Counter is decremented in multiples of CAN bit times [1...16] depending on the
55358configuration of TSCC.TCP. When decremented to zero, interrupt flag IR.TOO is set and the
55359Timeout Counter is stopped. Start and reset/restart conditions are configured via TOCC.TOS.</description>
55360                  <bitRange>[15:0]</bitRange>
55361                  <access>read-write</access>
55362                </field>
55363              </fields>
55364            </register>
55365            <register>
55366              <name>ECR</name>
55367              <description>Error Counter Register</description>
55368              <addressOffset>0x40</addressOffset>
55369              <size>32</size>
55370              <access>read-only</access>
55371              <resetValue>0x0</resetValue>
55372              <resetMask>0xFFFFFF</resetMask>
55373              <fields>
55374                <field>
55375                  <name>TEC</name>
55376                  <description>Transmit Error Counter
55377Actual state of the Transmit Error Counter, values between 0 and 255</description>
55378                  <bitRange>[7:0]</bitRange>
55379                  <access>read-only</access>
55380                </field>
55381                <field>
55382                  <name>REC</name>
55383                  <description>Receive Error Counter
55384Actual state of the Receive Error Counter, values between 0 and 127</description>
55385                  <bitRange>[14:8]</bitRange>
55386                  <access>read-only</access>
55387                </field>
55388                <field>
55389                  <name>RP</name>
55390                  <description>Receive Error Passive
553910= The Receive Error Counter is below the error passive level of 128
553921= The Receive Error Counter has reached the error passive level of 128</description>
55393                  <bitRange>[15:15]</bitRange>
55394                  <access>read-only</access>
55395                </field>
55396                <field>
55397                  <name>CEL</name>
55398                  <description>CAN Error Logging
55399The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter
55400or the Receive Error Counter to be incremented. It is reset by read access to CEL. The counter stops
55401at 0xFF; the next increment of TEC or REC sets interrupt flag IR.ELO.</description>
55402                  <bitRange>[23:16]</bitRange>
55403                  <access>read-only</access>
55404                </field>
55405              </fields>
55406            </register>
55407            <register>
55408              <name>PSR</name>
55409              <description>Protocol Status Register</description>
55410              <addressOffset>0x44</addressOffset>
55411              <size>32</size>
55412              <access>read-only</access>
55413              <resetValue>0x707</resetValue>
55414              <resetMask>0x7F7FFF</resetMask>
55415              <fields>
55416                <field>
55417                  <name>LEC</name>
55418                  <description>Last Error Code,
55419Set on Read0
55420The LEC indicates the type of the last error to occur on the CAN bus. This field will be cleared to '0'
55421when a message has been transferred (reception or transmission) without error.
55422
554230= No Error: No error occurred since LEC has been reset by successful reception or transmission.
554241= Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed.
554252= Form Error: A fixed format part of a received frame has the wrong format.
554263= AckError: The message transmitted by the M_TTCAN was not acknowledged by another node.
554274= Bit1Error: During the transmission of a message (with the exception of the arbitration field),
55428the device wanted to send a recessive level (bit of logical value '1'), but the monitored bus
55429 value was dominant.
554305= Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or
55431overload flag), the device wanted to send a dominant level (data or identifier bit logical value
554320'), but the monitored bus value was recessive. During Bus_Off recovery this status is set
55433each time a sequence of 11 recessive bits has been monitored. This enables the CPU to
55434monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at
55435dominant or continuously disturbed).
554366= CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming
55437message does not match with the CRC calculated from the received data.
554387= NoChange: Any read access to the Protocol Status Register re-initializes the LEC to '7'.
55439When the LEC shows the value '7', no CAN bus event was detected since the last CPU read
55440access to the Protocol Status Register.</description>
55441                  <bitRange>[2:0]</bitRange>
55442                  <access>read-only</access>
55443                </field>
55444                <field>
55445                  <name>ACT</name>
55446                  <description>Activity
55447Monitors the module's CAN communication state.
5544800= Synchronizing - node is synchronizing on CAN communication
5544901= Idle - node is neither receiver nor transmitter
5545010= Receiver - node is operating as receiver
5545111= Transmitter - node is operating as transmitter</description>
55452                  <bitRange>[4:3]</bitRange>
55453                  <access>read-only</access>
55454                </field>
55455                <field>
55456                  <name>EP</name>
55457                  <description>Error Passive
554580= The M_CAN is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected
554591= The M_CAN is in the Error_Passive state</description>
55460                  <bitRange>[5:5]</bitRange>
55461                  <access>read-only</access>
55462                </field>
55463                <field>
55464                  <name>EW</name>
55465                  <description>Warning Status
554660= Both error counters are below the Error_Warning limit of 96
554671= At least one of error counter has reached the Error_Warning limit of 96</description>
55468                  <bitRange>[6:6]</bitRange>
55469                  <access>read-only</access>
55470                </field>
55471                <field>
55472                  <name>BO</name>
55473                  <description>Bus_Off Status
554740= The M_CAN is not Bus_Off
554751= The M_CAN is in Bus_Off state</description>
55476                  <bitRange>[7:7]</bitRange>
55477                  <access>read-only</access>
55478                </field>
55479                <field>
55480                  <name>DLEC</name>
55481                  <description>Data Phase Last Error Code
55482, Set on Read
55483Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for LEC. This field will be cleared to zero when a CAN FD format frame with its BRS flag set has been transferred (reception or transmission) without error.</description>
55484                  <bitRange>[10:8]</bitRange>
55485                  <access>read-only</access>
55486                </field>
55487                <field>
55488                  <name>RESI</name>
55489                  <description>ESI flag of last received CAN FD Message
55490, Reset on Read
55491This bit is set together with RFDF, independent of acceptance filtering.
554920= Last received CAN FD message did not have its ESI flag set
554931= Last received CAN FD message had its ESI flag set</description>
55494                  <bitRange>[11:11]</bitRange>
55495                  <access>read-only</access>
55496                </field>
55497                <field>
55498                  <name>RBRS</name>
55499                  <description>BRS flag of last received CAN FD Message
55500, Reset on Read
55501This bit is set together with RFDF, independent of acceptance filtering.
555020= Last received CAN FD message did not have its BRS flag set
555031= Last received CAN FD message had its BRS flag set</description>
55504                  <bitRange>[12:12]</bitRange>
55505                  <access>read-only</access>
55506                </field>
55507                <field>
55508                  <name>RFDF</name>
55509                  <description>Received a CAN FD Message
55510, Reset on Read
55511This bit is set independent of acceptance filtering.
555120= Since this bit was reset by the CPU, no CAN FD message has been received
555131= Message in CAN FD format with FDF flag set has been received</description>
55514                  <bitRange>[13:13]</bitRange>
55515                  <access>read-only</access>
55516                </field>
55517                <field>
55518                  <name>PXE</name>
55519                  <description>Protocol Exception Event
55520, Reset on Read
555210= No protocol exception event occurred since last read access
555221= Protocol exception event occurred</description>
55523                  <bitRange>[14:14]</bitRange>
55524                  <access>read-only</access>
55525                </field>
55526                <field>
55527                  <name>TDCV</name>
55528                  <description>Transmitter Delay Compensation Value
555290x00-0x7F Position of the secondary sample point, defined by the sum of the measured delay from m_can_tx to m_can_rx and TDCR.TDCO. The SSP position is, in the data phase, the number of mtq between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq.</description>
55530                  <bitRange>[22:16]</bitRange>
55531                  <access>read-only</access>
55532                </field>
55533              </fields>
55534            </register>
55535            <register>
55536              <name>TDCR</name>
55537              <description>Transmitter Delay Compensation Register</description>
55538              <addressOffset>0x48</addressOffset>
55539              <size>32</size>
55540              <access>read-write</access>
55541              <resetValue>0x0</resetValue>
55542              <resetMask>0x7F7F</resetMask>
55543              <fields>
55544                <field>
55545                  <name>TDCF</name>
55546                  <description>Transmitter Delay Compensation Filter Window Length
555470x00-0x7F Defines the minimum value for the SSP position, dominant edges on m_ttcan_rx
55548that would result in an earlier SSP position are ignored for transmitter delay measurement.
55549The feature is enabled when TDCF is configured to a value greater than
55550TDCO. Valid values are 0 to 127 mtq</description>
55551                  <bitRange>[6:0]</bitRange>
55552                  <access>read-write</access>
55553                </field>
55554                <field>
55555                  <name>TDCO</name>
55556                  <description>Transmitter Delay Compensation Offset
555570x00-0x7F Offset value defining the distance between the measured delay from m_ttcan_tx to
55558m_ttcan_rx and the secondary sample point. Valid values are 0 to 127 mtq.</description>
55559                  <bitRange>[14:8]</bitRange>
55560                  <access>read-write</access>
55561                </field>
55562              </fields>
55563            </register>
55564            <register>
55565              <name>IR</name>
55566              <description>Interrupt Register</description>
55567              <addressOffset>0x50</addressOffset>
55568              <size>32</size>
55569              <access>read-write</access>
55570              <resetValue>0x0</resetValue>
55571              <resetMask>0x3FFFFFFF</resetMask>
55572              <fields>
55573                <field>
55574                  <name>RF0N</name>
55575                  <description>Rx FIFO 0 New Message
555760= No new message written to Rx FIFO 0
555771= New message written to Rx FIFO 0</description>
55578                  <bitRange>[0:0]</bitRange>
55579                  <access>read-write</access>
55580                </field>
55581                <field>
55582                  <name>RF0W</name>
55583                  <description>Rx FIFO 0 Watermark Reached
555840= Rx FIFO 0 fill level below watermark
555851= Rx FIFO 0 fill level reached watermark</description>
55586                  <bitRange>[1:1]</bitRange>
55587                  <access>read-write</access>
55588                </field>
55589                <field>
55590                  <name>RF0F</name>
55591                  <description>Rx FIFO 0 Full
555920= Rx FIFO 0 not full
555931= Rx FIFO 0 full</description>
55594                  <bitRange>[2:2]</bitRange>
55595                  <access>read-write</access>
55596                </field>
55597                <field>
55598                  <name>RF0L_</name>
55599                  <description>Rx FIFO 0 Message Lost
556000= No Rx FIFO 0 message lost
556011= Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero</description>
55602                  <bitRange>[3:3]</bitRange>
55603                  <access>read-write</access>
55604                </field>
55605                <field>
55606                  <name>RF1N</name>
55607                  <description>Rx FIFO 1 New Message
556080= No new message written to Rx FIFO 1
556091= New message written to Rx FIFO 1</description>
55610                  <bitRange>[4:4]</bitRange>
55611                  <access>read-write</access>
55612                </field>
55613                <field>
55614                  <name>RF1W</name>
55615                  <description>Rx FIFO 1 Watermark Reached
556160= Rx FIFO 1 fill level below watermark
556171= Rx FIFO 1 fill level reached watermark</description>
55618                  <bitRange>[5:5]</bitRange>
55619                  <access>read-write</access>
55620                </field>
55621                <field>
55622                  <name>RF1F</name>
55623                  <description>Rx FIFO 1 Full
556240= Rx FIFO 1 not full
556251= Rx FIFO 1 full</description>
55626                  <bitRange>[6:6]</bitRange>
55627                  <access>read-write</access>
55628                </field>
55629                <field>
55630                  <name>RF1L_</name>
55631                  <description>Rx FIFO 1 Message Lost
556320= No Rx FIFO 1 message lost
556331= Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero</description>
55634                  <bitRange>[7:7]</bitRange>
55635                  <access>read-write</access>
55636                </field>
55637                <field>
55638                  <name>HPM</name>
55639                  <description>High Priority Message
556400= No high priority message received
556411= High priority message received</description>
55642                  <bitRange>[8:8]</bitRange>
55643                  <access>read-write</access>
55644                </field>
55645                <field>
55646                  <name>TC</name>
55647                  <description>Transmission Completed
556480= No transmission completed
556491= Transmission completed</description>
55650                  <bitRange>[9:9]</bitRange>
55651                  <access>read-write</access>
55652                </field>
55653                <field>
55654                  <name>TCF</name>
55655                  <description>Transmission Cancellation Finished
556560= No transmission cancellation finished
556571= Transmission cancellation finished</description>
55658                  <bitRange>[10:10]</bitRange>
55659                  <access>read-write</access>
55660                </field>
55661                <field>
55662                  <name>TFE</name>
55663                  <description>Tx FIFO Empty
556640= Tx FIFO non-empty
556651= Tx FIFO empty</description>
55666                  <bitRange>[11:11]</bitRange>
55667                  <access>read-write</access>
55668                </field>
55669                <field>
55670                  <name>TEFN</name>
55671                  <description>Tx Event FIFO New Entry
556720= Tx Event FIFO unchanged
556731= Tx Handler wrote Tx Event FIFO element</description>
55674                  <bitRange>[12:12]</bitRange>
55675                  <access>read-write</access>
55676                </field>
55677                <field>
55678                  <name>TEFW</name>
55679                  <description>Tx Event FIFO Watermark Reached
556800= Tx Event FIFO fill level below watermark
556811= Tx Event FIFO fill level reached watermark</description>
55682                  <bitRange>[13:13]</bitRange>
55683                  <access>read-write</access>
55684                </field>
55685                <field>
55686                  <name>TEFF</name>
55687                  <description>Tx Event FIFO Full
556880= Tx Event FIFO not full
556891= Tx Event FIFO full</description>
55690                  <bitRange>[14:14]</bitRange>
55691                  <access>read-write</access>
55692                </field>
55693                <field>
55694                  <name>TEFL_</name>
55695                  <description>Tx Event FIFO Element Lost
556960= No Tx Event FIFO element lost
556971= Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero</description>
55698                  <bitRange>[15:15]</bitRange>
55699                  <access>read-write</access>
55700                </field>
55701                <field>
55702                  <name>TSW</name>
55703                  <description>Timestamp Wraparound
557040= No timestamp counter wrap-around
557051= Timestamp counter wrapped around</description>
55706                  <bitRange>[16:16]</bitRange>
55707                  <access>read-write</access>
55708                </field>
55709                <field>
55710                  <name>MRAF</name>
55711                  <description>Message RAM Access Failure
55712The flag is set, when the Rx Handler
55713- has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or message storage is aborted and the Rx Handler starts processing of the following message.
55714- was not able to write a message to the Message RAM. In this case message storage is aborted.
55715In both cases the FIFO put index is not updated resp. the New Data flag for a dedicated Rx Buffer is not set, a partly stored message is overwritten when the next message is stored to this location.
55716The flag is also set when the Tx Handler was not able to read a message from the Message RAM
55717in time. In this case message transmission is aborted. In case of a Tx Handler access failure the
55718M_TTCAN is switched into Restricted Operation Mode (see Section 3.1.5). To leave Restricted
55719Operation Mode, the Host CPU has to reset CCCR.ASM.
557200= No Message RAM access failure occurred
557211= Message RAM access failure occurred</description>
55722                  <bitRange>[17:17]</bitRange>
55723                  <access>read-write</access>
55724                </field>
55725                <field>
55726                  <name>TOO</name>
55727                  <description>Timeout Occurred
557280= No timeout
557291= Timeout reached</description>
55730                  <bitRange>[18:18]</bitRange>
55731                  <access>read-write</access>
55732                </field>
55733                <field>
55734                  <name>DRX</name>
55735                  <description>Message stored to Dedicated Rx Buffer
55736The flag is set whenever a received message has been stored into a dedicated Rx Buffer.
557370= No Rx Buffer updated
557381= At least one received message stored into a Rx Buffer</description>
55739                  <bitRange>[19:19]</bitRange>
55740                  <access>read-write</access>
55741                </field>
55742                <field>
55743                  <name>BEC</name>
55744                  <description>M_TTCAN reports correctable ECC fault to the generic fault structure, this bit always reads as 0.
55745Bit Error Corrected
55746Message RAM bit error detected and corrected. Controlled by input signal m_ttcan_aeim_berr[0]
55747generated by an optional external parity / ECC logic attached to the Message RAM.
557480= No bit error detected when reading from Message RAM
557491= Bit error detected and corrected (e.g. ECC)</description>
55750                  <bitRange>[20:20]</bitRange>
55751                  <access>read-write</access>
55752                </field>
55753                <field>
55754                  <name>BEU</name>
55755                  <description>Bit Error Uncorrected
55756Message RAM bit error detected, uncorrected. Controlled by input signal m_ttcan_aeim_berr[1]
55757generated by an optional external parity / ECC logic attached to the Message RAM. An uncorrected
55758Message RAM bit error sets CCCR.INIT to '1'. This is done to avoid transmission of corrupted data.
557590= No bit error detected when reading from Message RAM
557601= Bit error detected, uncorrected (e.g. parity logic)</description>
55761                  <bitRange>[21:21]</bitRange>
55762                  <access>read-write</access>
55763                </field>
55764                <field>
55765                  <name>ELO</name>
55766                  <description>Error Logging Overflow
557670= CAN Error Logging Counter did not overflow
557681= Overflow of CAN Error Logging Counter occurred</description>
55769                  <bitRange>[22:22]</bitRange>
55770                  <access>read-write</access>
55771                </field>
55772                <field>
55773                  <name>EP_</name>
55774                  <description>Error Passive
557750= Error_Passive status unchanged
557761= Error_Passive status changed</description>
55777                  <bitRange>[23:23]</bitRange>
55778                  <access>read-write</access>
55779                </field>
55780                <field>
55781                  <name>EW_</name>
55782                  <description>Warning Status
557830= Error_Warning status unchanged
557841= Error_Warning status changed</description>
55785                  <bitRange>[24:24]</bitRange>
55786                  <access>read-write</access>
55787                </field>
55788                <field>
55789                  <name>BO_</name>
55790                  <description>Bus_Off Status
557910= Bus_Off status unchanged
557921= Bus_Off status changed</description>
55793                  <bitRange>[25:25]</bitRange>
55794                  <access>read-write</access>
55795                </field>
55796                <field>
55797                  <name>WDI</name>
55798                  <description>Watchdog Interrupt
557990= No Message RAM Watchdog event occurred
558001= Message RAM Watchdog event due to missing READY</description>
55801                  <bitRange>[26:26]</bitRange>
55802                  <access>read-write</access>
55803                </field>
55804                <field>
55805                  <name>PEA</name>
55806                  <description>Protocol Error in Arbitration Phase (Nominal Bit Time is used)
558070= No protocol error in arbitration phase
558081= Protocol error in arbitration phase detected (PSR.LEC != 0,7)</description>
55809                  <bitRange>[27:27]</bitRange>
55810                  <access>read-write</access>
55811                </field>
55812                <field>
55813                  <name>PED</name>
55814                  <description>Protocol Error in Data Phase (Data Bit Time is used)
558150= No protocol error in data phase
558161= Protocol error in data phase detected (PSR.DLEC != 0,7)</description>
55817                  <bitRange>[28:28]</bitRange>
55818                  <access>read-write</access>
55819                </field>
55820                <field>
55821                  <name>ARA</name>
55822                  <description>N/A</description>
55823                  <bitRange>[29:29]</bitRange>
55824                  <access>read-write</access>
55825                </field>
55826              </fields>
55827            </register>
55828            <register>
55829              <name>IE</name>
55830              <description>Interrupt Enable</description>
55831              <addressOffset>0x54</addressOffset>
55832              <size>32</size>
55833              <access>read-write</access>
55834              <resetValue>0x0</resetValue>
55835              <resetMask>0x3FFFFFFF</resetMask>
55836              <fields>
55837                <field>
55838                  <name>RF0NE</name>
55839                  <description>Rx FIFO 0 New Message Interrupt Enable</description>
55840                  <bitRange>[0:0]</bitRange>
55841                  <access>read-write</access>
55842                </field>
55843                <field>
55844                  <name>RF0WE</name>
55845                  <description>Rx FIFO 0 Watermark Reached Interrupt Enable</description>
55846                  <bitRange>[1:1]</bitRange>
55847                  <access>read-write</access>
55848                </field>
55849                <field>
55850                  <name>RF0FE</name>
55851                  <description>Rx FIFO 0 Full Interrupt Enable</description>
55852                  <bitRange>[2:2]</bitRange>
55853                  <access>read-write</access>
55854                </field>
55855                <field>
55856                  <name>RF0LE</name>
55857                  <description>Rx FIFO 0 Message Lost Interrupt Enable</description>
55858                  <bitRange>[3:3]</bitRange>
55859                  <access>read-write</access>
55860                </field>
55861                <field>
55862                  <name>RF1NE</name>
55863                  <description>Rx FIFO 1 New Message Interrupt Enable</description>
55864                  <bitRange>[4:4]</bitRange>
55865                  <access>read-write</access>
55866                </field>
55867                <field>
55868                  <name>RF1WE</name>
55869                  <description>Rx FIFO 1 Watermark Reached Interrupt Enable</description>
55870                  <bitRange>[5:5]</bitRange>
55871                  <access>read-write</access>
55872                </field>
55873                <field>
55874                  <name>RF1FE</name>
55875                  <description>Rx FIFO 1 Full Interrupt Enable</description>
55876                  <bitRange>[6:6]</bitRange>
55877                  <access>read-write</access>
55878                </field>
55879                <field>
55880                  <name>RF1LE</name>
55881                  <description>Rx FIFO 1 Message Lost Interrupt Enable</description>
55882                  <bitRange>[7:7]</bitRange>
55883                  <access>read-write</access>
55884                </field>
55885                <field>
55886                  <name>HPME</name>
55887                  <description>High Priority Message Interrupt Enable</description>
55888                  <bitRange>[8:8]</bitRange>
55889                  <access>read-write</access>
55890                </field>
55891                <field>
55892                  <name>TCE</name>
55893                  <description>Transmission Completed Interrupt Enable</description>
55894                  <bitRange>[9:9]</bitRange>
55895                  <access>read-write</access>
55896                </field>
55897                <field>
55898                  <name>TCFE</name>
55899                  <description>Transmission Cancellation Finished Interrupt Enable</description>
55900                  <bitRange>[10:10]</bitRange>
55901                  <access>read-write</access>
55902                </field>
55903                <field>
55904                  <name>TFEE</name>
55905                  <description>Tx FIFO Empty Interrupt Enable</description>
55906                  <bitRange>[11:11]</bitRange>
55907                  <access>read-write</access>
55908                </field>
55909                <field>
55910                  <name>TEFNE</name>
55911                  <description>Tx Event FIDO New Entry Interrupt Enable</description>
55912                  <bitRange>[12:12]</bitRange>
55913                  <access>read-write</access>
55914                </field>
55915                <field>
55916                  <name>TEFWE</name>
55917                  <description>Tx Event FIFO Watermark Reached Interrupt Enable</description>
55918                  <bitRange>[13:13]</bitRange>
55919                  <access>read-write</access>
55920                </field>
55921                <field>
55922                  <name>TEFFE</name>
55923                  <description>Tx Event FIFO Full Interrupt Enable</description>
55924                  <bitRange>[14:14]</bitRange>
55925                  <access>read-write</access>
55926                </field>
55927                <field>
55928                  <name>TEFLE</name>
55929                  <description>Tx Event FIFO Event Lost Interrupt Enable</description>
55930                  <bitRange>[15:15]</bitRange>
55931                  <access>read-write</access>
55932                </field>
55933                <field>
55934                  <name>TSWE</name>
55935                  <description>Timestamp Wraparound Interrupt Enable</description>
55936                  <bitRange>[16:16]</bitRange>
55937                  <access>read-write</access>
55938                </field>
55939                <field>
55940                  <name>MRAFE</name>
55941                  <description>Message RAM Access Failure Interrupt Enable</description>
55942                  <bitRange>[17:17]</bitRange>
55943                  <access>read-write</access>
55944                </field>
55945                <field>
55946                  <name>TOOE</name>
55947                  <description>Timeout Occurred Interrupt Enable</description>
55948                  <bitRange>[18:18]</bitRange>
55949                  <access>read-write</access>
55950                </field>
55951                <field>
55952                  <name>DRXE</name>
55953                  <description>Message stored to Dedicated Rx Buffer Interrupt Enable</description>
55954                  <bitRange>[19:19]</bitRange>
55955                  <access>read-write</access>
55956                </field>
55957                <field>
55958                  <name>BECE</name>
55959                  <description>Bit Error Corrected Interrupt Enable (not used in M_TTCAN)</description>
55960                  <bitRange>[20:20]</bitRange>
55961                  <access>read-write</access>
55962                </field>
55963                <field>
55964                  <name>BEUE</name>
55965                  <description>Bit Error Uncorrected Interrupt Enable</description>
55966                  <bitRange>[21:21]</bitRange>
55967                  <access>read-write</access>
55968                </field>
55969                <field>
55970                  <name>ELOE</name>
55971                  <description>Error Logging Overflow Interrupt Enable</description>
55972                  <bitRange>[22:22]</bitRange>
55973                  <access>read-write</access>
55974                </field>
55975                <field>
55976                  <name>EPE</name>
55977                  <description>Error Passive Interrupt Enable</description>
55978                  <bitRange>[23:23]</bitRange>
55979                  <access>read-write</access>
55980                </field>
55981                <field>
55982                  <name>EWE</name>
55983                  <description>Warning Status Interrupt Enable</description>
55984                  <bitRange>[24:24]</bitRange>
55985                  <access>read-write</access>
55986                </field>
55987                <field>
55988                  <name>BOE</name>
55989                  <description>Bus_Off Status Interrupt Enable</description>
55990                  <bitRange>[25:25]</bitRange>
55991                  <access>read-write</access>
55992                </field>
55993                <field>
55994                  <name>WDIE</name>
55995                  <description>Watchdog Interrupt Enable</description>
55996                  <bitRange>[26:26]</bitRange>
55997                  <access>read-write</access>
55998                </field>
55999                <field>
56000                  <name>PEAE</name>
56001                  <description>Protocol Error in Arbitration Phase Enable</description>
56002                  <bitRange>[27:27]</bitRange>
56003                  <access>read-write</access>
56004                </field>
56005                <field>
56006                  <name>PEDE</name>
56007                  <description>Protocol Error in Data Phase Enable</description>
56008                  <bitRange>[28:28]</bitRange>
56009                  <access>read-write</access>
56010                </field>
56011                <field>
56012                  <name>ARAE</name>
56013                  <description>N/A</description>
56014                  <bitRange>[29:29]</bitRange>
56015                  <access>read-write</access>
56016                </field>
56017              </fields>
56018            </register>
56019            <register>
56020              <name>ILS</name>
56021              <description>Interrupt Line Select</description>
56022              <addressOffset>0x58</addressOffset>
56023              <size>32</size>
56024              <access>read-write</access>
56025              <resetValue>0x0</resetValue>
56026              <resetMask>0x3FFFFFFF</resetMask>
56027              <fields>
56028                <field>
56029                  <name>RF0NL</name>
56030                  <description>Rx FIFO 0 New Message Interrupt Line</description>
56031                  <bitRange>[0:0]</bitRange>
56032                  <access>read-write</access>
56033                </field>
56034                <field>
56035                  <name>RF0WL</name>
56036                  <description>Rx FIFO 0 Watermark Reached Interrupt Line</description>
56037                  <bitRange>[1:1]</bitRange>
56038                  <access>read-write</access>
56039                </field>
56040                <field>
56041                  <name>RF0FL</name>
56042                  <description>Rx FIFO 0 Full Interrupt Line</description>
56043                  <bitRange>[2:2]</bitRange>
56044                  <access>read-write</access>
56045                </field>
56046                <field>
56047                  <name>RF0LL</name>
56048                  <description>Rx FIFO 0 Message Lost Interrupt Line</description>
56049                  <bitRange>[3:3]</bitRange>
56050                  <access>read-write</access>
56051                </field>
56052                <field>
56053                  <name>RF1NL</name>
56054                  <description>Rx FIFO 1 New Message Interrupt Line</description>
56055                  <bitRange>[4:4]</bitRange>
56056                  <access>read-write</access>
56057                </field>
56058                <field>
56059                  <name>RF1WL</name>
56060                  <description>Rx FIFO 1 Watermark Reached Interrupt Line</description>
56061                  <bitRange>[5:5]</bitRange>
56062                  <access>read-write</access>
56063                </field>
56064                <field>
56065                  <name>RF1FL</name>
56066                  <description>Rx FIFO 1 Full Interrupt Line</description>
56067                  <bitRange>[6:6]</bitRange>
56068                  <access>read-write</access>
56069                </field>
56070                <field>
56071                  <name>RF1LL</name>
56072                  <description>Rx FIFO 1 Message Lost Interrupt Line</description>
56073                  <bitRange>[7:7]</bitRange>
56074                  <access>read-write</access>
56075                </field>
56076                <field>
56077                  <name>HPML</name>
56078                  <description>High Priority Message Interrupt Line</description>
56079                  <bitRange>[8:8]</bitRange>
56080                  <access>read-write</access>
56081                </field>
56082                <field>
56083                  <name>TCL</name>
56084                  <description>Transmission Completed Interrupt Line</description>
56085                  <bitRange>[9:9]</bitRange>
56086                  <access>read-write</access>
56087                </field>
56088                <field>
56089                  <name>TCFL</name>
56090                  <description>Transmission Cancellation Finished Interrupt Line</description>
56091                  <bitRange>[10:10]</bitRange>
56092                  <access>read-write</access>
56093                </field>
56094                <field>
56095                  <name>TFEL</name>
56096                  <description>Tx FIFO Empty Interrupt Line</description>
56097                  <bitRange>[11:11]</bitRange>
56098                  <access>read-write</access>
56099                </field>
56100                <field>
56101                  <name>TEFNL</name>
56102                  <description>Tx Event FIFO New Entry Interrupt Line</description>
56103                  <bitRange>[12:12]</bitRange>
56104                  <access>read-write</access>
56105                </field>
56106                <field>
56107                  <name>TEFWL</name>
56108                  <description>Tx Event FIFO Watermark Reached Interrupt Line</description>
56109                  <bitRange>[13:13]</bitRange>
56110                  <access>read-write</access>
56111                </field>
56112                <field>
56113                  <name>TEFFL</name>
56114                  <description>Tx Event FIFO Full Interrupt Line</description>
56115                  <bitRange>[14:14]</bitRange>
56116                  <access>read-write</access>
56117                </field>
56118                <field>
56119                  <name>TEFLL</name>
56120                  <description>Tx Event FIFO Event Lost Interrupt Line</description>
56121                  <bitRange>[15:15]</bitRange>
56122                  <access>read-write</access>
56123                </field>
56124                <field>
56125                  <name>TSWL</name>
56126                  <description>Timestamp Wraparound Interrupt Line</description>
56127                  <bitRange>[16:16]</bitRange>
56128                  <access>read-write</access>
56129                </field>
56130                <field>
56131                  <name>MRAFL</name>
56132                  <description>Message RAM Access Failure Interrupt Line</description>
56133                  <bitRange>[17:17]</bitRange>
56134                  <access>read-write</access>
56135                </field>
56136                <field>
56137                  <name>TOOL</name>
56138                  <description>Timeout Occurred Interrupt Line</description>
56139                  <bitRange>[18:18]</bitRange>
56140                  <access>read-write</access>
56141                </field>
56142                <field>
56143                  <name>DRXL</name>
56144                  <description>Message stored to Dedicated Rx Buffer Interrupt Line</description>
56145                  <bitRange>[19:19]</bitRange>
56146                  <access>read-write</access>
56147                </field>
56148                <field>
56149                  <name>BECL</name>
56150                  <description>Bit Error Corrected Interrupt Line  (not used in M_TTCAN)</description>
56151                  <bitRange>[20:20]</bitRange>
56152                  <access>read-write</access>
56153                </field>
56154                <field>
56155                  <name>BEUL</name>
56156                  <description>Bit Error Uncorrected Interrupt Line</description>
56157                  <bitRange>[21:21]</bitRange>
56158                  <access>read-write</access>
56159                </field>
56160                <field>
56161                  <name>ELOL</name>
56162                  <description>Error Logging Overflow Interrupt Line</description>
56163                  <bitRange>[22:22]</bitRange>
56164                  <access>read-write</access>
56165                </field>
56166                <field>
56167                  <name>EPL</name>
56168                  <description>Error Passive Interrupt Line</description>
56169                  <bitRange>[23:23]</bitRange>
56170                  <access>read-write</access>
56171                </field>
56172                <field>
56173                  <name>EWL</name>
56174                  <description>Warning Status Interrupt Line</description>
56175                  <bitRange>[24:24]</bitRange>
56176                  <access>read-write</access>
56177                </field>
56178                <field>
56179                  <name>BOL</name>
56180                  <description>Bus_Off Status Interrupt Line</description>
56181                  <bitRange>[25:25]</bitRange>
56182                  <access>read-write</access>
56183                </field>
56184                <field>
56185                  <name>WDIL</name>
56186                  <description>Watchdog Interrupt Line</description>
56187                  <bitRange>[26:26]</bitRange>
56188                  <access>read-write</access>
56189                </field>
56190                <field>
56191                  <name>PEAL</name>
56192                  <description>Protocol Error in Arbitration Phase Line</description>
56193                  <bitRange>[27:27]</bitRange>
56194                  <access>read-write</access>
56195                </field>
56196                <field>
56197                  <name>PEDL</name>
56198                  <description>Protocol Error in Data Phase Line</description>
56199                  <bitRange>[28:28]</bitRange>
56200                  <access>read-write</access>
56201                </field>
56202                <field>
56203                  <name>ARAL</name>
56204                  <description>N/A</description>
56205                  <bitRange>[29:29]</bitRange>
56206                  <access>read-write</access>
56207                </field>
56208              </fields>
56209            </register>
56210            <register>
56211              <name>ILE</name>
56212              <description>Interrupt Line Enable</description>
56213              <addressOffset>0x5C</addressOffset>
56214              <size>32</size>
56215              <access>read-write</access>
56216              <resetValue>0x0</resetValue>
56217              <resetMask>0x3</resetMask>
56218              <fields>
56219                <field>
56220                  <name>EINT0</name>
56221                  <description>Enable Interrupt Line 0
562220= Interrupt line m_ttcan_int0 disabled
562231= Interrupt line m_ttcan_int0 enabled</description>
56224                  <bitRange>[0:0]</bitRange>
56225                  <access>read-write</access>
56226                </field>
56227                <field>
56228                  <name>EINT1</name>
56229                  <description>Enable Interrupt Line 1
562300= Interrupt line m_ttcan_int1 disabled
562311= Interrupt line m_ttcan_int1 enabled</description>
56232                  <bitRange>[1:1]</bitRange>
56233                  <access>read-write</access>
56234                </field>
56235              </fields>
56236            </register>
56237            <register>
56238              <name>GFC</name>
56239              <description>Global Filter Configuration</description>
56240              <addressOffset>0x80</addressOffset>
56241              <size>32</size>
56242              <access>read-write</access>
56243              <resetValue>0x0</resetValue>
56244              <resetMask>0x3F</resetMask>
56245              <fields>
56246                <field>
56247                  <name>RRFE</name>
56248                  <description>Reject Remote Frames Extended
562490= Filter remote frames with 29-bit extended IDs
562501= Reject all remote frames with 29-bit extended IDs</description>
56251                  <bitRange>[0:0]</bitRange>
56252                  <access>read-write</access>
56253                </field>
56254                <field>
56255                  <name>RRFS</name>
56256                  <description>Reject Remote Frames Standard
562570= Filter remote frames with 11-bit standard IDs
562581= Reject all remote frames with 11-bit standard IDs</description>
56259                  <bitRange>[1:1]</bitRange>
56260                  <access>read-write</access>
56261                </field>
56262                <field>
56263                  <name>ANFE</name>
56264                  <description>Accept Non-matching Frames Extended
56265Defines how received messages with 29-bit IDs that do not match any element of the filter list are
56266treated.
5626700= Accept in Rx FIFO 0
5626801= Accept in Rx FIFO 1
5626910= Reject
5627011= Reject</description>
56271                  <bitRange>[3:2]</bitRange>
56272                  <access>read-write</access>
56273                </field>
56274                <field>
56275                  <name>ANFS</name>
56276                  <description>Accept Non-matching Frames Standard
56277Defines how received messages with 11-bit IDs that do not match any element of the filter list are
56278treated.
5627900= Accept in Rx FIFO 0
5628001= Accept in Rx FIFO 1
5628110= Reject
5628211= Reject</description>
56283                  <bitRange>[5:4]</bitRange>
56284                  <access>read-write</access>
56285                </field>
56286              </fields>
56287            </register>
56288            <register>
56289              <name>SIDFC</name>
56290              <description>Standard ID Filter Configuration</description>
56291              <addressOffset>0x84</addressOffset>
56292              <size>32</size>
56293              <access>read-write</access>
56294              <resetValue>0x0</resetValue>
56295              <resetMask>0xFFFFFC</resetMask>
56296              <fields>
56297                <field>
56298                  <name>FLSSA</name>
56299                  <description>Filter List Standard Start Address
56300Start address of standard Message ID filter list (32-bit word address, see Figure 2).</description>
56301                  <bitRange>[15:2]</bitRange>
56302                  <access>read-write</access>
56303                </field>
56304                <field>
56305                  <name>LSS</name>
56306                  <description>List Size Standard
563070= No standard Message ID filter
563081-128= Number of standard Message ID filter elements
56309128= Values greater than 128 are interpreted as 128</description>
56310                  <bitRange>[23:16]</bitRange>
56311                  <access>read-write</access>
56312                </field>
56313              </fields>
56314            </register>
56315            <register>
56316              <name>XIDFC</name>
56317              <description>Extended ID Filter Configuration</description>
56318              <addressOffset>0x88</addressOffset>
56319              <size>32</size>
56320              <access>read-write</access>
56321              <resetValue>0x0</resetValue>
56322              <resetMask>0x7FFFFC</resetMask>
56323              <fields>
56324                <field>
56325                  <name>FLESA</name>
56326                  <description>Filter List Extended Start Address
56327Start address of extended Message ID filter list (32-bit word address, see Figure 2).</description>
56328                  <bitRange>[15:2]</bitRange>
56329                  <access>read-write</access>
56330                </field>
56331                <field>
56332                  <name>LSE</name>
56333                  <description>List Size Extended
563340= No extended Message ID filter
563351-64= Number of extended Message ID filter elements
5633664= Values greater than 64 are interpreted as 64</description>
56337                  <bitRange>[22:16]</bitRange>
56338                  <access>read-write</access>
56339                </field>
56340              </fields>
56341            </register>
56342            <register>
56343              <name>XIDAM</name>
56344              <description>Extended ID AND Mask</description>
56345              <addressOffset>0x90</addressOffset>
56346              <size>32</size>
56347              <access>read-write</access>
56348              <resetValue>0x1FFFFFFF</resetValue>
56349              <resetMask>0x1FFFFFFF</resetMask>
56350              <fields>
56351                <field>
56352                  <name>EIDM</name>
56353                  <description>Extended ID Mask
56354For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message
56355ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all
56356bits set to one the mask is not active.</description>
56357                  <bitRange>[28:0]</bitRange>
56358                  <access>read-write</access>
56359                </field>
56360              </fields>
56361            </register>
56362            <register>
56363              <name>HPMS</name>
56364              <description>High Priority Message Status</description>
56365              <addressOffset>0x94</addressOffset>
56366              <size>32</size>
56367              <access>read-only</access>
56368              <resetValue>0x0</resetValue>
56369              <resetMask>0xFFFF</resetMask>
56370              <fields>
56371                <field>
56372                  <name>BIDX</name>
56373                  <description>Buffer Index
56374Index of Rx FIFO element to which the message was stored. Only valid when MSI[1] = '1'.</description>
56375                  <bitRange>[5:0]</bitRange>
56376                  <access>read-only</access>
56377                </field>
56378                <field>
56379                  <name>MSI</name>
56380                  <description>Message Storage Indicator
5638100= No FIFO selected
5638201= FIFO message lost
5638310= Message stored in FIFO 0
5638411= Message stored in FIFO 1</description>
56385                  <bitRange>[7:6]</bitRange>
56386                  <access>read-only</access>
56387                </field>
56388                <field>
56389                  <name>FIDX</name>
56390                  <description>Filter Index
56391Index of matching filter element. Range is 0 to SIDFC.LSS - 1 resp. XIDFC.LSE - 1.</description>
56392                  <bitRange>[14:8]</bitRange>
56393                  <access>read-only</access>
56394                </field>
56395                <field>
56396                  <name>FLST</name>
56397                  <description>Filter List
56398Indicates the filter list of the matching filter element.
563990= Standard Filter List
564001= Extended Filter List</description>
56401                  <bitRange>[15:15]</bitRange>
56402                  <access>read-only</access>
56403                </field>
56404              </fields>
56405            </register>
56406            <register>
56407              <name>NDAT1</name>
56408              <description>New Data 1</description>
56409              <addressOffset>0x98</addressOffset>
56410              <size>32</size>
56411              <access>read-write</access>
56412              <resetValue>0x0</resetValue>
56413              <resetMask>0xFFFFFFFF</resetMask>
56414              <fields>
56415                <field>
56416                  <name>ND</name>
56417                  <description>New Data
56418The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective
56419Rx Buffer has been updated from a received frame. The flags remain set until the Host clears them.
56420A flag is cleared by writing a '1' to the corresponding bit position. Writing a '0' has no effect. A hard
56421reset will clear the register.
564220= Rx Buffer not updated
564231= Rx Buffer updated from new message</description>
56424                  <bitRange>[31:0]</bitRange>
56425                  <access>read-write</access>
56426                </field>
56427              </fields>
56428            </register>
56429            <register>
56430              <name>NDAT2</name>
56431              <description>New Data 2</description>
56432              <addressOffset>0x9C</addressOffset>
56433              <size>32</size>
56434              <access>read-write</access>
56435              <resetValue>0x0</resetValue>
56436              <resetMask>0xFFFFFFFF</resetMask>
56437              <fields>
56438                <field>
56439                  <name>ND</name>
56440                  <description>New Data
56441The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective
56442Rx Buffer has been updated from a received frame. The flags remain set until the Host clears them.
56443A flag is cleared by writing a '1' to the corresponding bit position. Writing a '0' has no effect. A hard
56444reset will clear the register.
564450= Rx Buffer not updated
564461= Rx Buffer updated from new message</description>
56447                  <bitRange>[31:0]</bitRange>
56448                  <access>read-write</access>
56449                </field>
56450              </fields>
56451            </register>
56452            <register>
56453              <name>RXF0C</name>
56454              <description>Rx FIFO 0 Configuration</description>
56455              <addressOffset>0xA0</addressOffset>
56456              <size>32</size>
56457              <access>read-write</access>
56458              <resetValue>0x0</resetValue>
56459              <resetMask>0xFF7FFFFC</resetMask>
56460              <fields>
56461                <field>
56462                  <name>F0SA</name>
56463                  <description>Rx FIFO 0 Start Address
56464Start address of Rx FIFO 0 in Message RAM (32-bit word address, see Figure 2).</description>
56465                  <bitRange>[15:2]</bitRange>
56466                  <access>read-write</access>
56467                </field>
56468                <field>
56469                  <name>F0S</name>
56470                  <description>Rx FIFO 0 Size
564710= No Rx FIFO 0
564721-64= Number of Rx FIFO 0 elements
5647364= Values greater than 64 are interpreted as 64
56474The Rx FIFO 0 elements are indexed from 0 to F0S-1</description>
56475                  <bitRange>[22:16]</bitRange>
56476                  <access>read-write</access>
56477                </field>
56478                <field>
56479                  <name>F0WM</name>
56480                  <description>Rx FIFO 0 Watermark
564810= Watermark interrupt disabled
564821-64= Level for Rx FIFO 0 watermark interrupt (IR.RF0W)
5648364= Watermark interrupt disabled</description>
56484                  <bitRange>[30:24]</bitRange>
56485                  <access>read-write</access>
56486                </field>
56487                <field>
56488                  <name>F0OM</name>
56489                  <description>FIFO 0 Operation Mode
56490FIFO 0 can be operated in blocking or in overwrite mode (see Section 3.4.2).
564910= FIFO 0 blocking mode
564921= FIFO 0 overwrite mode</description>
56493                  <bitRange>[31:31]</bitRange>
56494                  <access>read-write</access>
56495                </field>
56496              </fields>
56497            </register>
56498            <register>
56499              <name>RXF0S</name>
56500              <description>Rx FIFO 0 Status</description>
56501              <addressOffset>0xA4</addressOffset>
56502              <size>32</size>
56503              <access>read-only</access>
56504              <resetValue>0x0</resetValue>
56505              <resetMask>0x33F3F7F</resetMask>
56506              <fields>
56507                <field>
56508                  <name>F0FL</name>
56509                  <description>Rx FIFO 0 Fill Level
56510Number of elements stored in Rx FIFO 0, range 0 to 64.</description>
56511                  <bitRange>[6:0]</bitRange>
56512                  <access>read-only</access>
56513                </field>
56514                <field>
56515                  <name>F0GI</name>
56516                  <description>Rx FIFO 0 Get Index
56517Rx FIFO 0 read index pointer, range 0 to 63.
56518This field is updated by the software writing to RxF0A.F0AI</description>
56519                  <bitRange>[13:8]</bitRange>
56520                  <access>read-only</access>
56521                </field>
56522                <field>
56523                  <name>F0PI</name>
56524                  <description>Rx FIFO 0 Put Index
56525Rx FIFO 0 write index pointer, range 0 to 63.</description>
56526                  <bitRange>[21:16]</bitRange>
56527                  <access>read-only</access>
56528                </field>
56529                <field>
56530                  <name>F0F</name>
56531                  <description>Rx FIFO 0 Full
565320= Rx FIFO 0 not full
565331= Rx FIFO 0 full</description>
56534                  <bitRange>[24:24]</bitRange>
56535                  <access>read-only</access>
56536                </field>
56537                <field>
56538                  <name>RF0L</name>
56539                  <description>Rx FIFO 0 Message Lost
56540This bit is a copy of interrupt flag IR.RF0L. When IR.RF0L is reset, this bit is also reset.
565410= No Rx FIFO 0 message lost
565421= Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero</description>
56543                  <bitRange>[25:25]</bitRange>
56544                  <access>read-only</access>
56545                </field>
56546              </fields>
56547            </register>
56548            <register>
56549              <name>RXF0A</name>
56550              <description>Rx FIFO 0 Acknowledge</description>
56551              <addressOffset>0xA8</addressOffset>
56552              <size>32</size>
56553              <access>read-write</access>
56554              <resetValue>0x0</resetValue>
56555              <resetMask>0x3F</resetMask>
56556              <fields>
56557                <field>
56558                  <name>F0AI</name>
56559                  <description>Rx FIFO 0 Acknowledge Index
56560After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the
56561 buffer index of the last element read from Rx FIFO 0 to F0AI. This will set the Rx FIFO 0 Get Index
56562 RXF0S.F0GI to F0AI + 1 and update the FIFO 0 Fill Level RXF0S.F0FL.</description>
56563                  <bitRange>[5:0]</bitRange>
56564                  <access>read-write</access>
56565                </field>
56566              </fields>
56567            </register>
56568            <register>
56569              <name>RXBC</name>
56570              <description>Rx Buffer Configuration</description>
56571              <addressOffset>0xAC</addressOffset>
56572              <size>32</size>
56573              <access>read-write</access>
56574              <resetValue>0x0</resetValue>
56575              <resetMask>0xFFFC</resetMask>
56576              <fields>
56577                <field>
56578                  <name>RBSA</name>
56579                  <description>Rx Buffer Start Address
56580Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address).
56581Also used to reference debug messages A,B,C.</description>
56582                  <bitRange>[15:2]</bitRange>
56583                  <access>read-write</access>
56584                </field>
56585              </fields>
56586            </register>
56587            <register>
56588              <name>RXF1C</name>
56589              <description>Rx FIFO 1 Configuration</description>
56590              <addressOffset>0xB0</addressOffset>
56591              <size>32</size>
56592              <access>read-write</access>
56593              <resetValue>0x0</resetValue>
56594              <resetMask>0xFF7FFFFC</resetMask>
56595              <fields>
56596                <field>
56597                  <name>F1SA</name>
56598                  <description>Rx FIFO 1 Start Address
56599Start address of Rx FIFO 1 in Message RAM (32-bit word address, see Figure 2).</description>
56600                  <bitRange>[15:2]</bitRange>
56601                  <access>read-write</access>
56602                </field>
56603                <field>
56604                  <name>F1S</name>
56605                  <description>Rx FIFO 1 Size
566060= No Rx FIFO 1
566071-64= Number of Rx FIFO 1 elements
5660864= Values greater than 64 are interpreted as 64
56609The Rx FIFO 1 elements are indexed from 0 to F1S - 1</description>
56610                  <bitRange>[22:16]</bitRange>
56611                  <access>read-write</access>
56612                </field>
56613                <field>
56614                  <name>F1WM</name>
56615                  <description>Rx FIFO 1 Watermark
566160= Watermark interrupt disabled
566171-64= Level for Rx FIFO 1 watermark interrupt (IR.RF1W)
5661864= Watermark interrupt disabled</description>
56619                  <bitRange>[30:24]</bitRange>
56620                  <access>read-write</access>
56621                </field>
56622                <field>
56623                  <name>F1OM</name>
56624                  <description>FIFO 1 Operation Mode
56625FIFO 1 can be operated in blocking or in overwrite mode (see Section 3.4.2).
566260= FIFO 1 blocking mode
566271= FIFO 1 overwrite mode</description>
56628                  <bitRange>[31:31]</bitRange>
56629                  <access>read-write</access>
56630                </field>
56631              </fields>
56632            </register>
56633            <register>
56634              <name>RXF1S</name>
56635              <description>Rx FIFO 1 Status</description>
56636              <addressOffset>0xB4</addressOffset>
56637              <size>32</size>
56638              <access>read-only</access>
56639              <resetValue>0x0</resetValue>
56640              <resetMask>0xC33F3F7F</resetMask>
56641              <fields>
56642                <field>
56643                  <name>F1FL</name>
56644                  <description>Rx FIFO 1 Fill Level
56645Number of elements stored in Rx FIFO 1, range 0 to 64.</description>
56646                  <bitRange>[6:0]</bitRange>
56647                  <access>read-only</access>
56648                </field>
56649                <field>
56650                  <name>F1GI</name>
56651                  <description>Rx FIFO 1 Get Index
56652Rx FIFO 1 read index pointer, range 0 to 63.
56653This field is updated by the software writing to RxF1A.FAI</description>
56654                  <bitRange>[13:8]</bitRange>
56655                  <access>read-only</access>
56656                </field>
56657                <field>
56658                  <name>F1PI</name>
56659                  <description>Rx FIFO 1 Put Index
56660Rx FIFO 1 write index pointer, range 0 to 63.</description>
56661                  <bitRange>[21:16]</bitRange>
56662                  <access>read-only</access>
56663                </field>
56664                <field>
56665                  <name>F1F</name>
56666                  <description>Rx FIFO 1 Full
566670= Rx FIFO 1 not full
566681= Rx FIFO 1 full</description>
56669                  <bitRange>[24:24]</bitRange>
56670                  <access>read-only</access>
56671                </field>
56672                <field>
56673                  <name>RF1L</name>
56674                  <description>Rx FIFO 1 Message Lost
56675This bit is a copy of interrupt flag IR.RF1L. When IR.RF1L is reset, this bit is also reset.
566760= No Rx FIFO 1 message lost
566771= Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero</description>
56678                  <bitRange>[25:25]</bitRange>
56679                  <access>read-only</access>
56680                </field>
56681                <field>
56682                  <name>DMS</name>
56683                  <description>Debug Message Status
5668400= Idle state, wait for reception of debug messages, DMA request is cleared
5668501= Debug message A received
5668610= Debug messages A, B received
5668711= Debug messages A, B, C received, DMA request is set</description>
56688                  <bitRange>[31:30]</bitRange>
56689                  <access>read-only</access>
56690                </field>
56691              </fields>
56692            </register>
56693            <register>
56694              <name>RXF1A</name>
56695              <description>Rx FIFO 1 Acknowledge</description>
56696              <addressOffset>0xB8</addressOffset>
56697              <size>32</size>
56698              <access>read-write</access>
56699              <resetValue>0x0</resetValue>
56700              <resetMask>0x3F</resetMask>
56701              <fields>
56702                <field>
56703                  <name>F1AI</name>
56704                  <description>Rx FIFO 1 Acknowledge Index
56705After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the
56706 buffer index of the last element read from Rx FIFO 1 to F1AI. This will set the Rx FIFO 1 Get Index
56707 RXF1S.F1GI to F1AI + 1 and update the FIFO 1 Fill Level RXF1S.F1FL.</description>
56708                  <bitRange>[5:0]</bitRange>
56709                  <access>read-write</access>
56710                </field>
56711              </fields>
56712            </register>
56713            <register>
56714              <name>RXESC</name>
56715              <description>Rx Buffer / FIFO Element Size Configuration</description>
56716              <addressOffset>0xBC</addressOffset>
56717              <size>32</size>
56718              <access>read-write</access>
56719              <resetValue>0x0</resetValue>
56720              <resetMask>0x777</resetMask>
56721              <fields>
56722                <field>
56723                  <name>F0DS</name>
56724                  <description>Rx FIFO 0 Data Field Size
56725000= 8 byte data field
56726001= 12 byte data field
56727010= 16 byte data field
56728011= 20 byte data field
56729100= 24 byte data field
56730101= 32 byte data field
56731110= 48 byte data field
56732111= 64 byte data field</description>
56733                  <bitRange>[2:0]</bitRange>
56734                  <access>read-write</access>
56735                </field>
56736                <field>
56737                  <name>F1DS</name>
56738                  <description>Rx FIFO 1 Data Field Size
56739000= 8 byte data field
56740001= 12 byte data field
56741010= 16 byte data field
56742011= 20 byte data field
56743100= 24 byte data field
56744101= 32 byte data field
56745110= 48 byte data field
56746111= 64 byte data field</description>
56747                  <bitRange>[6:4]</bitRange>
56748                  <access>read-write</access>
56749                </field>
56750                <field>
56751                  <name>RBDS</name>
56752                  <description>Rx Buffer Data Field Size
56753000= 8 byte data field
56754001= 12 byte data field
56755010= 16 byte data field
56756011= 20 byte data field
56757100= 24 byte data field
56758101= 32 byte data field
56759110= 48 byte data field
56760111= 64 byte data field</description>
56761                  <bitRange>[10:8]</bitRange>
56762                  <access>read-write</access>
56763                </field>
56764              </fields>
56765            </register>
56766            <register>
56767              <name>TXBC</name>
56768              <description>Tx Buffer Configuration</description>
56769              <addressOffset>0xC0</addressOffset>
56770              <size>32</size>
56771              <access>read-write</access>
56772              <resetValue>0x0</resetValue>
56773              <resetMask>0x7F3FFFFC</resetMask>
56774              <fields>
56775                <field>
56776                  <name>TBSA</name>
56777                  <description>Tx Buffers Start Address
56778Start address of Tx Buffers section in Message RAM (32-bit word address, see Figure 2).</description>
56779                  <bitRange>[15:2]</bitRange>
56780                  <access>read-write</access>
56781                </field>
56782                <field>
56783                  <name>NDTB</name>
56784                  <description>Number of Dedicated Transmit Buffers
567850= No Dedicated Tx Buffers
567861-32= Number of Dedicated Tx Buffers
5678732= Values greater than 32 are interpreted as 32</description>
56788                  <bitRange>[21:16]</bitRange>
56789                  <access>read-write</access>
56790                </field>
56791                <field>
56792                  <name>TFQS</name>
56793                  <description>Transmit FIFO/Queue Size
567940= No Tx FIFO/Queue
567951-32= Number of Tx Buffers used for Tx FIFO/Queue
5679632= Values greater than 32 are interpreted as 32</description>
56797                  <bitRange>[29:24]</bitRange>
56798                  <access>read-write</access>
56799                </field>
56800                <field>
56801                  <name>TFQM</name>
56802                  <description>Tx FIFO/Queue Mode
568030= Tx FIFO operation
568041= Tx Queue operation</description>
56805                  <bitRange>[30:30]</bitRange>
56806                  <access>read-write</access>
56807                </field>
56808              </fields>
56809            </register>
56810            <register>
56811              <name>TXFQS</name>
56812              <description>Tx FIFO/Queue Status</description>
56813              <addressOffset>0xC4</addressOffset>
56814              <size>32</size>
56815              <access>read-only</access>
56816              <resetValue>0x0</resetValue>
56817              <resetMask>0x3F1F3F</resetMask>
56818              <fields>
56819                <field>
56820                  <name>TFFL</name>
56821                  <description>Tx FIFO Free Level
56822Number of consecutive free Tx FIFO elements starting from TFGI, range 0 to 32. Read as zero when
56823Tx Queue operation is configured (TXBC.TFQM = '1')</description>
56824                  <bitRange>[5:0]</bitRange>
56825                  <access>read-only</access>
56826                </field>
56827                <field>
56828                  <name>TFGI</name>
56829                  <description>Tx FIFO Get Index
56830Tx FIFO read index pointer, range 0 to 31. Read as zero when Tx Queue operation is configured
56831TXBC.TFQM = '1').</description>
56832                  <bitRange>[12:8]</bitRange>
56833                  <access>read-only</access>
56834                </field>
56835                <field>
56836                  <name>TFQPI</name>
56837                  <description>Tx FIFO/Queue Put Index
56838Tx FIFO/Queue write index pointer, range 0 to 31.</description>
56839                  <bitRange>[20:16]</bitRange>
56840                  <access>read-only</access>
56841                </field>
56842                <field>
56843                  <name>TFQF</name>
56844                  <description>Tx FIFO/Queue Full
568450= Tx FIFO/Queue not full
568461= Tx FIFO/Queue full</description>
56847                  <bitRange>[21:21]</bitRange>
56848                  <access>read-only</access>
56849                </field>
56850              </fields>
56851            </register>
56852            <register>
56853              <name>TXESC</name>
56854              <description>Tx Buffer Element Size Configuration</description>
56855              <addressOffset>0xC8</addressOffset>
56856              <size>32</size>
56857              <access>read-write</access>
56858              <resetValue>0x0</resetValue>
56859              <resetMask>0x7</resetMask>
56860              <fields>
56861                <field>
56862                  <name>TBDS</name>
56863                  <description>Tx Buffer Data Field Size
56864000= 8 byte data field
56865001= 12 byte data field
56866010= 16 byte data field
56867011= 20 byte data field
56868100= 24 byte data field
56869101= 32 byte data field
56870110= 48 byte data field
56871111= 64 byte data field</description>
56872                  <bitRange>[2:0]</bitRange>
56873                  <access>read-write</access>
56874                </field>
56875              </fields>
56876            </register>
56877            <register>
56878              <name>TXBRP</name>
56879              <description>Tx Buffer Request Pending</description>
56880              <addressOffset>0xCC</addressOffset>
56881              <size>32</size>
56882              <access>read-only</access>
56883              <resetValue>0x0</resetValue>
56884              <resetMask>0xFFFFFFFF</resetMask>
56885              <fields>
56886                <field>
56887                  <name>TRP</name>
56888                  <description>Transmission Request Pending
56889Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via register TXBAR.
56890The bits are reset after a requested transmission has completed or has been cancelled via register
56891TXBCR.
56892TXBRP bits are set only for those Tx Buffers configured via TXBC. After a TXBRP bit has been set,
56893a Tx scan (see Section 3.5, Tx Handling) is started to check for the pending Tx request with the
56894highest priority (Tx Buffer with lowest Message ID).
56895A cancellation request resets the corresponding transmission request pending bit of register
56896TXBRP. In case a transmission has already been started when a cancellation is requested, this is
56897done at the end of the transmission, regardless whether the transmission was successful or not. The
56898cancellation request bits are reset directly after the corresponding TXBRP bit has been reset.
56899After a cancellation has been requested, a finished cancellation is signaled via TXBCF
56900after successful transmission together with the corresponding TXBTO bit
56901when the transmission has not yet been started at the point of cancellation
56902when the transmission has been aborted due to lost arbitration
56903when an error occurred during frame transmission
56904In DAR mode all transmissions are automatically cancelled if they are not successful. The
56905corresponding TXBCF bit is set for all unsuccessful transmissions.
569060= No transmission request pending
569071= Transmission request pending</description>
56908                  <bitRange>[31:0]</bitRange>
56909                  <access>read-only</access>
56910                </field>
56911              </fields>
56912            </register>
56913            <register>
56914              <name>TXBAR</name>
56915              <description>Tx Buffer Add Request</description>
56916              <addressOffset>0xD0</addressOffset>
56917              <size>32</size>
56918              <access>read-write</access>
56919              <resetValue>0x0</resetValue>
56920              <resetMask>0xFFFFFFFF</resetMask>
56921              <fields>
56922                <field>
56923                  <name>AR</name>
56924                  <description>Add Request
56925Each Tx Buffer has its own Add Request bit. Writing a '1' will set the corresponding Add Request
56926bit; writing a '0' has no impact. This enables the Host to set transmission requests for multiple Tx
56927Buffers with one write to TXBAR. TXBAR bits are set only for those Tx Buffers configured via TXBC.
56928When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan
56929process has completed.
569300= No transmission request added
569311= Transmission requested added</description>
56932                  <bitRange>[31:0]</bitRange>
56933                  <access>read-write</access>
56934                </field>
56935              </fields>
56936            </register>
56937            <register>
56938              <name>TXBCR</name>
56939              <description>Tx Buffer Cancellation Request</description>
56940              <addressOffset>0xD4</addressOffset>
56941              <size>32</size>
56942              <access>read-write</access>
56943              <resetValue>0x0</resetValue>
56944              <resetMask>0xFFFFFFFF</resetMask>
56945              <fields>
56946                <field>
56947                  <name>CR</name>
56948                  <description>Cancellation Request
56949Each Tx Buffer has its own Cancellation Request bit. Writing a '1' will set the corresponding
56950Cancellation Request bit; writing a '0' has no impact. This enables the Host to set cancellation
56951requests for multiple Tx Buffers with one write to TXBCR. TXBCR bits are set only for those Tx
56952Buffers configured via TXBC. The bits remain set until the corresponding bit of TXBRP is reset.
569530= No cancellation pending
569541= Cancellation pending</description>
56955                  <bitRange>[31:0]</bitRange>
56956                  <access>read-write</access>
56957                </field>
56958              </fields>
56959            </register>
56960            <register>
56961              <name>TXBTO</name>
56962              <description>Tx Buffer Transmission Occurred</description>
56963              <addressOffset>0xD8</addressOffset>
56964              <size>32</size>
56965              <access>read-only</access>
56966              <resetValue>0x0</resetValue>
56967              <resetMask>0xFFFFFFFF</resetMask>
56968              <fields>
56969                <field>
56970                  <name>TO</name>
56971                  <description>Transmission Occurred
56972Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding
56973TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission
56974is requested by writing a '1' to the corresponding bit of register TXBAR.
569750= No transmission occurred
569761= Transmission occurred</description>
56977                  <bitRange>[31:0]</bitRange>
56978                  <access>read-only</access>
56979                </field>
56980              </fields>
56981            </register>
56982            <register>
56983              <name>TXBCF</name>
56984              <description>Tx Buffer Cancellation Finished</description>
56985              <addressOffset>0xDC</addressOffset>
56986              <size>32</size>
56987              <access>read-only</access>
56988              <resetValue>0x0</resetValue>
56989              <resetMask>0xFFFFFFFF</resetMask>
56990              <fields>
56991                <field>
56992                  <name>CF</name>
56993                  <description>Cancellation Finished
56994Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding
56995TXBRP bit is cleared after a cancellation was requested via TXBCR. In case the corresponding
56996TXBRP bit was not set at the point of cancellation, CF is set immediately. The bits are reset when a
56997new transmission is requested by writing a '1' to the corresponding bit of register TXBAR.
569980= No transmit buffer cancellation
569991= Transmit buffer cancellation finished</description>
57000                  <bitRange>[31:0]</bitRange>
57001                  <access>read-only</access>
57002                </field>
57003              </fields>
57004            </register>
57005            <register>
57006              <name>TXBTIE</name>
57007              <description>Tx Buffer Transmission Interrupt Enable</description>
57008              <addressOffset>0xE0</addressOffset>
57009              <size>32</size>
57010              <access>read-write</access>
57011              <resetValue>0x0</resetValue>
57012              <resetMask>0xFFFFFFFF</resetMask>
57013              <fields>
57014                <field>
57015                  <name>TIE</name>
57016                  <description>Transmission Interrupt Enable
57017Each Tx Buffer has its own Transmission Interrupt Enable bit.
570180= Transmission interrupt disabled
570191= Transmission interrupt enable</description>
57020                  <bitRange>[31:0]</bitRange>
57021                  <access>read-write</access>
57022                </field>
57023              </fields>
57024            </register>
57025            <register>
57026              <name>TXBCIE</name>
57027              <description>Tx Buffer Cancellation Finished Interrupt Enable</description>
57028              <addressOffset>0xE4</addressOffset>
57029              <size>32</size>
57030              <access>read-write</access>
57031              <resetValue>0x0</resetValue>
57032              <resetMask>0xFFFFFFFF</resetMask>
57033              <fields>
57034                <field>
57035                  <name>CFIE</name>
57036                  <description>Cancellation Finished Interrupt Enable
57037Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
570380= Cancellation finished interrupt disabled
570391= Cancellation finished interrupt enabled</description>
57040                  <bitRange>[31:0]</bitRange>
57041                  <access>read-write</access>
57042                </field>
57043              </fields>
57044            </register>
57045            <register>
57046              <name>TXEFC</name>
57047              <description>Tx Event FIFO Configuration</description>
57048              <addressOffset>0xF0</addressOffset>
57049              <size>32</size>
57050              <access>read-write</access>
57051              <resetValue>0x0</resetValue>
57052              <resetMask>0x3F3FFFFC</resetMask>
57053              <fields>
57054                <field>
57055                  <name>EFSA</name>
57056                  <description>Event FIFO Start Address
57057Start address of Tx Event FIFO in Message RAM (32-bit word address, see Figure 2).</description>
57058                  <bitRange>[15:2]</bitRange>
57059                  <access>read-write</access>
57060                </field>
57061                <field>
57062                  <name>EFS</name>
57063                  <description>Event FIFO Size
570640= Tx Event FIFO disabled
570651-32= Number of Tx Event FIFO elements
5706632= Values greater than 32 are interpreted as 32
57067The Tx Event FIFO elements are indexed from 0 to EFS-1</description>
57068                  <bitRange>[21:16]</bitRange>
57069                  <access>read-write</access>
57070                </field>
57071                <field>
57072                  <name>EFWM</name>
57073                  <description>Event FIFO Watermark
570740= Watermark interrupt disabled
570751-32= Level for Tx Event FIFO watermark interrupt (IR.TEFW)
5707632= Watermark interrupt disabled</description>
57077                  <bitRange>[29:24]</bitRange>
57078                  <access>read-write</access>
57079                </field>
57080              </fields>
57081            </register>
57082            <register>
57083              <name>TXEFS</name>
57084              <description>Tx Event FIFO Status</description>
57085              <addressOffset>0xF4</addressOffset>
57086              <size>32</size>
57087              <access>read-only</access>
57088              <resetValue>0x0</resetValue>
57089              <resetMask>0x31F1F3F</resetMask>
57090              <fields>
57091                <field>
57092                  <name>EFFL</name>
57093                  <description>Event FIFO Fill Level
57094Number of elements stored in Tx Event FIFO, range 0 to 32.</description>
57095                  <bitRange>[5:0]</bitRange>
57096                  <access>read-only</access>
57097                </field>
57098                <field>
57099                  <name>EFGI</name>
57100                  <description>Event FIFO Get Index
57101Tx Event FIFO read index pointer, range 0 to 31.</description>
57102                  <bitRange>[12:8]</bitRange>
57103                  <access>read-only</access>
57104                </field>
57105                <field>
57106                  <name>EFPI</name>
57107                  <description>Event FIFO Put Index
57108Tx Event FIFO write index pointer, range 0 to 31.</description>
57109                  <bitRange>[20:16]</bitRange>
57110                  <access>read-only</access>
57111                </field>
57112                <field>
57113                  <name>EFF</name>
57114                  <description>Event FIFO Full
571150= Tx Event FIFO not full
571161= Tx Event FIFO full</description>
57117                  <bitRange>[24:24]</bitRange>
57118                  <access>read-only</access>
57119                </field>
57120                <field>
57121                  <name>TEFL</name>
57122                  <description>Tx Event FIFO Element Lost
57123This bit is a copy of interrupt flag IR.TEFL. When IR.TEFL is reset, this bit is also reset.
571240= No Tx Event FIFO element lost
571251= Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero.</description>
57126                  <bitRange>[25:25]</bitRange>
57127                  <access>read-only</access>
57128                </field>
57129              </fields>
57130            </register>
57131            <register>
57132              <name>TXEFA</name>
57133              <description>Tx Event FIFO Acknowledge</description>
57134              <addressOffset>0xF8</addressOffset>
57135              <size>32</size>
57136              <access>read-write</access>
57137              <resetValue>0x0</resetValue>
57138              <resetMask>0x1F</resetMask>
57139              <fields>
57140                <field>
57141                  <name>EFAI</name>
57142                  <description>Event FIFO Acknowledge Index
57143After the Host has read an element or a sequence of elements from the Tx Event FIFO it has to write
57144the index of the last element read from Tx Event FIFO to EFAI. This will set the Tx Event FIFO Get
57145Index TXEFS.EFGI to EFAI + 1 and update the Event FIFO Fill Level TXEFS.EFFL.</description>
57146                  <bitRange>[4:0]</bitRange>
57147                  <access>read-write</access>
57148                </field>
57149              </fields>
57150            </register>
57151            <register>
57152              <name>TTTMC</name>
57153              <description>TT Trigger Memory Configuration</description>
57154              <addressOffset>0x100</addressOffset>
57155              <size>32</size>
57156              <access>read-write</access>
57157              <resetValue>0x0</resetValue>
57158              <resetMask>0x7FFFFC</resetMask>
57159              <fields>
57160                <field>
57161                  <name>TMSA</name>
57162                  <description>Trigger Memory Start Address
57163Start address of Trigger Memory in Message RAM (32-bit word address, see Figure 2).</description>
57164                  <bitRange>[15:2]</bitRange>
57165                  <access>read-write</access>
57166                </field>
57167                <field>
57168                  <name>TME</name>
57169                  <description>Trigger Memory Elements
571700= No Trigger Memory
571711-64= Number of Trigger Memory elements
5717264= Values greater than 64 are interpreted as 64</description>
57173                  <bitRange>[22:16]</bitRange>
57174                  <access>read-write</access>
57175                </field>
57176              </fields>
57177            </register>
57178            <register>
57179              <name>TTRMC</name>
57180              <description>TT Reference Message Configuration</description>
57181              <addressOffset>0x104</addressOffset>
57182              <size>32</size>
57183              <access>read-write</access>
57184              <resetValue>0x0</resetValue>
57185              <resetMask>0xDFFFFFFF</resetMask>
57186              <fields>
57187                <field>
57188                  <name>RID</name>
57189                  <description>Reference Identifier
57190Identifier transmitted with reference message and used for reference message filtering. Standard or
57191extended reference identifier depending on bit XTD. A standard identifier has to be written to
57192ID[28:18].</description>
57193                  <bitRange>[28:0]</bitRange>
57194                  <access>read-write</access>
57195                </field>
57196                <field>
57197                  <name>XTD</name>
57198                  <description>Extended Identifier
571990= 11-bit standard identifier
572001= 29-bit extended identifier</description>
57201                  <bitRange>[30:30]</bitRange>
57202                  <access>read-write</access>
57203                </field>
57204                <field>
57205                  <name>RMPS</name>
57206                  <description>Reference Message Payload Select
57207Ignored in case of time slaves.
572080= Reference message has no additional payload
572091= The following elements are taken from Tx Buffer 0:
57210Message Marker MM, Event FIFO Control EFC, Data Length Code DLC, Data Bytes DB
57211Level 1: bytes 2-8, Level 0,2: bytes 5-8)</description>
57212                  <bitRange>[31:31]</bitRange>
57213                  <access>read-write</access>
57214                </field>
57215              </fields>
57216            </register>
57217            <register>
57218              <name>TTOCF</name>
57219              <description>TT Operation Configuration</description>
57220              <addressOffset>0x108</addressOffset>
57221              <size>32</size>
57222              <access>read-write</access>
57223              <resetValue>0x10000</resetValue>
57224              <resetMask>0x7FFFFFB</resetMask>
57225              <fields>
57226                <field>
57227                  <name>OM</name>
57228                  <description>Operation Mode
5722900= Event-driven CAN communication, default
5723001= TTCAN level 1
5723110= TTCAN level 2
5723211= TTCAN level 0</description>
57233                  <bitRange>[1:0]</bitRange>
57234                  <access>read-write</access>
57235                </field>
57236                <field>
57237                  <name>GEN</name>
57238                  <description>Gap Enable
572390= Strictly time-triggered operation
572401= External event-synchronized time-triggered operation</description>
57241                  <bitRange>[3:3]</bitRange>
57242                  <access>read-write</access>
57243                </field>
57244                <field>
57245                  <name>TM</name>
57246                  <description>Time Master
572470= Time Master function disabled
572481= Potential Time Master</description>
57249                  <bitRange>[4:4]</bitRange>
57250                  <access>read-write</access>
57251                </field>
57252                <field>
57253                  <name>LDSDL</name>
57254                  <description>LD of Synchronization Deviation Limit
57255The Synchronization Deviation Limit SDL is configured by its dual logarithm LDSDL with SDL =
572562(LDSDL + 5). It should not exceed the clock tolerance given by the CAN bit timing configuration.
572570x0-7 LD of Synchronization Deviation Limit (SDL &lt;= 32...4096)</description>
57258                  <bitRange>[7:5]</bitRange>
57259                  <access>read-write</access>
57260                </field>
57261                <field>
57262                  <name>IRTO</name>
57263                  <description>Initial Reference Trigger Offset
572640x00-7F Positive offset, range from 0 to 127</description>
57265                  <bitRange>[14:8]</bitRange>
57266                  <access>read-write</access>
57267                </field>
57268                <field>
57269                  <name>EECS</name>
57270                  <description>Enable External Clock Synchronization
57271If enabled, TUR configuration (TURCF.NCL only) may be updated during TTCAN operation.
572720= External clock synchronization in TTCAN Level 0,2 disabled
572731= External clock synchronization in TTCAN Level 0,2 enabled</description>
57274                  <bitRange>[15:15]</bitRange>
57275                  <access>read-write</access>
57276                </field>
57277                <field>
57278                  <name>AWL</name>
57279                  <description>Application Watchdog Limit
57280The application watchdog can be disabled by programming AWL to 0x00.
572810x00-FF Maximum time after which the application has to serve the application watchdog.
57282The application watchdog is incremented once each 256 NTUs.</description>
57283                  <bitRange>[23:16]</bitRange>
57284                  <access>read-write</access>
57285                </field>
57286                <field>
57287                  <name>EGTF</name>
57288                  <description>Enable Global Time Filtering
572890= Global time filtering in TTCAN Level 0,2 is disabled
572901= Global time filtering in TTCAN Level 0,2 is enabled</description>
57291                  <bitRange>[24:24]</bitRange>
57292                  <access>read-write</access>
57293                </field>
57294                <field>
57295                  <name>ECC</name>
57296                  <description>Enable Clock Calibration
572970= Automatic clock calibration in TTCAN Level 0,2 is disabled
572981= Automatic clock calibration in TTCAN Level 0,2 is enabled</description>
57299                  <bitRange>[25:25]</bitRange>
57300                  <access>read-write</access>
57301                </field>
57302                <field>
57303                  <name>EVTP</name>
57304                  <description>Event Trigger Polarity
573050= Rising edge trigger
573061= Falling edge trigger</description>
57307                  <bitRange>[26:26]</bitRange>
57308                  <access>read-write</access>
57309                </field>
57310              </fields>
57311            </register>
57312            <register>
57313              <name>TTMLM</name>
57314              <description>TT Matrix Limits</description>
57315              <addressOffset>0x10C</addressOffset>
57316              <size>32</size>
57317              <access>read-write</access>
57318              <resetValue>0x0</resetValue>
57319              <resetMask>0xFFF0FFF</resetMask>
57320              <fields>
57321                <field>
57322                  <name>CCM</name>
57323                  <description>N/A</description>
57324                  <bitRange>[5:0]</bitRange>
57325                  <access>read-write</access>
57326                </field>
57327                <field>
57328                  <name>CSS</name>
57329                  <description>N/A</description>
57330                  <bitRange>[7:6]</bitRange>
57331                  <access>read-write</access>
57332                </field>
57333                <field>
57334                  <name>TXEW</name>
57335                  <description>Tx Enable Window
573360x0-F Length of Tx enable window, 1-16 NTU cycles</description>
57337                  <bitRange>[11:8]</bitRange>
57338                  <access>read-write</access>
57339                </field>
57340                <field>
57341                  <name>ENTT</name>
57342                  <description>Expected Number of Tx Triggers
573430x000-FFF Expected number of Tx Triggers in one Matrix Cycle</description>
57344                  <bitRange>[27:16]</bitRange>
57345                  <access>read-write</access>
57346                </field>
57347              </fields>
57348            </register>
57349            <register>
57350              <name>TURCF</name>
57351              <description>TUR Configuration</description>
57352              <addressOffset>0x110</addressOffset>
57353              <size>32</size>
57354              <access>read-write</access>
57355              <resetValue>0x10000000</resetValue>
57356              <resetMask>0xBFFFFFFF</resetMask>
57357              <fields>
57358                <field>
57359                  <name>NCL</name>
57360                  <description>Numerator Configuration Low
57361Write access to the TUR Numerator Configuration Low is only possible during configuration with
57362TURCF.ELT = '0' or if TTOCF.EECS (external clock synchronization enabled) is set. When a new
57363value for NCL is written outside TT Configuration Mode, the new value takes effect when
57364TTOST.WECS is cleared to '0'. NCL is locked TTOST.WECS is '1'.
573650x0000-FFFF Numerator Configuration Low</description>
57366                  <bitRange>[15:0]</bitRange>
57367                  <access>read-write</access>
57368                </field>
57369                <field>
57370                  <name>DC</name>
57371                  <description>Denominator Configuration
573720x0000 Illegal value
573730x0001-3FFF Denominator Configuration</description>
57374                  <bitRange>[29:16]</bitRange>
57375                  <access>read-write</access>
57376                </field>
57377                <field>
57378                  <name>ELT</name>
57379                  <description>Enable Local Time
573800= Local time is stopped, default
573811= Local time is enabled</description>
57382                  <bitRange>[31:31]</bitRange>
57383                  <access>read-write</access>
57384                </field>
57385              </fields>
57386            </register>
57387            <register>
57388              <name>TTOCN</name>
57389              <description>TT Operation Control</description>
57390              <addressOffset>0x114</addressOffset>
57391              <size>32</size>
57392              <access>read-write</access>
57393              <resetValue>0x0</resetValue>
57394              <resetMask>0xBFFF</resetMask>
57395              <fields>
57396                <field>
57397                  <name>SGT</name>
57398                  <description>Set Global time
57399Writing a '1' to SGT sets TTOST.WGDT if the node is the actual Time Master. SGT is reset after one
57400Host clock period. The global time preset takes effect when the node transmits the next reference
57401message with the Master_Ref_Mark modified by the preset value written to TTGTP.</description>
57402                  <bitRange>[0:0]</bitRange>
57403                  <access>read-write</access>
57404                </field>
57405                <field>
57406                  <name>ECS</name>
57407                  <description>External Clock Synchronization
57408Writing a '1' to ECS sets TTOST.WECS if the node is the actual Time Master. ECS is reset after one
57409Host clock period. The external clock synchronization takes effect at the start of the next basic cycle.</description>
57410                  <bitRange>[1:1]</bitRange>
57411                  <access>read-write</access>
57412                </field>
57413                <field>
57414                  <name>SWP</name>
57415                  <description>Stop Watch Polarity
574160= Rising edge trigger
574171= Falling edge trigger</description>
57418                  <bitRange>[2:2]</bitRange>
57419                  <access>read-write</access>
57420                </field>
57421                <field>
57422                  <name>SWS</name>
57423                  <description>Stop Watch Source
5742400= Stop Watch disabled
5742501= Actual value of cycle time is copied to TTCPT.SWV
5742610= Actual value of local time is copied to TTCPT.SWV
5742711= Actual value of global time is copied to TTCPT.SWV</description>
57428                  <bitRange>[4:3]</bitRange>
57429                  <access>read-write</access>
57430                </field>
57431                <field>
57432                  <name>RTIE</name>
57433                  <description>Register Time Mark Interrupt Pulse Enable
57434Register time mark interrupts are configured by register TTTMK. A register time mark interrupt pulse
57435with the length of one NTU is generated when the time referenced by TTOCN.TMC (cycle, local, or
57436global) equals TTTMK.TM, independent of the synchronization state.
574370= Register Time Mark Interrupt output m_ttcan_rtp disabled
574381= Register Time Mark Interrupt output m_ttcan_rtp enabled</description>
57439                  <bitRange>[5:5]</bitRange>
57440                  <access>read-write</access>
57441                </field>
57442                <field>
57443                  <name>TMC</name>
57444                  <description>Register Time Mark Compare
5744500= No Register Time Mark Interrupt generated
5744601= Register Time Mark Interrupt if Time Mark = cycle time
5744710= Register Time Mark Interrupt if Time Mark = local time
5744811= Register Time Mark Interrupt if Time Mark = global time</description>
57449                  <bitRange>[7:6]</bitRange>
57450                  <access>read-write</access>
57451                </field>
57452                <field>
57453                  <name>TTIE</name>
57454                  <description>Trigger Time Mark Interrupt Pulse Enable
57455External time mark events are configured by trigger memory element TMEX (see Section 2.4.7). A
57456trigger time mark interrupt pulse is generated when the trigger memory element becomes active,
57457and the M_TTCAN is in synchronization state In_Schedule or In_Gap.
574580= Trigger Time Mark Interrupt output m_ttcan_tmp disabled
574591= Trigger Time Mark Interrupt output m_ttcan_tmp enabled</description>
57460                  <bitRange>[8:8]</bitRange>
57461                  <access>read-write</access>
57462                </field>
57463                <field>
57464                  <name>GCS</name>
57465                  <description>Gap Control Select
574660= Gap control independent from m_ttcan_evt
574671= Gap control by input pin m_ttcan_evt</description>
57468                  <bitRange>[9:9]</bitRange>
57469                  <access>read-write</access>
57470                </field>
57471                <field>
57472                  <name>FGP</name>
57473                  <description>Finish Gap
57474Set by the CPU, reset by each reference message
574750= No reference message requested
574761= Application requested start of reference message</description>
57477                  <bitRange>[10:10]</bitRange>
57478                  <access>read-write</access>
57479                </field>
57480                <field>
57481                  <name>TMG</name>
57482                  <description>Time Mark Gap
574830= Reset by each reference message
574841= Next reference message started when Register Time Mark interrupt TTIR.RTMI is activated</description>
57485                  <bitRange>[11:11]</bitRange>
57486                  <access>read-write</access>
57487                </field>
57488                <field>
57489                  <name>NIG</name>
57490                  <description>Next is Gap
57491This bit can only be set when the M_TTCAN is the actual Time Master and when it is configured for
57492external event-synchronized time-triggered operation (TTOCF.GEN = '1')
574930= No action, reset by reception of any reference message
574941= Transmit next reference message with Next_is_Gap = '1'</description>
57495                  <bitRange>[12:12]</bitRange>
57496                  <access>read-write</access>
57497                </field>
57498                <field>
57499                  <name>ESCN</name>
57500                  <description>External Synchronization Control
57501If enabled the M_TTCAN synchronizes its cycle time phase to an external event signaled by a rising
57502edge at pin m_ttcan_evt (see Section 4.11).
575030= External synchronization disabled
575041= External synchronization enabled</description>
57505                  <bitRange>[13:13]</bitRange>
57506                  <access>read-write</access>
57507                </field>
57508                <field>
57509                  <name>LCKC</name>
57510                  <description>TT Operation Control Register Locked
57511Set by a write access to register TTOCN. Reset when the updated configuration has been
57512synchronized into the CAN clock domain.
575130= Write access to TTOCN enabled
575141= Write access to TTOCN locked</description>
57515                  <bitRange>[15:15]</bitRange>
57516                  <access>read-only</access>
57517                </field>
57518              </fields>
57519            </register>
57520            <register>
57521              <name>TTGTP</name>
57522              <description>TT Global Time Preset</description>
57523              <addressOffset>0x118</addressOffset>
57524              <size>32</size>
57525              <access>read-write</access>
57526              <resetValue>0x0</resetValue>
57527              <resetMask>0xFFFFFFFF</resetMask>
57528              <fields>
57529                <field>
57530                  <name>TP</name>
57531                  <description>N/A</description>
57532                  <bitRange>[15:0]</bitRange>
57533                  <access>read-write</access>
57534                </field>
57535                <field>
57536                  <name>CTP</name>
57537                  <description>Cycle Time Target Phase
57538CTP is write-protected while TTOCN.ESCN or TTOST.SPL are set (see Section 4.11).
575390x0000-FFFF Defines target value of cycle time when a rising edge of m_ttcan_evt is expected</description>
57540                  <bitRange>[31:16]</bitRange>
57541                  <access>read-write</access>
57542                </field>
57543              </fields>
57544            </register>
57545            <register>
57546              <name>TTTMK</name>
57547              <description>TT Time Mark</description>
57548              <addressOffset>0x11C</addressOffset>
57549              <size>32</size>
57550              <access>read-write</access>
57551              <resetValue>0x0</resetValue>
57552              <resetMask>0x807FFFFF</resetMask>
57553              <fields>
57554                <field>
57555                  <name>TM_</name>
57556                  <description>Time Mark
575570x0000-FFFF Time Mark</description>
57558                  <bitRange>[15:0]</bitRange>
57559                  <access>read-write</access>
57560                </field>
57561                <field>
57562                  <name>TICC</name>
57563                  <description>Time Mark Cycle Code
57564Cycle count for which the time mark is valid.
575650b000000x valid for all cycles
575660b000001c valid every second cycle at cycle count mod2 = c
575670b00001cc valid every fourth cycle at cycle count mod4 = cc
575680b0001ccc valid every eighth cycle at cycle count mod8 = ccc
575690b001cccc valid every sixteenth cycle at cycle count mod16 = cccc
575700b01ccccc valid every thirty-second cycle at cycle count mod32 = ccccc
575710b1cccccc valid every sixty-fourth cycle at cycle count mod64 = cccccc</description>
57572                  <bitRange>[22:16]</bitRange>
57573                  <access>read-write</access>
57574                </field>
57575                <field>
57576                  <name>LCKM</name>
57577                  <description>TT Time Mark Register Locked
57578Always set by a write access to registers TTOCN. Set by write access to register TTTMK when
57579TTOCN.TMC != '00'. Reset when the registers have been synchronized into the CAN clock domain.
575800= Write access to TTTMK enabled
575811= Write access to TTTMK locked</description>
57582                  <bitRange>[31:31]</bitRange>
57583                  <access>read-only</access>
57584                </field>
57585              </fields>
57586            </register>
57587            <register>
57588              <name>TTIR</name>
57589              <description>TT Interrupt Register</description>
57590              <addressOffset>0x120</addressOffset>
57591              <size>32</size>
57592              <access>read-write</access>
57593              <resetValue>0x0</resetValue>
57594              <resetMask>0x7FFFF</resetMask>
57595              <fields>
57596                <field>
57597                  <name>SBC</name>
57598                  <description>Start of Basic Cycle
575990= No Basic Cycle started since bit has been reset
576001= Basic Cycle started</description>
57601                  <bitRange>[0:0]</bitRange>
57602                  <access>read-write</access>
57603                </field>
57604                <field>
57605                  <name>SMC</name>
57606                  <description>Start of Matrix Cycle
576070= No Matrix Cycle started since bit has been reset
576081= Matrix Cycle started</description>
57609                  <bitRange>[1:1]</bitRange>
57610                  <access>read-write</access>
57611                </field>
57612                <field>
57613                  <name>CSM_</name>
57614                  <description>Change of Synchronization Mode
576150= No change in master to slave relation or schedule synchronization
576161= Master to slave relation or schedule synchronization changed,
57617also set when TTOST.SPL is reset</description>
57618                  <bitRange>[2:2]</bitRange>
57619                  <access>read-write</access>
57620                </field>
57621                <field>
57622                  <name>SOG</name>
57623                  <description>Start of Gap
576240= No reference message seen with Next_is_Gap bit set
576251= Reference message with Next_is_Gap bit set becomes valid</description>
57626                  <bitRange>[3:3]</bitRange>
57627                  <access>read-write</access>
57628                </field>
57629                <field>
57630                  <name>RTMI</name>
57631                  <description>Register Time Mark Interrupt
57632Set when time referenced by TTOCN.TMC (cycle, local, or global) equals TTTMK.TM, independent
57633of the synchronization state.
576340= Time mark not reached
576351= Time mark reached</description>
57636                  <bitRange>[4:4]</bitRange>
57637                  <access>read-write</access>
57638                </field>
57639                <field>
57640                  <name>TTMI</name>
57641                  <description>Trigger Time Mark Event Internal
57642Internal time mark events are configured by trigger memory element TMIN (see Section 2.4.7). Set
57643when the trigger memory element becomes active, and the M_TTCAN is in synchronization state
57644In_Gap or In_Schedule.
576450= Time mark not reached
576461= Time mark reached (Level 0: cycle time TTOCF.IRTO * 0x200)</description>
57647                  <bitRange>[5:5]</bitRange>
57648                  <access>read-write</access>
57649                </field>
57650                <field>
57651                  <name>SWE</name>
57652                  <description>Stop Watch Event
576530= No rising/falling edge at stop watch trigger pin m_ttcan_swt detected
576541= Rising/falling edge at stop watch trigger pin m_ttcan_swt detected</description>
57655                  <bitRange>[6:6]</bitRange>
57656                  <access>read-write</access>
57657                </field>
57658                <field>
57659                  <name>GTW</name>
57660                  <description>Global Time Wrap
576610= No global time wrap occurred
576621= Global time wrap from 0xFFFF to 0x0000 occurred</description>
57663                  <bitRange>[7:7]</bitRange>
57664                  <access>read-write</access>
57665                </field>
57666                <field>
57667                  <name>GTD</name>
57668                  <description>Global Time Discontinuity
576690= No discontinuity of global time
576701= Discontinuity of global time</description>
57671                  <bitRange>[8:8]</bitRange>
57672                  <access>read-write</access>
57673                </field>
57674                <field>
57675                  <name>GTE</name>
57676                  <description>Global Time Error
57677Synchronization deviation SD exceeds limit specified by TTOCF.LDSDL, TTCAN Level 0,2 only.
576780= Synchronization deviation within limit
576791= Synchronization deviation exceeded limit</description>
57680                  <bitRange>[9:9]</bitRange>
57681                  <access>read-write</access>
57682                </field>
57683                <field>
57684                  <name>TXU</name>
57685                  <description>Tx Count Underflow
576860= Number of Tx Trigger as expected
576871= Less Tx trigger than expected in one matrix cycle</description>
57688                  <bitRange>[10:10]</bitRange>
57689                  <access>read-write</access>
57690                </field>
57691                <field>
57692                  <name>TXO</name>
57693                  <description>Tx Count Overflow
576940= Number of Tx Trigger as expected
576951= More Tx trigger than expected in one matrix cycle</description>
57696                  <bitRange>[11:11]</bitRange>
57697                  <access>read-write</access>
57698                </field>
57699                <field>
57700                  <name>SE1</name>
57701                  <description>Scheduling Error 1
577020= No scheduling error 1
577031= Scheduling error 1 occurred</description>
57704                  <bitRange>[12:12]</bitRange>
57705                  <access>read-write</access>
57706                </field>
57707                <field>
57708                  <name>SE2</name>
57709                  <description>Scheduling Error 2
577100= No scheduling error 2
577111= Scheduling error 2 occurred</description>
57712                  <bitRange>[13:13]</bitRange>
57713                  <access>read-write</access>
57714                </field>
57715                <field>
57716                  <name>ELC</name>
57717                  <description>Error Level Changed
57718Not set when error level changed during initialization.
577190= No change in error level
577201= Error level changed</description>
57721                  <bitRange>[14:14]</bitRange>
57722                  <access>read-write</access>
57723                </field>
57724                <field>
57725                  <name>IWT</name>
57726                  <description>Initialization Watch Trigger
57727The initialization is restarted by resetting IWT.
577280= No missing reference message during system startup
577291= No system startup due to missing reference message</description>
57730                  <bitRange>[15:15]</bitRange>
57731                  <access>read-write</access>
57732                </field>
57733                <field>
57734                  <name>WT</name>
57735                  <description>Watch Trigger
577360= No missing reference message
577371= Missing reference message (Level 0: cycle time 0xFF00)</description>
57738                  <bitRange>[16:16]</bitRange>
57739                  <access>read-write</access>
57740                </field>
57741                <field>
57742                  <name>AW</name>
57743                  <description>Application Watchdog
577440= Application watchdog served in time
577451= Application watchdog not served in time</description>
57746                  <bitRange>[17:17]</bitRange>
57747                  <access>read-write</access>
57748                </field>
57749                <field>
57750                  <name>CER</name>
57751                  <description>Configuration Error
57752Trigger out of order.
577530= No error found in trigger list
577541= Error found in trigger list</description>
57755                  <bitRange>[18:18]</bitRange>
57756                  <access>read-write</access>
57757                </field>
57758              </fields>
57759            </register>
57760            <register>
57761              <name>TTIE</name>
57762              <description>TT Interrupt Enable</description>
57763              <addressOffset>0x124</addressOffset>
57764              <size>32</size>
57765              <access>read-write</access>
57766              <resetValue>0x0</resetValue>
57767              <resetMask>0x7FFFF</resetMask>
57768              <fields>
57769                <field>
57770                  <name>SBCE</name>
57771                  <description>Start of Basic Cycle Interrupt Enable</description>
57772                  <bitRange>[0:0]</bitRange>
57773                  <access>read-write</access>
57774                </field>
57775                <field>
57776                  <name>SMCE</name>
57777                  <description>Start of Matrix Cycle Interrupt Enable</description>
57778                  <bitRange>[1:1]</bitRange>
57779                  <access>read-write</access>
57780                </field>
57781                <field>
57782                  <name>CSME</name>
57783                  <description>Change of Synchronization Mode Interrupt Enable</description>
57784                  <bitRange>[2:2]</bitRange>
57785                  <access>read-write</access>
57786                </field>
57787                <field>
57788                  <name>SOGE</name>
57789                  <description>Start of Gap Interrupt Enable</description>
57790                  <bitRange>[3:3]</bitRange>
57791                  <access>read-write</access>
57792                </field>
57793                <field>
57794                  <name>RTMIE</name>
57795                  <description>Register Time Mark Interrupt Enable</description>
57796                  <bitRange>[4:4]</bitRange>
57797                  <access>read-write</access>
57798                </field>
57799                <field>
57800                  <name>TTMIE</name>
57801                  <description>Trigger Time Mark Event Internal Enable</description>
57802                  <bitRange>[5:5]</bitRange>
57803                  <access>read-write</access>
57804                </field>
57805                <field>
57806                  <name>SWEE</name>
57807                  <description>Stop Watch Event Interrupt Enable</description>
57808                  <bitRange>[6:6]</bitRange>
57809                  <access>read-write</access>
57810                </field>
57811                <field>
57812                  <name>GTWE</name>
57813                  <description>Global Time Wrap Interrupt Enable</description>
57814                  <bitRange>[7:7]</bitRange>
57815                  <access>read-write</access>
57816                </field>
57817                <field>
57818                  <name>GTDE</name>
57819                  <description>Global Time Discontinuity Interrupt Enable</description>
57820                  <bitRange>[8:8]</bitRange>
57821                  <access>read-write</access>
57822                </field>
57823                <field>
57824                  <name>GTEE</name>
57825                  <description>Global Time Error Interrupt Enable</description>
57826                  <bitRange>[9:9]</bitRange>
57827                  <access>read-write</access>
57828                </field>
57829                <field>
57830                  <name>TXUE</name>
57831                  <description>Tx Count Underflow Interrupt Enable</description>
57832                  <bitRange>[10:10]</bitRange>
57833                  <access>read-write</access>
57834                </field>
57835                <field>
57836                  <name>TXOE</name>
57837                  <description>Tx Count Overflow Interrupt Enable</description>
57838                  <bitRange>[11:11]</bitRange>
57839                  <access>read-write</access>
57840                </field>
57841                <field>
57842                  <name>SE1E</name>
57843                  <description>Scheduling Error 1 Interrupt Enable</description>
57844                  <bitRange>[12:12]</bitRange>
57845                  <access>read-write</access>
57846                </field>
57847                <field>
57848                  <name>SE2E</name>
57849                  <description>Scheduling Error 2 Interrupt Enable</description>
57850                  <bitRange>[13:13]</bitRange>
57851                  <access>read-write</access>
57852                </field>
57853                <field>
57854                  <name>ELCE</name>
57855                  <description>Change Error Level Interrupt Enable</description>
57856                  <bitRange>[14:14]</bitRange>
57857                  <access>read-write</access>
57858                </field>
57859                <field>
57860                  <name>IWTE</name>
57861                  <description>Initialization Watch Trigger Interrupt Enable</description>
57862                  <bitRange>[15:15]</bitRange>
57863                  <access>read-write</access>
57864                </field>
57865                <field>
57866                  <name>WTE</name>
57867                  <description>Watch Trigger Interrupt Enable</description>
57868                  <bitRange>[16:16]</bitRange>
57869                  <access>read-write</access>
57870                </field>
57871                <field>
57872                  <name>AWE_</name>
57873                  <description>Application Watchdog Interrupt Enable</description>
57874                  <bitRange>[17:17]</bitRange>
57875                  <access>read-write</access>
57876                </field>
57877                <field>
57878                  <name>CERE</name>
57879                  <description>Configuration Error Interrupt Enable</description>
57880                  <bitRange>[18:18]</bitRange>
57881                  <access>read-write</access>
57882                </field>
57883              </fields>
57884            </register>
57885            <register>
57886              <name>TTILS</name>
57887              <description>TT Interrupt Line Select</description>
57888              <addressOffset>0x128</addressOffset>
57889              <size>32</size>
57890              <access>read-write</access>
57891              <resetValue>0x0</resetValue>
57892              <resetMask>0x7FFFF</resetMask>
57893              <fields>
57894                <field>
57895                  <name>SBCL</name>
57896                  <description>Start of Basic Cycle Interrupt Line</description>
57897                  <bitRange>[0:0]</bitRange>
57898                  <access>read-write</access>
57899                </field>
57900                <field>
57901                  <name>SMCL</name>
57902                  <description>Start of Matrix Cycle Interrupt Line</description>
57903                  <bitRange>[1:1]</bitRange>
57904                  <access>read-write</access>
57905                </field>
57906                <field>
57907                  <name>CSML</name>
57908                  <description>Change of Synchronization Mode Interrupt Line</description>
57909                  <bitRange>[2:2]</bitRange>
57910                  <access>read-write</access>
57911                </field>
57912                <field>
57913                  <name>SOGL</name>
57914                  <description>Start of Gap Interrupt Line</description>
57915                  <bitRange>[3:3]</bitRange>
57916                  <access>read-write</access>
57917                </field>
57918                <field>
57919                  <name>RTMIL</name>
57920                  <description>Register Time Mark Interrupt Line</description>
57921                  <bitRange>[4:4]</bitRange>
57922                  <access>read-write</access>
57923                </field>
57924                <field>
57925                  <name>TTMIL</name>
57926                  <description>Trigger Time Mark Event Internal Line</description>
57927                  <bitRange>[5:5]</bitRange>
57928                  <access>read-write</access>
57929                </field>
57930                <field>
57931                  <name>SWEL</name>
57932                  <description>Stop Watch Event Interrupt Line</description>
57933                  <bitRange>[6:6]</bitRange>
57934                  <access>read-write</access>
57935                </field>
57936                <field>
57937                  <name>GTWL</name>
57938                  <description>Global Time Wrap Interrupt Line</description>
57939                  <bitRange>[7:7]</bitRange>
57940                  <access>read-write</access>
57941                </field>
57942                <field>
57943                  <name>GTDL</name>
57944                  <description>Global Time Discontinuity Interrupt Line</description>
57945                  <bitRange>[8:8]</bitRange>
57946                  <access>read-write</access>
57947                </field>
57948                <field>
57949                  <name>GTEL</name>
57950                  <description>Global Time Error Interrupt Line</description>
57951                  <bitRange>[9:9]</bitRange>
57952                  <access>read-write</access>
57953                </field>
57954                <field>
57955                  <name>TXUL</name>
57956                  <description>Tx Count Underflow Interrupt Line</description>
57957                  <bitRange>[10:10]</bitRange>
57958                  <access>read-write</access>
57959                </field>
57960                <field>
57961                  <name>TXOL</name>
57962                  <description>Tx Count Overflow Interrupt Line</description>
57963                  <bitRange>[11:11]</bitRange>
57964                  <access>read-write</access>
57965                </field>
57966                <field>
57967                  <name>SE1L</name>
57968                  <description>Scheduling Error 1 Interrupt Line</description>
57969                  <bitRange>[12:12]</bitRange>
57970                  <access>read-write</access>
57971                </field>
57972                <field>
57973                  <name>SE2L</name>
57974                  <description>Scheduling Error 2 Interrupt Line</description>
57975                  <bitRange>[13:13]</bitRange>
57976                  <access>read-write</access>
57977                </field>
57978                <field>
57979                  <name>ELCL</name>
57980                  <description>Change Error Level Interrupt Line</description>
57981                  <bitRange>[14:14]</bitRange>
57982                  <access>read-write</access>
57983                </field>
57984                <field>
57985                  <name>IWTL</name>
57986                  <description>Initialization Watch Trigger Interrupt Line</description>
57987                  <bitRange>[15:15]</bitRange>
57988                  <access>read-write</access>
57989                </field>
57990                <field>
57991                  <name>WTL</name>
57992                  <description>Watch Trigger Interrupt Line</description>
57993                  <bitRange>[16:16]</bitRange>
57994                  <access>read-write</access>
57995                </field>
57996                <field>
57997                  <name>AWL_</name>
57998                  <description>Application Watchdog Interrupt Line</description>
57999                  <bitRange>[17:17]</bitRange>
58000                  <access>read-write</access>
58001                </field>
58002                <field>
58003                  <name>CERL</name>
58004                  <description>Configuration Error Interrupt Line</description>
58005                  <bitRange>[18:18]</bitRange>
58006                  <access>read-write</access>
58007                </field>
58008              </fields>
58009            </register>
58010            <register>
58011              <name>TTOST</name>
58012              <description>TT Operation Status</description>
58013              <addressOffset>0x12C</addressOffset>
58014              <size>32</size>
58015              <access>read-only</access>
58016              <resetValue>0x0</resetValue>
58017              <resetMask>0xFFC0FFFF</resetMask>
58018              <fields>
58019                <field>
58020                  <name>EL</name>
58021                  <description>Error Level
5802200= Severity 0 - No Error
5802301= Severity 1 - Warning
5802410= Severity 2 - Error
5802511= Severity 3 - Severe Error</description>
58026                  <bitRange>[1:0]</bitRange>
58027                  <access>read-only</access>
58028                </field>
58029                <field>
58030                  <name>MS</name>
58031                  <description>Master State
5803200= Master_Off, no master properties relevant
5803301= Operating as Time Slave
5803410= Operating as Backup Time Master
5803511= Operating as current Time Master</description>
58036                  <bitRange>[3:2]</bitRange>
58037                  <access>read-only</access>
58038                </field>
58039                <field>
58040                  <name>SYS</name>
58041                  <description>Synchronization State
5804200= Out of Synchronization
5804301= Synchronizing to TTCAN communication
5804410= Schedule suspended by Gap (In_Gap)
5804511= Synchronized to schedule (In_Schedule)</description>
58046                  <bitRange>[5:4]</bitRange>
58047                  <access>read-only</access>
58048                </field>
58049                <field>
58050                  <name>QGTP</name>
58051                  <description>Quality of Global Time Phase
58052Only relevant in TTCAN Level 0 and Level 2, otherwise fixed to '0'.
580530= Global time not valid
580541= Global time in phase with Time Master</description>
58055                  <bitRange>[6:6]</bitRange>
58056                  <access>read-only</access>
58057                </field>
58058                <field>
58059                  <name>QCS</name>
58060                  <description>Quality of Clock Speed
58061Only relevant in TTCAN Level 0 and Level 2, otherwise fixed to '1'.
580620= Local clock speed not synchronized to Time Master clock speed
580631= Synchronization Deviation &lt;= SDL</description>
58064                  <bitRange>[7:7]</bitRange>
58065                  <access>read-only</access>
58066                </field>
58067                <field>
58068                  <name>RTO</name>
58069                  <description>Reference Trigger Offset
58070The Reference Trigger Offset value is a signed integer with a range from -127 (0x81) to 127 (0x7F).
58071There is no notification when the lower limit of -127 is reached. In case the M_TTCAN becomes
58072Time Master (MS[1:0] = '11'), the reset of RTO is delayed due to synchronization between Host and
58073CAN clock domain. For time slaves the value configured by TTOCF.IRTO is read.
580740x00-FF Actual Reference Trigger offset value</description>
58075                  <bitRange>[15:8]</bitRange>
58076                  <access>read-only</access>
58077                </field>
58078                <field>
58079                  <name>WGTD</name>
58080                  <description>Wait for Global Time Discontinuity
580810= No global time preset pending
580821= Node waits for the global time preset to take effect. The bit is reset when the node has transmitted
58083a reference message with Disc_Bit = '1' or after it received a reference message.</description>
58084                  <bitRange>[22:22]</bitRange>
58085                  <access>read-only</access>
58086                </field>
58087                <field>
58088                  <name>GFI</name>
58089                  <description>Gap Finished Indicator
58090Set when the CPU writes TTOCN.FGP, or by a time mark interrupt if TMG = '1', or via input pin
58091m_ttcan_evt if TTOCN.GCS = '1'. Not set by Ref_Trigger_Gap or when Gap is finished by another
58092node sending a reference message.
580930= Reset at the end of each reference message
580941= Gap finished by M_TTCAN</description>
58095                  <bitRange>[23:23]</bitRange>
58096                  <access>read-only</access>
58097                </field>
58098                <field>
58099                  <name>TMP</name>
58100                  <description>Time Master Priority
581010x0-7 Priority of actual Time Master</description>
58102                  <bitRange>[26:24]</bitRange>
58103                  <access>read-only</access>
58104                </field>
58105                <field>
58106                  <name>GSI</name>
58107                  <description>Gap Started Indicator
581080= No Gap in schedule, reset by each reference message and for all time slaves
581091= Gap time after Basic Cycle has started</description>
58110                  <bitRange>[27:27]</bitRange>
58111                  <access>read-only</access>
58112                </field>
58113                <field>
58114                  <name>WFE</name>
58115                  <description>Wait for Event
581160= No Gap announced, reset by a reference message with Next_is_Gap = '0'
581171= Reference message with Next_is_Gap = '1' received</description>
58118                  <bitRange>[28:28]</bitRange>
58119                  <access>read-only</access>
58120                </field>
58121                <field>
58122                  <name>AWE</name>
58123                  <description>Application Watchdog Event
58124The application watchdog is served by reading TTOST. When the watchdog is not served in time,
58125bit AWE is set, all TTCAN communication is stopped, and the M_TTCAN is set into Bus Monitoring
58126Mode.
581270= Application Watchdog served in time
581281= Failed to serve Application Watchdog in time</description>
58129                  <bitRange>[29:29]</bitRange>
58130                  <access>read-only</access>
58131                </field>
58132                <field>
58133                  <name>WECS</name>
58134                  <description>Wait for External Clock Synchronization
581350= No external clock synchronization pending
581361= Node waits for external clock synchronization to take effect. The bit is reset at the start of the
58137next basic cycle.</description>
58138                  <bitRange>[30:30]</bitRange>
58139                  <access>read-only</access>
58140                </field>
58141                <field>
58142                  <name>SPL</name>
58143                  <description>Schedule Phase Lock
58144The bit is valid only when external synchronization is enabled (TTOCN.ESCN = '1'). In this case it
58145signals that the difference between cycle time configured by TTGTP.CTP and the cycle time at the
58146rising edge at pin m_ttcan_evt is less or equal 9 NTU (see Section 4.11).
581470= Phase outside range
581481= Phase inside range</description>
58149                  <bitRange>[31:31]</bitRange>
58150                  <access>read-only</access>
58151                </field>
58152              </fields>
58153            </register>
58154            <register>
58155              <name>TURNA</name>
58156              <description>TUR Numerator Actual</description>
58157              <addressOffset>0x130</addressOffset>
58158              <size>32</size>
58159              <access>read-only</access>
58160              <resetValue>0x10000</resetValue>
58161              <resetMask>0x3FFFF</resetMask>
58162              <fields>
58163                <field>
58164                  <name>NAV</name>
58165                  <description>N/A</description>
58166                  <bitRange>[17:0]</bitRange>
58167                  <access>read-only</access>
58168                </field>
58169              </fields>
58170            </register>
58171            <register>
58172              <name>TTLGT</name>
58173              <description>TT Local &amp; Global Time</description>
58174              <addressOffset>0x134</addressOffset>
58175              <size>32</size>
58176              <access>read-only</access>
58177              <resetValue>0x0</resetValue>
58178              <resetMask>0xFFFFFFFF</resetMask>
58179              <fields>
58180                <field>
58181                  <name>LT</name>
58182                  <description>Local Time
58183Non-fractional part of local time, incremented once each local NTU (see Section 4.5).
581840x0000-FFFF Local time value of TTCAN node</description>
58185                  <bitRange>[15:0]</bitRange>
58186                  <access>read-only</access>
58187                </field>
58188                <field>
58189                  <name>GT</name>
58190                  <description>Global Time
58191Non-fractional part of the sum of the node's local time and its local offset (see Section 4.5).
581920x0000-FFFF Global time value of TTCAN network</description>
58193                  <bitRange>[31:16]</bitRange>
58194                  <access>read-only</access>
58195                </field>
58196              </fields>
58197            </register>
58198            <register>
58199              <name>TTCTC</name>
58200              <description>TT Cycle Time &amp; Count</description>
58201              <addressOffset>0x138</addressOffset>
58202              <size>32</size>
58203              <access>read-only</access>
58204              <resetValue>0x3F0000</resetValue>
58205              <resetMask>0x3FFFFF</resetMask>
58206              <fields>
58207                <field>
58208                  <name>CT</name>
58209                  <description>Cycle Time
58210Non-fractional part of the difference of the node's local time and Ref_Mark (see Section 4.5).
582110x0000-FFFF Cycle time value of TTCAN Basic Cycle</description>
58212                  <bitRange>[15:0]</bitRange>
58213                  <access>read-only</access>
58214                </field>
58215                <field>
58216                  <name>CC</name>
58217                  <description>Cycle Count
582180x00-3F Number of actual Basic Cycle in the System Matrix</description>
58219                  <bitRange>[21:16]</bitRange>
58220                  <access>read-only</access>
58221                </field>
58222              </fields>
58223            </register>
58224            <register>
58225              <name>TTCPT</name>
58226              <description>TT Capture Time</description>
58227              <addressOffset>0x13C</addressOffset>
58228              <size>32</size>
58229              <access>read-only</access>
58230              <resetValue>0x0</resetValue>
58231              <resetMask>0xFFFF003F</resetMask>
58232              <fields>
58233                <field>
58234                  <name>CCV</name>
58235                  <description>Cycle Count Value
58236Cycle count value captured together with SWV.
582370x00-3F Captured cycle count value</description>
58238                  <bitRange>[5:0]</bitRange>
58239                  <access>read-only</access>
58240                </field>
58241                <field>
58242                  <name>SWV</name>
58243                  <description>Stop Watch Value
58244On a rising/falling edge (as configured via TTOCN.SWP) at the Stop Watch Trigger pin m_ttcan_swt, when TTOCN.SWS is != '00' and TTIR.SWE is '0', the actual time value as selected
58245by TTOCN.SWS (cycle, local, global) is copied to SWV and TTIR.SWE will be set to '1'. Capturing of the next stop watch value is enabled by resetting TTIR.SWE.
582460x0000-FFFF Captured Stop Watch value</description>
58247                  <bitRange>[31:16]</bitRange>
58248                  <access>read-only</access>
58249                </field>
58250              </fields>
58251            </register>
58252            <register>
58253              <name>TTCSM</name>
58254              <description>TT Cycle Sync Mark</description>
58255              <addressOffset>0x140</addressOffset>
58256              <size>32</size>
58257              <access>read-only</access>
58258              <resetValue>0x0</resetValue>
58259              <resetMask>0xFFFF</resetMask>
58260              <fields>
58261                <field>
58262                  <name>CSM</name>
58263                  <description>Cycle Sync Mark
58264The Cycle Sync Mark is measured</description>
58265                  <bitRange>[15:0]</bitRange>
58266                  <access>read-only</access>
58267                </field>
58268              </fields>
58269            </register>
58270          </cluster>
58271          <register>
58272            <name>RXFTOP_CTL</name>
58273            <description>Receive FIFO Top control</description>
58274            <addressOffset>0x180</addressOffset>
58275            <size>32</size>
58276            <access>read-write</access>
58277            <resetValue>0x0</resetValue>
58278            <resetMask>0x3</resetMask>
58279            <fields>
58280              <field>
58281                <name>F0TPE</name>
58282                <description>FIFO 0 Top Pointer Enable.
58283This enables the FIFO top pointer logic to set the FIFO Top Address (FnTA) and message word counter.
58284This logic is also disabled when the IP is being reconfigured (CCCR.CCE=1).
58285When this logic is disabled a Read from RXFTOP0_DATA is undefined.</description>
58286                <bitRange>[0:0]</bitRange>
58287                <access>read-write</access>
58288              </field>
58289              <field>
58290                <name>F1TPE</name>
58291                <description>FIFO 1 Top Pointer Enable.</description>
58292                <bitRange>[1:1]</bitRange>
58293                <access>read-write</access>
58294              </field>
58295            </fields>
58296          </register>
58297          <register>
58298            <name>RXFTOP0_STAT</name>
58299            <description>Receive FIFO 0 Top Status</description>
58300            <addressOffset>0x1A0</addressOffset>
58301            <size>32</size>
58302            <access>read-only</access>
58303            <resetValue>0x0</resetValue>
58304            <resetMask>0xFFFF</resetMask>
58305            <fields>
58306              <field>
58307                <name>F0TA</name>
58308                <description>Current FIFO 0 Top Address.
58309This is a pointer to the next word in the message buffer defined by the FIFO Start Address (FnSA), Get Index (FnGI), the FIFO message size (FnDS) and the message word counter (FnMWC)
58310FnTA = FnSA + FnGI * msg_size[FnDS] + FnMWC</description>
58311                <bitRange>[15:0]</bitRange>
58312                <access>read-only</access>
58313              </field>
58314            </fields>
58315          </register>
58316          <register>
58317            <name>RXFTOP0_DATA</name>
58318            <description>Receive FIFO 0 Top Data</description>
58319            <addressOffset>0x1A8</addressOffset>
58320            <size>32</size>
58321            <access>read-only</access>
58322            <resetValue>0x0</resetValue>
58323            <resetMask>0x0</resetMask>
58324            <fields>
58325              <field>
58326                <name>F0TD</name>
58327                <description>When enabled (F0TPE=1) read data from MRAM at location FnTA. This register can have a read side effect if the following conditions are met:
58328- M_TTCAN not being reconfigured (CCCR.CCE=0)
58329- FIFO Top Pointer logic is enabled (FnTPE=1)
58330- FIFO is not empty (FnFL!=0)
58331The read side effect is as follows:
58332- if FnMWC pointed to the last word of the message (as indicated by FnDS) then the corresponding message index (FnGI) is automatically acknowledge by a write to FnAI
58333- FnMWC is incremented (or restarted if FnMWC pointed to the last word of the message)
58334- the FIFO top address FnTA is incremented (with FIFO wrap around)
58335When this logic is disabled (F0TPE=0) a Read from this register returns undefined data.</description>
58336                <bitRange>[31:0]</bitRange>
58337                <access>read-only</access>
58338              </field>
58339            </fields>
58340          </register>
58341          <register>
58342            <name>RXFTOP1_STAT</name>
58343            <description>Receive FIFO 1 Top Status</description>
58344            <addressOffset>0x1B0</addressOffset>
58345            <size>32</size>
58346            <access>read-only</access>
58347            <resetValue>0x0</resetValue>
58348            <resetMask>0xFFFF</resetMask>
58349            <fields>
58350              <field>
58351                <name>F1TA</name>
58352                <description>See F0TA description</description>
58353                <bitRange>[15:0]</bitRange>
58354                <access>read-only</access>
58355              </field>
58356            </fields>
58357          </register>
58358          <register>
58359            <name>RXFTOP1_DATA</name>
58360            <description>Receive FIFO 1 Top Data</description>
58361            <addressOffset>0x1B8</addressOffset>
58362            <size>32</size>
58363            <access>read-only</access>
58364            <resetValue>0x0</resetValue>
58365            <resetMask>0x0</resetMask>
58366            <fields>
58367              <field>
58368                <name>F1TD</name>
58369                <description>See F0TD description</description>
58370                <bitRange>[31:0]</bitRange>
58371                <access>read-only</access>
58372              </field>
58373            </fields>
58374          </register>
58375        </cluster>
58376        <register>
58377          <name>CTL</name>
58378          <description>Global CAN control register</description>
58379          <addressOffset>0x1000</addressOffset>
58380          <size>32</size>
58381          <access>read-write</access>
58382          <resetValue>0x0</resetValue>
58383          <resetMask>0x800000FF</resetMask>
58384          <fields>
58385            <field>
58386              <name>STOP_REQ</name>
58387              <description>Clock Stop Request for each TTCAN IP .
58388The m_ttcan_clkstop_req of each TTCAN IP is directly driven by these bits.</description>
58389              <bitRange>[7:0]</bitRange>
58390              <access>read-write</access>
58391            </field>
58392            <field>
58393              <name>MRAM_OFF</name>
58394              <description>MRAM off
583950= Default MRAM on (with MRAM retained in DeepSleep).
583961= Switch MRAM off (not retained) to save power. Before setting this bit all the CAN channels have to be powered down using the STOP_REQ/ACK bits.
58397When the MRAM is off any access attempt to it is considered an address error (as if MRAM_SIZE=0).
58398After switching the MRAM on again software needs to allow for a certain power up time before MRAM can be used, i.e. before STOP_REQ can be de-asserted. The power up time is equivalent to the system SRAM power up time specified in the CPUSS.RAM_PWR_DELAY_CTL register.
58399
58400To meet S8 platform requirements, MRAM_OFF should be set to 0 prior to transitioning to Hibernate mode.</description>
58401              <bitRange>[31:31]</bitRange>
58402              <access>read-write</access>
58403            </field>
58404          </fields>
58405        </register>
58406        <register>
58407          <name>STATUS</name>
58408          <description>Global CAN status register</description>
58409          <addressOffset>0x1004</addressOffset>
58410          <size>32</size>
58411          <access>read-only</access>
58412          <resetValue>0x0</resetValue>
58413          <resetMask>0xFF</resetMask>
58414          <fields>
58415            <field>
58416              <name>STOP_ACK</name>
58417              <description>Clock Stop Acknowledge for each TTCAN IP.
58418These bits are directly driven by m_ttcan_clkstop_ack of each TTCAN IP.
58419When this bit is set the corresponding TTCAN IP clocks will be gated off, except HCLK will enabled for each AHB write</description>
58420              <bitRange>[7:0]</bitRange>
58421              <access>read-only</access>
58422            </field>
58423          </fields>
58424        </register>
58425        <register>
58426          <name>INTR0_CAUSE</name>
58427          <description>Consolidated interrupt0 cause register</description>
58428          <addressOffset>0x1010</addressOffset>
58429          <size>32</size>
58430          <access>read-only</access>
58431          <resetValue>0x0</resetValue>
58432          <resetMask>0xFF</resetMask>
58433          <fields>
58434            <field>
58435              <name>INT0</name>
58436              <description>Show pending m_ttcan_int0 of each channel</description>
58437              <bitRange>[7:0]</bitRange>
58438              <access>read-only</access>
58439            </field>
58440          </fields>
58441        </register>
58442        <register>
58443          <name>INTR1_CAUSE</name>
58444          <description>Consolidated interrupt1 cause register</description>
58445          <addressOffset>0x1014</addressOffset>
58446          <size>32</size>
58447          <access>read-only</access>
58448          <resetValue>0x0</resetValue>
58449          <resetMask>0xFF</resetMask>
58450          <fields>
58451            <field>
58452              <name>INT1</name>
58453              <description>Show pending m_ttcan_int1 of each channel</description>
58454              <bitRange>[7:0]</bitRange>
58455              <access>read-only</access>
58456            </field>
58457          </fields>
58458        </register>
58459        <register>
58460          <name>TS_CTL</name>
58461          <description>Time Stamp control register</description>
58462          <addressOffset>0x1020</addressOffset>
58463          <size>32</size>
58464          <access>read-write</access>
58465          <resetValue>0x0</resetValue>
58466          <resetMask>0x8000FFFF</resetMask>
58467          <fields>
58468            <field>
58469              <name>PRESCALE</name>
58470              <description>Time Stamp counter prescale value.
58471When enabled divide the Host clock (HCLK) by PRESCALE+1 to create Time Stamp clock ticks.</description>
58472              <bitRange>[15:0]</bitRange>
58473              <access>read-write</access>
58474            </field>
58475            <field>
58476              <name>ENABLED</name>
58477              <description>Counter enable bit
584780 = Count disabled. Stop counting up and keep the counter value
584791 = Count enabled. Start counting up from the current value</description>
58480              <bitRange>[31:31]</bitRange>
58481              <access>read-write</access>
58482            </field>
58483          </fields>
58484        </register>
58485        <register>
58486          <name>TS_CNT</name>
58487          <description>Time Stamp counter value</description>
58488          <addressOffset>0x1024</addressOffset>
58489          <size>32</size>
58490          <access>read-write</access>
58491          <resetValue>0x0</resetValue>
58492          <resetMask>0xFFFF</resetMask>
58493          <fields>
58494            <field>
58495              <name>VALUE</name>
58496              <description>The counter value of the Time Stamp Counter.
58497When enabled this counter will count Time Stamp clock ticks from the pre-scaler.
58498When written this counter and the pre-scaler will reset to 0 (write data is ignored).</description>
58499              <bitRange>[15:0]</bitRange>
58500              <access>read-write</access>
58501            </field>
58502          </fields>
58503        </register>
58504        <register>
58505          <name>ECC_CTL</name>
58506          <description>ECC control</description>
58507          <addressOffset>0x1080</addressOffset>
58508          <size>32</size>
58509          <access>read-write</access>
58510          <resetValue>0x0</resetValue>
58511          <resetMask>0x10000</resetMask>
58512          <fields>
58513            <field>
58514              <name>ECC_EN</name>
58515              <description>Enable ECC for CANFD SRAM
58516When disabled also all error injection functionality is disabled.</description>
58517              <bitRange>[16:16]</bitRange>
58518              <access>read-write</access>
58519            </field>
58520          </fields>
58521        </register>
58522        <register>
58523          <name>ECC_ERR_INJ</name>
58524          <description>ECC error injection</description>
58525          <addressOffset>0x1084</addressOffset>
58526          <size>32</size>
58527          <access>read-write</access>
58528          <resetValue>0xFFFC</resetValue>
58529          <resetMask>0x7F10FFFC</resetMask>
58530          <fields>
58531            <field>
58532              <name>ERR_ADDR</name>
58533              <description>Specifies the address of the word where an error will be injected on write or an non-correctable error will be suppressed.
58534When the ERR_EN bit is set an error parity (ERR_PAR) is injected when any write, from bus or a CAN channel, is done to this address.
58535When the ERR_EN bit is set and the access address matches ERR_ADDR then a non-correctable ECC error or an Address error will NOT result in a bus error or CAN channel shutdown.
58536Note that error reporting to the fault structure cannot be suppressed.</description>
58537              <bitRange>[15:2]</bitRange>
58538              <access>read-write</access>
58539            </field>
58540            <field>
58541              <name>ERR_EN</name>
58542              <description>Enable error injection (ECC_EN must be 1).
58543When this bit is set the error parity (ERR_PAR) will be used when an AHB write is done to the ERR_ADDR address.
58544When the error word is read a single or double error will be reported to the fault structure just like for a real ECC error (even if this bit is no longer set).
58545When this bit is set (and ECC_EN=1) a non-correctable error (ECC or address error) for the ERR_ADDR will not be reported back to the CAN channel or  AHB bus.</description>
58546              <bitRange>[20:20]</bitRange>
58547              <access>read-write</access>
58548            </field>
58549            <field>
58550              <name>ERR_PAR</name>
58551              <description>ECC Parity bits to use for ECC error injection at address ERR_ADDR.</description>
58552              <bitRange>[30:24]</bitRange>
58553              <access>read-write</access>
58554            </field>
58555          </fields>
58556        </register>
58557      </registers>
58558    </peripheral>
58559    <peripheral>
58560      <name>TDM0</name>
58561      <description>TDM</description>
58562      <headerStructName>TDM</headerStructName>
58563      <baseAddress>0x405A0000</baseAddress>
58564      <addressBlock>
58565        <offset>0</offset>
58566        <size>65536</size>
58567        <usage>registers</usage>
58568      </addressBlock>
58569      <registers>
58570        <cluster>
58571          <name>TDM_STRUCT</name>
58572          <description>TDM structure</description>
58573          <addressOffset>0x00008000</addressOffset>
58574          <cluster>
58575            <name>TDM_TX_STRUCT</name>
58576            <description>TDM TX structure</description>
58577            <addressOffset>0x00000000</addressOffset>
58578            <register>
58579              <name>TX_CTL</name>
58580              <description>TX control</description>
58581              <addressOffset>0x0</addressOffset>
58582              <size>32</size>
58583              <access>read-write</access>
58584              <resetValue>0x10000</resetValue>
58585              <resetMask>0x8001300F</resetMask>
58586              <fields>
58587                <field>
58588                  <name>WORD_SIZE</name>
58589                  <description>PCM word size:
58590'0': 8 bit.
58591'1': 10 bit.
58592'2': 12 bit.
58593'3': 14 bit.
58594'4': 16 bit.
58595'5': 18 bit.
58596'6': 20 bit.
58597'7': 24 bit.
58598'8': 32 bit.
58599'9'-'15': Undefined.</description>
58600                  <bitRange>[3:0]</bitRange>
58601                  <access>read-write</access>
58602                  <enumeratedValues>
58603                    <enumeratedValue>
58604                      <name>SIZE_8</name>
58605                      <description>N/A</description>
58606                      <value>0</value>
58607                    </enumeratedValue>
58608                    <enumeratedValue>
58609                      <name>SIZE_10</name>
58610                      <description>N/A</description>
58611                      <value>1</value>
58612                    </enumeratedValue>
58613                    <enumeratedValue>
58614                      <name>SIZE_12</name>
58615                      <description>N/A</description>
58616                      <value>2</value>
58617                    </enumeratedValue>
58618                    <enumeratedValue>
58619                      <name>SIZE_14</name>
58620                      <description>N/A</description>
58621                      <value>3</value>
58622                    </enumeratedValue>
58623                    <enumeratedValue>
58624                      <name>SIZE_16</name>
58625                      <description>N/A</description>
58626                      <value>4</value>
58627                    </enumeratedValue>
58628                    <enumeratedValue>
58629                      <name>SIZE_18</name>
58630                      <description>N/A</description>
58631                      <value>5</value>
58632                    </enumeratedValue>
58633                    <enumeratedValue>
58634                      <name>SIZE_20</name>
58635                      <description>N/A</description>
58636                      <value>6</value>
58637                    </enumeratedValue>
58638                    <enumeratedValue>
58639                      <name>SIZE_24</name>
58640                      <description>N/A</description>
58641                      <value>7</value>
58642                    </enumeratedValue>
58643                    <enumeratedValue>
58644                      <name>SIZE_32</name>
58645                      <description>N/A</description>
58646                      <value>8</value>
58647                    </enumeratedValue>
58648                  </enumeratedValues>
58649                </field>
58650                <field>
58651                  <name>FORMAT</name>
58652                  <description>Format:
58653'0': Left-aligned delayed.
58654'1': Left-aligned.
58655'2': Right-aligned delayed.
58656'3': Right-aligned.</description>
58657                  <bitRange>[13:12]</bitRange>
58658                  <access>read-write</access>
58659                  <enumeratedValues>
58660                    <enumeratedValue>
58661                      <name>LEFT_DELAYED</name>
58662                      <description>N/A</description>
58663                      <value>0</value>
58664                    </enumeratedValue>
58665                    <enumeratedValue>
58666                      <name>LEFT</name>
58667                      <description>N/A</description>
58668                      <value>1</value>
58669                    </enumeratedValue>
58670                    <enumeratedValue>
58671                      <name>RIGHT_DELAYED</name>
58672                      <description>N/A</description>
58673                      <value>2</value>
58674                    </enumeratedValue>
58675                    <enumeratedValue>
58676                      <name>RIGHT</name>
58677                      <description>N/A</description>
58678                      <value>3</value>
58679                    </enumeratedValue>
58680                  </enumeratedValues>
58681                </field>
58682                <field>
58683                  <name>MS</name>
58684                  <description>Master/slave setting:
58685'0': Slave.
58686- External transmitter 'tdm_tx_sck_in' and transmitter 'tdm_tx_fsync_in'.
58687'1': Master.
58688- Interface clock 'clk_if' is used to generate transmitter 'tdm_tx_sck_out' and transmitter 'tdm_tx_fsync_out'.</description>
58689                  <bitRange>[16:16]</bitRange>
58690                  <access>read-write</access>
58691                  <enumeratedValues>
58692                    <enumeratedValue>
58693                      <name>SLAVE</name>
58694                      <description>N/A</description>
58695                      <value>0</value>
58696                    </enumeratedValue>
58697                    <enumeratedValue>
58698                      <name>MASTER</name>
58699                      <description>N/A</description>
58700                      <value>1</value>
58701                    </enumeratedValue>
58702                  </enumeratedValues>
58703                </field>
58704                <field>
58705                  <name>ENABLED</name>
58706                  <description>Transmitter (TX) enable:
58707'0': Disabled. All non-retained MMIO registers (e.g. the TX_FIFO_STATUS and INTR_TX registers) have their fields reset to their default value.
58708'1': Enabled.
58709
58710Note: when all transmitters and receivers are disabled, the SRAMs are driven into low power mode, if supported by the SRAM. When exiting such low power mode software needs to allow for a certain power up time before SRAM can be used, i.e. before ACTIVE can be asserted. The power up time is equivalent to the system SRAM power up time specified in the CPUSS.RAM_PWR_DELAY_CTL register (or equivalent for platforms other than MXS40).</description>
58711                  <bitRange>[31:31]</bitRange>
58712                  <access>read-write</access>
58713                </field>
58714              </fields>
58715            </register>
58716            <register>
58717              <name>TX_IF_CTL</name>
58718              <description>TX interface control</description>
58719              <addressOffset>0x10</addressOffset>
58720              <size>32</size>
58721              <access>read-write</access>
58722              <resetValue>0x1F018707</resetValue>
58723              <resetMask>0x9F1FB7FF</resetMask>
58724              <fields>
58725                <field>
58726                  <name>CLOCK_DIV</name>
58727                  <description>Interface clock divider (legal range [1, 255]). The TDM interface 'tdm_tx_sck_out' output signal is defined as clk_if / (CLOCK_DIV + 1). CLOCK_DIV should be set to an odd value ({1, 3, 5, ..., 255}), to ensure a 50/50 percent duty cycle  clock.
58728
58729Note: Used in master configuration only.</description>
58730                  <bitRange>[7:0]</bitRange>
58731                  <access>read-write</access>
58732                </field>
58733                <field>
58734                  <name>CLOCK_SEL</name>
58735                  <description>Interface clock 'clk_if' selection:
58736'0': SRSS clock clk_if_srss[0].
58737'1': SRSS clock clk_if_srss[1].
58738'2': SRSS clock clk_if_srss[2].
58739'3': SRSS clock clk_if_srss[3].
58740'4': Master interface clock 'tdm_tx_mck_in'.
58741'5'-'7': undefined.
58742
58743Note: the application is always required to program this field to a value different from the default.</description>
58744                  <bitRange>[10:8]</bitRange>
58745                  <access>read-write</access>
58746                  <enumeratedValues>
58747                    <enumeratedValue>
58748                      <name>SEL_SRSS_CLOCK0</name>
58749                      <description>N/A</description>
58750                      <value>0</value>
58751                    </enumeratedValue>
58752                    <enumeratedValue>
58753                      <name>SEL_SRSS_CLOCK1</name>
58754                      <description>N/A</description>
58755                      <value>1</value>
58756                    </enumeratedValue>
58757                    <enumeratedValue>
58758                      <name>SEL_SRSS_CLOCK2</name>
58759                      <description>N/A</description>
58760                      <value>2</value>
58761                    </enumeratedValue>
58762                    <enumeratedValue>
58763                      <name>SEL_SRSS_CLOCK3</name>
58764                      <description>N/A</description>
58765                      <value>3</value>
58766                    </enumeratedValue>
58767                    <enumeratedValue>
58768                      <name>SEL_TDM_TX_MCK_IN</name>
58769                      <description>N/A</description>
58770                      <value>4</value>
58771                    </enumeratedValue>
58772                  </enumeratedValues>
58773                </field>
58774                <field>
58775                  <name>SCK_POLARITY</name>
58776                  <description>Clock polarity:
58777'0': Clock signal is used 'as is'.
58778'1': Clock signal is inverted.
58779
58780Note: Used in BOTH master and slave configurations.</description>
58781                  <bitRange>[12:12]</bitRange>
58782                  <access>read-write</access>
58783                </field>
58784                <field>
58785                  <name>FSYNC_POLARITY</name>
58786                  <description>Channel synchronization polarity:
58787'0': Channel synchronization signal is used 'as is'.
58788'1': Channel synchronization signal is inverted.
58789
58790Note: Used in BOTH master and slave configurations.</description>
58791                  <bitRange>[13:13]</bitRange>
58792                  <access>read-write</access>
58793                </field>
58794                <field>
58795                  <name>FSYNC_FORMAT</name>
58796                  <description>Channel synchronization pulse format:
58797'0': Duration of a single bit period.
58798'1': Duration of the first channel.</description>
58799                  <bitRange>[15:15]</bitRange>
58800                  <access>read-write</access>
58801                  <enumeratedValues>
58802                    <enumeratedValue>
58803                      <name>BIT_PERIOD</name>
58804                      <description>N/A</description>
58805                      <value>0</value>
58806                    </enumeratedValue>
58807                    <enumeratedValue>
58808                      <name>CH_PERIOD</name>
58809                      <description>N/A</description>
58810                      <value>1</value>
58811                    </enumeratedValue>
58812                  </enumeratedValues>
58813                </field>
58814                <field>
58815                  <name>CH_NR</name>
58816                  <description>Number of channels in the frame:
58817'0': Undefined/illegal.
58818'1': 2 channels.
58819'2': 3 channels.
58820...
58821'31': 32 channels.
58822
58823Note: the field value chould be less than CH_NR (the number of support channels).
58824
58825Note: the TX_CH_CTL.CH_EN fields can be used to enable/disable indvidual channels.</description>
58826                  <bitRange>[20:16]</bitRange>
58827                  <access>read-write</access>
58828                </field>
58829                <field>
58830                  <name>CH_SIZE</name>
58831                  <description>Channel size:
58832'0'-'2': Undefined/illegal.
58833'3': 4 bits.
58834...
58835'31': 32 bits.
58836
58837Note: if TX_CTL.WORD_SIZE is greater than CH_SIZE, the more significant bits of the word are transmitted and the lesser significant bits of the word are dropped.</description>
58838                  <bitRange>[28:24]</bitRange>
58839                  <access>read-write</access>
58840                  <enumeratedValues>
58841                    <enumeratedValue>
58842                      <name>SIZE_1</name>
58843                      <description>N/A</description>
58844                      <value>0</value>
58845                    </enumeratedValue>
58846                    <enumeratedValue>
58847                      <name>SIZE_2</name>
58848                      <description>N/A</description>
58849                      <value>1</value>
58850                    </enumeratedValue>
58851                    <enumeratedValue>
58852                      <name>SIZE_32</name>
58853                      <description>N/A</description>
58854                      <value>31</value>
58855                    </enumeratedValue>
58856                  </enumeratedValues>
58857                </field>
58858                <field>
58859                  <name>I2S_MODE</name>
58860                  <description>I2S mode setting:
58861'0': TDM mode.
58862'1': I2S mode.</description>
58863                  <bitRange>[31:31]</bitRange>
58864                  <access>read-write</access>
58865                  <enumeratedValues>
58866                    <enumeratedValue>
58867                      <name>TDM</name>
58868                      <description>N/A</description>
58869                      <value>0</value>
58870                    </enumeratedValue>
58871                    <enumeratedValue>
58872                      <name>I2S</name>
58873                      <description>N/A</description>
58874                      <value>1</value>
58875                    </enumeratedValue>
58876                  </enumeratedValues>
58877                </field>
58878              </fields>
58879            </register>
58880            <register>
58881              <name>TX_CH_CTL</name>
58882              <description>TX channel control</description>
58883              <addressOffset>0x14</addressOffset>
58884              <size>32</size>
58885              <access>read-write</access>
58886              <resetValue>0x0</resetValue>
58887              <resetMask>0xFFFFFFFF</resetMask>
58888              <fields>
58889                <field>
58890                  <name>CH_EN</name>
58891                  <description>Channel enables: channel i is controlled by CH_EN[i].
58892'0': Disabled. The TX FIFO does not produce channel i words and the transmitted channel i words on the interface are not driven (the output enable of the 'tdm_tx_sd_out' output signal is not driven).
58893'1': Enabled.
58894
58895Note: Only bit 0 through TX_IF_CTL.CH_NR may be set to '1'; i.e. only channels that are present in the frame can be enabled.</description>
58896                  <bitRange>[31:0]</bitRange>
58897                  <access>read-write</access>
58898                </field>
58899              </fields>
58900            </register>
58901            <register>
58902              <name>TX_TEST_CTL</name>
58903              <description>TX test control</description>
58904              <addressOffset>0x20</addressOffset>
58905              <size>32</size>
58906              <access>read-write</access>
58907              <resetValue>0x0</resetValue>
58908              <resetMask>0x80000000</resetMask>
58909              <fields>
58910                <field>
58911                  <name>ENABLED</name>
58912                  <description>Test mode enable.
58913'0': Disabled. Functional mode.
58914- Transmitter tx_sck_in = IOSS tdm_tx_sck_in.
58915- Transmitter tx_fsync_in = IOSS tdm_tx_fsync_in.
58916- Receiver rx_sd_in = IOSS tdm_rx_sd_in.
58917'1': Enabled. Test mode (intended to be used with (slave transmitter, master receiver) configuration).
58918- Transmitter tx_sck_in = Receiver tdm_rx_sck_out.
58919- Transmitter tx_fsync_in = Receiver tdm_rx_fsync_out.
58920- Receiver rx_sd_in = Transmitter tdm_tx_sd_out.
58921
58922Note: TX_TEST_CTL.ENABLED and RX_TEST_CTL.ENABLED should not be set to '1' simultaneously.</description>
58923                  <bitRange>[31:31]</bitRange>
58924                  <access>read-write</access>
58925                  <enumeratedValues>
58926                    <enumeratedValue>
58927                      <name>FUNCTIONAL</name>
58928                      <description>N/A</description>
58929                      <value>0</value>
58930                    </enumeratedValue>
58931                    <enumeratedValue>
58932                      <name>TEST</name>
58933                      <description>N/A</description>
58934                      <value>1</value>
58935                    </enumeratedValue>
58936                  </enumeratedValues>
58937                </field>
58938              </fields>
58939            </register>
58940            <register>
58941              <name>TX_ROUTE_CTL</name>
58942              <description>TX route control</description>
58943              <addressOffset>0x24</addressOffset>
58944              <size>32</size>
58945              <access>read-write</access>
58946              <resetValue>0x0</resetValue>
58947              <resetMask>0x3</resetMask>
58948              <fields>
58949                <field>
58950                  <name>MODE</name>
58951                  <description>Controls routing to the TX slave signalling inputs (FSYNC/SCK):
58952'0': TX slave signaling indipendent from RX signaling:
58953- Transmitter tx_sck_in = IOSS tdm_tx_sck_in
58954- Transmitter tx_fsync_in = IOSS tdm_tx_fsync_in
58955'1': TX slave signalling inputs driven by RX Slave:
58956- Transmitter tx_sck_in = IOSS tdm_rx_sck_in
58957- Transmitter tx_fsync_in = IOSS tdm_rx_fsync_in
58958'2': TX slave signalling inputs driven by RX Master:
58959- Transmitter tx_sck_in = receiver tdm_rx_sck_out
58960- Transmitter tx_fsync_in = receiver tdm_rx_fsync_out
58961
58962Note: MODE=0 is the default behaviour. MODE=1 or 2 is intended to allow the TX slave to share the same signaling used by the RX. This feature can be used to reduce the number of IO pins necessary to connect to an external codec supporting common TX/RX signaling.
58963
58964Note: when MODE=1 or 2, TX_TEST_CTL.ENABLED and RX_TEST_CTL.ENABLED should not be set to '1'.</description>
58965                  <bitRange>[1:0]</bitRange>
58966                  <access>read-write</access>
58967                  <enumeratedValues>
58968                    <enumeratedValue>
58969                      <name>TX_IN_DRIVEN_BY_IOSS_TX_IN</name>
58970                      <description>N/A</description>
58971                      <value>0</value>
58972                    </enumeratedValue>
58973                    <enumeratedValue>
58974                      <name>TX_IN_DRIVEN_BY_IOSS_RX_IN</name>
58975                      <description>N/A</description>
58976                      <value>1</value>
58977                    </enumeratedValue>
58978                    <enumeratedValue>
58979                      <name>TX_IN_DRIVEN_BY_RX_OUT</name>
58980                      <description>N/A</description>
58981                      <value>2</value>
58982                    </enumeratedValue>
58983                  </enumeratedValues>
58984                </field>
58985              </fields>
58986            </register>
58987            <register>
58988              <name>TX_FIFO_CTL</name>
58989              <description>TX FIFO control</description>
58990              <addressOffset>0x80</addressOffset>
58991              <size>32</size>
58992              <access>read-write</access>
58993              <resetValue>0x0</resetValue>
58994              <resetMask>0xF007F</resetMask>
58995              <fields>
58996                <field>
58997                  <name>TRIGGER_LEVEL</name>
58998                  <description>Trigger level. When the TX FIFO has less entries than the number of this field, a transmitter trigger event is generated:
58999- INTR_TX.FIFO_TRIGGER = (# FIFO entries &lt; TRIGGER_LEVEL)</description>
59000                  <bitRange>[6:0]</bitRange>
59001                  <access>read-write</access>
59002                </field>
59003                <field>
59004                  <name>MUTE</name>
59005                  <description>Mute functionality:
59006'0': HW uses TX FIFO data.
59007'1': HW uses a constant PCM data value of '0'. Mute does advance the FIFO read pointer.
59008
59009Note: HW ensures that mute functionality synchronizes on the first channel of a frame to ensure that either all or none of the frame's channels are muted.</description>
59010                  <bitRange>[16:16]</bitRange>
59011                  <access>read-write</access>
59012                </field>
59013                <field>
59014                  <name>FREEZE</name>
59015                  <description>Freeze functionality:
59016'0': HW uses TX FIFO data and advances the FIFO read pointer.
59017'1': HW uses a constant PCM data value of '0' or the previous channel PCM data is replayed. Freeze does not advance the FIFO read pointer (the FIFO data is not used).
59018
59019Note: HW ensures that freeze functionality synchronizes on the first channel of a frame to ensure that PCM data of one channel is not misassigned to another channel. As a result, the freeze functionality can be activated at any time.
59020
59021Note: This functionality is intended for debugging purposes.</description>
59022                  <bitRange>[17:17]</bitRange>
59023                  <access>read-write</access>
59024                </field>
59025                <field>
59026                  <name>ACTIVE</name>
59027                  <description>Activate functionality:
59028'0': Transmitter off. The FIFO_UNDERFLOW interrupt cause will not be activated.
59029'1': Transmitter on. The FIFO_UNDERFLOW interrupt may be activated (when an underflow event occurs).
59030
59031Note: This functionality is intended for startup purposes.</description>
59032                  <bitRange>[18:18]</bitRange>
59033                  <access>read-write</access>
59034                </field>
59035                <field>
59036                  <name>REPLAY</name>
59037                  <description>Replay functionality (used when FREEZE is '1' or in case of a FIFO underflow event):
59038'0': HW uses a constant PCM data value of '0'.
59039'1': HW uses the previous PCM data value.</description>
59040                  <bitRange>[19:19]</bitRange>
59041                  <access>read-write</access>
59042                </field>
59043              </fields>
59044            </register>
59045            <register>
59046              <name>TX_FIFO_STATUS</name>
59047              <description>TX FIFO status</description>
59048              <addressOffset>0x84</addressOffset>
59049              <size>32</size>
59050              <access>read-only</access>
59051              <resetValue>0x0</resetValue>
59052              <resetMask>0x7F7F00FF</resetMask>
59053              <fields>
59054                <field>
59055                  <name>USED</name>
59056                  <description>Number of used/occupied entries in the TX FIFO. The field value is in the range [0, 128]. When '0', the FIFO is empty. When '128', the FIFO is full.</description>
59057                  <bitRange>[7:0]</bitRange>
59058                  <access>read-only</access>
59059                </field>
59060                <field>
59061                  <name>RD_PTR</name>
59062                  <description>TX FIFO read pointer: FIFO location from which a data is read.
59063
59064Note: This functionality is intended for debugging purposes.</description>
59065                  <bitRange>[22:16]</bitRange>
59066                  <access>read-only</access>
59067                </field>
59068                <field>
59069                  <name>WR_PTR</name>
59070                  <description>TX FIFO write pointer: FIFO location at which a new data is written by the hardware.
59071
59072Note: This functionality is intended for debugging purposes.</description>
59073                  <bitRange>[30:24]</bitRange>
59074                  <access>read-only</access>
59075                </field>
59076              </fields>
59077            </register>
59078            <register>
59079              <name>TX_FIFO_WR</name>
59080              <description>TX FIFO write</description>
59081              <addressOffset>0x88</addressOffset>
59082              <size>32</size>
59083              <access>write-only</access>
59084              <resetValue>0x0</resetValue>
59085              <resetMask>0xFFFFFFFF</resetMask>
59086              <fields>
59087                <field>
59088                  <name>DATA</name>
59089                  <description>Data (PCM sample) written to the TX FIFO. Writing adds the data to the TX FIFO; i.e. behavior is similar to that of a PUSH operation (TX_FIFO_STATUS.WR_PTR is incremented and TX_FIFO_STATUS.USED is incremented). The write data (DATA) should be right aligned when it is written to the FIFO entry (data[31:0]):
59090- 8 bit, data[31:0] = DATA[7:0] &lt;&lt; 24.
59091- 10 bit, data[31:0] = DATA[9:0] &lt;&lt; 22.
59092- 12 bit, data[31:0] = DATA[11:0] &lt;&lt; 20.
59093- 14 bit, data[31:0] = DATA[13:0] &lt;&lt; 18.
59094- 16 bit, data[31:0] = DATA[15:0] &lt;&lt; 16.
59095- 18 bit, data[31:0] = DATA[17:0] &lt;&lt; 14.
59096- 20 bit, data[31:0] = DATA[19:0] &lt;&lt; 12.
59097- 24 bit, data[31:0] = DATA[23:0] &lt;&lt; 8.
59098- 32 bit, data[31:0] = DATA[31:0].
59099
59100Note: Writing to a full TX FIFO activates INTR.TX_FIFO_OVERFLOW.</description>
59101                  <bitRange>[31:0]</bitRange>
59102                  <access>write-only</access>
59103                </field>
59104              </fields>
59105            </register>
59106            <register>
59107              <name>INTR_TX</name>
59108              <description>Interrupt</description>
59109              <addressOffset>0xC0</addressOffset>
59110              <size>32</size>
59111              <access>read-write</access>
59112              <resetValue>0x0</resetValue>
59113              <resetMask>0x107</resetMask>
59114              <fields>
59115                <field>
59116                  <name>FIFO_TRIGGER</name>
59117                  <description>HW sets this field to '1', when a TX trigger is generated.</description>
59118                  <bitRange>[0:0]</bitRange>
59119                  <access>read-write</access>
59120                </field>
59121                <field>
59122                  <name>FIFO_OVERFLOW</name>
59123                  <description>HW sets this field to '1', when writing to a full TX FIFO (TX_FIFO_STATUS.USED is '128').</description>
59124                  <bitRange>[1:1]</bitRange>
59125                  <access>read-write</access>
59126                </field>
59127                <field>
59128                  <name>FIFO_UNDERFLOW</name>
59129                  <description>HW sets this field to '1', when reading from an (almost) empty TX FIFO (TX_FIFO_STATUS.USED &lt; 'number of enabled channels per frame'). This is referred to as an underflow event.
59130
59131Note: HW ensures that either all or none of the frame's channels are transmitted. In a TX FIFO underflow situation, HW replays previous PCM data or uses a constant PCM data value of '0'.</description>
59132                  <bitRange>[2:2]</bitRange>
59133                  <access>read-write</access>
59134                </field>
59135                <field>
59136                  <name>IF_UNDERFLOW</name>
59137                  <description>HW sets this field to '1', when PCM samples are not generated in time for the interface logic (interface underflow). This may be an indication that the IP system frequency is too low wrt. the interface frequency (a SW configuration error). The interface underflow is a non-recoverable error and requires SW disabling of the channel (a SW write to INTR_TX.IF_UNDERFLOW does not resolve the interface underflow).
59138
59139Note: This functionality is intended for debug purposes.</description>
59140                  <bitRange>[8:8]</bitRange>
59141                  <access>read-write</access>
59142                </field>
59143              </fields>
59144            </register>
59145            <register>
59146              <name>INTR_TX_SET</name>
59147              <description>Interrupt set</description>
59148              <addressOffset>0xC4</addressOffset>
59149              <size>32</size>
59150              <access>read-write</access>
59151              <resetValue>0x0</resetValue>
59152              <resetMask>0x107</resetMask>
59153              <fields>
59154                <field>
59155                  <name>FIFO_TRIGGER</name>
59156                  <description>Write this field with '1' to set corresponding INTR_TX field (a write of '0' has no effect).</description>
59157                  <bitRange>[0:0]</bitRange>
59158                  <access>read-write</access>
59159                </field>
59160                <field>
59161                  <name>FIFO_OVERFLOW</name>
59162                  <description>Write this field with '1' to set corresponding INTR_TX field (a write of '0' has no effect).</description>
59163                  <bitRange>[1:1]</bitRange>
59164                  <access>read-write</access>
59165                </field>
59166                <field>
59167                  <name>FIFO_UNDERFLOW</name>
59168                  <description>Write this field with '1' to set corresponding INTR_TX field (a write of '0' has no effect).</description>
59169                  <bitRange>[2:2]</bitRange>
59170                  <access>read-write</access>
59171                </field>
59172                <field>
59173                  <name>IF_UNDERFLOW</name>
59174                  <description>Write this field with '1' to set corresponding INTR_TX field (a write of '0' has no effect).</description>
59175                  <bitRange>[8:8]</bitRange>
59176                  <access>read-write</access>
59177                </field>
59178              </fields>
59179            </register>
59180            <register>
59181              <name>INTR_TX_MASK</name>
59182              <description>Interrupt mask</description>
59183              <addressOffset>0xC8</addressOffset>
59184              <size>32</size>
59185              <access>read-write</access>
59186              <resetValue>0x0</resetValue>
59187              <resetMask>0x107</resetMask>
59188              <fields>
59189                <field>
59190                  <name>FIFO_TRIGGER</name>
59191                  <description>Mask for corresponding field in INTR_TX register.</description>
59192                  <bitRange>[0:0]</bitRange>
59193                  <access>read-write</access>
59194                </field>
59195                <field>
59196                  <name>FIFO_OVERFLOW</name>
59197                  <description>Mask for corresponding field in INTR_TX register.</description>
59198                  <bitRange>[1:1]</bitRange>
59199                  <access>read-write</access>
59200                </field>
59201                <field>
59202                  <name>FIFO_UNDERFLOW</name>
59203                  <description>Mask for corresponding field in INTR_TX register.</description>
59204                  <bitRange>[2:2]</bitRange>
59205                  <access>read-write</access>
59206                </field>
59207                <field>
59208                  <name>IF_UNDERFLOW</name>
59209                  <description>Mask for corresponding field in INTR_TX register.</description>
59210                  <bitRange>[8:8]</bitRange>
59211                  <access>read-write</access>
59212                </field>
59213              </fields>
59214            </register>
59215            <register>
59216              <name>INTR_TX_MASKED</name>
59217              <description>Interrupt masked</description>
59218              <addressOffset>0xCC</addressOffset>
59219              <size>32</size>
59220              <access>read-only</access>
59221              <resetValue>0x0</resetValue>
59222              <resetMask>0x107</resetMask>
59223              <fields>
59224                <field>
59225                  <name>FIFO_TRIGGER</name>
59226                  <description>Logical AND of corresponding INTR_TX and INTR_TX_MASK fields.</description>
59227                  <bitRange>[0:0]</bitRange>
59228                  <access>read-only</access>
59229                </field>
59230                <field>
59231                  <name>FIFO_OVERFLOW</name>
59232                  <description>Logical AND of corresponding INTR_TX and INTR_TX_MASK fields.</description>
59233                  <bitRange>[1:1]</bitRange>
59234                  <access>read-only</access>
59235                </field>
59236                <field>
59237                  <name>FIFO_UNDERFLOW</name>
59238                  <description>Logical AND of corresponding INTR_TX and INTR_TX_MASK fields.</description>
59239                  <bitRange>[2:2]</bitRange>
59240                  <access>read-only</access>
59241                </field>
59242                <field>
59243                  <name>IF_UNDERFLOW</name>
59244                  <description>Logical AND of corresponding INTR_TX and INTR_TX_MASK fields.</description>
59245                  <bitRange>[8:8]</bitRange>
59246                  <access>read-only</access>
59247                </field>
59248              </fields>
59249            </register>
59250          </cluster>
59251          <cluster>
59252            <name>TDM_RX_STRUCT</name>
59253            <description>TDM RX structure</description>
59254            <addressOffset>0x00000100</addressOffset>
59255            <register>
59256              <name>RX_CTL</name>
59257              <description>RX control</description>
59258              <addressOffset>0x0</addressOffset>
59259              <size>32</size>
59260              <access>read-write</access>
59261              <resetValue>0x100</resetValue>
59262              <resetMask>0x8001310F</resetMask>
59263              <fields>
59264                <field>
59265                  <name>WORD_SIZE</name>
59266                  <description>PCM word size:
59267'0': 8 bit.
59268'1': 10 bit.
59269'2': 12 bit.
59270'3': 14 bit.
59271'4': 16 bit.
59272'5': 18 bit.
59273'6': 20 bit.
59274'7': 24 bit.
59275'8': 32 bit.
59276'9'-'15': Undefined.</description>
59277                  <bitRange>[3:0]</bitRange>
59278                  <access>read-write</access>
59279                  <enumeratedValues>
59280                    <enumeratedValue>
59281                      <name>SIZE_8</name>
59282                      <description>N/A</description>
59283                      <value>0</value>
59284                    </enumeratedValue>
59285                    <enumeratedValue>
59286                      <name>SIZE_10</name>
59287                      <description>N/A</description>
59288                      <value>1</value>
59289                    </enumeratedValue>
59290                    <enumeratedValue>
59291                      <name>SIZE_12</name>
59292                      <description>N/A</description>
59293                      <value>2</value>
59294                    </enumeratedValue>
59295                    <enumeratedValue>
59296                      <name>SIZE_14</name>
59297                      <description>N/A</description>
59298                      <value>3</value>
59299                    </enumeratedValue>
59300                    <enumeratedValue>
59301                      <name>SIZE_16</name>
59302                      <description>N/A</description>
59303                      <value>4</value>
59304                    </enumeratedValue>
59305                    <enumeratedValue>
59306                      <name>SIZE_18</name>
59307                      <description>N/A</description>
59308                      <value>5</value>
59309                    </enumeratedValue>
59310                    <enumeratedValue>
59311                      <name>SIZE_20</name>
59312                      <description>N/A</description>
59313                      <value>6</value>
59314                    </enumeratedValue>
59315                    <enumeratedValue>
59316                      <name>SIZE_24</name>
59317                      <description>N/A</description>
59318                      <value>7</value>
59319                    </enumeratedValue>
59320                    <enumeratedValue>
59321                      <name>SIZE_32</name>
59322                      <description>N/A</description>
59323                      <value>8</value>
59324                    </enumeratedValue>
59325                  </enumeratedValues>
59326                </field>
59327                <field>
59328                  <name>WORD_SIGN_EXTEND</name>
59329                  <description>Word extension:
59330'0': zero extension.
59331'1': sign extension.</description>
59332                  <bitRange>[8:8]</bitRange>
59333                  <access>read-write</access>
59334                  <enumeratedValues>
59335                    <enumeratedValue>
59336                      <name>ZERO_EXTEND</name>
59337                      <description>N/A</description>
59338                      <value>0</value>
59339                    </enumeratedValue>
59340                    <enumeratedValue>
59341                      <name>SIGN_EXTEND</name>
59342                      <description>N/A</description>
59343                      <value>1</value>
59344                    </enumeratedValue>
59345                  </enumeratedValues>
59346                </field>
59347                <field>
59348                  <name>FORMAT</name>
59349                  <description>Format:
59350'0': Left-aligned delayed.
59351'1': Left-aligned.
59352'2': Right-aligned delayed.
59353'3': Right-aligned.</description>
59354                  <bitRange>[13:12]</bitRange>
59355                  <access>read-write</access>
59356                  <enumeratedValues>
59357                    <enumeratedValue>
59358                      <name>LEFT_DELAYED</name>
59359                      <description>N/A</description>
59360                      <value>0</value>
59361                    </enumeratedValue>
59362                    <enumeratedValue>
59363                      <name>LEFT</name>
59364                      <description>N/A</description>
59365                      <value>1</value>
59366                    </enumeratedValue>
59367                    <enumeratedValue>
59368                      <name>RIGHT_DELAYED</name>
59369                      <description>N/A</description>
59370                      <value>2</value>
59371                    </enumeratedValue>
59372                    <enumeratedValue>
59373                      <name>RIGHT</name>
59374                      <description>N/A</description>
59375                      <value>3</value>
59376                    </enumeratedValue>
59377                  </enumeratedValues>
59378                </field>
59379                <field>
59380                  <name>MS</name>
59381                  <description>Master/slave setting:
59382'0': Slave.
59383- External receiver 'tdm_rx_sck_in' and receiver 'tdm_rx_fsync_in'.
59384'1': Master.
59385- Interface clock 'clk_if' is used to generate receiver 'tdm_rx_sck_out' and receiver 'tdm_rx_fsync_out'.</description>
59386                  <bitRange>[16:16]</bitRange>
59387                  <access>read-write</access>
59388                  <enumeratedValues>
59389                    <enumeratedValue>
59390                      <name>SLAVE</name>
59391                      <description>N/A</description>
59392                      <value>0</value>
59393                    </enumeratedValue>
59394                    <enumeratedValue>
59395                      <name>MASTER</name>
59396                      <description>N/A</description>
59397                      <value>1</value>
59398                    </enumeratedValue>
59399                  </enumeratedValues>
59400                </field>
59401                <field>
59402                  <name>ENABLED</name>
59403                  <description>Receiver (RX) enable:
59404'0': Disabled. All non-retained MMIO registers (e.g. the RX_FIFO_STATUS and INTR_RX registers) have their fields reset to their default value.
59405'1': Enabled.
59406
59407Note: when all transmitters and receivers are disabled, the SRAMs are driven into low power mode, if supported by the SRAM. When exiting such low power mode software needs to allow for a certain power up time before SRAM can be used, i.e. before ACTIVE can be asserted. The power up time is equivalent to the system SRAM power up time specified in the CPUSS.RAM_PWR_DELAY_CTL register (or equivalent for platforms other than MXS40).</description>
59408                  <bitRange>[31:31]</bitRange>
59409                  <access>read-write</access>
59410                </field>
59411              </fields>
59412            </register>
59413            <register>
59414              <name>RX_IF_CTL</name>
59415              <description>RX interface control</description>
59416              <addressOffset>0x10</addressOffset>
59417              <size>32</size>
59418              <access>read-write</access>
59419              <resetValue>0x1F018707</resetValue>
59420              <resetMask>0xFF1FF7FF</resetMask>
59421              <fields>
59422                <field>
59423                  <name>CLOCK_DIV</name>
59424                  <description>Interface clock divider (legal range [1, 255]). The TDM interface 'tdm_rx_sck_out' output signals is defined as clk_if / (CLOCK_DIV + 1). CLOCK_DIV should be set to an odd value ({1, 3, 5, ..., 255}), to ensure a 50/50 percent duty cycle  clock.
59425
59426Note: Used in master configuration only.
59427
59428Note: Due to delays in the IO SubSystem (specifically the IO cells), the maximum TDM interface clock 'tdm_rx_sck_out' may be restricted. As a result, the maximum bitrate is less than the theoretical maximum (32 channels, 32 bits per channel and a high Fs of e.g. 48 kHz). This restriction is most applicable to the master, receiver configuration.</description>
59429                  <bitRange>[7:0]</bitRange>
59430                  <access>read-write</access>
59431                </field>
59432                <field>
59433                  <name>CLOCK_SEL</name>
59434                  <description>Interface clock 'clk_if' selection:
59435'0': SRSS clock clk_if_srss[0].
59436'1': SRSS clock clk_if_srss[1].
59437'2': SRSS clock clk_if_srss[2].
59438'3': SRSS clock clk_if_srss[3].
59439'4': Master interface clock 'tdm_rx_mck_in'.
59440'5'-'7': undefined.
59441
59442Note: the application is always required to program this field to a value different from the default.</description>
59443                  <bitRange>[10:8]</bitRange>
59444                  <access>read-write</access>
59445                  <enumeratedValues>
59446                    <enumeratedValue>
59447                      <name>SEL_SRSS_CLOCK0</name>
59448                      <description>N/A</description>
59449                      <value>0</value>
59450                    </enumeratedValue>
59451                    <enumeratedValue>
59452                      <name>SEL_SRSS_CLOCK1</name>
59453                      <description>N/A</description>
59454                      <value>1</value>
59455                    </enumeratedValue>
59456                    <enumeratedValue>
59457                      <name>SEL_SRSS_CLOCK2</name>
59458                      <description>N/A</description>
59459                      <value>2</value>
59460                    </enumeratedValue>
59461                    <enumeratedValue>
59462                      <name>SEL_SRSS_CLOCK3</name>
59463                      <description>N/A</description>
59464                      <value>3</value>
59465                    </enumeratedValue>
59466                    <enumeratedValue>
59467                      <name>SEL_TDM_RX_MCK_IN</name>
59468                      <description>N/A</description>
59469                      <value>4</value>
59470                    </enumeratedValue>
59471                  </enumeratedValues>
59472                </field>
59473                <field>
59474                  <name>SCK_POLARITY</name>
59475                  <description>Clock polarity:
59476'0': Clock signal is used 'as is'.
59477'1': Clock signal is inverted.
59478
59479Note: Used in BOTH master and slave configurations.</description>
59480                  <bitRange>[12:12]</bitRange>
59481                  <access>read-write</access>
59482                </field>
59483                <field>
59484                  <name>FSYNC_POLARITY</name>
59485                  <description>Channel synchronization polarity:
59486'0': Channel synchronization signal is used 'as is'.
59487'1': Channel synchronization signal is inverted.
59488
59489Note: Used in BOTH master and slave configurations.</description>
59490                  <bitRange>[13:13]</bitRange>
59491                  <access>read-write</access>
59492                </field>
59493                <field>
59494                  <name>LATE_SAMPLE</name>
59495                  <description>Interface late sample sample delay:
59496Slave configuration (RX_CTL.MS is '0').
59497'0': Sample PCM bit value on rising edge (SCK_POLARITY is '0') or falling edge (SCK_POLARITY is '1') of receiver 'rx_sck_in'.
59498'1': Sample PCM bit value on falling edge  (SCK_POLARITY is '0') or rising edge (SCK_POLARITY is '1') of receiver 'rx_sck_in' (half a cycle delay).
59499
59500Master configuration (RX_CTL.MS is '1').
59501'0': Sample PCM bit value on rising edge (SCK_POLARITY is '0') or falling edge (SCK_POLARITY is '1') of receiver 'rx_sck_out'.
59502'1': Sample PCM bit value on falling edge  (SCK_POLARITY is '0') or rising edge (SCK_POLARITY is '1') of receiver 'rx_sck_out' (half a cycle delay).
59503
59504Note: This field can be set to '1' when the roundtrip delay is large (typically) in a master receiver configuration.</description>
59505                  <bitRange>[14:14]</bitRange>
59506                  <access>read-write</access>
59507                  <enumeratedValues>
59508                    <enumeratedValue>
59509                      <name>RISING</name>
59510                      <description>N/A</description>
59511                      <value>0</value>
59512                    </enumeratedValue>
59513                    <enumeratedValue>
59514                      <name>FALLING</name>
59515                      <description>N/A</description>
59516                      <value>1</value>
59517                    </enumeratedValue>
59518                  </enumeratedValues>
59519                </field>
59520                <field>
59521                  <name>FSYNC_FORMAT</name>
59522                  <description>Channel synchronization pulse format:
59523'0': Duration of a single bit period.
59524'1': Duration of the first channel.</description>
59525                  <bitRange>[15:15]</bitRange>
59526                  <access>read-write</access>
59527                  <enumeratedValues>
59528                    <enumeratedValue>
59529                      <name>BIT_PERIOD</name>
59530                      <description>N/A</description>
59531                      <value>0</value>
59532                    </enumeratedValue>
59533                    <enumeratedValue>
59534                      <name>CH_PERIOD</name>
59535                      <description>N/A</description>
59536                      <value>1</value>
59537                    </enumeratedValue>
59538                  </enumeratedValues>
59539                </field>
59540                <field>
59541                  <name>CH_NR</name>
59542                  <description>Number of channels in the frame:
59543'0': Undefined/illegal.
59544'1': 2 channels.
59545'2': 3 channels.
59546...
59547'31': 32 channels.
59548
59549Note: the field value chould be less than CH_NR (the number of support channels).
59550
59551Note: the RX_CH_CTL.CH_EN fields can be used to enable/disable indvidual channels.</description>
59552                  <bitRange>[20:16]</bitRange>
59553                  <access>read-write</access>
59554                </field>
59555                <field>
59556                  <name>CH_SIZE</name>
59557                  <description>Channel size:
59558'0'-'2': Undefined/illegal.
59559'3': 4 bits.
59560...
59561'31': 32 bits.
59562
59563Note: if RX_CTL.WORD_SIZE is greater than CH_SIZE, the lesser significant bits of the word are filled with '0's.</description>
59564                  <bitRange>[28:24]</bitRange>
59565                  <access>read-write</access>
59566                  <enumeratedValues>
59567                    <enumeratedValue>
59568                      <name>SIZE_1</name>
59569                      <description>N/A</description>
59570                      <value>0</value>
59571                    </enumeratedValue>
59572                    <enumeratedValue>
59573                      <name>SIZE_2</name>
59574                      <description>N/A</description>
59575                      <value>1</value>
59576                    </enumeratedValue>
59577                    <enumeratedValue>
59578                      <name>SIZE_32</name>
59579                      <description>N/A</description>
59580                      <value>31</value>
59581                    </enumeratedValue>
59582                  </enumeratedValues>
59583                </field>
59584                <field>
59585                  <name>LATE_CAPTURE</name>
59586                  <description>Extra delay (in 'rx_sck_out' cycles) for capturing 'tdm_rx_sd_in':
59587'0': no extra delay
59588'1': 1 cycle extra delay
59589'2': 2 cycles extra delay
59590'3': 3 cycles extra delay
59591
59592Note: the value of this field pushes further out the capturing edges used by the receiver to sample 'tdm_rx_sd_in'. This function is intended to support very large round-trip delays in a master receiver configuration, where the delay at the receiver between 'tdm_rx_fsync_out' and the arrival of the first bit on 'tdm_rx_sd_in' is multiple clock cycles.</description>
59593                  <bitRange>[30:29]</bitRange>
59594                  <access>read-write</access>
59595                  <enumeratedValues>
59596                    <enumeratedValue>
59597                      <name>EXTRA_DELAY_0</name>
59598                      <description>N/A</description>
59599                      <value>0</value>
59600                    </enumeratedValue>
59601                    <enumeratedValue>
59602                      <name>EXTRA_DELAY_1</name>
59603                      <description>N/A</description>
59604                      <value>1</value>
59605                    </enumeratedValue>
59606                    <enumeratedValue>
59607                      <name>EXTRA_DELAY_2</name>
59608                      <description>N/A</description>
59609                      <value>2</value>
59610                    </enumeratedValue>
59611                    <enumeratedValue>
59612                      <name>EXTRA_DELAY_3</name>
59613                      <description>N/A</description>
59614                      <value>3</value>
59615                    </enumeratedValue>
59616                  </enumeratedValues>
59617                </field>
59618                <field>
59619                  <name>I2S_MODE</name>
59620                  <description>I2S mode setting:
59621'0': TDM mode.
59622'1': I2S mode.</description>
59623                  <bitRange>[31:31]</bitRange>
59624                  <access>read-write</access>
59625                  <enumeratedValues>
59626                    <enumeratedValue>
59627                      <name>TDM</name>
59628                      <description>N/A</description>
59629                      <value>0</value>
59630                    </enumeratedValue>
59631                    <enumeratedValue>
59632                      <name>I2S</name>
59633                      <description>N/A</description>
59634                      <value>1</value>
59635                    </enumeratedValue>
59636                  </enumeratedValues>
59637                </field>
59638              </fields>
59639            </register>
59640            <register>
59641              <name>RX_CH_CTL</name>
59642              <description>RX channel control</description>
59643              <addressOffset>0x14</addressOffset>
59644              <size>32</size>
59645              <access>read-write</access>
59646              <resetValue>0x0</resetValue>
59647              <resetMask>0xFFFFFFFF</resetMask>
59648              <fields>
59649                <field>
59650                  <name>CH_EN</name>
59651                  <description>Channel enables: channel i is controlled by CH_EN[i].
59652'0': Disabled. The RX FIFO does not consume channel i words and the received channel i words on the interface are discarded.
59653'1': Enabled..
59654
59655Note: Only bit 0 through RX_IF_CTL.CH_NR may be set to '1'; i.e. only channels that are present in the frame can be enabled.</description>
59656                  <bitRange>[31:0]</bitRange>
59657                  <access>read-write</access>
59658                </field>
59659              </fields>
59660            </register>
59661            <register>
59662              <name>RX_TEST_CTL</name>
59663              <description>RX test control</description>
59664              <addressOffset>0x20</addressOffset>
59665              <size>32</size>
59666              <access>read-write</access>
59667              <resetValue>0x0</resetValue>
59668              <resetMask>0x80000000</resetMask>
59669              <fields>
59670                <field>
59671                  <name>ENABLED</name>
59672                  <description>Test mode enable.
59673'0': Disabled. Functional mode.
59674- Receiver rx_sck_in = IOSS tdm_rx_sck_in.
59675- Receiver rx_fsync_in = IOSS tdm_rx_fsync_in.
59676- Receiver rx_sd_in = IOSS tdm_rx_sd_in.
59677'1': Enabled. Test mode (intended to be used with (master transmitter, slave receiver) configuration).
59678- Receiver rx_sck_in = Transmitter tdm_tx_sck_out.
59679- Receiver rx_fsync_in = Transmitter tdm_tx_fsync_out.
59680- Receiver rx_sd_in = Transmitter tdm_tx_sd_out.
59681
59682Note: TX_TEST_CTL.ENABLED and RX_TEST_CTL.ENABLED should not be set to '1' simultaneously.</description>
59683                  <bitRange>[31:31]</bitRange>
59684                  <access>read-write</access>
59685                  <enumeratedValues>
59686                    <enumeratedValue>
59687                      <name>FUNCTIONAL</name>
59688                      <description>N/A</description>
59689                      <value>0</value>
59690                    </enumeratedValue>
59691                    <enumeratedValue>
59692                      <name>TEST</name>
59693                      <description>N/A</description>
59694                      <value>1</value>
59695                    </enumeratedValue>
59696                  </enumeratedValues>
59697                </field>
59698              </fields>
59699            </register>
59700            <register>
59701              <name>RX_ROUTE_CTL</name>
59702              <description>RX route control</description>
59703              <addressOffset>0x24</addressOffset>
59704              <size>32</size>
59705              <access>read-write</access>
59706              <resetValue>0x0</resetValue>
59707              <resetMask>0x3</resetMask>
59708              <fields>
59709                <field>
59710                  <name>MODE</name>
59711                  <description>Controls routing to the RX slave signalling inputs (FSYNC/SCK):
59712'0': RX slave signaling indipendent from TX signaling:
59713- Receiver rx_sck_in = IOSS tdm_rx_sck_in
59714- Receiver rx_fsync_in = IOSS tdm_rx_fsync_in
59715'1': RX slave signalling inputs driven by TX Slave:
59716- Receiver rx_sck_in = IOSS tdm_tx_sck_in
59717- Receiver rx_fsync_in = IOSS tdm_tx_fsync_in
59718'2': RX slave signalling inputs driven by TX Master:
59719- Receiver rx_sck_in = transmitter tdm_tx_sck_out
59720- Receiver rx_fsync_in = transmitter tdm_tx_fsync_out
59721
59722Note: MODE=0 is the default behaviour. MODE=1 or 2 is intended to allow the RX slave to share the same signaling used by the TX. This feature can be used to reduce the number of IO pins necessary to connect to an external codec supporting common TX/RX signaling.
59723
59724Note: when MODE=1 or 2, TX_TEST_CTL.ENABLED and RX_TEST_CTL.ENABLED should not be set to '1'.</description>
59725                  <bitRange>[1:0]</bitRange>
59726                  <access>read-write</access>
59727                  <enumeratedValues>
59728                    <enumeratedValue>
59729                      <name>RX_IN_DRIVEN_BY_IOSS_RX_IN</name>
59730                      <description>N/A</description>
59731                      <value>0</value>
59732                    </enumeratedValue>
59733                    <enumeratedValue>
59734                      <name>RX_IN_DRIVEN_BY_IOSS_TX_IN</name>
59735                      <description>N/A</description>
59736                      <value>1</value>
59737                    </enumeratedValue>
59738                    <enumeratedValue>
59739                      <name>RX_IN_DRIVEN_BY_TX_OUT</name>
59740                      <description>N/A</description>
59741                      <value>2</value>
59742                    </enumeratedValue>
59743                  </enumeratedValues>
59744                </field>
59745              </fields>
59746            </register>
59747            <register>
59748              <name>RX_FIFO_CTL</name>
59749              <description>RX FIFO control</description>
59750              <addressOffset>0x80</addressOffset>
59751              <size>32</size>
59752              <access>read-write</access>
59753              <resetValue>0x0</resetValue>
59754              <resetMask>0x6007F</resetMask>
59755              <fields>
59756                <field>
59757                  <name>TRIGGER_LEVEL</name>
59758                  <description>Trigger level. When the RX FIFO has more entries than the number of this field, a receiver trigger event is generated:
59759- INTR_RX.FIFO_TRIGGER = (# FIFO entries &gt; TRIGGER_LEVEL)</description>
59760                  <bitRange>[6:0]</bitRange>
59761                  <access>read-write</access>
59762                </field>
59763                <field>
59764                  <name>FREEZE</name>
59765                  <description>Freeze functionality:
59766'0': HW writes to the RX FIFO and advances the FIFO write pointer.
59767'1': HW writes from the RX FIFO have no effect: freeze will not advance the FIFO write pointer.
59768
59769Note: HW ensures that freeze functionality synchronizes on the first channel of a frame to ensure that PCM data of one channel is not misassigned to another channel. As a result, the freeze functionality can be activated at any time.
59770
59771Note: This functionality is intended for debugging purposes.</description>
59772                  <bitRange>[17:17]</bitRange>
59773                  <access>read-write</access>
59774                </field>
59775                <field>
59776                  <name>ACTIVE</name>
59777                  <description>Activate functionality:
59778'0': Receiver off. The FIFO_OVERFLOW interrupt cause will not be activated.
59779'1': Receiver on. The FIFO_OVERFLOW interrupt may be activated (when an overflow event occurs).
59780
59781Note: This functionality is intended for stopping purposes.</description>
59782                  <bitRange>[18:18]</bitRange>
59783                  <access>read-write</access>
59784                </field>
59785              </fields>
59786            </register>
59787            <register>
59788              <name>RX_FIFO_STATUS</name>
59789              <description>RX FIFO status</description>
59790              <addressOffset>0x84</addressOffset>
59791              <size>32</size>
59792              <access>read-only</access>
59793              <resetValue>0x0</resetValue>
59794              <resetMask>0x7F7F00FF</resetMask>
59795              <fields>
59796                <field>
59797                  <name>USED</name>
59798                  <description>Number of used/occupied entries in the RX FIFO. The field value is in the range [0, 128]. When '0', the FIFO is empty. When '128', the FIFO is full.</description>
59799                  <bitRange>[7:0]</bitRange>
59800                  <access>read-only</access>
59801                </field>
59802                <field>
59803                  <name>RD_PTR</name>
59804                  <description>RX FIFO read pointer: FIFO location from which a data is read.
59805
59806Note: This functionality is intended for debugging purposes.</description>
59807                  <bitRange>[22:16]</bitRange>
59808                  <access>read-only</access>
59809                </field>
59810                <field>
59811                  <name>WR_PTR</name>
59812                  <description>RX FIFO write pointer: FIFO location at which a new data is written by the hardware.
59813
59814Note: This functionality is intended for debugging purposes.</description>
59815                  <bitRange>[30:24]</bitRange>
59816                  <access>read-only</access>
59817                </field>
59818              </fields>
59819            </register>
59820            <register>
59821              <name>RX_FIFO_RD</name>
59822              <description>RX FIFO read</description>
59823              <addressOffset>0x88</addressOffset>
59824              <size>32</size>
59825              <access>read-only</access>
59826              <resetValue>0x0</resetValue>
59827              <resetMask>0xFFFFFFFF</resetMask>
59828              <fields>
59829                <field>
59830                  <name>DATA</name>
59831                  <description>Data (PCM sample) read from the RX FIFO. Reading removes the data from the RX FIFO; i.e. behavior is similar to that of a POP operation (RX_FIFO_STATUS.RD_PTR is incremented and RX_FIFO_STATUS.USED is decremented). The read data (DATA) is right aligned (unused bit positions follow the specified sign extension per RX_CTL.WORD_SIGN_EXTEND) when it is read from the FIFO entry (data[31:0]):
59832- 8 bit, DATA[7:0] = data[31:24].
59833- 10 bit, DATA[9:0] = data[31:22].
59834- 12 bit, DATA[11:0] = data[31:20].
59835- 14 bit, DATA[13:0] = data[31:18].
59836- 16 bit, DATA[15:0] = data[31:16].
59837- 18 bit, DATA[17:0] = data[31:14].
59838- 20 bit, DATA[19:0] = data[31:12].
59839- 24 bit, DATA[23:0] = data[31:8].
59840- 32 bit, DATA[31:0] = data[31:0].
59841
59842Note: Reading from an empty RX FIFO activates INTR_RX.FIFO_UNDERFLOW.</description>
59843                  <bitRange>[31:0]</bitRange>
59844                  <access>read-only</access>
59845                </field>
59846              </fields>
59847            </register>
59848            <register>
59849              <name>RX_FIFO_RD_SILENT</name>
59850              <description>RX FIFO silent read</description>
59851              <addressOffset>0x8C</addressOffset>
59852              <size>32</size>
59853              <access>read-only</access>
59854              <resetValue>0x0</resetValue>
59855              <resetMask>0xFFFFFFFF</resetMask>
59856              <fields>
59857                <field>
59858                  <name>DATA</name>
59859                  <description>N/A</description>
59860                  <bitRange>[31:0]</bitRange>
59861                  <access>read-only</access>
59862                </field>
59863              </fields>
59864            </register>
59865            <register>
59866              <name>INTR_RX</name>
59867              <description>Interrupt</description>
59868              <addressOffset>0xC0</addressOffset>
59869              <size>32</size>
59870              <access>read-write</access>
59871              <resetValue>0x0</resetValue>
59872              <resetMask>0x107</resetMask>
59873              <fields>
59874                <field>
59875                  <name>FIFO_TRIGGER</name>
59876                  <description>HW sets this field to '1', when a RX trigger is generated.</description>
59877                  <bitRange>[0:0]</bitRange>
59878                  <access>read-write</access>
59879                </field>
59880                <field>
59881                  <name>FIFO_OVERFLOW</name>
59882                  <description>HW sets this field to '1', when writing to a (almost) full RX FIFO (128 -RX_FIFO_STATUS.USED &lt; 'number of enabled channels per frame'). This is referred to as an overflow event.
59883
59884Note: HW ensures that either all or none of the frame's channels are received. In a RX FIFO overflow situation, HW discards received PCM data values.</description>
59885                  <bitRange>[1:1]</bitRange>
59886                  <access>read-write</access>
59887                </field>
59888                <field>
59889                  <name>FIFO_UNDERFLOW</name>
59890                  <description>HW sets this field to '1', when reading from an empty RX FIFO (RX_FIFO_STATUS.USED is '0').</description>
59891                  <bitRange>[2:2]</bitRange>
59892                  <access>read-write</access>
59893                </field>
59894                <field>
59895                  <name>IF_OVERFLOW</name>
59896                  <description>HW sets this field to '1', when PCM samples are generated too fast by the interface logic (interface overflow). This may be an indication that the IP system frequency is too low wrt. the interface frequency (a SW configuration error). The interface overflow is a non-recoverable error and requires SW disabling of the channel (a SW write to INTR_RX.IF_OVERFLOW does not resolve the interface underflow).
59897
59898Note: This functionality is intended for debug purposes.</description>
59899                  <bitRange>[8:8]</bitRange>
59900                  <access>read-write</access>
59901                </field>
59902              </fields>
59903            </register>
59904            <register>
59905              <name>INTR_RX_SET</name>
59906              <description>Interrupt set</description>
59907              <addressOffset>0xC4</addressOffset>
59908              <size>32</size>
59909              <access>read-write</access>
59910              <resetValue>0x0</resetValue>
59911              <resetMask>0x107</resetMask>
59912              <fields>
59913                <field>
59914                  <name>FIFO_TRIGGER</name>
59915                  <description>Write this field with '1' to set corresponding INTR_RX field (a write of '0' has no effect).</description>
59916                  <bitRange>[0:0]</bitRange>
59917                  <access>read-write</access>
59918                </field>
59919                <field>
59920                  <name>FIFO_OVERFLOW</name>
59921                  <description>Write this field with '1' to set corresponding INTR_RX field (a write of '0' has no effect).</description>
59922                  <bitRange>[1:1]</bitRange>
59923                  <access>read-write</access>
59924                </field>
59925                <field>
59926                  <name>FIFO_UNDERFLOW</name>
59927                  <description>Write this field with '1' to set corresponding INTR_RX field (a write of '0' has no effect).</description>
59928                  <bitRange>[2:2]</bitRange>
59929                  <access>read-write</access>
59930                </field>
59931                <field>
59932                  <name>IF_OVERFLOW</name>
59933                  <description>Write this field with '1' to set corresponding INTR_RX field (a write of '0' has no effect).</description>
59934                  <bitRange>[8:8]</bitRange>
59935                  <access>read-write</access>
59936                </field>
59937              </fields>
59938            </register>
59939            <register>
59940              <name>INTR_RX_MASK</name>
59941              <description>Interrupt mask</description>
59942              <addressOffset>0xC8</addressOffset>
59943              <size>32</size>
59944              <access>read-write</access>
59945              <resetValue>0x0</resetValue>
59946              <resetMask>0x107</resetMask>
59947              <fields>
59948                <field>
59949                  <name>FIFO_TRIGGER</name>
59950                  <description>Mask for corresponding field in INTR_RX register.</description>
59951                  <bitRange>[0:0]</bitRange>
59952                  <access>read-write</access>
59953                </field>
59954                <field>
59955                  <name>FIFO_OVERFLOW</name>
59956                  <description>Mask for corresponding field in INTR_RX register.</description>
59957                  <bitRange>[1:1]</bitRange>
59958                  <access>read-write</access>
59959                </field>
59960                <field>
59961                  <name>FIFO_UNDERFLOW</name>
59962                  <description>Mask for corresponding field in INTR_RX register.</description>
59963                  <bitRange>[2:2]</bitRange>
59964                  <access>read-write</access>
59965                </field>
59966                <field>
59967                  <name>IF_OVERFLOW</name>
59968                  <description>Mask for corresponding field in INTR_RX register.</description>
59969                  <bitRange>[8:8]</bitRange>
59970                  <access>read-write</access>
59971                </field>
59972              </fields>
59973            </register>
59974            <register>
59975              <name>INTR_RX_MASKED</name>
59976              <description>Interrupt masked</description>
59977              <addressOffset>0xCC</addressOffset>
59978              <size>32</size>
59979              <access>read-only</access>
59980              <resetValue>0x0</resetValue>
59981              <resetMask>0x107</resetMask>
59982              <fields>
59983                <field>
59984                  <name>FIFO_TRIGGER</name>
59985                  <description>Logical AND of corresponding INTR_RX and INTR_RX_MASK fields.</description>
59986                  <bitRange>[0:0]</bitRange>
59987                  <access>read-only</access>
59988                </field>
59989                <field>
59990                  <name>FIFO_OVERFLOW</name>
59991                  <description>Logical AND of corresponding INTR_RX and INTR_RX_MASK fields.</description>
59992                  <bitRange>[1:1]</bitRange>
59993                  <access>read-only</access>
59994                </field>
59995                <field>
59996                  <name>FIFO_UNDERFLOW</name>
59997                  <description>Logical AND of corresponding INTR_RX and INTR_RX_MASK fields.</description>
59998                  <bitRange>[2:2]</bitRange>
59999                  <access>read-only</access>
60000                </field>
60001                <field>
60002                  <name>IF_OVERFLOW</name>
60003                  <description>Logical AND of corresponding INTR_RX and INTR_RX_MASK fields.</description>
60004                  <bitRange>[8:8]</bitRange>
60005                  <access>read-only</access>
60006                </field>
60007              </fields>
60008            </register>
60009          </cluster>
60010        </cluster>
60011      </registers>
60012    </peripheral>
60013  </peripherals>
60014</device>