Cypress Semiconductor Cypress fx3g2 fx3g2 1.0 FX3G2 (c) (2016-2021), Cypress Semiconductor Corporation (an Infineon company)\n or an affiliate of Cypress Semiconductor Corporation.\n \n SPDX-License-Identifier: Apache-2.0\n \n Licensed under the Apache License, Version 2.0 (the "License");\n you may not use this file except in compliance with the License.\n You may obtain a copy of the License at\n \n http://www.apache.org/licenses/LICENSE-2.0\n \n Unless required by applicable law or agreed to in writing, software\n distributed under the License is distributed on an "AS IS" BASIS,\n WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n See the License for the specific language governing permissions and\n limitations under the License. CM4 r0p1 little true true 1 3 0 8 32 0x00000000 0xFFFFFFFF PERI Peripheral interconnect 0x40000000 0 65536 registers TIMEOUT_CTL Timeout control 0x200 32 read-write 0xFFFF 0xFFFF TIMEOUT This field specifies a number of clock cycles (clk_slow). If an AHB-Lite bus transfer takes more than the specified number of cycles (timeout detection), the bus transfer is terminated with an AHB-Lite bus error and a fault is generated (and possibly recorded in the fault report structure(s)). '0x0000'-'0xfffe': Number of clock cycles. '0xffff': This value is the default/reset value and specifies that no timeout detection is performed: a bus transfer will never be terminated and a fault will never be generated. [15:0] read-write TR_CMD Trigger command 0x220 32 read-write 0x0 0xE0001FFF TR_SEL Specifies the activated trigger when ACTIVATE is '1'. If the specified trigger is not present, the trigger activation has no effect. [7:0] read-write GROUP_SEL Specifies the trigger group: '0'-'15': trigger multiplexer groups. '16'-'31': trigger 1-to-1 groups. [12:8] read-write TR_EDGE Specifies if the activated trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. The trigger reflects TR_CMD.ACTIVATE. '1': edge sensitive trigger. The trigger is activated for two clk_peri cycles. [29:29] read-write OUT_SEL Specifies whether trigger activation is for a specific input or output trigger of the trigger multiplexer. Activation of a specific input trigger, will result in activation of all output triggers that have the specific input trigger selected through their TR_OUT_CTL.TR_SEL field. Activation of a specific output trigger, will result in activation of the specified TR_SEL output trigger only. '0': TR_SEL selection and trigger activation is for an input trigger to the trigger multiplexer. '1': TR_SEL selection and trigger activation is for an output trigger from the trigger multiplexer. Note: this field is not used for trigger 1-to-1 groups. [30:30] read-write ACTIVATE SW sets this field to '1' to activate (set to '1') a trigger as identified by TR_SEL, TR_EDGE and OUT_SEL. HW sets this field to '0' for edge sensitive triggers AFTER the selected trigger is activated for two clk_peri cycles. Note: when ACTIVATE is '1', SW should not modify the other register fields. SW MUST NOT set ACTIVATE bit to '1' while updating the other register bits simultaneously. At first the SW MUST update the other register bits as needed, and then set ACTIVATE to '1' with a new register write. [31:31] read-write DIV_CMD Divider command 0x400 32 read-write 0x3FF03FF 0xC3FF03FF DIV_SEL (TYPE_SEL, DIV_SEL) specifies the divider on which the command (DISABLE/ENABLE) is performed. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock signal(s) are generated. [7:0] read-write TYPE_SEL Specifies the divider type of the divider on which the command is performed: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. [9:8] read-write PA_DIV_SEL (PA_TYPE_SEL, PA_DIV_SEL) specifies the divider to which phase alignment is performed for the clock enable command. Any enabled divider can be used as reference. This allows all dividers to be aligned with each other, even when they are enabled at different times. If PA_DIV_SEL is '255' and PA_TYPE_SEL is '3', 'clk_peri' is used as reference. [23:16] read-write PA_TYPE_SEL Specifies the divider type of the divider to which phase alignment is performed for the clock enable command: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. [25:24] read-write DISABLE Clock divider disable command (mutually exclusive with ENABLE). SW sets this field to '1' and HW sets this field to '0'. The DIV_SEL and TYPE_SEL fields specify which divider is to be disabled. The HW sets the DISABLE field to '0' immediately and the HW sets the DIV_XXX_CTL.EN field of the divider to '0' immediately. [30:30] read-write ENABLE Clock divider enable command (mutually exclusive with DISABLE). Typically, SW sets this field to '1' to enable a divider and HW sets this field to '0' to indicate that divider enabling has completed. When a divider is enabled, its integer and fractional (if present) counters are initialized to '0'. If a divider is to be re-enabled using different integer and fractional divider values, the SW should follow these steps: 0: Disable the divider using the DIV_CMD.DISABLE field. 1: Configure the divider's DIV_XXX_CTL register. 2: Enable the divider using the DIV_CMD_ENABLE field. The DIV_SEL and TYPE_SEL fields specify which divider is to be enabled. The enabled divider may be phase aligned to either 'clk_peri' (typical usage) or to ANY enabled divider. The PA_DIV_SEL and PA_TYPE_SEL fields specify the reference divider. The HW sets the ENABLE field to '0' when the enabling is performed and the HW set the DIV_XXX_CTL.EN field of the divider to '1' when the enabling is performed. Note that enabling with phase alignment to a low frequency divider takes time. E.g. To align to a divider that generates a clock of 'clk_peri'/n (with n being the integer divider value INT_DIV+1), up to n cycles may be required to perform alignment. Phase alignment to 'clk_peri' takes affect immediately. SW can set this field to '0' during phase alignment to abort the enabling process. [31:31] read-write 256 4 CLOCK_CTL[%s] Clock control 0xC00 32 read-write 0x3FF 0x3FF DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. [7:0] read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. [9:8] read-write 256 4 DIV_8_CTL[%s] Divider control (for 8.0 divider) 0x1000 32 read-write 0x0 0xFF01 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. [0:0] read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. [15:8] read-write 256 4 DIV_16_CTL[%s] Divider control (for 16.0 divider) 0x1400 32 read-write 0x0 0xFFFF01 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. [0:0] read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. [23:8] read-write 256 4 DIV_16_5_CTL[%s] Divider control (for 16.5 divider) 0x1800 32 read-write 0x0 0xFFFFF9 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. [0:0] read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. [7:3] read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. [23:8] read-write 255 4 DIV_24_5_CTL[%s] Divider control (for 24.5 divider) 0x1C00 32 read-write 0x0 0xFFFFFFF9 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. [0:0] read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. [7:3] read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. [31:8] read-write ECC_CTL ECC control 0x2000 32 read-write 0x10000 0xFF0507FF WORD_ADDR Specifies the word address where the parity is injected. - On a 32-bit write access to this SRAM address and when ECC_INJ_EN bit is '1', the parity (PARITY) is injected. [10:0] read-write ECC_EN Enable ECC checking: '0': Disabled. '1': Enabled. [16:16] read-write ECC_INJ_EN Enable error injection for PERI protection structure SRAM. When '1', the parity (PARITY) is used when a write is done to the WORD_ADDR word address of the SRAM. [18:18] read-write PARITY ECC parity to use for ECC error injection at address WORD_ADDR. [31:24] read-write 6 32 GR[%s] Peripheral group structure 0x00004000 CLOCK_CTL Clock control 0x0 32 read-write 0x0 0xFF00 INT8_DIV Specifies a group clock divider (from the peripheral clock 'clk_peri' to the group clock 'clk_group[3/4/5/...15]'). Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. [15:8] read-write SL_CTL Slave control 0x10 32 read-write 0xFFFF 0xFFFFFFFF ENABLED_0 Peripheral group, slave 0 enable. If the slave is disabled, its clock is gated off (constant '0') and its resets are activated. Note: For peripheral group 0 (the peripheral interconnect MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled. [0:0] read-write ENABLED_1 Peripheral group, slave 1 enable. If the slave is disabled, its clock is gated off (constant '0') and its resets are activated. Note: For peripheral group 0 (the peripheral interconnect, master interface MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled. [1:1] read-write ENABLED_2 N/A [2:2] read-write ENABLED_3 N/A [3:3] read-write ENABLED_4 N/A [4:4] read-write ENABLED_5 N/A [5:5] read-write ENABLED_6 N/A [6:6] read-write ENABLED_7 N/A [7:7] read-write ENABLED_8 N/A [8:8] read-write ENABLED_9 N/A [9:9] read-write ENABLED_10 N/A [10:10] read-write ENABLED_11 N/A [11:11] read-write ENABLED_12 N/A [12:12] read-write ENABLED_13 N/A [13:13] read-write ENABLED_14 N/A [14:14] read-write ENABLED_15 N/A [15:15] read-write DISABLED_0 Peripheral group, slave 0 permanent disable. Setting this bit to 1 has the same effect as setting ENABLED_0 to 0. However, once set to 1, this bit cannot be changed back to 0 anymore. [16:16] read-write DISABLED_1 N/A [17:17] read-write DISABLED_2 N/A [18:18] read-write DISABLED_3 N/A [19:19] read-write DISABLED_4 N/A [20:20] read-write DISABLED_5 N/A [21:21] read-write DISABLED_6 N/A [22:22] read-write DISABLED_7 N/A [23:23] read-write DISABLED_8 N/A [24:24] read-write DISABLED_9 N/A [25:25] read-write DISABLED_10 N/A [26:26] read-write DISABLED_11 N/A [27:27] read-write DISABLED_12 N/A [28:28] read-write DISABLED_13 N/A [29:29] read-write DISABLED_14 N/A [30:30] read-write DISABLED_15 N/A [31:31] read-write 13 1024 TR_GR[%s] Trigger group 0x00008000 256 4 TR_CTL[%s] Trigger control register 0x0 32 read-write 0x0 0x13FF TR_SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. [7:0] read-write TR_INV Specifies if the output trigger is inverted. [8:8] read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. [9:9] read-write DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. [12:12] read-write 6 1024 TR_1TO1_GR[%s] Trigger 1-to-1 group 0x0000C000 256 4 TR_CTL[%s] Trigger control register 0x0 32 read-write 0x0 0x1301 TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. [0:0] read-write TR_INV Specifies if the output trigger is inverted. [8:8] read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. [9:9] read-write DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. [12:12] read-write PERI_MS Peripheral interconnect, master interface 0x40010000 0 65536 registers 8 64 PPU_PR[%s] Programmable protection structure pair 0x00000000 SL_ADDR Slave region, base address 0x0 32 read-write 0x0 0x0 ADDR30 This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore, some of the lesser significant address bits of ADDR30 must be '0's. E.g., a 64 KB address region (REGION_SIZE is '15') must be 64 KByte aligned, and ADDR30[13:0] must be '0's. [31:2] read-write SL_SIZE Slave region, size 0x4 32 read-write 0x0 0x80000000 REGION_SIZE This field specifies the size of the slave region: '0': Undefined. '1': 4 B region (this is the smallest region size). '2': 8 B region '3': 16 B region '4': 32 B region '5': 64 B region '6': 128 B region '7': 256 B region '8': 512 B region '9': 1 KB region '10': 2 KB region '11': 4 KB region '12': 8 KB region '13': 16 KB region '14': 32 KB region '15': 64 KB region '16': 128 KB region '17': 256 KB region '18': 512 KB region '19': 1 MB region '20': 2 MB region '21': 4 MB region '22': 8 MB region '23': 16 MB region '24': 32 MB region '25': 64 MB region '26': 128 MB region '27': 256 MB region '28': 512 MB region '29': 1 GB region '30': 2 GB region '31': 4 GB region [28:24] read-write VALID Slave region enable: '0': Disabled. A disabled region will never result in a match on the transfer address. '1': Enabled. [31:31] read-write SL_ATT0 Slave attributes 0 0x10 32 read-write 0x1F1F1F1F 0x1F1F1F1F PC0_UR Protection context 0, user read enable: '0': Disabled (user, read accesses are NOT allowed). '1': Enabled (user, read accesses are allowed). [0:0] read-only PC0_UW Protection context 0, user write enable: '0': Disabled (user, write accesses are NOT allowed). '1': Enabled (user, write accesses are allowed). [1:1] read-only PC0_PR Protection context 0, privileged read enable: '0': Disabled (privileged, read accesses are NOT allowed). '1': Enabled (privileged, read accesses are allowed). [2:2] read-only PC0_PW Protection context 0, privileged write enable: '0': Disabled (privileged, write accesses are NOT allowed). '1': Enabled (privileged, write accesses are allowed). [3:3] read-only PC0_NS Protection context 0, non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed). [4:4] read-only PC1_UR Protection context 1, user read enable. [8:8] read-write PC1_UW Protection context 1, user write enable. [9:9] read-write PC1_PR Protection context 1, privileged read enable. [10:10] read-write PC1_PW Protection context 1, privileged write enable. [11:11] read-write PC1_NS Protection context 1, non-secure. [12:12] read-write PC2_UR Protection context 2, user read enable. [16:16] read-write PC2_UW Protection context 2, user write enable. [17:17] read-write PC2_PR Protection context 2, privileged read enable. [18:18] read-write PC2_PW Protection context 2, privileged write enable. [19:19] read-write PC2_NS Protection context 2, non-secure. [20:20] read-write PC3_UR Protection context 3, user read enable. [24:24] read-write PC3_UW Protection context 3, user write enable. [25:25] read-write PC3_PR Protection context 3, privileged read enable. [26:26] read-write PC3_PW Protection context 3, privileged write enable. [27:27] read-write PC3_NS Protection context 3, non-secure. [28:28] read-write SL_ATT1 Slave attributes 1 0x14 32 read-write 0x1F1F1F1F 0x1F1F1F1F PC4_UR Protection context 4, user read enable. [0:0] read-write PC4_UW Protection context 4, user write enable. [1:1] read-write PC4_PR Protection context 4, privileged read enable. [2:2] read-write PC4_PW Protection context 4, privileged write enable. [3:3] read-write PC4_NS Protection context 4, non-secure. [4:4] read-write PC5_UR Protection context 5, user read enable. [8:8] read-write PC5_UW Protection context 5, user write enable. [9:9] read-write PC5_PR Protection context 5, privileged read enable. [10:10] read-write PC5_PW Protection context 5, privileged write enable. [11:11] read-write PC5_NS Protection context 5, non-secure. [12:12] read-write PC6_UR Protection context 6, user read enable. [16:16] read-write PC6_UW Protection context 6, user write enable. [17:17] read-write PC6_PR Protection context 6, privileged read enable. [18:18] read-write PC6_PW Protection context 6, privileged write enable. [19:19] read-write PC6_NS Protection context 6, non-secure. [20:20] read-write PC7_UR Protection context 7, user read enable. [24:24] read-write PC7_UW Protection context 7, user write enable. [25:25] read-write PC7_PR Protection context 7, privileged read enable. [26:26] read-write PC7_PW Protection context 7, privileged write enable. [27:27] read-write PC7_NS Protection context 7, non-secure. [28:28] read-write SL_ATT2 Slave attributes 2 0x18 32 read-write 0x1F1F1F1F 0x1F1F1F1F PC8_UR Protection context 8, user read enable. [0:0] read-write PC8_UW Protection context 8, user write enable. [1:1] read-write PC8_PR Protection context 8, privileged read enable. [2:2] read-write PC8_PW Protection context 8, privileged write enable. [3:3] read-write PC8_NS Protection context 8, non-secure. [4:4] read-write PC9_UR Protection context 9, user read enable. [8:8] read-write PC9_UW Protection context 9, user write enable. [9:9] read-write PC9_PR Protection context 9, privileged read enable. [10:10] read-write PC9_PW Protection context 9, privileged write enable. [11:11] read-write PC9_NS Protection context 9, non-secure. [12:12] read-write PC10_UR Protection context 10, user read enable. [16:16] read-write PC10_UW Protection context 10, user write enable. [17:17] read-write PC10_PR Protection context 10, privileged read enable. [18:18] read-write PC10_PW Protection context 10, privileged write enable. [19:19] read-write PC10_NS Protection context 10, non-secure. [20:20] read-write PC11_UR Protection context 11, user read enable. [24:24] read-write PC11_UW Protection context 11, user write enable. [25:25] read-write PC11_PR Protection context 11, privileged read enable. [26:26] read-write PC11_PW Protection context 11, privileged write enable. [27:27] read-write PC11_NS Protection context 11, non-secure. [28:28] read-write SL_ATT3 Slave attributes 3 0x1C 32 read-write 0x1F1F1F1F 0x1F1F1F1F PC12_UR Protection context 12, user read enable. [0:0] read-write PC12_UW Protection context 12, user write enable. [1:1] read-write PC12_PR Protection context 12, privileged read enable. [2:2] read-write PC12_PW Protection context 12, privileged write enable. [3:3] read-write PC12_NS Protection context 12, non-secure. [4:4] read-write PC13_UR Protection context 13, user read enable. [8:8] read-write PC13_UW Protection context 13, user write enable. [9:9] read-write PC13_PR Protection context 13, privileged read enable. [10:10] read-write PC13_PW Protection context 13, privileged write enable. [11:11] read-write PC13_NS Protection context 13, non-secure. [12:12] read-write PC14_UR Protection context 14, user read enable. [16:16] read-write PC14_UW Protection context 14, user write enable. [17:17] read-write PC14_PR Protection context 14, privileged read enable. [18:18] read-write PC14_PW Protection context 14, privileged write enable. [19:19] read-write PC14_NS Protection context 14, non-secure. [20:20] read-write PC15_UR Protection context 15, user read enable. [24:24] read-write PC15_UW Protection context 15, user write enable. [25:25] read-write PC15_PR Protection context 15, privileged read enable. [26:26] read-write PC15_PW Protection context 15, privileged write enable. [27:27] read-write PC15_NS Protection context 15, non-secure. [28:28] read-write MS_ADDR Master region, base address 0x20 32 read-only 0x0 0xFFFFFFC0 ADDR26 This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register. [31:6] read-only MS_SIZE Master region, size 0x24 32 read-only 0x85000000 0x9F000000 REGION_SIZE This field specifies the size of the master region: '5': 64 B region The master region includes the SL_ADDR, SL_SIZE, SL_ATT0, ..., SL_ATT3, MS_ADDR, MS_SIZE, MS_ATT0, ..., MS_ATT3 registers. Therefore, the access privileges for all these registers is determined by MS_ATT0, ..., MS_ATT3. [28:24] read-only VALID Master region enable: '1': Enabled. [31:31] read-only MS_ATT0 Master attributes 0 0x30 32 read-write 0x1F1F1F1F 0x1F1F1F1F PC0_UR Protection context 0, user read enable: '0': Disabled (user, read accesses are NOT allowed). '1': Enabled (user, read accesses are allowed). [0:0] read-only PC0_UW Protection context 0, user write enable: '0': Disabled (user, write accesses are NOT allowed). '1': Enabled (user, write accesses are allowed). [1:1] read-only PC0_PR Protection context 0, privileged read enable: '0': Disabled (privileged, read accesses are NOT allowed). '1': Enabled (privileged, read accesses are allowed). [2:2] read-only PC0_PW Protection context 0, privileged write enable: '0': Disabled (privileged, write accesses are NOT allowed). '1': Enabled (privileged, write accesses are allowed). [3:3] read-only PC0_NS Protection context 0, non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed). [4:4] read-only PC1_UR Protection context 1, user read enable. [8:8] read-only PC1_UW Protection context 1, user write enable. [9:9] read-write PC1_PR Protection context 1, privileged read enable. [10:10] read-only PC1_PW Protection context 1, privileged write enable. [11:11] read-write PC1_NS Protection context 1, non-secure. [12:12] read-write PC2_UR Protection context 2, user read enable. [16:16] read-only PC2_UW Protection context 2, user write enable. [17:17] read-write PC2_PR Protection context 2, privileged read enable. [18:18] read-only PC2_PW Protection context 2, privileged write enable. [19:19] read-write PC2_NS Protection context 2, non-secure. [20:20] read-write PC3_UR Protection context 3, user read enable. [24:24] read-only PC3_UW Protection context 3, user write enable. [25:25] read-write PC3_PR Protection context 3, privileged read enable. [26:26] read-only PC3_PW Protection context 3, privileged write enable. [27:27] read-write PC3_NS Protection context 3, non-secure. [28:28] read-write MS_ATT1 Master attributes 1 0x34 32 read-write 0x1F1F1F1F 0x1F1F1F1F PC4_UR Protection context 4, user read enable. [0:0] read-only PC4_UW Protection context 4, user write enable. [1:1] read-write PC4_PR Protection context 4, privileged read enable. [2:2] read-only PC4_PW Protection context 4, privileged write enable. [3:3] read-write PC4_NS Protection context 4, non-secure. [4:4] read-write PC5_UR Protection context 5, user read enable. [8:8] read-only PC5_UW Protection context 5, user write enable. [9:9] read-write PC5_PR Protection context 5, privileged read enable. [10:10] read-only PC5_PW Protection context 5, privileged write enable. [11:11] read-write PC5_NS Protection context 5, non-secure. [12:12] read-write PC6_UR Protection context 6, user read enable. [16:16] read-only PC6_UW Protection context 6, user write enable. [17:17] read-write PC6_PR Protection context 6, privileged read enable. [18:18] read-only PC6_PW Protection context 6, privileged write enable. [19:19] read-write PC6_NS Protection context 6, non-secure. [20:20] read-write PC7_UR Protection context 7, user read enable. [24:24] read-only PC7_UW Protection context 7, user write enable. [25:25] read-write PC7_PR Protection context 7, privileged read enable. [26:26] read-only PC7_PW Protection context 7, privileged write enable. [27:27] read-write PC7_NS Protection context 7, non-secure. [28:28] read-write MS_ATT2 Master attributes 2 0x38 32 read-write 0x1F1F1F1F 0x1F1F1F1F PC8_UR Protection context 8, user read enable. [0:0] read-only PC8_UW Protection context 8, user write enable. [1:1] read-write PC8_PR Protection context 8, privileged read enable. [2:2] read-only PC8_PW Protection context 8, privileged write enable. [3:3] read-write PC8_NS Protection context 8, non-secure. [4:4] read-write PC9_UR Protection context 9, user read enable. [8:8] read-only PC9_UW Protection context 9, user write enable. [9:9] read-write PC9_PR Protection context 9, privileged read enable. [10:10] read-only PC9_PW Protection context 9, privileged write enable. [11:11] read-write PC9_NS Protection context 9, non-secure. [12:12] read-write PC10_UR Protection context 10, user read enable. [16:16] read-only PC10_UW Protection context 10, user write enable. [17:17] read-write PC10_PR Protection context 10, privileged read enable. [18:18] read-only PC10_PW Protection context 10, privileged write enable. [19:19] read-write PC10_NS Protection context 10, non-secure. [20:20] read-write PC11_UR Protection context 11, user read enable. [24:24] read-only PC11_UW Protection context 11, user write enable. [25:25] read-write PC11_PR Protection context 11, privileged read enable. [26:26] read-only PC11_PW Protection context 11, privileged write enable. [27:27] read-write PC11_NS Protection context 11, non-secure. [28:28] read-write MS_ATT3 Master attributes 3 0x3C 32 read-write 0x1F1F1F1F 0x1F1F1F1F PC12_UR Protection context 12, user read enable. [0:0] read-only PC12_UW Protection context 12, user write enable. [1:1] read-write PC12_PR Protection context 12, privileged read enable. [2:2] read-only PC12_PW Protection context 12, privileged write enable. [3:3] read-write PC12_NS Protection context 12, non-secure. [4:4] read-write PC13_UR Protection context 13, user read enable. [8:8] read-only PC13_UW Protection context 13, user write enable. [9:9] read-write PC13_PR Protection context 13, privileged read enable. [10:10] read-only PC13_PW Protection context 13, privileged write enable. [11:11] read-write PC13_NS Protection context 13, non-secure. [12:12] read-write PC14_UR Protection context 14, user read enable. [16:16] read-only PC14_UW Protection context 14, user write enable. [17:17] read-write PC14_PR Protection context 14, privileged read enable. [18:18] read-only PC14_PW Protection context 14, privileged write enable. [19:19] read-write PC14_NS Protection context 14, non-secure. [20:20] read-write PC15_UR Protection context 15, user read enable. [24:24] read-only PC15_UW Protection context 15, user write enable. [25:25] read-write PC15_PR Protection context 15, privileged read enable. [26:26] read-only PC15_PW Protection context 15, privileged write enable. [27:27] read-write PC15_NS Protection context 15, non-secure. [28:28] read-write 219 64 PPU_FX[%s] Fixed protection structure pair 0x00000800 SL_ADDR Slave region, base address 0x0 32 read-only 0x0 0xFFFFFFFC ADDR30 This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore, some of the lesser significant address bits of ADDR30 must be '0's. E.g., a 64 KB address region (REGION_SIZE is '15') must be 64 KByte aligned, and ADDR30[13:0] must be '0's. [31:2] read-only SL_SIZE Slave region, size 0x4 32 read-only 0x80000000 0x9F000000 REGION_SIZE This field specifies the size of the slave region: '0': Undefined. '1': 4 B region (this is the smallest region size). '2': 8 B region '3': 16 B region '4': 32 B region '5': 64 B region '6': 128 B region '7': 256 B region '8': 512 B region '9': 1 KB region '10': 2 KB region '11': 4 KB region '12': 8 KB region '13': 16 KB region '14': 32 KB region '15': 64 KB region '16': 128 KB region '17': 256 KB region '18': 512 KB region '19': 1 MB region '20': 2 MB region '21': 4 MB region '22': 8 MB region '23': 16 MB region '24': 32 MB region '25': 64 MB region '26': 128 MB region '27': 256 MB region '28': 512 MB region '29': 1 GB region '30': 2 GB region '31': 4 GB region [28:24] read-only VALID Slave region enable: '0': Disabled. A disabled region will never result in a match on the transfer address. '1': Enabled. [31:31] read-only SL_ATT0 Slave attributes 0 0x10 32 read-write 0x1F1F1F1F 0x1F1F1F1F PC0_UR Protection context 0, user read enable: '0': Disabled (user, read accesses are NOT allowed). '1': Enabled (user, read accesses are allowed). [0:0] read-only PC0_UW Protection context 0, user write enable: '0': Disabled (user, write accesses are NOT allowed). '1': Enabled (user, write accesses are allowed). [1:1] read-only PC0_PR Protection context 0, privileged read enable: '0': Disabled (privileged, read accesses are NOT allowed). '1': Enabled (privileged, read accesses are allowed). [2:2] read-only PC0_PW Protection context 0, privileged write enable: '0': Disabled (privileged, write accesses are NOT allowed). '1': Enabled (privileged, write accesses are allowed). [3:3] read-only PC0_NS Protection context 0, non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed). [4:4] read-only PC1_UR Protection context 1, user read enable. [8:8] read-write PC1_UW Protection context 1, user write enable. [9:9] read-write PC1_PR Protection context 1, privileged read enable. [10:10] read-write PC1_PW Protection context 1, privileged write enable. [11:11] read-write PC1_NS Protection context 1, non-secure. [12:12] read-write PC2_UR Protection context 2, user read enable. [16:16] read-write PC2_UW Protection context 2, user write enable. [17:17] read-write PC2_PR Protection context 2, privileged read enable. [18:18] read-write PC2_PW Protection context 2, privileged write enable. [19:19] read-write PC2_NS Protection context 2, non-secure. [20:20] read-write PC3_UR Protection context 3, user read enable. [24:24] read-write PC3_UW Protection context 3, user write enable. [25:25] read-write PC3_PR Protection context 3, privileged read enable. [26:26] read-write PC3_PW Protection context 3, privileged write enable. [27:27] read-write PC3_NS Protection context 3, non-secure. [28:28] read-write SL_ATT1 Slave attributes 1 0x14 32 read-write 0x1F1F1F1F 0x1F1F1F1F PC4_UR Protection context 4, user read enable. [0:0] read-write PC4_UW Protection context 4, user write enable. [1:1] read-write PC4_PR Protection context 4, privileged read enable. [2:2] read-write PC4_PW Protection context 4, privileged write enable. [3:3] read-write PC4_NS Protection context 4, non-secure. [4:4] read-write PC5_UR Protection context 5, user read enable. [8:8] read-write PC5_UW Protection context 5, user write enable. [9:9] read-write PC5_PR Protection context 5, privileged read enable. [10:10] read-write PC5_PW Protection context 5, privileged write enable. [11:11] read-write PC5_NS Protection context 5, non-secure. [12:12] read-write PC6_UR Protection context 6, user read enable. [16:16] read-write PC6_UW Protection context 6, user write enable. [17:17] read-write PC6_PR Protection context 6, privileged read enable. [18:18] read-write PC6_PW Protection context 6, privileged write enable. [19:19] read-write PC6_NS Protection context 6, non-secure. [20:20] read-write PC7_UR Protection context 7, user read enable. [24:24] read-write PC7_UW Protection context 7, user write enable. [25:25] read-write PC7_PR Protection context 7, privileged read enable. [26:26] read-write PC7_PW Protection context 7, privileged write enable. [27:27] read-write PC7_NS Protection context 7, non-secure. [28:28] read-write SL_ATT2 Slave attributes 2 0x18 32 read-write 0x1F1F1F1F 0x1F1F1F1F PC8_UR Protection context 8, user read enable. [0:0] read-write PC8_UW Protection context 8, user write enable. [1:1] read-write PC8_PR Protection context 8, privileged read enable. [2:2] read-write PC8_PW Protection context 8, privileged write enable. [3:3] read-write PC8_NS Protection context 8, non-secure. [4:4] read-write PC9_UR Protection context 9, user read enable. [8:8] read-write PC9_UW Protection context 9, user write enable. [9:9] read-write PC9_PR Protection context 9, privileged read enable. [10:10] read-write PC9_PW Protection context 9, privileged write enable. [11:11] read-write PC9_NS Protection context 9, non-secure. [12:12] read-write PC10_UR Protection context 10, user read enable. [16:16] read-write PC10_UW Protection context 10, user write enable. [17:17] read-write PC10_PR Protection context 10, privileged read enable. [18:18] read-write PC10_PW Protection context 10, privileged write enable. [19:19] read-write PC10_NS Protection context 10, non-secure. [20:20] read-write PC11_UR Protection context 11, user read enable. [24:24] read-write PC11_UW Protection context 11, user write enable. [25:25] read-write PC11_PR Protection context 11, privileged read enable. [26:26] read-write PC11_PW Protection context 11, privileged write enable. [27:27] read-write PC11_NS Protection context 11, non-secure. [28:28] read-write SL_ATT3 Slave attributes 3 0x1C 32 read-write 0x1F1F1F1F 0x1F1F1F1F PC12_UR Protection context 12, user read enable. [0:0] read-write PC12_UW Protection context 12, user write enable. [1:1] read-write PC12_PR Protection context 12, privileged read enable. [2:2] read-write PC12_PW Protection context 12, privileged write enable. [3:3] read-write PC12_NS Protection context 12, non-secure. [4:4] read-write PC13_UR Protection context 13, user read enable. [8:8] read-write PC13_UW Protection context 13, user write enable. [9:9] read-write PC13_PR Protection context 13, privileged read enable. [10:10] read-write PC13_PW Protection context 13, privileged write enable. [11:11] read-write PC13_NS Protection context 13, non-secure. [12:12] read-write PC14_UR Protection context 14, user read enable. [16:16] read-write PC14_UW Protection context 14, user write enable. [17:17] read-write PC14_PR Protection context 14, privileged read enable. [18:18] read-write PC14_PW Protection context 14, privileged write enable. [19:19] read-write PC14_NS Protection context 14, non-secure. [20:20] read-write PC15_UR Protection context 15, user read enable. [24:24] read-write PC15_UW Protection context 15, user write enable. [25:25] read-write PC15_PR Protection context 15, privileged read enable. [26:26] read-write PC15_PW Protection context 15, privileged write enable. [27:27] read-write PC15_NS Protection context 15, non-secure. [28:28] read-write MS_ADDR Master region, base address 0x20 32 read-only 0x0 0xFFFFFFC0 ADDR26 This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register. [31:6] read-only MS_SIZE Master region, size 0x24 32 read-only 0x85000000 0x9F000000 REGION_SIZE This field specifies the size of the master region: '5': 64 B region The master region includes the SL_ADDR, SL_SIZE, SL_ATT0, ..., SL_ATT3, MS_ADDR, MS_SIZE, MS_ATT0, ..., MS_ATT3 registers. Therefore, the access privileges for all these registers is determined by MS_ATT0, ..., MS_ATT3. [28:24] read-only VALID Master region enable: '1': Enabled. [31:31] read-only MS_ATT0 Master attributes 0 0x30 32 read-write 0x1F1F1F1F 0x1F1F1F1F PC0_UR Protection context 0, user read enable: '0': Disabled (user, read accesses are NOT allowed). '1': Enabled (user, read accesses are allowed). [0:0] read-only PC0_UW Protection context 0, user write enable: '0': Disabled (user, write accesses are NOT allowed). '1': Enabled (user, write accesses are allowed). [1:1] read-only PC0_PR Protection context 0, privileged read enable: '0': Disabled (privileged, read accesses are NOT allowed). '1': Enabled (privileged, read accesses are allowed). [2:2] read-only PC0_PW Protection context 0, privileged write enable: '0': Disabled (privileged, write accesses are NOT allowed). '1': Enabled (privileged, write accesses are allowed). [3:3] read-only PC0_NS Protection context 0, non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed). [4:4] read-only PC1_UR Protection context 1, user read enable. [8:8] read-only PC1_UW Protection context 1, user write enable. [9:9] read-write PC1_PR Protection context 1, privileged read enable. [10:10] read-only PC1_PW Protection context 1, privileged write enable. [11:11] read-write PC1_NS Protection context 1, non-secure. [12:12] read-write PC2_UR Protection context 2, user read enable. [16:16] read-only PC2_UW Protection context 2, user write enable. [17:17] read-write PC2_PR Protection context 2, privileged read enable. [18:18] read-only PC2_PW Protection context 2, privileged write enable. [19:19] read-write PC2_NS Protection context 2, non-secure. [20:20] read-write PC3_UR Protection context 3, user read enable. [24:24] read-only PC3_UW Protection context 3, user write enable. [25:25] read-write PC3_PR Protection context 3, privileged read enable. [26:26] read-only PC3_PW Protection context 3, privileged write enable. [27:27] read-write PC3_NS Protection context 3, non-secure. [28:28] read-write MS_ATT1 Master attributes 1 0x34 32 read-write 0x1F1F1F1F 0x1F1F1F1F PC4_UR Protection context 4, user read enable. [0:0] read-only PC4_UW Protection context 4, user write enable. [1:1] read-write PC4_PR Protection context 4, privileged read enable. [2:2] read-only PC4_PW Protection context 4, privileged write enable. [3:3] read-write PC4_NS Protection context 4, non-secure. [4:4] read-write PC5_UR Protection context 5, user read enable. [8:8] read-only PC5_UW Protection context 5, user write enable. [9:9] read-write PC5_PR Protection context 5, privileged read enable. [10:10] read-only PC5_PW Protection context 5, privileged write enable. [11:11] read-write PC5_NS Protection context 5, non-secure. [12:12] read-write PC6_UR Protection context 6, user read enable. [16:16] read-only PC6_UW Protection context 6, user write enable. [17:17] read-write PC6_PR Protection context 6, privileged read enable. [18:18] read-only PC6_PW Protection context 6, privileged write enable. [19:19] read-write PC6_NS Protection context 6, non-secure. [20:20] read-write PC7_UR Protection context 7, user read enable. [24:24] read-only PC7_UW Protection context 7, user write enable. [25:25] read-write PC7_PR Protection context 7, privileged read enable. [26:26] read-only PC7_PW Protection context 7, privileged write enable. [27:27] read-write PC7_NS Protection context 7, non-secure. [28:28] read-write MS_ATT2 Master attributes 2 0x38 32 read-write 0x1F1F1F1F 0x1F1F1F1F PC8_UR Protection context 8, user read enable. [0:0] read-only PC8_UW Protection context 8, user write enable. [1:1] read-write PC8_PR Protection context 8, privileged read enable. [2:2] read-only PC8_PW Protection context 8, privileged write enable. [3:3] read-write PC8_NS Protection context 8, non-secure. [4:4] read-write PC9_UR Protection context 9, user read enable. [8:8] read-only PC9_UW Protection context 9, user write enable. [9:9] read-write PC9_PR Protection context 9, privileged read enable. [10:10] read-only PC9_PW Protection context 9, privileged write enable. [11:11] read-write PC9_NS Protection context 9, non-secure. [12:12] read-write PC10_UR Protection context 10, user read enable. [16:16] read-only PC10_UW Protection context 10, user write enable. [17:17] read-write PC10_PR Protection context 10, privileged read enable. [18:18] read-only PC10_PW Protection context 10, privileged write enable. [19:19] read-write PC10_NS Protection context 10, non-secure. [20:20] read-write PC11_UR Protection context 11, user read enable. [24:24] read-only PC11_UW Protection context 11, user write enable. [25:25] read-write PC11_PR Protection context 11, privileged read enable. [26:26] read-only PC11_PW Protection context 11, privileged write enable. [27:27] read-write PC11_NS Protection context 11, non-secure. [28:28] read-write MS_ATT3 Master attributes 3 0x3C 32 read-write 0x1F1F1F1F 0x1F1F1F1F PC12_UR Protection context 12, user read enable. [0:0] read-only PC12_UW Protection context 12, user write enable. [1:1] read-write PC12_PR Protection context 12, privileged read enable. [2:2] read-only PC12_PW Protection context 12, privileged write enable. [3:3] read-write PC12_NS Protection context 12, non-secure. [4:4] read-write PC13_UR Protection context 13, user read enable. [8:8] read-only PC13_UW Protection context 13, user write enable. [9:9] read-write PC13_PR Protection context 13, privileged read enable. [10:10] read-only PC13_PW Protection context 13, privileged write enable. [11:11] read-write PC13_NS Protection context 13, non-secure. [12:12] read-write PC14_UR Protection context 14, user read enable. [16:16] read-only PC14_UW Protection context 14, user write enable. [17:17] read-write PC14_PR Protection context 14, privileged read enable. [18:18] read-only PC14_PW Protection context 14, privileged write enable. [19:19] read-write PC14_NS Protection context 14, non-secure. [20:20] read-write PC15_UR Protection context 15, user read enable. [24:24] read-only PC15_UW Protection context 15, user write enable. [25:25] read-write PC15_PR Protection context 15, privileged read enable. [26:26] read-only PC15_PW Protection context 15, privileged write enable. [27:27] read-write PC15_NS Protection context 15, non-secure. [28:28] read-write CPUSS CPU subsystem (CPUSS) 0x40200000 0 65536 registers ioss_interrupts_gpio_dpslp_0 GPIO Port Interrupt #0 0 ioss_interrupts_gpio_dpslp_1 GPIO Port Interrupt #1 1 ioss_interrupts_gpio_dpslp_4 GPIO Port Interrupt #4 2 ioss_interrupts_gpio_dpslp_5 GPIO Port Interrupt #5 3 ioss_interrupts_gpio_dpslp_6 GPIO Port Interrupt #6 4 ioss_interrupts_gpio_dpslp_7 GPIO Port Interrupt #7 5 ioss_interrupts_gpio_dpslp_8 GPIO Port Interrupt #8 6 ioss_interrupts_gpio_dpslp_9 GPIO Port Interrupt #9 7 ioss_interrupts_gpio_dpslp_10 GPIO Port Interrupt #10 8 ioss_interrupts_gpio_dpslp_11 GPIO Port Interrupt #11 9 ioss_interrupts_gpio_dpslp_12 GPIO Port Interrupt #12 10 ioss_interrupts_gpio_dpslp_13 GPIO Port Interrupt #13 11 ioss_interrupt_gpio_dpslp GPIO All Ports 12 ioss_interrupt_vdd GPIO Supply Detect Interrupt 13 scb_0_interrupt Serial Communication Block #6 (DeepSleep capable) 14 srss_interrupt_mcwdt_0 Multi Counter Watchdog Timer interrupt 15 srss_interrupt_mcwdt_1 Multi Counter Watchdog Timer interrupt 16 usbhsdev_interrupt_u2d_dpslp_o USBHS DEV interuupt 17 srss_interrupt Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) 18 cpuss_interrupts_ipc_0 CPUSS Inter Process Communication Interrupt #0 19 cpuss_interrupts_ipc_1 CPUSS Inter Process Communication Interrupt #1 20 cpuss_interrupts_ipc_2 CPUSS Inter Process Communication Interrupt #2 21 cpuss_interrupts_ipc_3 CPUSS Inter Process Communication Interrupt #3 22 cpuss_interrupts_ipc_4 CPUSS Inter Process Communication Interrupt #4 23 cpuss_interrupts_ipc_5 CPUSS Inter Process Communication Interrupt #5 24 cpuss_interrupts_ipc_6 CPUSS Inter Process Communication Interrupt #6 25 cpuss_interrupts_ipc_7 CPUSS Inter Process Communication Interrupt #7 26 cpuss_interrupts_ipc_8 CPUSS Inter Process Communication Interrupt #8 27 cpuss_interrupts_ipc_9 CPUSS Inter Process Communication Interrupt #9 28 cpuss_interrupts_ipc_10 CPUSS Inter Process Communication Interrupt #10 29 cpuss_interrupts_ipc_11 CPUSS Inter Process Communication Interrupt #11 30 cpuss_interrupts_ipc_12 CPUSS Inter Process Communication Interrupt #12 31 cpuss_interrupts_ipc_13 CPUSS Inter Process Communication Interrupt #13 32 cpuss_interrupts_ipc_14 CPUSS Inter Process Communication Interrupt #14 33 cpuss_interrupts_ipc_15 CPUSS Inter Process Communication Interrupt #15 34 scb_1_interrupt Serial Communication Block #1 46 scb_2_interrupt Serial Communication Block #2 47 scb_3_interrupt Serial Communication Block #3 48 scb_4_interrupt Serial Communication Block #4 49 scb_5_interrupt Serial Communication Block #5 50 scb_6_interrupt Serial Communication Block #6 51 cpuss_interrupts_dmac_0 CPUSS DMAC, Channel #0 52 cpuss_interrupts_dmac_1 CPUSS DMAC, Channel #1 53 cpuss_interrupts_dmac_2 CPUSS DMAC, Channel #2 54 cpuss_interrupts_dmac_3 CPUSS DMAC, Channel #3 55 cpuss_interrupts_dmac_4 CPUSS DMAC, Channel #4 56 cpuss_interrupts_dmac_5 CPUSS DMAC, Channel #5 57 cpuss_interrupts_dw0_0 CPUSS DataWire #0, Channel #0 58 cpuss_interrupts_dw0_1 CPUSS DataWire #0, Channel #1 59 cpuss_interrupts_dw0_2 CPUSS DataWire #0, Channel #2 60 cpuss_interrupts_dw0_3 CPUSS DataWire #0, Channel #3 61 cpuss_interrupts_dw0_4 CPUSS DataWire #0, Channel #4 62 cpuss_interrupts_dw0_5 CPUSS DataWire #0, Channel #5 63 cpuss_interrupts_dw0_6 CPUSS DataWire #0, Channel #6 64 cpuss_interrupts_dw0_7 CPUSS DataWire #0, Channel #7 65 cpuss_interrupts_dw0_8 CPUSS DataWire #0, Channel #8 66 cpuss_interrupts_dw0_9 CPUSS DataWire #0, Channel #9 67 cpuss_interrupts_dw0_10 CPUSS DataWire #0, Channel #10 68 cpuss_interrupts_dw0_11 CPUSS DataWire #0, Channel #11 69 cpuss_interrupts_dw0_12 CPUSS DataWire #0, Channel #12 70 cpuss_interrupts_dw0_13 CPUSS DataWire #0, Channel #13 71 cpuss_interrupts_dw0_14 CPUSS DataWire #0, Channel #14 72 cpuss_interrupts_dw0_15 CPUSS DataWire #0, Channel #15 73 cpuss_interrupts_dw0_16 CPUSS DataWire #0, Channel #16 74 cpuss_interrupts_dw0_17 CPUSS DataWire #0, Channel #17 75 cpuss_interrupts_dw0_18 CPUSS DataWire #0, Channel #18 76 cpuss_interrupts_dw0_19 CPUSS DataWire #0, Channel #19 77 cpuss_interrupts_dw0_20 CPUSS DataWire #0, Channel #20 78 cpuss_interrupts_dw0_21 CPUSS DataWire #0, Channel #21 79 cpuss_interrupts_dw0_22 CPUSS DataWire #0, Channel #22 80 cpuss_interrupts_dw0_23 CPUSS DataWire #0, Channel #23 81 cpuss_interrupts_dw1_0 CPUSS DataWire #1, Channel #0 82 cpuss_interrupts_dw1_1 CPUSS DataWire #1, Channel #1 83 cpuss_interrupts_dw1_2 CPUSS DataWire #1, Channel #2 84 cpuss_interrupts_dw1_3 CPUSS DataWire #1, Channel #3 85 cpuss_interrupts_dw1_4 CPUSS DataWire #1, Channel #4 86 cpuss_interrupts_dw1_5 CPUSS DataWire #1, Channel #5 87 cpuss_interrupts_dw1_6 CPUSS DataWire #1, Channel #6 88 cpuss_interrupts_dw1_7 CPUSS DataWire #1, Channel #7 89 cpuss_interrupts_dw1_8 CPUSS DataWire #1, Channel #8 90 cpuss_interrupts_dw1_9 CPUSS DataWire #1, Channel #9 91 cpuss_interrupts_dw1_10 CPUSS DataWire #1, Channel #10 92 cpuss_interrupts_dw1_11 CPUSS DataWire #1, Channel #11 93 cpuss_interrupts_dw1_12 CPUSS DataWire #1, Channel #12 94 cpuss_interrupts_dw1_13 CPUSS DataWire #1, Channel #13 95 cpuss_interrupts_dw1_14 CPUSS DataWire #1, Channel #14 96 cpuss_interrupts_dw1_15 CPUSS DataWire #1, Channel #15 97 cpuss_interrupts_dw1_16 CPUSS DataWire #1, Channel #16 98 cpuss_interrupts_dw1_17 CPUSS DataWire #1, Channel #17 99 cpuss_interrupts_dw1_18 CPUSS DataWire #1, Channel #18 100 cpuss_interrupts_dw1_19 CPUSS DataWire #1, Channel #19 101 cpuss_interrupts_dw1_20 CPUSS DataWire #1, Channel #20 102 cpuss_interrupts_dw1_21 CPUSS DataWire #1, Channel #21 103 cpuss_interrupts_dw1_22 CPUSS DataWire #1, Channel #22 104 cpuss_interrupts_dw1_23 CPUSS DataWire #1, Channel #23 105 cpuss_interrupts_fault_0 CPUSS Fault Structure Interrupt #0 106 cpuss_interrupts_fault_1 CPUSS Fault Structure Interrupt #1 107 cpuss_interrupt_crypto CRYPTO Accelerator Interrupt 108 cpuss_interrupt_fm FLASH Macro Interrupt 109 cpuss_interrupts_cm4_fp Floating Point operation fault 110 cpuss_interrupts_cm0_cti_0 CM0+ CTI #0 111 cpuss_interrupts_cm0_cti_1 CM0+ CTI #1 112 cpuss_interrupts_cm4_cti_0 CM4 CTI #0 113 cpuss_interrupts_cm4_cti_1 CM4 CTI #1 114 tcpwm_0_interrupts_0 TCPWM #0, Counter #0 115 tcpwm_0_interrupts_1 TCPWM #0, Counter #1 116 tcpwm_0_interrupts_2 TCPWM #0, Counter #2 117 tcpwm_0_interrupts_3 TCPWM #0, Counter #3 118 tcpwm_0_interrupts_4 TCPWM #0, Counter #4 119 tcpwm_0_interrupts_5 TCPWM #0, Counter #5 120 tcpwm_0_interrupts_6 TCPWM #0, Counter #6 121 tcpwm_0_interrupts_7 TCPWM #0, Counter #7 122 tdm_0_interrupts_rx_0 TDM0 Audio interrupt RX 123 tdm_0_interrupts_tx_0 TDM0 Audio interrupt TX 124 smif_interrupt Serial Memory Interface interrupt 125 usb_interrupt_hi USB Interrupt 126 usb_interrupt_med USB Interrupt 127 usb_interrupt_lo USB Interrupt 128 usbhsdev_interrupt_u2d_active_o USB HS dev Interrupt 129 canfd_0_interrupt0 Can #0, Consolidated interrupt #0 130 canfd_0_interrupts0_0 CAN #0, Interrupt #0, Channel #0 131 canfd_0_interrupts1_0 CAN #0, Interrupt #1, Channel #0 132 pdm_0_interrupts_0 PDM interrupt 133 pdm_0_interrupts_1 PDM interrupt 134 lvds2usb32ss_lvds_int_o 135 lvds2usb32ss_lvds_pdma_int_o 136 lvds2usb32ss_lvds_wakeup_int_o 137 lvds2usb32ss_usb32_egrs_dma_int_o 138 lvds2usb32ss_usb32_ingrs_dma_int_o 139 lvds2usb32ss_usb32_int_o 140 lvds2usb32ss_usb32_wakeup_int_o 141 IDENTITY Identity 0x0 32 read-only 0x0 0x0 P This field specifies the privileged setting ('0': user mode; '1': privileged mode) of the transfer that reads the register. [0:0] read-only NS This field specifies the security setting ('0': secure mode; '1': non-secure mode) of the transfer that reads the register. [1:1] read-only PC This field specifies the protection context of the transfer that reads the register. [7:4] read-only MS This field specifies the bus master identifier of the transfer that reads the register. [11:8] read-only CM4_STATUS CM4 status 0x4 32 read-only 0x13 0x13 SLEEPING Specifies if the CPU is in Active, Sleep or DeepSleep power mode: - Active power mode: SLEEPING is '0'. - Sleep power mode: SLEEPING is '1' and SLEEPDEEP is '0'. - DeepSleep power mode: SLEEPING is '1' and SLEEPDEEP is '1'. [0:0] read-only SLEEPDEEP Specifies if the CPU is in Sleep or DeepSleep power mode. See SLEEPING field. [1:1] read-only PWR_DONE After a PWR_MODE change this flag indicates if the new power mode has taken effect or not. Note: this flag can also change as a result of a change in debug power up req [4:4] read-only CM4_CLOCK_CTL CM4 clock control 0x8 32 read-write 0x0 0xFF00 FAST_INT_DIV Specifies the fast clock divider (from the high frequency clock 'clk_hf' to the peripheral clock 'clk_fast'). Integer division by (1+FAST_INT_DIV). Allows for integer divisions in the range [1, 256] (FAST_INT_DIV is in the range [0, 255]). Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. [15:8] read-write CM4_CTL CM4 control 0xC 32 read-write 0x0 0x9F000000 IOC_MASK CPU floating point unit (FPU) exception mask for the CPU's FPCSR.IOC 'invalid operation' exception condition: '0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. '1': the CPU's exception condition activates the CPU's floating point interrupt. Note: the ARM architecture does NOT support FPU exceptions; i.e. there is no precise FPU exception handler. Instead, FPU conditions are captured in the CPU's FPCSR register and the conditions are provided as CPU interface signals. The interface signals are 'masked' with the fields a provide by this register (CM7_0_CTL). The 'masked' signals are reduced/OR-ed into a single CPU floating point interrupt signal. The associated CPU interrupt handler allows for imprecise handling of FPU exception conditions. Note: the CPU's FPCSR exception conditions are 'sticky'. Typically, the CPU FPU interrupt handler will clear the exception condition(s) to '0'. Note: by default, the FPU exception masks are '0'. Therefore, FPU exception conditions will NOT activate the CPU's floating point interrupt. [24:24] read-write DZC_MASK CPU FPU exception mask for the CPU's FPCSR.DZC 'divide by zero' exception condition: '0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. '1': the CPU's exception condition activates the CPU's floating point interrupt. [25:25] read-write OFC_MASK CPU FPU exception mask for the CPU's FPCSR.OFC 'overflow' exception condition: '0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. '1': the CPU's exception condition activates the CPU's floating point interrupt. [26:26] read-write UFC_MASK CPU FPU exception mask for the CPU's FPCSR.UFC 'underflow' exception condition: '0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. '1': the CPU's exception condition activates the CPU's floating point interrupt. [27:27] read-write IXC_MASK CPU FPU exception mask for the CPU's FPCSR.IXC 'inexact' exception condition: '0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. '1': the CPU's exception condition activates the CPU's floating point interrupt. Note: the 'inexact' condition is set as a result of rounding. Rounding may occur frequently and is typically not an error condition. To prevent frequent CPU FPU interrupts as a result of rounding, this field is typically set to '0'. [28:28] read-write IDC_MASK CPU FPU exception mask for the CPU's FPCSR.IDC 'input denormalized' exception condition: '0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. '1': the CPU's exception condition activates the CPU's floating point interrupt. Note: if the CPU FPCSR.FZ field is set to '1', denormalized inputs are 'flushed to zero'. Dependent on the FPU algorithm, this may or may not occur frequently. To prevent frequent CPU FPU interrupts as a result of denormalized inputs, this field may be set to '0'. [31:31] read-write CM4_INT0_STATUS CM4 interrupt 0 status 0x100 32 read-only 0x0 0x80000000 SYSTEM_INT_IDX Lowest CM4 activated system interrupt index for CPU interrupt 0. See description of CM0_INT0_STATUS. [9:0] read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. [31:31] read-only CM4_INT1_STATUS CM4 interrupt 1 status 0x104 32 read-only 0x0 0x80000000 SYSTEM_INT_IDX Lowest CM4 activated system interrupt index for CPU interrupt 1. See description of CM0_INT0_STATUS. [9:0] read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. [31:31] read-only CM4_INT2_STATUS CM4 interrupt 2 status 0x108 32 read-only 0x0 0x80000000 SYSTEM_INT_IDX Lowest CM4 activated system interrupt index for CPU interrupt 2. See description of CM0_INT0_STATUS. [9:0] read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. [31:31] read-only CM4_INT3_STATUS CM4 interrupt 3 status 0x10C 32 read-only 0x0 0x80000000 SYSTEM_INT_IDX Lowest CM4 activated system interrupt index for CPU interrupt 3. See description of CM0_INT0_STATUS. [9:0] read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. [31:31] read-only CM4_INT4_STATUS CM4 interrupt 4 status 0x110 32 read-only 0x0 0x80000000 SYSTEM_INT_IDX Lowest CM4 activated system interrupt index for CPU interrupt 4. See description of CM0_INT0_STATUS. [9:0] read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. [31:31] read-only CM4_INT5_STATUS CM4 interrupt 5 status 0x114 32 read-only 0x0 0x80000000 SYSTEM_INT_IDX Lowest CM4 activated system interrupt index for CPU interrupt 5. See description of CM0_INT0_STATUS. [9:0] read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. [31:31] read-only CM4_INT6_STATUS CM4 interrupt 6 status 0x118 32 read-only 0x0 0x80000000 SYSTEM_INT_IDX Lowest CM4 activated system interrupt index for CPU interrupt 6. See description of CM0_INT0_STATUS. [9:0] read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. [31:31] read-only CM4_INT7_STATUS CM4 interrupt 7 status 0x11C 32 read-only 0x0 0x80000000 SYSTEM_INT_IDX Lowest CM4 activated system interrupt index for CPU interrupt 7. See description of CM0_INT0_STATUS. [9:0] read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. [31:31] read-only CM4_VECTOR_TABLE_BASE CM4 vector table base 0x200 32 read-write 0x0 0xFFFFFC00 ADDR22 Address of CM4 vector table. This register is used for CM4 warm and cold boot purposes: the CM0+ CPU initializes the CM4_VECTOR_TABLE_BASE register and the CM4 boot code uses the register to initialize the CM4 internal VTOR register. Note: the CM4 vector table is at an address that is a 1024 B multiple. [31:10] read-write 4 4 CM4_NMI_CTL[%s] CM4 NMI control 0x240 32 read-write 0x3FF 0x3FF SYSTEM_INT_IDX System interrupt select for CPU NMI. The reset value ('1023') ensures that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset. [9:0] read-write UDB_PWR_CTL UDB power control 0x300 32 read-write 0xFA050001 0xFFFF0003 PWR_MODE Set Power mode for UDBs [1:0] read-write OFF See CM4_PWR_CTL 0 RESET See CM4_PWR_CTL 1 RETAINED See CM4_PWR_CTL 2 ENABLED See CM4_PWR_CTL 3 VECTKEYSTAT Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. [31:16] read-only UDB_PWR_DELAY_CTL UDB power control 0x304 32 read-write 0x12C 0x3FF UP Number clock cycles delay needed after power domain power up [9:0] read-write CM0_CTL CM0+ control 0x1000 32 read-write 0xFA050002 0xFFFF0003 SLV_STALL Processor debug access control: '0': Access. '1': Stall access. This field is used to stall/delay debug accesses. This is useful to protect execution of code that needs to be protected from debug accesses. [0:0] read-write ENABLED Processor enable: '0': Disabled. Processor clock is turned off and reset is activated. After SW clears this field to '0', HW automatically sets this field to '1'. This effectively results in a CM0+ reset, followed by a CM0+ warm boot. '1': Enabled. Note: The intent is that this bit is modified only through an external probe or by the CM4 while the CM0+ is in Sleep or DeepSleep power mode. If this field is cleared to '0' by the CM0+ itself, it should be done under controlled conditions (such that undesirable side effects can be prevented). Note: The CM0+ CPU has a AIRCR.SYSRESETREQ register field that allows the CM0+ to reset the complete device (ENABLED only disables/enables the CM0+), resulting in a warm boot. This CPU register field has similar 'built-in protection' as this CM0_CTL register to prevent accidental system writes (the upper 16-bits of the register need to be written with a 0x05fa key value; see CPU user manual for more details). [1:1] read-write VECTKEYSTAT Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. [31:16] read-only CM0_STATUS CM0+ status 0x1004 32 read-only 0x0 0x3 SLEEPING Specifies if the CPU is in Active, Sleep or DeepSleep power mode: - Active power mode: SLEEPING is '0'. - Sleep power mode: SLEEPING is '1' and SLEEPDEEP is '0'. - DeepSleep power mode: SLEEPING is '1' and SLEEPDEEP is '1'. [0:0] read-only SLEEPDEEP Specifies if the CPU is in Sleep or DeepSleep power mode. See SLEEPING field. [1:1] read-only CM0_CLOCK_CTL CM0+ clock control 0x1008 32 read-write 0x0 0xFF00FF00 SLOW_INT_DIV Specifies the slow clock divider (from the peripheral clock 'clk_peri' to the slow clock 'clk_slow'). Integer division by (1+SLOW_INT_DIV). Allows for integer divisions in the range [1, 256] (SLOW_INT_DIV is in the range [0, 255]). Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. [15:8] read-write PERI_INT_DIV Specifies the peripheral clock divider (from the high frequency clock 'clk_hf' to the peripheral clock 'clk_peri'). Integer division by (1+PERI_INT_DIV). Allows for integer divisions in the range [1, 256] (PERI_INT_DIV is in the range [0, 255]). Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. Note that Fperi <= Fperi_max. Fperi_max is likely to be smaller than Fhf_max. In other words, if Fhf = Fhf_max, PERI_INT_DIV should not be set to '0'. [31:24] read-write CM0_INT0_STATUS CM0+ interrupt 0 status 0x1100 32 read-only 0x0 0x80000000 SYSTEM_INT_IDX Lowest CM0+ activated system interrupt index for CPU interrupt 0. Multiple system interrupts can be mapped on the same CPU interrupt. The selected system interrupt is the system interrupt with the lowest system interrupt index that has an activated interrupt request at the time of the fetch (system_interrupts[SYSTEM_INT_IDX] is '1'). The CPU interrupt handler SW can read SYSTEM_INT_IDX to determine the system interrupt that activated the handler. [9:0] read-only SYSTEM_INT_VALID Valid indication for SYSTEM_INT_IDX. When '0', no system interrupt for CPU interrupt 0 is valid/activated. [31:31] read-only CM0_INT1_STATUS CM0+ interrupt 1 status 0x1104 32 read-only 0x0 0x80000000 SYSTEM_INT_IDX Lowest CM0+ activated system interrupt index for CPU interrupt 1. See description of CM0_INT0_STATUS. [9:0] read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. [31:31] read-only CM0_INT2_STATUS CM0+ interrupt 2 status 0x1108 32 read-only 0x0 0x80000000 SYSTEM_INT_IDX Lowest CM0+ activated system interrupt index for CPU interrupt 2. See description of CM0_INT0_STATUS. [9:0] read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. [31:31] read-only CM0_INT3_STATUS CM0+ interrupt 3 status 0x110C 32 read-only 0x0 0x80000000 SYSTEM_INT_IDX Lowest CM0+ activated system interrupt index for CPU interrupt 3. See description of CM0_INT0_STATUS. [9:0] read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. [31:31] read-only CM0_INT4_STATUS CM0+ interrupt 4 status 0x1110 32 read-only 0x0 0x80000000 SYSTEM_INT_IDX Lowest CM0+ activated system interrupt index for CPU interrupt 4. See description of CM0_INT0_STATUS. [9:0] read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. [31:31] read-only CM0_INT5_STATUS CM0+ interrupt 5 status 0x1114 32 read-only 0x0 0x80000000 SYSTEM_INT_IDX Lowest CM0+ activated system interrupt index for CPU interrupt 5. See description of CM0_INT0_STATUS. [9:0] read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. [31:31] read-only CM0_INT6_STATUS CM0+ interrupt 6 status 0x1118 32 read-only 0x0 0x80000000 SYSTEM_INT_IDX Lowest CM0+ activated system interrupt index for CPU interrupt 6. See description of CM0_INT0_STATUS. [9:0] read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. [31:31] read-only CM0_INT7_STATUS CM0+ interrupt 7 status 0x111C 32 read-only 0x0 0x80000000 SYSTEM_INT_IDX Lowest CM0+ activated system interrupt index for CPU interrupt 7. See description of CM0_INT0_STATUS. [9:0] read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. [31:31] read-only CM0_VECTOR_TABLE_BASE CM0+ vector table base 0x1120 32 read-write 0x0 0xFFFFFF00 ADDR24 Address of CM0+ vector table. This register is used for CM0+ warm boot purposes: the CM0+ warm boot code uses the register to initialize the CM0+ internal VTOR register. Note: the CM0+ vector table is at an address that is a 256 B multiple. [31:8] read-write 4 4 CM0_NMI_CTL[%s] CM0+ NMI control 0x1140 32 read-write 0x3FF 0x3FF SYSTEM_INT_IDX System interrupt select for CPU NMI. The reset value ('1023') ensures that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset. [9:0] read-write CM4_PWR_CTL CM4 power control 0x1200 32 read-write 0xFA050001 0xFFFF0003 PWR_MODE Power mode. [1:0] read-write OFF Switch CM4 off Power off, clock off, isolate, reset and no retain. 0 RESET Reset CM4 Clock off, no isolated, no retain and reset. Note: The CM4 CPU has a AIRCR.SYSRESETREQ register field that allows the CM4 to reset the complete device (RESET only resets the CM4), resulting in a warm boot. 1 RETAINED Put CM4 in Retained mode This can only become effective if CM4 is in SleepDeep mode. Check PWR_DONE flag to see if CM4 RETAINED state has been reached. Power off, clock off, isolate, no reset and retain. 2 ENABLED Switch CM4 on. Power on, clock on, no isolate, no reset and no retain. 3 VECTKEYSTAT Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. [31:16] read-only CM4_PWR_DELAY_CTL CM4 power control 0x1204 32 read-write 0x12C 0x3FF UP Number clock cycles delay needed after power domain power up [9:0] read-write RAM0_CTL0 RAM 0 control 0x1300 32 read-write 0x30001 0x70303 SLOW_WS Memory wait states for the slow clock domain ('clk_slow'). The number of wait states is expressed in 'clk_hf' clock domain cycles. [1:0] read-write FAST_WS Memory wait states for the fast clock domain ('clk_fast'). The number of wait states is expressed in 'clk_hf' clock domain cycles. [9:8] read-write ECC_EN Enable ECC checking: '0': Disabled. '1': Enabled. [16:16] read-write ECC_AUTO_CORRECT HW ECC autocorrect functionality: '0': Disabled. '1': Enabled. HW automatically writes back SRAM with corrected data when a recoverable ECC error is detected. [17:17] read-write ECC_INJ_EN Enable error injection for system SRAM 0. When '1', the parity (ECC_CTL.PARITY) is used when a full 32-bit write is done to the ECC_CTL.WORD_ADDR word address of system SRAM 0. [18:18] read-write RAM0_STATUS RAM 0 status 0x1304 32 read-only 0x1 0x1 WB_EMPTY Write buffer empty. This information is used when entering DeepSleep power mode: WB_EMPTY must be '1' before a transition to system DeepSleep power mode. '0': Write buffer NOT empty. '1': Write buffer empty. Note: the SRAM controller write buffer is only used when ECC checking is enabled. (RAMi_CTL.ECC_EN is '1'). [0:0] read-only 16 4 RAM0_PWR_MACRO_CTL[%s] RAM 0 power control 0x1340 32 read-write 0xFA050003 0xFFFF0003 PWR_MODE SRAM Power mode. [1:0] read-write OFF Turn OFF the SRAM. This will trun OFF both array and periphery power of the SRAM and SRAM memory contents are lost. 0 RSVD undefined 1 RETAINED Keep SRAM in Retained mode. This will turn OFF the SRAM periphery power, but array power is ON to retain memory contents. The SRAM contents will be retained in DeepSleep system power mode. 2 ENABLED Enable SRAM for regular operation. The SRAM contents will be retained in DeepSleep system power mode. 3 VECTKEYSTAT Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. [31:16] read-only RAM1_CTL0 RAM 1 control 0x1380 32 read-write 0x30001 0x70303 SLOW_WS See RAM0_CTL. [1:0] read-write FAST_WS See RAM0_CTL. [9:8] read-write ECC_EN See RAM0_CTL. [16:16] read-write ECC_AUTO_CORRECT See RAM0_CTL. [17:17] read-write ECC_INJ_EN See RAM0_CTL. [18:18] read-write RAM1_STATUS RAM 1 status 0x1384 32 read-only 0x1 0x1 WB_EMPTY See RAM0_STATUS. [0:0] read-only RAM1_PWR_CTL RAM 1 power control 0x1388 32 read-write 0xFA050003 0xFFFF0003 PWR_MODE Power mode. [1:0] read-write OFF See RAM0_PWR_MACRO_CTL. 0 RSVD undefined 1 RETAINED See RAM0_PWR_MACRO_CTL. 2 ENABLED See RAM0_PWR_MACRO_CTL. 3 VECTKEYSTAT See RAM0_PWR_MACRO_CTL. [31:16] read-only RAM2_CTL0 RAM 2 control 0x13A0 32 read-write 0x30001 0x70303 SLOW_WS See RAM0_CTL. [1:0] read-write FAST_WS See RAM0_CTL. [9:8] read-write ECC_EN See RAM0_CTL. [16:16] read-write ECC_AUTO_CORRECT See RAM0_CTL. [17:17] read-write ECC_INJ_EN See RAM0_CTL. [18:18] read-write RAM2_STATUS RAM 2 status 0x13A4 32 read-only 0x1 0x1 WB_EMPTY See RAM0_STATUS. [0:0] read-only RAM2_PWR_CTL RAM 2 power control 0x13A8 32 read-write 0xFA050003 0xFFFF0003 PWR_MODE Power mode. [1:0] read-write OFF See RAM0_PWR_MACRO_CTL. 0 RSVD undefined 1 RETAINED See RAM0_PWR_MACRO_CTL. 2 ENABLED See RAM0_PWR_MACRO_CTL. 3 VECTKEYSTAT See RAM0_PWR_MACRO_CTL. [31:16] read-only RAM_PWR_DELAY_CTL Power up delay used for all SRAM power domains 0x13C0 32 read-write 0x96 0x3FF UP Number clock cycles delay needed after power domain power up [9:0] read-write ROM_CTL ROM control 0x13C4 32 read-write 0x1 0x303 SLOW_WS Memory wait states for the slow clock domain ('clk_slow'). The number of wait states is expressed in 'clk_hf' clock domain cycles. Timing paths to and from the memory have a (fixed) minimum duration that always needs to be considered/met. The 'clk_hf' clock domain frequency determines this field's value such that the timing paths minimum duration is met. A table/formula will be provided for this field's values for different 'clk_hf' frequencies. [1:0] read-write FAST_WS Memory wait states for the fast clock domain ('clk_fast'). The number of wait states is expressed in 'clk_hf' clock domain cycles. [9:8] read-write ECC_CTL ECC control 0x13C8 32 read-write 0x0 0xFFFFFFFF WORD_ADDR Specifies the word address where an error will be injected. - On a write transfer to this SRAM address and when the corresponding RAM0/RAM1/RAM2_CTL0.ECC_INJ_EN bit is '1', the parity (PARITY) is injected. This field needs to be written with the offset address within the memory, divided by 4. For example, if the RAM1 start address is 0x08010000, and an error is to be injected to address 0x08010040, then this field needs to configured to 0x000010. [24:0] read-write PARITY ECC parity to use for ECC error injection at address WORD_ADDR. [31:25] read-write PRODUCT_ID Product identifier and version (same as CoreSight RomTables) 0x1400 32 read-only 0x0 0xFFF FAMILY_ID Family ID a.k.a. Partnumber a.k.a. Silicon ID [11:0] read-only MAJOR_REV Major Revision, starts with 1, increments with all layer tape-out (implemented with metal ECO-able tie-off) [19:16] read-only MINOR_REV Minor Revision, starts with 1, increments with metal layer only tape-out (implemented with metal ECO-able tie-off) [23:20] read-only DP_STATUS Debug port status 0x1410 32 read-only 0x4 0x7 SWJ_CONNECTED Specifies if the SWJ debug port is connected; i.e. debug host interface is active: '0': Not connected/not active. '1': Connected/active. [0:0] read-only SWJ_DEBUG_EN Specifies if SWJ debug is enabled, i.e. CDBGPWRUPACK is '1' and thus debug clocks are on: '0': Disabled. '1': Enabled. [1:1] read-only SWJ_JTAG_SEL Specifies if the JTAG or SWD interface is selected. This signal is valid when DP_CTL.PTM_SEL is '0' (SWJ mode selected) and SWJ_CONNECTED is '1' (SWJ is connected). '0': SWD selected. '1': JTAG selected. [2:2] read-only AP_CTL Access port control 0x1414 32 read-write 0x0 0x70007 CM0_ENABLE Enables the CM0 AP interface: '0': Disabled. '1': Enabled. [0:0] read-write CM4_ENABLE Enables the CM4 AP interface: '0': Disabled. '1': Enabled. [1:1] read-write SYS_ENABLE Enables the system AP interface: '0': Disabled. '1': Enabled. [2:2] read-write CM0_DISABLE Disables the CM0 AP interface: '0': Enabled. '1': Disabled. Typically, this field is set by the Cypress boot code with information from eFUSE. The access port is only enabled when CM0_DISABLE is '0' and CM0_ENABLE is '1'. [16:16] read-write CM4_DISABLE Disables the CM4 AP interface: '0': Enabled. '1': Disabled. Typically, this field is set by the Cypress boot code with information from eFUSE. The access port is only enabled when CM4_DISABLE is '0' and CM4_ENABLE is '1'. [17:17] read-write SYS_DISABLE Disables the system AP interface: '0': Enabled. '1': Disabled. Typically, this field is set by the Cypress boot code with information from eFUSE. The access port is only enabled when SYS_DISABLE is '0' and SYS_ENABLE is '1'. [18:18] read-write BUFF_CTL Buffer control 0x1500 32 read-write 0x1 0x1 WRITE_BUFF Specifies if write transfer can be buffered in the bus infrastructure bridges: '0': Write transfers are not buffered, independent of the transfer's bufferable attribute. '1': Write transfers can be buffered, if the transfer's bufferable attribute indicates that the transfer is a bufferable/posted write. [0:0] read-write SYSTICK_CTL SysTick timer control 0x1600 32 read-write 0x40000147 0xC3FFFFFF TENMS Specifies the number of clock source cycles (minus 1) that make up 10 ms. E.g., for a 32,768 Hz reference clock, TENMS is 328 - 1 = 327. [23:0] read-write CLOCK_SOURCE Specifies an external clock source: '0': The low frequency clock 'clk_lf' is selected. The precision of this clock depends on whether the low frequency clock source is a SRSS internal RC oscillator (imprecise) or a device external crystal oscillator (precise). '1': The internal main oscillator (IMO) clock 'clk_imo' is selected. The MXS40 platform uses a fixed frequency IMO clock. o '2': The external crystal oscillator (ECO) clock 'clk_eco' is selected. '3': The SRSS 'clk_timer' is selected ('clk_timer' is a divided/gated version of 'clk_hf' or 'clk_imo'). Note: If NOREF is '1', the CLOCK_SOURCE value is NOT used. Note: It is SW's responsibility to provide the correct NOREF, SKEW and TENMS field values for the selected clock source. [25:24] read-write SKEW Specifies the precision of the clock source and if the TENMS field represents exactly 10 ms (clock source frequency is a multiple of 100 Hz). This affects the suitability of the SysTick timer as a SW real-time clock: '0': Precise. '1': Imprecise. [30:30] read-write NOREF Specifies if an external clock source is provided: '0': An external clock source is provided. '1': An external clock source is NOT provided and only the CPU internal clock can be used as SysTick timer clock source. [31:31] read-write MBIST_STAT Memory BIST status 0x1704 32 read-only 0x0 0x3 SFP_READY Flag indicating the BIST run is done. Note that after starting a BIST run this flag must be set before a new run can be started. For the first BIST run this will be 0. [0:0] read-only SFP_FAIL Report status of the BIST run, only valid if SFP_READY=1 [1:1] read-only CAL_SUP_SET Calibration support set and read 0x1800 32 read-write 0x0 0xFFFFFFFF DATA Read without side effect, write 1 to set [31:0] read-write CAL_SUP_CLR Calibration support clear and reset 0x1804 32 read-write 0x0 0xFFFFFFFF DATA Read side effect: when read all bits are cleared, write 1 to clear a specific bit Note: no exception for the debug host, it also causes the read side effect [31:0] read-write CM0_PC_CTL CM0+ protection context control 0x2000 32 read-write 0x0 0xF VALID Valid fields for the protection context handler CM0_PCi_HANDLER registers: Bit 0: Valid field for CM0_PC0_HANDLER. Bit 1: Valid field for CM0_PC1_HANDLER. Bit 2: Valid field for CM0_PC2_HANDLER. Bit 3: Valid field for CM0_PC3_HANDLER. [3:0] read-write CM0_PC0_HANDLER CM0+ protection context 0 handler 0x2040 32 read-write 0x0 0xFFFFFFFF ADDR Address of the protection context 0 handler. This field is used to detect entry to Cypress 'trusted' code through an exception/interrupt. [31:0] read-write CM0_PC1_HANDLER CM0+ protection context 1 handler 0x2044 32 read-write 0x0 0xFFFFFFFF ADDR Address of the protection context 1 handler. [31:0] read-write CM0_PC2_HANDLER CM0+ protection context 2 handler 0x2048 32 read-write 0x0 0xFFFFFFFF ADDR Address of the protection context 2 handler. [31:0] read-write CM0_PC3_HANDLER CM0+ protection context 3 handler 0x204C 32 read-write 0x0 0xFFFFFFFF ADDR Address of the protection context 3 handler. [31:0] read-write PROTECTION Protection status 0x20C4 32 read-write 0x0 0x7 STATE Protection state: '0': UNKNOWN. '1': VIRGIN. '2': NORMAL. '3': SECURE. '4': DEAD. The following state transitions are allowed (and enforced by HW): - UNKNOWN => VIRGIN/NORMAL/SECURE/DEAD - NORMAL => DEAD - SECURE => DEAD An attempt to make a NOT allowed state transition will NOT affect this register field. [2:0] read-write TRIM_ROM_CTL ROM trim control 0x2100 32 read-write 0x0 0xFFFFFFFF TRIM N/A [31:0] read-write TRIM_RAM_CTL RAM trim control 0x2104 32 read-write 0x0 0xFFFFFFFF TRIM N/A [31:0] read-write 1023 4 CM0_SYSTEM_INT_CTL[%s] CM0+ system interrupt control 0x8000 32 read-write 0x0 0x80000000 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. [2:0] read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. [31:31] read-write 1023 4 CM4_SYSTEM_INT_CTL[%s] CM4 system interrupt control 0xA000 32 read-write 0x0 0x80000000 CPU_INT_IDX N/A [2:0] read-write CPU_INT_VALID N/A [31:31] read-write FAULT Fault structures 0x40210000 0 65536 registers 2 256 STRUCT[%s] Fault structure 0x00000000 CTL Fault control 0x0 32 read-write 0x0 0x7 TR_EN Trigger output enable: '0': Disabled. The trigger output 'tr_fault' is '0'. '1': Enabled. The trigger output 'tr_fault' reflects STATUS.VALID. The trigger can be used to initiate a Datawire transfer of the FAULT data (FAULT_DATA0 through FAULT_DATA3). [0:0] read-write OUT_EN IO output signal enable: '0': Disabled. The IO output signal 'fault_out' is '0'. The IO output enable signal 'fault_out_en' is '0'. '1': Enabled. The IO output signal 'fault_out' reflects STATUS.VALID. The IO output enable signal 'fault_out_en' is '1'. [1:1] read-write RESET_REQ_EN Reset request enable: '0': Disabled. '1': Enabled. The output reset request signal 'fault_reset_req' reflects STATUS.VALID. This reset causes a warm/soft/core reset. This warm/soft/core reset does not affect the fault logic STATUS, DATA0, ..., DATA3 registers (allowing for post soft reset failure analysis). The 'fault_reset_req' signals of the individual fault report structures are combined (logically OR'd) into a single SRSS 'fault_reset_req' signal. [2:2] read-write STATUS Fault status 0xC 32 read-write 0x0 0x80000000 IDX The fault source index for which fault information is captured in DATA0 through DATA3. The fault information is fault source specific and described below. Note: this register field (and associated fault source data in DATA0 through DATA3) should only be considered valid, when VALID is '1'. [6:0] read-only VALID Valid indication: '0': Invalid. '1': Valid. HW sets this field to '1' when new fault source data is captured. New fault source data is ONLY captured when VALID is '0'. SW can clear this field to '0' when the fault is handled (by SW). [31:31] read-write 4 4 DATA[%s] Fault data 0x10 32 read-only 0x0 0x0 DATA Captured fault source data. Note: the fault source index STATUS.IDX specifies the format of the DATA registers. [31:0] read-only PENDING0 Fault pending 0 0x40 32 read-only 0x0 0x0 SOURCE This field specifies the following sources: Bit 0: CM0 MPU. Bit 1: CRYPTO MPU. Bit 2: DW 0 MPU. Bit 3: DW 1 MPU. ... Bit 14: CM4 code bus MPU. Bit 15: DAP MPU. Bit 16: CM4 s+G92ystem bus MPU. Bit 28: Peripheral master interface 0 PPU. Bit 29: Peripheral master interface 1 PPU. Bit 30: Peripheral master interface 2 PPU. Bit 31: Peripheral master interface 3 PPU. [31:0] read-only PENDING1 Fault pending 1 0x44 32 read-only 0x0 0x0 SOURCE This field specifies the following sources: Bit 0: Peripheral group 0 PPU. Bit 1: Peripheral group 1 PPU. Bit 2: Peripheral group 2 PPU. Bit 3: Peripheral group 3 PPU. Bit 4: Peripheral group 4 PPU. Bit 5: Peripheral group 5 PPU. Bit 6: Peripheral group 6 PPU. Bit 7: Peripheral group 7 PPU. ... Bit 15: Peripheral group 15 PPU. Bit 18: Flash controller, main interface, bus error. [31:0] read-only PENDING2 Fault pending 2 0x48 32 read-only 0x0 0x0 SOURCE This field specifies the following sources: Bit 0 - 31: TBD. [31:0] read-only MASK0 Fault mask 0 0x50 32 read-write 0x0 0xFFFFFFFF SOURCE Fault source enables: Bits 31-0: Fault sources 31 to 0. [31:0] read-write MASK1 Fault mask 1 0x54 32 read-write 0x0 0xFFFFFFFF SOURCE Fault source enables: Bits 31-0: Fault sources 63 to 32. [31:0] read-write MASK2 Fault mask 2 0x58 32 read-write 0x0 0xFFFFFFFF SOURCE Fault source enables: Bits 31-0: Fault sources 95 to 64. [31:0] read-write INTR Interrupt 0xC0 32 read-write 0x0 0x1 FAULT This interrupt cause field is activated (HW sets the field to '1') when an enabled (MASK0/MASK1/MASK2) pending fault source is captured: - STATUS.VALID is set to '1'. - STATUS.IDX specifies the fault source index. - DATA0 through DATA3 captures the fault source data. SW writes a '1' to these field to clear the interrupt cause to '0'. [0:0] read-write INTR_SET Interrupt set 0xC4 32 read-write 0x0 0x1 FAULT SW writes a '1' to this field to set the corresponding field in the INTR register. [0:0] read-write INTR_MASK Interrupt mask 0xC8 32 read-write 0x0 0x1 FAULT Mask bit for corresponding field in the INTR register. [0:0] read-write INTR_MASKED Interrupt masked 0xCC 32 read-only 0x0 0x1 FAULT Logical and of corresponding INTR and INTR_MASK fields. [0:0] read-only IPC IPC 0x40220000 0 65536 registers 16 32 STRUCT[%s] IPC structure 0x00000000 ACQUIRE IPC acquire 0x0 32 read-only 0x0 0x80000000 P User/privileged access control: '0': user mode. '1': privileged mode. This field is set with the user/privileged access control of the access that successfully acquired the lock. [0:0] read-only NS Secure/non-secure access control: '0': secure. '1': non-secure. This field is set with the secure/non-secure access control of the access that successfully acquired the lock. [1:1] read-only PC This field specifies the protection context that successfully acquired the lock. [7:4] read-only MS This field specifies the bus master identifier that successfully acquired the lock. [11:8] read-only SUCCESS Specifies if the lock is successfully acquired or not (reading the ACQUIRE register can have affect on SUCCESS and LOCK_STATUS.ACQUIRED): '0': Not successfully acquired; i.e. the lock was already acquired by another read transaction and not released. The P, NS, PC and MS fields reflect the access attributes of the transaction that previously successfully acuired the lock; the fields are NOT affected by the current access. '1': Successfully acquired. The P, NS, PC and MS fields reflect the access attributes of the current access. Note that this field is NOT SW writable. A lock is released by writing to the associated RELEASE register (irrespective of the write value). [31:31] read-only RELEASE IPC release 0x4 32 write-only 0x0 0xFFFF INTR_RELEASE Writing this field releases a lock and allows for the generation of release events to the IPC interrupt structures, but only when the lock is acquired (LOCK_STATUS.ACQUIRED is '1'). The IPC release cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_RELEASE[] is set to '1'. SW writes a '1' to the bit fields to generate a release event. Due to the transient nature of this event, SW always reads a '0' from this field. [15:0] write-only NOTIFY IPC notification 0x8 32 write-only 0x0 0xFFFF INTR_NOTIFY This field allows for the generation of notification events to the IPC interrupt structures. The IPC notification cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_NOTIFY[] is set to '1'. SW writes a '1' to the bit fields to generate a notify event. Due to the transient nature of this event, SW always reads a '0' from this field. [15:0] write-only DATA0 IPC data 0 0xC 32 read-write 0x0 0x0 DATA This field holds a 32-bit data element that is associated with the IPC structure. [31:0] read-write DATA1 IPC data 1 0x10 32 read-write 0x0 0x0 DATA This field holds a 32-bit data element that is associated with the IPC structure. [31:0] read-write LOCK_STATUS IPC lock status 0x1C 32 read-only 0x0 0x80000000 P This field specifies the user/privileged access control: '0': user mode. '1': privileged mode. [0:0] read-only NS This field specifies the secure/non-secure access control: '0': secure. '1': non-secure. [1:1] read-only PC This field specifies the protection context that successfully acquired the lock. [7:4] read-only MS This field specifies the bus master identifier that successfully acquired the lock. [11:8] read-only ACQUIRED Specifies if the lock is acquired. This field is set to '1', if a ACQUIRE read transfer successfully acquires the lock (the ACQUIRE read transfer returns ACQUIRE.SUCCESS as '1'). If zero, P, NS, PC, and MS are not valid. [31:31] read-only 16 32 INTR_STRUCT[%s] IPC interrupt structure 0x00001000 INTR Interrupt 0x0 32 read-write 0x0 0xFFFFFFFF RELEASE These interrupt cause fields are activated (HW sets the field to '1') when a IPC release event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause. [15:0] read-write NOTIFY These interrupt cause fields are activated (HW sets the field to '1') when a IPC notification event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause. [31:16] read-write INTR_SET Interrupt set 0x4 32 read-write 0x0 0xFFFFFFFF RELEASE SW writes a '1' to this field to set the corresponding field in the INTR register. [15:0] read-write NOTIFY SW writes a '1' to this field to set the corresponding field in the INTR register. [31:16] read-write INTR_MASK Interrupt mask 0x8 32 read-write 0x0 0xFFFFFFFF RELEASE Mask bit for corresponding field in the INTR register. [15:0] read-write NOTIFY Mask bit for corresponding field in the INTR register. [31:16] read-write INTR_MASKED Interrupt masked 0xC 32 read-only 0x0 0xFFFFFFFF RELEASE Logical and of corresponding request and mask bits. [15:0] read-only NOTIFY Logical and of corresponding INTR and INTR_MASK fields. [31:16] read-only PROT Protection 0x40230000 0 65536 registers SMPU SMPU 0x00000000 MS0_CTL Master 0 protection context control 0x0 32 read-write 0x303 0xFFFF0303 P Privileged setting ('0': user mode; '1': privileged mode). Notes: This field is ONLY used for masters that do NOT provide their own user/privileged access control attribute. The default/reset field value provides privileged mode access capabilities. [0:0] read-write NS Security setting ('0': secure mode; '1': non-secure mode). Notes: This field is ONLY used for masters that do NOT provide their own secure/non-secure access control attribute. Note that the default/reset field value provides non-secure mode access capabilities to all masters. [1:1] read-write PRIO Device wide bus arbitration priority setting ('0': highest priority, '3': lowest priority). Notes: The AHB-Lite interconnect performs arbitration on the individual beats/transfers of a burst (this optimizes latency over locality/bandwidth). The AXI-Lite interconnects performs a single arbitration for the complete burst (this optimizes locality/bandwidth over latency). Masters with the same priority setting form a 'priority group'. Within a 'priority group', round robin arbitration is performed. [9:8] read-write PC_MASK_0 Protection context mask for protection context '0'. This field is a constant '0': - PC_MASK_0 is '0': MPU MS_CTL.PC[3:0] can NOT be set to '0' and PC[3:0] is not changed. If the protection context of the write transfer is '0', protection is not applied and PC[3:0] can be changed. [16:16] read-only PC_MASK_15_TO_1 Protection context mask for protection contexts '15' down to '1'. Bit PC_MASK_15_TO_1[i] indicates if the MPU MS_CTL.PC[3:0] protection context field can be set to the value 'i+1': - PC_MASK_15_TO_1[i] is '0': MPU MS_CTL.PC[3:0] can NOT be set to 'i+1'; and PC[3:0] is not changed. If the protection context of the write transfer is '0', protection is not applied and PC[3:0] can be changed. - PC_MASK_15_TO_1[i] is '1': MPU MS_CTL.PC[3:0] can be set to 'i+1'. Note: When CPUSS_CM0_PC_CTL.VALID[i] is '1' (the associated protection context handler is valid), write transfers to PC_MASK_15_TO_1[i-1] always write '0', regardless of data written. This ensures that when valid protection context handlers are used to enter protection contexts 1, 2 or 3 through (HW modifies MPU MS_CTL.PC[3:0] on entry of the handler), it is NOT possible for SW to enter those protection contexts (SW modifies MPU MS_CTL.PC[3:0]). [31:17] read-write MS1_CTL Master 1 protection context control 0x4 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS2_CTL Master 2 protection context control 0x8 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS3_CTL Master 3 protection context control 0xC 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS4_CTL Master 4 protection context control 0x10 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS5_CTL Master 5 protection context control 0x14 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS6_CTL Master 6 protection context control 0x18 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS7_CTL Master 7 protection context control 0x1C 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS8_CTL Master 8 protection context control 0x20 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS9_CTL Master 9 protection context control 0x24 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS10_CTL Master 10 protection context control 0x28 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS11_CTL Master 11 protection context control 0x2C 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS12_CTL Master 12 protection context control 0x30 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS13_CTL Master 13 protection context control 0x34 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS14_CTL Master 14 protection context control 0x38 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS15_CTL Master 15 protection context control 0x3C 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write 16 64 SMPU_STRUCT[%s] SMPU structure 0x00002000 ADDR0 SMPU region address 0 (slave structure) 0x0 32 read-write 0x0 0x0 SUBREGION_DISABLE This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. E.g., a 64 KByte address region (ATT0.REGION_SIZE is '15') has eight 8 KByte subregions. The access control as defined by ATT0 applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B. [7:0] read-write ADDR24 This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by ATT0.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result, some of the lesser significant address bits of ADDR24 may be ignored in determining whether a bus transfer address is within an address region. E.g., a 64 KByte address region (REGION_SIZE is '15') is 64 KByte aligned, and ADDR24[7:0] are ignored. [31:8] read-write ATT0 SMPU region attributes 0 (slave structure) 0x4 32 read-write 0x100 0x80000100 UR User read enable: '0': Disabled (user, read accesses are NOT allowed). '1': Enabled (user, read accesses are allowed). [0:0] read-write UW User write enable: '0': Disabled (user, write accesses are NOT allowed). '1': Enabled (user, write accesses are allowed). [1:1] read-write UX User execute enable: '0': Disabled (user, execute accesses are NOT allowed). '1': Enabled (user, execute accesses are allowed). [2:2] read-write PR Privileged read enable: '0': Disabled (privileged, read accesses are NOT allowed). '1': Enabled (privileged, read accesses are allowed). [3:3] read-write PW Privileged write enable: '0': Disabled (privileged, write accesses are NOT allowed). '1': Enabled (privileged, write accesses are allowed). [4:4] read-write PX Privileged execute enable: '0': Disabled (privileged, execute accesses are NOT allowed). '1': Enabled (privileged, execute accesses are allowed). [5:5] read-write NS Non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed). [6:6] read-write PC_MASK_0 This field specifies protection context identifier based access control for protection context '0'. [8:8] read-only PC_MASK_15_TO_1 This field specifies protection context identifier based access control. Bit i: protection context i+1 enable. If '0', protection context i+1 access is disabled; i.e. not allowed. If '1', protection context i+1 access is enabled; i.e. allowed. [23:9] read-write REGION_SIZE This field specifies the region size: '0'-'6': Undefined. '7': 256 B region '8': 512 B region '9': 1 KB region '10': 2 KB region '11': 4 KB region '12': 8 KB region '13': 16 KB region '14': 32 KB region '15': 64 KB region '16': 128 KB region '17': 256 KB region '18': 512 KB region '19': 1 MB region '20': 2 MB region '21': 4 MB region '22': 8 MB region '23': 16 MB region '24': 32 MB region '25': 64 MB region '26': 128 MB region '27': 256 MB region '28': 512 MB region '39': 1 GB region '30': 2 GB region '31': 4 GB region [28:24] read-write PC_MATCH This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process: '0': PC field participates in 'access evaluation'. '1': PC field participates in 'matching'. 'Matching' process. For each protection structure, the process identifies if a transfer address is contained within the address range. This identifies the 'matching' regions. 'Access evaluation' process. For each protection structure, the process evaluates the bus transfer access attributes against the access control attributes. Note that it is possible to define different access control for multiple protection contexts by using multiple protection structures with the same address region and PC_MATCH set to '1'. [30:30] read-write ENABLED Region enable: '0': Disabled. A disabled region will never result in a match on the bus transfer address. '1': Enabled. Note: a disabled address region performs logic gating to reduce dynamic power consumption. [31:31] read-write ADDR1 SMPU region address 1 (master structure) 0x20 32 read-only 0x0 0xFFFFFFFF SUBREGION_DISABLE This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. Note: this field is read-only. [7:0] read-only ADDR24 This field specifies the most significant bits of the 32-bit address of an address region. 'ADDR_DEF1': base address of structure. Note: this field is read-only. [31:8] read-only ATT1 SMPU region attributes 1 (master structure) 0x24 32 read-write 0x7000109 0x9F00012D UR User read enable: '0': Disabled (user, read accesses are NOT allowed). '1': Enabled (user, read accesses are allowed). Note that this register is constant '1'; i.e. user read accesses are ALWAYS allowed. [0:0] read-only UW User write enable: '0': Disabled (user, write accesses are NOT allowed). '1': Enabled (user, write accesses are allowed). [1:1] read-write UX User execute enable: '0': Disabled (user, execute accesses are NOT allowed). '1': Enabled (user, execute accesses are allowed). Note that this register is constant '0'; i.e. user execute accesses are NEVER allowed. [2:2] read-only PR Privileged read enable: '0': Disabled (privileged, read accesses are NOT allowed). '1': Enabled (privileged, read accesses are allowed). Note that this register is constant '1'; i.e. privileged read accesses are ALWAYS allowed. [3:3] read-only PW Privileged write enable: '0': Disabled (privileged, write accesses are NOT allowed). '1': Enabled (privileged, write accesses are allowed). [4:4] read-write PX Privileged execute enable: '0': Disabled (privileged, execute accesses are NOT allowed). '1': Enabled (privileged, execute accesses are allowed). Note that this register is constant '0'; i.e. privileged execute accesses are NEVER allowed. [5:5] read-only NS Non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed). [6:6] read-write PC_MASK_0 This field specifies protection context identifier based access control for protection context '0'. [8:8] read-only PC_MASK_15_TO_1 This field specifies protection context identifier based access control. Bit i: protection context i+1 enable. If '0', protection context i+1 access is disabled; i.e. not allowed. If '1', protection context i+1 access is enabled; i.e. allowed. [23:9] read-write REGION_SIZE This field specifies the region size: '7': 256 B region (8 32 B subregions) Note: this field is read-only. [28:24] read-only PC_MATCH This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process: '0': PC field participates in 'access evaluation'. '1': PC field participates in 'matching'. 'Matching' process. For each protection structure, the process identifies if a transfer address is contained within the address range. This identifies the 'matching' regions. 'Access evaluation' process. For each protection structure, the process evaluates the bus transfer access attributes against the access control attributes. Note that it is possible to define different access control for multiple protection contexts by using multiple protection structures with the same address region and PC_MATCH set to '1'. [30:30] read-write ENABLED Region enable: '0': Disabled. A disabled region will never result in a match on the bus transfer address. '1': Enabled. [31:31] read-write 16 1024 MPU[%s] MPU 0x00004000 MS_CTL Master control 0x0 32 read-write 0x0 0xF000F PC Active protection context (PC). Modifications to this field are constrained by the associated SMPU MS_CTL.PC_MASK_0 and MS_CTL.PC_MASK_15_TO_1[] fields. In addition, a write transfer with protection context '0' can change this field (protection context 0 has unrestricted access). The CM0+ MPU MS_CTL register is special: the PC field is modifiable by BOTH HW and SW (for all other masters, the MPU MS_CTL.PC field is modifiable by SW ONLY. For CM0+ PC field HW modifications, the following holds: * On entry of a CM0_PC0/1/2/3_HANDLER exception/interrupt handler: IF (the new PC is the same as MS_CTL.PC) PC is not affected; PC_SAVED is not affected. ELSE IF (CM0_PC_CTL.VALID[MS_CTL.PC]) An AHB-Lite bus error is generated for the exception handler fetch; PC is not affected; PC_SAVED is not affected. ELSE PC = 'new PC'; PC_SAVED = PC (push operation). * On entry of any other exception/interrupt handler: PC = PC_SAVED; PC_SAVED is not affected (pop operation). Note that the CM0_PC0/1/2/3_HANDLER and CM0_PC_CTL registers are part of repecitve CPUSS MMIO registers. Note: this field is NOT used by the DW controllers, DMA controller, AXI DMA controller, CRYPTO component and VIDEOSS. [3:0] read-write PC_SAVED Saved protection context. Modifications to this field are constrained by the associated SMPU MS_CTL.PC_MASK_0 and MS_CTL.PC_MASK_15_TO_1[] fields. Note: this field is ONLY used by the CM0+. [19:16] read-write 127 4 MS_CTL_READ_MIR[%s] Master control read mirror 0x4 32 read-only 0x0 0xF000F PC Read-only mirror of MS_CTL.PC [3:0] read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED [19:16] read-only 8 32 MPU_STRUCT[%s] MPU structure 0x00000200 ADDR MPU region address 0x0 32 read-write 0x0 0x0 SUBREGION_DISABLE This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. E.g., a 64 KByte address region (REGION_SIZE is '15') has eight 8 KByte subregions. The access control as defined by MPU_REGION_ATT applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B. [7:0] read-write ADDR24 This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by ATT.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result, some of the lesser significant address bits of ADDR24 may be ignored in determining whether a bus transfer address is within an address region. E.g., a 64 KByte address region (REGION_SIZE is '15') is 64 KByte aligned, and ADDR24[7:0] are ignored. [31:8] read-write ATT MPU region attrributes 0x4 32 read-write 0x0 0x80000000 UR User read enable: '0': Disabled (user, read accesses are NOT allowed). '1': Enabled (user, read accesses are allowed). [0:0] read-write UW User write enable: '0': Disabled (user, write accesses are NOT allowed). '1': Enabled (user, write accesses are allowed). [1:1] read-write UX User execute enable: '0': Disabled (user, execute accesses are NOT allowed). '1': Enabled (user, execute accesses are allowed). [2:2] read-write PR Privileged read enable: '0': Disabled (privileged, read accesses are NOT allowed). '1': Enabled (privileged, read accesses are allowed). [3:3] read-write PW Privileged write enable: '0': Disabled (privileged, write accesses are NOT allowed). '1': Enabled (privileged, write accesses are allowed). [4:4] read-write PX Privileged execute enable: '0': Disabled (privileged, execute accesses are NOT allowed). '1': Enabled (privileged, execute accesses are allowed). [5:5] read-write NS Non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed). [6:6] read-write REGION_SIZE This field specifies the region size: '0'-'6': Undefined. '7': 256 B region '8': 512 B region '9': 1 KB region '10': 2 KB region '11': 4 KB region '12': 8 KB region '13': 16 KB region '14': 32 KB region '15': 64 KB region '16': 128 KB region '17': 256 KB region '18': 512 KB region '19': 1 MB region '20': 2 MB region '21': 4 MB region '22': 8 MB region '23': 16 MB region '24': 32 MB region '25': 64 MB region '26': 128 MB region '27': 256 MB region '28': 512 MB region '39': 1 GB region '30': 2 GB region '31': 4 GB region [28:24] read-write ENABLED Region enable: '0': Disabled. A disabled region will never result in a match on the bus transfer address. '1': Enabled. Note: a disabled address region performs logic gating to reduce dynamic power consumption. [31:31] read-write FLASHC Flash controller 0x40240000 0 65536 registers FLASH_CTL Control 0x0 32 read-write 0x110000 0x77330F MAIN_WS FLASH macro main interface wait states: '0': 0 wait states. ... '15': 15 wait states [3:0] read-write MAIN_MAP Specifies mapping of FLASH macro main array. 0: Mapping A. 1: Mapping B. This field is only used when MAIN_BANK_MODE is '1' (dual bank mode). [8:8] read-write WORK_MAP Specifies mapping of FLASH macro work array. 0: Mapping A. 1: Mapping B. This field is only used when WORK_BANK_MODE is '1' (dual bank mode). [9:9] read-write MAIN_BANK_MODE Specifies bank mode of FLASH macro main array. 0: Single bank mode. 1: Dual bank mode. [12:12] read-write WORK_BANK_MODE Specifies bank mode of FLASH macro work array. 0: Single bank mode. 1: Dual bank mode. [13:13] read-write MAIN_ECC_EN Enable ECC checking for FLASH main interface: 0: Disabled. ECC checking/reporting on FLASH main interface is disabled. No correctable or non-correctable faults are reported. 1: Enabled. [16:16] read-write MAIN_ECC_INJ_EN Enable error injection for FLASH main interface. When'1', the parity (ECC_CTL.PARITY[7:0]) is used for a load from the ECC_CTL.WORD_ADDR[23:0] word address. [17:17] read-write MAIN_ERR_SILENT Specifies bus transfer behavior for a non-recoverable error on the FLASH macro main interface (either a non-correctable ECC error, a FLASH macro main interface internal error, a FLASH macro main interface memory hole access): 0: Bus transfer has a bus error. 1: Bus transfer does NOT have a bus error; i.e. the error is 'silent' In either case, the erroneous FLASH macro data is returned by the bus master interface. The erroneous data is NOT placed in a bus master interface's cache and/or buffer. This field is ONLY used by CPU (and debug i.e. SYS_AP/CM0_AP/CM4_AP) bus transfers. Non-CPU bus transfers always have a bus transfer with a bus error, in case of a non-recoverable error. Note: All CPU bus masters have dedicated status registers (CM0_STATUS and CM4_STATUS) to register the occurrence of FLASH macro main interface internal errors (non-correctable ECC errors and memory hole errors are NOT registered). Note: fault reporting can be used to identify the error that occurred: - FLASH macro main interface internal error. - FLASH macro main interface non-recoverable ECC error. - FLASH macro main interface recoverable ECC error. - FLASH macro main interface memory hole error. [18:18] read-write WORK_ECC_EN Enable ECC checking for FLASH work interface: 0: Disabled. ECC checking/reporting on FLASH work interface is disabled. No correctable or non-correctable faults are reported. 1: Enabled. [20:20] read-write WORK_ECC_INJ_EN Enable error injection for FLASH work interface. When'1', the parity (ECC_CTL.PARITY[6:0]) is used for a load from the ECC_CTL.WORD_ADDR[23:0] word address. [21:21] read-write WORK_ERR_SILENT Specifies bus transfer behavior for a non-recoverable error on the FLASH macro work interface (either a non-correctable ECC error, a FLASH macro work interface internal error, a FLASH macro work interface memory hole access): 0: Bus transfer has a bus error. 1: Bus transfer does NOT have a bus error; i.e. the error is 'silent' In either case, the erroneous FLASH macro data is returned by the bus master interface. The erroneous data is NOT placed in a bus master interface's cache and/or buffer. This field is ONLY used by CPU (and debug i.e. SYS_AP/CM0_AP/CM4_AP) bus transfers. Non-CPU bus transfers always have a bus transfer with a bus error, in case of a non-recoverable error. Note: All CPU bus masters have dedicated status registers (CM0_STATUS and CM4_STATUS) to register the occurrence of FLASH macro work interface internal errors (non-correctable ECC errors and memory hole errors are NOT registered). Note: fault reporting can be used to identify the error that occurred: - FLASH macro work interface internal error. - FLASH macro work interface non-recoverable ECC error. - FLASH macro work interface recoverable ECC error. - FLASH macro work interface memory hole error. [22:22] read-write FLASH_PWR_CTL Flash power control 0x4 32 read-write 0x3 0x3 ENABLE Controls 'enable' pin of the Flash memory. [0:0] read-write ENABLE_HV Controls 'enable_hv' pin of the Flash memory. [1:1] read-write FLASH_CMD Command 0x8 32 read-write 0x0 0x3 INV Invalidation of ALL caches (for CM0+ and CM4) and ALL buffers. SW writes a '1' to clear the caches. HW sets this field to '0' when the operation is completed. The operation takes a maximum of three clock cycles on the slowest of the clk_slow and clk_fast clocks. The caches' LRU structures are also reset to their default state. [0:0] read-write BUFF_INV Invalidation of ALL buffers (does not invalidate the caches). SW writes a '1' to clear the buffers. HW sets this field to '0' when the operation is completed. The operation takes a maximum of three clock cycles on the slowest of the clk_slow and clk_fast clocks. Note: the caches only capture FLASH macro main array data. Therefore, invalidating just the buffers (BUFF_INV) does not invalidate captures main array data in the caches. [1:1] read-write ECC_CTL ECC control 0x2A0 32 read-write 0x0 0xFFFFFFFF WORD_ADDR Specifies the word address where an error will be injected. - For cache SRAM ECC, the word address WORD_ADDR[23:0] is device address A[25:2]. On a FLASH macro refill to this word address and when the corresponding CM0/4_CA_CTL.RAM_ECC_INJ_EN bit is '1', the parity (PARITY[6:0]) is injected and stored in the cache. - For FLASH main interface ECC, the word address WORD_ADDR[23:0] is device address A[26:3]. On a FLASH main interface read and when FLASH_CTL.MAIN_ECC_INJ_EN bit is '1', the parity (PARITY[7:0]) replaces the FLASH macro parity (FLASH main interface read path is manipulated). - For FLASH work interface ECC, the word address WORD_ADDR[23:0] is device address A[24:2]. On a FLASH work interface read and when FLASH_CTL.WORK_ECC_INJ_EN bit is '1', the parity (PARITY[6:0]) replaces the FLASH macro parity (FLASH work interface read path is manipulated). [23:0] read-write PARITY ECC parity to use for ECC error injection at address WORD_ADDR. - For cache SRAM ECC, the 7-bit parity PARITY[6:0] is for a 32-bit word. - For FLASH main interface ECC, the 8-bit parity PARITY[7:0] is for a 64-bit word. - For FLASH work interface ECC, the 7-bit parity PARITY[6:0] is for a 32-bit word. [31:24] read-write FM_SRAM_ECC_CTL0 eCT Flash SRAM ECC control 0 0x2B0 32 read-write 0x0 0xFFFFFFFF ECC_INJ_DATA 32-bit data for ECC error injection test of eCT Flash SRAM ECC logic. [31:0] read-write FM_SRAM_ECC_CTL1 eCT Flash SRAM ECC control 1 0x2B4 32 read-write 0x0 0x7F ECC_INJ_PARITY 7-bit parity for ECC error injection test of eCT Flash SRAM ECC logic. [6:0] read-write FM_SRAM_ECC_CTL2 eCT Flash SRAM ECC control 2 0x2B8 32 read-only 0x0 0xFFFFFFFF CORRECTED_DATA 32-bit corrected data output of the ECC syndrome logic. [31:0] read-only FM_SRAM_ECC_CTL3 eCT Flash SRAM ECC control 3 0x2BC 32 read-write 0x1 0x111 ECC_ENABLE ECC generation/check enable for eCT Flash SRAM memory. [0:0] read-write ECC_INJ_EN eCT Flash SRAM ECC error injection test enable. Follow the steps below for ECC logic test: 1. Write corrupted or uncorrupted 39-bit data to FM_SRAM_ECC_CTL0/1 registers. 2. Set the ECC_INJ_EN bit to '1'. 3. Confirm that the bit ECC_TEST_FAIL is '0'. If this is not the case, start over at item 1 because the eCT Flash was not idle. 4. Check the corrected data in FM_SRAM_ECC_CTL2. 5. Confirm that fault was reported to fault structure, and check syndrome (only applicable if corrupted data was written in step 1). 6. If not finished, start over at 1 with different data. [4:4] read-write ECC_TEST_FAIL Status of ECC test. 1 : ECC test failed because eCT Flash macro is busy and using the SRAM. 0: ECC was performed. [8:8] read-only CM0_CA_CTL0 CM0+ cache control 0x400 32 read-write 0xC0000001 0xC7030003 RAM_ECC_EN Enable ECC checking for cache accesses: 0: Disabled. 1: Enabled. [0:0] read-write RAM_ECC_INJ_EN Enable error injection for cache. When '1', the parity (ECC_CTL.PARITY[6:0]) is used when a refill is done from the FLASH macro to the ECC_CTL.WORD_ADDR[23:0] word address. [1:1] read-write WAY Specifies the cache way for which cache information is provided in CM0_CA_STATUS0/1/2. [17:16] read-write SET_ADDR Specifies the cache set for which cache information is provided in CM0_CA_STATUS0/1/2. [26:24] read-write PREF_EN Prefetch enable: 0: Disabled. 1: Enabled. Prefetching requires the cache to be enabled; i.e. ENABLED is '1'. [30:30] read-write CA_EN Cache enable: 0: Disabled. The cache tag valid bits are reset to '0's and the cache LRU information is set to '1's (making way 0 the LRU way and way 3 the MRU way). 1: Enabled. [31:31] read-write CM0_CA_CTL1 CM0+ cache control 0x404 32 read-write 0xFA050003 0xFFFF0003 PWR_MODE Specifies power mode for CM0 cache. The following sequnece should be followed for turning OFF/ON the cache SRAM. Turn OFF sequence: a) Write CM0_CA_CTL0 to disable cache. b) Write CM0_CA_CTL1 to turn OFF cache SRAM. Turn ON sequence: a) Write CM0_CA_CTL1 to turn ON cache SRAM. b) Delay to allow power up of cache SRAM. Delay should be at a minimum of CM0_CA_CTL2.PWRUP_DELAY CLK_SLOW clock cycles. c) Write CM0_CA_CTL0 to enable cache. [1:0] read-write OFF Power OFF the CM0 cache SRAM. 0 RSVD Undefined 1 RETAINED Put CM0 cache SRAM in retained mode. 2 ENABLED Enable/Turn ON the CM0 cache SRAM. 3 VECTKEYSTAT Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW. [31:16] read-only CM0_CA_CTL2 CM0+ cache control 0x408 32 read-write 0x12C 0x3FF PWRUP_DELAY Number clock cycles delay needed after power domain power up [9:0] read-write CM0_CA_STATUS0 CM0+ cache status 0 0x440 32 read-only 0x0 0xFFFFFFFF VALID32 Sixteen valid bits of the cache line specified by CM0_CA_CTL.WAY and CM0_CA_CTL.SET_ADDR. [31:0] read-only CM0_CA_STATUS1 CM0+ cache status 1 0x444 32 read-only 0x0 0x0 TAG Cache line address of the cache line specified by CM0_CA_CTL.WAY and CM0_CA_CTL.SET_ADDR. [31:0] read-only CM0_CA_STATUS2 CM0+ cache status 2 0x448 32 read-only 0x0 0x0 LRU Six bit LRU representation of the cache set specified by CM0_CA_CTL.SET_ADDR. The encoding of the field is as follows ('X_LRU_Y' indicates that way X is Less Recently Used than way Y): Bit 5: 0_LRU_1: way 0 less recently used than way 1. Bit 4: 0_LRU_2. Bit 3: 0_LRU_3. Bit 2: 1_LRU_2. Bit 1: 1_LRU_3. Bit 0: 2_LRU_3. [5:0] read-only CM0_STATUS CM0+ interface status 0x460 32 read-write 0x0 0x3 MAIN_INTERNAL_ERR Specifies/registers the occurrence of a FLASH macro main interface internal error (typically the result of a read access while a program erase operation is ongoing) as a result of a CM0+ access (or debug access via SYS_AP/CM0_AP). SW clears this field to '0'. HW sets this field to '1' on a FLASH macro main interface internal error. Typically, SW reads this field after a code section to detect the occurrence of an error. Note: this field is independent of FLASH_CTL.MAIN_ERR_SILENT. [0:0] read-write WORK_INTERNAL_ERR See CM0_STATUS.MAIN_INTERNAL_ERROR. [1:1] read-write CM4_CA_CTL0 CM4 cache control 0x480 32 read-write 0xC0000001 0xC7030003 RAM_ECC_EN See CM0_CA_CTL. [0:0] read-write RAM_ECC_INJ_EN See CM0_CA_CTL. [1:1] read-write WAY See CM0_CA_CTL. [17:16] read-write SET_ADDR See CM0_CA_CTL. [26:24] read-write PREF_EN See CM0_CA_CTL. [30:30] read-write CA_EN See CM0_CA_CTL. [31:31] read-write CM4_CA_CTL1 CM4 cache control 0x484 32 read-write 0xFA050003 0xFFFF0003 PWR_MODE Specifies power mode for CM4 cache. Refer CM0_CA_CTL1 for more details. [1:0] read-write OFF See CM0_CA_CTL1 0 RSVD Undefined 1 RETAINED See CM0_CA_CTL1 2 ENABLED See CM0_CA_CTL1 3 VECTKEYSTAT Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW. [31:16] read-only CM4_CA_CTL2 CM4 cache control 0x488 32 read-write 0x12C 0x3FF PWRUP_DELAY Number clock cycles delay needed after power domain power up [9:0] read-write CM4_CA_STATUS0 CM4 cache status 0 0x4C0 32 read-only 0x0 0xFFFFFFFF VALID32 See CM0_CA_STATUS0. [31:0] read-only CM4_CA_STATUS1 CM4 cache status 1 0x4C4 32 read-only 0x0 0x0 TAG See CM0_CA_STATUS1. [31:0] read-only CM4_CA_STATUS2 CM4 cache status 2 0x4C8 32 read-only 0x0 0x0 LRU See CM0_CA_STATUS2. [5:0] read-only CM4_STATUS CM4 interface status 0x4E0 32 read-write 0x0 0x3 MAIN_INTERNAL_ERR Specifies/registers the occurrence of a FLASH macro main interface internal error (typically the result of a read access while a program erase operation is ongoing) as a result of a CM4 access (or debug access via SYS_AP/CM4_AP). SW clears this field to '0'. HW sets this field to '1' on a FLASH macro main interface internal error. Typically, SW reads this field after a code section to detect the occurrence of an error. Note: this field is independent of FLASH_CTL.MAIN_ERR_SILENT. [0:0] read-write WORK_INTERNAL_ERR See CM4_STATUS.MAIN_INTERNAL_ERROR. [1:1] read-write CRYPTO_BUFF_CTL Cryptography buffer control 0x500 32 read-write 0x40000000 0x40000000 PREF_EN Prefetch enable: 0: Disabled. 1: Enabled. A prefetch will be done when there is read 'hit' on the last 32-bit word of the buffer. For eCT work Flash, prefetch will not be done. [30:30] read-write DW0_BUFF_CTL Datawire 0 buffer control 0x580 32 read-write 0x40000000 0x40000000 PREF_EN See CRYPTO_BUFF_CTL. [30:30] read-write DW1_BUFF_CTL Datawire 1 buffer control 0x600 32 read-write 0x40000000 0x40000000 PREF_EN See CRYPTO_BUFF_CTL. [30:30] read-write DMAC_BUFF_CTL DMA controller buffer control 0x680 32 read-write 0x40000000 0x40000000 PREF_EN See CRYPTO_BUFF_CTL. [30:30] read-write EXT_MS0_BUFF_CTL External master 0 buffer control 0x700 32 read-write 0x40000000 0x40000000 PREF_EN See CRYPTO_BUFF_CTL. [30:30] read-write EXT_MS1_BUFF_CTL External master 1 buffer control 0x780 32 read-write 0x40000000 0x40000000 PREF_EN See CRYPTO_BUFF_CTL. [30:30] read-write FM_CTL Flash Macro Registers 0x0000F000 FM_CTL Flash macro control 0x0 32 read-write 0x0 0x37F030F FM_MODE Requires (IF_SEL|WR_EN)=1 Flash macro mode selection [3:0] read-write FM_SEQ Requires (IF_SEL|WR_EN)=1 Flash macro sequence selection [9:8] read-write DAA_MUX_SEL Direct memory cell access address. [22:16] read-write IF_SEL Interface selection. Specifies the interface that is used for flash memory read operations: 0: R interface is used (default value). In this case, the flash memory address is provided as part of the R signal interface. 1: C interface is used. In this case, the flash memory address is provided by FM_MEM_ADDR (the page address) and by the C interface access offset in the FM_MEM_DATA structure. Note: IF_SEL and WR_EN cannot be changed at the same time [24:24] read-write WR_EN 0: normal mode 1: Fm Write Enable Note: IF_SEL and WR_EN cannot be changed at the same time [25:25] read-write STATUS Status 0x4 32 read-only 0x1800 0xFFFFFFFF TIMER_ENABLED This is the timer_en bit set by writing a '1' in the TIMER_CTL bit 31. It is reset by HW when the timer expires 0: timer not running 1: Timer is enabled and not expired yet [0:0] read-only HV_REGS_ISOLATED Indicates the isolation status at HV trim and redundancy registers inputs 0: Not isolated, writing permitted 1: isolated writing disabled [1:1] read-only ILLEGAL_HVOP Indicates a bulk, sector erase, program has been requested when axa=1 0: no error 1: illegal HV operation error [2:2] read-only TURBO_N After FM power up indicates the analog blocks currents are boosted to faster reach their functional state.. Used in the testchip boot only as an 'FM READY' flag. 0: turbo mode 1: normal mode [3:3] read-only WR_EN_MON FM_CTL.WR_EN bit after being synchronized in clk_r domain [4:4] read-only IF_SEL_MON FM_CTL.IF_SEL bit after being synchronized in clk_r domain [5:5] read-only TIMER_STATUS The actual timer state sync-ed in clk_c domain: 0: timer is not running: 1: timer is running; [6:6] read-only R_GRANT_DELAY_STATUS 0: R_GRANT_DELAY timer is not running 1: R_GRANT_DELAY timer is running [7:7] read-only FM_BUSY 0': FM not busy 1: FM BUSY : R_GRANT is 0 as result of a busy request from FM ready, or from HV operations. [8:8] read-only FM_READY 0: FM not ready 1: FM ready [9:9] read-only POS_PUMP_VLO POS pump VLO [10:10] read-only NEG_PUMP_VHI NEG pump VHI [11:11] read-only RWW FM Type (Read While Write or Not Read While Write): 0: Non RWW FM Type 1: RWW FM Type [12:12] read-only MAX_DOUT_WIDTH Internal memory core max data out size (number of data out bits per column): 0: x128 bits 1: x256 bits [13:13] read-only SECTOR0_SR 0: Sector 0 does not contain special rows. The special rows are located in separate special sectors. 1: Sector 0 contains special rows [14:14] read-only RESET_MM Test_only, internal node: mpcon reset_mm [15:15] read-only ROW_ODD Test_only, internal node: mpcon row_odd [16:16] read-only ROW_EVEN Test_only, internal node: mpcon row_even [17:17] read-only HVOP_SUB_SECTOR_N Test_only, internal node: mpcon bk_subb [18:18] read-only HVOP_SECTOR Test_only, internal node: mpcon bk_sec [19:19] read-only HVOP_BULK_ALL Test_only, internal node: mpcon bk_all [20:20] read-only CBUS_RA_MATCH Test_only, internal node: mpcon ra match [21:21] read-only CBUS_RED_ROW_EN Test_only, internal node: mpcon red_row_en [22:22] read-only RQ_ERROR Test_only, internal node: rq_error sync-de in clk_c domain [23:23] read-only PUMP_PDAC Test_only, internal node: regif pdac outputs to pos pump [27:24] read-only PUMP_NDAC Test_only, internal node: regif ndac outputs to pos pump [31:28] read-only FM_ADDR Flash macro address 0x8 32 read-write 0x0 0x1FFFFFF RA Row address. [15:0] read-write BA Bank address. [23:16] read-write AXA Auxiliary address field: 0: regular flash memory. 1: supervisory flash memory. [24:24] read-write BOOKMARK Bookmark register - keeps the current FW HV seq 0xC 32 read-write 0x0 0xFFFFFFFF BOOKMARK Used by FW. Keeps the Current HV cycle sequence [31:0] read-write GEOMETRY Regular flash geometry 0x10 32 read-only 0x0 0xFFFFFFFF ROW_COUNT Number of rows (minus 1): 0: 1 row 1: 2 rows 2: 3 rows ... '65535': 65536 rows [15:0] read-only BANK_COUNT Number of banks (minus 1): 0: 1 bank 1: 2 banks ... '255': 256 banks [23:16] read-only WORD_SIZE_LOG2 Number of Bytes per word (log 2). A word is defined as the data that is read from the flash macro over the R interface with a single read access: 0: 1 Byte 1: 2 Bytes 2: 4 Bytes ... 3: 128 Bytes The currently planned flash macros have a word size of either 32-bit, 64-bit or 128-bit, resulting in WORD_SIZE_LOG2 settings of 2, 3 and 4 respectively. [27:24] read-only PAGE_SIZE_LOG2 Number of Bytes per page (log 2): 0: 1 Byte 1: 2 Bytes 2: 4 Bytes ... 15: 32768 Bytes The currently planned flash macros have a page size of either 256 Byte or 512 Byte, resulting in PAGE_SIZE_LOG2 settings of 8 and 9 respectively. [31:28] read-only GEOMETRY_SUPERVISORY Supervisory flash geometry 0x14 32 read-only 0x0 0xFFFFFFFF ROW_COUNT Number of rows (minus 1). ROW_COUNT is typically less than GEOMETRY.ROW_COUNT [15:0] read-only BANK_COUNT Number of banks (minus 1). BANK_COUNT is less or equal to GEOMETRY.BANK_COUNT. [23:16] read-only WORD_SIZE_LOG2 Number of Bytes per word (log 2). See GEOMETRY.WORD_SIZE_LOG2. Typically, WORD_SIZE_LOG2 equals GEOMETRY.WORD_SIZE_LOG2. [27:24] read-only PAGE_SIZE_LOG2 Number of Bytes per page (log 2). See GEOMETRY.PAGE_SIZE_LOG2. Typically, PAGE_SIZE_LOG2 equals GEOMETRY.PAGE_SIZE_LOG2. [31:28] read-only ANA_CTL0 Analog control 0 0x18 32 read-write 0x400 0xFFFFFFFF MDAC Trimming of the output margin Voltage as a function of Vpos and Vneg. [7:0] read-write CSLDAC Trimming of common source line DAC. [10:8] read-write FLIP_AMUXBUS_AB Flips amuxbusa and amuxbusb 0: amuxbusa, amuxbusb 1: amuxbusb, amuxbusb [11:11] read-write NDAC_MIN NDAC staircase min value [15:12] read-write PDAC_MIN PDAC staircase min value [19:16] read-write SCALE_PRG_SEQ01 PROG&PRE_PROG: Scale for R_GRANT_DELAY on seq0-seq1 transition: 00: 0.125uS 01: 1uS 10: 10uS 11: 100uS [21:20] read-write SCALE_PRG_SEQ12 PROG&PRE_PROG: Scale for R_GRANT_DELAY on seq1-seq2 transition: 00: 0.125uS 01: 1uS 10: 10uS 11: 100uS [23:22] read-write SCALE_PRG_SEQ23 PROG&PRE_PROG: Scale for R_GRANT_DELAY on seq2-seq3 transition: 00: 0.125uS 01: 1uS 10: 10uS 11: 100uS [25:24] read-write SCALE_SEQ30 PROG&PRE_PROG& ERASE: Scale for R_GRANT_DELAY on seq3-seq0 transition: 00: 0.125uS 01: 1uS 10: 10uS 11: 100uS [27:26] read-write SCALE_PRG_PEON PROG&PRE_PROG: Scale for R_GRANT_DELAY on PE On transition: 00: 0.125uS 01: 1uS 10: 10uS 11: 100uS [29:28] read-write SCALE_PRG_PEOFF PROG&PRE_PROG: Scale for R_GRANT_DELAY on PE OFF transition: 00: 0.125uS 01: 1uS 10: 10uS 11: 100uS [31:30] read-write ANA_CTL1 Analog control 1 0x1C 32 read-write 0xD32FAFA 0xFFFFFFFF NDAC_MAX Ndac Max Value.Trimming of negative pump output Voltage. [3:0] read-write NDAC_STEP Ndac step increment [7:4] read-write PDAC_MAX Pdac Max Value.Trimming of positive pump output Voltage: [11:8] read-write PDAC_STEP Pdac step increment [15:12] read-write NPDAC_STEP_TIME Ndac/Pdac step duration: (1uS .. 255uS) * 8 When = 0 N/PDAC_MAX control the pumps [23:16] read-write NPDAC_ZERO_TIME Ndac/Pdac LO duration: (1uS .. 255uS) * 8 When 0, N/PDAC don't return to 0 [31:24] read-write WAIT_CTL Wait State control 0x28 32 read-write 0x30B09 0x3F070F0F WAIT_FM_MEM_RD Number of C interface wait cycles (on 'clk_c') for a read from the memory [3:0] read-write WAIT_FM_HV_RD Number of C interface wait cycles (on 'clk_c') for a read from the high Voltage page latches. Common for reading HV Page Latches and the DATA_COMP_RESULT bit [11:8] read-write WAIT_FM_HV_WR Number of C interface wait cycles (on 'clk_c') for a write to the high Voltage page latches. [18:16] read-write FM_RWW_MODE 00: Full CBUS MODE 01: RWW 10: RWW. R_GRANT is stalling r_bus for the whole program/erase duration [25:24] read-write LV_SPARE_1 Spare register [26:26] read-write DRMM 0: Normal 1: Test mode to enable Margin mode for 2 rows at a time [27:27] read-write MBA 0: Normal 1: Test mode to enable Master Bulk Access which allows both normal rows and redundant rows to be erased / programmed in one HV cycle (Bulk / Sector Erase and Sector Program). [28:28] read-write PL_SOFT_SET_EN Page latch soft set enable, 0 = disabled, 1 = enabled (at end of seq_2), taken care in API [29:29] read-write TIMER_CLK_CTL Timer prescaler (clk_t to timer clock frequency divider) 0x34 32 read-write 0x8 0xFFFFFFFF TIMER_CLOCK_FREQ Clk_t frequency divider to provide the 1MHz reference clock for the Regif Timer. Equal to the frequency in MHz of the timer clock 'clk_t'. Example: if 'clk_t' has a frequency of 4 MHz then this field value is '4' Max clk_t frequency = 100MHz. This field is updated at runtime with the 'SW_TIMER_CLOCK_FREQ ' value from the HV parameters table [7:0] read-write RGRANT_DELAY_PRG_PEON PROG&PRE_PROG: R-grant blocking delay on PE ON. Scale = ANA_CTL0.SCALE_PEON When = 0 R_GRANT_DELAY control is disabled when IF_SEL=1 R_GRANT_DELAY control is disabled [15:8] read-write RGRANT_DELAY_PRG_PEOFF PROG&PRE_PROG: R-grant blocking delay on PE OFF. Scale = ANA_CTL0.SCALE_PEOFF When = 0 R_GRANT_DELAY control is disabled when IF_SEL=1 R_GRANT_DELAY control is disabled [23:16] read-write RGRANT_DELAY_PRG_SEQ01 PROG&PRE_PROG: R-grant blocking delay on seq0-seq1 transition. Scale = ANA_CTL0.SCALE_SEQ01 When = 0 R_GRANT_DELAY control is disabled when IF_SEL=1 R_GRANT_DELAY control is disabled [31:24] read-write TIMER_CTL Timer control 0x38 32 read-write 0x4000001 0xE700FFFF PERIOD Timer period in either microseconds (SCALE is '0') or 100's of microseconds (SCALE is '1') multiples. [14:0] read-write SCALE Timer tick scale: 0: 1 microsecond. 1: 100 microseconds. [15:15] read-write AUTO_SEQUENCE 1': Starts1 the HV automatic sequencing Cleared by HW [24:24] read-write PRE_PROG 1 during pre-program operation [25:25] read-write PRE_PROG_CSL 0: CSL lines driven by CSL_DAC 1: CSL lines driven by VNEG_G [26:26] read-write PUMP_EN Pump enable: 0: disabled 1: enabled (also requires FM_CTL.IF_SEL to be'1', this additional restriction is required to prevent non intentional clearing of the FM). SW sets this field to '1' to generate a single PE pulse. HW clears this field when timer is expired. [29:29] read-write ACLK_EN ACLK enable (generates a single cycle pulse for the FM): 0: disabled 1: enabled. SW set this field to '1' to generate a single cycle pulse. HW sets this field to '0' when the pulse is generated. [30:30] read-write TIMER_EN Timer enable: 0: disabled 1: enabled. SW sets this field to '1' to start the timer. HW sets this field to '0' when the timer is expired. [31:31] read-write ACLK_CTL MPCON clock 0x3C 32 write-only 0x0 0x1 ACLK_GEN A write to this register generates the clock pulse for HV control registers (mpcon outputs) [0:0] write-only INTR Interrupt 0x40 32 read-write 0x0 0x1 TIMER_EXPIRED Set to '1', when event is detected. Write INTR field with '1', to clear bit. Write INTR_SET field with '1', to set bit. [0:0] read-write INTR_SET Interrupt set 0x44 32 read-write 0x0 0x1 TIMER_EXPIRED Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [0:0] read-write INTR_MASK Interrupt mask 0x48 32 read-write 0x0 0x1 TIMER_EXPIRED Mask for corresponding field in INTR register. [0:0] read-write INTR_MASKED Interrupt masked 0x4C 32 read-only 0x0 0x1 TIMER_EXPIRED Logical and of corresponding request and mask fields. [0:0] read-only CAL_CTL0 Cal control BG LO trim bits 0x50 32 read-write 0x38F8F 0xFFFFF VCT_TRIM_LO_HV LO Bandgap Voltage Temperature Compensation trim control. [4:0] read-write CDAC_LO_HV LO Temperature compensated trim DAC. To control Vcstat slope for Vpos. [7:5] read-write VBG_TRIM_LO_HV LO Bandgap Voltage trim control. [12:8] read-write VBG_TC_TRIM_LO_HV LO Bandgap Voltage Temperature Compensation trim control [15:13] read-write ICREF_TC_TRIM_LO_HV LO Bandgap Current Temperature Compensation trim control [18:16] read-write IPREF_TRIMA_LO_HV Adds 100-150nA boost on IPREF_LO [19:19] read-write CAL_CTL1 Cal control BG HI trim bits 0x54 32 read-write 0x38F8F 0xFFFFF VCT_TRIM_HI_HV HI Bandgap Voltage Temperature Compensation trim control. [4:0] read-write CDAC_HI_HV HI Temperature compensated trim DAC. To control Vcstat slope for Vpos. [7:5] read-write VBG_TRIM_HI_HV HI Bandgap Voltage trim control. [12:8] read-write VBG_TC_TRIM_HI_HV HI Bandgap Voltage Temperature Compensation trim control. [15:13] read-write ICREF_TC_TRIM_HI_HV HI Bandgap Current Temperature Compensation trim control. [18:16] read-write IPREF_TRIMA_HI_HV Adds 100-150nA boost on IPREF_HI [19:19] read-write CAL_CTL2 Cal control BG LO&HI trim bits 0x58 32 read-write 0x7BE10 0xFFFFF ICREF_TRIM_LO_HV LO Bandgap Current trim control. [4:0] read-write ICREF_TRIM_HI_HV HI Bandgap Current trim control. [9:5] read-write IPREF_TRIM_LO_HV LO Bandgap IPTAT trim control. [14:10] read-write IPREF_TRIM_HI_HV HI Bandgap IPTAT trim control. [19:15] read-write CAL_CTL3 Cal control osc trim bits, idac, sdac, itim 0x5C 32 read-write 0x2004 0xFFFFF OSC_TRIM_HV Flash macro pump clock trim control. [3:0] read-write OSC_RANGE_TRIM_HV 0: Oscillator High Frequency Range 1: Oscillator Low Frequency range [4:4] read-write VPROT_ACT_HV Forces VPROT in active mode all the time [5:5] read-write IPREF_TC_HV 0: Increases the IPREF Tempco by subtracting ICREF from IPREF - IPREF internal will be 0.5uA 1: Reduces the IPREF Tempco without subtracting ICREF from IPREF - IPREF internal will be 1uA [6:6] read-write VREF_SEL_HV Voltage reference: 0: internal bandgap reference 1: external voltage reference [7:7] read-write IREF_SEL_HV Current reference: 0: internal current reference 1: external current reference [8:8] read-write REG_ACT_HV 0: VBST regulator will operate in active/standby mode based on control signal. 1: Forces the VBST regulator in active mode all the time [9:9] read-write FDIV_TRIM_HV FDIV_TRIM_HV[1:0]: Assuming oscillator frequency of 8MHz in standby. Following are the clock frequencies seen by doubler 00: F = 1MHz 01: F = 0.5MHz 10: F = 2MHz 11: F = 4MHz [11:10] read-write VDDHI_HV 0: vdd < 2.3V 1: vdd >= 2.3V '0' setting can used for vdd > 2.3V also, but with a current penalty. [12:12] read-write TURBO_PULSEW_HV Turbo pulse width trim (Typical) 00: 40 us 01: 20 us 10: 15 us 11: 8 us [14:13] read-write BGLO_EN_HV 0: Normal (Automatic change over from HI to LO) 1: Force enable LO Bandgap [15:15] read-write BGHI_EN_HV 0: Normal (Automatic change over from HI to LO) 1: Force enable HI Bandgap When both BGLO_EN_HV and BGHI_EN_HV are HIGH, only BGHI output is used and turbo_hv_n pulse is active [16:16] read-write CL_ISO_DIS_HV 0: The internal logic controls the CL isolation 1: Forces CL bypass [17:17] read-write R_GRANT_EN_HV 0: r_grant handshake disabled, r_grant always 1. 1: r_grand handshake enabled [18:18] read-write LP_ULP_SW_HV LP<-->ULP switch for trim signals: 0: LP 1: ULP [19:19] read-write CAL_CTL4 Cal Control Vlim, SA, fdiv, reg_act 0x60 32 read-write 0x12AE0 0xFFFFF VLIM_TRIM_ULP_HV VLIM_TRIM[1:0]: 00: V2 = 650mV 01: V2 = 600mV 10: V2 = 750mV 11: V2 = 700mV [1:0] read-write IDAC_ULP_HV Sets the sense current reference offset value. Refer to trim tables for details. [5:2] read-write SDAC_ULP_HV Sets the sense current reference temp slope. Refer to trim tables for details. [7:6] read-write ITIM_ULP_HV Trimming of timing current [12:8] read-write FM_READY_DEL_ULP_HV 00: Default : delay 1ns 01: Delayed by 1.5us 10: Delayed by 2.0us 11: Delayed by 2.5us [14:13] read-write SPARE451_ULP_HV N/A [15:15] read-write READY_RESTART_N_HV Toggle: 1-->0, ready goes low, ready will remain low as long as the bit is low. Toggle the bit back to 1 to activate the ready logic. To be used by API only. [16:16] read-write VBST_S_DIS_HV 0: VBST_S voltage for each sector to allow VBST level to be dropped to VCC during Erase in the selected sector, reducing coupling to GBL. 1: VBST_S voltage for each sector stays at VBST level during Erase in the selected sector. [17:17] read-write AUTO_HVPULSE_HV 0: HV Pulse controlled by FW 1: HV Pulse controlled by Hardware [18:18] read-write UGB_EN_HV UGB enable in TM control [19:19] read-write CAL_CTL5 Cal control 0x64 32 read-write 0x2AE0 0xFFFFF VLIM_TRIM_LP_HV VLIM_TRIM[1:0]: 00: V2 = 650mV 01: V2 = 600mV 10: V2 = 750mV 11: V2 = 700mV [1:0] read-write IDAC_LP_HV Sets the sense current reference offset value. Refer to trim tables for details. [5:2] read-write SDAC_LP_HV Sets the sense current reference temp slope. Refer to trim tables for details. [7:6] read-write ITIM_LP_HV Trimming of timing current [12:8] read-write FM_READY_DEL_LP_HV 00: Delayed by 1us 01: Delayed by 1.5us 10: Delayed by 2.0us 11: Delayed by 2.5us [14:13] read-write SPARE451_LP_HV N/A [15:15] read-write SPARE52_HV N/A [17:16] read-write AMUX_SEL_HV Amux Select in AMUX_UGB 00: Bypass UGB for both amuxbusa and amuxbusb 01: Bypass UGB for amuxbusb while passing amuxbusa through UGB. 10: Bypass UGB for amuxbusa while passing amuxbusb through UGB. 11: UGB Calibrate mode [19:18] read-write CAL_CTL6 SA trim LP/ULP 0x68 32 read-write 0x36F7F 0xFFFFF SA_CTL_TRIM_T1_ULP_HV clk_trk delay [0:0] read-write SA_CTL_TRIM_T4_ULP_HV SA_CTL_TRIM_T4_ULP_HV<2>= eqi (eq current trim) SA_CTL_TRIM_T4_ULP_HV<1:0> = eqc (eq cap trim) [3:1] read-write SA_CTL_TRIM_T5_ULP_HV SA_CTL_TRIM_T5_ULP_HV<2>= evi (integration current trim) SA_CTL_TRIM_T5_ULP_HV<1:0> = evc (integration cap trim) [6:4] read-write SA_CTL_TRIM_T6_ULP_HV SA_CTL_TRIM_T6_ULP_HV<1>= eni (enable current trim) SA_CTL_TRIM_T6_ULP_HV<0> = ecn (enable cap trim) [8:7] read-write SA_CTL_TRIM_T8_ULP_HV saen3 pulse width trim (Current trim) [9:9] read-write SA_CTL_TRIM_T1_LP_HV clk_trk delay [10:10] read-write SA_CTL_TRIM_T4_LP_HV SA_CTL_TRIM_T4_LP_HV<2>= eqi (eq current trim) SA_CTL_TRIM_T4_LP_HV<1:0> = eqc (eq cap trim) [13:11] read-write SA_CTL_TRIM_T5_LP_HV SA_CTL_TRIM_T5_LP_HV<2>= evi (integration current trim) SA_CTL_TRIM_T5_LP_HV<1:0> = evc (integration cap trim) [16:14] read-write SA_CTL_TRIM_T6_LP_HV SA_CTL_TRIM_T6_LP_HV<1>= eni (enable current trim) SA_CTL_TRIM_T6_LP_HV<0> = ecn (enable cap trim) [18:17] read-write SA_CTL_TRIM_T8_LP_HV saen3 pulse width trim (Current trim) [19:19] read-write CAL_CTL7 Cal control 0x6C 32 read-write 0x0 0xFFFFF ERSX8_CLK_SEL_HV Clock frequency into the ersx8 shift register block 00: Oscillator clock 01: Oscillator clock / 2 10: Oscillator clock / 4 11: Oscillator clock [1:0] read-write FM_ACTIVE_HV 0: Normal operation 1: Forces FM SYS in active mode [2:2] read-write TURBO_EXT_HV 0: Normal operation 1: Uses external turbo pulse [3:3] read-write NPDAC_HWCTL_DIS_HV 0': ndac, pdac staircase hardware controlled 1: ndac, pdac staircase disabled. Enables FW control. [4:4] read-write FM_READY_DIS_HV 0': fm ready is enabled 1: fm ready is disabled (fm_ready is always '1') [5:5] read-write ERSX8_EN_ALL_HV 0': Staggered turn on/off of GWL 1: GWL are turned on/off at the same time (old FM legacy) [6:6] read-write DISABLE_LOAD_ONCE_HV 0: Load common HV params during API HV operations depends on the HV_PARAMS_LOADED bit in RGRANT_DELAY_PRG register. 1: All HV params are loaded during every API HV operation irrespective of HV_PARAMS_LOADED bit in the RGRANT_DELAY_PRG register. [7:7] read-write SPARE7_HV N/A [9:8] read-write SPARE7_ULP_HV N/A [14:10] read-write SPARE7_LP_HV N/A [19:15] read-write RED_CTL01 Redundancy Control normal sectors 0,1 0x80 32 read-write 0x0 0x1FF01FF RED_ADDR_0 Bad Row Pair Address for Sector 0 [7:0] read-write RED_EN_0 1: Redundancy Enable for Sector 0 [8:8] read-write RED_ADDR_1 Bad Row Pair Address for Sector 1 [23:16] read-write RED_EN_1 1: Redundancy Enable for Sector 1 [24:24] read-write RED_CTL23 Redundancy Control normal sectors 2,3 0x84 32 read-write 0x0 0x1FF01FF RED_ADDR_2 Bad Row Pair Address for Sector 2 [7:0] read-write RED_EN_2 1: Redundancy Enable for Sector 2 [8:8] read-write RED_ADDR_3 Bad Row Pair Address for Sector 3 [23:16] read-write RED_EN_3 1: Redundancy Enable for Sector 3 [24:24] read-write RED_CTL45 Redundancy Control normal sectors 4,5 0x88 32 read-write 0x0 0x1FF01FF RED_ADDR_4 Bad Row Pair Address for Sector 4 [7:0] read-write RED_EN_4 1: Redundancy Enable for Sector 4 [8:8] read-write RED_ADDR_5 Bad Row Pair Address for Sector 5 [23:16] read-write RED_EN_5 1: Redundancy Enable for Sector 5 [24:24] read-write RED_CTL67 Redundancy Control normal sectors 6,7 0x8C 32 read-write 0x0 0x1FF01FF RED_ADDR_6 Bad Row Pair Address for Sector 6 [7:0] read-write RED_EN_6 1: Redundancy Enable for Sector 6 [8:8] read-write RED_ADDR_7 Bad Row Pair Address for Sector 7 [23:16] read-write RED_EN_7 1: Redundancy Enable for Sector 7 [24:24] read-write RED_CTL_SM01 Redundancy Control special sectors 0,1 0x90 32 read-write 0x0 0x1FF01FF RED_ADDR_SM0 Bad Row Pair Address for Special Sector 0 [7:0] read-write RED_EN_SM0 Redundancy Enable for Special Sector 0 [8:8] read-write RED_ADDR_SM1 Bad Row Pair Address for Special Sector 1 [23:16] read-write RED_EN_SM1 Redundancy Enable for Special Sector 1 [24:24] read-write RGRANT_DELAY_PRG R-grant delay for program 0x98 32 read-write 0x1000000 0x8FFFFFFF RGRANT_DELAY_PRG_SEQ12 PROG&PRE_PROG: R-grant blocking delay on seq1-seq2 transition. Scale = ANA_CTL0.SCALE_SEQ12 When = 0 R_GRANT_DELAY control is disabled when IF_SEL=1 R_GRANT_DELAY control is disabled [7:0] read-write RGRANT_DELAY_PRG_SEQ23 PROG&PRE_PROG: R-grant blocking delay on seq2-seq3 transition. Scale = ANA_CTL0.SCALE_SEQ23 When = 0 R_GRANT_DELAY control is disabled when IF_SEL=1 R_GRANT_DELAY control is disabled [15:8] read-write RGRANT_DELAY_SEQ30 PROG&PRE_PROG & ERASE: R-grant blocking delay on seq3-seq0 transition. Scale = ANA_CTL0.SCALE_SEQ30 When = 0 R_GRANT_DELAY control is disabled when IF_SEL=1 R_GRANT_DELAY control is disabled [23:16] read-write RGRANT_DELAY_CLK Frequency divider from clk_t to create the 8MHz reference clock for R_grant delay The value of this field is the integer result of 'clk_t frequency / 8'. Example: for clk_t=100 this field is INT(100/8) =12. This field is updated at runtime with the 'SW_RGRANT_DELAY_CLK ' value from the HV parameters table [27:24] read-write HV_PARAMS_LOADED 0: HV Pulse common params not loaded 1: HV Pulse common params loaded: r-grant delays, r-grant scale, prescaler, timer values for seq1,seq2_pre, seq2_post, seq3 [31:31] read-write PW_SEQ12 HV Pulse Delay for seq 1&2 pre 0xA0 32 read-write 0x0 0xFFFFFFFF PW_SEQ1 Seq1 delay [15:0] read-write PW_SEQ2_PRE Seq2 pre delay [31:16] read-write PW_SEQ23 HV Pulse Delay for seq2 post & seq3 0xA4 32 read-write 0x0 0xFFFFFFFF PW_SEQ2_POST Seq2 post delay [15:0] read-write PW_SEQ3 Seq3 delay [31:16] read-write RGRANT_SCALE_ERS R-grant delay scale for erase 0xA8 32 read-write 0x0 0xFFFF03FF SCALE_ERS_SEQ01 ERASE: Scale for R_GRANT_DELAY on seq0-seq1 transition: 00: 0.125uS 01: 1uS 10: 10uS 11: 100uS [1:0] read-write SCALE_ERS_SEQ12 ERASE: Scale for R_GRANT_DELAY on seq1-seq2 transition: 00: 0.125uS 01: 1uS 10: 10uS 11: 100uS [3:2] read-write SCALE_ERS_SEQ23 ERASE: Scale for R_GRANT_DELAY on seq2-seq3 transition: 00: 0.125uS 01: 1uS 10: 10uS 11: 100uS [5:4] read-write SCALE_ERS_PEON ERASE: Scale for R_GRANT_DELAY on PE On transition: 00: 0.125uS 01: 1uS 10: 10uS 11: 100uS [7:6] read-write SCALE_ERS_PEOFF ERASE: Scale for R_GRANT_DELAY on PE OFF transition: 00: 0.125uS 01: 1uS 10: 10uS 11: 100uS [9:8] read-write RGRANT_DELAY_ERS_PEON ERASE: R-grant blocking delay on PE ON. Scale = ANA_CTL0.SCALE_PEON When = 0 R_GRANT_DELAY control is disabled when IF_SEL=1 R_GRANT_DELAY control is disabled [23:16] read-write RGRANT_DELAY_ERS_PEOFF ERASE: R-grant blocking delay on PE OFF. Scale = ANA_CTL0.SCALE_PEOFF When = 0 R_GRANT_DELAY control is disabled when IF_SEL=1 R_GRANT_DELAY control is disabled [31:24] read-write RGRANT_DELAY_ERS R-grant delay for erase 0xAC 32 read-write 0x0 0xFFFFFF RGRANT_DELAY_ERS_SEQ01 ERASE: R-grant blocking delay on seq0-seq1 transition. Scale = ANA_CTL0.SCALE_SEQ01 When = 0 R_GRANT_DELAY control is disabled when IF_SEL=1 R_GRANT_DELAY control is disabled [7:0] read-write RGRANT_DELAY_ERS_SEQ12 ERASE: R-grant blocking delay on seq1-seq2 transition. Scale = ANA_CTL0.SCALE_SEQ12 When = 0 R_GRANT_DELAY control is disabled when IF_SEL=1 R_GRANT_DELAY control is disabled [15:8] read-write RGRANT_DELAY_ERS_SEQ23 ERASE: R-grant blocking delay on seq2-seq3 transition. Scale = ANA_CTL0.SCALE_SEQ23 When = 0 R_GRANT_DELAY control is disabled when IF_SEL=1 R_GRANT_DELAY control is disabled [23:16] read-write FM_PL_WRDATA_ALL Flash macro write page latches all 0x7FC 32 read-write 0x0 0xFFFFFFFF DATA32 Write all high Voltage page latches with the same 32-bit data in a single write cycle Read always returns 0. [31:0] read-write 256 4 FM_PL_DATA[%s] Flash macro Page Latches data 0x800 32 read-write 0x0 0xFFFFFFFF DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. [31:0] read-write 256 4 FM_MEM_DATA[%s] Flash macro memory sense amplifier and column decoder data 0xC00 32 read-only 0x0 0xFFFFFFFF DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. [31:0] read-only SRSS SRSS Core Registers 0x40260000 0 65536 registers PWR_CTL Power Mode Control 0x0 32 read-write 0x0 0xFFFC0033 POWER_MODE Current power mode of the device. Note that this field cannot be read in all power modes on actual silicon. [1:0] read-only RESET System is resetting. 0 ACTIVE At least one CPU is running. 1 SLEEP No CPUs are running. Peripherals may be running. 2 DEEPSLEEP Main high-frequency clock is off; low speed clocks are available. Communication interface clocks may be present. 3 DEBUG_SESSION Indicates whether a debug session is active (CDBGPWRUPREQ signal is 1) [4:4] read-only NO_SESSION No debug session active 0 SESSION_ACTIVE Debug session is active. Power modes behave differently to keep the debug session active, and current consumption may be higher than datasheet specification. 1 LPM_READY Indicates whether certain low power functions are ready. The low current circuits take longer to startup after XRES/POR/BOD/HIBERNATE wakeup than the normal mode circuits. HIBERNATE mode may be entered regardless of this bit. This register is only reset by XRES/POR/BOD/HIBERNATE. 0: If a low power circuit operation is requested, it will stay in its normal operating mode until it is ready. If DEEPSLEEP is requested by all processors WFI/WFE, the device will instead enter SLEEP. When low power circuits are ready, device will automatically enter the originally requested mode. 1: Normal operation. DEEPSLEEP and low power circuits operate as requested in other registers. [5:5] read-only IREF_LPMODE Control the power mode of the reference current generator. The value in this register is ignored and normal mode is used until LPM_READY==1. This register is only reset by XRES/POR/BOD/HIBERNATE. 0: Current reference generator operates in normal mode. 1: Current reference generator operates in low power mode. Response time is reduced to save current. [18:18] read-write VREFBUF_OK Indicates that the voltage reference buffer is ready. Due to synchronization delays, it may take two IMO clock cycles for hardware to clear this bit after asserting VREFBUF_DIS=1. [19:19] read-only DPSLP_REG_DIS Disable the DeepSleep regulator. This is only legal when the on-chip buck regulator supplies vccd, but there is no hardware protection for this case. This register is only reset by XRES/POR/BOD/HIBERNATE. 0: DeepSleep Regulator is on. 1: DeepSleep Regulator is off. [20:20] read-write RET_REG_DIS Disable the Retention regulator. This is only legal when the on-chip buck regulator supplies vccd, but there is no hardware protection for this case. This register is only reset by XRES/POR/BOD/HIBERNATE. 0: Retention Regulator is on. 1: Retention Regulator is off. [21:21] read-write NWELL_REG_DIS Disable the Nwell regulator. This is only legal when the on-chip buck regulator supplies vccd, but there is no hardware protection for this case. This register is only reset by XRES/POR/BOD/HIBERNATE. 0: Nwell Regulator is on. 1: Nwell Regulator is off. [22:22] read-write LINREG_DIS Disable the linear Core Regulator. This is only legal when the on-chip buck regulator supplies vccd, but there is no hardware protection for this case. This register is only reset by XRES/POR/BOD/HIBERNATE. 0: Linear regulator is on. 1: Linear regulator is off. [23:23] read-write LINREG_LPMODE Control the power mode of the Linear Regulator. The value in this register is ignored and normal mode is used until LPM_READY==1. This register is only reset by XRES/POR/BOD/HIBERNATE. 0: Linear Regulator operates in normal mode. 1: Linear Regulator operates in low power mode. Load current capability is reduced, and firmware must ensure the current is kept within the limit for this operating mode. [24:24] read-write PORBOD_LPMODE Control the power mode of the POR/BOD circuits. The value in this register is ignored and normal mode is used until LPM_READY==1. This register is only reset by XRES/POR/BOD/HIBERNATE. 0: POR/BOD circuits operate in normal mode. 1: POR/BOD circuits operate in low power mode. Response time is reduced to save current. [25:25] read-write BGREF_LPMODE Control the power mode of the Bandgap Voltage and Current References. This applies to voltage and current generation and is different than the reference voltage buffer. The value in this register is ignored and normal mode is used until LPM_READY==1. When lower power mode is used, the Active Reference circuit can be disabled to reduce current. Firmware is responsible to ensure ACT_REF_OK==1 before changing back to normal mode. This register is only reset by XRES/POR/BOD/HIBERNATE. 0: Active Bandgap Voltage and Current Reference operates in normal mode. 1: Active Bandgap Voltage and Current Reference operates in low power mode. Power supply rejection is reduced to save current. The Active Reference may be disabled using ACT_REF_DIS=0. [26:26] read-write PLL_LS_BYPASS Bypass level shifter inside the PLL. 0: Do not bypass the level shifter. This setting is ok for all operational modes and vccd target voltage. 1: Bypass the level shifter. This may reduce jitter on the PLL output clock, but can only be used when vccd is targeted to 1.1V nominal. Otherwise, it can result in clock degradation and static current. [27:27] read-write VREFBUF_LPMODE Control the power mode of the 800mV voltage reference buffer. The value in this register is ignored and normal mode is used until LPM_READY==1. 0: Voltage Reference Buffer operates in normal mode. This register is only reset by XRES/POR/BOD/HIBERNATE. 1: Voltage Reference Buffer operates in low power mode. Power supply rejection is reduced to save current. [28:28] read-write VREFBUF_DIS Disable the 800mV voltage reference buffer. Firmware should only disable the buffer when there is no connected circuit that is using it. SRSS circuits that require it are the PLL and ECO. A particular product may have circuits outside the SRSS that use the buffer. This register is only reset by XRES/POR/BOD/HIBERNATE. [29:29] read-write ACT_REF_DIS Disables the Active Reference. Firmware must ensure that LPM_READY==1 and BGREF_LPMODE==1 for at least 1us before disabling the Active Reference. When enabling the Active Reference, use ACT_REF_OK indicator to know when it is ready. This register is only reset by XRES/POR/BOD/HIBERNATE. 0: Active Reference is enabled 1: Active Reference is disabled [30:30] read-write ACT_REF_OK Indicates that the normal mode of the Active Reference is ready. [31:31] read-only PWR_HIBERNATE HIBERNATE Mode Register 0x4 32 read-write 0x0 0xCFFEFFFF TOKEN Contains a 8-bit token that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware to differentiate WAKEUP from a general RESET event. Note that waking up from HIBERNATE using XRES will reset this register. [7:0] read-write UNLOCK This byte must be set to 0x3A for FREEZE or HIBERNATE fields to operate. Any other value in this register will cause FREEZE/HIBERNATE to have no effect, except as noted in the FREEZE description. [15:8] read-write FREEZE Controls whether mode and state of GPIOs and SIOs in the system are frozen. This is intended to be used as part of the HIBERNATE entry and exit sequences. When entering HIBERNATE mode, the first write instructs DEEPSLEEP peripherals that they cannot ignore the upcoming freeze command. This occurs even in the illegal condition where UNLOCK is not set. If UNLOCK and HIBERNATE are properly set, the IOs actually freeze on the second write. [17:17] read-write MASK_HIBALARM When set, HIBERNATE will wakeup for a RTC interrupt [18:18] read-write MASK_HIBWDT When set, HIBERNATE will wakeup if WDT matches [19:19] read-write POLARITY_HIBPIN Each bit sets the active polarity of the corresponding wakeup pin. 0: Pin input of 0 will wakeup the part from HIBERNATE 1: Pin input of 1 will wakeup the part from HIBERNATE [23:20] read-write MASK_HIBPIN When set, HIBERNATE will wakeup if the corresponding pin input matches the POLARITY_HIBPIN setting. Each bit corresponds to one of the HIBERNATE wakeup pins. [27:24] read-write HIBERNATE_DISABLE Hibernate disable bit. 0: Normal operation, HIBERNATE works as described 1: Further writes to this register are ignored Note: This bit is a write-once bit until the next reset. Avoid changing any other bits in this register while disabling HIBERNATE mode. Also, it is recommended to clear the UNLOCK code, if it was previously written.. [30:30] read-write HIBERNATE Firmware sets this bit to enter HIBERNATE mode. The system will enter HIBERNATE mode immediately after writing to this bit and will wakeup only in response to XRES or WAKEUP event. Both UNLOCK and FREEZE must have been set correctly in a previous write operations. Otherwise, it will not enter HIBERNATE. External supplies must have been stable for 250us before entering HIBERNATE mode. [31:31] read-write PWR_LVD_CTL Low Voltage Detector (LVD) Configuration Register 0x8 32 read-write 0x0 0xFF HVLVD1_TRIPSEL Threshold selection for HVLVD1. Disable the LVD (HVLVD1_EN=0) before changing the threshold. 0: rise=1.225V (nom), fall=1.2V (nom) 1: rise=1.425V (nom), fall=1.4V (nom) 2: rise=1.625V (nom), fall=1.6V (nom) 3: rise=1.825V (nom), fall=1.8V (nom) 4: rise=2.025V (nom), fall=2V (nom) 5: rise=2.125V (nom), fall=2.1V (nom) 6: rise=2.225V (nom), fall=2.2V (nom) 7: rise=2.325V (nom), fall=2.3V (nom) 8: rise=2.425V (nom), fall=2.4V (nom) 9: rise=2.525V (nom), fall=2.5V (nom) 10: rise=2.625V (nom), fall=2.6V (nom) 11: rise=2.725V (nom), fall=2.7V (nom) 12: rise=2.825V (nom), fall=2.8V (nom) 13: rise=2.925V (nom), fall=2.9V (nom) 14: rise=3.025V (nom), fall=3.0V (nom) 15: rise=3.125V (nom), fall=3.1V (nom) [3:0] read-write HVLVD1_SRCSEL Source selection for HVLVD1 [6:4] read-write VDDD Select VDDD 0 AMUXBUSA Select AMUXBUSA (VDDD branch) 1 RSVD N/A 2 VDDIO N/A 3 AMUXBUSB Select AMUXBUSB (VDDD branch) 4 HVLVD1_EN Enable HVLVD1 voltage monitor. When the LVD is enabled, it takes 20us for it to settle. There is no hardware stabilization counter, and it may falsely trigger during settling. It is recommended that firmware keep the interrupt masked for at least 8us, write a 1'b1 to the corresponding SRSS_INTR field to any falsely pended interrupt, and then optionally unmask the interrupt. After enabling, it is further recommended to read the related PWR_LVD_STATUS field, since the interrupt only triggers on edges. This bit is cleared (LVD is disabled) when entering DEEPSLEEP to prevent false interrupts during wakeup. [7:7] read-write PWR_BUCK_CTL Buck Control Register 0x14 32 read-write 0x5 0xC0000007 BUCK_OUT1_SEL Voltage output selection for vccbuck1 output. This register is only reset by XRES/POR/BOD/HIBERNATE. When increasing the voltage, it can take up to 200us for the output voltage to settle. When decreasing the voltage, the settling time depends on the load current. 0: 0.85V 1: 0.875V 2: 0.90V 3: 0.95V 4: 1.05V 5: 1.10V 6: 1.15V 7: 1.20V [2:0] read-write BUCK_EN Master enable for buck converter. This register is only reset by XRES/POR/BOD/HIBERNATE. [30:30] read-write BUCK_OUT1_EN Enable for vccbuck1 output. The value in this register is ignored unless PWR_BUCK_CTL.BUCK_EN==1. This register is only reset by XRES/POR/BOD/HIBERNATE. The regulator takes up to 600us to charge the external capacitor. If there is additional load current while charging, this will increase the startup time. The TRM specifies the required sequence when transitioning vccd from the LDO to SIMO Buck output #1. [31:31] read-write PWR_BUCK_CTL2 Buck Control Register 2 0x18 32 read-write 0x0 0xC0000007 BUCK_OUT2_SEL Voltage output selection for vccbuck2 output. When increasing the voltage, it can take up to 200us for the output voltage to settle. When decreasing the voltage, the settling time depends on the load current. 0: 1.15V 1: 1.20V 2: 1.25V 3: 1.30V 4: 1.35V 5: 1.40V 6: 1.45V 7: 1.50V [2:0] read-write BUCK_OUT2_HW_SEL Hardware control for vccbuck2 output. When this bit is set, the value in BUCK_OUT2_EN is ignored and a hardware signal is used instead. If the product has supporting hardware, it can directly control the enable signal for vccbuck2. The same charging time in BUCK_OUT2_EN applies. [30:30] read-write BUCK_OUT2_EN Enable for vccbuck2 output. The value in this register is ignored unless PWR_BUCK_CTL.BUCK_EN==1. The regulator takes up to 600us to charge the external capacitor. If there is additional load current while charging, this will increase the startup time. [31:31] read-write PWR_LVD_STATUS Low Voltage Detector (LVD) Status Register 0x1C 32 read-only 0x0 0x1 HVLVD1_OK HVLVD1 output. 0: below voltage threshold 1: above voltage threshold [0:0] read-only 16 4 PWR_HIB_DATA[%s] HIBERNATE Data Register 0x80 32 read-write 0x0 0xFFFFFFFF HIB_DATA Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register. [31:0] read-write WDT_CTL Watchdog Counter Control Register 0x180 32 read-write 0xC0000001 0xC0000001 WDT_EN Enable this watchdog timer. This field is retained during DEEPSLEEP and HIBERNATE modes. [0:0] read-write WDT_LOCK Prohibits writing to WDT_*, CLK_ILO_CONFIG, CLK_SELECT.LFCLK_SEL, and CLK_TRIM_ILO_CTL registers when not equal 0. Requires at least two different writes to unlock. A change in WDT_LOCK takes effect beginning with the next write cycle. Note that this field is 2 bits to force multiple writes only. It represents only a single write protect signal protecting all those registers at the same time. WDT will lock on any reset. This field is not retained during DEEPSLEEP or HIBERNATE mode, so the WDT will be locked after wakeup from these modes. [31:30] read-write NO_CHG No effect 0 CLR0 Clears bit 0 1 CLR1 Clears bit 1 2 SET01 Sets both bits 0 and 1 3 WDT_CNT Watchdog Counter Count Register 0x184 32 read-write 0x0 0xFFFF COUNTER Current value of WDT Counter. The write feature of this register is for engineering use (DfV), have no synchronization, and can only be applied when the WDT is fully off. When writing, the value is updated immediately in the WDT counter, but it will read back as the old value until this register resynchronizes just after the negedge of ILO. Writes will be ignored if they occur when the WDT is enabled. [15:0] read-write WDT_MATCH Watchdog Counter Match Register 0x188 32 read-write 0x1000 0xFFFFF MATCH Match value for Watchdog counter. Every time WDT_COUNTER reaches MATCH an interrupt is generated. Two unserviced interrupts will lead to a system reset (i.e. at the third match). [15:0] read-write IGNORE_BITS The number of MSB bits of the watchdog timer that are NOT checked against MATCH. This value provides control over the time-to-reset of the watchdog (which happens after 3 successive matches). Up to 12 MSB can be ignored. Settings >12 behave like a setting of 12. [19:16] read-write 2 64 MCWDT_STRUCT[%s] Multi-Counter Watchdog Timer MCWDT_STRUCT 0x00000200 MCWDT_CNTLOW Multi-Counter Watchdog Sub-counters 0/1 0x4 32 read-write 0x0 0xFFFFFFFF WDT_CTR0 Current value of sub-counter 0 for this MCWDT. Software writes are ignored when the sub-counter is enabled. [15:0] read-write WDT_CTR1 Current value of sub-counter 1 for this MCWDT. Software writes are ignored when the sub-counter is enabled [31:16] read-write MCWDT_CNTHIGH Multi-Counter Watchdog Sub-counter 2 0x8 32 read-write 0x0 0xFFFFFFFF WDT_CTR2 Current value of sub-counter 2 for this MCWDT. Software writes are ignored when the sub-counter is enabled [31:0] read-write MCWDT_MATCH Multi-Counter Watchdog Counter Match Register 0xC 32 read-write 0x0 0xFFFFFFFF WDT_MATCH0 Match value for sub-counter 0 of this MCWDT [15:0] read-write WDT_MATCH1 Match value for sub-counter 1 of this MCWDT [31:16] read-write MCWDT_CONFIG Multi-Counter Watchdog Counter Configuration 0x10 32 read-write 0x0 0x1F010F0F WDT_MODE0 Watchdog Counter Action on Match. Action is taken on the next increment after the values match (WDT_CTR0=WDT_MATCH0). [1:0] read-write NOTHING Do nothing 0 INT Assert WDT_INTx 1 RESET Assert WDT Reset 2 INT_THEN_RESET Assert WDT_INTx, assert WDT Reset after 3rd unhandled interrupt 3 WDT_CLEAR0 Clear Watchdog Counter when WDT_CTR0=WDT_MATCH0. In other words WDT_CTR0 divides LFCLK by (WDT_MATCH0+1). 0: Free running counter 1: Clear on match. In this mode, the minimum legal setting of WDT_MATCH0 is 1. [2:2] read-write WDT_CASCADE0_1 Cascade Watchdog Counters 0,1. Counter 1 increments the cycle after WDT_CTR0=WDT_MATCH0. 0: Independent counters 1: Cascaded counters [3:3] read-write WDT_MODE1 Watchdog Counter Action on Match. Action is taken on the next increment after the values match (WDT_CTR1=WDT_MATCH1). [9:8] read-write NOTHING Do nothing 0 INT Assert WDT_INTx 1 RESET Assert WDT Reset 2 INT_THEN_RESET Assert WDT_INTx, assert WDT Reset after 3rd unhandled interrupt 3 WDT_CLEAR1 Clear Watchdog Counter when WDT_CTR1==WDT_MATCH1. In other words WDT_CTR1 divides LFCLK by (WDT_MATCH1+1). 0: Free running counter 1: Clear on match. In this mode, the minimum legal setting of WDT_MATCH1 is 1. [10:10] read-write WDT_CASCADE1_2 Cascade Watchdog Counters 1,2. Counter 2 increments the cycle after WDT_CTR1=WDT_MATCH1. It is allowed to cascade all three WDT counters. 0: Independent counters 1: Cascaded counters. When cascading all three counters, WDT_CLEAR1 must be 1. [11:11] read-write WDT_MODE2 Watchdog Counter 2 Mode. [16:16] read-write NOTHING Free running counter with no interrupt requests 0 INT Free running counter with interrupt request that occurs one LFCLK cycle after the specified bit in CTR2 toggles (see WDT_BITS2). 1 WDT_BITS2 Bit to observe for WDT_INT2: 0: Assert after bit0 of WDT_CTR2 toggles (one int every tick) ... 31: Assert after bit31 of WDT_CTR2 toggles (one int every 2^31 ticks) [28:24] read-write MCWDT_CTL Multi-Counter Watchdog Counter Control 0x14 32 read-write 0x0 0xB0B0B WDT_ENABLE0 Enable subcounter 0. May take up to 2 LFCLK cycles to take effect. 0: Counter is disabled (not clocked) 1: Counter is enabled (counting up) [0:0] read-write WDT_ENABLED0 Indicates actual state of counter. May lag WDT_ENABLE0 by up to two LFCLK cycles. [1:1] read-only WDT_RESET0 Resets counter 0 back to 0000. Hardware will reset this bit after counter was reset. This will take up to one LFCLK cycle to take effect. [3:3] read-write WDT_ENABLE1 Enable subcounter 1. May take up to 2 LFCLK cycles to take effect. 0: Counter is disabled (not clocked) 1: Counter is enabled (counting up) [8:8] read-write WDT_ENABLED1 Indicates actual state of counter. May lag WDT_ENABLE1 by up to two LFCLK cycles. [9:9] read-only WDT_RESET1 Resets counter 1 back to 0000. Hardware will reset this bit after counter was reset. This will take up to one LFCLK cycle to take effect. [11:11] read-write WDT_ENABLE2 Enable subcounter 2. May take up to 2 LFCLK cycles to take effect. 0: Counter is disabled (not clocked) 1: Counter is enabled (counting up) [16:16] read-write WDT_ENABLED2 Indicates actual state of counter. May lag WDT_ENABLE2 by up to two LFCLK cycles. [17:17] read-only WDT_RESET2 Resets counter 2 back to 0000. Hardware will reset this bit after counter was reset. This will take up to one LFCLK cycle to take effect. [19:19] read-write MCWDT_INTR Multi-Counter Watchdog Counter Interrupt Register 0x18 32 read-write 0x0 0x7 MCWDT_INT0 MCWDT Interrupt Request for sub-counter 0. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. Clearing this bit also prevents Reset from happening when WDT_MODE0=3. [0:0] read-write MCWDT_INT1 MCWDT Interrupt Request for sub-counter 1. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. Clearing this bit also prevents Reset from happening when WDT_MODE1=3. [1:1] read-write MCWDT_INT2 MCWDT Interrupt Request for sub-counter 2. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. Clearing this bit also prevents Reset from happening when WDT_MODE2=3. [2:2] read-write MCWDT_INTR_SET Multi-Counter Watchdog Counter Interrupt Set Register 0x1C 32 read-write 0x0 0x7 MCWDT_INT0 Set interrupt for MCWDT_INT0 [0:0] read-write MCWDT_INT1 Set interrupt for MCWDT_INT1 [1:1] read-write MCWDT_INT2 Set interrupt for MCWDT_INT2 [2:2] read-write MCWDT_INTR_MASK Multi-Counter Watchdog Counter Interrupt Mask Register 0x20 32 read-write 0x0 0x7 MCWDT_INT0 Mask for sub-counter 0 [0:0] read-write MCWDT_INT1 Mask for sub-counter 1 [1:1] read-write MCWDT_INT2 Mask for sub-counter 2 [2:2] read-write MCWDT_INTR_MASKED Multi-Counter Watchdog Counter Interrupt Masked Register 0x24 32 read-only 0x0 0x7 MCWDT_INT0 Logical and of corresponding request and mask bits. [0:0] read-only MCWDT_INT1 Logical and of corresponding request and mask bits. [1:1] read-only MCWDT_INT2 Logical and of corresponding request and mask bits. [2:2] read-only MCWDT_LOCK Multi-Counter Watchdog Counter Lock Register 0x28 32 read-write 0x0 0xC0000000 MCWDT_LOCK Prohibits writing control and configuration registers related to this MCWDT when not equal 0 (as specified in the other register descriptions). Requires at least two different writes to unlock. Note that this field is 2 bits to force multiple writes only. Each MCWDT has a separate local lock. LFCLK settings are locked by the global WDT_LOCK register, and this register has no effect on that. [31:30] read-write NO_CHG No effect 0 CLR0 Clears bit 0 1 CLR1 Clears bit 1 2 SET01 Sets both bits 0 and 1 3 16 4 CLK_DSI_SELECT[%s] Clock DSI Select Register 0x300 32 read-write 0x0 0x1F DSI_MUX Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH<i> using CLK_PATH_SELECT register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or to the reference inputs of FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock. [4:0] read-write DSI_OUT0 DSI0 - dsi_out[0] 0 DSI_OUT1 DSI1 - dsi_out[1] 1 DSI_OUT2 DSI2 - dsi_out[2] 2 DSI_OUT3 DSI3 - dsi_out[3] 3 DSI_OUT4 DSI4 - dsi_out[4] 4 DSI_OUT5 DSI5 - dsi_out[5] 5 DSI_OUT6 DSI6 - dsi_out[6] 6 DSI_OUT7 DSI7 - dsi_out[7] 7 DSI_OUT8 DSI8 - dsi_out[8] 8 DSI_OUT9 DSI9 - dsi_out[9] 9 DSI_OUT10 DSI10 - dsi_out[10] 10 DSI_OUT11 DSI11 - dsi_out[11] 11 DSI_OUT12 DSI12 - dsi_out[12] 12 DSI_OUT13 DSI13 - dsi_out[13] 13 DSI_OUT14 DSI14 - dsi_out[14] 14 DSI_OUT15 DSI15 - dsi_out[15] 15 ILO ILO - Internal Low-speed Oscillator 16 WCO WCO - Watch-Crystal Oscillator 17 ALTLF ALTLF - Alternate Low-Frequency Clock 18 PILO PILO - Precision Internal Low-speed Oscillator 19 16 4 CLK_PATH_SELECT[%s] Clock Path Select Register 0x340 32 read-write 0x0 0x7 PATH_MUX Selects a source for clock PATH<i>. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. [2:0] read-write IMO IMO - Internal R/C Oscillator 0 EXTCLK EXTCLK - External Clock Pin 1 ECO ECO - External-Crystal Oscillator 2 ALTHF ALTHF - Alternate High-Frequency clock input (product-specific clock) 3 DSI_MUX DSI_MUX - Output of DSI mux for this path. Using a DSI source directly as root of HFCLK will result in undefined behavior. 4 16 4 CLK_ROOT_SELECT[%s] Clock Root Select Register 0x380 32 read-write 0x0 0x8000003F ROOT_MUX Selects a clock path as the root of HFCLK<k> and for SRSS DSI input <k>. Use CLK_PATH_SELECT[i] to configure the desired path. Some paths may have FLL or PLL available (product-specific), and the control and bypass mux selections of these are in other registers. Configure the FLL using CLK_FLL_CONFIG register. Configure a PLL using the related CLK_PLL_CONFIG[k] register. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. [3:0] read-write PATH0 Select PATH0 (can be configured for FLL) 0 PATH1 Select PATH1 (can be configured for PLL0, if available in the product) 1 PATH2 Select PATH2 (can be configured for PLL1, if available in the product) 2 PATH3 Select PATH3 (can be configured for PLL2, if available in the product) 3 PATH4 Select PATH4 (can be configured for PLL3, if available in the product) 4 PATH5 Select PATH5 (can be configured for PLL4, if available in the product) 5 PATH6 Select PATH6 (can be configured for PLL5, if available in the product) 6 PATH7 Select PATH7 (can be configured for PLL6, if available in the product) 7 PATH8 Select PATH8 (can be configured for PLL7, if available in the product) 8 PATH9 Select PATH9 (can be configured for PLL8, if available in the product) 9 PATH10 Select PATH10 (can be configured for PLL9, if available in the product) 10 PATH11 Select PATH11 (can be configured for PLL10, if available in the product) 11 PATH12 Select PATH12 (can be configured for PLL11, if available in the product) 12 PATH13 Select PATH13 (can be configured for PLL12, if available in the product) 13 PATH14 Select PATH14 (can be configured for PLL13, if available in the product) 14 PATH15 Select PATH15 (can be configured for PLL14, if available in the product) 15 ROOT_DIV Selects predivider value for this clock root and DSI input. [5:4] read-write NO_DIV Transparent mode, feed through selected clock source w/o dividing. 0 DIV_BY_2 Divide selected clock source by 2 1 DIV_BY_4 Divide selected clock source by 4 2 DIV_BY_8 Divide selected clock source by 8 3 ENABLE Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled. [31:31] read-write CLK_SELECT Clock selection register 0x500 32 read-write 0x0 0xFF03 LFCLK_SEL Select source for LFCLK. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register. [1:0] read-write ILO ILO - Internal Low-speed Oscillator 0 WCO WCO - Watch-Crystal Oscillator. Requires Backup domain to be present and properly configured (including external watch crystal, if used). 1 ALTLF ALTLF - Alternate Low-Frequency Clock. Capability is product-specific 2 PILO PILO - Precision ILO. If present, it works in DEEPSLEEP and higher modes. Does not work in HIBERNATE mode. 3 PUMP_SEL Selects clock PATH<k>, where k=PUMP_SEL. The output of this mux goes to the PUMP_DIV to make PUMPCLK Each product has a specific number of available clock paths. Selecting a path that is not implemented on a product will result in undefined behavior. Note that this is not a glitch free mux. [11:8] read-write PUMP_DIV Division ratio for PUMPCLK. Uses selected PUMP_SEL clock as the source. [14:12] read-write NO_DIV Transparent mode, feed through selected clock source w/o dividing. 0 DIV_BY_2 Divide selected clock source by 2 1 DIV_BY_4 Divide selected clock source by 4 2 DIV_BY_8 Divide selected clock source by 8 3 DIV_BY_16 Divide selected clock source by 16 4 PUMP_ENABLE Enable the pump clock. PUMP_ENABLE and the PUMP_SEL mux are not glitch-free to minimize side-effects, avoid changing the PUMP_SEL and PUMP_DIV while changing PUMP_ENABLE. To change the settings, do the following: 1) If the pump clock is enabled, write PUMP_ENABLE=0 without changing PUMP_SEL and PUMP_DIV. 2) Change PUMP_SEL and PUMP_DIV to desired settings with PUMP_ENABLE=0. 3) Write PUMP_ENABLE=1 without changing PUMP_SEL and PUMP_DIV. [15:15] read-write CLK_TIMER_CTL Timer Clock Control Register 0x504 32 read-write 0x70000 0x80FF0301 TIMER_SEL Select source for TIMERCLK. The output of this mux can be further divided using TIMER_DIV. [0:0] read-write IMO IMO - Internal Main Oscillator 0 HF0_DIV Select the output of the predivider configured by TIMER_HF0_DIV. 1 TIMER_HF0_DIV Predivider used when HF0_DIV is selected in TIMER_SEL. If HFCLK0 frequency is less than 100MHz and has approximately 50 percent duty cycle, then no division is required (NO_DIV). Otherwise, select a divide ratio of 2, 4, or 8 before selected HF0_DIV as the timer clock. [9:8] read-write NO_DIV Transparent mode, feed through selected clock source w/o dividing or correcting duty cycle. 0 DIV_BY_2 Divide HFCLK0 by 2. 1 DIV_BY_4 Divide HFCLK0 by 4. 2 DIV_BY_8 Divide HFCLK0 by 8. 3 TIMER_DIV Divide selected timer clock source by (1+TIMER_DIV). The output of this divider is TIMERCLK Allows for integer divisions in the range [1, 256]. Do not change this setting while the timer is enabled. [23:16] read-write ENABLE Enable for TIMERCLK. 0: TIMERCLK is off 1: TIMERCLK is enabled [31:31] read-write CLK_ILO_CONFIG ILO Configuration 0x50C 32 read-write 0x80000000 0x80000001 ILO_BACKUP If backup domain is present on this product, this register indicates that ILO should stay enabled for use by backup domain during XRES, HIBERNATE mode, and through power-related resets like BOD on VDDD/VCCD. Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register. 0: ILO turns off at XRES/BOD event or HIBERNATE entry. 1: ILO remains on if backup domain is present and powered even for XRES/BOD or HIBERNATE entry. [0:0] read-write ENABLE Master enable for ILO. Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register. After enabling, it takes at most two cycles to reach the accuracy spec. [31:31] read-write CLK_IMO_CONFIG IMO Configuration 0x510 32 read-write 0x80000000 0x80000000 ENABLE Master enable for IMO oscillator. This bit must be high at all times for all functions to work properly. Hardware will automatically disable the IMO during HIBERNATE and XRES. It will automatically disable during DEEPSLEEP if CLK_MFO_CONFIG.DPSLP_ENABLE==0. [31:31] read-write CLK_OUTPUT_FAST Fast Clock Output Select Register 0x514 32 read-write 0x0 0xFFF0FFF FAST_SEL0 Select signal for fast clock output #0 [3:0] read-write NC Disabled - output is 0. For power savings, clocks are blocked before entering any muxes, including PATH_SEL0 and HFCLK_SEL0. 0 ECO External Crystal Oscillator (ECO) 1 EXTCLK External clock input (EXTCLK) 2 ALTHF Alternate High-Frequency (ALTHF) clock input to SRSS 3 TIMERCLK Timer clock. It is grouped with the fast clocks because it may be a gated version of a fast clock, and therefore may have a short high pulse. 4 PATH_SEL0 Selects the clock path chosen by PATH_SEL0 field 5 HFCLK_SEL0 Selects the output of the HFCLK_SEL0 mux 6 SLOW_SEL0 Selects the output of CLK_OUTPUT_SLOW.SLOW_SEL0 7 PATH_SEL0 Selects a clock path to use in fast clock output #0 logic. 0: FLL output 1-15: PLL output on path1-path15 (if available) [7:4] read-write HFCLK_SEL0 Selects a HFCLK tree for use in fast clock output #0 [11:8] read-write FAST_SEL1 Select signal for fast clock output #1 [19:16] read-write NC Disabled - output is 0. For power savings, clocks are blocked before entering any muxes, including PATH_SEL1 and HFCLK_SEL1. 0 ECO External Crystal Oscillator (ECO) 1 EXTCLK External clock input (EXTCLK) 2 ALTHF Alternate High-Frequency (ALTHF) clock input to SRSS 3 TIMERCLK Timer clock. It is grouped with the fast clocks because it may be a gated version of a fast clock, and therefore may have a short high pulse. 4 PATH_SEL1 Selects the clock path chosen by PATH_SEL1 field 5 HFCLK_SEL1 Selects the output of the HFCLK_SEL1 mux 6 SLOW_SEL1 Selects the output of CLK_OUTPUT_SLOW.SLOW_SEL1 7 PATH_SEL1 Selects a clock path to use in fast clock output #1 logic. 0: FLL output 1-15: PLL output on path1-path15 (if available) [23:20] read-write HFCLK_SEL1 Selects a HFCLK tree for use in fast clock output #1 logic [27:24] read-write CLK_OUTPUT_SLOW Slow Clock Output Select Register 0x518 32 read-write 0x0 0xFF SLOW_SEL0 Select signal for slow clock output #0 [3:0] read-write NC Disabled - output is 0. For power savings, clocks are blocked before entering any muxes. 0 ILO Internal Low Speed Oscillator (ILO) 1 WCO Watch-Crystal Oscillator (WCO) 2 BAK Root of the Backup domain clock tree (BAK) 3 ALTLF Alternate low-frequency clock input to SRSS (ALTLF) 4 LFCLK Root of the low-speed clock tree (LFCLK) 5 IMO Internal Main Oscillator (IMO). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit. 6 SLPCTRL Sleep Controller clock (SLPCTRL). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit. 7 PILO Precision Internal Low Speed Oscillator (PILO) 8 SLOW_SEL1 Select signal for slow clock output #1 [7:4] read-write NC Disabled - output is 0. For power savings, clocks are blocked before entering any muxes. 0 ILO Internal Low Speed Oscillator (ILO) 1 WCO Watch-Crystal Oscillator (WCO) 2 BAK Root of the Backup domain clock tree (BAK) 3 ALTLF Alternate low-frequency clock input to SRSS (ALTLF) 4 LFCLK Root of the low-speed clock tree (LFCLK) 5 IMO Internal Main Oscillator (IMO). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit. 6 SLPCTRL Sleep Controller clock (SLPCTRL). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit. 7 PILO Precision Internal Low Speed Oscillator (PILO) 8 CLK_CAL_CNT1 Clock Calibration Counter 1 0x51C 32 read-write 0x80000000 0x80FFFFFF CAL_COUNTER1 Down-counter clocked on fast clock output #0 (see CLK_OUTPUT_FAST). This register always reads as zero. Counting starts internally when this register is written with a nonzero value. CAL_COUNTER_DONE goes immediately low to indicate that the counter has started and will be asserted when the counters are done. Do not write this field unless CAL_COUNTER_DONE==1. Both clocks must be running or the measurement will not complete. A stalled counter can be recovered by selecting valid clocks, waiting until the measurement completes, and discarding the first result. [23:0] read-write CAL_COUNTER_DONE Status bit indicating that the internal counter #1 is finished counting and CLK_CAL_CNT2.COUNTER stopped counting up [31:31] read-only CLK_CAL_CNT2 Clock Calibration Counter 2 0x520 32 read-only 0x0 0xFFFFFF CAL_COUNTER2 Up-counter clocked on fast clock output #1 (see CLK_OUTPUT_FAST). When CLK_CAL_CNT1.CAL_COUNTER_DONE==1, the counter is stopped and can be read by SW. Do not read this value unless CAL_COUNTER_DONE==1. The expected final value is related to the ratio of clock frequencies used for the two counters and the value loaded into counter 1: CLK_CAL_CNT2.COUNTER=(F_cnt2/F_cnt1)*(CLK_CAL_CNT1.COUNTER) [23:0] read-only CLK_ECO_CONFIG ECO Configuration Register 0x52C 32 read-write 0x2 0x80000002 AGC_EN Automatic Gain Control (AGC) enable. When set, the oscillation amplitude is controlled to the level selected by ECO_TRIM0.ATRIM. When low, the amplitude is not explicitly controlled and can be as high as the vddd supply. WARNING: use care when disabling AGC because driving a crystal beyond its rated limit can permanently damage the crystal. [1:1] read-write ECO_EN Master enable for ECO oscillator. [31:31] read-write CLK_ECO_STATUS ECO Status Register 0x530 32 read-only 0x0 0x3 ECO_OK Indicates the ECO internal oscillator circuit has sufficient amplitude. It may not meet the PPM accuracy or duty cycle spec. [0:0] read-only ECO_READY Indicates the ECO internal oscillator circuit has had enough time to fully stabilize. This is the output of a counter since ECO was enabled, and it does not check the ECO output. It is recommended to also confirm ECO_OK==1. [1:1] read-only CLK_PILO_CONFIG Precision ILO Configuration Register 0x53C 32 read-write 0x80 0xE00003FF PILO_FFREQ Fine frequency trim allowing +/-250ppm accuracy with periodic calibration. The nominal step size of the LSB is 8Hz. [9:0] read-write PILO_CLK_EN Enable the PILO clock output. See PILO_EN field for required sequencing. [29:29] read-write PILO_RESET_N Reset the PILO. See PILO_EN field for required sequencing. [30:30] read-write PILO_EN Enable PILO. When enabling PILO, set PILO_EN=1, wait 1ms, then PILO_RESET_N=1 and PILO_CLK_EN=1. When disabling PILO, clear PILO_EN=0, PILO_RESET_N=0, and PLO_CLK_EN=0 in the same write cycle. [31:31] read-write CLK_MF_SELECT Medium Frequency Clock Select Register 0x544 32 read-write 0x0 0x8000FF07 MFCLK_SEL Select source for MFCLK (clk_mf). Note that not all products support all clock sources. Selecting a clock source that is not supported results in undefined behavior. [2:0] read-write MFO MFO - medium frequency oscillator 0 MFCLK_DIV Divide selected clock source by (1+MFCLK_DIV). The output of this divider is MFCLK (clk_mf). Allows for integer divisions in the range [1, 256]. Do not change this setting while ENABLE==1. [15:8] read-write ENABLE Enable for MFCLK (clk_mf). [31:31] read-write CLK_MFO_CONFIG MFO Configuration Register 0x548 32 read-write 0x80000000 0xC0000000 DPSLP_ENABLE Enable for MFO during DEEPSLEEP. This bit is ignored when ENABLE==0. When ENABLE==1: 0: MFO is automatically disabled during DEEPSLEEP and enables upon wakeup; 1: MFO is kept enabled throughout DEEPSLEEP [30:30] read-write ENABLE Enable for MFO. [31:31] read-write CLK_FLL_CONFIG FLL Configuration Register 0x580 32 read-write 0x1000000 0x8103FFFF FLL_MULT Multiplier to determine CCO frequency in multiples of the frequency of the selected reference clock (Fref). Ffll = (FLL_MULT) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV+1) [17:0] read-write FLL_OUTPUT_DIV Control bits for Output divider. Set the divide value before enabling the FLL, and do not change it while FLL is enabled. 0: no division 1: divide by 2 [24:24] read-write FLL_ENABLE Master enable for FLL. The FLL requires firmware sequencing when enabling, disabling, and entering/exiting DEEPSLEEP. To enable the FLL, first enable the CCO by writing CLK_FLL_CONFIG4.CCO_ENABLE=1 and wait until CLK_FLL_STATUS.CCO_READY==1. Next, ensure the reference clock has stabilized and CLK_FLL_CONFIG3.BYPASS_SEL=FLL_REF. Next, write FLL_ENABLE=1 and wait until CLK_FLL_STATUS.LOCKED==1. Finally, write CLK_FLL_CONFIG3.BYPASS_SEL=FLL_OUT to switch to the FLL output. It takes seven reference clock cycles plus four FLL output cycles to switch to the FLL output. Do not disable the FLL before this time completes. To disable the FLL, write CLK_FLL_CONFIG3.BYPASS_SEL=FLL_REF and (optionally) read the same register to ensure the write completes. Then, wait at least seven FLL reference clock cycles before disabling it with FLL_ENABLE=0. Lastly, disable the CCO by writing CLK_FLL_CONFIG4.CCO_ENABLE=0. Before entering DEEPSLEEP, either disable the FLL using above sequence or use the following procedure to deselect/select it before/after DEEPSLEEP. Before entering DEEPSLEEP, write CLK_FLL_CONFIG3.BYPASS_SEL=FLL_REF to change the FLL to use its reference clock. After DEEPSLEEP wakeup, wait until CLK_FLL_STATUS.LOCKED==1 and then write CLK_FLL_CONFIG3.BYPASS_SEL=FLL_OUT to switch to the FLL output. 0: Block is powered off 1: Block is powered on [31:31] read-write CLK_FLL_CONFIG2 FLL Configuration Register 2 0x584 32 read-write 0x20001 0x1FF1FFF FLL_REF_DIV Control bits for reference divider. Set the divide value before enabling the FLL, and do not change it while FLL is enabled. 0: illegal (undefined behavior) 1: divide by 1 ... 8191: divide by 8191 [12:0] read-write LOCK_TOL Lock tolerance sets the error threshold for when the FLL output is considered locked to the reference input. A high tolerance can be used to lock more quickly or to track a less accurate source. The tolerance should be set so that the FLL does not unlock under normal conditions. The tolerance is the allowed difference between the count value for the ideal formula and the measured value. 0: tolerate error of 1 count value 1: tolerate error of 2 count values ... 511: tolerate error of 512 count values [24:16] read-write CLK_FLL_CONFIG3 FLL Configuration Register 3 0x588 32 read-write 0x2800 0x301FFFFF FLL_LF_IGAIN FLL Loop Filter Gain Setting #1. The proportional gain is the sum of FLL_LF_IGAIN and FLL_LF_PGAIN. 0: 1/256 1: 1/128 2: 1/64 3: 1/32 4: 1/16 5: 1/8 6: 1/4 7: 1/2 8: 1.0 9: 2.0 10: 4.0 11: 8.0 >=12: illegal [3:0] read-write FLL_LF_PGAIN FLL Loop Filter Gain Setting #2. The proportional gain is the sum of FLL_LF_IGAIN and FLL_LF_PGAIN. 0: 1/256 1: 1/128 2: 1/64 3: 1/32 4: 1/16 5: 1/8 6: 1/4 7: 1/2 8: 1.0 9: 2.0 10: 4.0 11: 8.0 >=12: illegal [7:4] read-write SETTLING_COUNT Number of undivided reference clock cycles to wait after changing the CCO trim until the loop measurement restarts. A delay allows the CCO output to settle and gives a more accurate measurement. The default is tuned to an 8MHz reference clock since the IMO is expected to be the most common use case. 0: no settling time 1: wait one reference clock cycle ... 8191: wait 8191 reference clock cycles [20:8] read-write BYPASS_SEL Bypass mux located just after FLL output. See FLL_ENABLE description for instructions on how to use this field when enabling/disabling the FLL. [29:28] read-write AUTO N/A 0 AUTO1 N/A 1 FLL_REF Select FLL reference input (bypass mode). Ignores lock indicator 2 FLL_OUT Select FLL output. Ignores lock indicator. 3 CLK_FLL_CONFIG4 FLL Configuration Register 4 0x58C 32 read-write 0xFF 0xC1FF07FF CCO_LIMIT Maximum CCO offset allowed (used to prevent FLL dynamics from selecting an CCO frequency that the logic cannot support) [7:0] read-write CCO_RANGE Frequency range of CCO [10:8] read-write RANGE0 Target frequency is in range [48, 64) MHz 0 RANGE1 Target frequency is in range [64, 85) MHz 1 RANGE2 Target frequency is in range [85, 113) MHz 2 RANGE3 Target frequency is in range [113, 150) MHz 3 RANGE4 Target frequency is in range [150, 200] MHz 4 CCO_FREQ CCO frequency code. This is updated by HW when the FLL is enabled. It can be manually updated to use the CCO in an open loop configuration. The meaning of each frequency code depends on the range. [24:16] read-write CCO_HW_UPDATE_DIS Disable CCO frequency update by FLL hardware 0: Hardware update of CCO settings is allowed. Use this setting for normal FLL operation. 1: Hardware update of CCO settings is disabled. Use this setting for open-loop FLL operation. [30:30] read-write CCO_ENABLE Enable the CCO. It is required to enable the CCO before using the FLL. 0: Block is powered off 1: Block is powered on [31:31] read-write CLK_FLL_STATUS FLL Status Register 0x590 32 read-write 0x0 0x7 LOCKED FLL Lock Indicator. LOCKED is high when FLL is within CLK_FLL_CONFIG2.LOCK_TOL. If FLL is outside LOCK_TOL, LOCKED goes low. Note that this can happen during normal operation, if FLL needs to recalculate due to a change in the reference clock, change in voltage, or change in temperature. [0:0] read-only UNLOCK_OCCURRED N/A [1:1] read-write CCO_READY This indicates that the CCO is internally settled and ready to use. [2:2] read-only 15 4 CLK_PLL_CONFIG[%s] PLL Configuration Register 0x600 32 read-write 0x20116 0xB81F1F7F FEEDBACK_DIV Control bits for feedback divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0-21: illegal (undefined behavior) 22: divide by 22 ... 112: divide by 112 >112: illegal (undefined behavior) [6:0] read-write REFERENCE_DIV Control bits for reference divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: divide by 1 ... 20: divide by 20 others: illegal (undefined behavior) [12:8] read-write OUTPUT_DIV Control bits for Output divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: illegal (undefined behavior) 2: divide by 2. Suitable for direct usage as HFCLK source. ... 16: divide by 16. Suitable for direct usage as HFCLK source. >16: illegal (undefined behavior) [20:16] read-write PLL_LF_MODE VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled. 0: VCO frequency is [200MHz, 400MHz] 1: VCO frequency is [170MHz, 200MHz) [27:27] read-write BYPASS_SEL Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running. [29:28] read-write AUTO Automatic using lock indicator. When unlocked, automatically selects PLL reference input (bypass mode). When locked, automatically selects PLL output. 0 AUTO1 Same as AUTO 1 PLL_REF Select PLL reference input (bypass mode). Ignores lock indicator 2 PLL_OUT Select PLL output. Ignores lock indicator. 3 ENABLE Master enable for PLL. Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1. To disable the PLL, first deselect it using .BYPASS_SEL=PLL_REF, wait at least six PLL clock cycles, and then disable it with .ENABLE=0. Fpll = (FEEDBACK_DIV) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV) 0: Block is disabled 1: Block is enabled [31:31] read-write 15 4 CLK_PLL_STATUS[%s] PLL Status Register 0x640 32 read-write 0x0 0x3 LOCKED PLL Lock Indicator [0:0] read-only UNLOCK_OCCURRED This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware. [1:1] read-write SRSS_INTR SRSS Interrupt Register 0x700 32 read-write 0x0 0x23 WDT_MATCH WDT Interrupt Request. This bit is set each time WDT_COUNTR==WDT_MATCH. W1C also feeds the watch dog. Missing 2 interrupts in a row will generate a reset. Due to internal synchronization, it takes 2 SYSCLK cycles to update after a W1C. [0:0] read-write HVLVD1 Interrupt for low voltage detector HVLVD1 [1:1] read-write CLK_CAL Clock calibration counter is done. This field is reset during DEEPSLEEP mode. [5:5] read-write SRSS_INTR_SET SRSS Interrupt Set Register 0x704 32 read-write 0x0 0x23 WDT_MATCH Set interrupt for low voltage detector WDT_MATCH [0:0] read-write HVLVD1 Set interrupt for low voltage detector HVLVD1 [1:1] read-write CLK_CAL Set interrupt for clock calibration counter done. This field is reset during DEEPSLEEP mode. [5:5] read-write SRSS_INTR_MASK SRSS Interrupt Mask Register 0x708 32 read-write 0x0 0x23 WDT_MATCH Mask for watchdog timer. Clearing this bit will not forward the interrupt to the CPU. It will not, however, disable the WDT reset generation on 2 missed interrupts. When WDT resets the chip, it also internally pends an interrupt that survives the reset. To prevent unintended ISR execution, clear SRSS_INTR.WDT_MATCH before setting this bit. [0:0] read-write HVLVD1 Mask for low voltage detector HVLVD1 [1:1] read-write CLK_CAL Mask for clock calibration done [5:5] read-write SRSS_INTR_MASKED SRSS Interrupt Masked Register 0x70C 32 read-only 0x0 0x23 WDT_MATCH Logical and of corresponding request and mask bits. [0:0] read-only HVLVD1 Logical and of corresponding request and mask bits. [1:1] read-only CLK_CAL Logical and of corresponding request and mask bits. [5:5] read-only SRSS_INTR_CFG SRSS Interrupt Configuration Register 0x710 32 read-write 0x0 0x3 HVLVD1_EDGE_SEL Sets which edge(s) will trigger an IRQ for HVLVD1 [1:0] read-write DISABLE Disabled 0 RISING Rising edge 1 FALLING Falling edge 2 BOTH Both rising and falling edges 3 RES_CAUSE Reset Cause Observation Register 0x800 32 read-write 0x0 0x1FF RESET_WDT A basic WatchDog Timer (WDT) reset has occurred since last power cycle. [0:0] read-write RESET_ACT_FAULT Fault logging system requested a reset from its Active logic. [1:1] read-write RESET_DPSLP_FAULT Fault logging system requested a reset from its DeepSleep logic. [2:2] read-write RESET_CSV_WCO_LOSS Clock supervision logic requested a reset due to loss of a watch-crystal clock. [3:3] read-write RESET_SOFT A CPU requested a system reset through it's SYSRESETREQ. This can be done via a debugger probe or in firmware. [4:4] read-write RESET_MCWDT0 Multi-Counter Watchdog timer reset #0 has occurred since last power cycle. [5:5] read-write RESET_MCWDT1 Multi-Counter Watchdog timer reset #1 has occurred since last power cycle. [6:6] read-write RESET_MCWDT2 Multi-Counter Watchdog timer reset #2 has occurred since last power cycle. [7:7] read-write RESET_MCWDT3 Multi-Counter Watchdog timer reset #3 has occurred since last power cycle. [8:8] read-write RES_CAUSE2 Reset Cause Observation Register 2 0x804 32 read-write 0x0 0xFFFFFFFF RESET_CSV_HF_LOSS Clock supervision logic requested a reset due to loss of a high-frequency clock. Each bit index K corresponds to a HFCLK<K>. Unimplemented clock bits return zero. [15:0] read-write RESET_CSV_HF_FREQ Clock supervision logic requested a reset due to frequency error of high-frequency clock. Each bit index K corresponds to a HFCLK<K>. Unimplemented clock bits return zero. [31:16] read-write PWR_TRIM_REF_CTL Reference Trim Register 0x7F00 32 read-write 0x70F00000 0xF1FF5FFF ACT_REF_TCTRIM Active-Reference temperature trim. This register is only reset by XRES/POR/BOD/HIBERNATE. 0 -> default setting at POR; not for trimming use others -> normal trim range [3:0] read-write ACT_REF_ITRIM Active-Reference current trim. This register is only reset by XRES/POR/BOD/HIBERNATE. 0 -> default setting at POR; not for trimming use others -> normal trim range [7:4] read-write ACT_REF_ABSTRIM Active-Reference absolute voltage trim. This register is only reset by XRES/POR/BOD/HIBERNATE. 0 -> default setting at POR; not for trimming use others -> normal trim range [12:8] read-write ACT_REF_IBOOST Active-Reference current boost. This register is only reset by XRES/POR/BOD/HIBERNATE. 0: normal operation others: risk mitigation [14:14] read-write DPSLP_REF_TCTRIM DeepSleep-Reference temperature trim. This register is only reset by XRES/POR/BOD/HIBERNATE. 0 -> default setting at POR; not for trimming use others -> normal trim range [19:16] read-write DPSLP_REF_ABSTRIM DeepSleep-Reference absolute voltage trim. This register is only reset by XRES/POR/BOD/HIBERNATE. [24:20] read-write DPSLP_REF_ITRIM DeepSleep current reference trim. This register is only reset by XRES/POR/BOD/HIBERNATE. [31:28] read-write PWR_TRIM_BODOVP_CTL BOD/OVP Trim Register 0x7F04 32 read-write 0x40D04 0xFDFF7 HVPORBOD_TRIPSEL HVPORBOD trip point selection. Monitors vddd. This register is only reset by XRES/POR/BOD/HIBERNATE. [2:0] read-write HVPORBOD_OFSTRIM HVPORBOD offset trim. This register is only reset by XRES/POR/BOD/HIBERNATE. [6:4] read-write HVPORBOD_ITRIM HVPORBOD current trim. This register is only reset by XRES/POR/BOD/HIBERNATE. [9:7] read-write LVPORBOD_TRIPSEL LVPORBOD trip point selection. Monitors vccd. This register is only reset by XRES/POR/BOD/HIBERNATE. [12:10] read-write LVPORBOD_OFSTRIM LVPORBOD offset trim. This register is only reset by XRES/POR/BOD/HIBERNATE. [16:14] read-write LVPORBOD_ITRIM LVPORBOD current trim. This register is only reset by XRES/POR/BOD/HIBERNATE. [19:17] read-write CLK_TRIM_CCO_CTL CCO Trim Register 0x7F08 32 read-write 0xA7000020 0xBF00003F CCO_RCSTRIM CCO reference current source trim. [5:0] read-write CCO_STABLE_CNT Terminal count for the stabilization counter from CCO_ENABLE until stable. [29:24] read-write ENABLE_CNT Enables the automatic stabilization counter. [31:31] read-write CLK_TRIM_CCO_CTL2 CCO Trim Register 2 0x7F0C 32 read-write 0x884110 0x1FFFFFF CCO_FCTRIM1 CCO frequency 1st range calibration [4:0] read-write CCO_FCTRIM2 CCO frequency 2nd range calibration [9:5] read-write CCO_FCTRIM3 CCO frequency 3rd range calibration [14:10] read-write CCO_FCTRIM4 CCO frequency 4th range calibration [19:15] read-write CCO_FCTRIM5 CCO frequency 5th range calibration [24:20] read-write PWR_TRIM_WAKE_CTL Wakeup Trim Register 0x7F30 32 read-write 0x0 0xFF WAKE_DELAY Wakeup holdoff. Spec (fastest) wake time is achieved with a setting of 0. Additional delay can be added for debugging or workaround. The delay is counted by the IMO. [7:0] read-write PWR_TRIM_LVD_CTL LVD Trim Register 0xFF10 32 read-write 0x20 0x77 HVLVD1_OFSTRIM HVLVD1 offset trim [2:0] read-write HVLVD1_ITRIM HVLVD1 current trim [6:4] read-write CLK_TRIM_ILO_CTL ILO Trim Register 0xFF18 32 read-write 0x2C 0x3F ILO_FTRIM ILO frequency trims. LSB step size is 1.5 percent (typical) of the frequency. [5:0] read-write PWR_TRIM_PWRSYS_CTL Power System Trim Register 0xFF1C 32 read-write 0x17 0x1F ACT_REG_TRIM Trim for the Active-Regulator. This sets the output voltage level. This register is only reset by XRES/POR/BOD/HIBERNATE. The nominal output voltage is vccd=812.5mV + ACT_REG_TRIM*12.5mV. The actual output voltage will vary depending on conditions and load. The following settings are explicitly shown for convenience, and other values may be calculated using the formula: 5'h07: 900mV (nominal) 5'h17: 1100mV (nominal) [4:0] read-write ACT_REG_BOOST Controls the tradeoff between output current and internal operating current for the Active Regulator. The maximum output current depends on the silicon implementation, but an application may limit its maximum current to less than that. This may allow a reduction in the internal operating current of the regulator. The regulator internal operating current depends on the boost setting: 2'b00: 50uA 2'b01: 100uA 2'b10: 150uA 2'b11: 200uA The allowed setting is a lookup table based on the chip-specific maximum (set in factory) and an application-specific maximum (set by customer). The defaults are set assuming the application consumes the maximum allowed by the chip. 50mA chip: 2'b00 (default); 100mA chip: 2'b00 (default); 150mA chip: 50..100mA app => 2'b00, 150mA app => 2'b01 (default); 200mA chip: 50mA app => 2'b00, 100..150mA app => 2'b01, 200mA app => 2'b10 (default); 250mA chip: 50mA app => 2'b00, 100..150mA app => 2'b01, 200..250mA app => 2'b10 (default); 300mA chip: 50mA app => 2'b00, 100..150mA app => 2'b01, 200..250mA app => 2'b10, 300mA app => 2'b11 (default); This register is only reset by XRES/POR/BOD/HIBERNATE. [31:30] read-write CLK_TRIM_ECO_CTL ECO Trim Register 0xFF20 32 read-write 0x1F0003 0x3F3FF7 WDTRIM Watch Dog Trim - Delta voltage below steady state level 0x0 - 50mV 0x1 - 75mV 0x2 - 100mV 0x3 - 125mV 0x4 - 150mV 0x5 - 175mV 0x6 - 200mV 0x7 - 225mV [2:0] read-write ATRIM Amplitude trim to set the crystal drive level when ECO_CONFIG.AGC_EN=1. WARNING: use care when setting this field because driving a crystal beyond its rated limit can permanently damage the crystal. 0x0 - 150mV 0x1 - 175mV 0x2 - 200mV 0x3 - 225mV 0x4 - 250mV 0x5 - 275mV 0x6 - 300mV 0x7 - 325mV 0x8 - 350mV 0x9 - 375mV 0xA - 400mV 0xB - 425mV 0xC - 450mV 0xD - 475mV 0xE - 500mV 0xF - 525mV [7:4] read-write FTRIM Filter Trim - 3rd harmonic oscillation [9:8] read-write RTRIM Feedback resistor Trim [11:10] read-write GTRIM Gain Trim - Startup time [13:12] read-write ITRIM Current Trim [21:16] read-write CLK_TRIM_PILO_CTL PILO Trim Register 0xFF24 32 read-write 0x108500F 0x7DFF703F PILO_CFREQ Coarse frequency trim to meet 32.768kHz +/-2 percent across PVT without calibration. The nominal step size of the LSB is 1kHz. [5:0] read-write PILO_OSC_TRIM Trim for current in oscillator block. [14:12] read-write PILO_COMP_TRIM Trim for comparator bias current. [17:16] read-write PILO_NBIAS_TRIM Trim for biasn by trimming sub-Vth NMOS width in beta-multiplier [19:18] read-write PILO_RES_TRIM Trim for beta-multiplier branch current [24:20] read-write PILO_ISLOPE_TRIM Trim for beta-multiplier current slope [27:26] read-write PILO_VTDIFF_TRIM Trim for VT-DIFF output (internal power supply) [30:28] read-write CLK_TRIM_PILO_CTL2 PILO Trim Register 2 0xFF28 32 read-write 0xDA10E0 0xFF1FFF PILO_VREF_TRIM Trim for voltage reference [7:0] read-write PILO_IREFBM_TRIM Trim for beta-multiplier current reference [12:8] read-write PILO_IREF_TRIM Trim for current reference [23:16] read-write CLK_TRIM_PILO_CTL3 PILO Trim Register 3 0xFF2C 32 read-write 0x4800 0xFFFF PILO_ENGOPT Engineering options for PILO circuits 0: Short vdda to vpwr 1: Beta:mult current change 2: Iref generation Ptat current addition 3: Disable current path in secondary Beta:mult startup circuit 4: Double oscillator current 5: Switch between deep:sub:threshold and sub:threshold stacks in Vref generation block 6: Spare 7: Ptat component increase in Iref 8: vpwr_rc and vpwr_dig_rc shorting testmode 9: Switch b/w psub connection for cascode nfet for vref generation 10: Switch between sub:threshold and deep:sub:threshold stacks in comparator. 15-11: Frequency fine trim. See AKK-444 for an overview of the trim strategy. [15:0] read-write DW0 Datawire Controller DW 0x40280000 0 65536 registers CTL Control 0x0 32 read-write 0x1 0x80000003 ECC_EN Enable ECC checking: '0': Disabled. '1': Enabled. [0:0] read-write ECC_INJ_EN Enable parity injection for SRAM. When '1', the parity (ECC_CTL.PARITY) is used when a full 32-bit write is done to the ECC_CTL.WORD_ADDR word address of the SRAM. [1:1] read-write ENABLED IP enable: '0': Disabled. Disabling the IP activates the IP's Active logic reset: Active logic and non-retention MMIO registers are reset (retention MMIO registers are not affected). '1': Enabled. [31:31] read-write STATUS Status 0x4 32 read-only 0x0 0xF0000000 P Active channel, user/privileged access control: '0': user mode. '1': privileged mode. [0:0] read-only NS Active channel, secure/non-secure access control: '0': secure. '1': non-secure. [1:1] read-only B Active channel, non-bufferable/bufferable access control: '0': non-bufferable '1': bufferable. [2:2] read-only PC Active channel protection context. [7:4] read-only PRIO Active channel priority. [9:8] read-only PREEMPTABLE Active channel preemptable. [11:11] read-only CH_IDX Active channel index. [24:16] read-only STATE State of the DW controller. '0': Default/inactive state. '1': Loading descriptor. '2': Loading data element from source location. '3': Storing data element to destination location. '4': CRC functionality (only used for CRC transfer descriptor type). '5': Update of active control information (e.g. source and destination addresses) and wait for trigger de-activation. '6': Error. [30:28] read-only ACTIVE Active channel present: '0': No. '1': Yes. [31:31] read-only ACT_DESCR_CTL Active descriptor control 0x20 32 read-only 0x0 0x0 DATA N/A [31:0] read-only ACT_DESCR_SRC Active descriptor source 0x24 32 read-only 0x0 0x0 DATA Copy of DESCR_SRC of the currently active descriptor. Base address of source location. [31:0] read-only ACT_DESCR_DST Active descriptor destination 0x28 32 read-only 0x0 0x0 DATA Copy of DESCR_DST of the currently active descriptor. Base address of destination location. Note: For a CRC transfer descriptor, this field should be programmed with the address of the CRC_LFSR_CTL register. The calculated CRC LFSR state is written to this address (through the CRYPTO AHB-Lite master interface) when the input trigger is processed. The write transfer will be submitted to the CPUSS and PERI protection schemes. [31:0] read-only ACT_DESCR_X_CTL Active descriptor X loop control 0x30 32 read-only 0x0 0x0 DATA Copy of DESCR_X_CTL of the currently active descriptor. [11:0] SRC_X_INCR Specifies increment of source address for each X loop iteration (in multiples of SRC_TRANSFER_SIZE). This field is a signed number in the range [-2048, 2047]. If this field is '0', the source address is not incremented. This is useful for reading from RX FIFO structures. [23:12] DST_X_INCR Specifies increment of destination address for each X loop iteration (in multiples of DST_TRANSFER_SIZE). This field is a signed number in the range [-2048, 2047]. If this field is '0', the destination address is not incremented. This is useful for writing to TX FIFO structures. Note: this field is not used for CRC transfer descriptors and must be set to '0'. [31:24] X_COUNT Number of iterations (minus 1) of the 'X loop' (X_COUNT+1 is the number of single transfers in a 1D transfer). This field is an unsigned number in the range [0, 255], representing 1 through 256 iterations. For a single transfer descriptor type, descriptor will not have X_CTL. [31:0] read-only ACT_DESCR_Y_CTL Active descriptor Y loop control 0x34 32 read-only 0x0 0x0 DATA Copy of DESCR_Y_CTL of the currently active descriptor. [11:0] SRC_Y_INCR Specifies increment of source address for each Y loop iteration (in multiples of SRC_TRANSFER_SIZE). This field is a signed number in the range [-2048, 2047]. [23:12] DST_Y_INCR Specifies increment of destination address for each Y loop iteration (in multiples of DST_TRANSFER_SIZE). This field is a signed number in the range [-2048, 2047]. [31:24] Y_COUNT Number of iterations (minus 1) of the 'Y loop' (X_COUNT+1)*(Y_COUNT+1) is the number of single transfers in a 2D transfer). This field is an unsigned number in the range [0, 255], representing 1 through 256 iterations. For single, 1D and CRC transfer descriptor types, descriptor will not have Y_CTL. [31:0] read-only ACT_DESCR_NEXT_PTR Active descriptor next pointer 0x38 32 read-only 0x0 0x0 ADDR Copy of DESCR_NEXT_PTR of the currently active descriptor. [31:2] ADDR Address of next descriptor in descriptor list. When this field is '0', this is the last descriptor in the descriptor list. [31:2] read-only ACT_SRC Active source 0x40 32 read-only 0x0 0x0 SRC_ADDR Current address of source location. [31:0] read-only ACT_DST Active destination 0x44 32 read-only 0x0 0x0 DST_ADDR Current address of destination location. [31:0] read-only ECC_CTL ECC control 0x80 32 read-write 0x0 0xFE0003FF WORD_ADDR Specifies the word address where an error will be injected. - On a write transfer to this SRAM word address and when CTL.ECC_INJ_EN bit is '1', the parity (PARITY) is injected. [9:0] read-write PARITY ECC parity to use for ECC error injection at address WORD_ADDR. [31:25] read-write CRC_CTL CRC control 0x100 32 read-write 0x0 0x101 DATA_REVERSE Specifies the bit order in which a data Byte is processed (reversal is performed after XORing): '0': Most significant bit (bit 1) first. '1': Least significant bit (bit 0) first. [0:0] read-write REM_REVERSE Specifies whether the remainder is bit reversed (reversal is performed after XORing): '0': No. '1': Yes. [8:8] read-write CRC_DATA_CTL CRC data control 0x110 32 read-write 0x0 0xFF DATA_XOR Specifies a byte mask with which each data byte is XOR'd. The XOR is performed before data reversal. [7:0] read-write CRC_POL_CTL CRC polynomial control 0x120 32 read-write 0x0 0xFFFFFFFF POLYNOMIAL CRC polynomial. The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1'). The polynomial should be aligned/shifted such that the more significant bits (bit 31 and down) contain the polynomial and the less significant bits (bit 0 and up) contain padding '0's. Some frequently used polynomials: - CRC32: POLYNOMIAL is 0x04c11db7 (x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1). - CRC16: POLYNOMIAL is 0x80050000 (x^16 + x^15 + x^2 + 1, shifted by 16 bit positions). - CRC16 CCITT: POLYNOMIAL is 0x10210000 (x^16 + x^12 + x^5 + 1, shifted by 16 bit positions). [31:0] read-write CRC_LFSR_CTL CRC LFSR control 0x130 32 read-write 0x0 0xFFFFFFFF LFSR32 State of a 32-bit Linear Feedback Shift Registers (LFSR) that is used to implement CRC. This register needs to be initialized by SW to provide the CRC seed value. The seed value should be aligned such that the more significant bits (bit 31 and down) contain the seed value and the less significant bits (bit 0 and up) contain padding '0's. Note that SW can write this field. This functionality can be used prevent information leakage (through either CRC_LFSR_CTL or CRC_REM_RESULT). [31:0] read-write CRC_REM_CTL CRC remainder control 0x140 32 read-write 0x0 0xFFFFFFFF REM_XOR Specifies a mask with which the CRC_LFSR_CTL.LFSR32 register is XOR'd to produce a remainder. The XOR is performed before remainder reversal. [31:0] read-write CRC_REM_RESULT CRC remainder result 0x148 32 read-only 0x0 0xFFFFFFFF REM Remainder value. The alignment of the remainder depends on CRC_REM_CTL0.REM_REVERSE: '0': the more significant bits (bit 31 and down) contain the remainder. '1': the less significant bits (bit 0 and up) contain the remainder. Note: This field is combinatorially derived from CRC_LFSR_CTL.LFSR32, CRC_CTL.REM_REVERSE and CRC_REM_CTL.REM_XOR. [31:0] read-only 32 64 CH_STRUCT[%s] DW channel structure 0x00008000 CH_CTL Channel control 0x0 32 read-write 0x0 0x80000300 P User/privileged access control: '0': user mode. '1': privileged mode. This field is set with the user/privileged access control of the transaction that writes this register; i.e. the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel use the P field for the user/privileged access control ('hprot[1]'). [0:0] read-write NS Secure/on-secure access control: '0': secure. '1': non-secure. This field is set with the secure/non-secure access control of the transaction that writes this register; i.e. the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel use the NS field for the secure/non-secure access control ('hprot[4]'). [1:1] read-write B Non-bufferable/bufferable access control: '0': non-bufferable. '1': bufferable. This field is used to indicate to an AMBA bridge that a write transaction can complete without waiting for the destination to accept the write transaction data. All transactions for this channel uses the B field for the non-bufferable/bufferable access control ('hprot[2]'). [2:2] read-write PC Protection context. This field is set with the protection context of the transaction that writes this register; i.e. the 'write data' is ignored and instead the context is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel uses the PC field for the protection context. [7:4] read-write PRIO Channel priority: '0': highest priority. '1' '2' '3': lowest priority. Channels with the same priority constitute a priority group. Priority decoding determines the highest priority pending channel. This channel is determined as follows. First, the highest priority group with pending channels is identified. Second, within this priority group, round robin arbitration is applied. Round robin arbitration (within a priority group) gives the highest priority to the lower channel indices (within the priority group). [9:8] read-write PREEMPTABLE Specifies if the channel is preemptable. '0': Not preemptable. '1': Preemptable. This field allows higher priority pending channels (from a higher priority group; i.e. an active channel can NOT be preempted by a pending channel in the same priority group) to preempt the active channel in between 'single transfers' (a 1D transfer consists out of X_COUNT single transfers; a 2D transfer consists out of X_COUNT*Y_COUNT single transfers). Preemption will NOT affect the pending status of channel. As a result, after completion of a higher priority activated channel, the current channel may be reactivated. [11:11] read-write ENABLED Channel enable: '0': Disabled. The channel's trigger is ignored and the channel cannot be made pending and therefore cannot be made active. If a pending channel is disabled, the channel is made non pending. If the activate channel is disabled, the channel is de-activated (bus transactions are completed). '1': Enabled. SW sets this field to '1' to enable a specific channel. HW sets this field to '0' on an error interrupt cause (the specific error is specified by CH_STATUS.INTR_CAUSE). [31:31] read-write CH_STATUS Channel status 0x4 32 read-only 0x0 0x80000000 INTR_CAUSE Specifies the source of the interrupt cause: '0': No interrupt generated '1': Interrupt based on transfer complettion configuration based on INTR_TYPE '2': Source transfer bus error '3': Destination transfer bus error '4': Source address misalignment '5': Destination address misalignment '6': Current descriptor pointer is null '7': Active channel is disabled '8': Descriptor bus error '9'-'15': Not used. For error related interrupt causes (INTR_CAUSE is '2', '3', ..., '8'), the channel is disabled (HW sets CH_CTL.ENABLED to '0'). [3:0] read-only PENDING Specifies pending DW channels; i.e. enabled channels whose trigger got activated. This field includes all channels that are in the pending state (not scheduled) or active state (scheduled and performing data transfer(s)). [31:31] read-only CH_IDX Channel current indices 0x8 32 read-write 0x0 0x0 X_IDX Specifies the X loop index. In the range of [0, X_COUNT], with X_COUNT taken from the current descriptor. Note: HW sets this field to '0' when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: SW should set this field to '0' when it updates CH_CURR_PTR. [7:0] read-write Y_IDX Specifies the Y loop index, with X_COUNT taken from the current descriptor. Note: HW sets this field to '0' when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: SW should set this field to '0' when it updates CH_CURR_PTR. [15:8] read-write CH_CURR_PTR Channel current descriptor pointer 0xC 32 read-write 0x0 0x0 ADDR Address of current descriptor. When this field is '0', there is no valid descriptor. Note: HW updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: Typically, when SW updates the current descriptor pointer CH_CURR_PTR, it also sets CH_IDX.X_IDX and CH_IDX.Y_IDX to '0'. [31:2] read-write INTR Interrupt 0x10 32 read-write 0x0 0x1 CH Set to '1', when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1', to clear bit. Write INTR_SET.CH field with '1', to set bit. [0:0] read-write INTR_SET Interrupt set 0x14 32 read-write 0x0 0x1 CH Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect). [0:0] read-write INTR_MASK Interrupt mask 0x18 32 read-write 0x0 0x1 CH Mask for corresponding field in INTR register. [0:0] read-write INTR_MASKED Interrupt masked 0x1C 32 read-only 0x0 0x1 CH Logical and of corresponding INTR and INTR_MASK fields. [0:0] read-only SRAM_DATA0 SRAM data 0 0x20 32 read-write 0x0 0x0 DATA N/A [31:0] read-write SRAM_DATA1 SRAM data 1 0x24 32 read-write 0x0 0x0 DATA N/A [31:0] read-write TR_CMD Channel software trigger 0x28 32 read-write 0x0 0x1 ACTIVATE Software trigger. When written with '1', a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0. [0:0] read-write DW1 0x40290000 DMAC DMAC 0x402A0000 0 65536 registers CTL Control 0x0 32 read-write 0x0 0x80000000 ENABLED IP enable: '0': Disabled. All non-retention registers (command and status registers) are reset to their default value when the IP is disabled. All retention registers retain their value when the IP is disabled. '1': Enabled. [31:31] read-write DISABLED N/A 0 ENABLED N/A 1 ACTIVE Active channels 0x8 32 read-only 0x0 0xFF ACTIVE Specifies active channels; i.e. enabled channels whose trigger got activated. [7:0] read-only 6 256 CH[%s] DMA controller channel 0x00001000 CTL Channel control 0x0 32 read-write 0x2 0x800003F7 P User/privileged access control: '0': user mode. '1': privileged mode. This field is set with the user/privileged access control of the transaction that writes this register; i.e. the access control is inherited from the write transaction and not specified by the transaction write data. All transactions for this channel use the P field for the user/privileged access control ('hprot[1]'). [0:0] read-write NS Secure/on-secure access control: '0': secure. '1': non-secure. This field is set with the secure/non-secure access control of the transaction that writes this register; i.e. the access control is inherited from the write transaction and not specified by the transaction write data. All transactions for this channel use the NS field for the secure/non-secure access control ('hprot[4]'). [1:1] read-write B Non-bufferable/bufferable access control: '0': non-bufferable. '1': bufferable. This field is used to indicate to an AMBA bridge that a write transaction can complete without waiting for the destination to accept the write transaction data. All transactions for this channel uses the B field for the non-bufferable/bufferable access control ('hprot[2]'). [2:2] read-write PC Protection context. This field is set with the protection context of the transaction that writes this register; i.e. the context is inherited from the write transaction and not specified by the transaction write data. All transactions for this channel uses the PC field for the protection context. [7:4] read-write PRIO Channel priority: '0': highest priority. '1' '2' '3': lowest priority. Channels with the same priority constitute a priority group and within this priority group, the following 'roundrobin' arbitration is applied. A 'round' consists of a contiguous sequence of channel activations, within this priority group, without any repetition. Within a round, higher priority is given to the lower channel indices. The notion of a round guarantees that within a group, higher channel indices do not yield to lower indices indefinitely. [9:8] read-write ENABLED Channel enable: '0': Disabled. The channel's trigger is ignored and the channel cannot be made pending and therefore cannot be made active. If a pending channel is disabled, the channel is made non pending. If the activate channel is disabled, the channel is de-activated (bus transactions are completed). '1': Enabled. SW sets this field to '1' to enable a specific channel. HW sets this field to '0' when an error interrupt cause is activated. [31:31] read-write IDX Channel current indices 0x10 32 read-only 0x0 0x0 X Specifies the X loop index. In the range of [0, X_COUNT], with X_COUNT taken from the current descriptor. Note: HW sets this field to '0' when it loads a descriptor. [15:0] read-only Y Specifies the Y loop index, with Y_COUNT taken from the current descriptor. Note: HW sets this field to '0' when it loads a descriptor.. [31:16] read-only SRC Channel current source address 0x14 32 read-only 0x0 0x0 ADDR Current address of source location. [31:0] read-only DST Channel current destination address 0x18 32 read-only 0x0 0x0 ADDR Current address of destination location. [31:0] read-only CURR Channel current descriptor pointer 0x20 32 read-write 0x0 0x0 PTR Address of current descriptor. When this field is '0', there is no valid descriptor. Note: HW updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. [31:2] read-write TR_CMD Channle software trigger 0x28 32 read-write 0x0 0x1 ACTIVATE Software trigger. When written with '1', a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0. [0:0] read-write DESCR_STATUS Channel descriptor status 0x40 32 read-only 0x0 0x80000000 VALID Indicates whether the descriptor information present in DESCR_CTL, DESCR_SRC, DESCR_DST, DESCR_X_SIZE, DESCR_X_INCR, DESCR_Y_SIZE, DESCR_Y_INCR, DESCR_NEXT status registers is valid or not. [31:31] read-only DESCR_CTL Channel descriptor control 0x60 32 read-only 0x0 0x0 WAIT_FOR_DEACT Specifies whether the controller should wait for the input trigger to be deactivated; i.e. the selected system trigger is not active. This field is used to synchronize the controller with the agent that generated the trigger. This field is ONLY used at the completion of the transfer as specified by TR_IN. E.g., a TX FIFO indicates that it is empty and it needs a new data sample. The agent removes the trigger ONLY when the data sample has been written by the controller AND received by the agent. Furthermore, the agent's trigger may be delayed by a few cycles before it reaches the controller. This field is used for level sensitive trigger, which reflect state (pulse sensitive triggers should have this field set to '0'). The wait cycles incurred by this field reduce DW controller performance. '0': Do not wait for trigger de-activation (for pulse sensitive triggers). '1': Wait for up to 4 cycles. '2': Wait for up to 16 cycles. '3': Wait indefinitely. This option may result in controller lockup if the trigger is not de-activated. [1:0] read-only INTR_TYPE Specifies when a completion interrupt is generated (CH_STATUS.INTR_CAUSE is set to COMPLETION): '0': An interrupt is generated after a single transfer. '1': An interrupt is generated after a single 1D transfer or a memory copy transfer - If the descriptor type is 'single', the interrupt is generated after a single transfer. - If the descriptor type is '1D' or '2D', the interrupt is generated after the execution of a 1D transfer. - If the descriptor type is 'memory copy', the interrupt is generated after the execution of a memory copy transfer. - If the descriptor type is 'scatter' the interrupt is generated after the execution of a scatter transfer. '2': An interrupt is generated after the execution of the current descriptor (independent of the value of DESCR_NEXT_PTR.ADDR of the current descriptor). '3': An interrupt is generated after the execution of the current descriptor and the current descriptor's DESCR_NEXT_PTR.ADDR is '0'. [3:2] read-only TR_OUT_TYPE Specifies when an output trigger is generated: '0': An output trigger is generated after a single transfer. '1': An output trigger is generated after a single 1D transfer or a memory copy transfer. - If the descriptor type is 'single', the output trigger is generated after a single transfer. - If the descriptor type is '1D' or '2D', the output trigger is generated after the execution of a 1D transfer. - If the descriptor type is 'memory copy', the output trigger is generated after the execution of a memory copy transfer. - If the descriptor type is 'scatter', the output trigger is generated after the execution of a scatter transfer. '2': An output trigger is generated after the execution of the current descriptor. '3': An output trigger is generated after the execution of a descriptor list: after the execution of the current descriptor AND the current descriptor's DESCR_NEXT_PTR.ADDR is '0'. [5:4] read-only TR_IN_TYPE Specifies the input trigger type (not to be confused with the descriptor type): '0': A trigger results in the execution of a single transfer. The descriptor type can be single, 1D or 2D. '1': A trigger results in the execution of a single 1D transfer. - If the descriptor type is 'single', the trigger results in the execution of a single transfer. - If the descriptor type is '1D' or '2D', the trigger results in the execution of a 1D transfer. - If the descriptor type is 'memory copy', the trigger results in the execution of a memory copy transfer. - If the descriptor type is 'scatter', the trigger results in the execution of an scatter transfer. '2': A trigger results in the execution of the current descriptor. '3': A trigger results in the execution of the current descriptor and continues (without requiring another input trigger) with the execution of the next descriptor using the next descriptor's information. [7:6] read-only DATA_PREFETCH Source data prefetch: '0': No source data prefetch. Source data transfers are only initiated AFTER the input trigger is activated. '1': Source data prefetch. Source data transfers are initiated as soon as the channel is enabled, the current descriptor pointer is NOT '0' and there is space available in the channel's data FIFO. When the input trigger is activated, the trigger can initiate destination data transfers with data that is already in the channel's data FIFO. This effectively shortens the initial delay of the data transfer. Note: data prefetch should be used with care, to ensure that data coherency is guaranteed and that prefetches do not cause undesired side effects. [8:8] read-only DATA_SIZE Specifies the data element size: '0': Byte (8 bits). '1': Halfword (16 bits). '2': Word (32 bits). DATA_SIZE, SRC_TRANSFER_SIZE and DST_TRANSFER_SIZE together determine how data elements are transferred. The following are the 9 legal settings: - DATA is 8 bit, SRC is 8 bit, DST is 8 bit. - DATA is 8 bit, SRC is 32 bit (higher 24 bits are dropped), DST is 8 bit. - DATA is 8 bit, SRC is 8 bit, DST is 32 bit (higher 24 bits are made '0'). - DATA is 8 bit, SRC is 32 bit (higher 24 bits are dropped), DST is 32 bit (higher 24 bits are made '0'). - DATA is 16 bit, SRC is 16 bit, DST is 16 bit. - DATA is 16 bit, SRC is 32 bit (higher 16 bits are dropped), DST is 16 bit. - DATA is 16 bit, SRC is 16 bit, DST is 32 bit (higher 16 bits are made '0'). - DATA is 16 bit, SRC is 32 bit (higher 16 bits are dropped), DST is 32 bit (higher 16 bits are made '0'). - DATA is 32 bit, SRC is 32 bit, DST is 32 bit. Note: this field is not used for a 'memory copy' descriptor type. Note: this field must be set to '2' for a 'initialization' descriptor type. [17:16] read-only CH_DISABLE Specifies whether the channel is disabled or not after completion of the current descriptor (independent of the value of the DESCR_NEXT_PTR value): '0': Channel is not disabled. '1': Channel is disabled. [24:24] read-only SRC_TRANSFER_SIZE Specifies the bus transfer size to the source location: '0': As specified by DATA_SIZE. '1': Word (32 bits). Distinguishing bus transfer size from data element size allows for source components with data elements that are smaller than their 32-bit bus interface width. E.g., an ADC source has a 32-bit bus transfer size, but only provides a 16-bit data element. Note: this field is not used for a 'memory copy' descriptor type. Note: this field must be set to '1' for a 'scatter' descriptor type. [26:26] read-only DST_TRANSFER_SIZE Specifies the bus transfer size to the destination location: '0': As specified by DATA_SIZE. '1': Word (32 bits). Distinguishing bus transfer size from data element size allows for destination components with data elements that are smaller than their 32-bit bus interface width. E.g., a DAC destination has a 32-bit bus transfer size, but only requires a 16-bit data element. Note: this field is not used for a 'memory copy' descriptor type. Note: this field must be set to '1' for a 'scatter' descriptor type. [27:27] read-only DESCR_TYPE Specifies the descriptor type (not to be confused with the trigger type): '0': Single transfer. The DESCR_X_SIZE, DESCR_X_INCR, DESCR_Y_SIZE and DESCR_Y_INCR registers are NOT present. The DESCR_NEXT_PTR is at offset 0x0c. '1': 1D transfer. The DESCR_X_SIZE and DESCR_X_INCR registers are present, the DESCR_Y_SIZE and DESCR_Y_INCR are NOT present. A 1D transfer consists out of DESCR_X_SIZE.X_COUNT+1 single transfers. The DESCR_NEXT_PTR is at offset 0x14. '2': 2D transfer. The DESCR_X_SIZE, DESCR_X_INCR, DESCR_Y_SIZE and DESCR_Y_INCR registers are present. A 2D transfer consists of (DESCR_X_SIZE.X_COUNT+1)*(DESCR_Y_SIZE.Y_COUNT+1) single transfers. The DESCR_NEXT_PTR is at offset 0x1c. '3': Memory copy. The DESCR_X_SIZE register is present, the DESCR_X_INCR, DESCR_Y_SIZE and DESCR_Y_INCR are NOT present. A memory copy transfer copies DESCR_X_SIZE.X_COUNT+1 Bytes and may use Byte, halfword and word transfers. The DESCR_NEXT_PTR is at offset 0x10. '4': Scatter transfer. The DESCR_X_SIZE register is present, the DESCR_DST, DESCR_X_INCR, DESCR_Y_SIZE and DESCR_Y_INCR are NOT present. '5'-'7': Undefined. After the execution of the current descriptor, the DESCR_NEXT_PTR address is copied to the channel's CH_CURR_PTR address and CH_STATUS.X_IDX and CH_STATUS.Y_IDX are set to '0'. [30:28] read-only DESCR_SRC Channel descriptor source 0x64 32 read-only 0x0 0x0 ADDR Base address of source location. [31:0] read-only DESCR_DST Channel descriptor destination 0x68 32 read-only 0x0 0x0 ADDR Base address of destination location. [31:0] read-only DESCR_X_SIZE Channel descriptor X size 0x6C 32 read-only 0x0 0x0 X_COUNT Number of iterations (minus 1) of the 'X loop' (X_COUNT+1 is the number of single transfers in a 1D transfer). This field is an unsigned number in the range [0, 65535], representing 1 through 65536 iterations. For the 'memory copy' descriptor type, (X_COUNT + 1) is the number of transferred Bytes. For the 'scatter' descriptor type, ceiling(X_COUNT/2) is the number of (address, write data) initialization pairs processed. [15:0] read-only DESCR_X_INCR Channel descriptor X increment 0x70 32 read-only 0x0 0x0 SRC_X Specifies increment of source address for each X loop iteration (in multiples of SRC_TRANSFER_SIZE). This field is a signed number (sign-magnitude format) in the range [-32768, 32767]. If this field is '0', the source address is not incremented. This is useful for reading from RX FIFO structures. [15:0] read-only DST_X Specifies increment of destination address for each X loop iteration (in multiples of DST_TRANSFER_SIZE). This field is a signed number (sign-magnitude format) in the range [-32768, 32767]. If this field is '0', the destination address is not incremented. This is useful for writing to TX FIFO structures. [31:16] read-only DESCR_Y_SIZE Channel descriptor Y size 0x74 32 read-only 0x0 0x0 Y_COUNT Number of iterations (minus 1) of the 'Y loop' (X_COUNT+1)*(Y_COUNT+1) is the number of single transfers in a 2D transfer). This field is an unsigned number in the range [0, 65535], representing 1 through 65536 iterations. [15:0] read-only DESCR_Y_INCR Channel descriptor Y increment 0x78 32 read-only 0x0 0x0 SRC_Y Specifies increment of source address for each Y loop iteration (in multiples of SRC_TRANSFER_SIZE). This field is a signed number in the range [-32768, 32767]. [15:0] read-only DST_Y Specifies increment of destination address for each Y loop iteration (in multiples of DST_TRANSFER_SIZE). This field is a signed number in the range [-32768, 32767]. [31:16] read-only DESCR_NEXT Channel descriptor next pointer 0x7C 32 read-only 0x0 0x0 PTR Address of next descriptor in descriptor list. When this field is '0', this is the last descriptor in the descriptor list. [31:2] read-only INTR Interrupt 0x80 32 read-write 0x0 0xFF COMPLETION Activated (set to '1') on completion of data transfer(s) as specified by the descriptor's CH_DESCR_CTL.INTR_TYPE. [0:0] read-write SRC_BUS_ERROR Activated (set to '1') on a bus error for a load from the source. [1:1] read-write DST_BUS_ERROR Activated (set to '1') on a bus error for a store to the destination. [2:2] read-write SRC_MISAL Activated (set to '1') on a misalignment of the source address. [3:3] read-write DST_MISAL Activated (set to '1') on a misalignment of the destination address. [4:4] read-write CURR_PTR_NULL Activated (set to '1') when the channel is enabled (CH_CTL.ENABLED is '1') and CH_CURR_PTR is '0'. [5:5] read-write ACTIVE_CH_DISABLED Activated (set to '1') if the channel is disabled by SW (accidentally/incorrectly) when the data transfer engine is busy. [6:6] read-write DESCR_BUS_ERROR Activated (set to '1') on a bus error for a load of the descriptor. [7:7] read-write INTR_SET Interrupt set 0x84 32 read-write 0x0 0xFF COMPLETION Write this field with '1' to set INTR.COMPLETION field to '1' (a write of '0' has no effect). [0:0] read-write SRC_BUS_ERROR Write this field with '1' to set INTR.SRC_BUS_ERROR field to '1' (a write of '0' has no effect). [1:1] read-write DST_BUS_ERROR Write this field with '1' to set INTR.DST_BUS_ERROR field to '1' (a write of '0' has no effect). [2:2] read-write SRC_MISAL Write this field with '1' to set INTR.SRC_MISAL field to '1' (a write of '0' has no effect). [3:3] read-write DST_MISAL Write this field with '1' to set INTR.DST_MISAL field to '1' (a write of '0' has no effect). [4:4] read-write CURR_PTR_NULL Write this field with '1' to set INTR.CURR_PTR_NULL field to '1' (a write of '0' has no effect). [5:5] read-write ACTIVE_CH_DISABLED Write this field with '1' to set INTR.ACT_CH_DISABLED field to '1' (a write of '0' has no effect). [6:6] read-write DESCR_BUS_ERROR Write this field with '1' to set INTR.DESCR_BUS_ERROR field to '1' (a write of '0' has no effect). [7:7] read-write INTR_MASK Interrupt mask 0x88 32 read-write 0x0 0xFF COMPLETION Mask for INTR.COMPLETION interrupt. [0:0] read-write SRC_BUS_ERROR Mask for INTR.SRC_BUS_ERROR interrupt. [1:1] read-write DST_BUS_ERROR Mask for INTR.DST_BUS_ERROR interrupt. [2:2] read-write SRC_MISAL Mask for INTR.SRC_MISAL interrupt. [3:3] read-write DST_MISAL Mask for INTR.DST_MISAL interrupt. [4:4] read-write CURR_PTR_NULL Mask for INTR.CURR_PTR_NULL interrupt. [5:5] read-write ACTIVE_CH_DISABLED Mask for INTR.ACTIVE_CH_DISABLED interrupt. [6:6] read-write DESCR_BUS_ERROR Mask for INTR.DESCR_BUS_ERROR interrupt. [7:7] read-write INTR_MASKED Interrupt masked 0x8C 32 read-only 0x0 0xFF COMPLETION Logical and of corresponding INTR.COMPLETION and INTR_MASK.COMPLETION fields. [0:0] read-only SRC_BUS_ERROR Logical and of corresponding INTR.SRC_BUS_ERROR and INTR_MASK.SRC_BUS_ERROR fields. [1:1] read-only DST_BUS_ERROR Logical and of corresponding INTR.DST_BUS_ERROR and INTR_MASK.DST_BUS_ERROR fields. [2:2] read-only SRC_MISAL Logical and of corresponding INTR.SRC_MISAL and INTR_MASK.SRC_MISAL fields. [3:3] read-only DST_MISAL Logical and of corresponding INTR.DST_MISAL and INTR_MASK.DST_MISAL fields. [4:4] read-only CURR_PTR_NULL Logical and of corresponding INTR.CURR_PTR_NULL and INTR_MASK.CURR_PTR_NULL fields. [5:5] read-only ACTIVE_CH_DISABLED Logical and of corresponding INTR.ACTIVE_CH_DISABLED and INTR_MASK.ACTIVE_CH_DISABLED fields. [6:6] read-only DESCR_BUS_ERROR Logical and of corresponding INTR.DESCR_BUS_ERROR and INTR_MASK.DESCR_BUS_ERROR fields. [7:7] read-only EFUSE EFUSE MXS40 registers 0x402C0000 0 128 registers CTL Control 0x0 32 read-write 0x0 0x80000000 ENABLED IP enable: '0': Disabled. All non-retention registers (command and status registers) are reset to their default value when the IP is disabled. All retention registers retain their value when the IP is disabled. '1': Enabled. [31:31] read-write CMD Command 0x10 32 read-write 0x1 0x800F1F71 BIT_DATA Bit data. This field specifies the bit value that is to be programmed into the eFUSE macro array. The address of the bit is specified by the BIT_ADDR, BYTE_ADDR, and MACRO_ADDR fields. This bit is a don't care for the MXS40 Macro. [0:0] read-write BIT_ADDR Bit address. This field specifies a bit within a Byte. [6:4] read-write BYTE_ADDR Byte address. This field specifies a Byte within a eFUSE macro (each macro has 32 B). [12:8] read-write MACRO_ADDR Macro address. This field specifies an eFUSE macro. [19:16] read-write START FW sets this field to '1' to start a program operation. HW sets this field to '0' to indicate that the operation has completed. Note: it is good practice to verify the result of a program operation by reading back a programmed eFUSE memory location. Programming can only change an eFUSE memory bit from '0' to '1'; i.e. a programming operation is a 'one-off' operation for each eFUSE memory bit: once a bit is changed to '1', it can NEVER be changed back to '0' as a hardware fuse is blown. Programming a memory bit to '1' requires blowing a fuse and requires an eFUSE macro operation. Therefore, this programmiong operation takes time (as specified by the SEQ_PROGRAM_CTL reguisters). Programming amemory bit to '0' does not require an eFUSE macro operation (it is the default eFUSE macro state). Therefore, this programming operation is almost instantaneous. Note: during a program operation, a read operation can not be performed. An AHB-Lite read transfer to the eFUSE memory during a program operation results in an AHB-Lite bus error. [31:31] read-write SEQ_DEFAULT Sequencer Default value 0x20 32 read-write 0x1D0000 0x7F0000 STROBE_A Specifies value of eFUSE control signal strobe_f [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write SEQ_READ_CTL_0 Sequencer read control 0 0x40 32 read-write 0x80560001 0x807F03FF CYCLES Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. [9:0] read-write STROBE_A Specifies value of eFUSE control signal strobe_f [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write DONE When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. [31:31] read-write SEQ_READ_CTL_1 Sequencer read control 1 0x44 32 read-write 0x540004 0x807F03FF CYCLES Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. [9:0] read-write STROBE_A Specifies value of eFUSE control signal strobe_f [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write DONE When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. [31:31] read-write SEQ_READ_CTL_2 Sequencer read control 2 0x48 32 read-write 0x560001 0x807F03FF CYCLES Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. [9:0] read-write STROBE_A Specifies value of eFUSE control signal strobe_f [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write DONE When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. [31:31] read-write SEQ_READ_CTL_3 Sequencer read control 3 0x4C 32 read-write 0x540003 0x807F03FF CYCLES Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. [9:0] read-write STROBE_A Specifies value of eFUSE control signal strobe_f [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write DONE When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. [31:31] read-write SEQ_READ_CTL_4 Sequencer read control 4 0x50 32 read-write 0x80150001 0x807F03FF CYCLES Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. [9:0] read-write STROBE_A Specifies value of eFUSE control signal strobe_f [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write DONE When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. [31:31] read-write SEQ_READ_CTL_5 Sequencer read control 5 0x54 32 read-write 0x310004 0x807F03FF CYCLES Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. [9:0] read-write STROBE_A Specifies value of eFUSE control signal strobe_f [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write DONE When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. [31:31] read-write SEQ_PROGRAM_CTL_0 Sequencer program control 0 0x60 32 read-write 0x200001 0x807F03FF CYCLES Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. [9:0] read-write STROBE_A Specifies value of eFUSE control signal strobe_a [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write DONE When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. [31:31] read-write SEQ_PROGRAM_CTL_1 Sequencer program control 1 0x64 32 read-write 0x220020 0x807F03FF CYCLES Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. [9:0] read-write STROBE_A Specifies value of eFUSE control signal strobe_a [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write DONE When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. [31:31] read-write SEQ_PROGRAM_CTL_2 Sequencer program control 2 0x68 32 read-write 0x200001 0x807F03FF CYCLES Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. [9:0] read-write STROBE_A Specifies value of eFUSE control signal strobe_a [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write DONE When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. [31:31] read-write SEQ_PROGRAM_CTL_3 Sequencer program control 3 0x6C 32 read-write 0x310005 0x807F03FF CYCLES Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. [9:0] read-write STROBE_A Specifies value of eFUSE control signal strobe_a [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write DONE When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. [31:31] read-write SEQ_PROGRAM_CTL_4 Sequencer program control 4 0x70 32 read-write 0x80350006 0x807F03FF CYCLES Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. [9:0] read-write STROBE_A Specifies value of eFUSE control signal strobe_a [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write DONE When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. [31:31] read-write SEQ_PROGRAM_CTL_5 Sequencer program control 5 0x74 32 read-write 0x803D0019 0x807F03FF CYCLES Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. [9:0] read-write STROBE_A Specifies value of eFUSE control signal strobe_a [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write DONE When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. [31:31] read-write HSIOM High Speed IO Matrix (HSIOM) 0x40300000 0 16384 registers 14 16 PRT[%s] HSIOM port registers 0x00000000 PORT_SEL0 Port selection 0 0x0 32 read-write 0x0 0x1F1F1F1F IO0_SEL Selects connection for IO pin 0 route. [4:0] read-write GPIO GPIO controls 'out' 0 GPIO_DSI GPIO controls 'out', DSI controls 'output enable' 1 DSI_DSI DSI controls 'out' and 'output enable' 2 DSI_GPIO DSI controls 'out', GPIO controls 'output enable' 3 AMUXA Analog mux bus A 4 AMUXB Analog mux bus B 5 AMUXA_DSI Analog mux bus A, DSI control 6 AMUXB_DSI Analog mux bus B, DSI control 7 ACT_0 Active functionality 0 8 ACT_1 Active functionality 1 9 ACT_2 Active functionality 2 10 ACT_3 Active functionality 3 11 DS_0 DeepSleep functionality 0 12 DS_1 DeepSleep functionality 1 13 DS_2 DeepSleep functionality 2 14 DS_3 DeepSleep functionality 3 15 ACT_4 Active functionality 4 16 ACT_5 Active functionality 5 17 ACT_6 Active functionality 6 18 ACT_7 Active functionality 7 19 ACT_8 Active functionality 8 20 ACT_9 Active functionality 9 21 ACT_10 Active functionality 10 22 ACT_11 Active functionality 11 23 ACT_12 Active functionality 12 24 ACT_13 Active functionality 13 25 ACT_14 Active functionality 14 26 ACT_15 Active functionality 15 27 DS_4 DeepSleep functionality 4 28 DS_5 DeepSleep functionality 5 29 DS_6 DeepSleep functionality 6 30 DS_7 DeepSleep functionality 7 31 IO1_SEL Selects connection for IO pin 1 route. [12:8] read-write IO2_SEL Selects connection for IO pin 2 route. [20:16] read-write IO3_SEL Selects connection for IO pin 3 route. [28:24] read-write PORT_SEL1 Port selection 1 0x4 32 read-write 0x0 0x1F1F1F1F IO4_SEL Selects connection for IO pin 4 route. See PORT_SEL0 for connection details. [4:0] read-write IO5_SEL Selects connection for IO pin 5 route. [12:8] read-write IO6_SEL Selects connection for IO pin 6 route. [20:16] read-write IO7_SEL Selects connection for IO pin 7 route. [28:24] read-write 64 4 AMUX_SPLIT_CTL[%s] AMUX splitter cell control 0x2000 32 read-write 0x0 0x77 SWITCH_AA_SL T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed. [0:0] read-write SWITCH_AA_SR T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed. [1:1] read-write SWITCH_AA_S0 T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed. [2:2] read-write SWITCH_BB_SL T-switch control for Left AMUXBUSB switch. [4:4] read-write SWITCH_BB_SR T-switch control for Right AMUXBUSB switch. [5:5] read-write SWITCH_BB_S0 T-switch control for AMUXBUSB vssa/ground switch. [6:6] read-write MONITOR_CTL_0 Power/Ground Monitor cell control 0 0x2200 32 read-write 0x0 0xFFFFFFFF MONITOR_EN control for switch, which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed: '0': switch open. '1': switch closed. [31:0] read-write MONITOR_CTL_1 Power/Ground Monitor cell control 1 0x2204 32 read-write 0x0 0xFFFFFFFF MONITOR_EN control for switch, which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed: '0': switch open. '1': switch closed. [31:0] read-write MONITOR_CTL_2 Power/Ground Monitor cell control 2 0x2208 32 read-write 0x0 0xFFFFFFFF MONITOR_EN control for switch, which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed: '0': switch open. '1': switch closed. [31:0] read-write MONITOR_CTL_3 Power/Ground Monitor cell control 3 0x220C 32 read-write 0x0 0xFFFFFFFF MONITOR_EN control for switch, which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed: '0': switch open. '1': switch closed. [31:0] read-write ALT_JTAG_EN Alternate JTAG IF selection register 0x2240 32 read-write 0x0 0x80000000 ENABLE Provides the selection for alternate JTAG IF connectivity. 0: Primary JTAG interface is selected 1: Secondary (alternate) JTAG interface is selected. This connectivity works ONLY in ACTIVE mode. [31:31] read-write GPIO GPIO port control/configuration 0x40310000 0 65536 registers 14 128 PRT[%s] GPIO port registers 0x00000000 OUT Port output data register 0x0 32 read-write 0x0 0xFF OUT0 IO output data for pin 0 '0': Output state set to '0' '1': Output state set to '1' [0:0] read-write OUT1 IO output data for pin 1 [1:1] read-write OUT2 IO output data for pin 2 [2:2] read-write OUT3 IO output data for pin 3 [3:3] read-write OUT4 IO output data for pin 4 [4:4] read-write OUT5 IO output data for pin 5 [5:5] read-write OUT6 IO output data for pin 6 [6:6] read-write OUT7 IO output data for pin 7 [7:7] read-write OUT_CLR Port output data clear register 0x4 32 read-write 0x0 0xFF OUT0 IO clear output for pin 0: '0': Output state not affected. '1': Output state set to '0'. [0:0] read-write OUT1 IO clear output for pin 1 [1:1] read-write OUT2 IO clear output for pin 2 [2:2] read-write OUT3 IO clear output for pin 3 [3:3] read-write OUT4 IO clear output for pin 4 [4:4] read-write OUT5 IO clear output for pin 5 [5:5] read-write OUT6 IO clear output for pin 6 [6:6] read-write OUT7 IO clear output for pin 7 [7:7] read-write OUT_SET Port output data set register 0x8 32 read-write 0x0 0xFF OUT0 IO set output for pin 0: '0': Output state not affected. '1': Output state set to '1'. [0:0] read-write OUT1 IO set output for pin 1 [1:1] read-write OUT2 IO set output for pin 2 [2:2] read-write OUT3 IO set output for pin 3 [3:3] read-write OUT4 IO set output for pin 4 [4:4] read-write OUT5 IO set output for pin 5 [5:5] read-write OUT6 IO set output for pin 6 [6:6] read-write OUT7 IO set output for pin 7 [7:7] read-write OUT_INV Port output data invert register 0xC 32 read-write 0x0 0xFF OUT0 IO invert output for pin 0: '0': Output state not affected. '1': Output state inverted ('0' => '1', '1' => '0'). [0:0] read-write OUT1 IO invert output for pin 1 [1:1] read-write OUT2 IO invert output for pin 2 [2:2] read-write OUT3 IO invert output for pin 3 [3:3] read-write OUT4 IO invert output for pin 4 [4:4] read-write OUT5 IO invert output for pin 5 [5:5] read-write OUT6 IO invert output for pin 6 [6:6] read-write OUT7 IO invert output for pin 7 [7:7] read-write IN Port input state register 0x10 32 read-only 0x0 0x1FF IN0 IO pin state for pin 0 '0': Low logic level present on pin. '1': High logic level present on pin. On reset assertion , IN register will get reset. The Pad value takes 2 clock cycles to be reflected into IN Register. It's value then depends on the external pin value. [0:0] read-only IN1 IO pin state for pin 1 [1:1] read-only IN2 IO pin state for pin 2 [2:2] read-only IN3 IO pin state for pin 3 [3:3] read-only IN4 IO pin state for pin 4 [4:4] read-only IN5 IO pin state for pin 5 [5:5] read-only IN6 IO pin state for pin 6 [6:6] read-only IN7 IO pin state for pin 7 [7:7] read-only FLT_IN Reads of this register return the logical state of the filtered pin as selected in the INTR_CFG.FLT_SEL register. [8:8] read-only INTR Port interrupt status register 0x14 32 read-write 0x0 0x1FF01FF EDGE0 Edge detect for IO pin 0 '0': No edge was detected on pin. '1': An edge was detected on pin. [0:0] read-write EDGE1 Edge detect for IO pin 1 [1:1] read-write EDGE2 Edge detect for IO pin 2 [2:2] read-write EDGE3 Edge detect for IO pin 3 [3:3] read-write EDGE4 Edge detect for IO pin 4 [4:4] read-write EDGE5 Edge detect for IO pin 5 [5:5] read-write EDGE6 Edge detect for IO pin 6 [6:6] read-write EDGE7 Edge detect for IO pin 7 [7:7] read-write FLT_EDGE Edge detected on filtered pin selected by INTR_CFG.FLT_SEL [8:8] read-write IN_IN0 IO pin state for pin 0 [16:16] read-only IN_IN1 IO pin state for pin 1 [17:17] read-only IN_IN2 IO pin state for pin 2 [18:18] read-only IN_IN3 IO pin state for pin 3 [19:19] read-only IN_IN4 IO pin state for pin 4 [20:20] read-only IN_IN5 IO pin state for pin 5 [21:21] read-only IN_IN6 IO pin state for pin 6 [22:22] read-only IN_IN7 IO pin state for pin 7 [23:23] read-only FLT_IN_IN Filtered pin state for pin selected by INTR_CFG.FLT_SEL [24:24] read-only INTR_MASK Port interrupt mask register 0x18 32 read-write 0x0 0x1FF EDGE0 Masks edge interrupt on IO pin 0 '0': Pin interrupt forwarding disabled '1': Pin interrupt forwarding enabled [0:0] read-write EDGE1 Masks edge interrupt on IO pin 1 [1:1] read-write EDGE2 Masks edge interrupt on IO pin 2 [2:2] read-write EDGE3 Masks edge interrupt on IO pin 3 [3:3] read-write EDGE4 Masks edge interrupt on IO pin 4 [4:4] read-write EDGE5 Masks edge interrupt on IO pin 5 [5:5] read-write EDGE6 Masks edge interrupt on IO pin 6 [6:6] read-write EDGE7 Masks edge interrupt on IO pin 7 [7:7] read-write FLT_EDGE Masks edge interrupt on filtered pin selected by INTR_CFG.FLT_SEL [8:8] read-write INTR_MASKED Port interrupt masked status register 0x1C 32 read-only 0x0 0x1FF EDGE0 Edge detected AND masked on IO pin 0 '0': Interrupt was not forwarded to CPU '1': Interrupt occurred and was forwarded to CPU [0:0] read-only EDGE1 Edge detected and masked on IO pin 1 [1:1] read-only EDGE2 Edge detected and masked on IO pin 2 [2:2] read-only EDGE3 Edge detected and masked on IO pin 3 [3:3] read-only EDGE4 Edge detected and masked on IO pin 4 [4:4] read-only EDGE5 Edge detected and masked on IO pin 5 [5:5] read-only EDGE6 Edge detected and masked on IO pin 6 [6:6] read-only EDGE7 Edge detected and masked on IO pin 7 [7:7] read-only FLT_EDGE Edge detected and masked on filtered pin selected by INTR_CFG.FLT_SEL [8:8] read-only INTR_SET Port interrupt set register 0x20 32 read-write 0x0 0x1FF EDGE0 Sets edge detect interrupt for IO pin 0 '0': Interrupt state not affected '1': Interrupt set [0:0] read-write EDGE1 Sets edge detect interrupt for IO pin 1 [1:1] read-write EDGE2 Sets edge detect interrupt for IO pin 2 [2:2] read-write EDGE3 Sets edge detect interrupt for IO pin 3 [3:3] read-write EDGE4 Sets edge detect interrupt for IO pin 4 [4:4] read-write EDGE5 Sets edge detect interrupt for IO pin 5 [5:5] read-write EDGE6 Sets edge detect interrupt for IO pin 6 [6:6] read-write EDGE7 Sets edge detect interrupt for IO pin 7 [7:7] read-write FLT_EDGE Sets edge detect interrupt for filtered pin selected by INTR_CFG.FLT_SEL [8:8] read-write INTR_CFG Port interrupt configuration register 0x40 32 read-write 0x0 0x1FFFFF EDGE0_SEL Sets which edge will trigger an IRQ for IO pin 0 [1:0] read-write DISABLE Disabled 0 RISING Rising edge 1 FALLING Falling edge 2 BOTH Both rising and falling edges 3 EDGE1_SEL Sets which edge will trigger an IRQ for IO pin 1 [3:2] read-write EDGE2_SEL Sets which edge will trigger an IRQ for IO pin 2 [5:4] read-write EDGE3_SEL Sets which edge will trigger an IRQ for IO pin 3 [7:6] read-write EDGE4_SEL Sets which edge will trigger an IRQ for IO pin 4 [9:8] read-write EDGE5_SEL Sets which edge will trigger an IRQ for IO pin 5 [11:10] read-write EDGE6_SEL Sets which edge will trigger an IRQ for IO pin 6 [13:12] read-write EDGE7_SEL Sets which edge will trigger an IRQ for IO pin 7 [15:14] read-write FLT_EDGE_SEL Sets which edge will trigger an IRQ for the glitch filtered pin (selected by INTR_CFG.FLT_SEL [17:16] read-write DISABLE Disabled 0 RISING Rising edge 1 FALLING Falling edge 2 BOTH Both rising and falling edges 3 FLT_SEL Selects which pin is routed through the 50ns glitch filter to provide a glitch-safe interrupt. [20:18] read-write CFG Port configuration register 0x44 32 read-write 0x0 0xFFFFFFFF DRIVE_MODE0 The GPIO drive mode for IO pin 0. Resistive pull-up and pull-down is selected in the drive mode. Note: when initializing IO's that are connected to a live bus (such as I2C), make sure the peripheral and HSIOM (HSIOM_PRT_SELx) is properly configured before turning the IO on here to avoid producing glitches on the bus. Note: that peripherals other than GPIO & UDB/DSI directly control both the output and output-enable of the output buffer (peripherals can drive strong 0 or strong 1 in any mode except OFF='0'). Note: D_OUT, D_OUT_EN are pins of GPIO cell. [2:0] read-write HIGHZ Output buffer is off creating a high impedance input D_OUT = '0': High Impedance D_OUT = '1': High Impedance 0 RSVD N/A 1 PULLUP Resistive pull up For GPIO & UDB/DSI peripherals: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Weak/resistive pull up When D_OUT_EN = 0: D_OUT = '0': High impedance D_OUT = '1': High impedance For peripherals other than GPIO & UDB/DSI: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': Weak/resistive pull up D_OUT = '1': Weak/resistive pull up 2 PULLDOWN Resistive pull down For GPIO & UDB/DSI peripherals: When D_OUT_EN = 1: D_OUT = '0': Weak/resistive pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': High impedance D_OUT = '1': High impedance For peripherals other than GPIO & UDB/DSI: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': Weak/resistive pull down D_OUT = '1': Weak/resistive pull down 3 OD_DRIVESLOW Open drain, drives low For GPIO & UDB/DSI peripherals: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': High Impedance When D_OUT_EN = 0: D_OUT = '0': High impedance D_OUT = '1': High impedance For peripherals other than GPIO & UDB/DSI: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': High Impedance D_OUT = '1': High Impedance 4 OD_DRIVESHIGH Open drain, drives high For GPIO & UDB/DSI peripherals: When D_OUT_EN = 1: D_OUT = '0': High Impedance D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': High impedance D_OUT = '1': High impedance For peripherals other than GPIO & UDB/DSI: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': High Impedance D_OUT = '1': High Impedance 5 STRONG Strong D_OUTput buffer For GPIO & UDB/DSI peripherals: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': High impedance D_OUT = '1': High impedance For peripherals other than GPIO & UDB/DSI: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': High Impedance D_OUT = '1': High Impedance 6 PULLUP_DOWN Pull up or pull down For GPIO & UDB/DSI peripherals: When D_OUT_EN = '0': GPIO_DSI_OUT = '0': Weak/resistive pull down GPIO_DSI_OUT = '1': Weak/resistive pull up where 'GPIO_DSI_OUT' is a function of PORT_SEL, OUT & DSI_DATA_OUT. For peripherals other than GPIO & UDB/DSI: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': Weak/resistive pull down D_OUT = '1': Weak/resistive pull up 7 IN_EN0 Enables the input buffer for IO pin 0. This bit should be cleared when analog signals are present on the pin to avoid crowbar currents. The output buffer can be used to drive analog signals high or low without issue. '0': Input buffer disabled '1': Input buffer enabled [3:3] read-write DRIVE_MODE1 The GPIO drive mode for IO pin 1 [6:4] read-write IN_EN1 Enables the input buffer for IO pin 1 [7:7] read-write DRIVE_MODE2 The GPIO drive mode for IO pin 2 [10:8] read-write IN_EN2 Enables the input buffer for IO pin 2 [11:11] read-write DRIVE_MODE3 The GPIO drive mode for IO pin 3 [14:12] read-write IN_EN3 Enables the input buffer for IO pin 3 [15:15] read-write DRIVE_MODE4 The GPIO drive mode for IO pin4 [18:16] read-write IN_EN4 Enables the input buffer for IO pin 4 [19:19] read-write DRIVE_MODE5 The GPIO drive mode for IO pin 5 [22:20] read-write IN_EN5 Enables the input buffer for IO pin 5 [23:23] read-write DRIVE_MODE6 The GPIO drive mode for IO pin 6 [26:24] read-write IN_EN6 Enables the input buffer for IO pin 6 [27:27] read-write DRIVE_MODE7 The GPIO drive mode for IO pin 7 [30:28] read-write IN_EN7 Enables the input buffer for IO pin 7 [31:31] read-write CFG_IN Port input buffer configuration register 0x48 32 read-write 0x0 0xFF VTRIP_SEL0_0 Configures the pin 0 input buffer mode (trip points and hysteresis) [0:0] read-write CMOS S40S: Input buffer compatible with CMOS and I2C interfaces 0 TTL S40S: Input buffer compatible with TTL and MediaLB interfaces 1 VTRIP_SEL1_0 Configures the pin 1 input buffer mode (trip points and hysteresis) [1:1] read-write VTRIP_SEL2_0 Configures the pin 2 input buffer mode (trip points and hysteresis) [2:2] read-write VTRIP_SEL3_0 Configures the pin 3 input buffer mode (trip points and hysteresis) [3:3] read-write VTRIP_SEL4_0 Configures the pin 4 input buffer mode (trip points and hysteresis) [4:4] read-write VTRIP_SEL5_0 Configures the pin 5 input buffer mode (trip points and hysteresis) [5:5] read-write VTRIP_SEL6_0 Configures the pin 6 input buffer mode (trip points and hysteresis) [6:6] read-write VTRIP_SEL7_0 Configures the pin 7 input buffer mode (trip points and hysteresis) [7:7] read-write CFG_OUT Port output buffer configuration register 0x4C 32 read-write 0x0 0xFFFF00FF SLOW0 Enables slow slew rate for IO pin 0 '0': Fast slew rate '1': Slow slew rate [0:0] read-write SLOW1 Enables slow slew rate for IO pin 1 [1:1] read-write SLOW2 Enables slow slew rate for IO pin 2 [2:2] read-write SLOW3 Enables slow slew rate for IO pin 3 [3:3] read-write SLOW4 Enables slow slew rate for IO pin 4 [4:4] read-write SLOW5 Enables slow slew rate for IO pin 5 [5:5] read-write SLOW6 Enables slow slew rate for IO pin 6 [6:6] read-write SLOW7 Enables slow slew rate for IO pin 7 [7:7] read-write DRIVE_SEL0 Sets the GPIO drive strength for IO pin 0 [17:16] read-write DRIVE_SEL_ZERO N/A 0 DRIVE_SEL_ONE N/A 1 DRIVE_SEL_TWO N/A 2 DRIVE_SEL_THREE N/A 3 DRIVE_SEL1 Sets the GPIO drive strength for IO pin 1 [19:18] read-write DRIVE_SEL2 Sets the GPIO drive strength for IO pin 2 [21:20] read-write DRIVE_SEL3 Sets the GPIO drive strength for IO pin 3 [23:22] read-write DRIVE_SEL4 Sets the GPIO drive strength for IO pin 4 [25:24] read-write DRIVE_SEL5 Sets the GPIO drive strength for IO pin 5 [27:26] read-write DRIVE_SEL6 Sets the GPIO drive strength for IO pin 6 [29:28] read-write DRIVE_SEL7 Sets the GPIO drive strength for IO pin 7 [31:30] read-write CFG_SIO Port SIO configuration register 0x50 32 read-write 0x0 0xFFFFFFFF VREG_EN01 Selects the output buffer mode: '0': Unregulated output buffer '1': Regulated output buffer The regulated output mode is selected ONLY if the CFG.DRIVE_MODE bits are set to the strong pull up (Z_1 = '5') mode. If the CFG.DRIVE_MODE bits are set to any other mode the regulated output buffer will be disabled and the standard CMOS output buffer is used. [0:0] read-write IBUF_SEL01 Selects the input buffer mode: 0: Singled ended input buffer 1: Differential input buffer [1:1] read-write VTRIP_SEL01 Selects the input buffer trip-point in single ended input buffer mode (IBUF_SEL = '0'): '0': Input buffer functions as a CMOS input buffer. '1': Input buffer functions as a TTL input buffer. In differential input buffer mode (IBUF_SEL = '1') '0': Trip-point is 0.5*Vddio or 0.5*Voh (depends on VREF_SEL/VOH_SEL) '1': Trip-point is 0.4*Vddio or 1.0*Vref (depends on VREF_SEL) [2:2] read-write VREF_SEL01 Selects reference voltage (Vref) trip-point of the input buffer: '0': Trip-point reference from pin_ref '1': Trip-point reference of SRSS internal reference Vref (1.2 V) '2': Trip-point reference of AMUXBUS_A '3': Trip-point reference of AMUXBUS_B [4:3] read-write VOH_SEL01 Selects the regulated Voh output level and trip point of the input buffer for a specific SIO pin pair. Voh depends on the selected reference voltage (VREF_SEL). '0': Voh = 1*reference; e.g. reference at 1.2V -> Voh = 1.2V '1': Voh = 1.25*reference; e.g. reference at 1.2V -> Voh = 1.5V '2': Voh = 1.49*reference; e.g. reference at 1.2V -> Voh = ~1.8V '3': Voh = 1.67*reference; e.g. reference at 1.2V -> Voh = 2V '4': Voh = 2.08*reference; e.g. reference at 1.2V -> Voh = 2.5V '5': Voh = 2.5*reference; e.g. reference at 1.2V -> Voh = 3V '6': Voh = 2.78*reference; e.g. reference at 1.2V -> Voh = ~3.3V '7': Voh = 4.16*reference; e.g. reference at 1.2V -> Voh = 5.0V Note: The upper value on Voh is limited to Vddio - 400mV [7:5] read-write VREG_EN23 See corresponding definition for IO pins 0 and 1 [8:8] read-write IBUF_SEL23 See corresponding definition for IO pins 0 and 1 [9:9] read-write VTRIP_SEL23 See corresponding definition for IO pins 0 and 1 [10:10] read-write VREF_SEL23 See corresponding definition for IO pins 0 and 1 [12:11] read-write VOH_SEL23 See corresponding definition for IO pins 0 and 1 [15:13] read-write VREG_EN45 See corresponding definition for IO pins 0 and 1 [16:16] read-write IBUF_SEL45 See corresponding definition for IO pins 0 and 1 [17:17] read-write VTRIP_SEL45 See corresponding definition for IO pins 0 and 1 [18:18] read-write VREF_SEL45 See corresponding definition for IO pins 0 and 1 [20:19] read-write VOH_SEL45 See corresponding definition for IO pins 0 and 1 [23:21] read-write VREG_EN67 See corresponding definition for IO pins 0 and 1 [24:24] read-write IBUF_SEL67 See corresponding definition for IO pins 0 and 1 [25:25] read-write VTRIP_SEL67 See corresponding definition for IO pins 0 and 1 [26:26] read-write VREF_SEL67 See corresponding definition for IO pins 0 and 1 [28:27] read-write VOH_SEL67 See corresponding definition for IO pins 0 and 1 [31:29] read-write CFG_IN_AUTOLVL Port input buffer AUTOLVL configuration register 0x58 32 read-write 0x0 0xFF VTRIP_SEL0_1 Configures the input buffer mode (trip points and hysteresis) for GPIO upper bit. Lower bit is still selected by CFG_IN.VTRIP_SEL0_0 field. This field is used along with CFG_IN.VTRIP_SEL0_0 field as below: {CFG_IN_AUTOLVL.VTRIP_SEL0_1,CFG_IN.VTRIP_SEL0_0}: 0,0: CMOS 0,1: TTL 1,0: input buffer is compatible with automotive. 1,1: input buffer is compatible with automotive. [0:0] read-write CMOS_OR_TTL Input buffer compatible with CMOS/TTL interfaces as described in CFG_IN.VTRIP_SEL0_0. 0 AUTO Input buffer compatible with AUTO (elevated Vil) interfaces when used along with CFG_IN.VTRIP_SEL0_0. 1 VTRIP_SEL1_1 Input buffer compatible with automotive (elevated Vil) interfaces. [1:1] read-write VTRIP_SEL2_1 Input buffer compatible with automotive (elevated Vil) interfaces. [2:2] read-write VTRIP_SEL3_1 Input buffer compatible with automotive (elevated Vil) interfaces. [3:3] read-write VTRIP_SEL4_1 Input buffer compatible with automotive (elevated Vil) interfaces. [4:4] read-write VTRIP_SEL5_1 Input buffer compatible with automotive (elevated Vil) interfaces. [5:5] read-write VTRIP_SEL6_1 Input buffer compatible with automotive (elevated Vil) interfaces. [6:6] read-write VTRIP_SEL7_1 Input buffer compatible with automotive (elevated Vil) interfaces. [7:7] read-write CFG_OUT2 Port output buffer configuration register 2 0x60 32 read-write 0x0 0xFFFFFF DS_TRIM0 Sets the Drive Select Trim for IO pin 0 0 - Default (50ohms) 1 - 120ohms 2 - 90ohms 3 - 60ohms 4 - 50ohms 5 - 30ohms 6 - 20ohms 7 - 15ohms [2:0] read-write DEFAULT N/A 0 DS_120OHM N/A 1 DS_90OHM N/A 2 DS_60OHM N/A 3 DS_50OHM N/A 4 DS_30OHM N/A 5 DS_20OHM N/A 6 DS_15OHM N/A 7 DS_TRIM1 Sets the Drive Select Trim for IO pin 1 [5:3] read-write DS_TRIM2 Sets the Drive Select Trim for IO pin 2 [8:6] read-write DS_TRIM3 Sets the Drive Select Trim for IO pin 3 [11:9] read-write DS_TRIM4 Sets the Drive Select Trim for IO pin 4 [14:12] read-write DS_TRIM5 Sets the Drive Select Trim for IO pin 5 [17:15] read-write DS_TRIM6 Sets the Drive Select Trim for IO pin 6 [20:18] read-write DS_TRIM7 Sets the Drive Select Trim for IO pin 7 [23:21] read-write CFG_SLEW_EXT Port output buffer slew extension configuration register 0x64 32 read-write 0x0 0x77777777 SLEW0 Enables slow slew rate for IO pin 0 HSIO_STDLIN: slew_ctl[SLEW_WIDTH] = All 0s: Fastest slew rate slew_ctl[SLEW_WIDTH] = All 1s: Slowest slew rate HSIO_ENH: slew_sel[SLEW_WIDTH] = All 0s: Fastest slew rate slew_sel[SLEW_WIDTH] = All 1s: Slowest slew rate [2:0] read-write SLEW1 Slew rate for IO pin 1 [6:4] read-write SLEW2 Slew rate for IO pin 2 [10:8] read-write SLEW3 Slew rate for IO pin 3 [14:12] read-write SLEW4 Slew rate for IO pin 4 [18:16] read-write SLEW5 Slew rate for IO pin 5 [22:20] read-write SLEW6 Slew rate for IO pin 6 [26:24] read-write SLEW7 Slew rate for IO pin 7 [30:28] read-write CFG_DRIVE_EXT0 Port output buffer drive sel extension configuration register 0x68 32 read-write 0x0 0x1F1F1F1F DRIVE_SEL_EXT0 Sets the GPIO drive strength for IO pin 0 [4:0] read-write DRIVE_SEL_EXT1 Sets the GPIO drive strength for IO pin 1 [12:8] read-write DRIVE_SEL_EXT2 Sets the GPIO drive strength for IO pin 2 [20:16] read-write DRIVE_SEL_EXT3 Sets the GPIO drive strength for IO pin 3 [28:24] read-write CFG_DRIVE_EXT1 Port output buffer drive sel extension configuration register 0x6C 32 read-write 0x0 0x1F1F1F1F DRIVE_SEL_EXT4 Sets the GPIO drive strength for IO pin 4 [4:0] read-write DRIVE_SEL_EXT5 Sets the GPIO drive strength for IO pin 5 [12:8] read-write DRIVE_SEL_EXT6 Sets the GPIO drive strength for IO pin 6 [20:16] read-write DRIVE_SEL_EXT7 Sets the GPIO drive strength for IO pin 7 [28:24] read-write INTR_CAUSE0 Interrupt port cause register 0 0x4000 32 read-only 0x0 0xFFFFFFFF PORT_INT Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to determine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PRT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt. '0': Port has no pending interrupt '1': Port has pending interrupt [31:0] read-only INTR_CAUSE1 Interrupt port cause register 1 0x4004 32 read-only 0x0 0xFFFFFFFF PORT_INT Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to determine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PORT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt. '0': Port has no pending interrupt '1': Port has pending interrupt [31:0] read-only INTR_CAUSE2 Interrupt port cause register 2 0x4008 32 read-only 0x0 0xFFFFFFFF PORT_INT Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to determine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PORT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt. '0': Port has no pending interrupt '1': Port has pending interrupt [31:0] read-only INTR_CAUSE3 Interrupt port cause register 3 0x400C 32 read-only 0x0 0xFFFFFFFF PORT_INT Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to determine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PORT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt. '0': Port has no pending interrupt '1': Port has pending interrupt [31:0] read-only VDD_ACTIVE Extern power supply detection register 0x4010 32 read-only 0x0 0xC000FFFF VDDIO_ACTIVE Indicates presence or absence of VDDIO supplies (i.e. other than VDDD, VDDA) on the device (supplies are numbered 0..n-1). Note that VDDIO supplies have basic (crude) supply detectors only. If separate, robust, brown-out detection is desired on IO supplies, on-chip or off-chip analog resources need to provide it. For these bits to work reliable, the supply must be within valid spec range (per datasheet) or held at ground. Any in-between voltage has an undefined result. '0': Supply is not present '1': Supply is present When multiple VDDIO supplies are present, they will be assigned in alphanumeric ascending order to these bits during implementation. For example 'vddusb, vddio_0, vddio_a, vbackup, vddio_r, vddio_1' are present then they will be assigned to these bits as below: 0: vbackup, 1: vddio_0, 2: vddio_1, 3: vddio_a, 4: vddio_r, 5: vddusb' [15:0] read-only VDDA_ACTIVE Same as VDDIO_ACTIVE for the analog supply VDDA. [30:30] read-only VDDD_ACTIVE This bit indicates presence of the VDDD supply. This bit will always read-back 1. The VDDD supply has robust brown-out protection monitoring and it is not possible to read back this register without a valid supply. (This bit is used in certain test-modes to observe the brown-out detector status.) [31:31] read-only VDD_INTR Supply detection interrupt register 0x4014 32 read-write 0x0 0xC000FFFF VDDIO_ACTIVE Supply state change detected. '0': No change to supply detected '1': Change to supply detected [15:0] read-write VDDA_ACTIVE Same as VDDIO_ACTIVE for the analog supply VDDA. [30:30] read-write VDDD_ACTIVE The VDDD supply is always present during operation so a supply transition can not occur. This bit will always read back '1'. [31:31] read-write VDD_INTR_MASK Supply detection interrupt mask register 0x4018 32 read-write 0x0 0xC000FFFF VDDIO_ACTIVE Masks supply interrupt on VDDIO. '0': VDDIO interrupt forwarding disabled '1': VDDIO interrupt forwarding enabled [15:0] read-write VDDA_ACTIVE Same as VDDIO_ACTIVE for the analog supply VDDA. [30:30] read-write VDDD_ACTIVE Same as VDDIO_ACTIVE for the digital supply VDDD. [31:31] read-write VDD_INTR_MASKED Supply detection interrupt masked register 0x401C 32 read-only 0x0 0xC000FFFF VDDIO_ACTIVE Supply transition detected AND masked '0': Interrupt was not forwarded to CPU '1': Interrupt occurred and was forwarded to CPU [15:0] read-only VDDA_ACTIVE Same as VDDIO_ACTIVE for the analog supply VDDA. [30:30] read-only VDDD_ACTIVE Same as VDDIO_ACTIVE for the digital supply VDDD. [31:31] read-only VDD_INTR_SET Supply detection interrupt set register 0x4020 32 read-write 0x0 0xC000FFFF VDDIO_ACTIVE Sets supply interrupt. '0': Interrupt state not affected '1': Interrupt set [15:0] read-write VDDA_ACTIVE Same as VDDIO_ACTIVE for the analog supply VDDA. [30:30] read-write VDDD_ACTIVE Same as VDDIO_ACTIVE for the digital supply VDDD. [31:31] read-write VDD_LVL External power supply level register 0x4024 32 read-only 0x0 0xFFFF VDDIO_LVL The VDD_LVL circuit detects the VDDIO supply level and writes the detected value in this register. '0' indicates the VDDIO supply is at 1.2V and '1' indicates VDDIO supply is at 1.8V. [15:0] read-only PDM0 PDM PDM 0x40320000 0 65536 registers CTL Control 0x0 32 read-write 0x0 0xFF ACTIVE Activate functionality (1 bit for each channel): '0': Reception disabled. The FIFO_OVERFLOW interrupt cause will not be activated. '1': Reception enabled. The FIFO_OVERFLOW interrupt may be activated (when an overflow event occurs). Note: This functionality is intended for startup purposes. Typically, the startup sequence is as follows: - global registers CLOCK_CTL, ROUTE_CTL, TEST_CTL, FIR*_COEFF* are initialized - One or more structures are enabled (structure specific CTL.ENABLED register field is set to '1'). - The structures are initialized (structure specific MMIO registers are written). - The structures are activated. This last step is performed by writing the CTL or CTL_SET MMIO registers, or on a rising edge ('0' to '1' transition) of a receiver's 'tr_activate' input trigger. Note: on a rising edge ('0' to '1' transition) of a receiver's 'tr_activate' input trigger, its associated CTL.ACTIVE field is set to '1'. This allows HW based synchronization of PDM receiver activation based on system triggers. Implementation note: the trigger is synchronized on the receiver clock with the receiver reset (this requires the receiver to be enabled; i.e. CTL.ENABLED is '1'). Note: if CTL_CLR.ACTIVE[i] is written to '1' at the same time a rising edge of 'tr_activate[i]' occurs, CTL.ACTIVE[i] is set to '1' (i.e. trigger takes precedence). [7:0] read-write CTL_CLR Control clear 0x4 32 read-write 0x0 0xFF ACTIVE Activate functionality: '0': No effect. '1': Bit is set to '0'. [7:0] read-write CTL_SET Control set 0x8 32 read-write 0x0 0xFF ACTIVE Activate functionality: '0': No effect. '1': Bit is set to '1'. [7:0] read-write CLOCK_CTL Clock control 0x10 32 read-write 0x307 0x103FF CLOCK_DIV PDM interface clock divider (legal range [3, 255]). The PDM interface clock clk_pdm ('pdm_clk[]' output signals) is defined as pdm_clk = clk_if / (CLOCK_DIV + 1); i.e. each PDM interface clock cycle equals CLOCK_DIV + 1 clk_if clock cycles. CLOCK_DIV should be set to an odd value ([3, 5, ..., 255]), to ensure a 50/50 percent duty cycle PDM interface clock pdm_clk. '0-2': Illegal value. '3': pdm_clk frequency is 1/4 clk_if frequency (1 pdm_clk cycle consists of 4 clk_if cycles). '4': pdm_clk frequency is 1/5 clk_if frequency. Note: results in a non 50/50 percent duty cycle pdm_clk). ... '255': pdm_clk frequency is 1/256 clk_if frequency. [7:0] read-write CLOCK_SEL Interface clock clk_if selection: '0': SRSS clock clk_if_srss. '1': IOSS data input signal 'pdm_data[0]'. '2': IOSS data input signal 'pdm_data[1]'. '3': undefined. Note: when a data input signal is used as a clock source, it cannot be used as a data line. Note: the application is always required to program this field to a value different from the default. [9:8] read-write SEL_SRSS_CLOCK N/A 0 SEL_PDM_DATA0 N/A 1 SEL_PDM_DATA1 N/A 2 SEL_OR N/A 3 HALVE Halve rate sampling: '0': Full rate sampling. The PDM interface clock pdm_clk is as specified by CLOCK_DIV[]. Each captured PDM value is provided once to the CIC filter. '1': Halve rate sampling. The PDM interface clock clk_pdm is as specified by CLOCK_DIV[] divided by two (halve the frequency). Each PDM value is captured twice and provided twice to the CIC filter; i.e. the PDM value is repeated. Note: this field is provided to dynamically change the digital microphone's clock (pdm_clk) without affecting the PDM sample frequency towards the CIC filter. Halving the microphone clock results in lower system power consumption, but does lower audio quality. [16:16] read-write FULL N/A 0 HALVE N/A 1 ROUTE_CTL Route control 0x20 32 read-write 0x0 0xFF DATA_SEL Specifies what IOSS data input signal 'pdm_data[]' is routed to a specific PDM receiver. Each PDM receiver j has a dedicated 1-bit control field: PDM receiver j uses DATA_SEL[j]. The 1-bit field DATA_SEL[j] specification is as follows: '0': PDM receiver j uses data input signal 'pdm_data[j]'. '1': PDM receiver j uses data input signal 'pdm_data[j ^ 1]' (the lower bit of the index is inverted). Routing the same data input signal to two PDM receivers allows for: - A single stereo digital microphone. - Two (mono) digital microphones that share a data line. E.g., if DATA_SEL is 0b00000010, PDM receivers 0 and 1 BOTH use 'pdm_data[0]'. [7:0] read-write TEST_CTL Test control 0x30 32 read-write 0x7F0400 0xFFFFFFFF DRIVE_DELAY_HI Interface drive delay on the high phase of the PDM interface clock. This field specifies when a PDM value is driven expressed in clk_if clock cycles. DRIVE_DELAY should be set in the range [0, IF_CTL.CLOCK_DIV]: '0': Drive PDM value 1 clk_if cycle after the rising edge of clk_pdm. '1': Drive PDM value 2 clk_if cycles after the rising edge of clk_pdm. ... '255': Drive PDM value 256 clk_if cycles after the rising edge of clk_pdm. Note: To drive on the falling edge of the PDM interface clock clk_pdm, DRIVE_DELAY should be set to IF_CTL.CLOCK_DIV/2. To drive on the rising edge of clk_pdm, DRIVE_DELAY should be set to IF_CTL.CLOCK_DIV. [7:0] read-write DRIVE_DELAY_LO Interface drive delay on the low phase of the PDM interface clock. This field specifies when a PDM value is driven expressed in clk_if clock cycles. DRIVE_DELAY should be set in the range [0, IF_CTL.CLOCK_DIV]: '0': Drive PDM value 1 clk_if cycle after the rising edge of clk_pdm. '1': Drive PDM value 2 clk_if cycles after the rising edge of clk_pdm. ... '255': Drive PDM value 256 clk_if cycles after the rising edge of clk_pdm. Note: To drive on the falling edge of the PDM interface clock clk_pdm, DRIVE_DELAY should be set to IF_CTL.CLOCK_DIV/2. To drive on the rising edge of clk_pdm, DRIVE_DELAY should be set to IF_CTL.CLOCK_DIV. [15:8] read-write MODE_HI Pattern generator mode on the high phase of the PDM interface clock. This field specifies the type of PDM pattern driven by the generator: '0': constant 0's '1': constant 1's '2': alternating 0's and 1's (clock pattern) '3': sinusoid [17:16] read-write CONSTANT_0 N/A 0 CONSTANT_1 N/A 1 ALTERNATING N/A 2 SINUSOID N/A 3 MODE_LO Pattern generator mode on the low phase of the PDM interface clock. This field specifies the type of pattern driven by the generator: '0': constant 0's '1': constant 1's '2': alternating 0's and 1's (clock pattern) '3': sine wave [19:18] read-write CONSTANT_0 N/A 0 CONSTANT_1 N/A 1 ALTERNATING N/A 2 SINUSOID N/A 3 AUDIO_FREQ_DIV Frequency division factor (legal range [3, 13]) to obtain audio frequency from the PDM clock frequency. This field determines the frequency of the sine wave generated by the pattern generator when MODE=3. The formula is below: Sine wave Frequency = PDM clock frequency / 2p*2^(AUDIO_FREQ_DIV) Example: when PDM clock frequency = 3.072 MHz the audio frequencies obtained for the various values of AUDIO_FREQ_DIV are shown below: '3' : 61.115 kHz '4' : 30.558 kHz '5' : 15.279 kHz '6' : 7.639 kHz '7' : 3.820 kHz '8' : 1.910 kHz '9' : 955 Hz '10' : 477 Hz '11' : 239 Hz '12' : 119 Hz '13' : 60 Hz [23:20] read-write DIV_PDM_FREQ_BY_2PI_x_8 Example: 3.072 MHz/(2p*8) = 61.115 kHz 3 DIV_PDM_FREQ_BY_2PI_x_16 Example: 3.072 MHz/(2p*16) = 30.558 kHz 4 DIV_PDM_FREQ_BY_2PI_x_8192 Example: 3.072 MHz/(2p*8192) = 60 Hz 13 CH_ENABLED Pattern generator enable (1 bit for each channel): '0' : disabled, the channel input is taken as normal from external pin pdm_data_in '1' : enabled, the channel input is taken from the pattern generator Note: the pattern generator output is routed to pdm_data_out for testing purposes Note: when all channels are disabled the pattern generator is switched off [31:24] read-write FIR0_COEFF0 FIR 0 coefficients 0 0x100 32 read-write 0x0 0x0 DATA0 Filter taps 0 and 29 coefficient. [13:0] read-write DATA1 Filter taps 1 and 28 coefficient. [29:16] read-write FIR0_COEFF1 FIR 0 coefficients 1 0x104 32 read-write 0x0 0x0 DATA0 Filter taps 2 and 27 coefficient. [13:0] read-write DATA1 Filter taps 3 and 26 coefficient. [29:16] read-write FIR0_COEFF2 FIR 0 coefficients 2 0x108 32 read-write 0x0 0x0 DATA0 Filter taps 4 and 25 coefficient. [13:0] read-write DATA1 Filter taps 5 and 24 coefficient. [29:16] read-write FIR0_COEFF3 FIR 0 coefficients 3 0x10C 32 read-write 0x0 0x0 DATA0 Filter taps 6 and 23 coefficient. [13:0] read-write DATA1 Filter taps 7 and 22 coefficient. [29:16] read-write FIR0_COEFF4 FIR 0 coefficients 4 0x110 32 read-write 0x0 0x0 DATA0 Filter taps 8 and 21 coefficient. [13:0] read-write DATA1 Filter taps 9 and 20 coefficient. [29:16] read-write FIR0_COEFF5 FIR 0 coefficients 5 0x114 32 read-write 0x0 0x0 DATA0 Filter taps 10 and 19 coefficient. [13:0] read-write DATA1 Filter taps 11 and 18 coefficient. [29:16] read-write FIR0_COEFF6 FIR 0 coefficients 6 0x118 32 read-write 0x0 0x0 DATA0 Filter taps 12 and 17 coefficient. [13:0] read-write DATA1 Filter taps 13 and 16 coefficient. [29:16] read-write FIR0_COEFF7 FIR 0 coefficients 7 0x11C 32 read-write 0x0 0x0 DATA0 Filter tap 14 coefficient. [13:0] read-write DATA1 Filter tap 15 coefficient. [29:16] read-write FIR1_COEFF0 FIR 1 coefficients 0 0x140 32 read-write 0x153FFE 0x3FFF3FFF DATA0 Filter taps 0 and 54 coefficient (default value -2). [13:0] read-write DATA1 Filter taps 1 and 53 coefficient (default value 21). [29:16] read-write FIR1_COEFF1 FIR 1 coefficients 1 0x144 32 read-write 0x3FEF001A 0x3FFF3FFF DATA0 Filter taps 2 and 52 coefficient (default value 26). [13:0] read-write DATA1 Filter taps 3 and 51 coefficient (default value -17). [29:16] read-write FIR1_COEFF2 FIR 1 coefficients 2 0x148 32 read-write 0x193FD7 0x3FFF3FFF DATA0 Filter taps 4 and 50 coefficient (default value -41). [13:0] read-write DATA1 Filter taps 5 and 49 coefficient (default value 25). [29:16] read-write FIR1_COEFF3 FIR 1 coefficients 3 0x14C 32 read-write 0x3FDF0044 0x3FFF3FFF DATA0 Filter taps 6 and 48 coefficient (default value 68). [13:0] read-write DATA1 Filter taps 7 and 47 coefficient (default value -33). [29:16] read-write FIR1_COEFF4 FIR 1 coefficients 4 0x150 32 read-write 0x293F95 0x3FFF3FFF DATA0 Filter taps 8 and 46 coefficient (default value -107). [13:0] read-write DATA1 Filter taps 9 and 45 coefficient (default value 41). [29:16] read-write FIR1_COEFF5 FIR 1 coefficients 5 0x154 32 read-write 0x3FD000A0 0x3FFF3FFF DATA0 Filter taps 10 and 44 coefficient (default value 160). [13:0] read-write DATA1 Filter taps 11 and 43 coefficient (default value -48). [29:16] read-write FIR1_COEFF6 FIR 1 coefficients 6 0x158 32 read-write 0x363F1A 0x3FFF3FFF DATA0 Filter taps 12 and 42 coefficient (default value -230). [13:0] read-write DATA1 Filter taps 13 and 41 coefficient (default value 54). [29:16] read-write FIR1_COEFF7 FIR 1 coefficients 7 0x15C 32 read-write 0x3FC80145 0x3FFF3FFF DATA0 Filter taps 14 and 40 coefficient (default value 325). [13:0] read-write DATA1 Filter taps 15 and 39 coefficient (default value -56). [29:16] read-write FIR1_COEFF8 FIR 1 coefficients 8 0x160 32 read-write 0x333E3B 0x3FFF3FFF DATA0 Filter taps 16 and 38 coefficient (default value -453). [13:0] read-write DATA1 Filter taps 17 and 37 coefficient (default value 51). [29:16] read-write FIR1_COEFF9 FIR 1 coefficients 9 0x164 32 read-write 0x3FE10277 0x3FFF3FFF DATA0 Filter taps 18 and 36 coefficient (default value 631). [13:0] read-write DATA1 Filter taps 19 and 35 coefficient (default value -31). [29:16] read-write FIR1_COEFF10 FIR 1 coefficients 10 0x168 32 read-write 0x3FEB3C82 0x3FFF3FFF DATA0 Filter taps 20 and 34 coefficient (default value -894). [13:0] read-write DATA1 Filter taps 21 and 33 coefficient (default value -21). [29:16] read-write FIR1_COEFF11 FIR 1 coefficients 11 0x16C 32 read-write 0xAC052E 0x3FFF3FFF DATA0 Filter taps 22 and 32 coefficient (default value 1326). [13:0] read-write DATA1 Filter taps 23 and 31 coefficient (default value 172). [29:16] read-write FIR1_COEFF12 FIR 1 coefficients 12 0x170 32 read-write 0x3CFE3771 0x3FFF3FFF DATA0 Filter taps 24 and 30 coefficient (default value -2191). [13:0] read-write DATA1 Filter taps 25 and 29 coefficient (default value -770). [29:16] read-write FIR1_COEFF13 FIR 1 coefficients 13 0x174 32 read-write 0x1FFF12FB 0x3FFF3FFF DATA0 Filter taps 26 and 28 coefficient (default value 4859). [13:0] read-write DATA1 Filter taps 27 (center tap) coefficient (default value 8191). [29:16] read-write 2 256 CH[%s] PDM RX structure 0x00008000 CTL Control 0x0 32 read-write 0x100 0x8000010F WORD_SIZE PCM word size: '0': 8 bit. '1': 10 bit. '2': 12 bit. '3': 14 bit. '4': 16 bit. '5': 18 bit. '6': 20 bit. '7': 24 bit. '8': 32 bit. '9'-'15': Undefined. [3:0] read-write SIZE_8 N/A 0 SIZE_10 N/A 1 SIZE_12 N/A 2 SIZE_14 N/A 3 SIZE_16 N/A 4 SIZE_18 N/A 5 SIZE_20 N/A 6 SIZE_24 N/A 7 SIZE_32 N/A 8 WORD_SIGN_EXTEND Word extension: '0': zero extension. '1': sign extension. [8:8] read-write ZERO_EXTEND N/A 0 SIGN_EXTEND N/A 1 ENABLED Receiver enable: '0': Disabled. If a receiver is disabled, all non-retained MMIO registers (e.g. the RX_FIFO_STATUS and INTR_RX registers) have their fields reset to their default value. '1': Enabled. Note: when all receivers are disabled, the SRAMs are driven into low power mode, if supported by the SRAM. When exiting such low power mode software needs to allow for a certain power up time before SRAM can be used, i.e. before ACTIVE can be asserted. The power up time is equivalent to the system SRAM power up time specified in the CPUSS.RAM_PWR_DELAY_CTL register (or equivalent for platforms other than MXS40). [31:31] read-write IF_CTL Interface control 0x10 32 read-write 0x3 0xFF SAMPLE_DELAY Interface sample delay. This field specifies when a PDM value is captured, expressed in clk_if clock cycles. When CLOCK_CTL.HALVE=0: '0': Capture PDM value 1 clk_if cycle after the rising edge of clk_pdm. '1': Capture PDM value 2 clk_if cycles after the rising edge of clk_pdm. ... '255': Capture PDM value 256 clk_if cycles after the rising edge of clk_pdm. When CLOCK_CTL.HALVE=1: '0': Capture PDM value 1 and 2 clk_if cycles after the rising edge of clk_pdm. '1': Capture PDM value 3 and 4 clk_if cycles after the rising edge of clk_pdm. ... '255': Capture PDM value 511 and 512 clk_if cycles after the rising edge of clk_pdm. SAMPLE_DELAY should be set such that the clk_if capture edge is at the middle point between pdm_clk_out edges. Under ideal conditions the middle point is 1/4 of the PDM interface period for the first/even/left channel, and 3/4 of the PDM interface period for the second/odd/right channel, which corresponds to the following programmings: SAMPLE_DELAY(left)=((CLOCK_DIV+1)/4) - 1 SAMPLE_DELAY(right)=(3*(CLOCK_DIV+1)/4) - 1 In practice, due to the roundtrip delay, SAMPLE_DELAY may be set to a later point with respect to the ideal middle point. Note: in all cases a SAMPLE_DELAY value that brings the capture edge close to the pdm_clk_out edges should be avoided. [7:0] read-write CIC_CTL CIC control 0x14 32 read-write 0x4 0x7 DECIM_CODE CIC filter decimation. The CIC filter PCM frequency is a fraction of the PDM frequency: '0': CIC filter PCM frequency is 1/2 * PDM frequency. CIC PCM values are in the range [-0x10, 0x10]. '1': CIC filter PCM frequency is 1/4 * PDM frequency. CIC PCM values are in the range [-0x200, 0x200]. '2': CIC filter PCM frequency is 1/8 * PDM frequency. CIC PCM values are in the range [-0x4000, 0x4000]. '3': CIC filter PCM frequency is 1/16 * PDM frequency. CIC PCM values are in the range [-0x8:0000, 0x8:0000]. '4': CIC filter PCM frequency is 1/32 * PDM frequency. CIC PCM values are in the range [-0x100:0000, 0x100:0000]. '5'-'7': Illegal values. Note: The CIC filter functionality includes offsetting logic to ensure that 'digital silence' on the PDM interface (an alternating pattern of '0', '1', '0', '1' ... PDM values) results in CIC filter PCM values of '0'. Similarly, a pattern of '0', '0', '0', ... PDM values results in minimum CIC PCM value (-0x100:0000 when DECIMATION is '4') and a pattern of '1', '1', '1', ... PDM values results in maximum CIC PCM value (0x100:0000 when DECIMATION is '4'). Note: The IP's desired 'clk_sys' frequency is a function of the PDM interface clock, the CIC filter decimation (CIC_CTL.DECIM_CODE[]) and the FIR filter decimation (FIR_CTL.DECIM_CODE[]). [2:0] read-write DECIM_2 N/A 0 DECIM_4 N/A 1 DECIM_8 N/A 2 DECIM_16 N/A 3 DECIM_32 This is the default value and the most realistic value (together with the value '3'). Typically, an overall decimation (or oversample rate (OSR)) of 64 is used, and this is achieved with the default CIC and FIR decimation values. 4 FIR0_CTL FIR 0 control 0x18 32 read-write 0x0 0x80001F07 DECIM3 FIR filter decimation. The FIR filter PCM frequency is a fraction of the CIC filter PCM frequency: '0': FIR 0 filter PCM frequency is 1 * CIC filter PCM frequency. The FIR 0 filter is performed for every CIC filter PCM sample. '1': FIR 0 filter PCM frequency is 1/2 * CIC filter PCM frequency. The FIR 0 filter is performed for every second CIC filter PCM sample. '2': FIR 0 filter PCM frequency is 1/3 * CIC filter PCM frequency. The FIR 0 filter is performed for every third CIC filter PCM sample. '3': FIR 0 filter PCM frequency is 1/4 * CIC filter PCM frequency. The FIR 0 filter is performed for every fourth CIC filter PCM sample. '4': FIR 0 filter PCM frequency is 1/5 * CIC filter PCM frequency. The FIR 0 filter is performed for every fifth CIC filter PCM sample. [2:0] read-write DECIM_1 N/A 0 DECIM_2 N/A 1 DECIM_3 N/A 2 DECIM_4 N/A 3 DECIM_5 N/A 4 SCALE FIR 0 filter PCM scaling. FIR 0 filter PCM values (fir0_pcm[44:0]) are scaled (right shifted, rounded and clipped) to 26-bit signed PCM values (fir0_scaled_pcm[25:0]). These 26-bit PCM values are input to the FIR 1 filter. SCALE specifies the right shift amount (and performs a rounding): '0': fir0_scaled_pcm = CLIP26 (fir0_pcm[44:0]). '1': fir0_scaled_pcm = CLIP26 (fir0_pcm[44:1] + fir0_pcm[0]). ... '31': fir0_scaled_pcm = CLIP26 (fir0_pcm[44:31] + fir0_pcm[30]). With CLIP26(a) defined as: if (a >= 0x1ff:ffff) result = 0x1ff:ffff; else if (a < -0x200:0000) result = -0x200:0000; else result = a; Note: Clipping is not necessary for larger SCALE values, as the scaled value is guarneteed to be within the 26-bit signed integer range. [12:8] read-write SCALE_0 N/A 0 SCALE_1 N/A 1 SCALE_31 N/A 31 ENABLED FIR 0 filter coefficient enable (does NOT effect FIR filter scaling and FIR filter decimation): '0': Disabled. The middle FIR filter coefficient (16th coefficient, or tap 15 in [0:29] range) is '1' and all other FIR filter coefficients are '0'; i.e. the FIR filter is a pass through filter and the filter gain is '1'. fir0_pcm[44:0] = cic_pcm[25:0] (with sign extension) '1': Enabled. Note: This filter is disabled by default, and typically only used for sample frequencies (Fs) of 8 and 16 kHz. [31:31] read-write FIR1_CTL FIR 1 control 0x1C 32 read-write 0x80000F01 0x80001F03 DECIM2 FIR 1 filter decimation. The FIR filter PCM frequency is a fraction of the CIC filter PCM frequency: '0': FIR 1 filter PCM frequency is 1 * FIR 0 filter PCM frequency. The FIR filter is performed for every FIR 0 filter PCM sample. '1': FIR 1 filter PCM frequency is 1/2 * FIR 0 filter PCM frequency. The FIR filter is performed for every second FIR 0 filter PCM sample. '2': FIR 1 filter PCM frequency is 1/3 * FIR 0 filter PCM frequency. The FIR filter is performed for every third FIR 0 filter PCM sample. '3': FIR 1 filter PCM frequency is 1/4 * FIR 0 filter PCM frequency. The FIR filter is performed for every fourth FIR 0 filter PCM sample. [1:0] read-write DECIM_1 N/A 0 DECIM_2 N/A 1 DECIM_3 N/A 2 DECIM_4 N/A 3 SCALE FIR 1 filter PCM scaling. FIR filter PCM values (fir1_pcm[43:0]) are scaled (right shifted, rounded and clipped) to 24-bit signed PCM values (fir1_scaled_pcm[23:0]). These 24-bit PCM values are input to the DC blocker. SCALE specifies the right shift amount (and performs a rounding): '0': fir1_scaled_pcm = CLIP24 (fir1_pcm[43:0]). '1': fir1_scaled_pcm = CLIP24 (fir1_pcm[43:1] + fir1_pcm[0]). ... '31': fir1_scaled_pcm = CLIP24 (fir1_pcm[43:31] + fir1_pcm[30]). With CLIP24(a) defined as: if (a >= 0x7f:ffff) result = 0x7f:ffff; else if (a < -0x80:0000) result = -0x80:0000; else result = a; Note: Clipping is not necessary for larger SCALE values, as the scaled value is guarneteed to be within the 24-bit signed integer range. [12:8] read-write SCALE_0 N/A 0 SCALE_1 N/A 1 SCALE_31 N/A 31 ENABLED FIR 1 filter coefficient enable (does NOT effect FIR filter scaling and FIR filter decimation): '0': Disabled. The middle FIR filter coefficient (28th coefficient, or tap 27 in [0:54] range) is '1' and all other FIR filter coefficients are '0'; i.e. the FIR filter is a pass through filter and the filter gain is '1'. fir1_pcm[43:0] = fir0_scaled_pcm[25:0] (with sign extension) '1': Enabled. Note: Disabling of the filter functionality is provided for debug purposes. [31:31] read-write DC_BLOCK_CTL DC block control 0x20 32 read-write 0x80000001 0x80000007 CODE DC blocker coefficient. The DC blocker is defined as: dc_block_state_scaled(n-1) = dc_block_state(n-1) - (dc_block_state(n-1) >> (12-CODE)) dc_block_state(n) = CLIP37 ( 2^13 * (fir1_scaled_pcm(n) - fir1_scaled_pcm(n-1)) + dc_block_state_scaled(n-1)) dc_block_pcm(n) = dc_block_state(n) >> 13 This first step is a scaling step of the DC block state. It effectively multiplies the DC block state with a variable 'alpha' that is close to '1': '0': alpha = 1 - (1/2^(12-0)) = 0.999755859. '1': alpha = 1 - (1/2^(12-1)) = 0.999511719. '2': alpha = 1 - (1/2^(12-2)) = 0.999023438. '3': alpha = 1 - (1/2^(12-3)) = 0.998046875. '4': alpha = 1 - (1/2^(12-4)) = 0.99609375. '5': alpha = 1 - (1/2^(12-5)) = 0.9921875. '6': alpha = 1 - (1/2^(12-6)) = 0.984375. '7': alpha = 1 - (1/2^(12-7)) = 0.96875. [2:0] read-write CODE_1 N/A 0 CODE_2 N/A 1 CODE_4 N/A 2 CODE_8 N/A 3 CODE_16 N/A 4 CODE_32 N/A 5 CODE_64 N/A 6 CODE_128 N/A 7 ENABLED DC blocker enable: '0': Disabled. The functionality is defined as: dc_block_pcm(n) = fir1_scaled_pcm(n) '1': Enabled. The functionality is as specified by the CODE field. Note: disabling of the DC blocker filter functionality is provided for debug purposes. [31:31] read-write RX_FIFO_CTL RX FIFO control 0x80 32 read-write 0x0 0x2003F TRIGGER_LEVEL Trigger level. When the RX FIFO has more entries than the number of this field, a receiver trigger event is generated: - INTR_RX.FIFO_TRIGGER = (# FIFO entries > TRIGGER_LEVEL) [5:0] read-write EMPTY N/A 0 USED_1 N/A 1 USED_63 N/A 63 FREEZE Freeze functionality: '0': HW writes to the RX FIFO and advances the FIFO write pointer. '1': HW writes from the RX FIFO have no effect: freeze will not advance the FIFO write pointer. Note: This functionality is intended for debugging purposes. [17:17] read-write RX_FIFO_STATUS RX FIFO status 0x84 32 read-only 0x0 0x3F3F007F USED Number of used/occupied entries in the RX FIFO. The field value is in the range [0, 64]. When '0', the FIFO is empty. When '64', the FIFO is full. [6:0] read-only RD_PTR RX FIFO read pointer: FIFO location from which a data is read. Note: This functionality is intended for debugging purposes. [21:16] read-only WR_PTR RX FIFO write pointer: FIFO location at which a new data is written by the hardware. Note: This functionality is intended for debugging purposes. [29:24] read-only RX_FIFO_RD RX FIFO read 0x88 32 read-only 0x0 0xFFFFFFFF DATA Data (PCM sample) read from the RX FIFO. Reading removes the data from the RX FIFO; i.e. behavior is similar to that of a POP operation (RX_FIFO_STATUS.RD_PTR is incremented and RX_FIFO_STATUS.USED is decremented). The read data (DATA) is right aligned (unused bit positions follow the specified sign extension per CTL.WORD_SIGN_EXTEND) when it is read from the FIFO entry (data[23:0]): - 8 bit, DATA[7:0] = data[23:16]. - 10 bit, DATA[9:0] = data[23:14]. - 12 bit, DATA[11:0] = data[23:12]. - 14 bit, DATA[13:0] = data[23:10]. - 16 bit, DATA[15:0] = data[23:8]. - 18 bit, DATA[17:0] = data[23:6]. - 20 bit, DATA[19:0] = data[23:4]. - 24 bit, DATA[23:0] = data[23:0]. - 32 bit, DATA[31:0] = data[23:0] << 8. Note: Reading from an empty RX FIFO activates INTR_RX.FIFO_UNDERFLOW. [31:0] read-only RX_FIFO_RD_SILENT RX FIFO silent read 0x8C 32 read-only 0x0 0xFFFFFFFF DATA Data (PCM sample) read from the RX FIFO. Reading will NOT remove the data from the RX FIFO; i.e. behavior is similar to that of a PEEK operation. See RX_FIFO_RD for data alignment. Note: Reading from an empty RX FIFO activates INTR.RX_FIFO_UNDERFLOW (the read returns 0xffff:ffff). Note: This functionality is intended for debugging purposes. [31:0] read-only INTR_RX Interrupt 0xC0 32 read-write 0x0 0x117 FIFO_TRIGGER HW sets this field to '1', when a RX trigger is generated. [0:0] read-write FIFO_OVERFLOW HW sets this field to '1', when writing to a full RX FIFO (RX_FIFO_STATUS.USED is '64'). [1:1] read-write FIFO_UNDERFLOW HW sets this field to '1', when reading from an empty RX FIFO (RX_FIFO_STATUS.USED is '0'). [2:2] read-write FIR_OVERFLOW HW sets this field to '1', when CIC filter PCM samples are produced at a faster rate than the FIR filter can process them. This is an indication that the IP system frequency is too low. Note: This functionality is intended for debugging purposes. [4:4] read-write IF_OVERFLOW HW sets this field to '1', when PDM samples are generated too fast by the interface logic (interface overflow). This may be an indication that the IP system frequency is too low wrt. the interface frequency (a SW configuration error). The interface overflow is a non-recoverable error and requires SW disabling (CTL.ENABLED) of the receiver clearing INTR_RX.IF_OVERFLOW to '0' does not resolve the interface underflow). Note: This functionality is intended for debug purposes. [8:8] read-write INTR_RX_SET Interrupt set 0xC4 32 read-write 0x0 0x117 FIFO_TRIGGER Write this field with '1' to set corresponding INTR_RX field (a write of '0' has no effect). [0:0] read-write FIFO_OVERFLOW Write this field with '1' to set corresponding INTR_RX field (a write of '0' has no effect). [1:1] read-write FIFO_UNDERFLOW Write this field with '1' to set corresponding INTR_RX field (a write of '0' has no effect). [2:2] read-write FIR_OVERFLOW Write this field with '1' to set corresponding INTR_RX field (a write of '0' has no effect). [4:4] read-write IF_OVERFLOW Write this field with '1' to set corresponding INTR_RX field (a write of '0' has no effect). [8:8] read-write INTR_RX_MASK Interrupt mask 0xC8 32 read-write 0x0 0x117 FIFO_TRIGGER Mask for corresponding field in INTR_RX register. [0:0] read-write FIFO_OVERFLOW Mask for corresponding field in INTR_RX register. [1:1] read-write FIFO_UNDERFLOW Mask for corresponding field in INTR_RX register. [2:2] read-write FIR_OVERFLOW Mask for corresponding field in INTR_RX register. [4:4] read-write IF_OVERFLOW Mask for corresponding field in INTR_RX register. [8:8] read-write INTR_RX_MASKED Interrupt masked 0xCC 32 read-only 0x0 0x117 FIFO_TRIGGER Logical AND of corresponding INTR_RX and INTR_RX_MASK fields. [0:0] read-only FIFO_OVERFLOW Logical AND of corresponding INTR_RX and INTR_RX_MASK fields. [1:1] read-only FIFO_UNDERFLOW Logical AND of corresponding INTR_RX and INTR_RX_MASK fields. [2:2] read-only FIR_OVERFLOW Logical AND of corresponding INTR_RX and INTR_RX_MASK fields. [4:4] read-only IF_OVERFLOW Logical AND of corresponding INTR_RX and INTR_RX_MASK fields. [8:8] read-only TCPWM0 Timer/Counter/PWM TCPWM 0x40400000 0 65536 registers CTRL TCPWM control register 0x0 32 read-write 0x0 0xFFFFFFFF COUNTER_ENABLED Counter enables for counters 0 up to CNT_NR-1. '0': counter disabled. '1': counter enabled. Counter static configuration information (e.g. CTRL.MODE, all TR_CTRL0, TR_CTRL1, and TR_CTRL2 register fields) should only be modified when the counter is disabled. When a counter is disabled, command and status information associated to the counter is cleared by HW, this includes: - the associated counter triggers in the CMD register are set to '0'. - the counter's interrupt cause fields in counter's INTR register. - the counter's status fields in counter's STATUS register.. - the counter's trigger outputs ('tr_overflow', 'tr_underflow' and 'tr_compare_match'). - the counter's line outputs ('line_out' and 'line_compl_out'). In multi-core environments, use the CTRL_SET/CTRL_CLR registers to avoid race-conditions on read-modify-write attempts to this register. [31:0] read-write CTRL_CLR TCPWM control clear register 0x4 32 read-write 0x0 0xFFFFFFFF COUNTER_ENABLED Alias of CTRL that only allows disabling of counters. A write access: '0': Does nothing. '1': Clears respective COUNTER_ENABLED field. A read access returns CTRL.COUNTER_ENABLED. [31:0] read-write CTRL_SET TCPWM control set register 0x8 32 read-write 0x0 0xFFFFFFFF COUNTER_ENABLED Alias of CTRL that only allows enabling of counters. A write access: '0': Does nothing. '1': Sets respective COUNTER_ENABLED field. A read access returns CTRL.COUNTER_ENABLED. [31:0] read-write CMD_CAPTURE TCPWM capture command register 0xC 32 read-write 0x0 0xFFFFFFFF COUNTER_CAPTURE Counters SW capture trigger. When written with '1', a capture trigger is generated and the HW sets the field to '0' when the SW trigger has taken effect. It should be noted that the HW operates on the counter frequency. If the counter is disabled through CTRL.COUNTER_ENABLED, the field is immediately set to '0'. [31:0] read-write CMD_RELOAD TCPWM reload command register 0x10 32 read-write 0x0 0xFFFFFFFF COUNTER_RELOAD Counters SW reload trigger. For HW behavior, see COUNTER_CAPTURE field. [31:0] read-write CMD_STOP TCPWM stop command register 0x14 32 read-write 0x0 0xFFFFFFFF COUNTER_STOP Counters SW stop trigger. For HW behavior, see COUNTER_CAPTURE field. [31:0] read-write CMD_START TCPWM start command register 0x18 32 read-write 0x0 0xFFFFFFFF COUNTER_START Counters SW start trigger. For HW behavior, see COUNTER_CAPTURE field. [31:0] read-write INTR_CAUSE TCPWM Counter interrupt cause register 0x1C 32 read-only 0x0 0xFFFFFFFF COUNTER_INT Counters interrupt signal active. If the counter is disabled through CTRL.COUNTER_ENABLED, the associated interrupt field is immediately set to '0'. [31:0] read-only 8 64 CNT[%s] Timer/Counter/PWM Counter Module 0x00000100 CTRL Counter control register 0x0 32 read-write 0x0 0x737FF0F AUTO_RELOAD_CC Specifies switching of the CC and buffered CC values. This field has a function in TIMER, PWM, PWM_DT and PWM_PR modes. Timer mode: '0': never switch. '1': switch on a compare match event. PWM, PWM_DT, PWM_PR modes: '0: never switch. '1': switch on a terminal count event with an actively pending switch event. [0:0] read-write AUTO_RELOAD_PERIOD Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM, PWM_DT and PWM_PR modes. '0': never switch. '1': switch on a terminal count event with and actively pending switch event. [1:1] read-write PWM_SYNC_KILL Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill). In synchronous kill mode, STOP_EDGE should be RISING_EDGE. '0': asynchronous kill mode: the kill event only disables the 'dt_line_out' and 'dt_line_compl_out' signals when present. In asynchronous kill mode, STOP_EDGE should be NO_EDGE_DET. This field has a function in PWM and PWM_DT modes only. This field is only used when PWM_STOP_ON_KILL is '0'. [2:2] read-write PWM_STOP_ON_KILL Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter. '1': kill event stops counter. This field has a function in PWM, PWM_DT and PWM_PR modes only. [3:3] read-write GENERIC Generic 8-bit control field. In PWM_DT mode, this field is used to determine the dead time: amount of dead time cycles in the counter clock domain. In all other modes, the lower 3 bits of this field determine pre-scaling of the selected counter clock. [15:8] read-write UP_DOWN_MODE Determines counter direction. [17:16] read-write COUNT_UP Count up (to PERIOD). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. A terminal count event is generated when the counter changes from a state in which COUNTER equals PERIOD. 0 COUNT_DOWN Count down (to '0'). An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'. 1 COUNT_UPDN1 Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'. 2 COUNT_UPDN2 Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0' AND when the counter changes from a state in which COUNTER equals PERIOD (this counter direction can be used for PWM functionality with asymmetrical updates). 3 ONE_SHOT When '0', counter runs continuous. When '1', counter is turned off by hardware when a terminal count event is generated. [18:18] read-write QUADRATURE_MODE In QUAD mode selects quadrature encoding mode (X1/X2/X4). In PWM, PWM_DT and PWM_PR modes, these two bits can be used to invert 'dt_line_out' and 'dt_line_compl_out'. Inversion is the last step in generation of 'dt_line_out' and 'dt_line_compl_out'; i.e. a disabled output line 'dt_line_out' has the value QUADRATURE_MODE[0] and a disabled output line 'dt_line_compl_out' has the value QUADRATURE_MODE[1]. [21:20] read-write X1 X1 encoding (QUAD mode) 0 X2 X2 encoding (QUAD mode) 1 X4 X4 encoding (QUAD mode) 2 MODE Counter mode. [26:24] read-write TIMER Timer mode 0 CAPTURE Capture mode 2 QUAD Quadrature encoding mode 3 PWM Pulse width modulation (PWM) mode 4 PWM_DT PWM with deadtime insertion mode 5 PWM_PR Pseudo random pulse width modulation 6 STATUS Counter status register 0x4 32 read-only 0x0 0x8000FF01 DOWN When '0', counter is counting up. When '1', counter is counting down. In QUAD mode, this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented. [0:0] read-only GENERIC Generic 8-bit counter field. In PWM_DT mode, this counter is used for dead time insertion. In all other modes, this counter is used for pre-scaling the selected counter clock. PWM_DT mode can NOT use prescaled clock functionality. [15:8] read-only RUNNING When '0', the counter is NOT running. When '1', the counter is running. [31:31] read-only COUNTER Counter count register 0x8 32 read-write 0x0 0xFFFFFFFF COUNTER 16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running. [31:0] read-write CC Counter compare/capture register 0xC 32 read-write 0xFFFFFFFF 0xFFFFFFFF CC In CAPTURE mode, captures the counter value. In other modes, compared to counter value. [31:0] read-write CC_BUFF Counter buffered compare/capture register 0x10 32 read-write 0xFFFFFFFF 0xFFFFFFFF CC Additional buffer for counter CC register. [31:0] read-write PERIOD Counter period register 0x14 32 read-write 0xFFFFFFFF 0xFFFFFFFF PERIOD Period value: upper value of the counter. When the counter should count for n cycles, this field should be set to n-1. [31:0] read-write PERIOD_BUFF Counter buffered period register 0x18 32 read-write 0xFFFFFFFF 0xFFFFFFFF PERIOD Additional buffer for counter PERIOD register. [31:0] read-write TR_CTRL0 Counter trigger control register 0 0x20 32 read-write 0x10 0xFFFFF CAPTURE_SEL Selects one of the 16 input triggers as a capture trigger. Input trigger 0 is always '0' and input trigger is always '1'. In the PWM, PWM_DT and PWM_PR modes this trigger is used to switch the values if the compare and period registers with their buffer counterparts. [3:0] read-write COUNT_SEL Selects one of the 16 input triggers as a count trigger. In QUAD mode, this is the first phase (phi A). Default setting selects input trigger 1, which is always '1'. [7:4] read-write RELOAD_SEL Selects one of the 16 input triggers as a reload trigger. In QUAD mode, this is the index or revolution pulse. In this mode, it will update the counter with 0x8000 (counter midpoint). [11:8] read-write STOP_SEL Selects one of the 16 input triggers as a stop trigger. In PWM, PWM_DT and PWM_PR modes, this is the kill trigger. In these modes, the kill trigger is used to either temporarily block the PWM outputs (PWM_STOP_ON_KILL is '0') or stop the functionality (PWM_STOP_ON_KILL is '1'). For the PWM and PWM_DT modes, the blocking of the output signals can be asynchronous (STOP_EDGE should be NO_EDGE_DET) in which case the blocking is as long as the trigger is '1' or synchronous (STOP_EDGE should be RISING_EDGE) in which case it extends till the next terminal count event. [15:12] read-write START_SEL Selects one of the 16 input triggers as a start trigger. In QUAD mode, this is the second phase (phi B). [19:16] read-write TR_CTRL1 Counter trigger control register 1 0x24 32 read-write 0x3FF 0x3FF CAPTURE_EDGE A capture event will copy the counter value into the CC register. [1:0] read-write RISING_EDGE Rising edge. Any rising edge generates an event. 0 FALLING_EDGE Falling edge. Any falling edge generates an event. 1 BOTH_EDGES Rising AND falling edge. Any odd amount of edges generates an event. 2 NO_EDGE_DET No edge detection, use trigger as is. 3 COUNT_EDGE A counter event will increase or decrease the counter by '1'. [3:2] read-write RISING_EDGE Rising edge. Any rising edge generates an event. 0 FALLING_EDGE Falling edge. Any falling edge generates an event. 1 BOTH_EDGES Rising AND falling edge. Any odd amount of edges generates an event. 2 NO_EDGE_DET No edge detection, use trigger as is. 3 RELOAD_EDGE A reload event will initialize the counter. When counting up, the counter is initialized to '0'. When counting down, the counter is initialized with PERIOD. [5:4] read-write RISING_EDGE Rising edge. Any rising edge generates an event. 0 FALLING_EDGE Falling edge. Any falling edge generates an event. 1 BOTH_EDGES Rising AND falling edge. Any odd amount of edges generates an event. 2 NO_EDGE_DET No edge detection, use trigger as is. 3 STOP_EDGE A stop event, will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter. [7:6] read-write RISING_EDGE Rising edge. Any rising edge generates an event. 0 FALLING_EDGE Falling edge. Any falling edge generates an event. 1 BOTH_EDGES Rising AND falling edge. Any odd amount of edges generates an event. 2 NO_EDGE_DET No edge detection, use trigger as is. 3 START_EDGE A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does. [9:8] read-write RISING_EDGE Rising edge. Any rising edge generates an event. 0 FALLING_EDGE Falling edge. Any falling edge generates an event. 1 BOTH_EDGES Rising AND falling edge. Any odd amount of edges generates an event. 2 NO_EDGE_DET No edge detection, use trigger as is. 3 TR_CTRL2 Counter trigger control register 2 0x28 32 read-write 0x3F 0x3F CC_MATCH_MODE Determines the effect of a compare match event (COUNTER equals CC register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation. To generate a duty cycle of 0 percent, the counter CC register should be set to '0'. For a 100 percent duty cycle, the counter CC register should be set to larger than the counter PERIOD register. [1:0] read-write SET Set to '1' 0 CLEAR Set to '0' 1 INVERT Invert 2 NO_CHANGE No Change 3 OVERFLOW_MODE Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals. [3:2] read-write SET Set to '1' 0 CLEAR Set to '0' 1 INVERT Invert 2 NO_CHANGE No Change 3 UNDERFLOW_MODE Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals. [5:4] read-write SET Set to '1' 0 CLEAR Set to '0' 1 INVERT Invert 2 NO_CHANGE No Change 3 INTR Interrupt request register 0x30 32 read-write 0x0 0x3 TC Terminal count event. Set to '1', when event is detected. Write with '1' to clear bit. [0:0] read-write CC_MATCH Counter matches CC register event. Set to '1', when event is detected. Write with '1' to clear bit. [1:1] read-write INTR_SET Interrupt set request register 0x34 32 read-write 0x0 0x3 TC Write with '1' to set corresponding bit in interrupt request register. [0:0] read-write CC_MATCH Write with '1' to set corresponding bit in interrupt request register. [1:1] read-write INTR_MASK Interrupt mask register 0x38 32 read-write 0x0 0x3 TC Mask bit for corresponding bit in interrupt request register. [0:0] read-write CC_MATCH Mask bit for corresponding bit in interrupt request register. [1:1] read-write INTR_MASKED Interrupt masked request register 0x3C 32 read-only 0x0 0x3 TC Logical and of corresponding request and mask bits. [0:0] read-only CC_MATCH Logical and of corresponding request and mask bits. [1:1] read-only SMIF0 Serial Memory Interface SMIF 0x40410000 0 65536 registers CTL Control 0x0 32 read-write 0x3000 0x81073001 XIP_MODE Mode of operation. Note: this field should only be changed when the IP is disabled or when STATUS.BUSY is '0' and SW should not be executing from the XIP interface or MMIO interface. [0:0] read-write MMIO_MODE '0': MMIO mode. Individual MMIO accesses to TX and RX FIFOs are used to generate a sequence of SPI transfers. This mode of operation allows for large flexibility in terms of the SPI transfers that can be generated. 0 XIP_MODE 1': XIP mode. eXecute-In-Place mode: incoming read and write transfers over the AHB-Lite bus infrastructure are automatically translated in SPI transfers to read data from and write data to a device. This mode of operation allow for efficient device read and write operations. This mode is only supported in SPI_MODE. 1 CLOCK_IF_RX_SEL Specifies device interface receiver clock 'clk_if_rx' source. MISO data is captured on the rising edge of 'clk_if_rx'. '0': 'spi_clk_out' (internal clock) '1': !'spi_clk_out' (internal clock) '2': 'spi_clk_in' (feedback clock) '3': !'spi_clk_in' (feedback clock) Note: the device interface transmitter clock 'clk_if_tx' is fixed and is 'spi_clk_out' MOSI data is driven on the falling edge of 'clk_if_tx'. [13:12] read-write DESELECT_DELAY Specifies the minimum duration of SPI deselection ('spi_select_out[]' is high/'1') in between SPI transfers: '0': 1 interface clock cycle. '1': 2 interface clock cycles. '2': 3 interface clock cycles. '3': 4 interface clock cycles. '4': 5 interface clock cycles. '5': 6 interface clock cycles. '6': 7 interface clock cycles. '7': 8 interface clock cycles. During SPI deselection, 'spi_select_out[]' are '1'/inactive, 'spi_data_out[]' are '1' and 'spi_clk_out' is '0'/inactive. [18:16] read-write BLOCK Specifies what happens for MMIO interface read accesses to an empty RX data FIFO or to a full TX format/data FIFO. Note: the FIFOs can only be accessed in MMIO_MODE. This field is not used for test controller accesses. [24:24] read-write BUS_ERROR 0': Generate an AHB-Lite bus error. This option is useful when SW decides to use polling on STATUS.TR_BUSY to determine if a interface transfer is no longer busy (transfer is completed). This option adds SW complexity, but limits the number of AHB-Lite wait states (and limits ISR latency). 0 WAIT_STATES 1': Introduce wait states. This setting potentially locks up the AHB-Lite infrastructure and may increase the CPU interrupt latency.This option is useful when SW performs TX/RX data FIFO accesses immediately after a command is setup using the TX format FIFO. This option has low SW complexity, but may result in a significant number of AHB-Lite wait states (and may increase ISR latency). 1 ENABLED IP enable: '0': Disabled. All non-retention registers are reset to their default value when the IP is disabled. When the IP is disabled, the XIP accesses produce AHB-Lite bus errors. '1': Enabled. Note: Before disabling the IP, SW should ensure that the IP is NOT busy (STATUS.BUSY is '0'), otherwise illegal interface transfers may occur. [31:31] read-write DISABLED N/A 0 ENABLED N/A 1 STATUS Status 0x4 32 read-only 0x0 0x80000000 BUSY Cache, cryptography, XIP, device interface or any other logic busy in the IP: '0': not busy '1': busy When BUSY is '0', the IP can be safely disabled without: - the potential loss of transient write data. - the potential risk of aborting an inflight SPI device interface transfer. When BUSY is '0', the mode of operation (XIP_MODE or MMIO_MODE) can be safely changed. [31:31] read-only TX_CMD_FIFO_STATUS Transmitter command FIFO status 0x44 32 read-only 0x0 0x7 USED3 Number of entries that are used in the TX command FIFO (available in both XIP_MODE and MMIO_MODE). Legal range: [0, 4]. [2:0] read-only TX_CMD_FIFO_WR Transmitter command FIFO write 0x50 32 write-only 0x0 0xFFFFF DATA20 Command data. The higher two bits DATA[19:18] specify the specific command '0'/TX: A SPI transfer always start with a TX command FIFO entry of the 'TX' format. - DATA[17:16] specifies the width of the data transfer: - '0': 1 bit/cycle (single data transfer). - '1': 2 bits/cycle (dual data transfer). - '2': 4 bits/cycle (quad data transfer). - '3': 8 bits/cycle (octal data transfer). - DATA[15]: specifies whether this is the last TX Byte; i.e. whether the 'spi_select_out[3:0]' IO output signals are de-activated after the transfer. - DATA[11:8] specifies which of the four devices are selected. DATA[11:8] are directly mapped to 'spi_select_out[3:0]'. Two devices can be selected at the same time in dual-quad mode. - '0': device deselected - '1': device selected - DATA[7:0] specifies the transmitted Byte. '1'/TX_COUNT: The 'TX_COUNT' command relies on the TX data FIFO to provide the transmitted bytes. The 'TX_COUNT' command is ALWAYS considered to be the last command of a SPI data transfers. - DATA[17:16] specifies the width of the transfer. - DATA[15:0] specifies the number of to be transmitted Bytes (minus 1) from the TX data FIFO. '2'/RX_COUNT: The 'RX_COUNT' command relies on the RX data FIFO to accept the received bytes. The 'RX_COUNT' command is ALWAYS considered to be the last command of a SPI data transfers. - DATA[17:16] specifies the width of the transfer. - DATA[15:0] specifies the number of to be transmitted Bytes (minus 1) to the RX data FIFO. '3'/DUMMY_COUNT: The 'DUMMY_COUNT' command conveys dummy cycles. Dummy cycles are used to implement a Turn-Around time in which the SPI master changes from a transmitter driving the data lines to a receiver receiving on the same data lines. The 'DUMMY_COUNT' command is ALWAYS considered to be NOT the last command of a SPI data transfers; i.e. it needs to be followed by another command. - DATA[15:0] specifies the number of dummy cycles (minus 1). In dummy cycles, the data lines are not driven. [19:0] write-only TX_DATA_FIFO_CTL Transmitter data FIFO control 0x80 32 read-write 0x0 0x7 TRIGGER_LEVEL Determines when the TX data FIFO 'tr_tx_req' trigger is activated (trigger activation requires MMIO_MODE, the trigger is NOT activated in XIP_MODE): - Trigger is active when TX_DATA_FIFO_STATUS.USED <= TRIGGER_LEVEL. [2:0] read-write TX_DATA_FIFO_STATUS Transmitter data FIFO status 0x84 32 read-only 0x0 0xF USED4 Number of entries that are used in the TX data FIFO (available in both XIP_MODE and MMIO_MODE). Legal range: [0, 8]. [3:0] read-only TX_DATA_FIFO_WR1 Transmitter data FIFO write 0x90 32 write-only 0x0 0xFF DATA0 TX data (written to TX data FIFO). [7:0] write-only TX_DATA_FIFO_WR2 Transmitter data FIFO write 0x94 32 write-only 0x0 0xFFFF DATA0 TX data (written to TX data FIFO, first byte). [7:0] write-only DATA1 TX data (written to TX data FIFO, second byte). [15:8] write-only TX_DATA_FIFO_WR4 Transmitter data FIFO write 0x98 32 write-only 0x0 0xFFFFFFFF DATA0 TX data (written to TX data FIFO, first byte). [7:0] write-only DATA1 TX data (written to TX data FIFO, second byte). [15:8] write-only DATA2 TX data (written to TX data FIFO, third byte). [23:16] write-only DATA3 TX data (written to TX data FIFO, fourth byte). [31:24] write-only RX_DATA_FIFO_CTL Receiver data FIFO control 0xC0 32 read-write 0x0 0x7 TRIGGER_LEVEL Determines when RX data FIFO 'tr_rx_req' trigger is activated (trigger activation requires MMIO_MODE, the trigger is NOT activated in XIP_MODE): - Trigger is active when RX_DATA_FIFO_STATUS.USED > TRIGGER_LEVEL. [2:0] read-write RX_DATA_FIFO_STATUS Receiver data FIFO status 0xC4 32 read-only 0x0 0xF USED4 Number of entries that are used in the RX data FIFO (available in both XIP_MODE and MMIO_MODE). Legal range: [0, 8]. [3:0] read-only RX_DATA_FIFO_RD1 Receiver data FIFO read 0xD0 32 read-only 0x0 0xFF DATA0 RX data (read from RX data FIFO). [7:0] read-only RX_DATA_FIFO_RD2 Receiver data FIFO read 0xD4 32 read-only 0x0 0xFFFF DATA0 RX data (read from RX data FIFO, first byte). [7:0] read-only DATA1 RX data (read from RX data FIFO, second byte). [15:8] read-only RX_DATA_FIFO_RD4 Receiver data FIFO read 0xD8 32 read-only 0x0 0xFFFFFFFF DATA0 RX data (read from RX data FIFO, first byte). [7:0] read-only DATA1 RX data (read from RX data FIFO, second byte). [15:8] read-only DATA2 RX data (read from RX data FIFO, third byte). [23:16] read-only DATA3 RX data (read from RX data FIFO, fourth byte). [31:24] read-only RX_DATA_FIFO_RD1_SILENT Receiver data FIFO silent read 0xE0 32 read-only 0x0 0xFF DATA0 RX data (read from RX data FIFO). [7:0] read-only SLOW_CA_CTL Slow cache control 0x100 32 read-write 0xC0000000 0xC3030000 WAY Specifies the cache way for which cache information is provided in SLOW_CA_STATUS0/1/2. [17:16] read-write SET_ADDR Specifies the cache set for which cache information is provided in SLOW_CA_STATUS0/1/2. [25:24] read-write PREF_EN Prefetch enable: '0': Disabled. '1': Enabled. Prefetching requires the cache to be enabled; i.e. ENABLED is '1'. [30:30] read-write ENABLED Cache enable: '0': Disabled. '1': Enabled. [31:31] read-write SLOW_CA_CMD Slow cache command 0x108 32 read-write 0x0 0x1 INV Cache and prefetch buffer invalidation. SW writes a '1' to clear the cache and prefetch buffer. The cache's LRU structure is also reset to its default state. Note, A write access will invalidate the prefetch buffer automatically in hardware. A write access should invalidate both fast and slow caches, by firmware. Note, firmware should invalidate the cache and prefetch buffer only when STATUS.BUSY is '0'. [0:0] read-write FAST_CA_CTL Fast cache control 0x180 32 read-write 0xC0000000 0xC3030000 WAY See SLOW_CA_CTL.WAY. [17:16] read-write SET_ADDR See SLOW_CA_CTL.SET_ADDR. [25:24] read-write PREF_EN See SLOW_CA_CTL.PREF_EN. [30:30] read-write ENABLED See SLOW_CA_CTL.ENABLED. [31:31] read-write FAST_CA_CMD Fast cache command 0x188 32 read-write 0x0 0x1 INV See SLOW_CA_CMD.INV. [0:0] read-write CRYPTO_CMD Cryptography Command 0x200 32 read-write 0x0 0x1 START SW sets this field to '1' to start a AES-128 forward block cipher operation (on the address in CRYPTO_ADDR). HW sets this field to '0' to indicate that the operation has completed. Once completed, the result of the operation can be read from CRYPTO_RESULT0, ..., CRYPTO_RESULT3. The operation takes roughly 13 clk_hf clock cycles. Note: An operation can only be started in MMIO_MODE. [0:0] read-write CRYPTO_INPUT0 Cryptography input 0 0x220 32 read-write 0x0 0x0 INPUT Four Bytes of the plaintext PT[31:0] = CRYPTO_INPUT0.INPUT[31:0]. [31:0] read-write CRYPTO_INPUT1 Cryptography input 1 0x224 32 read-write 0x0 0x0 INPUT Four Bytes of the plaintext PT[63:32] = CRYPTO_INPUT1.INPUT[31:0]. [31:0] read-write CRYPTO_INPUT2 Cryptography input 2 0x228 32 read-write 0x0 0x0 INPUT Four Bytes of the plaintext PT[95:64] = CRYPTO_INPUT2.INPUT[31:0]. [31:0] read-write CRYPTO_INPUT3 Cryptography input 3 0x22C 32 read-write 0x0 0x0 INPUT Four Bytes of the plaintext PT[127:96] = CRYPTO_INPUT3.INPUT[31:0]. [31:0] read-write CRYPTO_KEY0 Cryptography key 0 0x240 32 write-only 0x0 0x0 KEY Four Bytes of the key KEY[31:0] = CRYPTO_KEY0.KEY[31:0]. [31:0] write-only CRYPTO_KEY1 Cryptography key 1 0x244 32 write-only 0x0 0x0 KEY Four Bytes of the key KEY[63:32] = CRYPTO_KEY1.KEY[31:0]. [31:0] write-only CRYPTO_KEY2 Cryptography key 2 0x248 32 write-only 0x0 0x0 KEY Four Bytes of the key KEY[95:64] = CRYPTO_KEY2.KEY[31:0]. [31:0] write-only CRYPTO_KEY3 Cryptography key 3 0x24C 32 write-only 0x0 0x0 KEY Four Bytes of the key KEY[127:96] = CRYPTO_KEY3.KEY[31:0]. [31:0] write-only CRYPTO_OUTPUT0 Cryptography output 0 0x260 32 read-write 0x0 0x0 OUTPUT Four Bytes of the ciphertext CT[31:0] = CRYPTO_OUTPUT0.OUTPUT[31:0]. [31:0] read-write CRYPTO_OUTPUT1 Cryptography output 1 0x264 32 read-write 0x0 0x0 OUTPUT Four Bytes of the ciphertext CT[63:32] = CRYPTO_OUTPUT1.OUTPUT[31:0]. [31:0] read-write CRYPTO_OUTPUT2 Cryptography output 2 0x268 32 read-write 0x0 0x0 OUTPUT Four Bytes of the ciphertext CT[95:64] = CRYPTO_OUTPUT2.OUTPUT[31:0]. [31:0] read-write CRYPTO_OUTPUT3 Cryptography output 3 0x26C 32 read-write 0x0 0x0 OUTPUT Four Bytes of the ciphertext CT[127:96] = CRYPTO_OUTPUT3.OUTPUT[31:0]. [31:0] read-write INTR Interrupt register 0x7C0 32 read-write 0x0 0x3F TR_TX_REQ Activated in MMIO mode, when a TX data FIFO trigger 'tr_tx_req' is activated. [0:0] read-write TR_RX_REQ Activated in MMIO mode, when a RX data FIFO trigger 'tr_rx_req' is activated. [1:1] read-write XIP_ALIGNMENT_ERROR Activated in XIP mode, if: - The selected device's ADDR_CTL.DIV2 is '1' and the AHB-Lite bus transfer address is not a multiple of 2. - The selected device's ADDR_CTL.DIV2 is '1' and the XIP transfer request is NOT for a multiple of 2 Bytes. Note: In dual-quad SPI mode (ADDR_CTL.DIV is '1'), each memory device contributes a 4-bit nibble for read data or write data. This is only possible if the request address is a multiple of 2 and the number of requested Bytes is a multiple of 2. [2:2] read-write TX_CMD_FIFO_OVERFLOW Activated in MMIO mode, on an AHB-Lite write transfer to the TX command FIFO (TX_CMD_FIFO_WR) with not enough free entries available. [3:3] read-write TX_DATA_FIFO_OVERFLOW Activated in MMIO mode, on an AHB-Lite write transfer to the TX data FIFO (TX_DATA_FIFO_WR1, TX_DATA_FIFO_WR2, TX_DATA_FIFO_WR4) with not enough free entries available. [4:4] read-write RX_DATA_FIFO_UNDERFLOW Activated in MMIO mode, on an AHB-Lite read transfer from the RX data FIFO (RX_DATA_FIFO_RD1, RX_DATA_FIFO_RD2, RX_DATA_FIFO_RD4) with not enough entries available. Only activated for NON test bus controller transfers. [5:5] read-write INTR_SET Interrupt set register 0x7C4 32 read-write 0x0 0x3F TR_TX_REQ Write with '1' to set corresponding bit in interrupt request register. [0:0] read-write TR_RX_REQ Write with '1' to set corresponding bit in interrupt request register. [1:1] read-write XIP_ALIGNMENT_ERROR Write with '1' to set corresponding bit in interrupt request register. [2:2] read-write TX_CMD_FIFO_OVERFLOW Write with '1' to set corresponding bit in interrupt request register. [3:3] read-write TX_DATA_FIFO_OVERFLOW Write with '1' to set corresponding bit in interrupt request register. [4:4] read-write RX_DATA_FIFO_UNDERFLOW Write with '1' to set corresponding bit in interrupt request register. [5:5] read-write INTR_MASK Interrupt mask register 0x7C8 32 read-write 0x0 0x3F TR_TX_REQ Mask bit for corresponding bit in interrupt request register. [0:0] read-write TR_RX_REQ Mask bit for corresponding bit in interrupt request register. [1:1] read-write XIP_ALIGNMENT_ERROR Mask bit for corresponding bit in interrupt request register. [2:2] read-write TX_CMD_FIFO_OVERFLOW Mask bit for corresponding bit in interrupt request register. [3:3] read-write TX_DATA_FIFO_OVERFLOW Mask bit for corresponding bit in interrupt request register. [4:4] read-write RX_DATA_FIFO_UNDERFLOW Mask bit for corresponding bit in interrupt request register. [5:5] read-write INTR_MASKED Interrupt masked register 0x7CC 32 read-only 0x0 0x3F TR_TX_REQ Logical and of corresponding request and mask bits. [0:0] read-only TR_RX_REQ Logical and of corresponding request and mask bits. [1:1] read-only XIP_ALIGNMENT_ERROR Logical and of corresponding request and mask bits. [2:2] read-only TX_CMD_FIFO_OVERFLOW Logical and of corresponding request and mask bits. [3:3] read-only TX_DATA_FIFO_OVERFLOW Logical and of corresponding request and mask bits. [4:4] read-only RX_DATA_FIFO_UNDERFLOW Logical and of corresponding request and mask bits. [5:5] read-only 3 128 DEVICE[%s] Device (only used in XIP mode) 0x00000800 CTL Control 0x0 32 read-write 0x0 0x80030101 WR_EN Write enable: '0': write transfers are not allowed to this device. An attempt to write to this device results in an AHB-Lite bus error. '1': write transfers are allowed to this device. [0:0] read-write CRYPTO_EN Cryptography on read/write accesses: '0': disabled. '1': enabled. [8:8] read-write DATA_SEL Specifies the connection of the IP's data lines (spi_data[0], ..., spi_data[7]) to the device's data lines (SI/IO0, SO/IO1, IO2, IO3, IO4, IO5, IO6, IO7): '0': spi_data[0] = IO0, spi_data[1] = IO1, ..., spi_data[7] = IO7. This value is allowed for single, dual, quad, dual quad and octal SPI modes. This value must be used for the first device in dual quad SPI mode. This value must be used for octal SPI mode. '1': spi_data[2] = IO0, spi_data[3] = IO1. This value is only allowed for single and dual SPI modes. '2': spi_data[4] = IO0, spi_data[5] = IO1, ..., spi_data[7] = IO3. This value is only allowed for single, dual, quad and dual quad SPI modes. In dual quad SPI mode, this value must be used for the second device. '3': spi_data[6] = IO0, spi_data[7] = IO1. This value is only allowed for single and dual SPI modes. [17:16] read-write ENABLED Device enable: '0': Disabled. '1': Enabled. [31:31] read-write ADDR Device region base address 0x8 32 read-write 0x0 0x0 ADDR Specifies the base address of the device region. If the device region is 2^m Bytes, ADDR MUST be a multiple of 2^m. In dual quad SPI data transfer, the two devices should have the same ADDR and MASK register settings. The device control information (ADDR_CTL, RD_CMD_CTL, etc.) are provided by the MMIO control registers of the device with the lowest index. The most significant bit fields are constants and set based on the SMIF_XIP_ADDR parameter. The most significant bits are identified on the SMIF_XIP_MASK parameter. E.g., if SMIF_XIP_MASK is 0xff00:0000 (16 MB XIP memory region), ADDR[31:24] = SMIF_XIP_ADDR[31:24]. [31:8] read-write MASK Device region mask 0xC 32 read-write 0x0 0x0 MASK Specifies the size of the device region. All '1' bits are used to compare the incoming transfer request address A[31:0] with the address as specified in ADDR.ADDR: Address A is in the device when (A[31:8] & MASK[31:8]) == ADDR.ADDR[31:8]. The most significant bit fields are constants and set to'1'. The most significant bits are identified on the SMIF_XIP_MASK parameter. E.g., if SMIF_XIP_MASK is 0xff00:0000 (16 MB XIP memory region), MASK[31:24] = 0xff. Note: a transfer request that is not in any device region results in an AHB-Lite bus error. [31:8] read-write ADDR_CTL Address control 0x20 32 read-write 0x0 0x103 SIZE2 Specifies the size of the XIP device address in Bytes: '0': 1 Byte address. '1': 2 Byte address. '2': 3 Byte address. '3': 4 Byte address. The lower significant address Bytes of the transfer request are used as XIP address to the external device. Note that for dual quad SPI data transfer, the transfer request address is divided by 2. Therefore, the transfer request address needs to be a multiple of 2. If the trasnfer requestaddress is NOT a multiple of 2, the XIP_ALIGNMENT_ERROR interrupt cause is activated. [1:0] read-write DIV2 Specifies if the AHB-Lite bus transfer address is divided by 2 or not: '0': No divide by 2. '1': Divide by 2. This functionality is used for read and write operation in XIP, dual quad SPI mode; i.e. this DIV2 must be set to '1' in dual quad SPI mode. If the transfer request address is NOT a multiple of 2 or the requested number of Bytes is not a multiple of 2, the XIP_ALIGNMENT_ERROR interrupt cause is activated. [8:8] read-write RD_CMD_CTL Read command control 0x40 32 read-write 0x0 0x800300FF CODE Command byte code. [7:0] read-write WIDTH Width of data transfer: '0': 1 bit/cycle (single data transfer). '1': 2 bits/cycle (dual data transfer). '2': 4 bits/cycle (quad data transfer). '3': 8 bits/cycle (octal data transfer). [17:16] read-write PRESENT Presence of command field: '0': not present '1': present [31:31] read-write RD_ADDR_CTL Read address control 0x44 32 read-write 0x0 0x30000 WIDTH Width of transfer. [17:16] read-write RD_MODE_CTL Read mode control 0x48 32 read-write 0x0 0x800300FF CODE Mode byte code. [7:0] read-write WIDTH Width of transfer. [17:16] read-write PRESENT Presence of mode field: '0': not present '1': present [31:31] read-write RD_DUMMY_CTL Read dummy control 0x4C 32 read-write 0x0 0x8000001F SIZE5 Number of dummy cycles (minus 1): '0': 1 cycles ... '31': 32 cycles. Note: this field specifies dummy cycles, not dummy Bytes! [4:0] read-write PRESENT Presence of dummy cycles: '0': not present '1': present [31:31] read-write RD_DATA_CTL Read data control 0x50 32 read-write 0x0 0x30000 WIDTH Width of transfer. [17:16] read-write WR_CMD_CTL Write command control 0x60 32 read-write 0x0 0x800300FF CODE Command byte code. [7:0] read-write WIDTH Width of transfer. [17:16] read-write PRESENT Presence of command field: '0': not present '1': present [31:31] read-write WR_ADDR_CTL Write address control 0x64 32 read-write 0x0 0x30000 WIDTH Width of transfer. [17:16] read-write WR_MODE_CTL Write mode control 0x68 32 read-write 0x0 0x800300FF CODE Mode byte code. [7:0] read-write WIDTH Width of transfer. [17:16] read-write PRESENT Presence of mode field: '0': not present '1': present [31:31] read-write WR_DUMMY_CTL Write dummy control 0x6C 32 read-write 0x0 0x8000001F SIZE5 Number of dummy cycles (minus 1): '0': 1 cycles ... '31': 32 cycles. [4:0] read-write PRESENT Presence of dummy cycles: '0': not present '1': present [31:31] read-write WR_DATA_CTL Write data control 0x70 32 read-write 0x0 0x30000 WIDTH Width of transfer. [17:16] read-write USBFS0 USB Host and Device Controller USBFS 0x40420000 0 65536 registers USBDEV USB Device 0x00000000 8 4 EP0_DR[%s] Control End point EP0 Data Register 0x0 32 read-write 0x0 0xFF DATA_BYTE This register is shared for both transmit and receive. The count in the EP0_CNT register determines the number of bytes received or to be transferred. [7:0] read-write CR0 USB control 0 Register 0x20 32 read-write 0x0 0xFF DEVICE_ADDRESS These bits specify the USB device address to which the SIE will respond. This address must be set by firmware and is specified by the USB Host with a SET ADDRESS command during USB enumeration. This value must be programmed by firmware when assigned during enumeration. It is not set automatically by the hardware. If USB bus reset is detected, these bits are initialized. [6:0] read-write USB_ENABLE This bit enables the device to respond to USB traffic. If USB bus reset is detected, this bit is cleared. Note: When USB PHY is GPIO mode(USBIO_CR1.IOMODE=0), USB bus reset is detected. Therefore, when USB PHY is GPIO mode, this bit is cleared even if this bit is set to 1. If this bit is set to 1, write this bit upon USB bus reset interrupt, and do not write to this bit during initialization steps. [7:7] read-write CR1 USB control 1 Register 0x24 32 read-write 0x0 0xF REG_ENABLE This bit controls the operation of the internal USB regulator. For applications with supply voltages in the 5V range this bit is set high to enable the internal regulator. For device supply voltage in the 3.3V range this bit is cleared to connect the transceiver directly to the supply. [0:0] read-write ENABLE_LOCK This bit is set to turn on the automatic frequency locking of the internal oscillator to USB traffic. Unless an external clock is being provided this bit should remain set for proper USB operation. [1:1] read-write BUS_ACTIVITY The Bus Activity bit is a stickybit that detects any non-idle USB event that has occurred on the USB bus. Once set to High by the SIE to indicate the bus activity this bit retains its logical High value until firmware clears it. [2:2] read-write RSVD_3 N/A [3:3] read-write SIE_EP_INT_EN USB SIE Data Endpoints Interrupt Enable Register 0x28 32 read-write 0x0 0xFF EP1_INTR_EN Enables interrupt for EP1 [0:0] read-write EP2_INTR_EN Enables interrupt for EP2 [1:1] read-write EP3_INTR_EN Enables interrupt for EP3 [2:2] read-write EP4_INTR_EN Enables interrupt for EP4 [3:3] read-write EP5_INTR_EN Enables interrupt for EP5 [4:4] read-write EP6_INTR_EN Enables interrupt for EP6 [5:5] read-write EP7_INTR_EN Enables interrupt for EP7 [6:6] read-write EP8_INTR_EN Enables interrupt for EP8 [7:7] read-write SIE_EP_INT_SR USB SIE Data Endpoint Interrupt Status 0x2C 32 read-write 0x0 0xFF EP1_INTR Interrupt status for EP1 [0:0] read-write EP2_INTR Interrupt status for EP2 [1:1] read-write EP3_INTR Interrupt status for EP3 [2:2] read-write EP4_INTR Interrupt status for EP4 [3:3] read-write EP5_INTR Interrupt status for EP5 [4:4] read-write EP6_INTR Interrupt status for EP6 [5:5] read-write EP7_INTR Interrupt status for EP7 [6:6] read-write EP8_INTR Interrupt status for EP8 [7:7] read-write SIE_EP1_CNT0 Non-control endpoint count register 0x30 32 read-write 0x0 0xC7 DATA_COUNT_MSB These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. [2:0] read-write DATA_VALID This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. [6:6] read-write DATA_ERROR No ACK'd transactions since bit was last cleared. 0 DATA_VALID Indicates a transaction ended with an ACK. 1 DATA_TOGGLE This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. [7:7] read-write SIE_EP1_CNT1 Non-control endpoint count register 0x34 32 read-write 0x0 0xFF DATA_COUNT These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. [7:0] read-write SIE_EP1_CR0 Non-control endpoint's control Register 0x38 32 read-write 0x0 0xFF MODE The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. [3:0] read-write DISABLE Ignore all USB traffic to this endpoint 0 NAK_INOUT SETUP: Accept IN: NAK OUT: NAK 1 STATUS_OUT_ONLY SETUP: Accept IN: STALL OUT: ACK 0B tokens, NAK others 2 STALL_INOUT SETUP: Accept IN: STALL OUT: STALL 3 ISO_OUT SETUP: Ignore IN: Ignore OUT: Accept Isochronous OUT token 5 STATUS_IN_ONLY SETUP: Accept IN: Respond with 0B data OUT: Stall 6 ISO_IN SETUP: Ignore IN: Accept Isochronous IN token OUT: Ignore 7 NAK_OUT SETUP: Ignore IN: Ignore OUT: NAK 8 ACK_OUT SETUP: Ignore IN: Ignore OUT: Accept data and ACK if STALL=0, STALL otherwise. Change to MODE=8 after one succesfull OUT token. 9 ACK_OUT_STATUS_IN SETUP: Accept IN: Respond with 0B data OUT: Accept data 11 NAK_IN SETUP: Ignore IN: NAK OUT: Ignore 12 ACK_IN SETUP: Ignore IN: Respond to IN with data if STALL=0, STALL otherwise OUT: Ignore 13 ACK_IN_STATUS_OUT SETUP: Accept IN: Respond to IN with data OUT: ACK 0B tokens, NAK others 15 ACKED_TXN The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. [4:4] read-write ACKED_NO No ACK'd transactions since bit was last cleared. 0 ACKED_YES Indicates a transaction ended with an ACK. 1 NAK_INT_EN When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. [5:5] read-write ERR_IN_TXN The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. [6:6] read-write STALL When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. [7:7] read-write USBIO_CR0 USBIO Control 0 Register 0x40 32 read-write 0x0 0xE0 RD Received Data. This read only bit gives the state of the USB differential receiver when IOMODE bit is '0' and USB doesn't transmit. This bit is valid if USB Device. If D+=D- (SE0), this value is undefined. [0:0] read-only DIFF_LOW D+ < D- (K state) 0 DIFF_HIGH D+ > D- (J state) 1 TD Transmit Data. Transmit a USB J or K state on the USB bus. No effect if TEN=0 or TSE0=1. [5:5] read-write DIFF_K Force USB K state (D+ is low D- is high). 0 DIFF_J Force USB J state (D+ is high D- is low). 1 TSE0 Transmit Single-Ended Zero. SE0: both D+ and D- low. No effect if TEN=0. [6:6] read-write TEN USB Transmit Enable. This is used to manually transmit on the D+ and D- pins. Normally this bit should be cleared to allow the internal SIE to drive the pins. The most common reason for manually transmitting is to force a resume state on the bus. [7:7] read-write USBIO_CR2 USBIO control 2 Register 0x44 32 read-write 0x0 0xFF RSVD_5_0 N/A [5:0] read-only TEST_PKT This bit enables the device to transmit a packet in response to an internally generated IN packet. When set, one packet will be generated. [6:6] read-write RSVD_7 N/A [7:7] read-write USBIO_CR1 USBIO control 1 Register 0x48 32 read-write 0x20 0x20 DMO This read only bit gives the state of the D- pin when IOMODE bit is '0' and USB doesn't transmit. This bit is '0' when USB transmits SE0, and this bit is '1' when USB transmits other than SE0. This bit is valid if USB Device. [0:0] read-only DPO This read only bit gives the state of the D+ pin when IOMODE bit is '0' and USB doesn't transmit. This bit displays the output value of D+ pin when USB transmits SE0 or data. This bit is valid if USB Device. [1:1] read-only RSVD_2 N/A [2:2] read-write IOMODE This bit allows the D+ and D- pins to be configured for either USB mode or bit-banged modes. If this bit is set the DMI and DPI bits are used to drive the D- and D+ pins. [5:5] read-write DYN_RECONFIG USB Dynamic reconfiguration register 0x50 32 read-write 0x0 0x1F DYN_CONFIG_EN This bit is used to enable the dynamic re-configuration for the selected EP. If set to 1, indicates the reconfiguration required for selected EP. Use 0 for EP1, 1 for EP2, etc. [0:0] read-write DYN_RECONFIG_EPNO These bits indicates the EP number for which reconfiguration is required when dyn_config_en bit is set to 1. [3:1] read-write DYN_RECONFIG_RDY_STS This bit indicates the ready status for the dynamic reconfiguration, when set to 1, indicates the block is ready for reconfiguration. [4:4] read-only SOF0 Start Of Frame Register 0x60 32 read-only 0x0 0xFF FRAME_NUMBER It has the lower 8 bits [7:0] of the SOF frame number. [7:0] read-only SOF1 Start Of Frame Register 0x64 32 read-only 0x0 0x7 FRAME_NUMBER_MSB It has the upper 3 bits [10:8] of the SOF frame number. [2:0] read-only SIE_EP2_CNT0 Non-control endpoint count register 0x70 32 read-write 0x0 0xC7 DATA_COUNT_MSB These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. [2:0] read-write DATA_VALID This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. [6:6] read-write DATA_ERROR No ACK'd transactions since bit was last cleared. 0 DATA_VALID Indicates a transaction ended with an ACK. 1 DATA_TOGGLE This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. [7:7] read-write SIE_EP2_CNT1 Non-control endpoint count register 0x74 32 read-write 0x0 0xFF DATA_COUNT These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. [7:0] read-write SIE_EP2_CR0 Non-control endpoint's control Register 0x78 32 read-write 0x0 0xFF MODE The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. [3:0] read-write DISABLE Ignore all USB traffic to this endpoint 0 NAK_INOUT SETUP: Accept IN: NAK OUT: NAK 1 STATUS_OUT_ONLY SETUP: Accept IN: STALL OUT: ACK 0B tokens, NAK others 2 STALL_INOUT SETUP: Accept IN: STALL OUT: STALL 3 ISO_OUT SETUP: Ignore IN: Ignore OUT: Accept Isochronous OUT token 5 STATUS_IN_ONLY SETUP: Accept IN: Respond with 0B data OUT: Stall 6 ISO_IN SETUP: Ignore IN: Accept Isochronous IN token OUT: Ignore 7 NAK_OUT SETUP: Ignore IN: Ignore OUT: NAK 8 ACK_OUT SETUP: Ignore IN: Ignore OUT: Accept data and ACK if STALL=0, STALL otherwise. Change to MODE=8 after one succesfull OUT token. 9 ACK_OUT_STATUS_IN SETUP: Accept IN: Respond with 0B data OUT: Accept data 11 NAK_IN SETUP: Ignore IN: NAK OUT: Ignore 12 ACK_IN SETUP: Ignore IN: Respond to IN with data if STALL=0, STALL otherwise OUT: Ignore 13 ACK_IN_STATUS_OUT SETUP: Accept IN: Respond to IN with data OUT: ACK 0B tokens, NAK others 15 ACKED_TXN The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. [4:4] read-write ACKED_NO No ACK'd transactions since bit was last cleared. 0 ACKED_YES Indicates a transaction ended with an ACK. 1 NAK_INT_EN When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. [5:5] read-write ERR_IN_TXN The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. [6:6] read-write STALL When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. [7:7] read-write OSCLK_DR0 Oscillator lock data register 0 0x80 32 read-only 0x0 0x0 ADDER These bits return the lower 8 bits of the oscillator locking circuits adder output. [7:0] read-only OSCLK_DR1 Oscillator lock data register 1 0x84 32 read-only 0x0 0x0 ADDER_MSB These bits return the upper 7 bits of the oscillator locking circuits adder output. [6:0] read-only EP0_CR Endpoint0 control Register 0xA0 32 read-write 0x0 0xFF MODE The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. [3:0] read-write DISABLE Ignore all USB traffic to this endpoint 0 NAK_INOUT SETUP: Accept IN: NAK OUT: NAK 1 STATUS_OUT_ONLY SETUP: Accept IN: STALL OUT: ACK 0B tokens, NAK others 2 STALL_INOUT SETUP: Accept IN: STALL OUT: STALL 3 ISO_OUT SETUP: Ignore IN: Ignore OUT: Accept Isochronous OUT token 5 STATUS_IN_ONLY SETUP: Accept IN: Respond with 0B data OUT: Stall 6 ISO_IN SETUP: Ignore IN: Accept Isochronous IN token OUT: Ignore 7 NAK_OUT SETUP: Ignore IN: Ignore OUT: NAK 8 ACK_OUT SETUP: Ignore IN: Ignore OUT: Accept data and ACK if STALL=0, STALL otherwise. Change to MODE=8 after one succesfull OUT token. 9 ACK_OUT_STATUS_IN SETUP: Accept IN: Respond with 0B data OUT: Accept data 11 NAK_IN SETUP: Ignore IN: NAK OUT: Ignore 12 ACK_IN SETUP: Ignore IN: Respond to IN with data if STALL=0, STALL otherwise OUT: Ignore 13 ACK_IN_STATUS_OUT SETUP: Accept IN: Respond to IN with data OUT: ACK 0B tokens, NAK others 15 ACKED_TXN The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. [4:4] read-write ACKED_NO No ACK'd transactions since bit was last cleared. 0 ACKED_YES Indicates a transaction ended with an ACK. 1 OUT_RCVD When set this bit indicates a valid OUT packet has been received and ACKed. This bit is updated to '1' after the last received packet in an OUT transaction. When clear this bit indicates no OUT received. It is cleared by any writes to the register. [5:5] read-write IN_RCVD When set this bit indicates a valid IN packet has been received. This bit is updated to '1' after the host acknowledges an IN data packet. When clear this bit indicates either no IN has been received or that the host did not acknowledge the IN data by sending ACK handshake. It is cleared by any writes to the register. [6:6] read-write SETUP_RCVD When set this bit indicates a valid SETUP packet was received and ACKed. This bit is forced HIGH from the start of the data packet phase of the SETUP transaction until the start of the ACK packet returned by the SIE. The CPU is prevented from clearing this bit during this interval. After this interval the bit will remain set until cleared by firmware. While this bit is set to '1' the CPU cannot write to the EP0_DRx registers. This prevents firmware from overwriting an incoming SETUP transaction before firmware has a chance to read the SETUP data. This bit is cleared by any non-locked writes to the register. [7:7] read-write EP0_CNT Endpoint0 count Register 0xA4 32 read-write 0x0 0xCF BYTE_COUNT These bits indicate the number of data bytes in a transaction. For IN transactions firmware loads the count with the number of bytes to be transmitted to the host from the endpoint FIFO. Valid values are 0 to 8. For OUT or SETUP transactions the count is updated by hardware to the number of data bytes received plus two for the CRC bytes. Valid values are 2 to 10. [3:0] read-write DATA_VALID This bit is used for OUT/SETUP transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. [6:6] read-write DATA_ERROR No ACK'd transactions since bit was last cleared. 0 DATA_VALID Indicates a transaction ended with an ACK. 1 DATA_TOGGLE This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. [7:7] read-write SIE_EP3_CNT0 Non-control endpoint count register 0xB0 32 read-write 0x0 0xC7 DATA_COUNT_MSB These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. [2:0] read-write DATA_VALID This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. [6:6] read-write DATA_ERROR No ACK'd transactions since bit was last cleared. 0 DATA_VALID Indicates a transaction ended with an ACK. 1 DATA_TOGGLE This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. [7:7] read-write SIE_EP3_CNT1 Non-control endpoint count register 0xB4 32 read-write 0x0 0xFF DATA_COUNT These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. [7:0] read-write SIE_EP3_CR0 Non-control endpoint's control Register 0xB8 32 read-write 0x0 0xFF MODE The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. [3:0] read-write DISABLE Ignore all USB traffic to this endpoint 0 NAK_INOUT SETUP: Accept IN: NAK OUT: NAK 1 STATUS_OUT_ONLY SETUP: Accept IN: STALL OUT: ACK 0B tokens, NAK others 2 STALL_INOUT SETUP: Accept IN: STALL OUT: STALL 3 ISO_OUT SETUP: Ignore IN: Ignore OUT: Accept Isochronous OUT token 5 STATUS_IN_ONLY SETUP: Accept IN: Respond with 0B data OUT: Stall 6 ISO_IN SETUP: Ignore IN: Accept Isochronous IN token OUT: Ignore 7 NAK_OUT SETUP: Ignore IN: Ignore OUT: NAK 8 ACK_OUT SETUP: Ignore IN: Ignore OUT: Accept data and ACK if STALL=0, STALL otherwise. Change to MODE=8 after one succesfull OUT token. 9 ACK_OUT_STATUS_IN SETUP: Accept IN: Respond with 0B data OUT: Accept data 11 NAK_IN SETUP: Ignore IN: NAK OUT: Ignore 12 ACK_IN SETUP: Ignore IN: Respond to IN with data if STALL=0, STALL otherwise OUT: Ignore 13 ACK_IN_STATUS_OUT SETUP: Accept IN: Respond to IN with data OUT: ACK 0B tokens, NAK others 15 ACKED_TXN The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. [4:4] read-write ACKED_NO No ACK'd transactions since bit was last cleared. 0 ACKED_YES Indicates a transaction ended with an ACK. 1 NAK_INT_EN When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. [5:5] read-write ERR_IN_TXN The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. [6:6] read-write STALL When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. [7:7] read-write SIE_EP4_CNT0 Non-control endpoint count register 0xF0 32 read-write 0x0 0xC7 DATA_COUNT_MSB These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. [2:0] read-write DATA_VALID This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. [6:6] read-write DATA_ERROR No ACK'd transactions since bit was last cleared. 0 DATA_VALID Indicates a transaction ended with an ACK. 1 DATA_TOGGLE This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. [7:7] read-write SIE_EP4_CNT1 Non-control endpoint count register 0xF4 32 read-write 0x0 0xFF DATA_COUNT These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. [7:0] read-write SIE_EP4_CR0 Non-control endpoint's control Register 0xF8 32 read-write 0x0 0xFF MODE The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. [3:0] read-write DISABLE Ignore all USB traffic to this endpoint 0 NAK_INOUT SETUP: Accept IN: NAK OUT: NAK 1 STATUS_OUT_ONLY SETUP: Accept IN: STALL OUT: ACK 0B tokens, NAK others 2 STALL_INOUT SETUP: Accept IN: STALL OUT: STALL 3 ISO_OUT SETUP: Ignore IN: Ignore OUT: Accept Isochronous OUT token 5 STATUS_IN_ONLY SETUP: Accept IN: Respond with 0B data OUT: Stall 6 ISO_IN SETUP: Ignore IN: Accept Isochronous IN token OUT: Ignore 7 NAK_OUT SETUP: Ignore IN: Ignore OUT: NAK 8 ACK_OUT SETUP: Ignore IN: Ignore OUT: Accept data and ACK if STALL=0, STALL otherwise. Change to MODE=8 after one succesfull OUT token. 9 ACK_OUT_STATUS_IN SETUP: Accept IN: Respond with 0B data OUT: Accept data 11 NAK_IN SETUP: Ignore IN: NAK OUT: Ignore 12 ACK_IN SETUP: Ignore IN: Respond to IN with data if STALL=0, STALL otherwise OUT: Ignore 13 ACK_IN_STATUS_OUT SETUP: Accept IN: Respond to IN with data OUT: ACK 0B tokens, NAK others 15 ACKED_TXN The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. [4:4] read-write ACKED_NO No ACK'd transactions since bit was last cleared. 0 ACKED_YES Indicates a transaction ended with an ACK. 1 NAK_INT_EN When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. [5:5] read-write ERR_IN_TXN The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. [6:6] read-write STALL When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. [7:7] read-write SIE_EP5_CNT0 Non-control endpoint count register 0x130 32 read-write 0x0 0xC7 DATA_COUNT_MSB These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. [2:0] read-write DATA_VALID This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. [6:6] read-write DATA_ERROR No ACK'd transactions since bit was last cleared. 0 DATA_VALID Indicates a transaction ended with an ACK. 1 DATA_TOGGLE This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. [7:7] read-write SIE_EP5_CNT1 Non-control endpoint count register 0x134 32 read-write 0x0 0xFF DATA_COUNT These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. [7:0] read-write SIE_EP5_CR0 Non-control endpoint's control Register 0x138 32 read-write 0x0 0xFF MODE The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. [3:0] read-write DISABLE Ignore all USB traffic to this endpoint 0 NAK_INOUT SETUP: Accept IN: NAK OUT: NAK 1 STATUS_OUT_ONLY SETUP: Accept IN: STALL OUT: ACK 0B tokens, NAK others 2 STALL_INOUT SETUP: Accept IN: STALL OUT: STALL 3 ISO_OUT SETUP: Ignore IN: Ignore OUT: Accept Isochronous OUT token 5 STATUS_IN_ONLY SETUP: Accept IN: Respond with 0B data OUT: Stall 6 ISO_IN SETUP: Ignore IN: Accept Isochronous IN token OUT: Ignore 7 NAK_OUT SETUP: Ignore IN: Ignore OUT: NAK 8 ACK_OUT SETUP: Ignore IN: Ignore OUT: Accept data and ACK if STALL=0, STALL otherwise. Change to MODE=8 after one succesfull OUT token. 9 ACK_OUT_STATUS_IN SETUP: Accept IN: Respond with 0B data OUT: Accept data 11 NAK_IN SETUP: Ignore IN: NAK OUT: Ignore 12 ACK_IN SETUP: Ignore IN: Respond to IN with data if STALL=0, STALL otherwise OUT: Ignore 13 ACK_IN_STATUS_OUT SETUP: Accept IN: Respond to IN with data OUT: ACK 0B tokens, NAK others 15 ACKED_TXN The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. [4:4] read-write ACKED_NO No ACK'd transactions since bit was last cleared. 0 ACKED_YES Indicates a transaction ended with an ACK. 1 NAK_INT_EN When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. [5:5] read-write ERR_IN_TXN The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. [6:6] read-write STALL When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. [7:7] read-write SIE_EP6_CNT0 Non-control endpoint count register 0x170 32 read-write 0x0 0xC7 DATA_COUNT_MSB These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. [2:0] read-write DATA_VALID This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. [6:6] read-write DATA_ERROR No ACK'd transactions since bit was last cleared. 0 DATA_VALID Indicates a transaction ended with an ACK. 1 DATA_TOGGLE This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. [7:7] read-write SIE_EP6_CNT1 Non-control endpoint count register 0x174 32 read-write 0x0 0xFF DATA_COUNT These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. [7:0] read-write SIE_EP6_CR0 Non-control endpoint's control Register 0x178 32 read-write 0x0 0xFF MODE The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. [3:0] read-write DISABLE Ignore all USB traffic to this endpoint 0 NAK_INOUT SETUP: Accept IN: NAK OUT: NAK 1 STATUS_OUT_ONLY SETUP: Accept IN: STALL OUT: ACK 0B tokens, NAK others 2 STALL_INOUT SETUP: Accept IN: STALL OUT: STALL 3 ISO_OUT SETUP: Ignore IN: Ignore OUT: Accept Isochronous OUT token 5 STATUS_IN_ONLY SETUP: Accept IN: Respond with 0B data OUT: Stall 6 ISO_IN SETUP: Ignore IN: Accept Isochronous IN token OUT: Ignore 7 NAK_OUT SETUP: Ignore IN: Ignore OUT: NAK 8 ACK_OUT SETUP: Ignore IN: Ignore OUT: Accept data and ACK if STALL=0, STALL otherwise. Change to MODE=8 after one succesfull OUT token. 9 ACK_OUT_STATUS_IN SETUP: Accept IN: Respond with 0B data OUT: Accept data 11 NAK_IN SETUP: Ignore IN: NAK OUT: Ignore 12 ACK_IN SETUP: Ignore IN: Respond to IN with data if STALL=0, STALL otherwise OUT: Ignore 13 ACK_IN_STATUS_OUT SETUP: Accept IN: Respond to IN with data OUT: ACK 0B tokens, NAK others 15 ACKED_TXN The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. [4:4] read-write ACKED_NO No ACK'd transactions since bit was last cleared. 0 ACKED_YES Indicates a transaction ended with an ACK. 1 NAK_INT_EN When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. [5:5] read-write ERR_IN_TXN The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. [6:6] read-write STALL When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. [7:7] read-write SIE_EP7_CNT0 Non-control endpoint count register 0x1B0 32 read-write 0x0 0xC7 DATA_COUNT_MSB These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. [2:0] read-write DATA_VALID This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. [6:6] read-write DATA_ERROR No ACK'd transactions since bit was last cleared. 0 DATA_VALID Indicates a transaction ended with an ACK. 1 DATA_TOGGLE This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. [7:7] read-write SIE_EP7_CNT1 Non-control endpoint count register 0x1B4 32 read-write 0x0 0xFF DATA_COUNT These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. [7:0] read-write SIE_EP7_CR0 Non-control endpoint's control Register 0x1B8 32 read-write 0x0 0xFF MODE The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. [3:0] read-write DISABLE Ignore all USB traffic to this endpoint 0 NAK_INOUT SETUP: Accept IN: NAK OUT: NAK 1 STATUS_OUT_ONLY SETUP: Accept IN: STALL OUT: ACK 0B tokens, NAK others 2 STALL_INOUT SETUP: Accept IN: STALL OUT: STALL 3 ISO_OUT SETUP: Ignore IN: Ignore OUT: Accept Isochronous OUT token 5 STATUS_IN_ONLY SETUP: Accept IN: Respond with 0B data OUT: Stall 6 ISO_IN SETUP: Ignore IN: Accept Isochronous IN token OUT: Ignore 7 NAK_OUT SETUP: Ignore IN: Ignore OUT: NAK 8 ACK_OUT SETUP: Ignore IN: Ignore OUT: Accept data and ACK if STALL=0, STALL otherwise. Change to MODE=8 after one succesfull OUT token. 9 ACK_OUT_STATUS_IN SETUP: Accept IN: Respond with 0B data OUT: Accept data 11 NAK_IN SETUP: Ignore IN: NAK OUT: Ignore 12 ACK_IN SETUP: Ignore IN: Respond to IN with data if STALL=0, STALL otherwise OUT: Ignore 13 ACK_IN_STATUS_OUT SETUP: Accept IN: Respond to IN with data OUT: ACK 0B tokens, NAK others 15 ACKED_TXN The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. [4:4] read-write ACKED_NO No ACK'd transactions since bit was last cleared. 0 ACKED_YES Indicates a transaction ended with an ACK. 1 NAK_INT_EN When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. [5:5] read-write ERR_IN_TXN The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. [6:6] read-write STALL When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. [7:7] read-write SIE_EP8_CNT0 Non-control endpoint count register 0x1F0 32 read-write 0x0 0xC7 DATA_COUNT_MSB These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. [2:0] read-write DATA_VALID This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. [6:6] read-write DATA_ERROR No ACK'd transactions since bit was last cleared. 0 DATA_VALID Indicates a transaction ended with an ACK. 1 DATA_TOGGLE This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. [7:7] read-write SIE_EP8_CNT1 Non-control endpoint count register 0x1F4 32 read-write 0x0 0xFF DATA_COUNT These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. [7:0] read-write SIE_EP8_CR0 Non-control endpoint's control Register 0x1F8 32 read-write 0x0 0xFF MODE The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. [3:0] read-write DISABLE Ignore all USB traffic to this endpoint 0 NAK_INOUT SETUP: Accept IN: NAK OUT: NAK 1 STATUS_OUT_ONLY SETUP: Accept IN: STALL OUT: ACK 0B tokens, NAK others 2 STALL_INOUT SETUP: Accept IN: STALL OUT: STALL 3 ISO_OUT SETUP: Ignore IN: Ignore OUT: Accept Isochronous OUT token 5 STATUS_IN_ONLY SETUP: Accept IN: Respond with 0B data OUT: Stall 6 ISO_IN SETUP: Ignore IN: Accept Isochronous IN token OUT: Ignore 7 NAK_OUT SETUP: Ignore IN: Ignore OUT: NAK 8 ACK_OUT SETUP: Ignore IN: Ignore OUT: Accept data and ACK if STALL=0, STALL otherwise. Change to MODE=8 after one succesfull OUT token. 9 ACK_OUT_STATUS_IN SETUP: Accept IN: Respond with 0B data OUT: Accept data 11 NAK_IN SETUP: Ignore IN: NAK OUT: Ignore 12 ACK_IN SETUP: Ignore IN: Respond to IN with data if STALL=0, STALL otherwise OUT: Ignore 13 ACK_IN_STATUS_OUT SETUP: Accept IN: Respond to IN with data OUT: ACK 0B tokens, NAK others 15 ACKED_TXN The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. [4:4] read-write ACKED_NO No ACK'd transactions since bit was last cleared. 0 ACKED_YES Indicates a transaction ended with an ACK. 1 NAK_INT_EN When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. [5:5] read-write ERR_IN_TXN The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. [6:6] read-write STALL When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. [7:7] read-write ARB_EP1_CFG Endpoint Configuration Register *1 0x200 32 read-write 0x0 0xF IN_DATA_RDY Indication that Endpoint Packet Data is Ready in Main memory [0:0] read-write DMA_REQ Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. [1:1] read-write CRC_BYPASS Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware [2:2] read-write CRC_NORMAL No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s 0 CRC_BYPASS CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s 1 RESET_PTR Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. [3:3] read-write RESET_KRYPTON Do not Reset Pointer; Krypton Backward compatibility mode 0 RESET_NORMAL Reset Pointer; recommended value for reduction of CPU Configuration Writes. 1 ARB_EP1_INT_EN Endpoint Interrupt Enable Register *1 0x204 32 read-write 0x0 0x3F IN_BUF_FULL_EN IN Endpoint Local Buffer Full Enable [0:0] read-write DMA_GNT_EN Endpoint DMA Grant Enable [1:1] read-write BUF_OVER_EN Endpoint Buffer Overflow Enable [2:2] read-write BUF_UNDER_EN Endpoint Buffer Underflow Enable [3:3] read-write ERR_INT_EN Endpoint Error in Transaction Interrupt Enable [4:4] read-write DMA_TERMIN_EN Endpoint DMA Terminated Enable [5:5] read-write ARB_EP1_SR Endpoint Interrupt Enable Register *1 0x208 32 read-write 0x0 0x2F IN_BUF_FULL IN Endpoint Local Buffer Full Interrupt [0:0] read-write DMA_GNT Endpoint DMA Grant Interrupt [1:1] read-write BUF_OVER Endpoint Buffer Overflow Interrupt [2:2] read-write BUF_UNDER Endpoint Buffer Underflow Interrupt [3:3] read-write DMA_TERMIN Endpoint DMA Terminated Interrupt [5:5] read-write ARB_RW1_WA Endpoint Write Address value *1, *2 0x210 32 read-write 0x0 0xFF WA Write Address for EP [7:0] read-write ARB_RW1_WA_MSB Endpoint Write Address value *1, *2 0x214 32 read-write 0x0 0x1 WA_MSB Write Address for EP [0:0] read-write ARB_RW1_RA Endpoint Read Address value *1, *2 0x218 32 read-write 0x0 0xFF RA Read Address for EP [7:0] read-write ARB_RW1_RA_MSB Endpoint Read Address value *1, *2 0x21C 32 read-write 0x0 0x1 RA_MSB Read Address for EP [0:0] read-write ARB_RW1_DR Endpoint Data Register 0x220 32 read-write 0x0 0x0 DR Data Register for EP ; This register is linked to the memory, hence reset value is undefined [7:0] read-write BUF_SIZE Dedicated Endpoint Buffer Size Register *1 0x230 32 read-write 0x0 0xFF IN_BUF Buffer size for IN Endpoints. [3:0] read-write OUT_BUF Buffer size for OUT Endpoints. [7:4] read-write EP_ACTIVE Endpoint Active Indication Register *1 0x238 32 read-write 0x0 0xFF EP1_ACT Indicates that Endpoint is currently active. [0:0] read-write EP2_ACT Indicates that Endpoint is currently active. [1:1] read-write EP3_ACT Indicates that Endpoint is currently active. [2:2] read-write EP4_ACT Indicates that Endpoint is currently active. [3:3] read-write EP5_ACT Indicates that Endpoint is currently active. [4:4] read-write EP6_ACT Indicates that Endpoint is currently active. [5:5] read-write EP7_ACT Indicates that Endpoint is currently active. [6:6] read-write EP8_ACT Indicates that Endpoint is currently active. [7:7] read-write EP_TYPE Endpoint Type (IN/OUT) Indication *1 0x23C 32 read-write 0x0 0xFF EP1_TYP Endpoint Type Indication. [0:0] read-write EP_IN IN outpoint 0 EP_OUT OUT outpoint 1 EP2_TYP Endpoint Type Indication. [1:1] read-write EP_IN IN outpoint 0 EP_OUT OUT outpoint 1 EP3_TYP Endpoint Type Indication. [2:2] read-write EP_IN IN outpoint 0 EP_OUT OUT outpoint 1 EP4_TYP Endpoint Type Indication. [3:3] read-write EP_IN IN outpoint 0 EP_OUT OUT outpoint 1 EP5_TYP Endpoint Type Indication. [4:4] read-write EP_IN IN outpoint 0 EP_OUT OUT outpoint 1 EP6_TYP Endpoint Type Indication. [5:5] read-write EP_IN IN outpoint 0 EP_OUT OUT outpoint 1 EP7_TYP Endpoint Type Indication. [6:6] read-write EP_IN IN outpoint 0 EP_OUT OUT outpoint 1 EP8_TYP Endpoint Type Indication. [7:7] read-write EP_IN IN outpoint 0 EP_OUT OUT outpoint 1 ARB_EP2_CFG Endpoint Configuration Register *1 0x240 32 read-write 0x0 0xF IN_DATA_RDY Indication that Endpoint Packet Data is Ready in Main memory [0:0] read-write DMA_REQ Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. [1:1] read-write CRC_BYPASS Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware [2:2] read-write CRC_NORMAL No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s 0 CRC_BYPASS CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s 1 RESET_PTR Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. [3:3] read-write RESET_KRYPTON Do not Reset Pointer; Krypton Backward compatibility mode 0 RESET_NORMAL Reset Pointer; recommended value for reduction of CPU Configuration Writes. 1 ARB_EP2_INT_EN Endpoint Interrupt Enable Register *1 0x244 32 read-write 0x0 0x3F IN_BUF_FULL_EN IN Endpoint Local Buffer Full Enable [0:0] read-write DMA_GNT_EN Endpoint DMA Grant Enable [1:1] read-write BUF_OVER_EN Endpoint Buffer Overflow Enable [2:2] read-write BUF_UNDER_EN Endpoint Buffer Underflow Enable [3:3] read-write ERR_INT_EN Endpoint Error in Transaction Interrupt Enable [4:4] read-write DMA_TERMIN_EN Endpoint DMA Terminated Enable [5:5] read-write ARB_EP2_SR Endpoint Interrupt Enable Register *1 0x248 32 read-write 0x0 0x2F IN_BUF_FULL IN Endpoint Local Buffer Full Interrupt [0:0] read-write DMA_GNT Endpoint DMA Grant Interrupt [1:1] read-write BUF_OVER Endpoint Buffer Overflow Interrupt [2:2] read-write BUF_UNDER Endpoint Buffer Underflow Interrupt [3:3] read-write DMA_TERMIN Endpoint DMA Terminated Interrupt [5:5] read-write ARB_RW2_WA Endpoint Write Address value *1, *2 0x250 32 read-write 0x0 0xFF WA Write Address for EP [7:0] read-write ARB_RW2_WA_MSB Endpoint Write Address value *1, *2 0x254 32 read-write 0x0 0x1 WA_MSB Write Address for EP [0:0] read-write ARB_RW2_RA Endpoint Read Address value *1, *2 0x258 32 read-write 0x0 0xFF RA Read Address for EP [7:0] read-write ARB_RW2_RA_MSB Endpoint Read Address value *1, *2 0x25C 32 read-write 0x0 0x1 RA_MSB Read Address for EP [0:0] read-write ARB_RW2_DR Endpoint Data Register 0x260 32 read-write 0x0 0x0 DR Data Register for EP ; This register is linked to the memory, hence reset value is undefined [7:0] read-write ARB_CFG Arbiter Configuration Register *1 0x270 32 read-write 0x0 0xF0 AUTO_MEM Enables Auto Memory Configuration. Manual memory configuration by default. [4:4] read-write DMA_CFG DMA Access Configuration. [6:5] read-write DMA_NONE No DMA 0 DMA_MANUAL Manual DMA 1 DMA_AUTO Auto DMA 2 CFG_CMP Register Configuration Complete Indication. Posedge is detected on this bit. Hence a 0 to 1 transition is required. [7:7] read-write USB_CLK_EN USB Block Clock Enable Register 0x274 32 read-write 0x0 0x1 CSR_CLK_EN Clock Enable for Core Logic clocked by AHB bus clock [0:0] read-write ARB_INT_EN Arbiter Interrupt Enable *1 0x278 32 read-write 0x0 0xFF EP1_INTR_EN Enables interrupt for EP1 [0:0] read-write EP2_INTR_EN Enables interrupt for EP2 [1:1] read-write EP3_INTR_EN Enables interrupt for EP3 [2:2] read-write EP4_INTR_EN Enables interrupt for EP4 [3:3] read-write EP5_INTR_EN Enables interrupt for EP5 [4:4] read-write EP6_INTR_EN Enables interrupt for EP6 [5:5] read-write EP7_INTR_EN Enables interrupt for EP7 [6:6] read-write EP8_INTR_EN Enables interrupt for EP8 [7:7] read-write ARB_INT_SR Arbiter Interrupt Status *1 0x27C 32 read-only 0x0 0xFF EP1_INTR Interrupt status for EP1 [0:0] read-only EP2_INTR Interrupt status for EP2 [1:1] read-only EP3_INTR Interrupt status for EP3 [2:2] read-only EP4_INTR Interrupt status for EP4 [3:3] read-only EP5_INTR Interrupt status for EP5 [4:4] read-only EP6_INTR Interrupt status for EP6 [5:5] read-only EP7_INTR Interrupt status for EP7 [6:6] read-only EP8_INTR Interrupt status for EP8 [7:7] read-only ARB_EP3_CFG Endpoint Configuration Register *1 0x280 32 read-write 0x0 0xF IN_DATA_RDY Indication that Endpoint Packet Data is Ready in Main memory [0:0] read-write DMA_REQ Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. [1:1] read-write CRC_BYPASS Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware [2:2] read-write CRC_NORMAL No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s 0 CRC_BYPASS CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s 1 RESET_PTR Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. [3:3] read-write RESET_KRYPTON Do not Reset Pointer; Krypton Backward compatibility mode 0 RESET_NORMAL Reset Pointer; recommended value for reduction of CPU Configuration Writes. 1 ARB_EP3_INT_EN Endpoint Interrupt Enable Register *1 0x284 32 read-write 0x0 0x3F IN_BUF_FULL_EN IN Endpoint Local Buffer Full Enable [0:0] read-write DMA_GNT_EN Endpoint DMA Grant Enable [1:1] read-write BUF_OVER_EN Endpoint Buffer Overflow Enable [2:2] read-write BUF_UNDER_EN Endpoint Buffer Underflow Enable [3:3] read-write ERR_INT_EN Endpoint Error in Transaction Interrupt Enable [4:4] read-write DMA_TERMIN_EN Endpoint DMA Terminated Enable [5:5] read-write ARB_EP3_SR Endpoint Interrupt Enable Register *1 0x288 32 read-write 0x0 0x2F IN_BUF_FULL IN Endpoint Local Buffer Full Interrupt [0:0] read-write DMA_GNT Endpoint DMA Grant Interrupt [1:1] read-write BUF_OVER Endpoint Buffer Overflow Interrupt [2:2] read-write BUF_UNDER Endpoint Buffer Underflow Interrupt [3:3] read-write DMA_TERMIN Endpoint DMA Terminated Interrupt [5:5] read-write ARB_RW3_WA Endpoint Write Address value *1, *2 0x290 32 read-write 0x0 0xFF WA Write Address for EP [7:0] read-write ARB_RW3_WA_MSB Endpoint Write Address value *1, *2 0x294 32 read-write 0x0 0x1 WA_MSB Write Address for EP [0:0] read-write ARB_RW3_RA Endpoint Read Address value *1, *2 0x298 32 read-write 0x0 0xFF RA Read Address for EP [7:0] read-write ARB_RW3_RA_MSB Endpoint Read Address value *1, *2 0x29C 32 read-write 0x0 0x1 RA_MSB Read Address for EP [0:0] read-write ARB_RW3_DR Endpoint Data Register 0x2A0 32 read-write 0x0 0x0 DR Data Register for EP ; This register is linked to the memory, hence reset value is undefined [7:0] read-write CWA Common Area Write Address *1 0x2B0 32 read-write 0x0 0xFF CWA Write Address for Common Area [7:0] read-write CWA_MSB Endpoint Read Address value *1 0x2B4 32 read-write 0x0 0x1 CWA_MSB Write Address for Common Area [0:0] read-write ARB_EP4_CFG Endpoint Configuration Register *1 0x2C0 32 read-write 0x0 0xF IN_DATA_RDY Indication that Endpoint Packet Data is Ready in Main memory [0:0] read-write DMA_REQ Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. [1:1] read-write CRC_BYPASS Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware [2:2] read-write CRC_NORMAL No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s 0 CRC_BYPASS CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s 1 RESET_PTR Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. [3:3] read-write RESET_KRYPTON Do not Reset Pointer; Krypton Backward compatibility mode 0 RESET_NORMAL Reset Pointer; recommended value for reduction of CPU Configuration Writes. 1 ARB_EP4_INT_EN Endpoint Interrupt Enable Register *1 0x2C4 32 read-write 0x0 0x3F IN_BUF_FULL_EN IN Endpoint Local Buffer Full Enable [0:0] read-write DMA_GNT_EN Endpoint DMA Grant Enable [1:1] read-write BUF_OVER_EN Endpoint Buffer Overflow Enable [2:2] read-write BUF_UNDER_EN Endpoint Buffer Underflow Enable [3:3] read-write ERR_INT_EN Endpoint Error in Transaction Interrupt Enable [4:4] read-write DMA_TERMIN_EN Endpoint DMA Terminated Enable [5:5] read-write ARB_EP4_SR Endpoint Interrupt Enable Register *1 0x2C8 32 read-write 0x0 0x2F IN_BUF_FULL IN Endpoint Local Buffer Full Interrupt [0:0] read-write DMA_GNT Endpoint DMA Grant Interrupt [1:1] read-write BUF_OVER Endpoint Buffer Overflow Interrupt [2:2] read-write BUF_UNDER Endpoint Buffer Underflow Interrupt [3:3] read-write DMA_TERMIN Endpoint DMA Terminated Interrupt [5:5] read-write ARB_RW4_WA Endpoint Write Address value *1, *2 0x2D0 32 read-write 0x0 0xFF WA Write Address for EP [7:0] read-write ARB_RW4_WA_MSB Endpoint Write Address value *1, *2 0x2D4 32 read-write 0x0 0x1 WA_MSB Write Address for EP [0:0] read-write ARB_RW4_RA Endpoint Read Address value *1, *2 0x2D8 32 read-write 0x0 0xFF RA Read Address for EP [7:0] read-write ARB_RW4_RA_MSB Endpoint Read Address value *1, *2 0x2DC 32 read-write 0x0 0x1 RA_MSB Read Address for EP [0:0] read-write ARB_RW4_DR Endpoint Data Register 0x2E0 32 read-write 0x0 0x0 DR Data Register for EP ; This register is linked to the memory, hence reset value is undefined [7:0] read-write DMA_THRES DMA Burst / Threshold Configuration 0x2F0 32 read-write 0x0 0xFF DMA_THS DMA Threshold count [7:0] read-write DMA_THRES_MSB DMA Burst / Threshold Configuration 0x2F4 32 read-write 0x0 0x1 DMA_THS_MSB DMA Threshold count [0:0] read-write ARB_EP5_CFG Endpoint Configuration Register *1 0x300 32 read-write 0x0 0xF IN_DATA_RDY Indication that Endpoint Packet Data is Ready in Main memory [0:0] read-write DMA_REQ Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. [1:1] read-write CRC_BYPASS Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware [2:2] read-write CRC_NORMAL No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s 0 CRC_BYPASS CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s 1 RESET_PTR Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. [3:3] read-write RESET_KRYPTON Do not Reset Pointer; Krypton Backward compatibility mode 0 RESET_NORMAL Reset Pointer; recommended value for reduction of CPU Configuration Writes. 1 ARB_EP5_INT_EN Endpoint Interrupt Enable Register *1 0x304 32 read-write 0x0 0x3F IN_BUF_FULL_EN IN Endpoint Local Buffer Full Enable [0:0] read-write DMA_GNT_EN Endpoint DMA Grant Enable [1:1] read-write BUF_OVER_EN Endpoint Buffer Overflow Enable [2:2] read-write BUF_UNDER_EN Endpoint Buffer Underflow Enable [3:3] read-write ERR_INT_EN Endpoint Error in Transaction Interrupt Enable [4:4] read-write DMA_TERMIN_EN Endpoint DMA Terminated Enable [5:5] read-write ARB_EP5_SR Endpoint Interrupt Enable Register *1 0x308 32 read-write 0x0 0x2F IN_BUF_FULL IN Endpoint Local Buffer Full Interrupt [0:0] read-write DMA_GNT Endpoint DMA Grant Interrupt [1:1] read-write BUF_OVER Endpoint Buffer Overflow Interrupt [2:2] read-write BUF_UNDER Endpoint Buffer Underflow Interrupt [3:3] read-write DMA_TERMIN Endpoint DMA Terminated Interrupt [5:5] read-write ARB_RW5_WA Endpoint Write Address value *1, *2 0x310 32 read-write 0x0 0xFF WA Write Address for EP [7:0] read-write ARB_RW5_WA_MSB Endpoint Write Address value *1, *2 0x314 32 read-write 0x0 0x1 WA_MSB Write Address for EP [0:0] read-write ARB_RW5_RA Endpoint Read Address value *1, *2 0x318 32 read-write 0x0 0xFF RA Read Address for EP [7:0] read-write ARB_RW5_RA_MSB Endpoint Read Address value *1, *2 0x31C 32 read-write 0x0 0x1 RA_MSB Read Address for EP [0:0] read-write ARB_RW5_DR Endpoint Data Register 0x320 32 read-write 0x0 0x0 DR Data Register for EP ; This register is linked to the memory, hence reset value is undefined [7:0] read-write BUS_RST_CNT Bus Reset Count Register 0x330 32 read-write 0xA 0xF BUS_RST_CNT Bus Reset Count Length [3:0] read-write ARB_EP6_CFG Endpoint Configuration Register *1 0x340 32 read-write 0x0 0xF IN_DATA_RDY Indication that Endpoint Packet Data is Ready in Main memory [0:0] read-write DMA_REQ Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. [1:1] read-write CRC_BYPASS Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware [2:2] read-write CRC_NORMAL No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s 0 CRC_BYPASS CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s 1 RESET_PTR Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. [3:3] read-write RESET_KRYPTON Do not Reset Pointer; Krypton Backward compatibility mode 0 RESET_NORMAL Reset Pointer; recommended value for reduction of CPU Configuration Writes. 1 ARB_EP6_INT_EN Endpoint Interrupt Enable Register *1 0x344 32 read-write 0x0 0x3F IN_BUF_FULL_EN IN Endpoint Local Buffer Full Enable [0:0] read-write DMA_GNT_EN Endpoint DMA Grant Enable [1:1] read-write BUF_OVER_EN Endpoint Buffer Overflow Enable [2:2] read-write BUF_UNDER_EN Endpoint Buffer Underflow Enable [3:3] read-write ERR_INT_EN Endpoint Error in Transaction Interrupt Enable [4:4] read-write DMA_TERMIN_EN Endpoint DMA Terminated Enable [5:5] read-write ARB_EP6_SR Endpoint Interrupt Enable Register *1 0x348 32 read-write 0x0 0x2F IN_BUF_FULL IN Endpoint Local Buffer Full Interrupt [0:0] read-write DMA_GNT Endpoint DMA Grant Interrupt [1:1] read-write BUF_OVER Endpoint Buffer Overflow Interrupt [2:2] read-write BUF_UNDER Endpoint Buffer Underflow Interrupt [3:3] read-write DMA_TERMIN Endpoint DMA Terminated Interrupt [5:5] read-write ARB_RW6_WA Endpoint Write Address value *1, *2 0x350 32 read-write 0x0 0xFF WA Write Address for EP [7:0] read-write ARB_RW6_WA_MSB Endpoint Write Address value *1, *2 0x354 32 read-write 0x0 0x1 WA_MSB Write Address for EP [0:0] read-write ARB_RW6_RA Endpoint Read Address value *1, *2 0x358 32 read-write 0x0 0xFF RA Read Address for EP [7:0] read-write ARB_RW6_RA_MSB Endpoint Read Address value *1, *2 0x35C 32 read-write 0x0 0x1 RA_MSB Read Address for EP [0:0] read-write ARB_RW6_DR Endpoint Data Register 0x360 32 read-write 0x0 0x0 DR Data Register for EP ; This register is linked to the memory, hence reset value is undefined [7:0] read-write ARB_EP7_CFG Endpoint Configuration Register *1 0x380 32 read-write 0x0 0xF IN_DATA_RDY Indication that Endpoint Packet Data is Ready in Main memory [0:0] read-write DMA_REQ Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. [1:1] read-write CRC_BYPASS Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware [2:2] read-write CRC_NORMAL No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s 0 CRC_BYPASS CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s 1 RESET_PTR Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. [3:3] read-write RESET_KRYPTON Do not Reset Pointer; Krypton Backward compatibility mode 0 RESET_NORMAL Reset Pointer; recommended value for reduction of CPU Configuration Writes. 1 ARB_EP7_INT_EN Endpoint Interrupt Enable Register *1 0x384 32 read-write 0x0 0x3F IN_BUF_FULL_EN IN Endpoint Local Buffer Full Enable [0:0] read-write DMA_GNT_EN Endpoint DMA Grant Enable [1:1] read-write BUF_OVER_EN Endpoint Buffer Overflow Enable [2:2] read-write BUF_UNDER_EN Endpoint Buffer Underflow Enable [3:3] read-write ERR_INT_EN Endpoint Error in Transaction Interrupt Enable [4:4] read-write DMA_TERMIN_EN Endpoint DMA Terminated Enable [5:5] read-write ARB_EP7_SR Endpoint Interrupt Enable Register *1 0x388 32 read-write 0x0 0x2F IN_BUF_FULL IN Endpoint Local Buffer Full Interrupt [0:0] read-write DMA_GNT Endpoint DMA Grant Interrupt [1:1] read-write BUF_OVER Endpoint Buffer Overflow Interrupt [2:2] read-write BUF_UNDER Endpoint Buffer Underflow Interrupt [3:3] read-write DMA_TERMIN Endpoint DMA Terminated Interrupt [5:5] read-write ARB_RW7_WA Endpoint Write Address value *1, *2 0x390 32 read-write 0x0 0xFF WA Write Address for EP [7:0] read-write ARB_RW7_WA_MSB Endpoint Write Address value *1, *2 0x394 32 read-write 0x0 0x1 WA_MSB Write Address for EP [0:0] read-write ARB_RW7_RA Endpoint Read Address value *1, *2 0x398 32 read-write 0x0 0xFF RA Read Address for EP [7:0] read-write ARB_RW7_RA_MSB Endpoint Read Address value *1, *2 0x39C 32 read-write 0x0 0x1 RA_MSB Read Address for EP [0:0] read-write ARB_RW7_DR Endpoint Data Register 0x3A0 32 read-write 0x0 0x0 DR Data Register for EP ; This register is linked to the memory, hence reset value is undefined [7:0] read-write ARB_EP8_CFG Endpoint Configuration Register *1 0x3C0 32 read-write 0x0 0xF IN_DATA_RDY Indication that Endpoint Packet Data is Ready in Main memory [0:0] read-write DMA_REQ Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. [1:1] read-write CRC_BYPASS Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware [2:2] read-write CRC_NORMAL No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s 0 CRC_BYPASS CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s 1 RESET_PTR Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. [3:3] read-write RESET_KRYPTON Do not Reset Pointer; Krypton Backward compatibility mode 0 RESET_NORMAL Reset Pointer; recommended value for reduction of CPU Configuration Writes. 1 ARB_EP8_INT_EN Endpoint Interrupt Enable Register *1 0x3C4 32 read-write 0x0 0x3F IN_BUF_FULL_EN IN Endpoint Local Buffer Full Enable [0:0] read-write DMA_GNT_EN Endpoint DMA Grant Enable [1:1] read-write BUF_OVER_EN Endpoint Buffer Overflow Enable [2:2] read-write BUF_UNDER_EN Endpoint Buffer Underflow Enable [3:3] read-write ERR_INT_EN Endpoint Error in Transaction Interrupt Enable [4:4] read-write DMA_TERMIN_EN Endpoint DMA Terminated Enable [5:5] read-write ARB_EP8_SR Endpoint Interrupt Enable Register *1 0x3C8 32 read-write 0x0 0x2F IN_BUF_FULL IN Endpoint Local Buffer Full Interrupt [0:0] read-write DMA_GNT Endpoint DMA Grant Interrupt [1:1] read-write BUF_OVER Endpoint Buffer Overflow Interrupt [2:2] read-write BUF_UNDER Endpoint Buffer Underflow Interrupt [3:3] read-write DMA_TERMIN Endpoint DMA Terminated Interrupt [5:5] read-write ARB_RW8_WA Endpoint Write Address value *1, *2 0x3D0 32 read-write 0x0 0xFF WA Write Address for EP [7:0] read-write ARB_RW8_WA_MSB Endpoint Write Address value *1, *2 0x3D4 32 read-write 0x0 0x1 WA_MSB Write Address for EP [0:0] read-write ARB_RW8_RA Endpoint Read Address value *1, *2 0x3D8 32 read-write 0x0 0xFF RA Read Address for EP [7:0] read-write ARB_RW8_RA_MSB Endpoint Read Address value *1, *2 0x3DC 32 read-write 0x0 0x1 RA_MSB Read Address for EP [0:0] read-write ARB_RW8_DR Endpoint Data Register 0x3E0 32 read-write 0x0 0x0 DR Data Register for EP ; This register is linked to the memory, hence reset value is undefined [7:0] read-write 512 4 MEM_DATA[%s] DATA 0x400 32 read-write 0x0 0x0 DR Data Register for EP ; This register is linked to the memory, hence reset value is undefined [7:0] read-write SOF16 Start Of Frame Register 0x1060 32 read-only 0x0 0x7FF FRAME_NUMBER16 The frame number (11b) [10:0] read-only OSCLK_DR16 Oscillator lock data register 0x1080 32 read-only 0x0 0x0 ADDER16 These bits return the oscillator locking circuits adder output. [14:0] read-only ARB_RW1_WA16 Endpoint Write Address value *3 0x1210 32 read-write 0x0 0x1FF WA16 Write Address for EP [8:0] read-write ARB_RW1_RA16 Endpoint Read Address value *3 0x1218 32 read-write 0x0 0x1FF RA16 Read Address for EP [8:0] read-write ARB_RW1_DR16 Endpoint Data Register 0x1220 32 read-write 0x0 0x0 DR16 Data Register for EP ; This register is linked to the memory, hence reset value is undefined [15:0] read-write ARB_RW2_WA16 Endpoint Write Address value *3 0x1250 32 read-write 0x0 0x1FF WA16 Write Address for EP [8:0] read-write ARB_RW2_RA16 Endpoint Read Address value *3 0x1258 32 read-write 0x0 0x1FF RA16 Read Address for EP [8:0] read-write ARB_RW2_DR16 Endpoint Data Register 0x1260 32 read-write 0x0 0x0 DR16 Data Register for EP ; This register is linked to the memory, hence reset value is undefined [15:0] read-write ARB_RW3_WA16 Endpoint Write Address value *3 0x1290 32 read-write 0x0 0x1FF WA16 Write Address for EP [8:0] read-write ARB_RW3_RA16 Endpoint Read Address value *3 0x1298 32 read-write 0x0 0x1FF RA16 Read Address for EP [8:0] read-write ARB_RW3_DR16 Endpoint Data Register 0x12A0 32 read-write 0x0 0x0 DR16 Data Register for EP ; This register is linked to the memory, hence reset value is undefined [15:0] read-write CWA16 Common Area Write Address 0x12B0 32 read-write 0x0 0x1FF CWA16 Write Address for Common Area [8:0] read-write ARB_RW4_WA16 Endpoint Write Address value *3 0x12D0 32 read-write 0x0 0x1FF WA16 Write Address for EP [8:0] read-write ARB_RW4_RA16 Endpoint Read Address value *3 0x12D8 32 read-write 0x0 0x1FF RA16 Read Address for EP [8:0] read-write ARB_RW4_DR16 Endpoint Data Register 0x12E0 32 read-write 0x0 0x0 DR16 Data Register for EP ; This register is linked to the memory, hence reset value is undefined [15:0] read-write DMA_THRES16 DMA Burst / Threshold Configuration 0x12F0 32 read-write 0x0 0x1FF DMA_THS16 DMA Threshold count [8:0] read-write ARB_RW5_WA16 Endpoint Write Address value *3 0x1310 32 read-write 0x0 0x1FF WA16 Write Address for EP [8:0] read-write ARB_RW5_RA16 Endpoint Read Address value *3 0x1318 32 read-write 0x0 0x1FF RA16 Read Address for EP [8:0] read-write ARB_RW5_DR16 Endpoint Data Register 0x1320 32 read-write 0x0 0x0 DR16 Data Register for EP ; This register is linked to the memory, hence reset value is undefined [15:0] read-write ARB_RW6_WA16 Endpoint Write Address value *3 0x1350 32 read-write 0x0 0x1FF WA16 Write Address for EP [8:0] read-write ARB_RW6_RA16 Endpoint Read Address value *3 0x1358 32 read-write 0x0 0x1FF RA16 Read Address for EP [8:0] read-write ARB_RW6_DR16 Endpoint Data Register 0x1360 32 read-write 0x0 0x0 DR16 Data Register for EP ; This register is linked to the memory, hence reset value is undefined [15:0] read-write ARB_RW7_WA16 Endpoint Write Address value *3 0x1390 32 read-write 0x0 0x1FF WA16 Write Address for EP [8:0] read-write ARB_RW7_RA16 Endpoint Read Address value *3 0x1398 32 read-write 0x0 0x1FF RA16 Read Address for EP [8:0] read-write ARB_RW7_DR16 Endpoint Data Register 0x13A0 32 read-write 0x0 0x0 DR16 Data Register for EP ; This register is linked to the memory, hence reset value is undefined [15:0] read-write ARB_RW8_WA16 Endpoint Write Address value *3 0x13D0 32 read-write 0x0 0x1FF WA16 Write Address for EP [8:0] read-write ARB_RW8_RA16 Endpoint Read Address value *3 0x13D8 32 read-write 0x0 0x1FF RA16 Read Address for EP [8:0] read-write ARB_RW8_DR16 Endpoint Data Register 0x13E0 32 read-write 0x0 0x0 DR16 Data Register for EP ; This register is linked to the memory, hence reset value is undefined [15:0] read-write USBLPM USB Device LPM and PHY Test 0x00002000 POWER_CTL Power Control Register 0x0 32 read-write 0x0 0x303F0004 SUSPEND Put PHY into Suspend mode. If the PHY is enabled, this bit MUST be set before entering a low power mode (DeepSleep). Note: - This bit is invalid if the HOST bit of the Host Control 0 Register (HOST_CTL0) is '1'. [2:2] read-write DP_UP_EN Enables the pull up on the DP. '0' : Disable. '1' : Enable. [16:16] read-write DP_BIG Select the resister value if POWER_CTL.DP_EN='1'. This bit is valid in GPIO. '0' : The resister value is from 900 to1575Ohmpull up on the DP. '1' : The resister value is from 1425 to 3090Ohmpull up on the DP [17:17] read-write DP_DOWN_EN Enables the ~15k pull down on the DP. [18:18] read-write DM_UP_EN Enables the pull up on the DM. The bit is valid in GPIO. The pull up resistor is disabled in not GPIO. '0' : Disable. '1' : Enable. [19:19] read-write DM_BIG Select the resister value if POWER_CTL.DM_EN='1'. This bit is valid in GPIO. '0' : The resister value is from 900 to1575Ohmpull up on the DM. '1' : The resister value is from 1425 to 3090Ohmpull up on the DM [20:20] read-write DM_DOWN_EN Enables the ~15k pull down on the DP. [21:21] read-write ENABLE_DPO Enables the single ended receiver on D+. [28:28] read-write ENABLE_DMO Enables the signle ended receiver on D-. [29:29] read-write USBIO_CTL USB IO Control Register 0x8 32 read-write 0x0 0x3F DM_P The GPIO Drive Mode for DP IO pad. This field only applies if USBIO_CR1.IOMODE =1. Data comes from the corresponding GPIO.DR register. [2:0] read-write OFF Mode 0: Output buffer off (high Z). Input buffer off. 0 INPUT Mode 1: Output buffer off (high Z). Input buffer on. Other values, not supported. 1 DM_M The GPIO Drive Mode for DM IO pad. [5:3] read-write FLOW_CTL Flow Control Register 0xC 32 read-write 0x0 0xFF EP1_ERR_RESP End Point 1 error response 0: do nothing (backward compatibility mode) 1: if this is an IN EP and an underflow occurs then cause a CRC error, if this is an OUT EP and an overflow occurs then send a NAK [0:0] read-write EP2_ERR_RESP End Point 2 error response [1:1] read-write EP3_ERR_RESP End Point 3 error response [2:2] read-write EP4_ERR_RESP End Point 4 error response [3:3] read-write EP5_ERR_RESP End Point 5 error response [4:4] read-write EP6_ERR_RESP End Point 6 error response [5:5] read-write EP7_ERR_RESP End Point 7 error response [6:6] read-write EP8_ERR_RESP End Point 8 error response [7:7] read-write LPM_CTL LPM Control Register 0x10 32 read-write 0x0 0x17 LPM_EN LPM enable 0: Disabled, LPM token will not get a response (backward compatibility mode) 1: Enable, LPM token will get a handshake response (ACK, STALL, NYET or NAK) A STALL will be sent if the bLinkState is not 0001b A NYET, NAK or ACK response will be sent depending on the NYET_EN and LPM_ACK_RESP bits below [0:0] read-write LPM_ACK_RESP LPM ACK response enable (if LPM_EN=1), to allow firmware to refuse a low power request 0: a LPM token will get a NYET or NAK (depending on NYET_EN bit below) response and the device will NOT go to a low power mode 1: a LPM token will get an ACK response and the device will go to the requested low power mode [1:1] read-write NYET_EN Allow firmware to choose which response to use for an LPM token (LPM_EN=1) when the device is NOT ready to go to the requested low power mode (LPM_ACK_RESP=0). 0: a LPM token will get an NAK response (indicating a CRC error), the host is expected to repeat the LPM token. 1: a LPM token will get a NYET response [2:2] read-write SUB_RESP Enable a STALL response for all undefined SubPIDs, i.e. other than LPM (0011b). If not enabled then there will be no response (Error) for the undefined SubPIDs. [4:4] read-write LPM_STAT LPM Status register 0x14 32 read-only 0x0 0x1F LPM_BESL Best Effort Service Latency This value should match either the Baseline (DeepSleep) or Deep (Hibernate) BESL in the BOS descriptor. [3:0] read-only LPM_REMOTEWAKE 0: Device is prohibited from initiating a remote wake 1: Device is allow to wake the host [4:4] read-only INTR_SIE USB SOF, BUS RESET and EP0 Interrupt Status 0x20 32 read-write 0x0 0x1F SOF_INTR Interrupt status for USB SOF [0:0] read-write BUS_RESET_INTR Interrupt status for BUS RESET [1:1] read-write EP0_INTR Interrupt status for EP0 [2:2] read-write LPM_INTR Interrupt status for LPM (Link Power Management, L1 entry) [3:3] read-write RESUME_INTR Interrupt status for Resume [4:4] read-write INTR_SIE_SET USB SOF, BUS RESET and EP0 Interrupt Set 0x24 32 read-write 0x0 0x1F SOF_INTR_SET Write with '1' to set corresponding bit in interrupt request register. [0:0] read-write BUS_RESET_INTR_SET Write with '1' to set corresponding bit in interrupt request register. [1:1] read-write EP0_INTR_SET Write with '1' to set corresponding bit in interrupt request register. [2:2] read-write LPM_INTR_SET Write with '1' to set corresponding bit in interrupt request register. [3:3] read-write RESUME_INTR_SET Write with '1' to set corresponding bit in interrupt request register. [4:4] read-write INTR_SIE_MASK USB SOF, BUS RESET and EP0 Interrupt Mask 0x28 32 read-write 0x0 0x1F SOF_INTR_MASK Set to 1 to enable interrupt corresponding to interrupt request register [0:0] read-write BUS_RESET_INTR_MASK Set to 1 to enable interrupt corresponding to interrupt request register [1:1] read-write EP0_INTR_MASK Set to 1 to enable interrupt corresponding to interrupt request register [2:2] read-write LPM_INTR_MASK Set to 1 to enable interrupt corresponding to interrupt request register [3:3] read-write RESUME_INTR_MASK Set to 1 to enable interrupt corresponding to interrupt request register [4:4] read-write INTR_SIE_MASKED USB SOF, BUS RESET and EP0 Interrupt Masked 0x2C 32 read-only 0x0 0x1F SOF_INTR_MASKED Logical and of corresponding request and mask bits. [0:0] read-only BUS_RESET_INTR_MASKED Logical and of corresponding request and mask bits. [1:1] read-only EP0_INTR_MASKED Logical and of corresponding request and mask bits. [2:2] read-only LPM_INTR_MASKED Logical and of corresponding request and mask bits. [3:3] read-only RESUME_INTR_MASKED Logical and of corresponding request and mask bits. [4:4] read-only INTR_LVL_SEL Select interrupt level for each interrupt source 0x30 32 read-write 0x0 0xFFFFC3FF SOF_LVL_SEL USB SOF Interrupt level select [1:0] read-write HI High priority interrupt 0 MED Medium priority interrupt 1 LO Low priority interrupt 2 RSVD illegal 3 BUS_RESET_LVL_SEL BUS RESET Interrupt level select [3:2] read-write EP0_LVL_SEL EP0 Interrupt level select [5:4] read-write LPM_LVL_SEL LPM Interrupt level select [7:6] read-write RESUME_LVL_SEL Resume Interrupt level select [9:8] read-write ARB_EP_LVL_SEL Arbiter Endpoint Interrupt level select [15:14] read-write EP1_LVL_SEL EP1 Interrupt level select [17:16] read-write EP2_LVL_SEL EP2 Interrupt level select [19:18] read-write EP3_LVL_SEL EP3 Interrupt level select [21:20] read-write EP4_LVL_SEL EP4 Interrupt level select [23:22] read-write EP5_LVL_SEL EP5 Interrupt level select [25:24] read-write EP6_LVL_SEL EP6 Interrupt level select [27:26] read-write EP7_LVL_SEL EP7 Interrupt level select [29:28] read-write EP8_LVL_SEL EP8 Interrupt level select [31:30] read-write INTR_CAUSE_HI High priority interrupt Cause register 0x34 32 read-only 0x0 0xFF9F SOF_INTR USB SOF Interrupt [0:0] read-only BUS_RESET_INTR BUS RESET Interrupt [1:1] read-only EP0_INTR EP0 Interrupt [2:2] read-only LPM_INTR LPM Interrupt [3:3] read-only RESUME_INTR Resume Interrupt [4:4] read-only ARB_EP_INTR Arbiter Endpoint Interrupt [7:7] read-only EP1_INTR EP1 Interrupt [8:8] read-only EP2_INTR EP2 Interrupt [9:9] read-only EP3_INTR EP3 Interrupt [10:10] read-only EP4_INTR EP4 Interrupt [11:11] read-only EP5_INTR EP5 Interrupt [12:12] read-only EP6_INTR EP6 Interrupt [13:13] read-only EP7_INTR EP7 Interrupt [14:14] read-only EP8_INTR EP8 Interrupt [15:15] read-only INTR_CAUSE_MED Medium priority interrupt Cause register 0x38 32 read-only 0x0 0xFF9F SOF_INTR USB SOF Interrupt [0:0] read-only BUS_RESET_INTR BUS RESET Interrupt [1:1] read-only EP0_INTR EP0 Interrupt [2:2] read-only LPM_INTR LPM Interrupt [3:3] read-only RESUME_INTR Resume Interrupt [4:4] read-only ARB_EP_INTR Arbiter Endpoint Interrupt [7:7] read-only EP1_INTR EP1 Interrupt [8:8] read-only EP2_INTR EP2 Interrupt [9:9] read-only EP3_INTR EP3 Interrupt [10:10] read-only EP4_INTR EP4 Interrupt [11:11] read-only EP5_INTR EP5 Interrupt [12:12] read-only EP6_INTR EP6 Interrupt [13:13] read-only EP7_INTR EP7 Interrupt [14:14] read-only EP8_INTR EP8 Interrupt [15:15] read-only INTR_CAUSE_LO Low priority interrupt Cause register 0x3C 32 read-only 0x0 0xFF9F SOF_INTR USB SOF Interrupt [0:0] read-only BUS_RESET_INTR BUS RESET Interrupt [1:1] read-only EP0_INTR EP0 Interrupt [2:2] read-only LPM_INTR LPM Interrupt [3:3] read-only RESUME_INTR Resume Interrupt [4:4] read-only ARB_EP_INTR Arbiter Endpoint Interrupt [7:7] read-only EP1_INTR EP1 Interrupt [8:8] read-only EP2_INTR EP2 Interrupt [9:9] read-only EP3_INTR EP3 Interrupt [10:10] read-only EP4_INTR EP4 Interrupt [11:11] read-only EP5_INTR EP5 Interrupt [12:12] read-only EP6_INTR EP6 Interrupt [13:13] read-only EP7_INTR EP7 Interrupt [14:14] read-only EP8_INTR EP8 Interrupt [15:15] read-only DFT_CTL DFT control 0x70 32 read-write 0x0 0x1F DDFT_OUT_SEL DDFT output select signal [2:0] read-write OFF Nothing connected, output 0 0 DP_SE Single Ended output of DP 1 DM_SE Single Ended output of DM 2 TXOE Output Enable 3 RCV_DF Differential Receiver output 4 GPIO_DP_OUT GPIO output of DP 5 GPIO_DM_OUT GPIO output of DM 6 DDFT_IN_SEL DDFT input select signal [4:3] read-write OFF Nothing connected, output 0 0 GPIO_DP_IN GPIO input of DP 1 GPIO_DM_IN GPIO input of DM 2 USBHOST USB Host Controller 0x00004000 HOST_CTL0 Host Control 0 Register. 0x0 32 read-write 0x0 0x80000001 HOST This bit selects an operating mode of this IP. '0' : USB Device '1' : USB Host Notes: - The mode of operation mode does not transition immediately after setting this bit. Read this bit to confirm that the operation mode has changed. - This bit is reset to '0' if the ENABLE bit in this register changes from '1' to '0'. - Before changing from the USB Host to the USB Device, check that the following conditions are satisfied and also set the RST bit of the Host Control 1 Register (HOST_CTL1). to '1'. * The SOFBUSY bit of the Host Status Register (HOST_STATUS) is set to '0'. * The TKNEN bits of the Host Token Endpoint Register (HOST_TOKEN) is set to '000'. * The SUSP bit of the Host Status Register (HOST_STATUS) is set to '0'. [0:0] read-write ENABLE This bit enables the operation of this IP. '0' : Disable USB Host '1' : Enable USB Host Note: - This bit doesn't affect the USB Device. [31:31] read-write HOST_CTL1 Host Control 1 Register. 0x10 32 read-write 0x83 0x83 CLKSEL This bit selects the operating clock of USB Host. '0' : Low-speed clock '1' : Full-speed clock Notes: - This bit is set to it's default vaulue '1' if the ENABLE bit of the Host Control 0 Register (HOST_CTL0) changes from '1' to '0'. - This bit must always be set to '1' in the USB Device mode. [0:0] read-write USTP This bit stops the clock for the USB Host operating unit. When this bit is '1', power consumption can be reduced by configuring this bit. '0' : Normal operating mode. '1' : Stops the clock for the USB Host operating unit. Notes: - If this bit is set to '1', the function of USB Host can't be used because internal clock is stopped. - This bit is initialized if ENABLE bit of the Host Control 0 Register (HOST_CTL0) changes from '1' to '0'. [1:1] read-write RST This bit resets the USB Host. '0' : Normal operating mode. '1' : USB Host is reset. Notes: - This bit is to it's default value '1' if the ENABLE bit of the Host Control 0 Register (HOST_CTL0) changes from '1' to '0'. - If this bit is set to '1', both the BFINI bits of the Host Endpoint 1 Control Register (HOST_EP1_CTL) and Host Endpoint 2 Control Register (HOST_EP2_CTL) are set to '1'. [7:7] read-write HOST_CTL2 Host Control 2 Register. 0x100 32 read-write 0x1 0xFF RETRY If this bit is set to '1', the target token is retried if a NAK or error* occurs. Retry processing is performed after the time that is specified in the Host Retry Timer Setup Register (HOST_RTIMER). * : HOST_ERR.RERR='1', HOST_ERR.TOUT='1', HOST_ERR.CRC='1', HOST_ERR.TGERR='1', HOST_ERR.STUFF='1' '0' : Doesn't retry token sending. '1' : Retries token sending Note: - This bit isn't initialized even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. [0:0] read-write CANCEL When this bit is set to '1', if the target token is written to the Host Token Endpoint Register (HOST_TOKEN) in the EOF area (specified in the Host EOF Setup Register), its sending is canceled. When this bit is set to '0', token sending is not canceled even if the target token is written to the register. The cancellation of token sending is detected by reading the TCAN bit of the Interrupt USB Host Register (INTR_USBHOST). '0' : Continues a token. '1' : Cancels a token. [1:1] read-write SOFSTEP If this bit is set to '1', the SOF interrupt flag (INTR_USBHOST.SOFIRQ) is set to '1' each time SOF is sent. If this bit is set to '0', the set value of the Host SOF Interrupt Frame Compare Register (HOST_FCOMP) is compared with the low-order eight bits of the SOF frame number. If they match, the SOF interrupt flag (INTR_USBHOST.SOFIRQ) is set to '1'. '0' : An interrupt occurred due to the HOST_HFCOMP setting. '1' : An interrupt occurred. Notes: - If a SOF token (TKNEN='001') is sent by the setting of the Host Token Endpoint Register (HOST_TOKEN), the SOF interrupt flag (INTR_USBHOST.SOFIRQ) is not set to '1' regardless of the setting of this bit. [2:2] read-write ALIVE This bit is used to specify the keep-alive function in the low-speed mode. If this bit it set to '1' while the CLKSEL bit of the Host Control 1 Register (HOST_CTL1) is '0', SE0 is output instead of SOF. This bit is only effective when the CLKSEL bit is '0'. If the CLKSEL bit is '1' (Full-Speed mode), SOF is output regardless of the setting of the ALIVE bit. '0' : SOF output. '1' : SE0 output (Keep alive) [3:3] read-write RSVD_4 N/A [4:4] read-write RSVD_5 N/A [5:5] read-write TTEST N/A [7:6] read-write HOST_ERR Host Error Status Register. 0x104 32 read-write 0x3 0xFF HS These flags indicate the status of a handshake packet to be sent or received. These flags are set to 'NULL' when no handshake occurs due to an error or when a SOF token has been ended with the TKNEN bit of the Host Token Endpoint Register (HOST_TOKEN). These bits are updated when sending or receiving has been ended. Write '11' to set the status back to 'NULL', all other write values are ignored. Note: This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. [1:0] read-write ACK Acknowledge Packet 0 NAK Non-Acknowledge Packet 1 STALL Stall Packet 2 NULL Null Packet 3 STUFF If this bit is set to '1', it means that a bit stuffing error has been detected. When this bit is '0', it means that no error is detected. If a stuffing error is detected, bit5 (TOUT) of this register is also set to '1'. Write '1' to clear, a write of '0' is ignored. '0' : No stuffing error. '1' : Stuffing error detected. Note: - This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. [2:2] read-write TGERR If this bit is set to '1', it means that the data does not match the TGGL data. When this bit is '0', it means that no error is detected. Write '1' to clear, a write of '0' is ignored. '0' : No toggle error. '1' : Toggle error detected. Note: - This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. [3:3] read-write CRC If this bit is set to '1', it means that a CRC error is detected in the USB Host. When this bit is '0', it means that no error is detected. If a CRC error is detected, bit5 (TOUT) of this register is also set to '1'. Write '1' to clear, a write of '0' is ignored. '0' : No CRC error. '1' : CRC error detected. Note: - This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. [4:4] read-write TOUT If this bit is set to '1', it means that no response is returned from the device within the specified time after a token has been sent in the USB Host. When this bit is '0', it means that no timeout is detected. Write '1' to clear, a write of '0' is ignored. '0' : No timeout. '1' : Timeout has detected. Note: - This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. [5:5] read-write RERR When this bit is set to '1', it means that the received data exceeds the specified maximum number of packets in the USB Host. If a receive error is detected, bit5 (TOUT) of this register is also set to '1'. When this bit is '0', it means that no error is detected. Write '1' to clear, a write of '0' is ignored. '0' : No receive error. '1' : Maximum packet receive error detected. - This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. [6:6] read-write LSTSOF If this bit is set to '1', it means that the SOF token can't be sent in the USB Host because other token is in process. When this bit is '0', it means that SOF token was sent with no error. Write '1' to clear, a write of '0' is ignored. '0' : SOF sent without error. '1' : SOF error detected. Note: - This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. [7:7] read-write HOST_STATUS Host Status Register. 0x108 32 read-write 0xC2 0x1FF CSTAT When this bit is '1', it means that the device is connected. When this bit is '0', it means that the device is disconnected. '0' : Device is disconnected. '1' : Device is connected. Notes: - This bit is set to the default value if the RST bit of the Host Control 1 Register (Host_CTL1) is set to '1'. - The transition to disconnected on RST isn't immediate. Read this bit to confirm the transition is complete. [0:0] read-only TMODE If this bit is '1', it means that the device is connected in the full-speed mode. When this bit is '0', it means that the device is connected in the low-speed mode. This bit is valid when the CSTAT bit of the Host Status Register (HOST_STATUS) is '1'. '0' : Low-speed. '1' : Full-speed. Notes: - This bit is set to the default value if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. - The transition to disconnected on RST isn't immediate. Read this bit to confirm the transition is complete. [1:1] read-only SUSP If this bit is set to '1', the USB Host is placed into the suspend state. If this bit is set to '0' while it is '1' or the USB bus is placed into the k-state mode, then suspend state is released, and the RWIRQ bit of the Interrupt USB Host Register (INTR_USBHOST) is set to '1'. Set to '1' : Suspend. Set '0' when this bit is '1' : Resume. Other conditions : Holds the status. Notes: - This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. - The transition to disconnected on RST isn't immediate. Read this bit to confirm the transition is complete. - If this bit is set to '1', this bit must not be set to '1' until the RWIRQ bit of the Interrupt USB Host Register (INTR_USBHOST) is set to '1'. - Do not set this bit to '1' while the USB is active (during USB bus resetting, data transfer, or SOF timer running). - If the value of this bit is changed, it is not immediately reflected on the state of the USB bus. To check whether or not the state is updated, read this bit. [2:2] read-write SOFBUSY When a SOF token is sent using the Host Token Endpoint Register (HOST_TOKEN), this bit is set to '1', which means that the SOF timer is active. When this bit is '0', it means that the SOF timer is under suspension. To stop the active SOF timer, write '0' to this bit. However, if this bit is written with '1', its value is ignored. '0' : The SOF timer is stopped. '1' : The SOF timer is active. Notes: - This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. - This bit takes time to be initialized by the RST bit of the Host Control 1 Resgiter (HOST_CTL1). - The SOF timer does not stop immediately after this bit has been set to '0' to stop the SOF timer. To check whether or not the SOF timer is stopped, read this bit. [3:3] read-write URST When this bit is set to '1', the USB bus is reset. This bit remains a '1' during USB bus resetting, and changes to '0' when USB bus resetting is ended. If this bit is set to '0', the USB bus reset is complete [4:4] read-write RSVD_5 N/A [5:5] read-only RSTBUSY This bit shows that USB Host is being reset internally. If the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1', this bit is set to '1'. If the RST bit of Host Control 1 Register (HOST_CTL1) is set to '0', this bit is set to '0'. '0' : USB Host isn't being reset. '1' : USB Host is being reset. Notes: - If this bit is '1', the a token must not be executed. - This bit isn't set to '0' or '1' immediately even if the RST bit of Host Control 1 Register (HOST_CTL1) is set to '0' or '1'. Read this bit to confirm the operation is complete. [6:6] read-only CLKSEL_ST This bit shows whether it is full-speed or not. If the CLKSEL bit of the Host Control 1 Register (HOST_CTL1) is set to '1', this bit is set to '1'. '0' : Low speed '1' : Full speed Note: - If this bit is different from the CLKSEL bit, The execution of the token and bus reset must wait these bits match. - This bit takes time to be initialized by the RST bit of the Host Control 1 Resgiter (HOST_CTL1). Read this bit to confirm the operation is complete. [7:7] read-only HOST_ST This bit shows whether the device is in USB Host mode. If the HOST bit of the Host Control Register (HOST_CTL0) is set to '1', this bit is set to '1'. '0' : USB Device '1' : USB Host Notes: - If this bit is different from the HOST bit, The execution of a token must wait these bits match. - This bit takes time to be initialized by the RST bit of the Host Control 1 Resgiter (HOST_CTL1). Read this bit to confirm the operation is complete. [8:8] read-only HOST_FCOMP Host SOF Interrupt Frame Compare Register 0x10C 32 read-write 0x0 0xFF FRAMECOMP These bits are used to specify the data to be compared with the low-order eight bits of a frame number when sending a SOF token. If the SOFSTEP bit of Host Control 2 Register (HOST_CTL2) is '0', the frame number of SOF is compared with the value of this register when sending a SOF token. If they match, the SOFIRQ bit of the Interrupt USB Host Register (INTR_USBHOST) is set to '1'. The setting of this register is invalid when the SOFSTEP bit of Host Control 2 Register (HOST_CTL2) is '1'. Note: - This bit is not reset to default even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. [7:0] read-write HOST_RTIMER Host Retry Timer Setup Register 0x110 32 read-write 0x0 0x3FFFF RTIMER These bits are used to specify the retry time in this register. The retry timer is activated when token sending starts while the RETRY bit of Host Control 2 Register (HOST_CTL2) is '1'. The retry time is then decremented by one when a 1-bit transfer clock (12 MHz in the full-speed mode) is output. When the retry timer reaches 0, the target token is sent, and processing ends. If a token retry occurs in the EOF area, the retry timer is stopped until SOF sending is ended. After SOF sending has been completed, the retry timer restarts with the value that is set when the timer stopped. [17:0] read-write HOST_ADDR Host Address Register 0x114 32 read-write 0x0 0x7F ADDRESS These bits are used to specify a token address. Note: - This bit is reset to default even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. [6:0] read-write HOST_EOF Host EOF Setup Register 0x118 32 read-write 0x0 0x3FFF EOF These bits are used to specify the time to disable token sending before transferring SOF. Specify the time with a margin, which is longer than the one-packet length. The time unit is the 1-bit transfer time. Setting example: MAXPKT = 64 bytes, full-speed mode (Token_length + packet_length + header + CRC)*7/6 + Turn_around_time =(34 bit + 546 bit)*7/6 + 36 bit = 712.7 bit Therefore, set 0x2C9. Note: - This bit is not reset to default even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. [13:0] read-write HOST_FRAME Host Frame Setup Register 0x11C 32 read-write 0x0 0x7FF FRAME These bits are used to specify a frame number of SOF. Notes: - This bit isn't reset to default even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. - Specify a frame number in this register before setting SOF in the TKNEN bit of the Host Token Endpoint Register (HOST_TOKEN). - This register cannot be written while the SOFBUSY bit of the Host Status Register (HOST_STATUS) is '1' and a SOF token is in process. [10:0] read-write HOST_TOKEN Host Token Endpoint Register 0x120 32 read-write 0x0 0x17F ENDPT These bits are used to specify an endpoint to send or receive data to or from the device. Note: - This bit isn't reset to default even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. [3:0] read-write TKNEN These bits send a token according to the current settings. After operation is complete, the TKNEN bit is set to '000', and the CMPIRQ bit of the Interrupt USB Host Register (INTR_USBHOST) is set to '1'. The settings of the TGGL and ENDPT bits are ignored when sending a SOF token. Notes: - This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. - The PRE packet isn't supported. - Do not set '100' to the TKNEN bit when the SOFBUSY bit of the Host Status Register (HOST_STATUS) is '1' - Mode should be USB Host before writing data to this bit. - When issuing a token again after the token interrupt flag (CMPIRQ) has been set to '1', wait for 3 cycles or more after a USB transfer clock (12 MHz in the full-speed mode, 1.5 MHz in the low-speed mode) was output, then write data to this bit. - Read the value of TKNEN bit if a new value is written in it .Continue writing in this bit until a retrieved value equals a new value written in. During this checking process, it is needed to prevent any interrupt. - Take the following steps when CMPIRQ bit of Interrupt USB Host Register (INTR_USBHOST) is set to '1' by finishing IN token or Isochronous IN token. 1. Read HS bit of Host Error Status Register (HOST_ERR), then set CMPIRQ bit to '0'. 2. Set EPn bit of Host DMA Enable Register (HOST_DMA_ENBL) (n=1 or 2) to '1' if HS bit of Host Error Status Register (HOST_ERR) is equal to '00' and wait until EPn bit of Host DMA Data Request Register (HOST_DMA_DREQ) changes to '1'. Finish the IN token processing if HS bit is not equal to '00'. 3. Read the received data if EPn bit of Host DMA Data Requet (HOST_DMA_DREQ) (n=1 or 2) changes to '1'. [6:4] read-write NONE Sends no data. 0 SETUP Sends SETUP token. 1 IN Sends IN token. 2 OUT Sends OUT token. 3 SOF Sends SOF token. 4 ISO_IN Sends Isochronous IN. 5 ISO_OUT Sends Isochronous OUT. 6 RSV N/A 7 TGGL This bit is used to set toggle data. Toggle data is sent depending on the setting of this bit. When receiving toggle data, received toggle data is compared with the toggle data of this bit to verify whether or not an error occurs. '0' : DATA0 '1' : DATA1 Notes: - This bit isn't reset to the default value even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. - Set this bit when the TKNEN bit of the Host Token Endpoint Register (HOST_TOKEN) is '000'. [8:8] read-write HOST_EP1_CTL Host Endpoint 1 Control Register 0x400 32 read-write 0x8100 0x9DFF PKS1 This bit specifies the maximum size transferred by one packet. The configurable range is from 0x001 to 0x100. - If automatic buffer transfer mode (DMAE='1') is used, Endpoint 0,1, or 2 cannot be used, [8:0] read-write NULLE When a data transfer request in OUT the direction is transmitted while automatic buffer transfer mode is set (DMAE = 1), this bit sets a mode that transfers 0-byte data automatically upon the detection of the last packet transfer. '0' : Releases the NULL automatic transfer mode. '1' : Sets the NULL automatic transfer mode. Note : - For data transfer in the IN direction or when automatic buffer transfer mode is not set, the NULL bit configuration does not affect communication. [10:10] read-write DMAE This bit sets a mode that uses DMA for writing or reading transfer data to/from send/receive buffer, and automatically transfers the send/receive data synchronized with an data request in the IN or OUT direction. Until the data size set in the DMA is reached, the data is transferred. '0' : Releases the packet transfer mode. '1' : Sets the packet transfer mode. Note : - The CPU must not access the send/receive buffer while the DMAE bit is set to '1'. For data transfer in the IN direction, set the DMA transfer size to the multiples of that set in PKS1 bits of the Host EP1 Control Register (HOST_EP1_CTL) and Host EP2 Control Register (HOST_EP2_CTR). [11:11] read-write DIR This bit specifies the transfer direction the Endpoint support. '0' : IN Endpoint. '1' : OUT Endpoint Note: - This bit must be changed when INI_ST bit of the Host Endpoint 1 Status Register (HOST_EP1_STATUS) is '1'. [12:12] read-write BFINI This bit initializes the send/receive buffer of transfer data. The BFINI bit is also automatically set by setting the RST bit of the HOST Control 1 Register (HOST_CTL1). If the RST bit was used for resetting, therefore, set the RST bit to '0' before clearing the BFINI bit. '0' : Clears the initialization. '1' : Initializes the send/receive buffer Note : - The EP1 buffer has a double-buffer configuration. The BFINI bit initialization initializes the double buffers concurrently and also initializes the EP1DRQ and EP1SPK bits. [15:15] read-write HOST_EP1_STATUS Host Endpoint 1 Status Register 0x404 32 read-only 0x60000 0x70000 SIZE1 These bits indicate the number of data bytes written to the receive buffer when IN packet transfer of EP1 has finished. The indication range is from 0x000 to 0x100. Note : - These bits are set to the data size transferred in the IN direction and written to the buffer. Therefore, a value read during transfer in the OUT direction has no effect. [8:0] read-only VAL_DATA This bit shows that there is valid data in the EP1 buffer. '0' : Invalid data in the buffer '1' : Valid data in the buffer [16:16] read-only INI_ST This bit shows that EP1 is initialized. If the init bit of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is set to '1' and EP1 is initialized, this bit is to '1'. '0' : Not initiatialized '1' : Initialized Note: - This bit isn't set to '0' or '1' immediately even if BFINI bit of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is set to '0' or '1'. Read this bit to confirm the transition. [17:17] read-only RSVD_18 N/A [18:18] read-only HOST_EP1_RW1_DR Host Endpoint 1 Data 1-Byte Register 0x408 32 read-write 0x0 0xFF BFDT8 Data Register for EP1 for 1-byte data [7:0] read-write HOST_EP1_RW2_DR Host Endpoint 1 Data 2-Byte Register 0x40C 32 read-write 0x0 0xFFFF BFDT16 Data Register for EP1 for 2-byte data [15:0] read-write HOST_EP2_CTL Host Endpoint 2 Control Register 0x500 32 read-write 0x8040 0x9C7F PKS2 This bit specifies the maximum size transferred by one packet. The configurable range is from 0x001 to 0x40. - If automatic buffer transfer mode (DMAE='1') is used, this Endpoint must not set from 0 to 2. [6:0] read-write NULLE When a data transfer request in the OUT direction transmitted while packet transfer mode is set (DMAE = 1), this bit sets a mode that transfers 0-byte data automatically upon the detection of the last packet transfer. '0' : Releases the NULL automatic transfer mode. '1' : Sets the NULL automatic transfer mode. Note : - For data transfer in the IN direction or when automatic buffer transfer mode is not set, the NULL bit configuration does not affect communication. [10:10] read-write DMAE This bit sets a mode that uses DMA for writing or reading transfer data to/from send/receive buffer, and automatically transfers the send/receive data synchronized with an data request in the IN or OUT direction. Until the data size set in the DMA is reached, the data is transferred. '0' : Releases the automatic buffer transfer mode. '1' : Sets the automatic buffer transfer mode. Note : - The CPU must not access the send/receive buffer while the DMAE bit is set to '1'. For data transfer in the IN direction, set the DMA transfer size to the multiples of that set in PKS bits of the Host EP1 Control Register (HOST_EP1_CTL) and Host EP2 Control Register (HOST_EP2_CTR). [11:11] read-write DIR This bit specifies the transfer direction the Endpoint support. '0' : IN Endpoint. '1' : OUT Endpoint Note: - This bit must be changed when INI_ST bit of the Host Endpoint 2 Status Register (HOST_EP2_STATUS) is '1'. [12:12] read-write BFINI This bit initializes the send/receive buffer of transfer data. The BFINI bit is also automatically set by setting the RST bit of the HOST Control 1 Register (HOST_CTL1). If the RST bit was used for resetting, therefore, set the RST bit to '0' before clearing the BFINI bit. '0' : Clears the initialization. '1' : Initializes the send/receive buffer Note : - The EP2 buffer has a double-buffer configuration. The BFINI bit initialization initializes the double buffers concurrently and also initializes the EP2DRQ and EP2SPK bits. [15:15] read-write HOST_EP2_STATUS Host Endpoint 2 Status Register 0x504 32 read-only 0x60000 0x70000 SIZE2 These bits indicate the number of data bytes written to the receive buffer when IN packet transfer of EP2 has finished. The indication range is from 0x000 to 0x40. Note : - These bits are set to the data size transferred in the IN direction and written to the buffer. Therefore, a value read during transfer in the OUT direction has no effect. [6:0] read-only VAL_DATA This bit shows that there is valid data in the EP2 buffer. '0' : Invalid data in the buffer '1' : Valid data in the buffer [16:16] read-only INI_ST This bit shows that EP2 is initialized. If the BFINI bit of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is set to '1' and EP2 is initialized, this bit is to '1'. '0' : Not Initialized '1' : Initialized Note: - This bit isn't set to '0' or '1' immediately evne if BFINI bit of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is set to '0' or '1'. [17:17] read-only RSVD_18 N/A [18:18] read-only HOST_EP2_RW1_DR Host Endpoint 2 Data 1-Byte Register 0x508 32 read-write 0x0 0xFF BFDT8 Data Register for EP2 for 1-byte data. [7:0] read-write HOST_EP2_RW2_DR Host Endpoint 2 Data 2-Byte Register 0x50C 32 read-write 0x0 0xFFFF BFDT16 Data Register for EP2 for 2 byte data. [15:0] read-write HOST_LVL1_SEL Host Interrupt Level 1 Selection Register 0x800 32 read-write 0x0 0xFFFF SOFIRQ_SEL These bits assign SOFIRQ interrupt flag to selected interrupt signals. [1:0] read-write HI High priority interrupt 0 MED Medium priority interrupt 1 LO Low priority interrupt 2 RSVD N/A 3 DIRQ_SEL These bits assign DIRQ interrupt flag to selected interrupt signals. [3:2] read-write CNNIRQ_SEL These bits assign CNNIRQ interrupt flag to selected interrupt signals. [5:4] read-write CMPIRQ_SEL These bits assign URIRQ interrupt flag to selected interrupt signals. [7:6] read-write URIRQ_SEL These bits assign URIRQ interrupt flag to selected interrupt signals. [9:8] read-write RWKIRQ_SEL These bits assign RWKIRQ interrupt flag to selected interrupt signals. [11:10] read-write RSVD_13_12 N/A [13:12] read-write TCAN_SEL These bits assign TCAN interrupt flag to selected interrupt signals. [15:14] read-write HOST_LVL2_SEL Host Interrupt Level 2 Selection Register 0x804 32 read-write 0x0 0xFF0 EP1_DRQ_SEL These bits assign EP1_DRQ interrupt flag to selected interrupt signals. [5:4] read-write HI High priority interrupt 0 MED Medium priority interrupt 1 LO Low priority interrupt 2 RSVD N/A 3 EP1_SPK_SEL These bits assign EP1_SPK interrupt flag to selected interrupt signals. [7:6] read-write EP2_DRQ_SEL These bits assign EP2_DRQ interrupt flag to selected interrupt signals. [9:8] read-write EP2_SPK_SEL These bits assign EP2_SPK interrupt flag to selected interrupt signals. [11:10] read-write INTR_USBHOST_CAUSE_HI Interrupt USB Host Cause High Register 0x900 32 read-only 0x0 0xFF SOFIRQ_INT SOFIRQ interrupt [0:0] read-only DIRQ_INT DIRQ interrupt [1:1] read-only CNNIRQ_INT CNNIRQ interrupt [2:2] read-only CMPIRQ_INT CMPIRQ interrupt [3:3] read-only URIRQ_INT URIRQ interrupt [4:4] read-only RWKIRQ_INT RWKIRQ interrupt [5:5] read-only RSVD_6 N/A [6:6] read-only TCAN_INT TCAN interrupt [7:7] read-only INTR_USBHOST_CAUSE_MED Interrupt USB Host Cause Medium Register 0x904 32 read-only 0x0 0xFF SOFIRQ_INT SOFIRQ interrupt [0:0] read-only DIRQ_INT DIRQ interrupt [1:1] read-only CNNIRQ_INT CNNIRQ interrupt [2:2] read-only CMPIRQ_INT CMPIRQ interrupt [3:3] read-only URIRQ_INT URIRQ interrupt [4:4] read-only RWKIRQ_INT RWKIRQ interrupt [5:5] read-only RSVD_6 N/A [6:6] read-only TCAN_INT TCAN interrupt [7:7] read-only INTR_USBHOST_CAUSE_LO Interrupt USB Host Cause Low Register 0x908 32 read-only 0x0 0xFF SOFIRQ_INT SOFIRQ interrupt [0:0] read-only DIRQ_INT DIRQ interrupt [1:1] read-only CNNIRQ_INT CNNIRQ interrupt [2:2] read-only CMPIRQ_INT CMPIRQ interrupt [3:3] read-only URIRQ_INT URIRQ interrupt [4:4] read-only RWKIRQ_INT RWKIRQ interrupt [5:5] read-only RSVD_6 N/A [6:6] read-only TCAN_INT TCAN interrupt [7:7] read-only INTR_HOST_EP_CAUSE_HI Interrupt USB Host Endpoint Cause High Register 0x920 32 read-only 0x0 0x3C EP1DRQ_INT EP1DRQ interrupt [2:2] read-only EP1SPK_INT EP1SPK interrupt [3:3] read-only EP2DRQ_INT EP2DRQ interrupt [4:4] read-only EP2SPK_INT EP2SPK interrupt [5:5] read-only INTR_HOST_EP_CAUSE_MED Interrupt USB Host Endpoint Cause Medium Register 0x924 32 read-only 0x0 0x3C EP1DRQ_INT EP1DRQ interrupt [2:2] read-only EP1SPK_INT EP1SPK interrupt [3:3] read-only EP2DRQ_INT EP2DRQ interrupt [4:4] read-only EP2SPK_INT EP2SPK interrupt [5:5] read-only INTR_HOST_EP_CAUSE_LO Interrupt USB Host Endpoint Cause Low Register 0x928 32 read-only 0x0 0x3C EP1DRQ_INT EP1DRQ interrupt [2:2] read-only EP1SPK_INT EP1SPK interrupt [3:3] read-only EP2DRQ_INT EP2DRQ interrupt [4:4] read-only EP2SPK_INT EP2SPK interrupt [5:5] read-only INTR_USBHOST Interrupt USB Host Register 0x940 32 read-write 0x0 0xFF SOFIRQ If this bit is set to '1', it means that SOF token sending is started. When this bit is '0', it has no meaning. Write '1' to clear, a write of '0' is ignored. '0' : Does not issue an interrupt request by starting a SOF token. '1' : Issues an interrupt request by starting a SOF token. Note : - This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. [0:0] read-write DIRQ If this bit is set to '1', it means that a device disconnection is detected. When this bit is '0', it has no meaning. Write '1' to clear, a write of '0' is ignored. '0' : Issues no interrupt request by detecting a device disconnection. '1' : Issues an interrupt request by detecting a device disconnection. Note : - This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. [1:1] read-write CNNIRQ If this bit is set to '1', it means that a device connection is detected. When this bit is '0', it has no meaning. Write '1' to clear, a write of '0' is ignored. '0' : Issues no interrupt request by detecting a device connection. '1' : Issues an interrupt request by detecting a device connection. Note : - This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. [2:2] read-write CMPIRQ If this bit is set to '1', it means that a token is completed. When this bit is '0', it has no meaning. Write '1' to clear, a write of '0' is ignored. '0' : Issues no interrupt request by token completion. '1' : Issues an interrupt request by token completion. Note : - This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. - This bit is not set to '1' even if the TCAN bit of the Interrupt USBHost Register (INTR_USBHOST) changes to '1'. - Take the following steps when this bit is set to '1' by finishing IN token or Isochronous IN token. 1. Read HS bit of Host Error Status Register (HOST_ERR), then set CMPIRQ bit to '0'. 2. Set EPn bit of Host DMA Enable Register (HOST_DMA_ENBL) (n=1 or 2) to '1' if HS bit of Host Error Status Register (HOST_ERR) is equal to '00' and wait until EPn bit of Host DMA Data Request Register (HOST_DMA_DREQ) changes to '1'. Finish the IN token processing if HS bit is not equal to '00'. 3. Read the received data if EPn bit of Host DMA Data Requet (HOST_DMA_DREQ) (n=1 or 2) changes to '1'. [3:3] read-write URIRQ If this bit is set to '1', it means that USB bus resetting is ended. When this bit is '0', it has no meaning. If this bit is written with '1', it is set to '0'. However, if this bit is written with '0', its value is ignored. '0' : Issues no interrupt request by USB bus resetting. '1' : Issues an interrupt request by USB bus resetting. Note : - This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. [4:4] read-write RWKIRQ If this bit is set to '1', it means that remote Wake-up is ended. When this bit is '0', it has no meaning. Write '1' to clear, a write of '0' is ignored. '0' : Issues no interrupt request by restart. '1' : Issues an interrupt request by restart. Note : - This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. [5:5] read-write RSVD_6 N/A [6:6] read-write TCAN If this bit is set to '1', it means that token sending is canceled based on the setting of the CANCEL bit of Host Control 2 Register (HOST_CTL2). When this bit is '0', it means that token sending is not canceled. Write '1' to clear, a write of '0' is ignored. '0' : Does not cancel token sending. '1' : Cancels token sending. Note : - This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. [7:7] read-write INTR_USBHOST_SET Interrupt USB Host Set Register 0x944 32 read-write 0x0 0xFF SOFIRQS This bit sets SOFIRQ bit. If this bit is written to '1', SOFIRQ is set to '1'. However, if this bit is written with '0', its value is ignored. [0:0] read-write DIRQS This bit sets DIRQ bit. If this bit is written to '1', DIRQ is set to '1'. However, if this bit is written with '0', its value is ignored. [1:1] read-write CNNIRQS This bit sets CNNIRQ bit. If this bit is written to '1', CNNIRQ is set to '1'. However, if this bit is written with '0', its value is ignored. [2:2] read-write CMPIRQS This bit sets CMPIRQ bit. If this bit is written to '1', CMPIRQ is set to '1'. However, if this bit is written with '0', its value is ignored. [3:3] read-write URIRQS This bit sets URIRQ bit. If this bit is written to '1', URIRQ is set to '1'. However, if this bit is written with '0', its value is ignored. [4:4] read-write RWKIRQS This bit sets RWKIRQ bit. If this bit is written to '1', RWKIRQ is set to '1'. However, if this bit is written with '0', its value is ignored. [5:5] read-write RSVD_6 N/A [6:6] read-write TCANS This bit sets TCAN bit. If this bit is written to '1', TCAN is set to '1'. However, if this bit is written with '0', its value is ignored. [7:7] read-write INTR_USBHOST_MASK Interrupt USB Host Mask Register 0x948 32 read-write 0x0 0xFF SOFIRQM This bit masks the interrupt by SOF flag. '0' : Disables '1' : Enables [0:0] read-write DIRQM This bit masks the interrupt by DIRQ flag. '0' : Disables '1' : Enables [1:1] read-write CNNIRQM This bit masks the interrupt by CNNIRQ flag. '0' : Disables '1' : Enables [2:2] read-write CMPIRQM This bit masks the interrupt by CMPIRQ flag. '0' : Disables '1' : Enables [3:3] read-write URIRQM This bit masks the interrupt by URIRQ flag. '0' : Disables '1' : Enables [4:4] read-write RWKIRQM This bit masks the interrupt by RWKIRQ flag. '0' : Disables '1' : Enables [5:5] read-write RSVD_6 N/A [6:6] read-write TCANM This bit masks the interrupt by TCAN flag. '0' : Disables '1' : Enables [7:7] read-write INTR_USBHOST_MASKED Interrupt USB Host Masked Register 0x94C 32 read-only 0x0 0xFF SOFIRQED This bit indicates the interrupt by SOF flag. '0' : Doesn't request the interrupt by SOF '1' : Request the interrupt by SOF [0:0] read-only DIRQED This bit indicates the interrupt by DIRQ flag. '0' : Doesn't request the interrupt by DIRQ '1' : Request the interrupt by DIRQ [1:1] read-only CNNIRQED This bit indicates the interrupt by CNNIRQ flag. '0' : Doesn't request the interrupt by CNNIRQ '1' : Request the interrupt by CNNIRQ [2:2] read-only CMPIRQED This bit indicates the interrupt by CMPIRQ flag. '0' : Doesn't request the interrupt by CMPIRQ '1' : Request the interrupt by CMPIRQ [3:3] read-only URIRQED This bit indicates the interrupt by URIRQ flag. '0' : Doesn't request the interrupt by URIRQ '1' : Request the interrupt by URIRQ [4:4] read-only RWKIRQED This bit indicates the interrupt by RWKIRQ flag. '0' : Doesn't request the interrupt by RWKIRQ '1' : Request the interrupt by RWKIRQ [5:5] read-only RSVD_6 N/A [6:6] read-only TCANED This bit indicates the interrupt by TCAN flag. '0' : Doesn't request the interrupt by TCAN '1' : Request the interrupt by TCAN [7:7] read-only INTR_HOST_EP Interrupt USB Host Endpoint Register 0xA00 32 read-write 0x0 0x3C EP1DRQ This bit indicates that the EP1 packet transfer has normally ended, and processing of the data is required. The DRQ bit is an interrupt cause, and writing '0' is ignored. Clear the DRQ bit by writing '1'. '0' : Clears the interrupt cause '1' : Packet transfer normally ended Note : - If automatic buffer transfer mode (DMAE = '1') is not used, '1' must be written to the DRQ bit after data has been written or read to/from the send/receive buffer. Switch the access buffers once the DRQ bit is cleared. That DRQ = '0' may not be read after the DRQ bit is cleared. If the transfer direction is set to OUT, and the DRQ bit is cleared without writing buffer data while the DRQ bit is '1', it implies that 0-byte data is set. If DIR of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is set to '1' at initial settings, the DRQ bit of corresponding Endpoint is set at the same time. Also while the DRQ bit is not set, '1' must not be written. [2:2] read-write EP1SPK This bit indicates that the data size transferred from the host does not satisfy the maximum packet size (including 0-byte) set by PKS in the Host Endpoint 1 Control Register (HOST_EP1_CTL) when the data has been received successfully. This bit is an interrupt cause, and writing '0' is ignored. Clear it by writing '1'. '0' : Received data size satisfies the maximum packet size '1' : Received data size does not satisfy the maximum packet size Note : - The EP1SPK bit is not set during data transfer in the OUT direction. [3:3] read-write EP2DRQ This bit indicates that the EP2 packet transfer has normally ended, and processing of the data is required. The DRQ bit is an interrupt cause, and writing '0' is ignored. Clear the DRQ bit by writing '1'. '0' : Clears the interrupt cause '1' : Packet transfer normally ended Note : - If packet transfer mode (DMAE = '1') is not used, '1' must be written to the DRQ bit after data has been written or read to/from the send/receive buffer. Switch the access buffers once the DRQ bit is cleared. That DRQ = '0' may not be read after the DRQ bit is cleared. If the transfer direction is set to OUT, and the DRQ bit is cleared without writing buffer data while the DRQ bit is '1', it implies that 0-byte data is set. If DIR of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is set to '1' at initial settings, the DRQ bit of corresponding Endpoint is set at the same time. Also while the DRQ bit is not set, '1' must not be written. [4:4] read-write EP2SPK This bit indicates that the data size transferred from the host does not satisfy the maximum packet size (including 0-byte) set by PKS1 in the Host Endpoint 2 Control Register (HOST_EP2_CTL) when the data has been received successfully. This bit is an interrupt cause, and writing '0' is ignored. Clear it by writing '1'. '0' : Received data size satisfies the maximum packet size '1' : Received data size does not satisfy the maximum packet size Note : - The SPK bit is not set during data transfer in the OUT direction. [5:5] read-write INTR_HOST_EP_SET Interrupt USB Host Endpoint Set Register 0xA04 32 read-write 0x0 0x3C EP1DRQS This bit sets EP1DRQ bit. If this bit is written to '1', EP1DRQ is set to '1'. However, if this bit is written with '0', its value is ignored. Note: If BFINI bit of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is '1', EP1DRQ can't be set to '1'. [2:2] read-write EP1SPKS This bit sets EP1SPK bit. If this bit is written to '1', EP1SPK is set to '1'. However, if this bit is written with '0', its value is ignored. Note: If BFINI bit of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is '1', EP1SPK can't be set to '1'. [3:3] read-write EP2DRQS This bit sets EP2DRQ bit. If this bit is written to '1', EP2DRQ is set to '1'. However, if this bit is written with '0', its value is ignored. Note: If BFINI bit of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is '1', EP2DRQ can't be set to '1'. [4:4] read-write EP2SPKS This bit sets EP2SPK bit. If this bit is written to '1', EP2SPK is set to '1'. However, if this bit is written with '0', its value is ignored. Note: If BFINI bit of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is '1', EP2SPK can't be set to '1'. [5:5] read-write INTR_HOST_EP_MASK Interrupt USB Host Endpoint Mask Register 0xA08 32 read-write 0x0 0x3C EP1DRQM This bit masks the interrupt by EP1DRQ flag. '0' : Disables '1' : Enables [2:2] read-write EP1SPKM This bit masks the interrupt by EP1SPK flag. '0' : Disables '1' : Enables [3:3] read-write EP2DRQM This bit masks the interrupt by EP2DRQ flag. '0' : Disables '1' : Enables [4:4] read-write EP2SPKM This bit masks the interrupt by EP2SPK flag. '0' : Disables '1' : Enables [5:5] read-write INTR_HOST_EP_MASKED Interrupt USB Host Endpoint Masked Register 0xA0C 32 read-only 0x0 0x3C EP1DRQED This bit indicates the interrupt by EP1DRQ flag. '0' : Doesn't request the interrupt by EP1DRQ '1' : Request the interrupt by EP1DRQ [2:2] read-only EP1SPKED This bit indicates the interrupt by EP1SPK flag. '0' : Doesn't request the interrupt by EP1SPK '1' : Request the interrupt by EP1SPK [3:3] read-only EP2DRQED This bit indicates the interrupt by EP2DRQ flag. '0' : Doesn't request the interrupt by EP2DRQ '1' : Request the interrupt by EP2DRQ [4:4] read-only EP2SPKED This bit indicates the interrupt by EP2SPK flag. '0' : Doesn't request the interrupt by EP2SPK '1' : Request the interrupt by EP2SPK [5:5] read-only HOST_DMA_ENBL Host DMA Enable Register 0xB00 32 read-write 0x0 0xC DM_EP1DRQE This bit enables DMA Request by EP1DRQ. '0' : Disable '1' : Enable [2:2] read-write DM_EP2DRQE This bit enables DMA Request by EP2DRQ. '0' : Disable '1' : Enable [3:3] read-write HOST_EP1_BLK Host Endpoint 1 Block Register 0xB20 32 read-write 0x0 0xFFFF0000 BLK_NUM Set the total byte number for DMA transfer. If HOST_EP1_RW1_DR or HOST_EP1_RW2_DR is written, the block number counter is decremented when DMAE='1'. - Set this bits before DMA transfer is enabled (HOST_DMA_ENBL.DM_DP1DRQE='1') [31:16] read-write HOST_EP2_BLK Host Endpoint 2 Block Register 0xB30 32 read-write 0x0 0xFFFF0000 BLK_NUM Set the total byte number for DMA transfer. If HOST_EP2_RW1_DR or HOST_EP2_RW2_DR is written, the block number counter is decremented when DMAE='1'. - Set this bits before DMA transfer is enabled (HOST_DMA_ENBL.DM_DP2DRQE='1') [31:16] read-write MXS40USBHSDEV USB 2 Device Controller Memory Register Map 0x40430000 0 4096 registers USBHSDEV USB 2.0 Device Controller Registers 0x00000000 DEV_CS Device controller Master Control and Status 0x0 32 read-write 0x4 0x87FFFFFF ERR_LIMIT Error interrupt limit (COUNT >= LIMIT will cause UIB_ERR_INTR.ERRLIMIT interrupt) [7:0] read-write COUNT Number of errors detected. To clear the error count write 0 to these bits [15:8] read-write DEVICEADDR During the USB enumeration process, the host sends a device a unique 7-bit address, which the USB core copies into this register. The USB Core will automatically respond only to its assigned address. During the USB RESET, this register will be cleared to zero. [22:16] read-write TEST_MODE USB Test Mode 000: normal operation 001: Test_J 010: Test_K 011: Test_SE0_NAK 100: Test_Packet [USB 2.0, Sec 7.1.20, p 169; Sec 9.4.9, Table 9-7, p 259] [25:23] read-write SETUP_CLR_BUSY Allow device to ACK SETUP data/status phase packets [26:26] read-write NAKALL Set '1' to this bit, the HW will NAK all transfers from the host in all endpoint1-31. [31:31] read-write DEV_FRAMECNT FRAMECNT register 0x4 32 read-only 0x0 0x3FFF MICROFRAME MICROFRAME contains a count 0-7 which indicates which of the 8 125-microsecond micro-frames last occurred. This register is active only when Bay is operating at high speed (480 Mbits/sec). [2:0] read-only FRAMECNT Every millisecond the host sends a SOF token indicating 'Start Of Frame,' along with an 11-bit incrementing frame count. The Bay copies the frame count into these registers at every SOF. One use of the frame count is to respond to the USB SYNC_FRAME Request. If the USB core detects a missing or garbled SOF, it generates an internal SOF and increments USBFRAMEL-USBRAMEH. [13:3] read-only DEV_PWR_CS Power management control and status 0x8 32 read-write 0x8 0xDD SIGRSUME L2-Suspend: Set SIGRSUME=1 to drive the 'K' state onto the USB bus. This should be done only by a device that is capable of remote wakeup, and then only during the SUSPEND state. To signal RESUME, set SIGRSUME=1, waits 10-15 ms, then set SIGRSUME=0. The bit is set and cleared by firmware for device-initiated resume from suspend state. L1-Sleep: The bit is set by firmware and cleared by hardware for device-initiated resume from L1-sleep. The resume is driven for 50us. [0:0] read-write NOSYNSOF If set to 1, disable synthesizing missing SOFs. [2:2] read-write DISCON Setting this bit to '1' will disconnect HW from the USB bus by removing the internal 1.5 K pull-up resistor from the D+ [3:3] read-write DEV_SUSPEND Puts the USB device controller and PHY into suspend mode (pull up connected, drivers, PLLs etc turned off). [4:4] read-write FORCE_FS Forces the device controller to enumerate as FS-only device. [6:6] read-write HSM If HSM=1, the SIE is operating in High Speed Mode 0-1 transition of this bit causes a HSGRANT interrupt request. [7:7] read-only DEV_SETUPDAT_0 SETUPDAT0 register 0xC 32 read-only 0x0 0xFFFFFFFF SETUP_REQUEST_TYPE Setup data field [7:0] read-only SETUP_REQUEST Setup data field [15:8] read-only SETUP_VALUE Setup data field [31:16] read-only DEV_SETUPDAT_1 SETUPDAT1 register 0x10 32 read-only 0x0 0xFFFFFFFF SETUP_INDEX Setup data field [15:0] read-only SETUP_LENGTH Setup data field [31:16] read-only DEV_TOGGLE Data toggle for endpoints 0x14 32 read-write 0x100 0x1FF ENDPOINT Endpoint [3:0] read-write IO 1=IN, 0=OUT [4:4] read-write R Write '1' to reset data toggle to '0'. When both R and S are set, behavior is undefined. [5:5] read-write S Write '1' to set data toggle to '1'. When both R and S are set, behavior is undefined. [6:6] read-write Q Current value of toggle bit for EP selected in IO/ENDPOINT [7:7] read-only TOGGLE_VALID Indicates Q is valid for selected endpoint, may be polled in s/w. After writing to R/S, indicates write completion. This bit must be cleared by s/w to initiate an operation. [8:8] read-write 16 4 DEV_EPI_CS[%s] IN Endpoint Control and Status register 0x18 32 read-write 0x4040 0xFCFDFFFF PAYLOAD Max number of bytes transferred for each token 0=1024 (Powerup default value = 64) [9:0] read-write TYPE The End Point Type (Control on EP0 only) 00: Control 01: Isochronous 10: Bulk 11: Interrupt [11:10] read-write ISOINPKS Number of packets to be sent per microframe (aka high-bandwidth mode ISO). For this implementation only EP3 and EP7 support values other than 1. EP3 and EP7 support values 1..3. This field must be 0 for non-ISO endpoints. [13:12] read-write VALID Set VALID=1 to activate an endpoint, and VALID=0 to de-activate it. All USB endpoints default to valid. An endpoint whose VALID bit is 0 does not respond to any USB traffic. [14:14] read-write NAK Setting this bit causes NAK on IN transactions. [15:15] read-write STALL Set this bit to '1' to stall an endpoint, and to '0' to clear a stall. [16:16] read-write COMMIT Set whenever an IN token was ACKed by the host. [18:18] read-write BNAK When the host sends an IN token to any Bulk IN endpoint which does not have data to send, the Bay automatically NAKs the IN token and asserts this interrupt. Note that this bit will not be set if either the Endpoint NAK or global NAK_ALL bits are set when the NAK is transmitted [19:19] read-write DONE Indicates transfer is done (UIB_EPI_XFER_CNT=0). This bit must be cleared by s/w. [20:20] read-write ZERO Indicates a zero length packet was returned to the host in an IN transaction. Must be cleared by s/w. [21:21] read-write SHORT Indicates a shorter-than-maxsize packet was received, but UIB_EPI_XFER_CNT did not reach 0). [22:22] read-write ISOERR The ISO_ERR is set when ISO data PIDs arrive out of sequence (applies to high speed only), or when an an ISO packet was dropped because no data was available (FS or HS) [23:23] read-write COMMIT_MASK Interrupt mask for COMMIT bit [26:26] read-write BNAK_MASK Interrupt mask for BNAK bit [27:27] read-write DONE_MASK Interrupt mask for DONE bit [28:28] read-write ZERO_MASK Interrupt mask for ZERO bit [29:29] read-write SHORT_MASK Interrupt mask for SHORT bit [30:30] read-write ISOERR_MASK Interrupt mask for ISOERR bit [31:31] read-write 16 4 DEV_EPI_XFER_CNT[%s] IN Endpoint remaining transfer length register 0x58 32 read-write 0x0 0xFFFFFFFF BYTES_REMAINING Number of bytes remaining in the transfer. This value will never go negative (if more bytes are transferred than remaining in counter, counter will go to 0). [31:0] read-write 16 4 DEV_EPO_CS[%s] OUT Endpoint Control and Status 0x98 32 read-write 0x4040 0xFEFFFFFF PAYLOAD Max number of bytes transferred for each token 0=1024 (Powerup default value = 64) [9:0] read-write TYPE The End Point Type (Control on EP0 only) 00: Control 01: Isochronous 10: Bulk 11: Interrupt [11:10] read-write ISOINPKS Number of packets to be sent per microframe (aka high-bandwidth mode ISO). For this implementation only EP3 and EP7 support values other than 1. EP3 and EP7 support values 1..3. This field must be 0 for non-ISO endpoints. [13:12] read-write VALID Set VALID=1 to activate an endpoint, and VALID=0 to de-activate it. All USB endpoints default to valid. An endpoint whose VALID bit is 0 does not respond to any USB traffic. [14:14] read-write NAK Setting this bit causes NAK on OUT and PING transactions. [15:15] read-write STALL Set this bit to '1' to stall an endpoint, and to '0' to clear a stall. [16:16] read-write OVF Indicates a packet was received in an OUT token with more bytes than PAYLOAD. [17:17] read-write COMMIT Set whenever device controller ACKs an OUT token. [18:18] read-write BNAK When the host sends a PING/OUT token to any Bulk OUT endpoint, which does not have an empty buffer, the Bay automatically NAKs the token and asserts this interrupt. Note that this bit will be set if there is no empty buffer at the receipt of the OUT Packet and if neither the Endpoint NAK or global NAK_ALL bits are set when the NAK is transmitted. [19:19] read-write DONE Indicates transfer is done (UIB_EPI_XFER_CNT=0). This bit must be cleared by s/w. [20:20] read-write ZERO Indicates a zero length packet was returned to the host in an IN transaction. Must be cleared by s/w. [21:21] read-write SHORT Indicates a shorter-than-maxsize packet was received, but UIB_EPI_XFER_CNT did not reach 0). [22:22] read-write ISOERR The ISO_ERR is set when ISO data PIDs arrive out of sequence (applies to high speed only), or when an an ISO packet was dropped because no buffer space was available (FS or HS) [23:23] read-write OVF_MASK Interrupt mask for OVUF bit [25:25] read-write COMMIT_MASK Intterupt mask for COMMIT bit [26:26] read-write BNAK_MASK Interrupt mask for BNAK bit [27:27] read-write DONE_MASK Interrupt mask for DONE bit [28:28] read-write ZERO_MASK Interrupt mask for ZERO bit [29:29] read-write SHORT_MASK Interrupt mask for SHORT bit [30:30] read-write ISOERR_MASK Interrupt mask for ISOERR bit [31:31] read-write 16 4 DEV_EPO_XFER_CNT[%s] OUT Endpoint remaining transfer length register 0xD8 32 read-write 0x0 0xFFFFFFFF BYTES_REMAINING Number of bytes remaining in the transfer. This value will never go negative (if more bytes are transferred than remaining in counter, counter will go to 0). [31:0] read-write DEV_CTL_INTR_MASK CONTROL interrupt mask register 0x118 32 read-write 0x0 0x1FFF SETADDR Active high. 1 - Masks the SET_ADDRESS interrupt. 0 - Unmasks the SET_ADDRESS interrupt. [0:0] read-write SOF Set whenever a SOF occurrs [1:1] read-write SUSP Set when the host suspends the USB bus (USB SUSPEND) [2:2] read-write URESET Set when the host has initiated USB RESET (2.5us single ended 0 on bus) [3:3] read-write HSGRANT Set when the host grants high speed communications. [4:4] read-write SUTOK Set whenever a (valid of invalid) SETUP token is received [5:5] read-write SUDAV Set when a valid SETUP token and data is received. Data from this token can be read from UIB_DEV_SETUPDAT. [6:6] read-write ERRLIMIT USB Error limit detect from UIB_DEV_CS (COUNT>=LIMIT) [7:7] read-write URESUME Set when the host has initiated USB RESUME (>2.5us K state on bus) [8:8] read-write STATUS_STAGE Set when host completes Status Stage of a Control Transfer [9:9] read-write L1_SLEEP_REQ Set when host issues a LPM-L1-SLEEP request [10:10] read-write L1_URESUME Set when the host has initiated USB RESUME to exit from L1-Sleep low-power mode. It indicates both host-initiated and host-reflected resume request. [11:11] read-write RESETDONE Set when an end-of-reset signaling is detected by the device. [12:12] read-write DEV_CTL_INTR CONTROL interrupt request register 0x11C 32 read-write 0x0 0x1FFF SETADDR Set when host issues a SET_ADDR request to the device [0:0] read-write SOF Set whenever a SOF occurrs [1:1] read-write SUSP Set when the host suspends the USB bus (USB SUSPEND) [2:2] read-write URESET Set when the host has initiated USB RESET (2.5us single ended 0 on bus) [3:3] read-write HSGRANT Set when the host grants high speed communications. [4:4] read-write SUTOK Set whenever a (valid of invalid) SETUP token is received [5:5] read-write SUDAV Set when a valid SETUP token and data is received. Data from this token can be read from UIB_DEV_SETUPDAT. [6:6] read-write ERRLIMIT USB Error limit detect from UIB_DEV_CS (COUNT>=LIMIT) [7:7] read-write URESUME Set when the host has initiated USB RESUME (>2.5us K state on bus) [8:8] read-write STATUS_STAGE Set when host completes Status Stage of a Control Transfer [9:9] read-write L1_SLEEP_REQ Set when host issues a LPM token to enter L1-SLEEP request [10:10] read-write L1_URESUME Set when host sent a USB RESUME request when in L1-Sleep low-power mode. It indicates both host-initiated and host-reflected resume request. [11:11] read-write RESETDONE Set when an end-of-reset signaling is detected by the device [12:12] read-write DEV_CTL_INTR_MASKED CONTROL interrupt masked register 0x120 32 read-only 0x0 0x1FFF SETADDR_MASKED Mask status for SET_ADDRESS interrupt [0:0] read-only SOF_MASKED Mask status for SOF interrupt [1:1] read-only SUSP_MASKED Mask status for Suspend interrupt [2:2] read-only URESET_MASKED Mask status for USB interface interrupt [3:3] read-only HSGRANT_MASKED Mask status for interrupt indicating the host accepting high speed communications. [4:4] read-only SUTOK_MASKED Mask status for SETUP token interrupt. [5:5] read-only SUDAV_MASKED Mask status for interrupt - Receiving SETUP and Data tokens. [6:6] read-only ERRLIMIT_MASKED Mask status for USB Error limit detect interrupt [7:7] read-only URESUME_MASKED Mask status for host initiated USB RESUME interrupt (>2.5us K state on bus) [8:8] read-only STATUS_STAGE_MASKED Mask status for interrupt indicating host completed Status Stage of a Control Transfer [9:9] read-only L1_SLEEP_REQ_MASKED Mask status for interrupt indicating host issued a LPM token for L1-SLEEP request [10:10] read-only L1_URESUME_MASKED Mask status for interrupt indicating host sent a resume request when in L1-Sleep low-power mode. It indicates both host-initiated and host-reflected resume request. [11:11] read-only RESETDONE_MASKED Mask status for interrupt indicating end-of-reset signaling detected by the device controller. [12:12] read-only DEV_CTL_INTR_SET CONTROL interrupt set register 0x124 32 read-write 0x0 0x1FFF SETADDR_MASKED Write with '1' to set corresponding bit in interrupt request register. [0:0] read-write SOF_MASKED Write with '1' to set corresponding bit in interrupt request register. [1:1] read-write SUSP_MASKED Write with '1' to set corresponding bit in interrupt request register. [2:2] read-write URESET_MASKED Write with '1' to set corresponding bit in interrupt request register. [3:3] read-write HSGRANT_MASKED Write with '1' to set corresponding bit in interrupt request register. [4:4] read-write SUTOK_MASKED Write with '1' to set corresponding bit in interrupt request register. [5:5] read-write SUDAV_MASKED Write with '1' to set corresponding bit in interrupt request register. [6:6] read-write ERRLIMIT_MASKED Write with '1' to set corresponding bit in interrupt request register. [7:7] read-write URESUME_MASKED Write with '1' to set corresponding bit in interrupt request register. [8:8] read-write STATUS_STAGE_MASKED Write with '1' to set corresponding bit in interrupt request register. [9:9] read-write L1_SLEEP_REQ_MASKED Write with '1' to set corresponding bit in interrupt request register. [10:10] read-write L1_URESUME_MASKED Write with '1' to set corresponding bit in interrupt request register. [11:11] read-write RESETDONE_MASKED Write with '1' to set corresponding bit in interrupt request register. [12:12] read-write DEV_EP_INTR_MASK USB EP interrupt mask register 0x128 32 read-write 0x0 0xFFFFFFFF EP_IN Bit <x> masks any interrupt from EPI_CS[x] [15:0] read-write EP_OUT Bit <16+x> masks any interrupt from EPO_CS[x] [31:16] read-write DEV_EP_INTR USB EP interrupt request register 0x12C 32 read-write 0x0 0xFFFFFFFF EP_IN Bit <x> indicates an interrupt from EPI_CS[x] [15:0] read-write EP_OUT Bit <16+x> indicates an interrupt from EPO_CS[x] [31:16] read-write DEV_EP_INTR_MASKED USB EP interrupt masked register 0x130 32 read-only 0x0 0xFFFFFFFF EP_IN 1 - Corresponding interrupt is masked. 0 - Not masked. Bit <x> indicates an interrupt from EPI_CS[x] [15:0] read-only EP_OUT 1 - Corresponding interrupt is masked. 0 - Not masked. Bit <16+x> indicates an interrupt from EPO_CS[x] [31:16] read-only DEV_EP_INTR_SET USB EP interrupt set register 0x134 32 read-write 0x0 0xFFFFFFFF EP_IN Write with '1' to set corresponding bit in interrupt request register. [15:0] read-write EP_OUT Write with '1' to set corresponding bit in interrupt request register. [31:16] read-write DEV_EP_INGRS_INTR_MASK USB EP INGRS interrupt mask register 0x138 32 read-write 0x0 0xFFFFFFFF EP_INGRS_ZLP_RCVD Bit <x> masks any interrupt from DEV_EP_INGRS_INTR[x] [15:0] read-write EP_INGRS_SLP_RCVD Bit <16+x> masks any interrupt from DEV_EP_INGRS_INTR[x] [31:16] read-write DEV_EP_INGRS_INTR USB EP INGRS interrupt request register 0x13C 32 read-write 0x0 0xFFFFFFFF EP_INGRS_ZLP_RCVD Bit <x> indicates a zero-packet arrival interrupt for each endpoint. [15:0] read-write EP_INGRS_SLP_RCVD Bit <16+x> indicates a zero-packet arrival interrupt for each endpoint. [31:16] read-write DEV_EP_INGRS_INTR_MASKED USB EP INGRS interrupt masked register 0x140 32 read-only 0x0 0xFFFFFFFF EP_INGRS_ZLP_RCVD 1 - Corresponding interrupt is masked. 0 - Not masked. Bit <x> indicates masked bit for DEV_EP_INGRS_INTR[x] [15:0] read-only EP_INGRS_SLP_RCVD 1 - Corresponding interrupt is masked. 0 - Not masked. Bit <16+x> indicates masked bit for DEV_EP_INGRS_INTR[x] [31:16] read-only DEV_EP_INGRS_INTR_SET USB EP INGRS interrupt set register 0x144 32 read-write 0x0 0xFFFFFFFF EP_INGRS_ZLP_RCVD Write with '1' to set corresponding bit in interrupt request register. [15:0] read-write EP_INGRS_SLP_RCVD Write with '1' to set corresponding bit in interrupt request register. [31:16] read-write DEV_EP_EGRS_INTR_MASK USB EP EGRS interrupt mask register 0x148 32 read-write 0x0 0xFFFFFFFF EP_EGRS_ZLP_SENT Bit <x> masks any interrupt from DEV_EP_EGRS_INTR[x] [15:0] read-write EP_EGRS_SLP_SENT Bit <16+x> masks any interrupt from DEV_EP_EGRS_INTR[x] [31:16] read-write DEV_EP_EGRS_INTR USB EP EGRS interrupt request register 0x14C 32 read-write 0x0 0xFFFFFFFF EP_EGRS_ZLP_SENT 1 - Firmware sets to schedule a ZLP request on egress path for an endpoint. 0 - Hardware clears to indicate a ZLP packet is sent after all pending transfers for an endpoint. Each bit represents an endpoint on egress path. [15:0] read-write EP_EGRS_SLP_SENT 1 - Firmware sets to schedule a SLP request on egress path for an endpoint. 0 - Hardware clears to indicate a SLP packet is sent on egress path for an endpoint. Each bit represents an endpoint on egress path. [31:16] read-write DEV_EP_EGRS_INTR_MASKED USB EP EGRS interrupt masked register 0x150 32 read-only 0x0 0xFFFFFFFF EP_EGRS_ZLP_SENT 1 - Corresponding interrupt is masked. 0 - Not masked. Bit <x> indicates an interrupt from DEV_EP_EGRS_INTR[x] [15:0] read-only EP_EGRS_SLP_SENT 1 - Corresponding interrupt is masked. 0 - Not masked. Bit <16+x> indicates an interrupt from DEV_EP_EGRS_INTR[x] [31:16] read-only DEV_EP_EGRS_INTR_SET USB EP EGRS interrupt set register 0x154 32 read-write 0x0 0xFFFFFFFF EP_EGRS_ZLP_SENT Write with '1' to set corresponding bit in interrupt request register. [15:0] read-write EP_EGRS_SLP_SENT Write with '1' to set corresponding bit in interrupt request register. [31:16] read-write POWER USB 2.0 Device Power, Clock & Reset Control Register 0x158 32 read-write 0x12 0x3F RESETN Active LOW reset signal for all logic in the block. Note that reset is active on all flops in the block when either system reset is asserted (RESET# pin or SYSTEM_POWER.RESETN is asserted) or this signal is active. After setting this bit to 1, firmware shall poll and wait for the 'active' bit to assert. Reading '1' from 'resetn' does not indicate the block is out of reset - this may take some time depending on initialization tasks and clock frequencies. [0:0] read-write EPM_DCG_ENABLE Active High. 1 - Indicates that dynamic clock gating is enabled in the EPM core. 0 - Indicates that dynamic clock gating is disabled in the EPM core. [1:1] read-write CLK_SCALING_EN Active High. 1 - Improves timing margin for HS mode when clk_slow is scaled down to 75MHz. 0 - No change in timing margin for HS mode when clk_slow is at 100MHz. [2:2] read-write SEL_EXT_FS_CLK Active High. 1 - Selects an external PLL to provide clock during full-speed mode of operation. 0 - Selects an internal PLL in PHY to provide clock during full-speed mode of operation. [3:3] read-write LPM_ENABLE Active High. 1 - Indicates LPM feature is enabled in controller. 0 - Indicates LPM feature is disabledi n controller. [4:4] read-write VBUS_VALID Active High. 1 - Indicates VBUS supply ready and stable on USB interface. 0 - Indicates VBUS supply is not ready on USB interface. [5:5] read-write DEV_LPM_ATTR USB 2.0 Device LPM HIRD Register 0x15C 32 read-write 0x10E00 0xFFFF3F RMT_WAKEUP_ENABLE Active High. 1 - Host enabled support for remote wake-up by device during L1-Sleep. 0 - Host disabled support for remote wake-up by device during L1-sleep. [0:0] read-only HIRD Host publishes value of the HIRD ranging from 75us till 9.95ms for the device. 0x0: Duration of resume sequence by host 75us. 0x1: Duration of resume sequence by host 100us. 0x2: Duration of resume sequence by host 150us. 0x3: Duration of resume sequence by host 250us. 0x4: Duration of resume sequence by host 350us. 0x5: Duration of resume sequence by host 450us. 0x6: Duration of resume sequence by host 950us. 0x7: Duration of resume sequence by host 1950us. 0x8: Duration of resume sequence by host 2950us. 0x9: Duration of resume sequence by host 3950us. 0xA: Duration of resume sequence by host 4950us. 0xB: Duration of resume sequence by host 5950us. 0xC: Duration of resume sequence by host 6950us. 0xD: Duration of resume sequence by host 7950us. 0xE: Duration of resume sequence by host 8950us. 0xF: Duration of resume sequence by host 9950us. [4:1] read-only NYET Active High. 1 - Sends a NYET response for a LPM token received from the Host. 0 - No NYET response sent to the host for a LPM token received. [5:5] read-write T_L1_TOKEN_RETRY Programmable value to wait for 10us after a LPM token is received and before the device enters L1-state. Allowed values range from 240 till 300 as required by USB LPM specification. [23:8] read-write DEV_LPM_TIM_1 USB 2.0 Device LPM Timer Parameter Register 0x160 32 read-write 0x5DC 0xFFF T_L1_DEV_DRV_RESUME Programmable value to wait for 50us while driving resume when in L1-sleep low-power mode. Allowed values range from 0x5BE till 0x5FA as required by USB LPM specification. [11:0] read-write DEV_CHIRP_OVERRIDE USB 2.0 Device Chirp Override Register 0x164 32 read-write 0x0 0xFF OVERRIDE_FSM Active High. 1 - Allows override of initialization sequence by forcing transitions indicated by other bits of this register. 0 - Override is disabled. [0:0] read-write FORCE_CHIRP_K Active High. 1 - Forces chirp-K sequence on interface if override is enabled. 0 - Disables chirp-K sequence on interface. [1:1] read-write FORCE_CHIRP_J Active High. 1 - Forces chirp-J sequence on interface if override is enabled. 0 - Disables chirp-J sequence on interface. [2:2] read-write STATE Override state value for chirp state machine when override is enabled. 0x0 - Full-Speed Mode, 0xD - High-Speed Mode. [7:3] read-write CRU_EXT_LSFS_CLK_DIVIDER EXT LSFS Clock Divider Register 0x168 32 read-write 0x0 0xF DIVN_VALUE Programmable divider to generated 30MHz UTMI clock from external clk_hf_i source (150MHz). Duty cycle is ((1/divn_value)*100)) percent for the generated clock. 0x0: Disables the clock. 0xN: Divide-by-N of clk_hf. [3:0] read-write DEV_TIM_T_DETRST_FILT USB 2.0 Device Init Timing 1 Register 0x16C 32 read-write 0x780005A 0xFFFFFFFF T_DETRST Programmable value to detect T_DETRST timing parameter for reset detection as governed by USB 2.0 specification. The value ranges from 0x4B to 0x493E0. [19:0] read-write T_FILT Programmable value to detect T_FILT timing parameter for chirp detection as governed by USB 2.0 specification. Supports from 2.5us to 136.5us. The specification does not provide an upper limit for this field. [31:20] read-write DEV_TIM_T_WTFS USB 2.0 Device Init Timing 2 Register 0x170 32 read-write 0xEAC4 0x1FFFF T_WTFS Programmable value to detect T_WTFS timing parameter to switch to full-speed mode after no chirp is detected during interface reset request. The value ranges from 0x7530 to 0x124F8. [16:0] read-write DEV_TIM_T_SUSP USB 2.0 Device Init Timing 3 Register 0x174 32 read-write 0x15FF4 0x1FFFF T_SUSP Programmable timing parameter value to detect suspend in full-speed or high-speed mode. [16:0] read-write DEV_TIM_T_WTRSTHS USB 2.0 Device Init Timing 4 Register 0x178 32 read-write 0x3A98 0xFFFF T_WTRSTHS Programmable timing parameter value. It indicates time a device must wait after reverting to FS before sampling the bus state for SE0. Support values range from 0xBB8 to 0x668A. [15:0] read-write DEV_TIM_T_UCH USB 2.0 Device Init Timing 5 Register 0x17C 32 read-write 0xEA60 0x1FFFF T_UCH Programmable timing parameter value. It indicates minimum chirp pulse width in a device in SE0. Support values range from 0x7530 to 0x15F90. [16:0] read-write DEV_TIM_T_WTREV_WTRSTFS USB 2.0 Device Init Timing 6 Register 0x180 32 read-write 0x15F90 0x1FFFF T_WTREV_WTRSTFS Programmable timing parameter value. It indicates minimum chirp pulse width in a device in SE0. Support values range from 0x7530 to 0x15F90. [16:0] read-write EPM_CS EPM Control and Status Register 0x200 32 read-write 0x0 0x7 EGRS_FORCE_FLUSH_ALL 1 - Forcefully flushes the Egress SRAM. 0 - Does not flush the Egress SRAM. [0:0] read-write IGRS_FORCE_FLUSH_ALL 1 - Forcefully flush the contents in Ingress SRAM. 0 - Does not flush Ingress SRAM. [1:1] read-write ALLOW_TRIG_ON_SLP 1 - Allow EPM to send a trigger to DMA when interrupt is cleared by the processor for SLP on ingress path. 0 - Allow processor to send a trigger to DMA for SLP on ingress path [2:2] read-write EPM_DEBUG EPM Debug Register 0x208 32 read-only 0x0 0xF3F C_EPNUM Indicates the active endpoint for which the transfer is going on in egress path. [3:0] read-only C_REQUEST Indicates current request for active endpoint for which the transfer is going on in egress path. [5:4] read-only ACTIVE_EP_NUM Indicates the active endpoint for which the transfer is going on in ingress path. [11:8] read-only 16 4 EEPM_ENDPOINT[%s] Egress EPM per Endpoint Control and Status 0x220 32 read-only 0x0 0x3FF EGRS_SLP_BYTE_COUNT Number of bytes in short-length packet in the last USB transaction. [9:0] read-only 16 4 IEPM_ENDPOINT[%s] Ingress EPM Per Endpoint Control and Status 0x260 32 read-only 0x0 0x3FF INGRS_SLP_BYTE_COUNT Number of bytes in short-length packet in last USB transaction. [9:0] read-only 16 4 EEPM_DEBUG_ENDPOINT[%s] Egress EPM Per Endpoint Debug 0x2A0 32 read-only 0x0 0x7 EGRS_P_REQUESTS Number of pending requests for each endpoint in Egress SRAM. Used for debug only. [1:0] read-only EGRS_DMA_TRIGGERED 1 - Egress path sent a trigger to the DMA. 0 - No trigger is sent to the DMA. Used for debug only. [2:2] read-only 16 4 IEPM_DEBUG_ENDPOINT[%s] Ingress EPM Per Endpoint Debug 0x2F0 32 read-only 0x0 0x1 INGRS_DMA_TRIGGERED 1 - Indicates the DMA was triggered on ingress path. 0 - No trigger sent to DMA on ingress path. Used for debug only. [0:0] read-only USBHSPHY USB 2.0 PHY Registers 0x00000800 AFE_CONTROL_1 AFE Control register #1 0x0 32 read-write 0x0 0xFFFFFFFF HS_PRED_DP_SEL HS PMOS Pre-driver Skew [1:0] read-write HS_PRED_DN_SEL HS NMOS Pre-driver Skew [3:2] read-write HS_AMP_SEL HS Driver Amplitude Control [7:4] read-write HS_PREE_SEL HS Driver Pre-emphasis Amplitude [10:8] read-write HS_SR_FINE_SEL HS Driver Fine Slew Rate Control [13:11] read-write HS_TED_LP_MODE HS TED Low Power Mode 0: Normal operation 1: Reduced current mode [14:14] read-write EN_LANE_SWAP The DP/DN pins are swapped on both the transmit and receive direction [15:15] read-write HS_CTLE_SEL HS Receiver CTLE Control [18:16] read-write FS_VTRIG_SEL FS Receiver Trigger Voltage Control [21:19] read-write FS_SR_SEL FS Driver Slew Rate Control [25:22] read-write LS_SR_SEL LS Driver Slew Rate Control [27:26] read-write HS_LB_EN This bit enables the loopback mode. In this mode, the TX can either be looped back at the pads or at the input of the AFE. This is specified by the RX_EN of the AFE. [28:28] read-write HS_TED_25_MODE HS Squelch VDDD Selection bit 1: VDDD = 3.3V range - DONOT USE THIS SETTING for normal operation 0: VDDD = 1.8V range [29:29] read-write CPU_DELAY_ENABLE_VCCD INTR0.ENABLE_VCCD indicates that the 2p5 regulator is powered up. FW is required to set this bit after a delay as specified in the AFE requirements [30:30] read-write CPU_DELAY_ENABLE_HS_VCCD INTR0.ENABLE_HS_VCCD indicates that the 1p1 regulator is powere up. FW is required to set this aftera a delay as specifed in the AFE requirements [31:31] read-write AFE_CONTROL_2 AFE Control register #2 0x4 32 read-write 0x0 0x27FFF AFE_DFT_SEL N/A [9:0] read-write EUSB_RX_CRUDE_EN Enables the OVERRIDE function for the eUSB receiver. This bit is used in conjunction with EUSB_RX_MUX_SEL and EUSB_RX_MISSION_EN. When 0, the switching between default and mission mode receiver happens through ENABLE_EUSB_RX [10:10] read-write EUSB_RX_MUX_SEL This bit selects between the default receiver and mission mode receiver 0 - Default receiver selected 1 - Mission mode receiver selected [11:11] read-write EUSB_RX_OVERRIDE N/A [12:12] read-write EUSB_RX_MISSION_EN This bit enables the default receiver 0 - mission mode receiver enabled based on se_rx_en. In testmode this can be done by setting ENABLE_EUSB_RX and AFE_CONTROL_3.SE_RX_EN_EDP 1 - default mode receiver enabled [13:13] read-write SE_RX_SE1_FILTER_EN_N Enable signal for SE1 RX filter, active LOW [14:14] read-write ENABLE_EUSB_RX This bit enabled the mission mode receiver for EUSB. Until this the default crude receiver is ON. This bit must be set after REG_SW_1P2 is turned on and cleared before disabling REG_SW_1P2 [17:17] read-write UTMI_CONTROL UTMI Control register 0x8 32 read-write 0x55420000 0xFFFFFFFF SOFT_DISCONNECT_N 1: Connect D+/D Pull downs for DS PHY and Pull-ups for US PHY in Non-Driving Mode indicated by op_mode=01. For test-mode controllability only. [0:0] read-write VLOAD Active Low Signal. On setting this signal to 1, the VCONTROL values determin the PHY Test modes. To change the testmode this bit has to be cleared and set again. [1:1] read-write VCONTROL_TESTCODE This will contain the TESTCODE PHY during PHY Test modes and BISTMODE for BIST operation. This value is latched by PHY using VLOAD during Test Modes and BIST_EN during BIST mode. Refer to the PHY BROS for the Testcodes [5:2] read-write VCONTROL_TESTDATA This will contain the TESTDATA for the PHY during PHY Test modes. This value is latched by PHY using VLOAD during Test Modes and BIST_EN during BIST mode. Refer to the PHY BROS for the testdata [9:6] read-write BIST_EN Triggers bist operation. VCONTROL values specifies the parameters of bist are latched when this bit is test. [10:10] read-write TUNE_BYPASS_EN 1: Bypass calibration for D+ and D- lines [11:11] read-write EXT_CAL_VALUE Apply this value to D+ and D- lines when self calibration is bypassed through CAL_BYPASS_EN=1 [16:12] read-write OTG_IN_SUSPEND N/A [17:17] read-write BIST_CONTINOUS_EN 1: If BIST_EN is 1, Bist will continue a long pattern specified in BIST_CONTINUOUS_PATTERN until BIST_EN==0. 0: If BIST_EN is 1, Bist will send one packet. [18:18] read-write LINESTATE_COMBO_SEQ Specifies if the generated linestate is filtered or unfiltered 0: use combo logic 1: use sequential logic [19:19] read-write LINESTATE_EXT_SEL Selects where the selection between combo and sequential logic is coming from. 0: Internal. Done by HW. 1: from LINE_STATE_COMBO_SEQ [20:20] read-write LINESTATE_CLK_SEL Selects clock input for the linestate module. 0: selects sieclk 1: selects clk480m [21:21] read-write CAL_BIG_LITTLE_ENDIAN 0: Little endian 5,4,3,2,1,0 1: Big endian 0,1,2,3,4,5 [22:22] read-write BIST_CONTINOUS_PATTERN Bist pattern sent when BIST_CONTINOUS_EN==1 and BIST_EN==1 [30:23] read-write REVERT_RPU_CTRL Setting this bit will revert the RPU control to the old logic used on HX3/Benicia. 0 - New implementation 1 - RPU Control not available in Serial Mode of operation [31:31] read-write CDR_CONTROL CDR registers 0xC 32 read-write 0x2143 0xFFFF CONF_EOI_VEC N/A [2:0] read-write CONF_HS_6_SYNC Enables 6 or 4 bit SYNC detection in HS Serial Interface for PHY 1: Enables 6 Bit SYNC detection 0: Enables 4 Bit SYNC detection [3:3] read-write EBUF_DEPTH Specifies the half depth of the elastic buffer. 0: 13 1: 12 2: 14 3: 15 [5:4] read-write CDR_CONFIG_1 It specifies the phase offset at which serial data is selected during recovery 0 : Serial data is captured 3 phases before clkrec. 1: serial data is captured 2 phasses before clkrec [6:6] read-write CDR_ENABLE 0: CDR is kept in reset 1: CDR is enabled CDR has to be enabled only after the PLL is locked [7:7] read-write SQUELCH_FILTER Squelch Filter specified in terms of 480MHz cycles 0 - no filtering 1-5 - 2-6 cycles of filtering [10:8] read-write SYNC_MATCH_PATTERN 0: SYNC declared on seeing 3 KJ pairs 1: SYNC delcared on seeing 2 KJ pairs [11:11] read-write GATE_SERIAL_IN_TILL_SQUELCH 0: Data is synchronized in parallel to squelch. Recovered data is qualified by squelch filter 1: Data input to CDR is qualified by squelch. Introduces delay on the repeater latency path [12:12] read-write SERIAL_IN_DELAY Bits [1:0]Delaying the Serial_in signal in CDR. There is a mismatch of 3 cycles between data and TED on the input to the elasticbuffer. This can be used to delay the data also to the elastic buffer. The squelch filter gates the output of this delay Bit[2] Risk Mitigation for CDR. Will fasten lock time by changing phases once in 2 cycles, instead of once in 3 cycles [15:13] read-write BC_CONTROL UHC Battery Charging CSR Bank 0x10 32 read-write 0x0 0x7 CHRGR_DET_ON 1: Power on AFE charger detector circuit [0:0] read-write VDM_SRC_EN 1: Enables voltage source on DN pin. If lane swap is enabled, enables voltage source on DP pin [1:1] read-write VDP_SRC_EN 1: Enables voltage source on DP pin. If lane swap is enabled, enables voltage source on DN pin [2:2] read-write PLL_CONTROL_1 Primary PLL control register#1 0x14 32 read-write 0x0 0x3FFFEF7F RUN_AWAY_DEL Internal delay from comparator indicate run away to output rise [1:0] read-write RUN_AWAY_DIS Disable run away operation [2:2] read-write VCO_GAIN Gain of the vco circuit [6:3] read-write PLL_EN Enable pll core operation. This bit can only be set after SUPPLY_EN is set. Refer to PLL BROS for further details of startup sequencing [8:8] read-write SUPPLY_EN Enable the PLL suply [9:9] read-write LD_DELAY Lock window adjust [11:10] read-write LDO_VCO_BYPASS Bypass LDO operation - PLL core operate from vccd [13:13] read-write P_DIV Feedback divider - division [15:14] read-write Q_DIV Input divider division [17:16] read-write PLL_SPARE Spare bit for future use [18:18] read-write VCO_INIT_DIS Bypass core LDO [19:19] read-write ATST_SEL Test mode bits [23:20] read-write CAL_UP_DN Trim for up/dn calibration mismatch [27:24] read-write RA_UP_TR Trim for run away detector upper level threshold [29:28] read-write PLL_CONTROL_2 Primary PLL control register#2 0x18 32 read-write 0x2080 0xFE01FFFF EN_CPU_OVERIDE_PLL_LOCK Setting this bit will drive the CPU_OVERIDE_PLL_LOCK_VALUE to pll_lock [0:0] read-write CPU_OVERIDE_PLL_LOCK_VALUE Value to driven on pll_lock [1:1] read-write SOURCE_OF_PLL_LOCK Specifies whether the pll_lock towards the logic is filtered version or from the PLL Hard-IP directly 0: Filter 1: s40pllusb2 [2:2] read-write LOCK_DELAY The output of the PLL lock signal is filtered for #LOCK_DELAY of refclk. The PLL lock signal must be high for # of LOCK_DELAY before declaring LOCKED. Once the PLL lock signal is high, the internal counter for lock detection restarts. This register should be programmed when PLL_CONTROL.PLL_EN is 0. [10:3] read-write LOSS_LOCK_DELAY The output of the PLL lock signal is filtered for #LOSS_LOCK_DELAY of refclk. The PLL lock signal must be low for # of LOSS_LOCK_DELAY before declaring UNLOCKED. Once the PLL lock signal is low, the internal counter for lock loss detection restarts. This register should be programmed when PLL_CONTROL.PLL_EN is 0. [15:11] read-write JITTER_TEST_MODE Setting this bit will put the PHY that has the PLL inJitter measurement mode. In this mode a 240MHz signal generated on p0 is output through the HS transmitter. The References required for HS and the PLL should be enabled before setting this bit [16:16] read-write DIV_VALUE This register is used to divide the selected PLL output phase (Per PLL_CLKOUT_DDFT_SEL) for observing on DDFT [28:25] read-write PLL_CLKOUT_DDFT_SEL The selected PLL output will be divided by DIV_VALUE and routed to IP DDFT mux. DDFT selection: 0: p0 1: p45 2: p90 3: p135 4: p180 5: p225 6: p270 7: p315 [31:29] read-write TEST_PLL_CONTROL Test PLL control register 0x1C 32 read-write 0x0 0xFFFFEF7F RUN_AWAY_DEL Internal delay from comparator indicate run away to signal rise [1:0] read-write RUN_AWAY_DIS Disable run away operation [2:2] read-write VCO_GAIN Gain of the vco circuit [6:3] read-write PLL_EN Enable pll core operation [8:8] read-write SUPPLY_EN Enable the PLL suply [9:9] read-write LD_DELAY Lock window adjust [11:10] read-write LDO_VCO_BYPASS Bypass LDO operation - PLL core operate from vccd [13:13] read-write P_DIV Feedback divider - division [15:14] read-write Q_DIV Input divider division [17:16] read-write PLL_SPARE N/A [18:18] read-write VCO_INIT_DIS Bypass core LDO [19:19] read-write ATST_SEL Test mode bits [23:20] read-write CAL_UP_DN Trim for up/dn calibration mismatch [27:24] read-write RA_UP_TR Trim for run away detector upper level threshold [29:28] read-write TEST_LOCK_DELAY The output of the PLL lock signal is filtered for # of LOCK_DELAY. The PLL lock signal must be high for # of LOCK_DELAY before declaring LOCKED. Once the PLL lock signal is low, the internal counter for lock detection restarts. This register should be programmed when TEST_PLL_CONTROL.PLL_EN is 0. 0: 16 REFCLK 1: 32 REFCLK 2: 64 REFCLK 3: 128 REFCLK [31:30] read-write TEST_CONTROL Test control register 0x20 32 read-write 0x0 0x3F RUN_CALIBRATION Test mode trigger to run calibration [0:0] read-write CALIBRATED_VALUE Calibration value from calibration logic [5:1] read-only DDFT_CFG DDFT configuration 0x24 32 read-write 0x0 0xFFFF DDFT0_SEL 77 controlled_oncal, 76 controlled_cal_f1, 75 controlled_cal_f2, 74 controlled_hs_pree_en, 73 controlled_conn_rpu1, 72 controlled_conn_rpu2, 71 controlled_hs_ded_en, 70 controlled_hs_ded_reset, 69 controlled_hs_ded_start, 68 controlled_rpu_sel, 67 controlled_ls_nfs, 66 controlled_lsfs_diff_rx_en, 65 controlled_conn_rpd_dp, 64 controlled_conn_rpd_dn, 63 controlled_iref_en, 62 controlled_hs_rx_en, 61 controlled_hs_rx_buf_on, 60 controlled_hs_ted_en, 59 controlled_hs_tx_en_slow, 58 controlled_se_rx_en_dp, 57 controlled_se_rx_en_dn, 56 controlled_lfs_tx_en, 55 controlled_lfs_tx_in, 54 controlled_lfs_tx_on, 53 controlled_enase0, 52 eusb_onlfsserec, 51 controlled_enase1, 50 controlled_se_tx_in_edn, 49 controlled_se_tx_en_edn, 48:47 increase_ted_threshold[1:0], 46 irefgen_bypass_mode, 45 PLL_SUPPLY_EN 44 PLL_EN 43 AFE hs_ted_out 42 AFE cal_out 41 AFE se_rx_out_dn/se_rx_out_edn 40 AFE se_rx_out_dp/se_rx_out_edp 39 AFE hs_rx_out 38 AFE hs_ded_out 37 AFE lsfs_diff_rx_out 36 AFE stress_out 35 s40usb2afe_reg_2p5.ok_v25_vccd 34 s40usb2afe_reg_1p1.ok_vhs_vccd 33 0 32: PLL clockoutput per PLL_CONTROL2.PLL_CLKOUT_DDFT_SEL 31: reg_sw_1p2_control_enable_lv, 30: reg_2p5_control_enable_lv, 29: vrefgen_control_enable_lv 28: regulator_1p1_enable 27: irefgen_enable 26:19: lbstatus 18:11: vstatustester 10: intr0_cause_bistdone_done 9: intr0_cause_pll_run_away_sticky_change_done 8: intr0_cause_test_pll_run_away_sticky_change_done 7: 0 6: 0 5: test_pll_lock 4: pll_lock 3: test_pll_dft 2: pll_dft 1:0: afe_ddft [6:0] read-write DDFT0_POLARITY 0 - Observed DDFT output is not inverted 1 - DDFT output is inverted [7:7] read-write DDFT1_SEL 77 controlled_oncal, 76 controlled_cal_f1, 75 controlled_cal_f2, 74 controlled_hs_pree_en, 73 controlled_conn_rpu1, 72 controlled_conn_rpu2, 71 controlled_hs_ded_en, 70 controlled_hs_ded_reset, 69 controlled_hs_ded_start, 68 controlled_rpu_sel, 67 controlled_ls_nfs, 66 controlled_lsfs_diff_rx_en, 65 controlled_conn_rpd_dp, 64 controlled_conn_rpd_dn, 63 controlled_iref_en, 62 controlled_hs_rx_en, 61 controlled_hs_rx_buf_on, 60 controlled_hs_ted_en, 59 controlled_hs_tx_en_slow, 58 controlled_se_rx_en_dp, 57 controlled_se_rx_en_dn, 56 controlled_lfs_tx_en, 55 controlled_lfs_tx_in, 54 controlled_lfs_tx_on, 53 controlled_enase0, 52 eusb_onlfsserec, 51 controlled_enase1, 50 controlled_se_tx_in_edn, 49 controlled_se_tx_en_edn, 48:47 increase_ted_threshold[1:0], 46 irefgen_bypass_mode, 45 PLL_SUPPLY_EN 44 PLL_EN 43 AFE hs_ted_out 42 AFE cal_out 41 AFE se_rx_out_dn/se_rx_out_edn 40 AFE se_rx_out_dp/se_rx_out_edp 39 AFE hs_rx_out 38 AFE hs_ded_out 37 AFE lsfs_diff_rx_out 36 AFE stress_out 35 s40usb2afe_reg_2p5.ok_v25_vccd 34 s40usb2afe_reg_1p1.ok_vhs_vccd 33 0 32: PLL clockoutput per PLL_CONTROL2.PLL_CLKOUT_DDFT_SEL 31: reg_sw_1p2_control_enable_lv, 30: reg_2p5_control_enable_lv, 29: vrefgen_control_enable_lv 28: regulator_1p1_enable 27: irefgen_enable 26:19: lbstatus 18:11: vstatustester 10: intr0_cause_bistdone_done 9: intr0_cause_pll_run_away_sticky_change_done 8: intr0_cause_test_pll_run_away_sticky_change_done 7: 0 6: 0 5: test_pll_lock 4: pll_lock 3: test_pll_dft 2: pll_dft 1:0: afe_ddft [14:8] read-write DDFT1_POLARITY 0 - Observed DDFT output is not inverted 1 - DDFT output is inverted [15:15] read-write DIGITAL_CONTROL Provides control and configuration to digital blocks 0x28 32 read-write 0x120 0xEFFF7FEF DLAUNCH_SEL selects pre-emphasis phase 0: Pre-emphasis disabled 1: pll phase 2 2: pll phase 4 3: pll phase 6 [1:0] read-write TX_CLOCK_SOURCE_DFT Selects the source of TX clock. 0: TX clock source is the Primary of primary PLL, 1: TX clock source is the test PLL This bit should be set when loopback is enabled if the CDR is to be validated [2:2] read-write CLK480_PHASE_SEL Selects which phase of PLL to use as the TX clock for the PHY 0: selects phase 0 1: selects phase 4 [3:3] read-write DLAUNCH_ON_DELAY This field controls the delay from assertion of hs_tx_en_fast to assertion of hs_dum_sr_sel. The actual delay applied is DLAUNCH_ON_DELAY+1 [7:5] read-write DLAUNCH_OFF_DELAY N/A [10:8] read-write BURN_IN_EN Enables Burn-in Mode [11:11] read-write BURN 2p5 Regulator Burn-in Output Voltage Select [13:12] read-write DIS_PRE_EMPHASIS_HS_SOF Setting this bit to 1 disables the PRE_EMPHASIS during the EOP of an SOF packet. The bit position at which the pre-emphasis is disabled is determined by BIT_TIME_DIS_PRE_EMPHASIS [14:14] read-write BIT_TIME_DIS_PRE_EMPHASIS The 40-bit EOP counter is designed as two counter of 3-bits each to meet 480MHZ timing A 3-bit counter counts every 6 bits and another every 6-bit word (x6) The counters cycle through values as follows 0,4,6,7,3,1 - starting with 0 This field specifies the bit position, [21:19] specify the word and [18:16] specify the bit in the word [21:16] read-write CONTROL_HS_TX_IN 1: The hs_tx_in_dp/hs_tx_in_dn output ports of D-Launch block will be driven by the HX_TX_IN_DP_VALUE/HX_TX_IN_DN_VALUE 0: The hs_tx_in_dp/hs_tx_in_dn will be driven by D-launch logic [22:22] read-write HX_TX_IN_DP_VALUE When CONTROL_HS_TX_IN is set, hs_tx_in_dp output port of D-Launch block is driven by this register, otherwise it is driven by the D-Luanch logic. [23:23] read-write HX_TX_IN_DN_VALUE When CONTROL_HS_TX_IN is set, hs_tx_in_dn output port of D-Launch block is driven by this register, otherwise it is driven by the D-Luanch logic. [24:24] read-write CONTROL_HS_TX_PREE 1: The hs_tx_pree_dp/hs_tx_pree_dn output ports of D-Launch block will be driven by the HX_TX_PREE_DP_VALUE/HX_TX_PREE_DN_VALUE 0: The hs_tx_pree_dp/hs_tx_pree_dn will be driven by D-launch logic [25:25] read-write HX_TX_PREE_DP_VALUE When CONTROL_HS_TX_PREE is set, hs_tx_pree_dp output port of D-Launch block is driven by this register, otherwise it is driven by the D-Luanch logic. [26:26] read-write HX_TX_PREE_DN_VALUE When CONTROL_HS_TX_PREE is set, hs_tx_pree_dn output port of D-Launch block is driven by this register, otherwise it is driven by the D-Luanch logic. [27:27] read-write DISABLE_POWER_SAVING_CDR_CLK480M This bit disables the dynamic clock gating on CDR clock . [29:29] read-write DISABLE_POWER_SAVING_UTMI_HSRX_CLK480M This bit disables the dynamic clock gating on UTMI RX clock [30:30] read-write DISABLE_POWER_SAVING_UTMI_HSTX_CLK480M This bit disables the dynamic clock gating on UTMI TX clock [31:31] read-write VREFGEN_CONTROL VREFGEN control 0x2C 32 read-write 0x0 0x801FFFFF TED_SEL_0 TED Threshold Select for vref_ted_hi<0> [3:0] read-write TED_SEL_1 TED Threshold Select for vref_ted_hi<1> [7:4] read-write DED_SEL_0 DED Threshold Select for vref_ded<0> [11:8] read-write DED_SEL_1 DED Threshold Select for vref_ded<1> [15:12] read-write VREFGEN_ADFT_CTRL Analog DFT mode slection bits [19:16] read-write VREFGEN_ADFT_EN Analog DFT master enable [20:20] read-write ENABLE_LV Vrefgen block enable [31:31] read-write REG_SW_1P2_CONTROL REG_SW_1P2 control 0x30 32 read-write 0x0 0x8000003F SW_ADFT_CTRL analog DFT mode slection bits [3:0] read-write SW_ADFT_EN analog DFT master enable [4:4] read-write USE_REG Indicator that selects vout_1p2 driver: 0: regulator 1: switch [5:5] read-write ENABLE_LV Regulator block enable [31:31] read-write REG_1P1_CONTROL REG_1P1 control 0x34 32 read-write 0x0 0x8000011F ONEP1_ADFT_CTRL analog DFT mode slection bits [3:0] read-write ONEP1_ADFT_EN analog DFT master enable [4:4] read-write SWITCH_EN Indicator that selects vout_1p1 driver: 0: regulator 1: switch [8:8] read-write ENABLE_LV Regulator block enable [31:31] read-write REG_2P5_CONTROL REG_2P5_ control 0x38 32 read-write 0x0 0x8000011F TWOP5_ADFT_CTRL analog DFT mode slection bits [3:0] read-write TWOP5_ADFT_EN analog DFT master enable [4:4] read-write BYPASS_MODE When set the 2.5V regulator is bypassed to 3V3 supply.This bit has to be set to allow Deepsleep in Suspend mode [8:8] read-write ENABLE_LV Regulator block enable [31:31] read-write IREFGEN_CONTROL IREFGEN_ control 0x3C 32 read-write 0x0 0x8000011F IREF_ADFT_CTRL analog DFT mode slection bits [3:0] read-write IREF_ADFT_EN analog DFT master enable [4:4] read-write BYPASS_MODE When set vref/iref to PLL is generated from 3.3 supply and not SRSS vref. Forced to 1 in SCAN_TDF mode [8:8] read-write ENABLE_LV Irefgen block enable [31:31] read-write STATUS Status 0x40 32 read-only 0x0 0x7FFFFFD PLL_LOCK Live status of pll.pll_lock [0:0] read-only TEST_PLL_LOCK Live status of test_pll.pll_lock [2:2] read-only VSTATUSTESTER Refer to TEST_CONTROL.VCONTROL [10:3] read-only LBSTATUS 17: reginprogress 16: error 15: startbist 14: bistdone 13: txready 12: txvalid 11: rxactive 10: rxerror [18:11] read-only LINE_STATE Current state of single ended D+/D- receivers. Used in production test [20:19] read-only HOST_DISCONNECT Indicates Peripheral disconnect detection. Only valid if dppulldown and dmpulldown signals are '1'. In UHC, all the DS Ports dppulldown and dmpulldown are tied to '1'. Hence this bit is valid only for DS ports and invalid for US port. So named to keep UTMO spec compatibility, should have been named DEVICE_DISCONNECT otherwise. 0: Device Connected 1: Device Disconnect Detected This signal is the output from the UTMI+ PHY. During reset, the value resets to 0 and reflects the current status of the ports TDIS ot TCONN after reset is deasserted, typically in 2.5us. [21:21] read-only PLL_LOSS_CNT Count of PLL lossing lock [25:22] read-only BISTOK This bit should be read after INTR0.BISTDONE 0: BIST failed 1: BIST passed [26:26] read-only INTR0 INTR0 Cause. These are the wakeup interrupts get reflected on interrupt_wakeup pin. 0x44 32 read-write 0x0 0x7FF PLL_LOCK PLL is locked [0:0] read-write PLL_LOSS PLL lost lock. [1:1] read-write TEST_PLL_LOCK test_pll.pll_lock [2:2] read-write PLL_RUN_AWAY_STICKY_CHANGE pll.pll_run_away_sticky [3:3] read-write TEST_PLL_RUN_AWAY_STICKY_CHANGE pll.pll_run_away_sticky [4:4] read-write ENABLE_VCCD s40usb2afe_reg_2p5.ok_v25_vccd is detected [5:5] read-write ENABLE_HS_VCCD s40usb2afe_reg_1p1.ok_vhs_vccd is detected [6:6] read-write BISTDONE Bist is done if BIST_CONTINOUS_EN is 0. Status of BIST is BISTOK STATUS register [7:7] read-write ERRORFLOW Elasticity buffer overflow error indicator [8:8] read-write STRESS_OUT Over-voltage stress event detected on the dp or dn pins [9:9] read-write CAL_DONE Calibration Complete [10:10] read-write INTR0_SET INTR0 Set 0x48 32 read-write 0x0 0x7FF PLL_LOCK Write with '1' to set corresponding bit in interrupt request register. [0:0] read-write PLL_LOSS Write with '1' to set corresponding bit in interrupt request register. [1:1] read-write TEST_PLL_LOCK Write with '1' to set corresponding bit in interrupt request register. [2:2] read-write PLL_RUN_AWAY_STICKY_CHANGE Write with '1' to set corresponding bit in interrupt request register. [3:3] read-write TEST_PLL_RUN_AWAY_STICKY_CHANGE Write with '1' to set corresponding bit in interrupt request register. [4:4] read-write ENABLE_VCCD Write with '1' to set corresponding bit in interrupt request register. [5:5] read-write ENABLE_HS_VCCD Write with '1' to set corresponding bit in interrupt request register. [6:6] read-write BISTDONE Write with '1' to set corresponding bit in interrupt request register. [7:7] read-write ERRORFLOW Write with '1' to set corresponding bit in interrupt request register. [8:8] read-write STRESS_OUT Write with '1' to set corresponding bit in interrupt request register. [9:9] read-write CAL_DONE Write with '1' to set corresponding bit in interrupt request register. [10:10] read-write INTR0_MASK INTR0 Mask 0x4C 32 read-write 0x0 0x7FF PLL_LOCK_MASK Mask bit for corresponding bit in interrupt request register. [0:0] read-write PLL_LOSS_MASK Mask bit for corresponding bit in interrupt request register. [1:1] read-write TEST_PLL_LOCK_MASK Mask bit for corresponding bit in interrupt request register. [2:2] read-write PLL_RUN_AWAY_STICKY_CHANGE_MASK Mask bit for corresponding bit in interrupt request register. [3:3] read-write TEST_PLL_RUN_AWAY_STICKY_CHANGE_MASK Mask bit for corresponding bit in interrupt request register. [4:4] read-write ENABLE_VCCD_MASK Mask bit for corresponding bit in interrupt request register. [5:5] read-write ENABLE_HS_VCCD_MASK Mask bit for corresponding bit in interrupt request register. [6:6] read-write BISTDONE_MASK Mask bit for corresponding bit in interrupt request register. [7:7] read-write ERRORFLOW_MASK Mask bit for corresponding bit in interrupt request register. [8:8] read-write STRESS_OUT_MASK Mask bit for corresponding bit in interrupt request register. [9:9] read-write CAL_DONE_MASK Mask bit for corresponding bit in interrupt request register. [10:10] read-write INTR0_MASKED INTR0 Masked 0x50 32 read-only 0x0 0x7FF PLL_LOCK_MASKED Logical and of corresponding request and mask bits. [0:0] read-only PLL_LOSS_MASKED Logical and of corresponding request and mask bits. [1:1] read-only TEST_PLL_LOCK_MASKED Logical and of corresponding request and mask bits. [2:2] read-only PLL_RUN_AWAY_STICKY_CHANGE_MASKED Logical and of corresponding request and mask bits. [3:3] read-only TEST_PLL_RUN_AWAY_STICKY_CHANGE_MASKED Logical and of corresponding request and mask bits. [4:4] read-only ENABLE_VCCD_MASKED Logical and of corresponding request and mask bits. [5:5] read-only ENABLE_HS_VCCD_MASKED Logical and of corresponding request and mask bits. [6:6] read-only BISTDONE_MASKED Logical and of corresponding request and mask bits. [7:7] read-only ERRORFLOW_MASKED Logical and of corresponding request and mask bits. [8:8] read-only STRESS_OUT_MASKED Logical and of corresponding request and mask bits. [9:9] read-only CAL_DONE_MASKED Logical and of corresponding request and mask bits. [10:10] read-only SPARE Spare 0x54 32 read-write 0xFF000000 0xFFFFFFFF DFT Spare [11:0] read-only SPARE0 Spare with default 0 [23:12] read-write SPARE1 Spare with default 1 [31:24] read-write AFE_CONTROL_3 AFE Control register #3 0x58 32 read-write 0x0 0xFFFFFFFF CONTROL_CONN_RPD 1: The conn_rpd_dp/conn_rpd_dn input ports of AFE block will be driven by the CONN_RPD_DP_VALUE/CONN_RPD_DN_VALUE 0: The conn_rpd_dp/conn_rpd_dn will be driven by logic [0:0] read-write CONN_RPD_DP_VALUE When CONTROL_CONN_RPT is set, conn_rpd_dp input port of AFE block block is driven by this register, otherwise it is driven by logic. [1:1] read-write CONN_RPD_DN_VALUE When CONTROL_CONN_RPT is set, conn_rpd_dn input port of AFE block block is driven by this register, otherwise it is driven by logic. [2:2] read-write CONTROL_CONN_RPU 1: The conn_rpu1/conn_rpu2 input ports of AFE block will be driven by the CONN_RPU1_VALUE/CONN_RPU2_VALUE 0: The conn_rpu1/conn_rpu2 will be driven by logic [3:3] read-write CONN_RPU1_VALUE When CONTROL_CONN_RPU is set, conn_rpu1 input port of AFE block block is driven by this register, otherwise it is driven by logic. [4:4] read-write CONN_RPU2_VALUE When CONTROL_CONN_RPU is set, conn_rpu2 input port of AFE block block is driven by this register, otherwise it is driven by logic. [5:5] read-write CONTROL_HS_DED 1: The hs_ded_en/hs_ded_reset/hs_ded_start input ports of AFE block will be driven by the HS_DED_EN_VALUE/HS_DED_RESET_VALUE/HS_DED_START_VALUE 0: The hs_ded_en/hs_ded_reset/hs_ded_start will be driven by logic [6:6] read-write HS_DED_EN_VALUE When CONTROL_HS_DED is set, hs_ded_en input ports of AFE block block is driven by this register, otherwise it is driven by logic. [7:7] read-write HS_DED_RESET_VALUE When CONTROL_HS_DED is set, hs_ded_reset input port of AFE block block is driven by this register, otherwise it is driven by logic. [8:8] read-write HS_DED_START_VALUE When CONTROL_HS_DED is set, chs_ded_start input port of AFE block block is driven by this register, otherwise it is driven by logic. [9:9] read-write CONTROL_IREF_EN 1: The iref_en input ports of AFE block will be driven by the IREF_EN_VALUE 0: The iref_en will be driven by logic [10:10] read-write IREF_EN_VALUE When CONTROL_IREF_EN is set, iref_en input ports of AFE block block is driven by this register, otherwise it is driven by logic. [11:11] read-write CONTROL_HS_RX_EN 1: The hs_rx_en input ports of AFE block will be driven by the HS_RX_EN_VALUE 0: The hs_rx_en will be driven by logic [12:12] read-write HS_RX_EN_VALUE When CONTROL_HS_RX_EN is set, hs_rx_en input ports of AFE block block is driven by this register, otherwise it is driven by logic. [13:13] read-write CONTROL_HS_RX_BUF_ON 1: The hs_rx_buf_on input ports of AFE block will be driven by the HS_RX_BUF_ON_VALUE 0: The hs_rx_buf_on will be driven by logic [14:14] read-write HS_RX_BUF_ON_VALUE When CONTROL_HS_RX_BUF_ON is set, hs_rx_buf_on input ports of AFE block block is driven by this register, otherwise it is driven by logic. [15:15] read-write CONTROL_HS_TED_EN 1: The hs_ted_en input ports of AFE block will be driven by the HS_TED_EN_VALUE 0: The hs_ted_en will be driven by logic [16:16] read-write HS_TED_EN_VALUE When CONTROL_HS_TED_EN is set, hs_ted_en input ports of AFE block block is driven by this register, otherwise it is driven by logic. [17:17] read-write CONTROL_HS_TX_EN_SLOW 1: The hs_tx_en_slow input ports of AFE block will be driven by the HS_TX_EN_SLOW_VALUE 0: The hs_tx_en_slow will be driven by logic [18:18] read-write HS_TX_EN_SLOW_VALUE When CONTROL_HS_TX_EN_SLOW is set, hs_tx_en_slow input ports of AFE block block is driven by this register, otherwise it is driven by logic. [19:19] read-write CONTROL_RPU_SEL 1: The rpu_sel input ports of AFE block will be driven by the RPU_SEL_VALUE 0: The rpu_sel will be driven by logic [20:20] read-write RPU_SEL_VALUE When CONTROL_RPU_SEL is set, rpu_sel input ports of AFE block block is driven by this register, otherwise it is driven by logic. [21:21] read-write CONTROL_SE_RX_EN_DP 1: The se_rx_en_dp input ports of AFE block will be driven by the SE_RX_EN_DP_VALUE 0: The se_rx_en_dp will be driven by logic [22:22] read-write SE_RX_EN_DP_VALUE When CONTROL_SE_RX_EN_DP is set, se_rx_en_dp input ports of AFE block block is driven by this register, otherwise it is driven by logic. [23:23] read-write CONTROL_SE_RX_EN_DN 1: The se_rx_en_dn input ports of AFE block will be driven by the SE_RX_EN_DN_VALUE 0: The se_rx_en_dn will be driven by logic [24:24] read-write SE_RX_EN_DN_VALUE When CONTROL_SE_RX_EN_DN is set, se_rx_en_dn input ports of AFE block block is driven by this register, otherwise it is driven by logic. [25:25] read-write CONTROL_LS_NFS 1: The ls_nfs input ports of AFE block will be driven by the LS_NFS_VALUE 0: The ls_nfs will be driven by logic [26:26] read-write LS_NFS_VALUE When CONTROL_LS_NFS is set, ls_nfs input ports of AFE block block is driven by this register, otherwise it is driven by logic. [27:27] read-write CONTROL_LSFS_DIFF_RX_EN 1: The lsfs_diff_rx_en input ports of AFE block will be driven by the LSFS_DIFF_RX_EN_VALUE 0: The lsfs_diff_rx_en will be driven by logic [28:28] read-write LSFS_DIFF_RX_EN_VALUE When CONTROL_LSFS_DIFF_RX_EN is set, lsfs_diff_rx_en input ports of AFE block block is driven by this register, otherwise it is driven by logic. [29:29] read-write CONTROL_LFS_TX_EN 1: The lfs_tx_en input ports of AFE block will be driven by the LFS_TX_EN_VALUE 0: The lfs_tx_en will be driven by logic [30:30] read-write LFS_TX_EN_VALUE When CONTROL_LFS_TX_EN is set, lfs_tx_en input ports of AFE block block is driven by this register, otherwise it is driven by logic. [31:31] read-write AFE_CONTROL_4 AFE Control register #4 0x5C 32 read-write 0x0 0xFFFFFFF CONTROL_LFS_TX_IN 1: The lfs_tx_in input ports of AFE block will be driven by the LFS_TX_IN_VALUE 0: The lfs_tx_in will be driven by logic [0:0] read-write LFS_TX_IN_VALUE When CONTROL_LFS_TX_IN is set, lfs_tx_in input ports of AFE block block is driven by this register, otherwise it is driven by logic. [1:1] read-write CONTROL_LFS_TX_ON 1: The lfs_tx_on input ports of AFE block will be driven by the LFS_TX_ON_VALUE 0: The lfs_tx_on will be driven by logic [2:2] read-write LFS_TX_ON_VALUE When CONTROL_LFS_TX_ON is set, lfs_tx_on input ports of AFE block block is driven by this register, otherwise it is driven by logic. [3:3] read-write CONTROL_ENASE0 1: The enase0 input ports of AFE block will be driven by the ENASE0_VALUE 0: The enase0 will be driven by logic [4:4] read-write ENASE0_VALUE When CONTROL_ENASE0 is set, enase0 input ports of AFE block block is driven by this register, otherwise it is driven by logic. [5:5] read-write CONTROL_ENASE1 1: The enase1 input ports of AFE block will be driven by the ENASE1_VALUE 0: The enase0 will be driven by logic [6:6] read-write ENASE1_VALUE When CONTROL_ENASE1 is set, enase1 input ports of AFE block block is driven by this register, otherwise it is driven by logic. [7:7] read-write CONTROL_CAL 1: The cal/oncal/cal_f1/cal_f2 input ports of AFE block will be driven by the CAL_VALUE, ONCAL_VALUE, CAL_F1_VALUE, CAL_F2_VALUE 0: The cal/oncal/cal_f1/cal_f2 will be driven by logic [8:8] read-write CAL_VALUE When CONTROL_CAL is set, cal input ports of AFE block block is driven by this register, otherwise it is driven by logic. [13:9] read-write ONCAL_VALUE When CONTROL_CAL is set, cal input ports of AFE block block is driven by this register, otherwise it is driven by logic. [14:14] read-write CAL_F1_VALUE When CONTROL_CAL is set, cal input ports of AFE block block is driven by this register, otherwise it is driven by logic. [15:15] read-write CAL_F2_VALUE When CONTROL_CAL is set, cal input ports of AFE block block is driven by this register, otherwise it is driven by logic. [16:16] read-write CONTROL_SE_TX_IN_EDN 1: The se_tx_in_edn input ports of AFE block will be driven by the SE_TX_IN_EDN_VALUE 0: The se_tx_in_edn will be driven by logic [17:17] read-write SE_TX_IN_EDN_VALUE When CONTROL_SE_TX_IN_EDN is set, se_tx_in_edn input ports of AFE block block is driven by this register, otherwise it is driven by logic. [18:18] read-write CONTROL_SE_TX_EN_EDN 1: The se_tx_en_edn input ports of AFE block will be driven by the SE_TX_EN_EDN_VALUE 0: The se_tx_en_edn will be driven by logic [19:19] read-write SE_TX_EN_EDN_VALUE When CONTROL_SE_TX_EN_EDN is set, se_tx_en_edn input ports of AFE block block is driven by this register, otherwise it is driven by logic. [20:20] read-write CONTROL_HS_PREE_EN 1: The hs_pree_en input ports of AFE block will be driven by the HS_PREE_EN_VALUE 0: The hs_pree_en will be driven by logic [21:21] read-write HS_PREE_EN_VALUE When CONTROL_HS_PREE_EN is set, hs_pree_en input ports of AFE block block is driven by this register, otherwise it is driven by logic. [22:22] read-write CONTROL_HS_TERM_EN 1: hs_term_en input ports of USB2 AFE will be driven by HS_TERM_EN_VALUE 0:Controlled by logic [23:23] read-write HS_TERM_EN_VALUE When CONTROL.HS_TERM_EN is set, hs_term_en input of USB2 AFE is driven by this register [24:24] read-write CONTROL_HS_TX_EN 1: HS Tranmit control signals are generated in dlaunch based on HS_TX_EN_VALUE and HS_TX_EN_FAST_VALUE 0:Controlled by logic [25:25] read-write HS_TX_EN_VALUE When CONTROL.HS_TX_EN is set, the AFE hs_tx_en_n signal is controlled from this filed through dlaunch [26:26] read-write HS_TX_EN_FAST_VALUE 1: *dum* ports of the AFE are controlled in dlaunch through this field 0:Controlled by logic [27:27] read-write UTMI_CONTROL_2 UTMI Configurtation Registers 0x60 32 read-write 0x809C21 0xFFFFFF DED_RESET_ASSERT_X6_BIT To detect HS disconnect 2 signals reset and start are generated during the 40-bit of the EOP The 40-bit EOP counter is designed as two counter of 3-bits each to meet 480MHZ timing A 3-bit counter counts every 6 bits and another every 6-bit word (x6) The counters cycle through values as follows 0,4,6,7,3,1 - starting with 0 This field specifies the word position at which RESET is asserted - currently set to 32nd bit of EOP [2:0] read-write DED_RESET_ASSERT_BIT This filed specifies the bit position at which RESET is asserted - current set to 32nd bit of EOP [5:3] read-write DED_RESET_DEASSERT_X6_BIT This field specifies the word position at which RESET is deasserted - currently set to 39th bit of EOP [8:6] read-write DED_RESET_DEASSERT_BIT This filed specifies the bit position at which RESET is deasserted - current set to 39th bit of EOP [11:9] read-write DED_START_ASSERT_X6_BIT This filed specifies the bit position at which START is asserted - current set to 36th bit of EOP [14:12] read-write DED_START_ASSERT_BIT This filed specifies the bit position at which START is asserted - current set to 36th bit of EOP [17:15] read-write DED_START_DEASSERT_X6_BIT This field specifies the word position at which START is deasserted - currently set to 38th bit of EOP [20:18] read-write DED_START_DEASSERT_BIT This filed specifies the bit position at which START is deasserted - current set to 38th bit of EOP [23:21] read-write PLL_TRIMS Trim register for the PLL 0xF0 32 read-write 0x92A4A 0xFFFFF RUN_AWAY PLL Run away detector level trim [1:0] read-write CP_CUR PLL Trim option for analog charge pump [3:2] read-write LDO_VCO PLL LDO VCO voltage trim [6:4] read-write LDO_CORE PLL Spare bits - unused [9:7] read-write TEST_RUN_AWAY TEST PLL Run away detector level trim [11:10] read-write TEST_CP_CUR TEST PLL Trim option for analog charge pump [13:12] read-write TEST_LDO_VCO TEST PLL LDO VCO voltage trim [16:14] read-write TEST_LDO_CORE TEST PLL Spare bits - unused [19:17] read-write AFE_TRIMS Trim register for the AFE 0xF4 32 read-write 0x0 0x7FFFFFFF TRIM_VREF Vrefgen - Trim output reference voltage level [3:0] read-write TRIM_IREF Irefgen - Trim output reference current level [7:4] read-write TRIM_VREG_2P5 2p5 Regulator output votlage trim control [11:8] read-write TRIM_VREG_1P1 1p1 Regulator output votlage trim control [15:12] read-write TRIM_REG_SW_1P2 1p2 Regulator output votlage trim control [19:16] read-write TRIM_AFE_HS_IREF High Speed Transmit Current Source Trim [22:20] read-write TRIM_VREF_600M_0 Voltage Select for vref_600m<0> [26:23] read-write TRIM_VREF_600M_1 Voltage Select for vref_600m<1> [30:27] read-write MAIN_REG HBWSS Main Registers 0x40440000 0 4096 registers CTRL Main Control Register 0x0 32 read-write 0x4 0x80000007 DMA_SRC_SEL AXI clock select 00: 480Mhz from USB2 divided to 320Mhz 01: Not used 10: 312.5Mhz from USB32 11: 100Mhz from System Interface [1:0] read-write DMA_DIV2_ENA Enables div2 of DMA src clock - active high - default enabled [2:2] read-write IP_ENABLED 0: IP is disabled, Resets the IP, this reset is an async reset. 1: IP is enabled. Note that when the IP is disabled, all the interrupt sources are also disabled. All the clocks that their source is clk_hf will be turned off when IP is disabled. [31:31] read-write MTRIM Memory Control Register 0x4 32 read-write 0x0 0x73FF SRAM_RM SRAM trim bus - match mxsramwrap bit order [3:0] read-write SRAM_RME SRAM trim bus enable [4:4] read-write SRAM_WPULSE SRAM trim bus [7:5] read-write SRAM_RA SRAM trim bus [9:8] read-write SRAM_WA SRAM trim bus [14:12] read-write SPCTRL SRAM Power Control Register 0x8 32 read-write 0x960F 0x13FF0F PWR_MODE_MACRO_0 Power Mode Control for SRAM MACROs 0,1,2,3. 0x3 - Enabled, 0x2 - Retained, 0x1 - Reset, 0x0 - Off [1:0] read-write PWR_MODE_MACRO_1 Power Mode Control for SRAM MACROs 4,5,6,7. 0x3 - Enabled, 0x2 - Retained, 0x1 - Reset, 0x0 - Off [3:2] read-write PWRUP_DELAY Power Up Time [17:8] read-write WOUND_BIT When 1 SRAM MACROs 0,1,2,3 are turned off [20:20] read-write TR_CMD Trigger command 0x20 32 read-write 0x0 0xF00000FF TR_SEL Specifies the activated trigger when ACTIVATE is '1'. If the specified trigger is not present, the trigger activation has no effect. [7:0] read-write TRA_MINTENAB Trigger Assist logic Master Interrupt Enable [28:28] read-write TR_EDGE Specifies if the activated trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. The trigger reflects TR_CMD.ACTIVATE. '1': edge sensitive trigger. The trigger is activated for two clk_peri cycles. [29:29] read-write OUT_SEL Specifies whether trigger activation is for a specific input or output trigger of the trigger multiplexer. Activation of a specific input trigger, will result in activation of all output triggers that have the specific input trigger selected through their TR_OUT_CTL.TR_SEL field. Activation of a specific output trigger, will result in activation of the specified TR_SEL output trigger only. '0': TR_SEL selection and trigger activation is for an input trigger to the trigger multiplexer. '1': TR_SEL selection and trigger activation is for an output trigger from the trigger multiplexer. Note: this field is not used for trigger 1-to-1 groups. [30:30] read-write ACTIVATE SW sets this field to '1' to activate (set to '1') a trigger as identified by TR_SEL, TR_EDGE and OUT_SEL. HW sets this field to '0' for edge sensitive triggers AFTER the selected trigger is activated for two clk_peri cycles. Note: when ACTIVATE is '1', SW should not modify the other register fields. SW MUST NOT set ACTIVATE bit to '1' while updating the other register bits simultaneously. At first the SW MUST update the other register bits as needed, and then set ACTIVATE to '1' with a new register write. [31:31] read-write TRA_CISNP CDMA input tr_assist snoop mode 0x24 32 read-write 0x0 0xFFFFFFFF ISNP_BITS Turn on snoop mode per trigger -- used for streaming transfers [31:0] read-write TRA_COSNP CDMA output tr_assist snoop mode 0x28 32 read-write 0x0 0xFFFFFFFF OSNP_BITS Turn on snoop mode per trigger -- used for streaming transfers [31:0] read-write TRA_CI_INTR CDMA input tr_assist Interrupt Status 0x30 32 read-write 0x0 0xFFFFFFFF IINTR_BITS Trigger Assist Interrupt per trigger [31:0] read-write TRA_CI_INTR_SET CDMA input tr_assist Interrupt Set 0x34 32 read-write 0x0 0xFFFFFFFF IINTRS_BITS Trigger Assist Interrupt Set per trigger [31:0] read-write TRA_CI_INTR_MASK CDMA input tr_assist Interrupt Mask 0x38 32 read-write 0x0 0xFFFFFFFF IINTRM_BITS Trigger Assist Interrupt Mask per trigger [31:0] read-write TRA_CI_INTR_MASKED CDMA input tr_assist Interrupt Masked 0x3C 32 read-only 0x0 0xFFFFFFFF IINTRMD_BITS Trigger Assist Interrupt Masked per trigger [31:0] read-only TRA_CO_INTR CDMA output tr_assist Interrupt Status 0x40 32 read-write 0x0 0xFFFFFFFF OINTR_BITS Trigger Assist Interrupt per trigger [31:0] read-write TRA_CO_INTR_SET CDMA output tr_assist Interrupt Set 0x44 32 read-write 0x0 0xFFFFFFFF OINTRS_BITS Trigger Assist Interrupt Set per trigger [31:0] read-write TRA_CO_INTR_MASK CDMA output tr_assist Interrupt Mask 0x48 32 read-write 0x0 0xFFFFFFFF OINTRM_BITS Trigger Assist Interrupt Mask per trigger [31:0] read-write TRA_CO_INTR_MASKED CDMA output tr_assist Interrupt Masked 0x4C 32 read-only 0x0 0xFFFFFFFF OINTRMD_BITS Trigger Assist Interrupt Masked per trigger [31:0] read-only TR_GR Trigger group 0x00000400 96 4 TR_CTL[%s] Trigger control register 0x20 32 read-write 0x0 0x13FF TR_SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. [7:0] read-write TR_INV Specifies if the output trigger is inverted. [8:8] read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. [9:9] read-write DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. [12:12] read-write TR_ASSIST_GR Trigger Assist - for CDMA triggers 0x00000800 32 4 TRA_SCK_DSCR[%s] Trigger Assist current descriptor number register - input 0x0 32 read-write 0x0 0x8000FFFF TR_DSCR_NUMBER Specifies current dscr number FW init to start of dscr chain tr_assist HW updates on dscr fetch [15:0] read-write TR_CONS_PRODN Specifies if trigger is Consumer or Producer [31:31] read-write 32 4 TRA_DSCR_SIZE[%s] Trigger Assist current descriptor size/count/occupied register - input 0x100 32 read-write 0x0 0xFFFFFFFF TR_MARKER FW use [0:0] read-write TR_EOP EOP indicator [1:1] read-write TR_BUFF_ERR Buffer Error [2:2] read-write TR_BUFF_OCCUPIED Buffer Occupied 1 for Cons, Buffer Empty 0 for Prod [3:3] read-write TR_BUFF_SIZE Specifies buffer size Size in terms of groups of 16 bytes Does this buffer size need byte resolution? Godwin verifies NO [15:4] read-write TR_BYTE_COUNT Byte count of current buffer at event time - not updated during transfer [31:16] read-write 32 4 TRA_CMD_STAT[%s] Trigger Assist command and status - input 0x300 32 read-write 0x0 0xCFF00000 TRA_STATE tr_assist internal state [23:20] read-only TRA_SNP_MODE Puts tr_assist logic in snoop mode for this trigger [24:24] read-write TRA_NO1STTR Suppress first trigger event for a transfer [25:25] read-write TRA_IN_OUTN Trigger Registers control - 1 the input trigger - 0 the output trigger [26:26] read-write TRA_IS_PROD 1 for trigger muxed to Prod, 0 for trigger muxed to Cons [27:27] read-write TRA_GO2MAINST Atfer FW intervention, write 1 to this cmd bit to enable tr_assist functions again [30:30] read-write TRA_INIT_TR Write 1 to this cmd bit to init the tr_assist logic for this trigger [31:31] read-write USB32DEV USB32 IP Registers 0x40480000 0 196608 registers 2 196608 USB32DEV[%s] USB32DEV Registers 0x00000000 MAIN USB32 Main Register 0x00000000 CTRL Main Control Register 0x0 32 read-write 0x40 0xE000007F SSDEV_ENABLE Enables the Super Speed device function. [0:0] read-write LOOPBACK_EN TBD: TED [1:1] read-write DISABLE_SRAM Disable all the SRAMS in this IP [2:2] read-write USB2_BUS_RESET 0: There is no USB2 Bus Reset 1: There is a USB2 Bus Reset [3:3] read-write CLK_EN Steps to enable the Clock for USB3.2 function: 1: Program CTRL.IP_ENABLED to 1 2: Program CTRL.CLK_EN to 1 (This will cause the USB3.2 function to use DMA clock) 3: Program CTRL.SSDEV_ENABLE to 1 4: Program CTRL.PCLK_SRC to 1 (This will cause the USB3.2 function to use PHY-PCLK) [4:4] read-write PCLK_SRC Clock source for the USB function: 0: clk_lf_i (typ 32KHz) 1: USB3 PHY 312.5/125MHz (Spread Spectrum Clock) 2: Bus clock (typ 200MHz) 3: clk_lf_i (typ 32KHz) [6:5] read-write SI_MODE This register is used to configure how the Egress packets are sent to host in SuperSpeedPlus. This register is not used in Gen1x1. This is mainly used for handling Simultanous-IN. 0: First-Come/First-Serve: In this mode, packet are sent to host the same order that the ACK were received for the EPs. 1: Weight Round-Robin arbitration: In this mode, the packet are sent to host based on a round-robin function. The number of packets that can be sent for every arbitation grant for each EP is defined in Protocol PROT_EPI_ARB_PKT configuration register. [29:29] read-write CONFIG_LANE Configuration Lane register: 0: Lane0 is the configuration lane 1: Lane1 is the configuration lane [30:30] read-write IP_ENABLED 0: IP is disabled, Resets the IP, this reset is an async reset. 1: IP is enabled. Note that when the IP is disabled, all the interrupt sources are also disabled. All the clocks that their source is clk_hf will be turned off when IP is disabled. [31:31] read-write INTR Main Interrupt Register 0x4 32 read-write 0x0 0x1F LINK SuperSpeedPlus Link Controller Interrupt [0:0] read-write PROT SuperSpeedPlus Protocol Layer Interrupt [1:1] read-write PROT_EP SuperSpeedPlus Device Endpoint Interrupt [2:2] read-write EPM_URUN SuperSpeedPlus Egress EPM Interrupt [3:3] read-write EPM_URUN_TIMEOUT SuperSpeedPlus Egress EPM Interrupt [4:4] read-write INTR_SET Main Interrupt Set Register 0x8 32 read-write 0x0 0x1F LINK Write with '1' to set corresponding bit in interrupt request register. [0:0] read-write PROT Write with '1' to set corresponding bit in interrupt request register. [1:1] read-write PROT_EP Write with '1' to set corresponding bit in interrupt request register. [2:2] read-write EPM_URUN Write with '1' to set corresponding bit in interrupt request register. [3:3] read-write EPM_URUN_TIMEOUT Write with '1' to set corresponding bit in interrupt request register. [4:4] read-write INTR_MASK Main Interrupt Mask Register 0xC 32 read-write 0x0 0x1F LINK_MASK Mask bit for corresponding bit in interrupt request register. [0:0] read-write PROT_MASK Mask bit for corresponding bit in interrupt request register. [1:1] read-write PROT_EP_MASK Mask bit for corresponding bit in interrupt request register. [2:2] read-write EPM_URUN_MASK Mask bit for corresponding bit in interrupt request register. [3:3] read-write EPM_URUN_TIMEOUT_MASK Mask bit for corresponding bit in interrupt request register. [4:4] read-write INTR_MASKED Main Interrupt Masked Register 0x10 32 read-only 0x0 0x1F LINK_MASKED Logical and of corresponding request and mask bits. [0:0] read-only PROT_MASKED Logical and of corresponding request and mask bits. [1:1] read-only PROT_EP_MASKED Logical and of corresponding request and mask bits. [2:2] read-only EPM_URUN_MASKED Logical and of corresponding request and mask bits. [3:3] read-only EPM_URUN_TIMEOUT_MASKED Logical and of corresponding request and mask bits. [4:4] read-only DDFT_MUX DDFT0/1 mux selection Register 0x14 32 read-write 0x0 0xFFFF DDFT0_SEL This register selects the following inputs to be routed to DDFT0. 0: PHY-SS[0] DDFT0 1: PHY-SS[0] DDFT1 2: PHY-SS[1] DDFT0 3: PHY-SS[1] DDFT1 [7:0] read-write DDFT1_SEL This register selects the following inputs to be routed to DDFT1. 0: PHY-SS[0] DDFT0 1: PHY-SS[0] DDFT1 2: PHY-SS[1] DDFT0 3: PHY-SS[1] DDFT1 [15:8] read-write GPIO_DDFT_MUX GPIO DDFT0/1 mux selection Register 0x18 32 read-write 0x0 0xFFFF DDFT0_SEL This register selects the following inputs to be routed to GPIO-DDFT0. 0: PHY-SS[0] DDFT0 1: PHY-SS[0] DDFT1 2: PHY-SS[1] DDFT0 3: PHY-SS[1] DDFT1 [7:0] read-write DDFT1_SEL This register selects the following inputs to be routed to GPIO-DDFT1. 0: PHY-SS[0] DDFT0 1: PHY-SS[0] DDFT1 2: PHY-SS[1] DDFT0 3: PHY-SS[1] DDFT1 [15:8] read-write EPM USB32 Controller End Point Manager Registers 0x00001000 EEPM_CS Egress EPM Retry Buffer Status 0x0 32 read-write 0x30000 0xF3FF0000 URUN_REPAIR_EN This bit will repair the EPM whenever there is under run due to SYSTEM EPM will keep on reading the packet from SYSMEM whenever data is ready from SYSMEM. If an under-run occurs, EPM will raise the UIB_INTR.EPM_URUN interrupt. [16:16] read-write URUN_REPAIR_TIMEOUT_EN If an under run occurs and the URUN_REPAIR_EN is set and this register bit is set, then EPM will start a timmer(16-bit counter). If the repair is not complete after 65535*epm clock, EPM will raise the UIB_INTR.EPM_URUN_TIMEOUT interrupt. [17:17] read-write URUN_T1_EP_NUM The Type1 End Point that the under-run occurred. [21:18] read-only URUN_T2_EP_NUM The Type2 End Point that the under-run occurred. [25:22] read-only EG_EPNUM Active Endpoint Number [31:28] read-only IEPM_CS Ingress EPM Control and Status 0x4 32 read-write 0x0 0x3FFF0FFF READ_PTR Number of bytes in packet. [11:0] read-only WRITE_PTR End of Transfer. Set for short packets. [27:16] read-only EPM_FLUSH This will flush both the Egress and Ingress EPM. [28:28] read-write EPM_MUX_RESET This will reset the EPM Mux. [29:29] read-write IEPM_MULT Ingress EPM MULT function Control 0x8 32 read-write 0x8000 0x3FFFFFF MULT_EN Mult Enable for EP1-15. [14:0] read-write MULT_THRSHOLD This field is used to when evaluate the mult signal from ingress adapter. If number of packet space available in the buffer goes down by this field, then mult signal from adapter will be evaluated and if it is set the original buffer space(number of packets) is added to NUM_PACKETS in the IEPM_ENDPOINT register. [25:15] read-write 16 4 EEPM_ENDPOINT[%s] Egress EPM per Endpoint Control and Status 0x40 32 read-write 0x400 0xCFFFFFFF PACKET_SIZE Maximum packet size for this end-point. Typically this value is 1024, 512, 64, 1023 (last 2 for USB2 only). [10:0] read-write EEPM_BYTE_COUNT Number of bytes in the current buffer. [26:11] read-only ZLP ZLP present in the current buffer [27:27] read-only EEPM_EP_READY The EPM condition used by USB block. [30:30] read-only SOCKET_FLUSH This bit will flush the corresponding Socket. [31:31] read-write 16 4 IEPM_ENDPOINT[%s] Ingress EPM Per Endpoint Control and Status 0x80 32 read-write 0x400 0xFF7FFFFF PACKET_SIZE Maximum packet size for this end-point. Typically this value is 1024, 512, 64, 1023 (last 2 for USB2 only). [10:0] read-write NUM_IN_PACKETS Number of packets that are guaranteed to fit in the remaining buffer space of the current and next buffers. If the computed number of packets available is larger than 16, this number will be assumed to be 16 in the protocol block. [21:11] read-only EP_READY The EPM condition used by USB block. [22:22] read-only ODD_MAX_NUM_PKTS Number of odd byte packets that can fit in the DMA buffer. Only valid if ODD_MAX_PKT_SIZE_EN is set. [28:24] read-write ODD_MAX_PKT_SIZE_EN If this bit is enabled, then at the time of calculation of number of packets space in current DMA buffer, OddMaxNumPkts will over-ride the hardware calculation. [29:29] read-write EOT_EOP Configure end-of-packet signalling to DMA adapter. 0: Send EOP at the end of a full packet and EOT for short/zlp packets 1: Send EOT at the end of every packet Setting this bit to 1 is useful for variable size packet endpoints only. [30:30] read-write SOCKET_FLUSH This bit will flush the corresponding Socket. [31:31] read-write IEPM_FIFO Ingress EPM FIFO Entry 0xC0 32 read-only 0x0 0x1FFFF BYTES Number of bytes in the packet. [10:0] read-only EOT End of Transfer. Set for by the protocol layer short and zero length packets; forwarded to DMA Adapter. [11:11] read-only IN_EPNUM Endpoint number for this packet [15:12] read-only EP_VALID Entry is valid [16:16] read-only 16 4 EEPM_VALID[%s] Egress EPM Retry Buffer Valid packet 0xC4 32 read-only 0x0 0xFFFFFFFF TYPE1_VALID_PACKETS For Type1 End-Points. Bit vector indicating which of the 16 retry buffer contain a valid packet. In SuperSpeed mode, this buffer functions as a circular buffer trailing packets that can be retried behind the WRITE_PTR. These bits are cleared when the Protocol Layer 'activates' an End Point (as opposed to 'reactivating' it). In SuperSpeed mode all bits are cleared at once. [15:0] read-only TYPE2_VALID_PACKETS For Type2 End-Points. Bit vector indicating which of the 16 retry buffer contain a valid packet. In SuperSpeed mode, this buffer functions as a circular buffer trailing packets that can be retried behind the WRITE_PTR. These bits are cleared when the Protocol Layer 'activates' an End Point (as opposed to 'reactivating' it). In SuperSpeed mode all bits are cleared at once. [31:16] read-only 16 4 EEPM_RETRY_OFFSET[%s] Egress EPM Retry Buffer EndPoint offset 0x104 32 read-write 0x0 0x3FFF START_OFFSET The Offset is used for Write/Read Address of the 64K Retry-Memory for each End Point. A 64k memory allows retry for 64 packet with size of 1k. The 64k is shared between all the 16 EndPoints. This register is used to indicate where the stating address The offset has to be N*256, (0<=N<63 ). Note: 4-1K single port sram of 128-bit wide is used to create the 64k memory. Example for calculating the start_offset in decimal: Assume the folloiwng available EndPoint and their MaxBurst size: EP1: EP1-MaxBurst=2 EP2: EP2-MaxBurst=5 EP3: EP3-MaxBurst=8 EP4: EP4-MaxBurst=16 Assume the following structure for retry buffer, where EP2 is at the bottom, then EP1, EP4,EP6: EP2: EP2-Start_Offset= 0 EP1: EP1-Start_Offset= EP2-Start_Offset+EP2-MaxBurst*256 = 0+256*5 =1280 EP4: EP4-Start_offset = EP1-Start_Offset+EP1-MaxBurst*256 = 1280+256*2 =1792 EP6: EP6-Start_offset = EP4-Start_Offset+EP4-MaxBurst*256 = 1792+256*16= 5888 [13:0] read-write LNK USB32 SuperSpeedPlus Device Controller Link Layer Registers 0x00002000 LNK_CONF Link Configuration Register 0x0 32 read-write 0xC0005040 0xC000F7C3 TX_ARBITRATION Link Arbitration Scheme 0=Link Commands wins 1=HP wins 2=Round Robin [1:0] read-write LCW_IGNORE_RSVD N/A [6:6] read-write DEBUG_FEATURE_ENABLE Enable LNK State Debug Override [7:7] read-write FORCE_POWER_PRESENT Force PowerPresent from PHY On [8:8] read-write LDN_DETECTION Enable host LDN detection (see USB ECN#001) [9:9] read-write CREDIT_ADV_HOLDOFF Hold-off Credit Advertisement until Sequence Number Advertisement Received [10:10] read-write EPM_FIRST_DELAY Delay sending of first Header in a egress burst in PCLK cycles (125MHz). This is to give the DMA network time to warmup the data pipeline. [15:12] read-write RATE_CONFIG Initial rate configuration 2'b00: Gen1x1 2'b01: Gen1x2 2'b10: Gen2x1 3'b11: Gen2x2 [31:30] read-write LNK_INTR Link Interrupts 0x4 32 read-write 0x0 0x7FFFF LTSSM_STATE_CHG LTSSM State Change Interrupt [0:0] read-write LGOOD LGOOD Received Interrupt [1:1] read-write LRTY LRTY Received Interrupt [2:2] read-write LBAD LBAD Received Interrupt [3:3] read-write LCRD LCRD Recevied Interrupt [4:4] read-write LGO_U1 LGO_U1 Received Interrupt [5:5] read-write LGO_U2 LGO_U2 Received Interrupt [6:6] read-write LGO_U3 LGO_U3 Received Interrupt [7:7] read-write LAU LAU Received Interrupt [8:8] read-write LXU LXU Received Interrupt [9:9] read-write LPMA LPMA Received Interrupt [10:10] read-write BAD_LCW Illegal LCW received (see LNK_CONTROL_WORD for details) [11:11] read-write LINK_ERROR Link Error Count Threshold Reached [12:12] read-write PHY_ERROR PHY Error Count Threshold Reached [13:13] read-write U2_INACTIVITY_TIMEOUT U2 Inactivity Timeout Interrupt [14:14] read-write LTSSM_CONNECT LTSSM Transition to Polling - indicating successful SuperSpeed far-end receiver termination detection [15:15] read-write LTSSM_DISCONNECT LTSSM Transitions to SS.Disabled [16:16] read-write LTSSM_RESET LTSSM Reset Received (Hot or Warm) [17:17] read-write DATA_RATE_CHANGE Data Rate Changed [18:18] read-write LNK_INTR_SET Link Interrupts Set 0x8 32 read-write 0x0 0x7FFFF LTSSM_STATE_CHG Write with '1' to set corresponding bit in interrupt request register. [0:0] read-write LGOOD Write with '1' to set corresponding bit in interrupt request register. [1:1] read-write LRTY Write with '1' to set corresponding bit in interrupt request register. [2:2] read-write LBAD Write with '1' to set corresponding bit in interrupt request register. [3:3] read-write LCRD Write with '1' to set corresponding bit in interrupt request register. [4:4] read-write LGO_U1 Write with '1' to set corresponding bit in interrupt request register. [5:5] read-write LGO_U2 Write with '1' to set corresponding bit in interrupt request register. [6:6] read-write LGO_U3 Write with '1' to set corresponding bit in interrupt request register. [7:7] read-write LAU Write with '1' to set corresponding bit in interrupt request register. [8:8] read-write LXU Write with '1' to set corresponding bit in interrupt request register. [9:9] read-write LPMA Write with '1' to set corresponding bit in interrupt request register. [10:10] read-write BAD_LCW Write with '1' to set corresponding bit in interrupt request register. [11:11] read-write LINK_ERROR Write with '1' to set corresponding bit in interrupt request register. [12:12] read-write PHY_ERROR Write with '1' to set corresponding bit in interrupt request register. [13:13] read-write U2_INACTIVITY_TIMEOUT Write with '1' to set corresponding bit in interrupt request register. [14:14] read-write LTSSM_CONNECT Write with '1' to set corresponding bit in interrupt request register. [15:15] read-write LTSSM_DISCONNECT Write with '1' to set corresponding bit in interrupt request register. [16:16] read-write LTSSM_RESET Write with '1' to set corresponding bit in interrupt request register. [17:17] read-write DATA_RATE_CHANGE Write with '1' to set corresponding bit in interrupt request register. [18:18] read-write LNK_INTR_MASK LINK Interrupts Mask 0xC 32 read-write 0x0 0x7FFFF LTSSM_STATE_CHG_MASK Mask bit for corresponding bit in interrupt request register. [0:0] read-write LGOOD_MASK Mask bit for corresponding bit in interrupt request register. [1:1] read-write LRTY_MASK Mask bit for corresponding bit in interrupt request register. [2:2] read-write LBAD_MASK Mask bit for corresponding bit in interrupt request register. [3:3] read-write LCRD_MASK Mask bit for corresponding bit in interrupt request register. [4:4] read-write LGO_U1_MASK Mask bit for corresponding bit in interrupt request register. [5:5] read-write LGO_U2_MASK Mask bit for corresponding bit in interrupt request register. [6:6] read-write LGO_U3_MASK Mask bit for corresponding bit in interrupt request register. [7:7] read-write LAU_MASK Mask bit for corresponding bit in interrupt request register. [8:8] read-write LXU_MASK Mask bit for corresponding bit in interrupt request register. [9:9] read-write LPMA_MASK Mask bit for corresponding bit in interrupt request register. [10:10] read-write BAD_LCW_MASK Mask bit for corresponding bit in interrupt request register. [11:11] read-write LINK_ERROR_MASK Mask bit for corresponding bit in interrupt request register. [12:12] read-write PHY_ERROR_MASK Mask bit for corresponding bit in interrupt request register. [13:13] read-write U2_INACTIVITY_TIMEOUT_MASK Mask bit for corresponding bit in interrupt request register. [14:14] read-write LTSSM_CONNECT_MASK Mask bit for corresponding bit in interrupt request register. [15:15] read-write LTSSM_DISCONNECT_MASK Mask bit for corresponding bit in interrupt request register. [16:16] read-write LTSSM_RESET_MASK Mask bit for corresponding bit in interrupt request register. [17:17] read-write DATA_RATE_CHANGE Mask bit for corresponding bit in interrupt request register. [18:18] read-write LNK_INTR_MASKED Protocol Interrupts Masked 0x10 32 read-only 0x0 0x7FFFF LTSSM_STATE_CHG_MASKED Logical and of corresponding request and mask bits. [0:0] read-only LGOOD_MASKED Logical and of corresponding request and mask bits. [1:1] read-only LRTY_MASKED Logical and of corresponding request and mask bits. [2:2] read-only LBAD_MASKED Logical and of corresponding request and mask bits. [3:3] read-only LCRD_MASKED Logical and of corresponding request and mask bits. [4:4] read-only LGO_U1_MASKED Logical and of corresponding request and mask bits. [5:5] read-only LGO_U2_MASKED Logical and of corresponding request and mask bits. [6:6] read-only LGO_U3_MASKED Logical and of corresponding request and mask bits. [7:7] read-only LAU_MASKED Logical and of corresponding request and mask bits. [8:8] read-only LXU_MASKED Logical and of corresponding request and mask bits. [9:9] read-only LPMA_MASKED Logical and of corresponding request and mask bits. [10:10] read-only BAD_LCW_MASKED Logical and of corresponding request and mask bits. [11:11] read-only LINK_ERROR_MASKED Logical and of corresponding request and mask bits. [12:12] read-only PHY_ERROR_MASKED Logical and of corresponding request and mask bits. [13:13] read-only U2_INACTIVITY_TIMEOUT_MASKED Logical and of corresponding request and mask bits. [14:14] read-only LTSSM_CONNECT_MASKED Logical and of corresponding request and mask bits. [15:15] read-only LTSSM_DISCONNECT_MASKED Logical and of corresponding request and mask bits. [16:16] read-only LTSSM_RESET_MASKED Logical and of corresponding request and mask bits. [17:17] read-only DATA_RATE_CHANGE Logical and of corresponding request and mask bits. [18:18] read-only LNK_ERROR_CONF Link Error Counter Configuration 0x14 32 read-write 0x7FFF 0x7FFF HP_TIMEOUT_EN PENDING_HP_TIMER Timeout Count Enable Header Packet acknowledgement has not been received by PENDING_HP_TIMEOUT. [USB 3.0: 7.2.4.1.10, p 7-21] [0:0] read-write RX_SEQ_NUM_ERR_EN Rx Header Sequence Number Error Count Enable Received Rx Header Sequence Number does not match what is expected. [USB 3.0: 7.3.3.3, p 7-28] [1:1] read-write RX_HP_FAIL_EN Receive Header Packet Fail Count Enable Link Layer Block has failed to receive a Header Packet for three consecutive times. Failures are CRC errors or spurious K-symbols. [USB 3.0: 7.3.3.2, p 7-28] [2:2] read-write MISSING_LGOOD_EN Missing LGOOD_n Detection Count Enable LGOOD_n Sequence Number does not match what is expected. [USB 3.0: 7.3.4, p 7-29] [3:3] read-write MISSING_LCRD_EN Missing LCRD_x Detection Count Enable LCRD_x Sequence does not match what is expected. [USB 3.0: 7.3.4, p 7-29] [4:4] read-write CREDIT_HP_TIMEOUT_EN CREDIT_HP_TIMER Timeout Count Enable Remote Rx Header Buffer Credit has not been received by CREDIT_HP_TIMEOUT. [USB 3.0: 7.2.4.1.10, p 7-21...7-22] [5:5] read-write PM_LC_TIMEOUT_EN PM_LC_TIMER Timeout Count Enable This indicates that an LGO_Ux, LAU, or LXU Link Command has been missed. [USB 3.0: 7.3.4, p 7-29] [6:6] read-write TX_SEQ_NUM_ERR_EN ACK Tx Header Sequence Number Error Count Enable Received LGOOD_n does not match ACK Tx Header Sequence Number. [USB 3.0: 7.3.5, p 7-30] [7:7] read-write HDR_ADV_TIMEOUT_EN Header Sequence Number Advertisement PENDING_HP_TIMER Timeout Count Enable PENDING_HP_TIMER timeout before receipt of Header Sequence Number LGOOD_n Link Command [USB 3.0: 7.3.6, p 7-30] [8:8] read-write HDR_ADV_HP_EN Header Sequence Number Advertisement HP Received Error Count Enable Header Packet received during Header Sequence Number Advertisement [USB 3.0: 7.3.6, p 7-30] [9:9] read-write HDR_ADV_LCRD_EN Header Sequence Number Advertisement LCRD_x Received Error Count Enable LCRD_x Link Command received during Header Sequence Number Advertisement [USB 3.0: 7.3.6, p 7-30] [10:10] read-write HDR_ADV_LGO_EN Header Sequence Number Advertisement LGO_Ux Received Error Count Enable LGO_Ux Link Command received during Header Sequence Number Advertisement [USB 3.0: 7.3.6, p 7-30] [11:11] read-write CREDIT_ADV_TIMEOUT_EN Rx Header Buffer Credit Advertisement CREDIT_HP_TIMER Timeout Count Enable CREDIT_HP_TIMER timeout before receipt of LCRD_x Link Command during Rx Header Buffer Credit Advertisement [USB 3.0: 7.3.7, p 7-30...7-31] [12:12] read-write CREDIT_ADV_HP_EN Rx Header Buffer Credit Advertisement HP Received Error Count Enable Header Packet received during Rx Header Buffer Credit Advertisement. [USB 3.0: 7.3.7, p 7-30...7-31] [13:13] read-write CREDIT_ADV_LGO_EN Rx Header Buffer Credit Advertisement LGO_Ux Received Error Count Enable LGO_Ux Link Command received during Rx Header Buffer Credit Advertisement. [USB 3.0: 7.3.7, p 7-30...7-31] [14:14] read-write LNK_ERROR_STATUS Link Error Status Register 0x18 32 read-write 0x0 0x7FFF HP_TIMEOUT_EV Indicates this error (see LNK_ERROR_CONF for description) occurred since this bit was last cleared by firmware. [0:0] read-write RX_SEQ_NUM_ERR_EV Indicates this error (see LNK_ERROR_CONF for description) occurred since this bit was last cleared by firmware. [1:1] read-write RX_HP_FAIL_EV Indicates this error (see LNK_ERROR_CONF for description) occurred since this bit was last cleared by firmware. [2:2] read-write MISSING_LGOOD_EV Indicates this error (see LNK_ERROR_CONF for description) occurred since this bit was last cleared by firmware. [3:3] read-write MISSING_LCRD_EV Indicates this error (see LNK_ERROR_CONF for description) occurred since this bit was last cleared by firmware. [4:4] read-write CREDIT_HP_TIMEOUT_EV Indicates this error (see LNK_ERROR_CONF for description) occurred since this bit was last cleared by firmware. [5:5] read-write PM_LC_TIMEOUT_EV Indicates this error (see LNK_ERROR_CONF for description) occurred since this bit was last cleared by firmware. [6:6] read-write TX_SEQ_NUM_ERR_EV Indicates this error (see LNK_ERROR_CONF for description) occurred since this bit was last cleared by firmware. [7:7] read-write HDR_ADV_TIMEOUT_EV Indicates this error (see LNK_ERROR_CONF for description) occurred since this bit was last cleared by firmware. [8:8] read-write HDR_ADV_HP_EV Indicates this error (see LNK_ERROR_CONF for description) occurred since this bit was last cleared by firmware. [9:9] read-write HDR_ADV_LCRD_EV Indicates this error (see LNK_ERROR_CONF for description) occurred since this bit was last cleared by firmware. [10:10] read-write HDR_ADV_LGO_EV Indicates this error (see LNK_ERROR_CONF for description) occurred since this bit was last cleared by firmware. [11:11] read-write CREDIT_ADV_TIMEOUT_EV Indicates this error (see LNK_ERROR_CONF for description) occurred since this bit was last cleared by firmware. [12:12] read-write CREDIT_ADV_HP_EV Indicates this error (see LNK_ERROR_CONF for description) occurred since this bit was last cleared by firmware. [13:13] read-write CREDIT_ADV_LGO_EV Indicates this error (see LNK_ERROR_CONF for description) occurred since this bit was last cleared by firmware. [14:14] read-write LNK_ERROR_COUNT Error Counter Register 0x1C 32 read-write 0x0 0xFFFFFFFF LINK_ERROR_COUNT The Link Error Count keeps track of the number of errors for which the Link Layer Block had to transition to the Recovery State before resuming normal operation. Each error class is enablable (default on) to allow for debugging purposes. [15:0] read-write PHY_ERROR_COUNT Count of receive errors from the USB 3.0 PHY. This is for debug purposes. [31:16] read-write LNK_ERROR_COUNT_THRESHOLD Error Count Thresholds 0x20 32 read-write 0x0 0xFFFFFFFF LINK_ERROR_THRESHOLD Link Error Count Threshold for Interrupt Generation [15:0] read-write PHY_ERROR_THRESHOLD PHY Error Count Threshold for Interrupt Generation [31:16] read-write LNK_PHY_CONF USB 3.0 PHY Configuration 0x24 32 read-write 0x202005 0xFFFFFFFF PHY_MODE PHY Operation Mode 01 = USB Super Speed [1:0] read-only ELASTICIY_BUFFER_MODE PHY Elasticity Buffer Operation Mode 0 = half full 1 = empty [2:2] read-write TXDETECTRX_LB_OVR PHY TxDetectRx/Loopback Override [3:3] read-write TXDETECTRX_LB_OVR_VAL PHY TxDetectRx/Loopback Override Value [4:4] read-write TXELECIDLE_OVR PHY TxElecIdle Override [5:5] read-write TXELECIDLE_OVR_VAL PHY TxElecIdle Override Value [6:6] read-write TXCOMPLIANCE_OVR PHY TxCompliance Override [7:7] read-only TXCOMPLIANCE_OVR_VAL PHY TxCompliance Override Value [8:8] read-only TXONESZEROS_OVR PHY TxOnesZeros Override [9:9] read-write TXONESZEROS_OVR_VAL PHY TxOnesZeros Override Value [10:10] read-write RXPOLARITY_OVR PHY RxPolarity Override [11:11] read-write RXPOLARITY_OVR_VAL PHY RxPolarity Override Value [12:12] read-write RXEQ_TRAINING_OVR PHY RxEqTraining Override [13:13] read-write RXEQ_TRAINING_OVR_VAL PHY RxEqTraining Override Value [14:14] read-write PHY_RESET_N_OVR PHY PIPE RESET# Override [15:15] read-write PHY_RESET_N_OVR_VAL PHY PIPE RESET# Override Value [16:16] read-write PHY_POWERDOWN_OVR PHY PowerDown Override [17:17] read-write PHY_POWERDOWN_OVR_VAL PHY PowerDown Override Value [19:18] read-write PHY_RATE_OVR PHY Rate Override [20:20] read-only PHY_RATE_OVR_VAL PHY Rate Override Value [21:21] read-only PHY_TX_DEEMPH_OVR PHY Transmitter De-emphasis Override [22:22] read-write PHY_TX_DEEMPH_OVR_VAL PHY Transmitter De-emphasis Override Value [24:23] read-write PHY_TX_MARGIN PHY Transmitter Voltage Levels [27:25] read-write TXSWING PHY Transmitter Voltage Swing Level 0=full swing 1=low swing [28:28] read-write RX_TERMINATION_OVR PHY Receiver Termination Override [29:29] read-write RX_TERMINATION_OVR_VAL PHY Receiver Termination Override Value 0=removed 1=present [30:30] read-write RX_TERMINATION_ENABLE PHY Receiver Termination Enable [31:31] read-write LNK_PHY_STATUS USB 3.0 PHY Status 0x28 32 read-only 0x0 0x3FF RXVALID PHY Receive Valid (symbol lock and valid data) [0:0] read-only PHY_STATUS PHY Status (operation complete) [1:1] read-only RX_ELEC_IDLE Receiver Detection of an Electrical Idle (LFPS Signalling) [2:2] read-only RXSTATUS PHY Receiver Status and Error Codes 000 Receive Data OK 001 1 SKP Ordered Set added (USB SuperSpeed Mode) 010 1 SKP Ordered Set removed (USB SuperSpeed Mode) 011 Receiver Detected (during Receiver Detection Sequence) 100 8b/10b Decode Error or Receive Disparity Error 101 Elastic Buffer overflow 110 Elastic Buffer underflow 111 Receive Disparity Error [5:3] read-only POWER_PRESENT Presence of VBUS [6:6] read-only DATA_BUS_WIDTH Data Bus Width 00: 32-bit mode [8:7] read-only RXCONNECT Rx Connect/Disconnect - Far-end Receiver Termination Detection Stored result from last Rx.Detect Sequence [9:9] read-only LNK_PHY_ERROR_CONF PHY Error Counter Configuration 0x48 32 read-write 0x1FF 0x1FF PHY_ERROR_DECODE_EN Enable Counting of 8b/10b Decode Errors (RxStatus == 3'b100) [0:0] read-write PHY_ERROR_EB_OVR_EN Enable Counting of Elastic Buffer Overflow (RxStatus == 3'b101) [1:1] read-write PHY_ERROR_EB_UND_EN Enable Counting of Elastic Buffer Underflow (RxStatus == 3'b110) [2:2] read-write PHY_ERROR_DISPARITY_EN Enable Counting of Receive Disparity Error (RxStatus == 3'b111) [3:3] read-write RX_ERROR_CRC5_EN Enable Counting of Receive CRC-5 Error [4:4] read-write RX_ERROR_CRC16_EN Enable Counting of Receive CRC-16 Error [5:5] read-write RX_ERROR_CRC32_EN Enable Counting of Receive CRC-32 Error [6:6] read-write TRAINING_ERROR_EN Enable Counting of Training Sequence Error [7:7] read-write PHY_LOCK_EN Enable Counting of PHY Lock Loss Lock Indicator To Be Determined [8:8] read-write LNK_PHY_ERROR_STATUS PHY Error Status Register 0x4C 32 read-write 0x0 0x1FF PHY_ERROR_DECODE_EV Indicates this error (see LNK_ERROR_CONF for description) occurred since this bit was last cleared by firmware. [0:0] read-write PHY_ERROR_EB_OVR_EV Indicates this error (see LNK_ERROR_CONF for description) occurred since this bit was last cleared by firmware. [1:1] read-write PHY_ERROR_EB_UND_EV Indicates this error (see LNK_ERROR_CONF for description) occurred since this bit was last cleared by firmware. [2:2] read-write PHY_ERROR_DISPARITY_EV Indicates this error (see LNK_ERROR_CONF for description) occurred since this bit was last cleared by firmware. [3:3] read-write RX_ERROR_CRC5_EV Indicates this error (see LNK_ERROR_CONF for description) occurred since this bit was last cleared by firmware. [4:4] read-write RX_ERROR_CRC16_EV Indicates this error (see LNK_ERROR_CONF for description) occurred since this bit was last cleared by firmware. [5:5] read-write RX_ERROR_CRC32_EV Indicates this error (see LNK_ERROR_CONF for description) occurred since this bit was last cleared by firmware. [6:6] read-write TRAINING_ERROR_EV Indicates this error (see LNK_ERROR_CONF for description) occurred since this bit was last cleared by firmware. [7:7] read-write PHY_LOCK_EV Indicates this error (see LNK_ERROR_CONF for description) occurred since this bit was last cleared by firmware. [8:8] read-write LNK_PHY_TRAINING_HOLDOFF PHY Training Hold Off 0x50 32 read-write 0x249F0EA6 0xFFFFFFFF GEN1_HOLDOFF Hold off period before PHY training begins to prevent termination reflection errors. Default is 30 us, period is measured in 125MHz clocks. [USB 3.0: 7.5.4.4.1, p 7-44] [15:0] read-write GEN2_HOLDOFF Hold off period before PHY training, assertion of the rxequalization of PIPE begins to prevent termination reflection errors. Default is 30 us, period is measured in 312.5MHz clocks. [USB 3.2: 7.5.4.7.1] [31:16] read-write LNK_COMMAND_WORD Link Command Word (received) 0x54 32 read-only 0x0 0x7FF COMMAND Link Command Word [10:0] read-only LNK_DEVICE_POWER_CONTROL USB 3.0 Device Power State Control 0x58 32 read-write 0x0 0xFC0003F7 TX_U1 Transmit LGO_U1 - Request to go to U1 Power State (send LGO_U1) This bit is cleared by h/w when the LCW is transmitted. [0:0] read-write TX_U2 Transmit LGO_U2 - Request to go to U2 Power State (send LGO_U2) This bit is cleared by h/w when the LCW is transmitted. [1:1] read-write TX_U3 Transmit LGO_U3 - Request to go to U3 Power State (send LGO_U3) This bit is cleared by h/w when the LCW is transmitted. Note that an upstream port is not allowed to initiate entry to U3, so this should not be used for device mode. [USB 3.0: 7.2.4.2.4, p 7-25] [2:2] read-write RX_U1 LGO_U1 Received - Request to go to U1 Power State This bit is cleared by h/w concurrent with TX_LAU/TX_LXU being cleared. [4:4] read-only RX_U2 LGO_U2 Received - Request to go to U2 Power State, clear to NAK (send LXU) This bit is cleared by h/w concurrent with TX_LAU/TX_LXU being cleared. [5:5] read-only RX_U3 LGO_U3 Received - Request to go to U3 Power State, clear to NAK (send LXU) This bit is cleared by h/w concurrent with TX_LAU/TX_LXU being cleared. Note that an upstream port is not allowed to reject entry to U3. [USB 3.0: 7.2.4.2.4, p 7-25] [6:6] read-only TX_LAU Transmit LAU (ACK) in response to RX_U1/RX_U2/RX_U3. Transition to requested power state (LTSSM) This bit is cleared when the acknowledgement is sent. [7:7] read-write TX_LXU Transmit LXU (NAK) in response to RX_U1/RX_U2/RX_U3. Do not transition to requested power state (LTSSM) This bit is cleared when the acknowledgement is sent. [8:8] read-write EXIT_LP Exit Low Power State This bit is cleared by h/w when the Link Layer has exited U1/U2/U3. [9:9] read-write AUTO_U1 When host requests transition to U1, automatically accept (send LAU) or rejects (send LXU) depending on pending activity. The interrupt RX_U1 is still raised for firmware to monitor, take additional power saving actions. [26:26] read-write AUTO_U2 When host requests transition to U2, automatically accept (send LAU) or rejects (send LXU) depending on pending activity. The interrupt RX_U2 is still raised for firmware to monitor, take additional power saving actions. [27:27] read-write NO_U1 When host requests transition to U1, automatically reject (send LXU). The interrupt RX_U1 is still raised for firmware to monitor, take additional actions. This bit must be cleared by firmware when FORCE_PM_ACCEPT is received from host. [28:28] read-write NO_U2 When host requests transition to U2, automatically reject (send LXU). The interrupt RX_U2 is still raised for firmware to monitor, take additional actions. This bit must be cleared by firmware when FORCE_PM_ACCEPT is received from host. [29:29] read-write YES_U1 When host requests transition to U1, automatically accept (send LAU). The interrupt RX_U1 is still raised for firmware to monitor, take additional power saving actions. [30:30] read-write YES_U2 When host requests transition to U2, automatically accept (send LAU). The interrupt RX_U2 is still raised for firmware to monitor, take additional power saving actions. [31:31] read-write LNK_LTSSM_STATE Link Training Status State Machine (LTSSM) State 0x5C 32 read-write 0x0 0x8003FFFF LTSSM_STATE LTSSM State See USB3LNK_LTSSM Tab for more details. [5:0] read-only LTSSM_OVERRIDE_VALUE LTSSM State from FW (if LTSSM_OVERRIDE_ENABLE == 1 or LTSSM_OVERRIDE_GO == 1) [11:6] read-write LTSSM_OVERRIDE_EN FW Control of LTSSM State Setting this bit will cause the LTSSM State Machine to transition to the state in LTSSM_OVERRIDE_VALUE and remain there. [12:12] read-write LTSSM_OVERRIDE_GO FW Setting of LTSSM State Setting this bit will cause the LTSSM State Machine to transition to the value given in LTSSM_OVERRIDE_VALUE, but the state machine will not be held there and may transition to other states as dictated by the logic To enable the U0 force entry: // This is for Powerdown as 0 regacc.regrd_n('USB32DEV_LNK_LNK_PHY_CONF', rd_data); wr_data = rd_data ; wr_data[17] = 'd1 ; wr_data[19:18] = 'd0 ; regacc.regwr_n('USB32DEV_LNK_LNK_PHY_CONF', wr_data); // This is for U0 LTSSM regacc.regrd_n('USB32DEV_LNK_LNK_LTSSM_STATE', rd_data); wr_data = rd_data ; wr_data[11:6] = 'd16 ; wr_data[12] = 'd1 ; regacc.regwr_n('USB32DEV_LNK_LNK_LTSSM_STATE', wr_data); // Wait #0.5us ; // Here enable is de-asserted and go is asserted regacc.regrd_n('USB32DEV_LNK_LNK_LTSSM_STATE', rd_data); wr_data = rd_data ; wr_data[11:6] = 'd16 ; wr_data[12] = 'd0 ; wr_data[13] = 'd1 ; regacc.regwr_n('USB32DEV_LNK_LNK_LTSSM_STATE', wr_data); [13:13] read-write LOOPBACK_MASTER Loopback Master Enable When transmitting TS2 ordered sets in Polling or Recovery State, the Link Layer Block will enter the Loopback State as the Loopback Master if this bit is set. The Link Layer Block will then exit the Loopback State when this bit is cleared. [USB 3.0: 7.5.4.6.1, p 7-45; 7.5.10.5.2, p 7-55] [14:14] read-write DISABLE_SCRAMBLING Scrambling Disable When transmitting TS2 ordered sets in Polling or Recovery State, the Link Layer Block will set the Disable Scrambling bit. [USB 3.0: 7.5.4.6.1, p 7-45] [15:15] read-write LOOPBACK_ERROR Loopback Master Error Detected [16:16] read-only LOOPBACK_GOOD Loopback Master Good Transmit sequence is being received correctly. [17:17] read-only LTSSM_FREEZE Freeze LTSSM to allow FW to inspect its current state. Setting this bit will cease all header packet transmission. Incoming header packets will still be received and acknowledged but no more header packets will be accepted for transmission from the protocol layer. It is expected that soon after this bit is set RX a queue will fill up and become stable for firmware to inspect. [31:31] read-write LNK_LOOPBACK_INIT Loopback LFSR Initial Value 0x60 32 read-write 0x1 0xFFFFFFFF INIT Initial value for Loopback LFSR Transmitter [31:0] read-write LNK_LOOPBACK_GENERATOR Loopback LFSR Transmitter Generator Polynomial 0x64 32 read-write 0xC0000030 0xFFFFFFFF GENERATOR Generator Polynomial for Loopback LFSR Transmitter [31:0] read-write LNK_LTSSM_OBSERVE Link Training Status State Machine (LTSSM) Observation 0x68 32 read-write 0x4080 0xDFFFFFFF RX_DETECT_MISS_CNT Number of RxDetect events where no termination was detected since last RxDetect event [3:0] read-only RX_DETECT_MISS_LIMIT Number of RxDetect attempts before giving up (default 8x as per spec) [7:4] read-write RECOVERY_CNT Number of Recovery attempts from U0 since last entering U0 [11:8] read-only RECOVERY_LIMIT Number of Recovery attempts before going to SS.Inactive from U0 (default 4x as per spec). [15:12] read-write TS1_RCVD_CNT Number of TS1 Ordered Sets received since last Polling state entry [19:16] read-only TS2_RCVD_CNT Number of TS2 Ordered Sets received since last Polling/HotReset state entry [23:20] read-only IDLE_RCVD_CNT Number of Idle Symbols Received since last HotReset entry [27:24] read-only POLLING_LFPS_COMPLETED Indicates whether a Polling.LFPS sequence has ever been completed since the last UIB Block Reset or VBUS Off/On event [28:28] read-only DATA_RATE_CONFIG 00: GEN1x1 01: GEN1x2 10: GEN2x1 11: GEN2x2 [31:30] read-only LNK_LFPS_OBSERVE LFPS Receiver Observability 0x6C 32 read-write 0x0 0x3FF0FFF POLLING_DET LFPS Sequence detected since last cleared by CPU [0:0] read-write PING_DET LFPS Sequence detected since last cleared by CPU [1:1] read-write RESET_DET LFPS Sequence detected since last cleared by CPU [2:2] read-write U1_EXIT_DET LFPS Sequence detected since last cleared by CPU [3:3] read-write U2_EXIT_DET LFPS Sequence detected since last cleared by CPU [4:4] read-write U3_EXIT_DET LFPS Sequence detected since last cleared by CPU [5:5] read-write LOOPBACK_DET LFPS Sequence detected since last cleared by CPU [6:6] read-write SCD1_DET LFPS Sequence detected since last cleared by CPU [7:7] read-write SCD2_DET LFPS Sequence detected since last cleared by CPU [8:8] read-write PHY_CAP_LBPM_10G_DET LFPS Sequence detected since last cleared by CPU [9:9] read-write PHY_CAP_LBPM_5G_DET LFPS Sequence detected since last cleared by CPU [10:10] read-write PHY_READY_LBPM_DET LFPS Sequence detected since last cleared by CPU [11:11] read-write POLLING_LFPS_RCVD Number of LFPS Polling Bursts Received since last Polling.LFPS entry [20:16] read-only POLLING_LFPS_SENT Number of LFPS Polling Bursts Sent since last Polling.LFPS entry [25:21] read-only LNK_LFPS_TX_POLLING_BURST LFPS Polling Transmit Configuration 0x70 32 read-write 0x7D 0xFFFF BURST16 Clock periods for LFPS Burst, when LFPS signalling is transmitted (default: 1.0us) [15:0] read-write LNK_LFPS_TX_POLLING_REPEAT LFPS Polling Transmit Configuration 0x74 32 read-write 0x4E2 0xFFFF REPEAT16 Clock periods for LFPS Repeat, the time between LFPS Bursts (default: 10.0 us) [15:0] read-write LNK_LFPS_TX_PING_BURST LFPS Ping Transmit Configuration 0x78 32 read-write 0xF 0xFFFF BURST16 Clock periods for Ping.LFPS Burst signalling transmission (default: 120 ns) SS: range of (40ns, 200ns) [15:0] read-write LNK_LFPS_TX_PING_REPEAT LFPS Ping Transmit Configuration 0x7C 32 read-write 0x17D7840 0xFFFFFFFF REPEAT32 Clock periods for LFPS Repeat [31:0] read-write LNK_LFPS_TX_U1_EXIT LFPS U1_EXIT Transmit Configuration 0x80 32 read-write 0x71 0xFFFF BURST16 Number of clock periods for LFPS Burst transmission (default: 904 ns) [15:0] read-write LNK_LFPS_TX_U2_EXIT LFPS U2_EXIT Transmit Configuration 0x84 32 read-write 0x2710 0xFFFFFF BURST24 Minimum number of clock periods for LFPS Burst transmission (default: 80 us) [23:0] read-write LNK_LFPS_TX_U3_EXIT LFPS U3 Exit Transmit Configuration 0x88 32 read-write 0x2710 0xFFFFFF BURST24 Minimum number of clock periods for LFPS Burst transmission (default: 80 us) [23:0] read-write LNK_LFPS_RX_POLLING_BURST LFPS Polling Detect Configuration 0x8C 32 read-write 0xAF004B 0xFFFFFFFF BURST_MIN Minimum number of clock periods for detection of Polling.LFPS Burst (default: 0.6 us) [15:0] read-write BURST_MAX Maximum number of clock periods for detection of Polling.LFPS Burst (default: 1.4 us) [31:16] read-write LNK_LFPS_RX_POLLING_REPEAT LFPS Polling Detect Configuration 0x90 32 read-write 0x6D602EE 0xFFFFFFFF REPEAT_MIN Minimum number of clock periods of idle (non-LFPS) time between LFPS Bursts for detection of Polling.LFPS signalling (default: 6 us) [15:0] read-write REPEAT_MAX Maximum number of clock periods of idle (non-LFPS) time between LFPS Bursts for detection of Polling.LFPS signalling (default: 14 us) [31:16] read-write LNK_LFPS_RX_PING LFPS Ping Detect Configuration 0x94 32 read-write 0x190005 0xFFFFFFFF BURST_MIN Minimum number of clock periods for detection of Ping.LFPS Burst (default: 40 ns) [15:0] read-write BURST_MAX Maximum number of clock periods for detection of Ping.LFPS Burst (default: 200 ns) [31:16] read-write LNK_LFPS_RX_RESET LFPS Reset Detect Configuration 0x98 32 read-write 0x989680 0xFFFFFF BURST24 Minimum number of clock periods for detection (default: 80ms) [23:0] read-write LNK_LFPS_RX_U1_EXIT LFPS U1 Exit Detect Configuration 0x9C 32 read-write 0x26 0xFFFF BURST16 Minimum number of clock periods for U1 Exit Burst detection (default: 304 ns) [15:0] read-write LNK_LFPS_RX_U2_EXIT LFPS U2 Exit Detect Configuration 0xA0 32 read-write 0x2710 0xFFFFFF BURST24 Minimum number of clock periods for U2 Exit Burst detection (default: 80 us) [23:0] read-write LNK_LFPS_RX_U3_EXIT LFPS U3 Exit Detect Configuration 0xA4 32 read-write 0x2 0xFFFF BURST16 Minimum number of clock periods for detection (default: 62.5us) [15:0] read-write LNK_LFPS_RX_U1_HANDSHAKE LFPS U1 Exit Handshake Configuration 0xA8 32 read-write 0x26 0xFFFF BURST16 Minimum number of clock periods for LFPS handshake detection (default: 304 ns) [15:0] read-write LNK_LFPS_RX_U2_HANDSHAKE LFPS U2 Exit Handshake Configuration 0xAC 32 read-write 0x2710 0xFFFFFF BURST24 Minimum number of clock periods for LFPS handshake detection (default: 80 us) [23:0] read-write LNK_LFPS_RX_U3_HANDSHAKE LFPS U3 Exit Handshake Configuration 0xB0 32 read-write 0x2710 0xFFFFFF BURST24 Minimum number of clock periods for LFPS handshake detection (default: 80 us) [23:0] read-write LNK_LFPS_RX_LOOPBACK_EXIT LFPS Loopback Exit Detect Configuration 0xB4 32 read-write 0x2710 0xFFFFFF BURST24 Minimum number of clock periods for detection (default: 80us) [23:0] read-write LNK_LFPS_RX_LOOPBACK_HANDSHAKE LFPS Loopback Exit Handshake Configuration 0xB8 32 read-write 0x2710 0xFFFFFF BURST24 Minimum number of clock periods for LFPS handshake detection (default: 80 us) [23:0] read-write LNK_LFPS_RX_IDLE LFPS Idle Time 0xBC 32 read-only 0x0 0xFFFFFFFF TIME Idle time before last LFPS burst [31:0] read-only LNK_LFPS_RX_BURST LFPS Burst Length 0xC0 32 read-only 0x0 0xFFFFFFFF TIME Last LFPS burst length [31:0] read-only LNK_LFPS_RX_TIME LFPS Idle Counter 0xC4 32 read-only 0x0 0xFFFFFFFF TIME Time since end of last LFPS burst [31:0] read-only LNK_PENDING_HP_TIMER Header Packet LGOOD/LBAD Timer 0xC8 32 read-only 0x0 0xFFFF TIMER16 PENDING_HP_TIMER Value [15:0] read-only LNK_PENDING_HP_TIMEOUT Header Packet LGOOD/LBAD Timeout 0xCC 32 read-write 0x4E2 0xFFFF TIMEOUT16 PENDING_HP_TIMER Timeout (default: 10 us) [default: table 7-7, p 7-22] (0= Timer Disabled) [15:0] read-write LNK_CREDIT_HP_TIMER Header Packet LCRDx Timer 0xD0 32 read-only 0x0 0xFFFFFFFF TIMER CREDIT_HP_TIMER Value [31:0] read-only LNK_CREDIT_HP_TIMEOUT Header Packet LCRDx Timeout 0xD4 32 read-write 0x98968 0xFFFFFFFF TIMEOUT CREDIT_HP_TIMER Timeout (default: 5 ms) [default: table 7-7, p 7-22] (0= Timer Disabled) [31:0] read-write LNK_PM_TIMER Power Mode Timer 0xD8 32 read-only 0x0 0xFFFFFFFF TIMER PM_TIMER Value [31:0] read-only LNK_PM_LC_TIMEOUT Power Mode PM_LC_TIMER Timeout 0xDC 32 read-write 0x1F4 0xFFFF TIMEOUT16 PM_LC_TIMER Gen1x1 Timeout (default: 4 us) (0= Timer Disabled) [15:0] read-write LNK_PM_ENTRY_TIMEOUT Power Mode PM_ENTRY_TIMER Timeout 0xE0 32 read-write 0x3E8 0xFFFF TIMEOUT16 PM_ENTRY_TIMER Timeout (default: 8 us) (0= Timer Disabled) [15:0] read-write LNK_PM_UX_EXIT_TIMEOUT Power Mode Ux_EXIT_TIMER Timeout 0xE4 32 read-write 0xB71B0 0xFFFFFFFF TIMEOUT Ux_EXIT_TIMER Timeout (default: 6 ms) [default: table 7-8, p 7-23] (0= Timer Disabled) [31:0] read-write LNK_LTSSM_TIMER LTSSM Timer Register 0xE8 32 read-only 0x0 0xFFFFFFFF TIMER LTSSM State Transition Timer [31:0] read-only LNK_LTSSM_TIMEOUT LTSSM Timeout Observability Register 0xEC 32 read-write 0x0 0x3FFF POLLING_LFPS LTSSM Polling LFPS Timeout [0:0] read-write POLLING_ACTIVE LTSSM Polling Active Timeout [1:1] read-write POLLING_IDLE LTSSM Polling Idle Timeout [2:2] read-write U1_EXIT LTSSM U1 Exit Timeout [3:3] read-write U2_EXIT LTSSM U2 Exit Timeout [4:4] read-write U3_EXIT LTSSM U3 Exit Timeout [5:5] read-write HOT_RESET_ACTIVE LTSSM Hot Reset Active Timeout [6:6] read-write HOT_RESET_EXIT LTSSM Hot Reset Exit Timeout [7:7] read-write LOOPBACK_EXIT LTSSM Loopback Exit Timeout [8:8] read-write RECOVERY_IDLE LTSSM Recovery Idle Timeout [9:9] read-write RECOVERY_ACTIVE LTSSM Recovery Active Timeout [10:10] read-write RECOVERY_CONFIG LTSSM Recovery Configuration Timeout [11:11] read-write POLLING_SCD_LFPS LTSSM Polling SCD LFPS Timeout [12:12] read-write POLLING_LBPM_LFPS LTSSM Polling LBPM Timeout [13:13] read-write LNK_LTSSM_U2_TERM_DET_PERIOD LTSSM U2 Termination Detect Period 0xF0 32 read-write 0x0 0xFFFFFF PERIOD24 Time between far-end receiver termination detection sequences in the U2 State (default: off) (0= Timer Disabled) [23:0] read-write LNK_LTSSM_U3_TERM_DET_PERIOD LTSSM U3 Termination Detect Period 0xF4 32 read-write 0x0 0xFFFFFF PERIOD24 Time between far-end receiver termination detection sequences in the U3 State (default: off) (0= Timer Disabled) [23:0] read-write LNK_LTSSM_RX_DETECT_PERIOD LTSSM RxDetect Period 0xF8 32 read-write 0x16E360 0xFFFFFF PERIOD24 LTSSM RxDetect.Quiet Period (default: 12 ms) [default: table 7-12, p 7-36] (0= Timer Disabled) [23:0] read-write LNK_LTSSM_LUP_PERIOD LTSSM LUP Period 0xFC 32 read-write 0x4E2 0xFFFFFF PERIOD24 LTSSM U0 LUP Transmision Interval (default: 10 us) [default: table7.5.6.1, p 7-48] (0= Timer Disabled) [23:0] read-write LNK_LTSSM_SS_INACTIVE_PERIOD LTSSM SS.Inactive Timeout 0x100 32 read-write 0x16E360 0xFFFFFF PERIOD24 LTSSM SS.Inactive.Quiet timeout (default: 12ms) (0= Timer Disabled) [23:0] read-write LNK_LTSSM_POLLING_LFPS_TIMEOUT LTSSM Polling LFPS Timeout 0x104 32 read-write 0x2AEA540 0xFFFFFFFF TIMEOUT LTSSM Polling.LFPS Timeout (default: 360 ms) [default: table 7-12, p 7-36] (0= Timer Disabled) [31:0] read-write LNK_LTSSM_POLLING_ACTIVE_TIMEOUT LTSSM Polling Active Timeout 0x108 32 read-write 0x16E360 0xFFFFFF TIMEOUT24 LTSSM Polling.Active Timeout (default: 12 ms) [default: table 7-12, p 7-36] (0= Timer Disabled) [23:0] read-write LNK_LTSSM_POLLING_CONFIG_TIMEOUT LTSSM Polling Configuration Timeout 0x10C 32 read-write 0x16E360 0xFFFFFF TIMEOUT24 LTSSM Polling.Configuration Timeout (default: 12 ms) [default: table 7-12, p 7-36] (0= Timer Disabled) [23:0] read-write LNK_LTSSM_POLLING_IDLE_TIMEOUT LTSSM Polling Idle Timeout 0x110 32 read-write 0x3D090 0xFFFFFF TIMEOUT24 LTSSM Polling.Idle Timeout (default: 2 ms) [default: table 7-12, p 7-36] (0= Timer Disabled) [23:0] read-write LNK_LTSSM_U1_EXIT_TIMEOUT LTSSM U1 Exit Timeout 0x114 32 read-write 0x3D090 0xFFFFFF TIMEOUT24 LTSSM U1 Timeout (default: 2 ms) for LFPS Handshake [default: table 7-12, p 7-36] (0= Timer Disabled) [23:0] read-write LNK_LTSSM_U2_EXIT_TIMEOUT LTSSM U2 Exit Timeout 0x118 32 read-write 0x3D090 0xFFFFFF TIMEOUT24 LTSSM U2 Timeout (default: 2 ms) for LFPS Handshake [default: table 7-12, p 7-36] (0= Timer Disabled) [23:0] read-write LNK_LTSSM_U3_EXIT_TIMEOUT LTSSM U3 Exit Timeout 0x11C 32 read-write 0x1E848 0xFFFFFF TIMEOUT24 LTSSM U3 Timeout (default: 10 ms) for LFPS Handshake [default: table 7-12, p 7-36] (0= Timer Disabled) [23:0] read-write LNK_LTSSM_HOT_RESET_ACTIVE_TIMEOUT LTSSM Hot Reset Active Timeout 0x120 32 read-write 0x16E360 0xFFFFFF TIMEOUT24 LTSSM Hot Reset Acitve Timeout (default: 12 ms) [default: table 7-12, p 7-36] (0= Timer Disabled) [23:0] read-write LNK_LTSSM_HOT_RESET_EXIT_TIMEOUT LTSSM Hot Reset Exit Timeout 0x124 32 read-write 0x3D090 0xFFFFFF TIMEOUT24 LTSSM Hot Reset Exit Timeout (default: 2 ms) [default: table 7-12, p 7-36] (0= Timer Disabled) [23:0] read-write LNK_LTSSM_LOOPBACK_EXIT_TIMEOUT LTSSM Loopback Exit Timeout 0x128 32 read-write 0x3D090 0xFFFFFFFF TIMEOUT LTSSM Loopback Exit Timeout (default: 2 ms) [default: table 7-12, p 7-36] (0= Timer Disabled) [31:0] read-write LNK_LTSSM_RECOVERY_IDLE_TIMEOUT LTSSM Recovery Idle Timeout 0x12C 32 read-write 0x3D090 0xFFFFFF TIMEOUT24 LTSSM Recovery Idle Timeout (default: 2 ms) [default: table 7-12, p 7-36] (0= Timer Disabled) [23:0] read-write LNK_LTSSM_RECOVERY_ACTIVE_TIMEOUT LTSSM Recovery Active Timeout 0x130 32 read-write 0x16E360 0xFFFFFF TIMEOUT24 LTSSM Recovery Active Timeout (default: 12 ms) [default: table 7-12, p 7-36] (0= Timer Disabled) [23:0] read-write LNK_LTSSM_RECOVERY_CONFIG_TIMEOUT LTSSM Recovery.Configuration Timeout 0x134 32 read-write 0xB71B0 0xFFFFFF TIMEOUT24 LTSSM Recovery Configuration Timeout (default: 6 ms) [default: table 7-12, p 7-36] (0= Timer Disabled) [23:0] read-write LNK_LTSSM_LDN_TIMEOUT LTSSM LDN Received Timeout 0x138 32 read-write 0x1E848 0xFFFFFF TIMEOUT24 LTSSM LDN Received Timeout (default: 1 ms) (0= Timer Disabled) [23:0] read-write LNK_LTSSM_LDN_TIMER LTSSM LDN Received Timer 0x13C 32 read-only 0x0 0xFFFFFF TIMER24 LTSSM Recovery Configuration Timeout (default: 6 ms) [default: table 7-12, p 7-36] (0= Timer Disabled) [23:0] read-only LNK_COMPLIANCE_PATTERN_0 Compliance Pattern CP0 0x140 32 read-write 0x600 0x1FFF CP Compliance Pattern [7:0] read-write K_D Symbol Type - 0: Data (D), 1: Symbol (K) [8:8] read-write SCRAMBLED Scramble On/Off [9:9] read-write DEEMPHASIS De-emphasis On/Off [10:10] read-write LFPS LFPS On/Off [11:11] read-write TXONESZEROS Enable TXONESZEROS (PIPE PHY Transmit Signal) [12:12] read-write LNK_COMPLIANCE_PATTERN_1 Compliance Pattern CP1 0x144 32 read-write 0x44A 0x1FFF CP Compliance Pattern [7:0] read-write K_D Symbol Type - 0: Data (D), 1: Symbol (K) [8:8] read-write SCRAMBLED Scramble On/Off [9:9] read-write DEEMPHASIS De-emphasis On/Off [10:10] read-write LFPS LFPS On/Off [11:11] read-write TXONESZEROS Enable TXONESZEROS (PIPE PHY Transmit Signal) [12:12] read-write LNK_COMPLIANCE_PATTERN_2 Compliance Pattern CP2 0x148 32 read-write 0x478 0x1FFF CP Compliance Pattern [7:0] read-write K_D Symbol Type - 0: Data (D), 1: Symbol (K) [8:8] read-write SCRAMBLED Scramble On/Off [9:9] read-write DEEMPHASIS De-emphasis On/Off [10:10] read-write LFPS LFPS On/Off [11:11] read-write TXONESZEROS Enable TXONESZEROS (PIPE PHY Transmit Signal) [12:12] read-write LNK_COMPLIANCE_PATTERN_3 Compliance Pattern CP3 0x14C 32 read-write 0x5BC 0x1FFF CP Compliance Pattern [7:0] read-write K_D Symbol Type - 0: Data (D), 1: Symbol (K) [8:8] read-write SCRAMBLED Scramble On/Off [9:9] read-write DEEMPHASIS De-emphasis On/Off [10:10] read-write LFPS LFPS On/Off [11:11] read-write TXONESZEROS Enable TXONESZEROS (PIPE PHY Transmit Signal) [12:12] read-write LNK_COMPLIANCE_PATTERN_4 Compliance Pattern CP4 0x150 32 read-write 0xC00 0x1FFF CP Compliance Pattern [7:0] read-write K_D Symbol Type - 0: Data (D), 1: Symbol (K) [8:8] read-write SCRAMBLED Scramble On/Off [9:9] read-write DEEMPHASIS De-emphasis On/Off [10:10] read-write LFPS LFPS On/Off [11:11] read-write TXONESZEROS Enable TXONESZEROS (PIPE PHY Transmit Signal) [12:12] read-write LNK_COMPLIANCE_PATTERN_5 Compliance Pattern CP5 0x154 32 read-write 0x5FC 0x1FFF CP Compliance Pattern [7:0] read-write K_D Symbol Type - 0: Data (D), 1: Symbol (K) [8:8] read-write SCRAMBLED Scramble On/Off [9:9] read-write DEEMPHASIS De-emphasis On/Off [10:10] read-write LFPS LFPS On/Off [11:11] read-write TXONESZEROS Enable TXONESZEROS (PIPE PHY Transmit Signal) [12:12] read-write LNK_COMPLIANCE_PATTERN_6 Compliance Pattern CP6 0x158 32 read-write 0x1FC 0x1FFF CP Compliance Pattern [7:0] read-write K_D Symbol Type - 0: Data (D), 1: Symbol (K) [8:8] read-write SCRAMBLED Scramble On/Off [9:9] read-write DEEMPHASIS De-emphasis On/Off [10:10] read-write LFPS LFPS On/Off [11:11] read-write TXONESZEROS Enable TXONESZEROS (PIPE PHY Transmit Signal) [12:12] read-write LNK_COMPLIANCE_PATTERN_7 Compliance Pattern CP7 0x15C 32 read-write 0x1400 0x1FFF CP Compliance Pattern [7:0] read-write K_D Symbol Type - 0: Data (D), 1: Symbol (K) [8:8] read-write SCRAMBLED Scramble On/Off [9:9] read-write DEEMPHASIS De-emphasis On/Off [10:10] read-write LFPS LFPS On/Off [11:11] read-write TXONESZEROS Enable TXONESZEROS (PIPE PHY Transmit Signal) [12:12] read-write LNK_COMPLIANCE_PATTERN_8 Compliance Pattern CP8 0x160 32 read-write 0x1000 0x1FFF CP Compliance Pattern [7:0] read-write K_D Symbol Type - 0: Data (D), 1: Symbol (K) [8:8] read-write SCRAMBLED Scramble On/Off [9:9] read-write DEEMPHASIS De-emphasis On/Off [10:10] read-write LFPS LFPS On/Off [11:11] read-write TXONESZEROS Enable TXONESZEROS (PIPE PHY Transmit Signal) [12:12] read-write LNK_DEBUG_BUFFER_CTRL Buffer direct access control 0x164 32 read-write 0x0 0x7 MEM_PTR 0: Retry buffer locations 0x00-0xFF 1: Retry buffer locations 0x100-0x1FF 2: Retry buffer locations 0x200-0x2FF 3: Retry buffer locations 0x300-0x3FF 4: Debug features 0x00-0xFF [2:0] read-write LNK_DATARATE_CHG_OBSERVE Dtat Rate Observability 0x168 32 read-write 0x0 0x1F DATA_RATE_CHG_DET Data rate change event detected since last cleared by CPU: 0: PHY initialized in Gen2 (10G) 1: PHY initialized in Gen1 (5G ) 2: G2->G1 switch due Polling.LFPS ->Polling.RxEq 3: G2->G1 switch due to Polling.LFPSPlus ->Polling.RxEq 4: G2->G1 switch due to receiving 5G-PHY capabiltiy LBPMs from partner in Polling.PortMatch state 5: G2->G1 switch due to Gen2-12ms timeout in Polling.Active (Polling.Active ->Polling.PortMatch ->Polling.PortConfig ->Polling.RxEq) 6: G2->G1 switch due to Gen2-12ms timeout in Polling.Configuration (Polling.Configuration ->Polling.PortMatch ->Polling.PortConfig ->Polling.RxEq) 7: G2->G1 switch due to Gen2-2ms timeout in Polling.Idle (Polling.Idle ->Polling.PortMatch ->Polling.PortConfig ->Polling.RxEq) 8: G1G2 swithching in Compliance (CP pattern swithces to Gen2) 9: G2G1 swithching in Compliance (CP pattern swithces to Gen1) 10: G1G2 swithching in Compliance due to receiving warm reset when the Gen2 link is transmitting Gen1 patterns 11: G1G2 swithcing Upon RX_DETECT_ACTIVE -> Polling States ( e.g. Gen2 Link settled in 5G data rate and then moves to SS.Inactive. Upon warm reset, HW switches to G1G2 ) [4:0] read-write LNK_LFPS_TX_POLLING_BURST_GEN2 LFPS Polling Transmit Gen2 Configuration 0x16C 32 read-write 0x139 0xFFFF BURST16 Clock periods for LFPS Burst, when LFPS signalling is transmitted (default: ~1.0us) [15:0] read-write LNK_LFPS_TX_POLLING_REPEAT_GEN2 LFPS Polling Transmit Gen2 Configuration 0x170 32 read-write 0xC35 0xFFFF REPEAT16 Clock periods for LFPS Repeat, the time between LFPS Bursts (default: 10.0 us) [15:0] read-write LNK_LFPS_TX_PING_BURST_GEN2 LFPS Ping Transmit Gen2 Configuration 0x174 32 read-write 0x20 0xFFFF BURST16 Clock periods for Ping.LFPS Burst signalling transmission (default: ~100 ns) SSP: range of (40ns, 160ns) [15:0] read-write LNK_LFPS_TX_PING_REPEAT_GEN2 LFPS Ping Transmit Gen2 Configuration 0x178 32 read-write 0x3B9ACA0 0xFFFFFFFF REPEAT32 Clock periods for LFPS Repeat (default: 200 ms) [31:0] read-write LNK_LFPS_TX_U1_EXIT_GEN2 LFPS U1_EXIT Transmit Gen2 Configuration 0x17C 32 read-write 0x11B 0xFFFF BURST16 Number of clock periods for LFPS Burst transmission (default: 905.6 ns) It is in the range of (900ns,2ms). [15:0] read-write LNK_LFPS_TX_U2_EXIT_GEN2 LFPS U2_EXIT Transmit Gen2 Configuration 0x180 32 read-write 0x61A8 0xFFFFFF BURST24 Minimum number of clock periods for LFPS Burst transmission (default: 80 us) [23:0] read-write LNK_LFPS_TX_U3_EXIT_GEN2 LFPS U3 Exit Transmit Gen2 Configuration 0x184 32 read-write 0x3D090 0xFFFFFF BURST24 Minimum number of clock periods for LFPS Burst transmission (default: 80 us) [23:0] read-write LNK_LFPS_RX_POLLING_BURST_GEN2 LFPS Polling Detect Gen2 Configuration 0x188 32 read-write 0x1B500BC 0xFFFFFFFF BURST_MIN Minimum number of clock periods for detection of Polling.LFPS Burst (default: ~0.6 us) [15:0] read-write BURST_MAX Maximum number of clock periods for detection of Polling.LFPS Burst (default: ~1.4 us) [31:16] read-write LNK_LFPS_RX_POLLING_REPEAT_GEN2 LFPS Polling Detect Gen2 Configuration 0x18C 32 read-write 0x11170753 0xFFFFFFFF REPEAT_MIN Minimum number of clock periods of idle (non-LFPS) time between LFPS Bursts for detection of Polling.LFPS signalling (default: 6 us) [15:0] read-write REPEAT_MAX Maximum number of clock periods of idle (non-LFPS) time between LFPS Bursts for detection of Polling.LFPS signalling (default: 14 us) [31:16] read-write LNK_LFPS_RX_PING_GEN2 LFPS Ping Detect Gen2 Configuration 0x190 32 read-write 0x32000D 0xFFFFFFFF BURST_MIN Minimum number of clock periods for detection of Ping.LFPS Burst (default: ~40 ns) [15:0] read-write BURST_MAX Maximum number of clock periods for detection of Ping.LFPS Burst (default: 160 ns) [31:16] read-write LNK_LFPS_RX_RESET_GEN2 LFPS Reset Detect Gen2 Configuration 0x194 32 read-write 0x3E800 0xFFFFFF BURST24 Minimum number of clock periods for detection (default: 80 ms) [23:0] read-write LNK_LFPS_RX_U1_EXIT_GEN2 LFPS U1 Exit Detect Gen2 Configuration 0x198 32 read-write 0x5E 0xFFFF BURST16 Minimum number of clock periods for U1 Exit Burst detection A port is still required to detect U1 LFPS exit signal at a minimum of 300ns. The extra 300ns is provided as the guard band for successful U1 LFPS exit handshake. (default: 300 ns) [15:0] read-write LNK_LFPS_RX_U2_EXIT_GEN2 LFPS U2 Exit Detect Gen2 Configuration 0x19C 32 read-write 0x61A8 0xFFFFFF BURST24 Minimum number of clock periods for U2 Exit Burst detection (default: 80 us) [23:0] read-write LNK_LFPS_RX_U1_HANDSHAKE_GEN2 LFPS U1 Exit Handshake Gen2 Configuration 0x1A0 32 read-write 0x5E 0xFFFF BURST16 Minimum number of clock periods for LFPS handshake detection (default: 301 ns) [15:0] read-write LNK_LFPS_RX_U2_HANDSHAKE_GEN2 LFPS U2 Exit Handshake Gen 2 Configuration 0x1A4 32 read-write 0x61A8 0xFFFFFF BURST24 Minimum number of clock periods for LFPS handshake detection (default: 80 us) [23:0] read-write LNK_LFPS_RX_U3_HANDSHAKE_GEN2 LFPS U3 Exit Handshake Gen 2 Configuration 0x1A8 32 read-write 0x61A8 0xFFFFFF BURST24 Minimum number of clock periods for LFPS handshake detection (default: 80 us) [23:0] read-write LNK_LFPS_RX_LOOPBACK_EXIT_GEN2 LFPS Loopback Exit Detect Gen2 Configuration 0x1AC 32 read-write 0x61A8 0xFFFFFF BURST24 Minimum number of clock periods for detection (default: 80us) [23:0] read-write LNK_LFPS_RX_LOOPBACK_HANDSHAKE_GEN2 LFPS Loopback Exit Handshake Gen2 Configuration 0x1B0 32 read-write 0x61A8 0xFFFFFF BURST24 Minimum number of clock periods for LFPS handshake detection (default: 80 us) [23:0] read-write LNK_PENDING_HP_TIMEOUT_GEN2 Header Packet LGOOD/LBAD Gen2 Timeout 0x1B4 32 read-write 0xC35 0xFFFF TIMEOUT16 PENDING_HP_TIMER Timeout (default: 10 us) (0= Timer Disabled) [15:0] read-write LNK_CREDIT_HP_TIMEOUT_GEN2 Header Packet LCRD_x Gen2 Timeout 0x1C4 32 read-write 0xEE6B28 0xFFFFFFFF TIMEOUT CREDIT_HP_TIMER Timeout (default: 5 ms) (0= Timer Disabled) [31:0] read-write LNK_PM_LC_X2_TIMEOUT_GEN1 Power Mode PM_LC_X2_TIMER Gen1 Timeout 0x1C8 32 read-write 0x3E8 0xFFFF TIMEOUT16 PM_LC_TIMER Timeout (default: 8 us) (0= Timer Disabled) It is used by initiating port. [15:0] read-write LNK_PM_LC_X1_TIMEOUT_GEN2 Power Mode PM_LC_X1_TIMER Gen2 Timeout 0x1CC 32 read-write 0x4E2 0xFFFF TIMEOUT16 PM_LC_TIMER Timeout (default: 4 us) (0= Timer Disabled) It is used by initiating port. [15:0] read-write LNK_PM_LC_X2_TIMEOUT_GEN2 Power Mode PM_LC_X2_TIMER Gen2 Timeout 0x1D0 32 read-write 0x9C4 0xFFFF TIMEOUT16 PM_LC_TIMER Timeout (default: 8 us) (0= Timer Disabled) It is used by initiating port. [15:0] read-write LNK_PM_ENTRY_X2_TIMEOUT_GEN1 Power Mode PM_ENTRY_X2_TIMER Gen1 Timeout 0x1D4 32 read-write 0x7D0 0xFFFF TIMEOUT16 PM_ENTRY_TIMER Timeout (default: 16 us) (0= Timer Disabled) It is used by the port receiving the request to enter the low power state. [15:0] read-write LNK_PM_ENTRY_X1_TIMEOUT_GEN2 Power Mode PM_ENTRY_X1_TIMER Gen2 Timeout 0x1D8 32 read-write 0x9C4 0xFFFF TIMEOUT16 PM_ENTRY_TIMER Timeout (default: 8 us) (0= Timer Disabled) It is used by the port receiving the request to enter the low power state. [15:0] read-write LNK_PM_ENTRY_X2_TIMEOUT_GEN2 Power Mode PM_ENTRY_X2_TIMER Gen2 Timeout 0x1DC 32 read-write 0x1388 0xFFFF TIMEOUT16 PM_ENTRY_TIMER Timeout (default: 16 us) (0= Timer Disabled) It is used by the port receiving the request to enter the low power state. [15:0] read-write LNK_PM_UX_EXIT_TIMEOUT_GEN2 Power Mode Ux_EXIT_TIMER Gen2 Timeout 0x1E0 32 read-write 0x1C9C38 0xFFFFFFFF TIMEOUT Ux_EXIT_TIMER Timeout (default: 6 ms) (0= Timer Disabled) It is used by the resume initiator. [31:0] read-write LNK_U1_MIN_RESIDENCY_TIMEOUT_GEN1 Power Mode U1_MIN_RESIDENCY_TIMER Gen1 Timeout 0x1E4 32 read-write 0x177 0xFFFF TIMEOUT16 U1_MIN_RESIDENCY_TIMER Timeout (default: 3 us) (0= Timer Disabled) [15:0] read-write LNK_U1_MIN_RESIDENCY_TIMEOUT_GEN2 Power Mode U1_MIN_RESIDENCY_TIMER Gen2 Timeout 0x1E8 32 read-write 0x3AA 0xFFFF TIMEOUT16 U1_MIN_RESIDENCY_TIMER Timeout (default: 3 us) (0= Timer Disabled) [15:0] read-write LNK_LFPS_TX_SCD_LOGIC0_REPEAT_GEN1 LFPS SCD Transmit Logic 0 Gen1 Configuration 0x1EC 32 read-write 0x3AA 0xFFFF REPEAT16 tRepeat duration of SCD Logic-0 LFPS transmission in 8 ns (default 7.5 us) tBURST+ElecIdle = 6 us - 9 us [15:0] read-write LNK_LFPS_TX_SCD_LOGIC1_REPEAT_GEN1 LFPS SCD Transmit Logic 1 Gen1 Configuration 0x1F0 32 read-write 0x61B 0xFFFF REPEAT16 tRepeat duration of SCD Logic-0 LFPS transmission in 8 ns (default 12.5 us) tBURST+ElecIdle = 11 us - 14 us [15:0] read-write LNK_LFPS_TX_SCD_END_REPEAT_GEN1 LFPS SCD Transmit End Gen1 Configuration 0x1F4 32 read-write 0xEA6 0xFFFF REPEAT16 tRepeat duration of SCD Logic-0 LFPS transmission in 8 ns (default 30 us) tBURST (0.6us ~1.4us) + ElecIdle (>28 us) [15:0] read-write LNK_LFPS_RX_SCD_LOGIC0_REPEAT_GEN1 LFPS SCD Receive Logic 0 Gen1 Gen1 Configuration 0x1F8 32 read-write 0x46502EE 0xFFFFFFFF REPEAT_MIN Minimum number of clock periods for detection of Polling.LFPS based SCD Logic 0 (default: 6 us) [15:0] read-write REPEAT_MAX Maximum number of clock periods for detection of Polling.LFPS based SCD Logic 0 (default: 9 us) [31:16] read-write LNK_LFPS_RX_SCD_LOGIC1_REPEAT_GEN1 LFPS SCD Receive Logic 1 Gen1 Configuration 0x1FC 32 read-write 0x6D6055F 0xFFFFFFFF REPEAT_MIN Minimum number of clock periods for detection of Polling.LFPS based SCD Logic 1 (default: 11 us) [15:0] read-write REPEAT_MAX Maximum number of clock periods for detection of Polling.LFPS based SCD Logic 1 (default: 14 us) [31:16] read-write LNK_LFPS_RX_SCD_END_REPEAT_GEN1 LFPS SCD Receive End Gen1 Configuration 0x200 32 read-write 0x22EA 0xFFFF REPEAT_MIN Minimum number of clock periods for detection of Polling.LFPS based SCD End (default: 28.6 us) [15:0] read-write LNK_LFPS_TX_SCD_LOGIC0_REPEAT_GEN2 LFPS SCD Transmit Logic 0 Gen2 Configuration 0x204 32 read-write 0x930 0xFFFF REPEAT16 tRepeat duration of SCD Logic-0 LFPS transmission in 3.2 ns (default 7.5 us) tBURST+ElecIdle = 6 us - 9 us [15:0] read-write LNK_LFPS_TX_SCD_LOGIC1_REPEAT_GEN2 LFPS SCD Transmit Logic 1 Gen2 Configuration 0x208 32 read-write 0xF42 0xFFFF REPEAT16 tRepeat duration of SCD Logic-0 LFPS transmission in 3.2 ns (default 12.5 us) tBURST+ElecIdle = 11 us - 14 us [15:0] read-write LNK_LFPS_TX_SCD_END_REPEAT_GEN2 LFPS SCD Transmit End Gen2 Configuration 0x20C 32 read-write 0x249F 0xFFFF REPEAT16 tRepeat duration of SCD Logic-0 LFPS transmission in 3.2ns (default 30 us) tBURST (0.6us ~1.4us) + ElecIdle (>28 us) [15:0] read-write LNK_LFPS_RX_SCD_LOGIC0_REPEAT_GEN2 LFPS SCD Receive Logic 0 Gen2 Configuration 0x210 32 read-write 0xAFC0753 0xFFFFFFFF REPEAT_MIN Minimum number of clock periods for detection of Polling.LFPS based SCD Logic 0 (default: 6 us) [15:0] read-write REPEAT_MAX Maximum number of clock periods for detection of Polling.LFPS based SCD Logic 0 (default: 9 us) [31:16] read-write LNK_LFPS_RX_SCD_LOGIC1_REPEAT_GEN2 LFPS SCD Receive Logic 1 Gen2 Configuration 0x220 32 read-write 0x11170D6E 0xFFFFFFFF REPEAT_MIN Minimum number of clock periods for detection of Polling.LFPS based SCD Logic 1 (default: 11 us) [15:0] read-write REPEAT_MAX Maximum number of clock periods for detection of Polling.LFPS based SCD Logic 1 (default: 14 us) [31:16] read-write LNK_LFPS_RX_SCD_END_REPEAT_GEN2 LFPS SCD Receive End Gen2 Configuration 0x224 32 read-write 0x22EA 0xFFFF REPEAT_MIN Minimum number of clock periods for detection of Polling.LFPS based SCD End (default: 28.6 us) [15:0] read-write LNK_LFPS_TX_LBPS_TPWM_GEN1 LFPS LBPS Transmit tPWM Gen1 Configuration 0x228 32 read-write 0x113 0xFFFF REPEAT16 tPWM duration of LFPS transmission in 8 ns (default 2.2 us) [15:0] read-write LNK_LFPS_TX_LBPS_TLFPS0_GEN1 LFPS LBPS Transmit tLFPS-0 Gen1 Configuration 0x238 32 read-write 0x52 0xFFFF BURST16 tLFPS-0 duration of LFPS transmission in 8 ns (default 0.65 us) [15:0] read-write LNK_LFPS_TX_LBPS_TLFPS1_GEN1 LFPS LBPS Transmit tLFPS-1 Gen1 Configuration 0x23C 32 read-write 0xC4 0xFFFF BURST16 tLFPS-1 duration of LFPS transmission in 8 ns (default 1.565 us) [15:0] read-write LNK_LFPS_RX_LBPS_TPWM_GEN1 LFPS LBPS Receive tPWM Gen1 Configuration 0x240 32 read-write 0x12C00FA 0xFFFFFFFF REPEAT_MIN Minimum number of clock periods for detection of tPWM of LFPS Based PWM Signaling (LBPS) (default: 2.0 us) [15:0] read-write REPEAT_MAX Maximum number of clock periods for detection of tPWM of LFPS Based PWM Signaling (LBPS) (default: 2.4 us) [31:16] read-write LNK_LFPS_RX_LBPS_TLFPS0_GEN1 LFPS LBPS Receive tLFPS-0 Gen1 Configuration 0x244 32 read-write 0x6A0039 0xFFFFFFFF BURST_MIN Minimum number of clock periods for detection of tLFPS-0 of LFPS Based PWM Signaling (LBPS) (default: 0.45 us) [15:0] read-write BURST_MAX Maximum number of clock periods for detection of tLFPS-0 of LFPS Based PWM Signaling (LBPS) (default: 0.85 us) [31:16] read-write LNK_LFPS_RX_LBPS_TLFPS1_GEN1 LFPS LBPS Receive tLFPS-1 Gen1 Configuration 0x248 32 read-write 0xE700A0 0xFFFFFFFF BURST_MIN Minimum number of clock periods for detection of tLFPS-1 of LFPS Based PWM Signaling (LBPS) (default: 1.28 us) [15:0] read-write BURST_MAX Maximum number of clock periods for detection of tLFPS-1 of LFPS Based PWM Signaling (LBPS) (default: 1.85 us) [31:16] read-write LNK_LFPS_TX_LBPS_TPWM_GEN2 LFPS LBPS Transmit tPWM Gen2 Configuration 0x24C 32 read-write 0x2AF 0xFFFF REPEAT16 tPWM duration of LFPS transmission in 3.2 ns (default 2.2 us) [15:0] read-write LNK_LFPS_TX_LBPS_TLFPS0_GEN2 LFPS LBPS Transmit tLFPS-0 Gen2 Configuration 0x250 32 read-write 0xCB 0xFFFF BURST16 tLFPS-0 duration of LFPS transmission in 3.2 ns (default 0.65 us) [15:0] read-write LNK_LFPS_TX_LBPS_TLFPS1_GEN2 LFPS LBPS Transmit tLFPS-1 Gen2 Configuration 0x254 32 read-write 0x1E9 0xFFFF BURST16 tLFPS-1 duration of LFPS transmission in 3.2 ns (default 1.565 us) [15:0] read-write LNK_LFPS_RX_LBPS_TPWM_GEN2 LFPS LBPS Receive tPWM Gen2 Configuration 0x258 32 read-write 0x2EE0271 0xFFFFFFFF REPEAT_MIN Minimum number of clock periods for detection of tPWM of LFPS Based PWM Signaling (LBPS) (default: 2.0 us) [15:0] read-write REPEAT_MAX Maximum number of clock periods for detection of tPWM of LFPS Based PWM Signaling (LBPS) (default: 2.4 us) [31:16] read-write LNK_LFPS_RX_LBPS_TLFPS0_GEN2 LFPS LBPS Receive tLFPS-0 Gen2 Configuration 0x25C 32 read-write 0x109008D 0xFFFFFFFF BURST_MIN Minimum number of clock periods for detection of tLFPS-0 of LFPS Based PWM Signaling (LBPS) (default: 0.45 us) [15:0] read-write BURST_MAX Maximum number of clock periods for detection of tLFPS-0 of LFPS Based PWM Signaling (LBPS) (default: 0.85 us) [31:16] read-write LNK_LFPS_RX_LBPS_TLFPS1_GEN2 LFPS LBPS Receive tLFPS-1 Gen2 Configuration 0x260 32 read-write 0x2420190 0xFFFFFFFF BURST_MIN Minimum number of clock periods for detection of tLFPS-1 of LFPS Based PWM Signaling (LBPS) (default: 1.28 us) [15:0] read-write BURST_MAX Maximum number of clock periods for detection of tLFPS-1 of LFPS Based PWM Signaling (LBPS) (default: 1.85 us) [31:16] read-write LNK_LFPS_SCD_PATTERN LFPS SCD Pattern Configuration 0x264 32 read-write 0xD2 0xFF SCD1_PATTERN SCD1 pattern (default: b0010) Only for Debug purpose and FW is not expected to modify [3:0] read-write SCD2_PATTERN SCD2 pattern (default: b1101) Only for Debug purpose and FW is not expected to modify [7:4] read-write LNK_TSEQ_COUNT_GEN1 TSEQ Count Gen1 Configuration 0x268 32 read-write 0x10000 0xFFFFFF COUNT24 The port in Gen 1 operation shall transition to Polling.Active after 65,536 consecutive TSEQ ordered sets (default 65536) [23:0] read-write LNK_TSEQ_COUNT_GEN2 TSEQ Count Gen2 Configuration 0x26C 32 read-write 0x80000 0xFFFFFF COUNT24 The port in Gen 2 operation shall transition to Polling.Active after 65,536 consecutive TSEQ ordered sets (default 524288) [23:0] read-write LNK_SCD1_GEN2_HSK SCD1 Handshake Gen2 Configuration 0x270 32 read-write 0x2101 0x7307 RX_SCDX_CNT The port in SuperSpeedPlus operation shall transition to Polling.LFPSPlus if two SCD1 are transmitted after one SCD1 or SCD2 as defined in Section 6.9.4.2 is received. [2:0] read-write ARX_SCDX_LIMIT N/A [9:8] read-write TX_ARX_SCD1_CNT N/A [14:12] read-write LNK_SCD1_GEN2_TO_GEN1_HSK SCD1 Handshake Gen2_to_Gen1 Configuration 0x274 32 read-write 0x10112410 0x1F777F7F SCDXCHK_RX_LFPS_CNT If it has received sixteen or more consecutive Polling.LFPS bursts and the tPollingSCDLFPSTimeout timer has not expired, it shall switch to SuperSpeed operation and transmit Polling.LFPS with non-varying tRepeat after four SCD1 are transmitted. [6:0] read-write G2G1_TX_SCD1_CNT N/A [11:8] read-write G2G1_RX_LFPS_CNT The completion of SS Polling.LFPS with two consecutive Polling.LFPS bursts received and one SCD1 or four consecutive Polling.LFPS bursts transmitted after receiving one Polling.LFPS burst. [14:12] read-write G2G1_ARX_LFPS_LIMIT N/A [18:16] read-write G2G1_TX_ARX_SCD1_CNT N/A [22:20] read-write G2G1_TX_LFPS_CNT At least 16 consecutive Polling.LFPS bursts meeting the Polling.LFPS specification defined in Section 6.9 are sent. [28:24] read-write LNK_SCD1_OBSERVE Polling.LFPS SCD1 Observability 0x278 32 read-write 0x0 0xC0707077 RCVD_SCD2_CNT N/A [2:0] read-only RCVD_SCD1_CNT N/A [6:4] read-only SENT_SCD1_CNT_G2_ARX N/A [14:12] read-only SENT_SCD1_CNT_G2G1_ARX N/A [22:20] read-only G2G1_LFPS_HSK_DONE Gen2 to Gen1 LFPS Handshake Done since last cleared by CPU [30:30] read-write SCD1_HSK_DONE SCD1 handshake Done since last cleared by CPU [31:31] read-write LNK_SCD2_GEN2_HSK SCD2 Handshake Gen2 Configuration 0x27C 32 read-write 0x2101 0x7307 RX_SCD2_CNT The port in SuperSpeedPlus operation shall transition to Polling.PortMatch if two SCD2 are transmitted after one SCD2 as defined in Section 6.9.4.2 is received. [2:0] read-write ARX_SCD2_LIMIT N/A [9:8] read-write TX_ARX_SCD2_CNT N/A [14:12] read-write LNK_SCD2_GEN2_TO_GEN1_HSK SCD2 Handshake Gen2_to_Gen1 Configuration 0x280 32 read-write 0x14000040 0x1F00007F SCD2CHK_RX_LFPS_CNT The port in SuperSpeedPlus operation shall transmit SCD2 defined in Table 6-33. If SCD2 cannot be found in 64 consecutive Polling.LFPS received, it shall transmit Polling.LFPS with non-varying tRepeat instead of SCD2. [6:0] read-write G2G1_TX_LFPS_CNT Twenty Polling.LFPS bursts with non-varying tRepeat are transmitted, after finding no SCD2 is detected. [28:24] read-write LNK_SCD2_OBSERVE Polling.LFPSPlus SCD2 Observability 0x284 32 read-write 0x0 0xC0000707 RCVD_SCD2_CNT The port in SuperSpeedPlus operation shall transition to Polling.PortMatch if two SCD2 are transmitted after one SCD2 as defined in Section 6.9.4.2 is received. [2:0] read-only SENT_SCD2_CNT_G2_ARX N/A [10:8] read-only G2G1_LFPS_HSK_DONE Gen2 to Gen1 LFPS Handshake Done since last cleared by CPU [30:30] read-write SCD2_HSK_DONE SCD2 handshake Done since last cleared by CPU Note: This asserts before SCD_END transmitting. After SCD_END transmitting completion, LTSSM moves to PORT_MATCH state. [31:31] read-write LNK_CAP_LBPM_HSK Polling.PortMatch LBPM Handshake Configuration 0x288 32 read-write 0x5220 0xF770 RX_CAP_LBPM_CNT The port shall transition to Polling.PortConfig when four consecutive and matched PHY Capability LBPMs are sent after two consecutive and matched PHY Capability LBPMs or PHY Ready LBPMs are received. [6:4] read-write ARX_LBPM_LIMIT N/A [10:8] read-write TX_ARX_CAP_LBPM_CNT N/A [15:12] read-write LNK_CAP_LBPM_OBSERVE Polling.PortMatch LBPM Observability 0x28C 32 read-write 0x0 0x80777777 RCVD_10GX1_CAP_LBPM_CNT N/A [2:0] read-only RCVD_5GX1_CAP_LBPM_CNT N/A [6:4] read-only RCVD_10GX2_CAP_LBPM_CNT N/A [10:8] read-only RCVD_5GX2_CAP_LBPM_CNT N/A [14:12] read-only RCVD_READY_LBPM_CNT N/A [18:16] read-only SENT_CAP_LBPM_CNT_ARX N/A [22:20] read-only CAP_LBPM_HSK_DONE Capability LBPM handshake Done since last cleared by CPU [31:31] read-write LNK_READY_LBPM_HSK Polling.PortConfig LBPM Handshake Configuration 0x290 32 read-write 0x422 0xFF0F77 RX_RDY_LBPM_CNT The port shall transition to Polling.PortConfig when four consecutive and matched PHY Capability LBPMs are sent after two consecutive and matched PHY Capability LBPMs or PHY Ready LBPMs are received. [2:0] read-write ARX_RDY_LBPM_LIMIT N/A [6:4] read-write TX_ARX_RDY_LBPM_CNT N/A [11:8] read-write ENTRY_TO_TX_DELAY Start-up delay to transmit Ready.LBPMs once LTSSM enters the Polling.PortConfig state if PHY re-configuration required. Note that the delay value is counted in the unit of 8 ns. [23:16] read-write LNK_READY_LBPM_OBSERVE Polling.PortConfig LBPM Observability 0x294 32 read-write 0x0 0x800000F7 RCVD_RDY_LBPM_CNT The port shall transition to Polling.PortConfig when four consecutive and matched PHY Capability LBPMs are sent after two consecutive and matched PHY Capability LBPMs or PHY Ready LBPMs are received. [2:0] read-only SENT_RDY_LBPM_CNT_ARX N/A [7:4] read-only RDY_LBPM_HSK_DONE ReadyLBPM handshake Done since last cleared by CPU [31:31] read-write LNK_RCVD_LBPM_OBSERVE Received LBPM Observability 0x298 32 read-only 0x0 0xFF LBPM Reveived LBPM [7:0] read-only LNK_LTSSM_SCD_LFPS_TIMEOUT LTSSM SCD LFPS Timeout (SuperSpeedPlus Only) 0x29C 32 read-write 0x1D4C 0xFFFF TIMEOUT16 LTSSM Polling.LFPS/Polling.LFPSPlus Timeout (default: 60 us in 8 ns) (0= Timer Disabled) [15:0] read-write LNK_LTSSM_LBPM_LFPS_TIMEOUT LTSSM LBPM LFPS Timeout (SuperSpeedPlus Only) 0x2A0 32 read-write 0x16E360 0xFFFFFF TIMEOUT24 LTSSM PollingPortMatch/Polling.PortConfig Timeout (default: 12 ms in 8ns) (0= Timer Disabled) [23:0] read-write LNK_COMPLIANCE_PATTERN_9_TO_12 Compliance Pattern CP9 to CP12 0x2A4 32 read-write 0x2 0x3FFFF DEEMPH_COEFF N/A [17:0] read-write LNK_COMPLIANCE_PATTERN_13 Compliance Pattern CP13 0x2A8 32 read-write 0x2 0x3FFFF DEEMPH_COEFF N/A [17:0] read-write LNK_COMPLIANCE_PATTERN_14 Compliance Pattern CP14 0x2AC 32 read-write 0x2 0x3FFFF DEEMPH_COEFF N/A [17:0] read-write LNK_COMPLIANCE_PATTERN_15 Compliance Pattern CP15 0x2B0 32 read-write 0x2 0x3FFFF DEEMPH_COEFF N/A [17:0] read-write LNK_COMPLIANCE_PATTERN_16 Compliance Pattern CP16 0x2B4 32 read-write 0x2 0x3FFFF DEEMPH_COEFF N/A [17:0] read-write 21 4 LNK_RX_TYPE1_HEADER_BUFFER[%s] Receive Type1 Packet Header Buffer 0x300 32 read-only 0x0 0xFFFFFFFF HEADER Rx Header Packet(SS)/Type1 Rx Header Packet(SSP) [31:0] read-only LNK_RX_TYPE1_HEADER_BUFFER_STATE_0 Receive Type1 Packet Header Buffer Status 0 0x380 32 read-only 0x0 0x3F3F3F3F SEQUENCE0 Packet Sequence Number [3:0] read-only VALID0 Packet Valid. Set on transmission of LGOOD_n, cleared on transmission of LCRD_x/LCRD1_x [4:4] read-only RCVD0 Packet Received. Set when packet received (good or bad), cleared on transmission of LCRD_x/LCRD1_x [5:5] read-only SEQUENCE1 Packet Sequence Number [11:8] read-only VALID1 Packet Valid. Set on transmission of LGOOD_n, cleared on transmission of LCRD_x/LCRD1_x [12:12] read-only RCVD1 Packet Received. Set when packet received (good or bad), cleared on transmission of LCRD_x/LCRD1_x [13:13] read-only SEQUENCE2 Packet Sequence Number [19:16] read-only VALID2 Packet Valid. Set on transmission of LGOOD_n, cleared on transmission of LCRD_x/LCRD1_x [20:20] read-only RCVD2 Packet Received. Set when packet received (good or bad), cleared on transmission of LCRD_x/LCRD1_x [21:21] read-only SEQUENCE3 Packet Sequence Number [27:24] read-only VALID3 Packet Valid. Set on transmission of LGOOD_n, cleared on transmission of LCRD_x/LCRD1_x [28:28] read-only RCVD3 Packet Received. Set when packet received (good or bad), cleared on transmission of LCRD_x/LCRD1_x [29:29] read-only LNK_RX_TYPE1_HEADER_BUFFER_STATE_1 Receive Type1 Packet Header Buffer Status 1 0x384 32 read-only 0x0 0x3F3F3F SEQUENCE4 Packet Sequence Number [3:0] read-only VALID4 Packet Valid. Set on transmission of LGOOD_n, cleared on transmission of LCRD_x/LCRD1_x [4:4] read-only RCVD4 Packet Received. Set when packet received (good or bad), cleared on transmission of LCRD_x/LCRD1_x [5:5] read-only SEQUENCE5 Packet Sequence Number [11:8] read-only VALID5 Packet Valid. Set on transmission of LGOOD_n, cleared on transmission of LCRD_x/LCRD1_x [12:12] read-only RCVD5 Packet Received. Set when packet received (good or bad), cleared on transmission of LCRD_x/LCRD1_x [13:13] read-only SEQUENCE6 Packet Sequence Number [19:16] read-only VALID6 Packet Valid. Set on transmission of LGOOD_n, cleared on transmission of LCRD_x/LCRD1_x [20:20] read-only RCVD6 Packet Received. Set when packet received (good or bad), cleared on transmission of LCRD_x/LCRD1_x [21:21] read-only 21 4 LNK_RX_TYPE2_HEADER_BUFFER[%s] Receive Type2 Packet Header Buffer 0x400 32 read-only 0x0 0xFFFFFFFF HEADER Type2 Rx Header Packet(SSP) [31:0] read-only LNK_RX_TYPE2_HEADER_BUFFER_STATE_0 Receive Type2 Packet Header Buffer Status 0 0x480 32 read-only 0x0 0x3F3F3F3F SEQUENCE0 Packet Sequence Number [3:0] read-only VALID0 Packet Valid. Set on transmission of LGOOD_n, cleared on transmission of LCRD2_x [4:4] read-only RCVD0 Packet Received. Set when packet received (good or bad), cleared on transmission of LCRD2_x [5:5] read-only SEQUENCE1 Packet Sequence Number [11:8] read-only VALID1 Packet Valid. Set on transmission of LGOOD_n, cleared on transmission of LCRD2_x [12:12] read-only RCVD1 Packet Received. Set when packet received (good or bad), cleared on transmission of LCRD2_x [13:13] read-only SEQUENCE2 Packet Sequence Number [19:16] read-only VALID2 Packet Valid. Set on transmission of LGOOD_n, cleared on transmission of LCRD2_x [20:20] read-only RCVD2 Packet Received. Set when packet received (good or bad), cleared on transmission of LCRD2_x [21:21] read-only SEQUENCE3 Packet Sequence Number [27:24] read-only VALID3 Packet Valid. Set on transmission of LGOOD_n, cleared on transmission of LCRD2_x [28:28] read-only RCVD3 Packet Received. Set when packet received (good or bad), cleared on transmission of LCRD2_x [29:29] read-only LNK_RX_TYPE2_HEADER_BUFFER_STATE_1 Receive Type2 Packet Header Buffer Status 1 0x484 32 read-only 0x0 0x3F3F3F SEQUENCE4 Packet Sequence Number [3:0] read-only VALID4 Packet Valid. Set on transmission of LGOOD_n, cleared on transmission of LCRD2_x [4:4] read-only RCVD4 Packet Received. Set when packet received (good or bad), cleared on transmission of LCRD2_x [5:5] read-only SEQUENCE5 Packet Sequence Number [11:8] read-only VALID5 Packet Valid. Set on transmission of LGOOD_n, cleared on transmission of LCRD2_x [12:12] read-only RCVD5 Packet Received. Set when packet received (good or bad), cleared on transmission of LCRD2_x [13:13] read-only SEQUENCE6 Packet Sequence Number [19:16] read-only VALID6 Packet Valid. Set on transmission of LGOOD_n, cleared on transmission of LCRD2_x [20:20] read-only RCVD6 Packet Received. Set when packet received (good or bad), cleared on transmission of LCRD2_x [21:21] read-only 21 4 LNK_TX_TYPE1_HEADER_BUFFER[%s] Transmit Type1 Packet Header Buffer 0x500 32 read-only 0x0 0xFFFFFFFF HEADER Tx Header Packet(SS)/Type1 Rx Header Packet(SSP) [31:0] read-only LNK_TX_TYPE1_HEADER_BUFFER_STATE_0 Transmit Type1 Packet Header Buffer Status 0 0x580 32 read-only 0x0 0x3F3F3F3F SEQUENCE0 Packet Sequence Number [3:0] read-only VALID0 Packet Valid. Set on receipt of buffer from Protocol Layer; cleared on receipt of LGOOD_n [4:4] read-only SENT0 Packet Sent. Set on receipt of buffer from Protocol Layer; cleared when sent out for first time [5:5] read-only SEQUENCE1 Packet Sequence Number [11:8] read-only VALID1 Packet Valid. Set on receipt of buffer from Protocol Layer; cleared on receipt of LGOOD_n [12:12] read-only SENT1 Packet Sent. Set on receipt of buffer from Protocol Layer; cleared when sent out for first time [13:13] read-only SEQUENCE2 Packet Sequence Number [19:16] read-only VALID2 Packet Valid. Set on receipt of buffer from Protocol Layer; cleared on receipt of LGOOD_n [20:20] read-only SENT2 Packet Sent. Set on receipt of buffer from Protocol Layer; cleared when sent out for first time [21:21] read-only SEQUENCE3 Packet Sequence Number [27:24] read-only VALID3 Packet Valid. Set on receipt of buffer from Protocol Layer; cleared on receipt of LGOOD_n [28:28] read-only SENT3 Packet Sent. Set on receipt of buffer from Protocol Layer; cleared when sent out for first time [29:29] read-only LNK_TX_TYPE1_HEADER_BUFFER_STATE_1 Transmit Type1 Packet Header Buffer Status 1 0x584 32 read-only 0x0 0xE03F3F3F SEQUENCE4 Packet Sequence Number [3:0] read-only VALID4 Packet Valid. Set on receipt of buffer from Protocol Layer; cleared on receipt of LGOOD_n [4:4] read-only SENT4 Packet Sent. Set on receipt of buffer from Protocol Layer; cleared when sent out for first time [5:5] read-only SEQUENCE5 Packet Sequence Number [11:8] read-only VALID5 Packet Valid. Set on receipt of buffer from Protocol Layer; cleared on receipt of LGOOD_n [12:12] read-only SENT5 Packet Sent. Set on receipt of buffer from Protocol Layer; cleared when sent out for first time [13:13] read-only SEQUENCE6 Packet Sequence Number [19:16] read-only VALID6 Packet Valid. Set on receipt of buffer from Protocol Layer; cleared on receipt of LGOOD_n [20:20] read-only SENT6 Packet Sent. Set on receipt of buffer from Protocol Layer; cleared when sent out for first time [21:21] read-only REMOTE_CREDITS Remote Rx (Type1) Header Buffer Credit Count. The number of free entries in the Link Partner's Receive Header Packet Buffer. [31:29] read-only 21 4 LNK_TX_TYPE2_HEADER_BUFFER[%s] Transmit Type2 Packet Header Buffer 0x600 32 read-only 0x0 0xFFFFFFFF HEADER Type2 Rx Header Packet(SSP) [31:0] read-only LNK_TX_TYPE2_HEADER_BUFFER_STATE_0 Transmit Type2 Packet Header Buffer Status 0 0x680 32 read-only 0x0 0x3F3F3F3F SEQUENCE0 Packet Sequence Number [3:0] read-only VALID0 Packet Valid. Set on receipt of buffer from Protocol Layer; cleared on receipt of LGOOD_n [4:4] read-only SENT0 Packet Sent. Set on receipt of buffer from Protocol Layer; cleared when sent out for first time [5:5] read-only SEQUENCE1 Packet Sequence Number [11:8] read-only VALID1 Packet Valid. Set on receipt of buffer from Protocol Layer; cleared on receipt of LGOOD_n [12:12] read-only SENT1 Packet Sent. Set on receipt of buffer from Protocol Layer; cleared when sent out for first time [13:13] read-only SEQUENCE2 Packet Sequence Number [19:16] read-only VALID2 Packet Valid. Set on receipt of buffer from Protocol Layer; cleared on receipt of LGOOD_n [20:20] read-only SENT2 Packet Sent. Set on receipt of buffer from Protocol Layer; cleared when sent out for first time [21:21] read-only SEQUENCE3 Packet Sequence Number [27:24] read-only VALID3 Packet Valid. Set on receipt of buffer from Protocol Layer; cleared on receipt of LGOOD_n [28:28] read-only SENT3 Packet Sent. Set on receipt of buffer from Protocol Layer; cleared when sent out for first time [29:29] read-only LNK_TX_TYPE2_HEADER_BUFFER_STATE_1 Transmit Type2 Packet Header Buffer Status 1 0x684 32 read-only 0x0 0xE03F3F3F SEQUENCE4 Packet Sequence Number [3:0] read-only VALID4 Packet Valid. Set on receipt of buffer from Protocol Layer; cleared on receipt of LGOOD_n [4:4] read-only SENT4 Packet Sent. Set on receipt of buffer from Protocol Layer; cleared when sent out for first time [5:5] read-only SEQUENCE5 Packet Sequence Number [11:8] read-only VALID5 Packet Valid. Set on receipt of buffer from Protocol Layer; cleared on receipt of LGOOD_n [12:12] read-only SENT5 Packet Sent. Set on receipt of buffer from Protocol Layer; cleared when sent out for first time [13:13] read-only SEQUENCE6 Packet Sequence Number [19:16] read-only VALID6 Packet Valid. Set on receipt of buffer from Protocol Layer; cleared on receipt of LGOOD_n [20:20] read-only SENT6 Packet Sent. Set on receipt of buffer from Protocol Layer; cleared when sent out for first time [21:21] read-only REMOTE_CREDITS Remote Rx Type2 Header Buffer Credit Count. The number of free entries in the Link Partner's Receive Header Packet Buffer. [31:29] read-only PROT USB32 SuperSpeedPlus Device Controller Protocol Layer Registers 0x00003000 PROT_CS Protocol Control and Status 0x0 32 read-write 0xC0E80000 0xFFFFFFFF DEVICEADDR During the USB enumeration process, the host sends a device a unique 7-bit address, which the USB core copies into this register. The USB Core will automatically respond only to its assigned address. During the USB RESET, this register will be cleared to zero. [6:0] read-only DISABLE_INGRS_SEQ_MATCH Disable the Ingress Sequence match detection [7:7] read-write DISABLE_EGRS_SEQ_MATCH Disable the egress Sequence match detection [8:8] read-write SPARE Spare [12:9] read-write EN_STATUS_CONTROL To control the respond to the HOST-STATUS token. [13:13] read-write STATUS_RESPONSE This is valid only for none Set_Address_Command. The Status phase of theSet_Address_Command is always ACKED. 0: NRDY is sent for the STATUS response If EN_STATUS_CONTROL is '1' and STATUS_CLR_BUSY is '1' before STATUS phase. 1: STALL is sent for the STATUS response If EN_STATUS_CONTROL is '1' and STATUS_CLR_BUSY is '0' before STATUS phase. [14:14] read-write STATUS_CLR_BUSY This is valid only for none Set_Address_Command. This register is used only when EN_STATUS_CONTROL is set. This register is used for control the status phase. This gets set by HW once a valid setup token is received. If this bit is not cleared before status phase, A NRDY/STALL(based on STATUS_RESPONSE) is issued when a STATUS token is received. If this bit is cleared before status phase, an ACK is issued when a STATUS token is received. If this bit is cleared after status phase, an ERDY is issued to the HOST to continue the STATUS phase. [15:15] read-write SETUP_CLR_BUSY Hardware set this bit to '1' once a valid Setup packet is detected. The 8-byte data port of the SETUP packet is in PROT_SETUPDAT0/PROT_SETUPDAT. This register bit used by Hardware to see if FW has finished processing the 8-bytes data. If this regsiter is NOT cleared by FW, HW will isssue NRDY for the data-phase if any. If this regsiter is cleared by FW, HW will response like other End-point transaction [16:16] read-write NRDY_ALL Set '1' to this bit, the HW will send NRDY all transfers from the host in all endpoint1-31. [17:17] read-write TP_THRESHOLD Ingress TP response transmit buffer threshold for almost full flag. When buffer contains TP_THRESHOLD items or more, controller will stop issuing credits to host. This field must be larger than 0. The transmit buffer can hold up to 64 responses. [23:18] read-write PROT_HOST_RESET_RESP This bit is used to infom the protocol of what the response to incoming TP/DPH should be after warm/host reset. This register will be used by Protocol until the LINK_INTR.LTSSM_RESET is cleared by CPU. 0: Issue NRDY 1: Ignore TP [24:24] read-write SEQ_NUM_CONFIG This bit indicates if the seq numbers are EP based or Stream ID(Socket) based 0: EP based 1: Stream ID(Socket) based [25:25] read-write DISABLE_IDLE_DET This bit will control the idle detection logic in the protocol. 0: Logic is not disabled. 1: Logic is disabled. [26:26] read-write MULT_TIMER This timer indicates how long protocol should wait for data (MULT is enabled) to be available by EPM before terminating a burst. Protocol will multiply the value programmed by 4. [31:27] read-write PROT_INTR Protocol Interrupts 0x4 32 read-write 0x0 0xFF7F LMP_RCV_EV A LMP was received and placed in PROT_LMP_PACKET_RX. The LMP may have been recognized and processed as well (leading to other interrupts in this register). [0:0] read-write LMP_UNKNOWN_EV An unkown LMP was received and placed in PROT_LMP_PACKET_RX. The LMP was not recognized and no response LMP was sent back. [1:1] read-write LMP_PORT_CAP_EV A Port Capabilities LMP was received. A response may have been sent automatically depending on settings for PROT_LMP_PORT_CAPABILITIES_TIMER. [2:2] read-write LMP_PORT_CFG_EV A Port Configuration LMP was received. A response may have been sent automatically depending on settings for PROT_LMP_PORT_CONFIGURATION_TIMER. [3:3] read-write TIMEOUT_PORT_CAP_EV The Port Capabilities LMP Timer expired [4:4] read-write TIMEOUT_PORT_CFG_EV The Port Configuraiton LMP Timer expired [5:5] read-write TIMEOUT_PING_EV The Ping Timer expired [6:6] read-write ITP_EV Set whenever a ITP(SOF) occurrs [8:8] read-write SUTOK_EV Set whenever a (valid of invalid) SETUP DPP is received that is not a set_address. The set_address DPP is handled entirely in hardware and does not require any firmware intervention. [9:9] read-write HOST_ERR_EV Set whenever an ACK TP is received with HE=1 [USB 3.0: section 8.5.1, Table 8-12, p 8-13] [10:10] read-write STATUS_STAGE Set when host completes Status Stage of a Control Transfer [11:11] read-write LMP_INVALID_PORT_CAP_EV Set whenever a LMP port capability is received but the Link Speed is not '1' or Num HP buffer is not '4' or bit zero of the Direction is not '1'. [12:12] read-write LMP_INVALID_PORT_CFG_EV Set whenever a LMP port configuration is received but the Link Speed is not '1'. [13:13] read-write EP0_STALLED_EV Device sets this interrupt based on the following conditions: 1: When Host sends more data than it is suppose to in ingress. 2: When Device sends more data that it suppose to in egress. 3: During STATUS Stage, host sends/asks to/for data from device. Device will come out of stall condition when it receives a valid SETUP(SUTOK_EV interrupt will be generated). [14:14] read-write SET_ADDR0_EV Device sets this interrupt when it receives a set address 0 command. [15:15] read-write PROT_INTR_SET Protocol Interrupts Set 0x8 32 read-write 0x0 0xFF7F LMP_RCV_EV Write with '1' to set corresponding bit in interrupt request register. [0:0] read-write LMP_UNKNOWN_EV Write with '1' to set corresponding bit in interrupt request register. [1:1] read-write LMP_PORT_CAP_EV Write with '1' to set corresponding bit in interrupt request register. [2:2] read-write LMP_PORT_CFG_EV Write with '1' to set corresponding bit in interrupt request register. [3:3] read-write TIMEOUT_PORT_CAP_EV Write with '1' to set corresponding bit in interrupt request register. [4:4] read-write TIMEOUT_PORT_CFG_EV Write with '1' to set corresponding bit in interrupt request register. [5:5] read-write TIMEOUT_PING_EV Write with '1' to set corresponding bit in interrupt request register. [6:6] read-write ITP_EV Write with '1' to set corresponding bit in interrupt request register. [8:8] read-write SUTOK_EV Write with '1' to set corresponding bit in interrupt request register. [9:9] read-write HOST_ERR_EV Write with '1' to set corresponding bit in interrupt request register. [10:10] read-write STATUS_STAGE Write with '1' to set corresponding bit in interrupt request register. [11:11] read-write LMP_INVALID_PORT_CAP_EV Write with '1' to set corresponding bit in interrupt request register. [12:12] read-write LMP_INVALID_PORT_CFG_EV Write with '1' to set corresponding bit in interrupt request register. [13:13] read-write EP0_STALLED_EV Write with '1' to set corresponding bit in interrupt request register. [14:14] read-write SET_ADDR0_EV Write with '1' to set corresponding bit in interrupt request register. [15:15] read-write PROT_INTR_MASK Protocol Interrupts Mask 0xC 32 read-write 0x0 0xFF7F LMP_RCV_MASK Mask bit for corresponding bit in interrupt request register. [0:0] read-write LMP_UNKNOWN_MASK Mask bit for corresponding bit in interrupt request register. [1:1] read-write LMP_PORT_CAP_MASK Mask bit for corresponding bit in interrupt request register. [2:2] read-write LMP_PORT_CFG_MASK Mask bit for corresponding bit in interrupt request register. [3:3] read-write TIMEOUT_PORT_CAP_MASK Mask bit for corresponding bit in interrupt request register. [4:4] read-write TIMEOUT_PORT_CFG_MASK Mask bit for corresponding bit in interrupt request register. [5:5] read-write TIMEOUT_PING_MASK Mask bit for corresponding bit in interrupt request register. [6:6] read-write ITP_MASK Mask bit for corresponding bit in interrupt request register. [8:8] read-write SUTOK_MASK Mask bit for corresponding bit in interrupt request register. [9:9] read-write HOST_ERR_MASK Mask bit for corresponding bit in interrupt request register. [10:10] read-write STATUS_STAGE_MASK Mask bit for corresponding bit in interrupt request register. [11:11] read-write LMP_INVALID_PORT_CAP_MASK Mask bit for corresponding bit in interrupt request register. [12:12] read-write LMP_INVALID_PORT_CFG_MASK Mask bit for corresponding bit in interrupt request register. [13:13] read-write EP0_STALLED_MASK Mask bit for corresponding bit in interrupt request register. [14:14] read-write SET_ADDR0_MASK Mask bit for corresponding bit in interrupt request register. [15:15] read-write PROT_INTR_MASKED Protocol Interrupts Masked 0x10 32 read-only 0x0 0xFF7F LMP_RCV_MASKED Logical and of corresponding request and mask bits. [0:0] read-only LMP_UNKNOWN_MASKED Logical and of corresponding request and mask bits. [1:1] read-only LMP_PORT_CAP_MASKED Logical and of corresponding request and mask bits. [2:2] read-only LMP_PORT_CFG_MASKED Logical and of corresponding request and mask bits. [3:3] read-only TIMEOUT_PORT_CAP_MASKED Logical and of corresponding request and mask bits. [4:4] read-only TIMEOUT_PORT_CFG_MASKED Logical and of corresponding request and mask bits. [5:5] read-only TIMEOUT_PING_MASKED Logical and of corresponding request and mask bits. [6:6] read-only ITP_MASKED Logical and of corresponding request and mask bits. [8:8] read-only SUTOK_MASKED Logical and of corresponding request and mask bits. [9:9] read-only HOST_ERR_MASKED Logical and of corresponding request and mask bits. [10:10] read-only STATUS_STAGE_MASKED Logical and of corresponding request and mask bits. [11:11] read-only LMP_INVALID_PORT_CAP_MASKED Logical and of corresponding request and mask bits. [12:12] read-only LMP_INVALID_PORT_CFG_MASKED Logical and of corresponding request and mask bits. [13:13] read-only EP0_STALLED_MASKED Logical and of corresponding request and mask bits. [14:14] read-only SET_ADDR0_MASKED Logical and of corresponding request and mask bits. [15:15] read-only PROT_EP_INTR Endpoint Interrupts 0x14 32 read-write 0x0 0xFFFFFFFF EP_IN Bit <x> indicates an interrupt from EPI_CS[x] [15:0] read-write EP_OUT Bit <16+x> indicates an interrupt from EPO_CS[x] [31:16] read-write PROT_EP_INTR_SET Endpoint Interrupts set 0x18 32 read-write 0x0 0xFFFFFFFF EP_IN Write with '1' to set corresponding bit in interrupt request register. [15:0] read-write EP_OUT Write with '1' to set corresponding bit in interrupt request register. [31:16] read-write PROT_EP_INTR_MASK Endpoint Interrupts Mask 0x1C 32 read-write 0x0 0xFFFFFFFF EP_IN_MASK Bit <x> masks any interrupt from EPI_CS[x] [15:0] read-write EP_OUT_MASK Bit <16+x> masks any interrupt from EPO_CS[x] [31:16] read-write PROT_EP_INTR_MASKED Endpoint Interrupts Masked 0x20 32 read-only 0x0 0xFFFFFFFF EP_IN_MASKED Logical and of corresponding request and mask bits. [15:0] read-only EP_OUT_MASKED Logical and of corresponding request and mask bits. [31:16] read-only PROT_DEVICE_NOTIF_FUNC_WAKE Device Notification Remote Wake up TP 0x24 32 read-write 0x0 0x800000FF INTERFACE Interface. This field identifies the first interface in the function that caused the device to perform a remote wake operation. [7:0] read-write REQUEST Firmware writes 1 to enable it and hardware clears this bit after device notification TP service request has been completed [31:31] read-write PROT_DEVICE_NOTIF_LTM Device Notification Latency Tolerance Message TP 0x28 32 read-write 0xC00 0x80000FFF BELT_LATENCY BELT. This field describes the Best Effort Latency Tolerance value, representing the time in nanoseconds that a device can wait for service before experiencing unintended operational side effects. [9:0]: LatencyValue in nano-seconds (ns) [9:0] read-write BELT_SCALE N/A [11:10] read-write REQUEST Firmware writes 1 to enable it and hardware clears this bit after servicing the request [31:31] read-write PROT_DEVICE_NOTIF_BIAM Device Notification Bus Interval Adjustment TP 0x2C 32 read-write 0x0 0x8000FFFF BIA Bus Interval Adjustment. This field is a two's complement value ranging from -32768 to +32767 expressed in BusIntervalAdjustmentGranularity units. [15:0] read-write REQUEST Firmware writes 1 to enable it and hardware clears this bit after servicing the request [31:31] read-write PROT_LMP_PORT_CAPABILITY_TIMER Port Capabilites LMP Timeout Configuration 0x30 32 read-write 0x9C4 0xFFFFFFFF RX_TIMEOUT Maximum time after a successful warm reset or a power on reset that the device should wait for port capability LMP on its RX link. Default is 20us (2500 cycles using 125 mhz clock) [14:0] read-write RX_DISABLE Disables the protocol layer to wait for port capabilities LMP [15:15] read-write TX_TIMEOUT This for TX lane, device should send port capability within 20us of link initialization done. Firmware can load a timer and ask device to wait for that much time before sending port Capability LMP [30:16] read-write TX_DISABLE Disables the protocol layer to send port capabilities LMP [31:31] read-write PROT_LMP_PORT_CONFIGURATION_TIMER Port Configuration LMP Timeout Configuration 0x34 32 read-write 0x9C4 0xFFFFFFFF RX_TIMEOUT Maximum time after a successful warm reset or a power on reset that the link partners should send the port configuration LMP. Default is 20us (2500 cycles using 125 mhz clock) [14:0] read-write RX_DISABLE Disables the protocol layer to wait for port configuration LMP [15:15] read-write TX_TIMEOUT Maximum time device protocol layer will wait after receiving Port Configuration LMP. [30:16] read-write TX_DISABLE Disables the protocol layer to send Port configuration response LMP [31:31] read-write PROT_PING_TIMEOUT Ping Timeout Configuration 0x38 32 read-write 0x7A12 0x80FFFFFF PING_TIMEOUT Timeout after a device receives a ping from the host and when it can initiate U1 or U2. This parameter is measured in terms of the maximum of all the service intervals for all isochronous endpoints within the device. Default is 2 service intervals (1 service interval = 1 bus interval in this case) Default we are taking 250 us = 31250 clock cycles of 125Mhz) [23:0] read-write PING_DISABLE Directs the protocol layer to disable ping timer [31:31] read-write PROT_FRAMECNT Frame Counter Register 0x44 32 read-only 0x0 0x7FFFFFF SS_MICROFRAME MICROFRAME counter which indicates which of the 8 125-microsecond micro-frames last occurred... This is based on ITPs recieved from Host [13:0] read-only DELTA The delta value in the last ITP received [26:14] read-only PROT_BIAC Bus Interval Adjustment Addres 0x48 32 read-only 0x0 0x7F BIAC Bus Interval Adjustment control: This field specifies the address of the device that controls the bus interval adjustment mechanism. Upon reset, power-up, or if the device is disconnected, the host shall set this field to zero. [6:0] read-only PROT_ITP_TIME ITP Time Free Running Counter 0x4C 32 read-only 0x0 0xFFFFFF COUNTER24 Current counter value. [23:0] read-only PROT_ITP_TIMESTAMP ITP Time Stamp Register 0x50 32 read-only 0x0 0xFFFFFFFF TIMESTAMP Timestamp from a free running counter at 125MHz of the last ITP reception. [23:0] read-only MICROFRAME_LSB LSBs of MICROFRAME field of ITP when timestamp was taken. [31:24] read-only PROT_SETUPDAT0 Received SETUP Packet Data 0x54 32 read-only 0x0 0xFFFFFFFF SETUP_REQUEST_TYPE Setup data field [7:0] read-only SETUP_REQUEST Setup data field [15:8] read-only SETUP_VALUE Setup data field [31:16] read-only PROT_SETUPDAT1 Received SETUP Packet Data 0x58 32 read-only 0x0 0xFFFFFFFF SETUP_INDEX Setup data field [15:0] read-only SETUP_LENGTH Setup data field [31:16] read-only PROT_SEQ_NUM Sequence Number 0x5C 32 read-write 0x80000000 0xC01F1F1F ENDPOINT Endpoint Number [3:0] read-write DIR 0: OUT 1: IN [4:4] read-write SEQUENCE_NUMBER Packet sequence number of next packet to receive/transmit. Set by hardware if COMMAND=0, set by software when COMMAND=1. [12:8] read-write LAST_COMMITTED Sequence number of last packet that was transmitted (can be higher than SEQUENCE NUMBER). Returned as part of a read operation. [20:16] read-only COMMAND 0: Read 1: Write [30:30] read-write SEQ_VALID Set by hardware when read/write operation has completed. Must be cleared by software to initiate a read/write operation. [31:31] read-write PROT_LMP_RECEIVED Link Management Packet Received Value 0x80 32 read-only 0x0 0x1FF U2_INACTIVITY_TIMEOUT U2 Inactivity Timeout Value [7:0] read-only FORCE_LINKPM_ACCEPT Force Link to accept LGO_Ux Link Commands [8:8] read-only PROT_LMP_OVERRIDE Link Management Packet Override Values 0x84 32 read-write 0x0 0xE00001FF U2_INACTIVITY_TIMEOUT U2 Inactivity Timeout Value [7:0] read-write FORCE_LINKPM_ACCEPT Force Link to accept LGO_Ux Link Commands [8:8] read-write INACITIVITY_TIMEOUT_OVR Enable U2 Inactivity Timeout Setting Override [29:29] read-write LINKPM_ACCEPT_OVR Enable Force_LINKPM_Accept Setting Override [30:30] read-write LMP_SEND Initiates sending of the Port Configuration Response LMP [31:31] read-write PROT_LMP_PORT_CAPABILITIES_RX Port Capabilities LMP Received 0x88 32 read-only 0x0 0x1FFFFF LINK_SPEED The Link Speed supported by device [6:0] read-only NUM_HP_BUFFERS This field specifies the number of header packet buffers (in each direction Transmit or Receive) this device supports. [14:7] read-only DIRECTION This field is used to identify the upstream or downstream capabilities of the port [16:15] read-only TIEBREAKER This field is used to determine the port type when two devices with both upstream and downstream capability are connected to each other [20:17] read-only PROT_LMP_PORT_CAPABILITIES_TX Port Capabilities LMP Transmitted 0x8C 32 read-write 0x10201 0x801FFFFF LINK_SPEED Only used for Gen1x1. HW will use this only for Gen1x1 for others HW send a value '0'. The Link Speed supported by device [6:0] read-write NUM_HP_BUFFERS Only used for Gen1x1. HW will use this only for Gen1x1 for others HW send a value '0'. This field specifies the number of header packet buffers (in each direction Transmit or Receive) this device supports. [14:7] read-write DIRECTION This field is used to identify the upstream or downstream capabilities of the port [16:15] read-write TIEBREAKER This field is used to determine the port type when two devices with both upstream and downstream capability are connected to each other [20:17] read-write LMP_SEND Initiates sending of the Port Configuration Response LMP [31:31] read-write PROT_LMP_PORT_CONFIGURATION_RX Port Configuration LMP Received 0x90 32 read-only 0x0 0x7F LINK_SPEED This field describes the link speed at which the upstream port shall operate. [6:0] read-only PROT_LMP_PORT_CONFIGURATION_TX Port Configuration Response LMP 0x94 32 read-write 0x1 0x8000007F LINK_SPEED This field indicates the settings that were accepted in the Port Configuration LMP that was sent to a device. [6:0] read-write LMP_SEND Initiates sending of the Port Configuration Response LMP [31:31] read-write PROT_STREAM_ERROR_DISABLE Streams Error Disable Type Registers 0x98 32 read-write 0x0 0x3F TYPE This register controls the type of Stream Error that would cause the ERROR_DETECTED bit in the PROT_STREAM_ERROR_STATUS register to bet set. Setting any bit will disable an specific error type. [0]: Stream ID changed while in MOVE DATA stage. [1]: ACK/DP PRIMEP PP is '1' [2]: ACK/DP NoStream PP is '1' [3]: ACK PRIME NumP is '0' [4]: ACK NoStream NumP is NOT '0' [5:0] read-write PROT_STREAM_ERROR_STATUS Streams Error STATUS Registers 0x9C 32 read-write 0x0 0xBFFFFFFF ID The stream id when the error occurred. [15:0] read-only EP_NUM The End Point number when the error occurred. [19:16] read-only EP_IO 1: IN EP, 0: OUT EP [20:20] read-only ERROR_TYPE The type of the stream error that was detected. [1]: Stream ID changed while in MOVE DATA stage. [2]: ACK/DP PRIMEP PP is '1' [3]: ACK/DP NoStream PP is '1' [4]: ACK PRIME NumP is '0' [5]: ACK NoStream NumP is NOT '0' [26:21] read-only ERROR_STATE The stream state when the error occurred. 1: Disabled 2: Prime Pipe 3: DFR Prime Pipe 4: Idle 5: Start Stream 6: Move Data 7: End [29:27] read-only ERROR_DETECTED An Stream Error was detected. [31:31] read-write 3 4 PROT_LMP_PACKET_RX[%s] Link Management Packet Received 0x100 32 read-only 0x0 0xFFFFFFFF RX_LMP_PACKET Link Management Packet [31:0] read-only 3 4 PROT_LMP_PACKET_TX[%s] Link Management Packet to be sent 0x110 32 read-write 0x0 0xFFFFFFFF TX_LMP_PACKET Link Management Packet [31:0] read-write 16 4 PROT_EPI_INTR[%s] Per IN-Endpoint Interrupt 0x140 32 read-write 0x0 0x7FF COMMIT Set whenever an IN token was ACKed by the host. [0:0] read-write RETRY Whenever the USB3.0 does a retry it will asserts this interrupt. [1:1] read-write FLOWCONTROL EP in flow control due to EPM not being available. [2:2] read-write STREAMNRDY Nrdy was sent for a bulk stream request because of EP-stream not present in the mapper. [3:3] read-write ZERO Indicates a zero length packet was returned to the host in an IN transaction. Must be cleared by s/w. [4:4] read-write SHORT Indicates a shorter-than-maxsize packet was received, but UIB_EPI_XFER_CNT did not reach 0). [5:5] read-write OOSERR Out Of Sequence Error. Anytime an ACK is received with unexpected sequence number request, the ACK will be dropped and intr will be raised [6:6] read-write HBTERM The Burst Was terminated by the host. [7:7] read-write DBTERM The Burst was terminated by the device when the MULT_TIMER expires. [8:8] read-write STREAM_ERROR Stream Error occurred. [9:9] read-write FIRST_ACK_NUMP_0 The NumP for the first ACK is zero. [10:10] read-write 16 4 PROT_EPI_INTR_SET[%s] Per IN-Endpoint Interrupt set 0x180 32 read-write 0x0 0x7FF COMMIT Write with '1' to set corresponding bit in interrupt request register. [0:0] read-write RETRY Write with '1' to set corresponding bit in interrupt request register. [1:1] read-write FLOWCONTROL Write with '1' to set corresponding bit in interrupt request register. [2:2] read-write STREAMNRDY Write with '1' to set corresponding bit in interrupt request register. [3:3] read-write ZERO Write with '1' to set corresponding bit in interrupt request register. [4:4] read-write SHORT Write with '1' to set corresponding bit in interrupt request register. [5:5] read-write OOSERR Write with '1' to set corresponding bit in interrupt request register. [6:6] read-write HBTERM Write with '1' to set corresponding bit in interrupt request register. [7:7] read-write DBTERM Write with '1' to set corresponding bit in interrupt request register. [8:8] read-write STREAM_ERROR Write with '1' to set corresponding bit in interrupt request register. [9:9] read-write FIRST_ACK_NUMP_0 Write with '1' to set corresponding bit in interrupt request register. [10:10] read-write 16 4 PROT_EPI_INTR_MASK[%s] Per IN-Endpoint Interrupt Mask 0x1C0 32 read-write 0x0 0x7FF COMMIT_MASK Mask bit for corresponding bit in interrupt request register. [0:0] read-write RETRY_MASK Mask bit for corresponding bit in interrupt request register. [1:1] read-write FLOWCONTROL_MASK Mask bit for corresponding bit in interrupt request register. [2:2] read-write STREAMNRDY_MASK Mask bit for corresponding bit in interrupt request register. [3:3] read-write ZERO_MASK Mask bit for corresponding bit in interrupt request register. [4:4] read-write SHORT_MASK Mask bit for corresponding bit in interrupt request register. [5:5] read-write OOSERR_MASK Mask bit for corresponding bit in interrupt request register. [6:6] read-write HBTERM_MASK Mask bit for corresponding bit in interrupt request register. [7:7] read-write DBTERM_MASK Mask bit for corresponding bit in interrupt request register. [8:8] read-write STREAM_ERROR_MASK Mask bit for corresponding bit in interrupt request register. [9:9] read-write FIRST_ACK_NUMP_0_MASK Mask bit for corresponding bit in interrupt request register. [10:10] read-write 16 4 PROT_EPI_INTR_MASKED[%s] Per IN-Endpoint Interrupt Masked 0x200 32 read-only 0x0 0x7FF COMMIT_MASKED Logical and of corresponding request and mask bits. [0:0] read-only RETRY_MASKED Logical and of corresponding request and mask bits. [1:1] read-only FLOWCONTROL_MASKED Logical and of corresponding request and mask bits. [2:2] read-only STREAMNRDY_MASKED Logical and of corresponding request and mask bits. [3:3] read-only ZERO_MASKED Logical and of corresponding request and mask bits. [4:4] read-only SHORT_MASKED Logical and of corresponding request and mask bits. [5:5] read-only OOSERR_MASKED Logical and of corresponding request and mask bits. [6:6] read-only HBTERM_MASKED Logical and of corresponding request and mask bits. [7:7] read-only DBTERM_MASKED Logical and of corresponding request and mask bits. [8:8] read-only STREAM_ERROR_MASKED Logical and of corresponding request and mask bits. [9:9] read-only FIRST_ACK_NUMP_0_MASKED Logical and of corresponding request and mask bits. [10:10] read-only 16 4 PROT_EPI_CS1[%s] SuperSpeed IN Endpoint Control and Status 0x240 32 read-write 0x20 0x8000003F VALID Set VALID=1 to activate an endpoint, and VALID=0 to de-activate it. All USB endpoints default to invalid. An endpoint whose VALID bit is 0 does not respond to any USB traffic. [0:0] read-write NRDY Setting this bit causes NRDY on IN transactions. [1:1] read-write STALL Set this bit to '1' to stall an endpoint, and to '0' to clear a stall. [2:2] read-write STREAM_EN Enables bulk stream protocol handling for this EP [3:3] read-write EP_RESET Per End Point Reset. [4:4] read-write STREAM_ERROR_STALL_EN Issue STALL whenever Stream error occurs. [5:5] read-write DISABLE_EOB_ON_SHORT 0: EOB is '1' for short packet 1: EOB is '0' for short packet [31:31] read-write 16 4 PROT_EPI_CS2[%s] SuperSpeed IN Endpoint Control and Status 0x280 32 read-write 0x40 0x1FFFF EPI_TYPE Endpoint type (EP0 suports CONTROL only) 0: ISO 1: INT 2: BULK 3: CONTROL (only valid for EP0) [1:0] read-write ISOINPKS Number of packets to be sent per service interval . Maximum can be 48 ( Max burst size* Mult field) [7:2] read-write MAXBURST Maximum number of packets the endpoint can send. (truncated to 4b, 0 means 16) [11:8] read-write BTERM_NUMP Number of packets that need to be cleaned up by CPU whenever there is a BTERM interrupt. [16:12] read-only 16 4 PROT_EPI_UNMAPPED_STREAM[%s] Unmapped Stream Request 0x2C0 32 read-only 0x0 0xFFFFF STREAM_ID The StreamID of the current stream activated (or requested to be activated) by the protocol layer. [15:0] read-only SPSM_STATE Stream Protocol State Machine (SPSM) State for this EndPoint: 0: Not Configured 1: Disabled 2: Prime Pipe 3: DFR Prime Pipe 4: Idle 5: Start Stream 6: Move Data 7: End 8: Error [19:16] read-only 16 4 PROT_EPI_MAPPED_STREAM[%s] Mapped Streams Registers 0x300 32 read-write 0x0 0xE00FFFFF STREAM_ID The StreamID of the stream connected to the corresponding socket by firmware. [15:0] read-write EP_NUMBER The Endpoint number of the stream connected to the corresponding socket by firmware. [19:16] read-write UNMAPPED Stream is unmapped (not in use by the corresponding EP's SPSM). [29:29] read-only UNMAP Request to unmap this stream. May be cleared to revert/withdaw request. [30:30] read-write ENABLE Set by firmware if a stream is mapped to the corresponding socket. If this bit is set, the endpoint number corresponding to this socket number can no longer be used in non-streaming mode (that would create a conflict of two endpoints wanting to use the same socket). [31:31] read-write 16 4 PROT_EPO_INTR[%s] Per OUT-Endpoint Interrupt 0x340 32 read-write 0x0 0x7FF COMMIT Set whenever an OUT DATA was commited into the EPM. [0:0] read-write RETRY Whenever the USB3.0 device does a retry it will asserts this interrupt. [1:1] read-write FLOWCONTROL EP in flow control due to EPM not being available. [2:2] read-write STREAMNRDY Nrdy was sent for a bulk stream request because of EP-stream not present in the mapper. [3:3] read-write ZERO Indicates a zero length packet was received by the device in an OUT transaction. Must be cleared by s/w. [4:4] read-write SHORT Indicates a shorter-than-maxsize packet was received. [5:5] read-write OOSERR Out Of Sequence Error. Anytime an OUT-DATA is received with unexpected sequence number request, the data will be dropped and intr will be raised [6:6] read-write HBTERM The Burst Was terminated by the host. [7:7] read-write DBTERM The Burst was terminated by the device when the MULT_TIMER expires. [8:8] read-write STREAM_ERROR Stream Error occurred. [9:9] read-write FIRST_ACK_NUMP_0 The NumP for the first ACK is zero. [10:10] read-write 16 4 PROT_EPO_INTR_SET[%s] Per OUT-Endpoint Interrupt set 0x380 32 read-write 0x0 0x7FF COMMIT Write with '1' to set corresponding bit in interrupt request register. [0:0] read-write RETRY Write with '1' to set corresponding bit in interrupt request register. [1:1] read-write FLOWCONTROL Write with '1' to set corresponding bit in interrupt request register. [2:2] read-write STREAMNRDY Write with '1' to set corresponding bit in interrupt request register. [3:3] read-write ZERO Write with '1' to set corresponding bit in interrupt request register. [4:4] read-write SHORT Write with '1' to set corresponding bit in interrupt request register. [5:5] read-write OOSERR Write with '1' to set corresponding bit in interrupt request register. [6:6] read-write HBTERM Write with '1' to set corresponding bit in interrupt request register. [7:7] read-write DBTERM Write with '1' to set corresponding bit in interrupt request register. [8:8] read-write STREAM_ERROR Write with '1' to set corresponding bit in interrupt request register. [9:9] read-write FIRST_ACK_NUMP_0 Write with '1' to set corresponding bit in interrupt request register. [10:10] read-write 16 4 PROT_EPO_INTR_MASK[%s] Per OUT-Endpoint Interrupt Mask 0x3C0 32 read-write 0x0 0x7FF COMMIT_MASK Mask bit for corresponding bit in interrupt request register. [0:0] read-write RETRY_MASK Mask bit for corresponding bit in interrupt request register. [1:1] read-write FLOWCONTROL_MASK Mask bit for corresponding bit in interrupt request register. [2:2] read-write STREAMNRDY_MASK Mask bit for corresponding bit in interrupt request register. [3:3] read-write ZERO_MASK Mask bit for corresponding bit in interrupt request register. [4:4] read-write SHORT_MASK Mask bit for corresponding bit in interrupt request register. [5:5] read-write OOSERR_MASK Mask bit for corresponding bit in interrupt request register. [6:6] read-write HBTERM_MASK Mask bit for corresponding bit in interrupt request register. [7:7] read-write DBTERM_MASK Mask bit for corresponding bit in interrupt request register. [8:8] read-write STREAM_ERROR_MASK Mask bit for corresponding bit in interrupt request register. [9:9] read-write FIRST_ACK_NUMP_0_MASK Mask bit for corresponding bit in interrupt request register. [10:10] read-write 16 4 PROT_EPO_INTR_MASKED[%s] Per OUT-Endpoint Interrupt Masked 0x400 32 read-only 0x0 0x7FF COMMIT_MASKED Mask bit for corresponding bit in interrupt request register. [0:0] read-only RETRY_MASKED Mask bit for corresponding bit in interrupt request register. [1:1] read-only FLOWCONTROL_MASKED Mask bit for corresponding bit in interrupt request register. [2:2] read-only STREAMNRDY_MASKED Mask bit for corresponding bit in interrupt request register. [3:3] read-only ZERO_MASKED Mask bit for corresponding bit in interrupt request register. [4:4] read-only SHORT_MASKED Mask bit for corresponding bit in interrupt request register. [5:5] read-only OOSERR_MASKED Mask bit for corresponding bit in interrupt request register. [6:6] read-only HBTERM_MASKED Mask bit for corresponding bit in interrupt request register. [7:7] read-only DBTERM_MASKED Mask bit for corresponding bit in interrupt request register. [8:8] read-only STREAM_ERROR_MASKED Mask bit for corresponding bit in interrupt request register. [9:9] read-only FIRST_ACK_NUMP_0_MASKED Mask bit for corresponding bit in interrupt request register. [10:10] read-only 16 4 PROT_EPO_CS1[%s] SuperSpeed OUT Endpoint Control and Status 0x440 32 read-write 0x20 0x3F VALID Set VALID=1 to activate an endpoint, and VALID=0 to de-activate it. All USB endpoints default to invalid. An endpoint whose VALID bit is 0 does not respond to any USB traffic. [0:0] read-write NRDY Setting this bit causes NRDY on IN transactions. [1:1] read-write STALL Set this bit to '1' to stall an endpoint, and to '0' to clear a stall. [2:2] read-write STREAM_EN Enables bulk stream protocol handling for this EP [3:3] read-write EP_RESET Per End Point Reset. [4:4] read-write STREAM_ERROR_STALL_EN Issue STALL whenever Stream error occurs. [5:5] read-write 16 4 PROT_EPO_CS2[%s] SuperSpeed IN Endpoint Control and Status 0x480 32 read-write 0x40 0xFFF EPO_TYPE Endpoint type (EP0 suports CONTROL only) 0: ISO 1: INT 2: BULK 3: CONTROL (only valid for EP0) [1:0] read-write ISOINPKS Number of packets to be sent per service interval . Maximum can be 48 ( Max burst size* Mult field) [7:2] read-write MAXBURST Maximum number of packets the endpoint can receive (truncated to 4b, 0 means 16) [11:8] read-write 16 4 PROT_EPO_UNMAPPED_STREAM[%s] Unmapped Stream Request 0x4C0 32 read-only 0x0 0xFFFFF STREAM_ID The StreamID of the current stream activated (or requested to be activated) by the protocol layer. [15:0] read-only SPSM_STATE Stream Protocol State Machine (SPSM) State for this EndPoint: 0: Not Configured 1: Disabled 2: Prime Pipe 3: DFR Prime Pipe 4: Idle 5: Start Stream 6: Move Data 7: End 8: Error [19:16] read-only 16 4 PROT_EPO_MAPPED_STREAM[%s] Mapped Streams Registers 0x500 32 read-write 0x0 0xE00FFFFF STREAM_ID The StreamID of the stream connected to the corresponding socket by firmware. [15:0] read-write EP_NUMBER The Endpoint number of the stream connected to the corresponding socket by firmware. [19:16] read-write UNMAPPED Stream is unmapped (not in use by the corresponding EP's SPSM). [29:29] read-only UNMAP Request to unmap this stream. May be cleared to revert/withdaw request. [30:30] read-write ENABLE Set by firmware if a stream is mapped to the corresponding socket. If this bit is set, the endpoint number corresponding to this socket number can no longer be used in non-streaming mode (that would create a conflict of two endpoints wanting to use the same socket). [31:31] read-write 16 4 PROT_EPI_ARB_PKT[%s] Per IN-Endpoint # of packets per arbitration grant 0x540 32 read-write 0x1 0x1F NUM_PKT_PER_ARB The number of packets that can be sent for every arbitation grant for each EP [4:0] read-write PHYSS USB32 SuperSpeedPlus Physical Layer Registers 0x00004000 2 4096 USB40PHY[%s] PHY Registers 0x00000000 USB40PHY PHY TOP, PCS, Tx registers 0x00000000 USB40PHY_VERSION_CORE USB40PHY Version core register 0x0 32 read-only 0x11100000 0xFFF00FFF REG_VERSION_AFE_PLL_SYS USB40PHY PLL Soft_IP Version [3:0] read-only REG_VERSION_AFE_RX USB40PHY Rx Soft_IP Version [7:4] read-only REG_VERSION_AFE_TX USB40PHY Tx Soft_IP Version [11:8] read-only REG_VERSION_PCS USB40PHY Core Version [23:20] read-only REG_VERSION_TX_DIGITAL_SERIALIZER USB40PHY Core Version [27:24] read-only REG_VERSION_CORE USB40PHY Core Version [31:28] read-only TOP_CTRL_0 TOP control register 0x4 32 read-write 0x20 0x7F REG_PIPE_MODE PIPE mode selection 0: PIPE 4.4.1 1: PIPE 5 for SerDes architecture [0:0] read-write REG_PWR_GOOD_CORE_RX Power Good Rx [1:1] read-write REG_PWR_GOOD_CORE_PLL Power Good PLL [2:2] read-write REG_VBUS VBUS indication register. It connects to PowerPresent on PIPE [3:3] read-write REG_PLL_RSTB PLL reset [4:4] read-write REG_LFPS_CLK_DIV LFPS clock divide nunber 0: 100/(1+1) = 50MHz 1: 100/(3+1) = 25MHz 2: 100/(5+1) = 16MHz 3: 100/(9+1) = 10MHz [6:5] read-write TOP_STATUS_0 TOP status register 0xC 32 read-only 0x0 0x3 REG_TOP_RATE_CHANGE_DONE Rate change configuration is done [0:0] read-only REG_TOP_STATUS_TBD2 TBD [1:1] read-only PCS_CTRL_0 PCS control register 0x10 32 read-write 0x22 0x73 REG_SEL_BIT_MODE Data bitwidth mode selection (Not used. Replaced to the 'reg_pipe_rate_ovrd') 0: 16bit 1: 20bit, Gen1(5Gbps), (8b/10b), 125MHz PCLK, 250MHz PCS PCLK(internal) 2: 32bit, Gen2(10Gbps), (128b/132b), 312.5MHz PCLK 3: 40bit [1:0] read-write REG_ONEZERO_CNT USB 3.1 CP7/CP8 one_zero number selection (1clk = 40bit) 0: 2clk -> one*80, zero*80 1: 3clk -> one*120, zero*120 2: 4clk -> one*160, zero*160 3: 5clk -> one*200, zero*200 4: 6clk -> one*240, zero*240 [6:4] read-write PCS_STATUS PCS status register 0x18 32 read-only 0x0 0x3 REG_PCS_STATUS TBD [1:0] read-only PCS_SPARE PCS spare 0x1C 32 read-write 0xFF000000 0xFFFFFFFF REG_DFT Spare [11:0] read-write REG_SPARE0 Spare with default 0 [23:12] read-write REG_SPARE1 Spare with default 1 [31:24] read-write PIPE_OVERRIDE_0 PIPE interface control signals override register #0 0x30 32 read-write 0x0 0x7FFFFFFF REG_PIPE_PHY_MODE_OVRD_EN PIPE - Selects PHY operating mode. (PCIe/USB/SATA/DP) [0:0] read-write REG_PIPE_PHY_MODE_OVRD_VALUE PIPE - Selects PHY operating mode. (PCIe/USB/SATA/DP) [4:1] read-write REG_PIPE_EB_MODE_OVRD_EN PIPE - Selects elastic buffer operating mode [5:5] read-write REG_PIPE_EB_MODE_OVRD_VALUE PIPE - Selects elastic buffer operating mode [6:6] read-write REG_PIPE_TX_DETECTRX_OVRD_EN PIPE - Controls receiver detection or loopback mode [7:7] read-write REG_PIPE_TX_DETECTRX_OVRD_VALUE PIPE - Controls receiver detection or loopback mode [8:8] read-write REG_PIPE_TX_ELECTIDLE_OVRD_EN PIPE - Tx Electric Idle - Forces Tx output to Electrical Idle when asserted [9:9] read-write REG_PIPE_TX_ELECTIDLE_OVRD_VALUE PIPE - Tx Electric Idle - Forces Tx output to Electrical Idle when asserted [10:10] read-write REG_PIPE_TX_ONE_ZEROS_OVRD_EN PIPE - Enables USB SS compliance pattern CP7 or CP8 [11:11] read-write REG_PIPE_TX_ONE_ZEROS_OVRD_VALUE PIPE - Enables USB SS compliance pattern CP7 or CP8 [12:12] read-write REG_PIPE_RX_POLARITY_OVRD_EN PIPE - Enables receiver polarity inversion [13:13] read-write REG_PIPE_RX_POLARITY_OVRD_VALUE PIPE - Enables receiver polarity inversion [14:14] read-write REG_PIPE_RX_EQ_TRAINING_OVRD_EN PIPE - Enables equalization training [15:15] read-write REG_PIPE_RX_EQ_TRAINING_OVRD_VALUE PIPE - Enables equalization training [16:16] read-write REG_PIPE_POWER_DOWN_OVRD_EN PIPE - Controls the transceiver power state [17:17] read-write REG_PIPE_POWER_DOWN_OVRD_VALUE PIPE - Controls the transceiver power state [20:18] read-write REG_PIPE_RATE_OVRD_EN PIPE - Control the link signlaing rate [21:21] read-write REG_PIPE_RATE_OVRD_VALUE PIPE - Control the link signlaing rate [23:22] read-write REG_PIPE_WIDTH_OVRD_EN PIPE - Control the PIPE data path width [24:24] read-write REG_PIPE_WIDTH_OVRD_VALUE PIPE - Control the PIPE data path width [26:25] read-write REG_PIPE_PCLK_RATE_OVRD_EN PIPE - Control the PIPE PCLK rate [27:27] read-write REG_PIPE_PCLK_RATE_OVRD_VALUE PIPE - Control the PIPE PCLK rate [30:28] read-write PIPE_OVERRIDE_1 PIPE interface control signals override register #1 0x34 32 read-write 0x0 0x7FFFFFF REG_PIPE_RX_TERMINATION_OVRD_EN PIPE - Controls presence of receiver terminations [0:0] read-write REG_PIPE_RX_TERMINATION_OVRD_VALUE PIPE - Controls presence of receiver terminations [1:1] read-write REG_PIPE_RX_STANDBY_OVRD_EN PIPE - Controls whether the PHY RX is active when the PHY is in any power state with PCLK on [2:2] read-write REG_PIPE_RX_STANDBY_OVRD_VALUE PIPE - Controls whether the PHY RX is active when the PHY is in any power state with PCLK on [3:3] read-write REG_PIPE_ENC_DEC_BYPASS_OVRD_EN PIPE - Controls whether the PHY performs 8b/10b encode and decode [4:4] read-write REG_PIPE_ENC_DEC_BYPASS_OVRD_VALUE PIPE - Controls whether the PHY performs 8b/10b encode and decode [5:5] read-write REG_PIPE_BLOCK_ALIGN_CONTROL_OVRD_EN PIPE - Enables SYNC OS detection [6:6] read-write REG_PIPE_BLOCK_ALIGN_CONTROL_OVRD_VALUE PIPE - Enables SYNC OS detection [7:7] read-write REG_PIPE_TX_DEEMPH_OVRD_EN PIPE - Selects transmitter de-emphasis [8:8] read-write REG_PIPE_TX_DEEMPH_OVRD_VALUE PIPE - Selects transmitter de-emphasis [26:9] read-write PIPE_STATUS PIPE interface status read register 0x38 32 read-only 0x0 0x7F REG_PIPE_RXVALID PIPE - Indicates symbol lock and valid data [0:0] read-only REG_PIPE_PHY_STATUS PIPE - Indicates completion of PHY operations [1:1] read-only REG_PIPE_RX_ELECIDLE PIPE - Indicates receiver detection of electrical idle [2:2] read-only REG_PIPE_RX_STATUS PIPE - Indicates status of received data and receiver detection [5:3] read-only REG_PIPE_POWER_PRESENT PIPE - Indicates the presence of VBUS [6:6] read-only INTR0 INTR0 Cause. These are the wakeup interrupts get reflected on interrupt_wakeup pin. 0x40 32 read-write 0x0 0x7FFFF REG_INT_RATE_CHANGE Indicates RATE change to F/W. RATE information comes from MAC [0:0] read-write REG_INT_P0_CHANGE Indicates P0 change to F/W. PowerDown information comes from MAC [1:1] read-write REG_INT_P1_CHANGE Indicates P1 change to F/W. PowerDown information comes from MAC [2:2] read-write REG_INT_P2_CHANGE Indicates P2 change to F/W. PowerDown information comes from MAC [3:3] read-write REG_INT_P3_CHANGE Indicates P3 change to F/W. PowerDown information comes from MAC [4:4] read-write REG_INT_TX_SFT_REG_WDONE Indicates shift register write done [5:5] read-write REG_INT_RX_PLL_LOCKED Loss of RX PLL clock [6:6] read-write REG_INT_RX_POWER_GOOD_RXA RXA Regulator power good [7:7] read-write REG_INT_RX_POWER_GOOD_RXCK RXCK Regulator power good [8:8] read-write REG_INT_RX_POWER_GOOD_RXD RXD Regulator power good [9:9] read-write REG_INT_RX_OSA_ERROR Indicates failure of offset calibration [10:10] read-write REG_INT_RX_OSA_ALL_DONE Indicates all offset calibration complete [11:11] read-write REG_INT_RX_LFPSDET_OUT Indicates LFPS detected on RX pins [12:12] read-write REG_INT_RX_EYE_HIGHT_DONE Interrupt to controller indicating completation of eye height measurement [13:13] read-write REG_INT_RX_EYE_MON_DONE Interrupt to controller indicating completation of eye monitor measurement [14:14] read-write REG_INT_PLL_LOCKED Loss of PLL clock [15:15] read-write REG_INT_PLL_PWR_GOOD_LCPLL Indicates vreglcpll power good [16:16] read-write REG_INT_PLL_PWR_GOOD_REF Indicates vregref power good [17:17] read-write REG_INT_PLL_PWR_GOOD_DIG Indicates vregdig power good [18:18] read-write INTR0_SET INTR0 Set 0x44 32 read-write 0x0 0x7FFFF REG_INT_RATE_CHANGE Write with '1' to set corresponding bit in interrupt request register. [0:0] read-write REG_INT_P0_CHANGE Write with '1' to set corresponding bit in interrupt request register. [1:1] read-write REG_INT_P1_CHANGE Write with '1' to set corresponding bit in interrupt request register. [2:2] read-write REG_INT_P2_CHANGE Write with '1' to set corresponding bit in interrupt request register. [3:3] read-write REG_INT_P3_CHANGE Write with '1' to set corresponding bit in interrupt request register. [4:4] read-write REG_INT_TX_SFT_REG_WDONE Write with '1' to set corresponding bit in interrupt request register. [5:5] read-write REG_INT_RX_PLL_LOCKED Write with '1' to set corresponding bit in interrupt request register. [6:6] read-write REG_INT_RX_POWER_GOOD_RXA Write with '1' to set corresponding bit in interrupt request register. [7:7] read-write REG_INT_RX_POWER_GOOD_RXCK Write with '1' to set corresponding bit in interrupt request register. [8:8] read-write REG_INT_RX_POWER_GOOD_RXD Write with '1' to set corresponding bit in interrupt request register. [9:9] read-write REG_INT_RX_OSA_ERROR Write with '1' to set corresponding bit in interrupt request register. [10:10] read-write REG_INT_RX_OSA_ALL_DONE Write with '1' to set corresponding bit in interrupt request register. [11:11] read-write REG_INT_RX_LFPSDET_OUT Write with '1' to set corresponding bit in interrupt request register. [12:12] read-write REG_INT_RX_EYE_HIGHT_DONE Write with '1' to set corresponding bit in interrupt request register. [13:13] read-write REG_INT_RX_EYE_MON_DONE Write with '1' to set corresponding bit in interrupt request register. [14:14] read-write REG_INT_PLL_LOCKED Write with '1' to set corresponding bit in interrupt request register. [15:15] read-write REG_INT_PLL_PWR_GOOD_LCPLL Write with '1' to set corresponding bit in interrupt request register. [16:16] read-write REG_INT_PLL_PWR_GOOD_REF Write with '1' to set corresponding bit in interrupt request register. [17:17] read-write REG_INT_PLL_PWR_GOOD_DIG Write with '1' to set corresponding bit in interrupt request register. [18:18] read-write INTR0_MASK INTR0 Mask 0x48 32 read-write 0x0 0x7FFFF REG_INT_RATE_CHANGE_MASK Mask bit for corresponding bit in interrupt request register. [0:0] read-write REG_INT_P0_CHANGE_MASK Mask bit for corresponding bit in interrupt request register. [1:1] read-write REG_INT_P1_CHANGE_MASK Mask bit for corresponding bit in interrupt request register. [2:2] read-write REG_INT_P2_CHANGE_MASK Mask bit for corresponding bit in interrupt request register. [3:3] read-write REG_INT_P3_CHANGE_MASK Mask bit for corresponding bit in interrupt request register. [4:4] read-write REG_INT_TX_SFT_REG_WDONE_MASK Mask bit for corresponding bit in interrupt request register. [5:5] read-write REG_INT_RX_PLL_LOCKED_MASK Mask bit for corresponding bit in interrupt request register. [6:6] read-write REG_INT_RX_POWER_GOOD_RXA_MASK Mask bit for corresponding bit in interrupt request register. [7:7] read-write REG_INT_RX_POWER_GOOD_RXCK_MASK Mask bit for corresponding bit in interrupt request register. [8:8] read-write REG_INT_RX_POWER_GOOD_RXD_MASK Mask bit for corresponding bit in interrupt request register. [9:9] read-write REG_INT_RX_OSA_ERROR_MASK Mask bit for corresponding bit in interrupt request register. [10:10] read-write REG_INT_RX_OSA_ALL_DONE_MASK Mask bit for corresponding bit in interrupt request register. [11:11] read-write REG_INT_RX_LFPSDET_OUT_MASK Mask bit for corresponding bit in interrupt request register. [12:12] read-write REG_INT_RX_EYE_HIGHT_DONE_MASK Mask bit for corresponding bit in interrupt request register. [13:13] read-write REG_INT_RX_EYE_MON_DONE_MASK Mask bit for corresponding bit in interrupt request register. [14:14] read-write REG_INT_PLL_LOCKED_MASK Mask bit for corresponding bit in interrupt request register. [15:15] read-write REG_INT_PLL_PWR_GOOD_LCPLL_MASK Mask bit for corresponding bit in interrupt request register. [16:16] read-write REG_INT_PLL_PWR_GOOD_REF_MASK Mask bit for corresponding bit in interrupt request register. [17:17] read-write REG_INT_PLL_PWR_GOOD_DIG_MASK Mask bit for corresponding bit in interrupt request register. [18:18] read-write INTR0_MASKED INTR0 Masked 0x4C 32 read-only 0x0 0x7FFFF REG_INT_RATE_CHANGE_MASKD Logical and of corresponding request and mask bits. [0:0] read-only REG_INT_P0_CHANGE_MASKD Logical and of corresponding request and mask bits. [1:1] read-only REG_INT_P1_CHANGE_MASKD Logical and of corresponding request and mask bits. [2:2] read-only REG_INT_P2_CHANGE_MASKD Logical and of corresponding request and mask bits. [3:3] read-only REG_INT_P3_CHANGE_MASKD Logical and of corresponding request and mask bits. [4:4] read-only REG_INT_TX_SFT_REG_WDONE_MASKD Logical and of corresponding request and mask bits. [5:5] read-only REG_INT_RX_PLL_LOCKED_MASKD Logical and of corresponding request and mask bits. [6:6] read-only REG_INT_RX_POWER_GOOD_RXA_MASKD Logical and of corresponding request and mask bits. [7:7] read-only REG_INT_RX_POWER_GOOD_RXCK_MASKD Logical and of corresponding request and mask bits. [8:8] read-only REG_INT_RX_POWER_GOOD_RXD_MASKD Logical and of corresponding request and mask bits. [9:9] read-only REG_INT_RX_OSA_ERROR_MASKD Logical and of corresponding request and mask bits. [10:10] read-only REG_INT_RX_OSA_ALL_DONE_MASKD Logical and of corresponding request and mask bits. [11:11] read-only REG_INT_RX_LFPSDET_OUT_MASKD Logical and of corresponding request and mask bits. [12:12] read-only REG_INT_RX_EYE_HIGHT_DONE_MASKD Logical and of corresponding request and mask bits. [13:13] read-only REG_INT_RX_EYE_MON_DONE_MASKD Logical and of corresponding request and mask bits. [14:14] read-only REG_INT_PLL_LOCKED_MASKD Logical and of corresponding request and mask bits. [15:15] read-only REG_INT_PLL_PWR_GOOD_LCPLL_MASKD Logical and of corresponding request and mask bits. [16:16] read-only REG_INT_PLL_PWR_GOOD_REF_MASKD Logical and of corresponding request and mask bits. [17:17] read-only REG_INT_PLL_PWR_GOOD_DIG_MASKD Logical and of corresponding request and mask bits. [18:18] read-only TX_AFE_CTRL_0 Tx AFE control register #0 0x60 32 read-write 0x10000000 0x3FFFFFF7 REG_TX_AFE_EN Enable signal for Tx [0:0] read-write REG_TX_AFE_DRV_EN Enable signal for Tx driver [1:1] read-write REG_TX_AFE_CML2CMOS_EN Enable signal for CML2CMOS clock converter [2:2] read-write REG_TX_AFE_VCPREG_EN voltage regulator charge pump enable [4:4] read-write REG_TX_AFE_VCPREG_SEL charge pump output voltage selection [8:5] read-write REG_TX_AFE_CPCLK_SEL charge pump clock frequency selection [9:9] read-write REG_TX_AFE_VREG_CLK_EN clock regulator enable [10:10] read-write REG_TX_AFE_VREG_CLK_SEL clock regulator output voltage selection [14:11] read-write REG_TX_AFE_VREG_DRV_EN Driver regulator enable [15:15] read-write REG_TX_AFE_VREG_DRV_SEL Driver regulator output voltage selection [19:16] read-write REG_TX_AFE_TX_PULL_DN Control bit to make txp/n pads low [20:20] read-write REG_TX_AFE_TX_LOOPBK_EN Analog Serial Loopback Enable [21:21] read-write REG_TX_AFE_TX_DCD_CTRL Duty cycle control for internal high speed clock [25:22] read-write REG_TX_AFE_TX_DETECTRX_TRIM Enable receiver detection threshold selection [27:26] read-write REG_TX_AFE_TX_ELECIDLE_DRV Electricle idle driver stregnth control 00: Hi-Z 01: weak drive strength (default) 10: Moderate drive strength 11: strongest drive strength [29:28] read-write TX_AFE_CTRL_1 Tx AFE control register #1 0x64 32 read-write 0x0 0x7FFBF REG_TX_AFE_TX_ICAL_TRIM Input current trim for output Impedance calibration [5:0] read-write REG_TX_AFE_BURNIN_EN burnin enable for internal regulator [7:7] read-write REG_TX_AFE_TX_ADFT_EN ADFT enable [8:8] read-write REG_TX_AFE_TX_ADFT TX adft control [13:9] read-write REG_TX_AFE_TX_DDFT TX ddft control [18:14] read-write TX_AFE_PULL_UP_CNT Tx AFE Tx pull-up wait counter 0x68 32 read-write 0x9D3F 0xFFFF REG_TX_AFE_TX_PULL_UP_CNT_GEN1 tx_pull_up wait counter (default is 63, 0x3F), 0.5us target [7:0] read-write REG_TX_AFE_TX_PULL_UP_CNT_GEN2 tx_pull_up wait counter (default is 157, 0x9D), 0.5us target [15:8] read-write TX_AFE_RXDETECT_CNT Tx AFE TxDetectRx wait counter 0x6C 32 read-write 0x139007D 0xFFFFFFFF REG_TX_AFE_TX_RXDETECT_CNT_GEN1 TxDetectRx wait counter (default is 125, 0x7D) , 1us target [15:0] read-write REG_TX_AFE_TX_RXDETECT_CNT_GEN2 TxDetectRx wait counter (default is 313, 0x139), 1us target [31:16] read-write TX_AFE_OVERRIDE_0 Tx AFE override 0 register 0x70 32 read-write 0x0 0x3FFF3F REG_TX_AFE_TX_ENABLE_OVRD_EN Transmit Enable control 0 - Trnsmitter disabled 1 - Trnsmitter enabled [0:0] read-write REG_TX_AFE_TX_ENABLE_OVRD_VALUE Transmit Enable control 0 - Trnsmitter disabled 1 - Trnsmitter enabled [1:1] read-write REG_TX_AFE_TX_SER_EN_OVRD_EN Serializer Enable control 0 - Serializer disabled 1 - Serilizer enabled [2:2] read-write REG_TX_AFE_TX_SER_EN_OVRD_VALUE Serializer Enable control 0 - Serializer disabled 1 - Serilizer enabled [3:3] read-write REG_TX_AFE_TX_HSCLK_DRV_EN_OVRD_EN Enable signal for high speed clock that drives the final driver [4:4] read-write REG_TX_AFE_TX_HSCLK_DRV_EN_OVRD_VALUE Enable signal for high speed clock that drives the final driver [5:5] read-write REG_TX_AFE_TX_DETECTRX_OVRD_EN Enable receiver detection [8:8] read-write REG_TX_AFE_TX_DETECTRX_OVRD_VALUE Enable receiver detection [9:9] read-write REG_TX_AFE_TX_ELECIDLE_OVRD_EN Enable TX electrical idle [10:10] read-write REG_TX_AFE_TX_ELECIDLE_OVRD_VALUE Enable TX electrical idle [11:11] read-write REG_TX_AFE_TX_LFPS_OVRD_EN Enable LFPS signaling [12:12] read-write REG_TX_AFE_TX_LFPS_OVRD_VALUE Enable LFPS signaling [13:13] read-write REG_TX_AFE_TX_ZCAL_OVRD_EN Automatic impedance calibration enable [14:14] read-write REG_TX_AFE_TX_ZCAL_OVRD_VALUE Automatic impedance calibration enable [15:15] read-write REG_TX_AFE_TX_ZTRIM_OVRD_EN Automatic impedance calibration trim bits [16:16] read-write REG_TX_AFE_TX_ZTRIM_OVRD_VALUE Automatic impedance calibration trim bits [21:17] read-write TX_AFE_OVERRIDE_1 Tx AFE override 0 register 0x74 32 read-write 0x0 0x3FFF1 REG_TX_AFE_TX_CTRL_IN_OVRD_EN Control bits to configure TX slices [0:0] read-write REG_TX_AFE_TX_CTRL_IN_OVRD_VALUE Control bits to configure TX slices [11:4] read-write REG_TX_AFE_TX_SHIFT_CLK_OVRD_EN shift clock input for tx_ctrl_in<7:0> input [12:12] read-write REG_TX_AFE_TX_SHIFT_CLK_OVRD_VALUE shift clock input for tx_ctrl_in<7:0> input [13:13] read-write REG_TX_AFE_TX_LOAD_CLK_OVRD_EN Load clock input for tx_ctrl_in<7:0> input [14:14] read-write REG_TX_AFE_TX_LOAD_CLK_OVRD_VALUE Load clock input for tx_ctrl_in<7:0> input [15:15] read-write REG_TX_AFE_TX_PULL_UP_OVRD_EN Control bit to make txp/n pads high [16:16] read-write REG_TX_AFE_TX_PULL_UP_OVRD_VALUE Control bit to make txp/n pads high [17:17] read-write TX_AFE_DEBUG Tx AFE debug register 0x78 32 read-only 0x0 0x3 REG_TX_AFE_DDFT_OUT1 DDFT output [0:0] read-only REG_TX_AFE_DDFT_OUT2 DDFT output [1:1] read-only TX_AFE_STATUS Tx AFE status register 0x7C 32 read-only 0x0 0x600F REG_TX_ZCAL_EXCEED_INC impedance calibration comperator exceed indicate when increment mode [0:0] read-only REG_TX_ZCAL_EXCEED_DEC impedance calibration comperator exceed indicate when decrement mode [1:1] read-only REG_TX_ZCAL_COMP_OUT Automatic impedance calibration comparator output (stuck check for debug) [2:2] read-only REG_TX_DETECTRX_OUT Exteranl Rx detect output [3:3] read-only REG_TX_STATUS_TBD TBD [14:13] read-only TX_AFE_ZTRIM Tx AFE impedance calibration register 0x84 32 read-write 0x0 0x1F1F REG_TX_ZCAL_EN Impedance calibration enable [0:0] read-write REG_TX_ZCAL_MODE Impedance calibration mode, TBD [1:1] read-write REG_TX_COMP_WAIT impedance calibration comperator wait delay 0: 10ns (default) 1: 20ns 2: 30ns 3: 40ns [3:2] read-write REG_TX_ZCAL_FORCE_EN Impedance calibration trim force enable [4:4] read-write REG_TX_ZCAL_FORCE Impedance calibration trim force [12:8] read-write TX_AFE_ZTRIM_RESULT Tx AFE impedance calibration result register 0x88 32 read-only 0x0 0x1F REG_TX_ZTRIM Impedance calibration trim result [4:0] read-only TX_AFE_ZTRIM_NVALUES Tx AFE impedance calibration Nmain, Npre, Npost, Nvswing register 0x8C 32 read-write 0x0 0x3F3F3F3F REG_TX_ZCAL_NMAIN Impedance calibration Nmain[5:0] for debug [5:0] read-write REG_TX_ZCAL_NPRE Impedance calibration Npre[5:0] for debug [13:8] read-write REG_TX_ZCAL_NPOST Impedance calibration Npost[5:0] for debug [21:16] read-write REG_TX_ZCAL_NVSWING Impedance calibration Nvswing[5:0] for debug [29:24] read-write TX_AFE_CFG Tx AFE configuration control register 0x90 32 read-write 0x0 0x1 REG_TX_CFG_WRITE_DONE Tx AFE config shift register write done. [0:0] read-write TX_AFE_CFG_SFT_W_0 Tx AFE configuration control shift write register #0 0x94 32 read-write 0x3FFFFF 0x3FFFFF REG_TX_CFG_SFT_W_0 Tx AFE config shift register write [21:0] read-write TX_AFE_CFG_SFT_W_1 Tx AFE configuration control shift write register #1 0x98 32 read-write 0x3FFFFF 0x3FFFFF REG_TX_CFG_SFT_W_1 Tx AFE config shift register write [21:0] read-write TX_AFE_CFG_SFT_W_2 Tx AFE configuration control shift write register #2 0x9C 32 read-write 0x3FFFFF 0x3FFFFF REG_TX_CFG_SFT_W_2 Tx AFE config shift register write [21:0] read-write TX_AFE_CFG_SFT_W_3 Tx AFE configuration control shift write register #3 0xA0 32 read-write 0x3FFFFF 0x3FFFFF REG_TX_CFG_SFT_W_3 Tx AFE config shift register write [21:0] read-write TX_AFE_CFG_SFT_W_4 Tx AFE configuration control shift write register #4 0xA4 32 read-write 0x3FFFFF 0x3FFFFF REG_TX_CFG_SFT_W_4 Tx AFE config shift register write [21:0] read-write TX_AFE_CFG_SFT_W_5 Tx AFE configuration control shift write register #5 0xA8 32 read-write 0x3FFFFF 0x3FFFFF REG_TX_CFG_SFT_W_5 Tx AFE config shift register write [21:0] read-write TX_AFE_CFG_SFT_W_6 Tx AFE configuration control shift write register #6 0xAC 32 read-write 0x3FFFFF 0x3FFFFF REG_TX_CFG_SFT_W_6 Tx AFE config shift register write [21:0] read-write TX_AFE_CFG_SFT_W_7 Tx AFE configuration control shift write register #7 0xB0 32 read-write 0x3FFFFF 0x3FFFFF REG_TX_CFG_SFT_W_7 Tx AFE config shift register write [21:0] read-write ADC_0 Analog to Digital Converter register #0 0xC0 32 read-write 0x0 0xF37FFF REG_ADC_FUNC_ADC_DAC_CNTRL ADC function control, This can be controlled via SAR Logic (SAR_EN) or via direct config register. [7:0] read-write REG_ADC_TRIMS_TRIM_VREG_SEL ADC Trim [11:8] read-write REG_ADC_CTRL_ADC_VSEL ADC [14:12] read-write REG_ADC_CTRL_ADC_VREF_DAC_SEL ADC [17:16] read-write REG_ADC_CTRL_ADC_ISO_N ADC [20:20] read-write REG_ADC_CTRL_ADC_PD_LV ADC [21:21] read-write REG_ADC_CTRL_ADC_DFT_MUXSEL ADC [22:22] read-write REG_ADC_CTRL_ADC_EN_LDO ADC [23:23] read-write ADC_STATUS Analog to Digital Converter status register 0xC4 32 read-only 0x0 0x1 REG_ADC_COMP_OUT_FX ADC status [0:0] read-only USB40PHY_RX PHY Rx registers 0x00000800 RX_SDM_CFG0 Sigma-Delta Modulator (SDM) Configuration 0x0 16 read-write 0x0 0xFF DIVF_INTEGER Feedback Divider Ratio integer vlaue (not required if SSM is present) [7:0] read-write RX_SDM_CFG1 Sigma-Delta Modulator (SDM) Configuration 0x4 16 read-write 0x0 0xFFFF DIVF_FRAC_MSB Feedback Divider Ratio fractional vlaue (not required if SSM is used) [15:0] read-write RX_SDM_CFG2 Sigma-Delta Modulator (SDM) Configuration 0x8 16 read-write 0x0 0x3 DIVF_FRAC_LSB Feedback Divider Ratio fractional vlaue (not required if SSM is used) [1:0] read-write RX_SDM_CFG3 Sigma-Delta Modulator (SDM) Configuration 0xC 16 read-write 0x0 0x1F SDM_ENABLE Sigma-Delta modulator enable, (active low power down), SSM will be down too [0:0] read-write DITHER_EN Sigma-Delta Modulator dither enable [1:1] read-write DITHER_GAIN Sigma-Delta Modulator dither gain, specifies number of dither bits [4:2] read-write RX_DFE_CFG0 DFE FSM (DFE) Configuration 0x10 16 read-write 0x0 0xFF9F OVRD_VGATAP VGA tap Coefficient setting for override [4:0] read-write OVRD_VGATAP_EN VGA tap override enable [7:7] read-write OVRD_DFETAP1 DFE tap 1 Coefficient setting for overrid [14:8] read-write OVRD_DFETAP1_EN DFE tap 1 override enable [15:15] read-write RX_DFE_CFG1 DFE FSM (DFE) Configuration 0x14 16 read-write 0x0 0xFFFF OVRD_DFETAP2 DFE tap 2 Coefficient setting for overrid [6:0] read-write OVRD_DFETAP2_EN DFE tap 2 override enable [7:7] read-write OVRD_DFETAP3 DFE tap 3 Coefficient setting for overrid [14:8] read-write OVRD_DFETAP3_EN DFE tap 3 override enable [15:15] read-write RX_DFE_CFG2 DFE FSM (DFE) Configuration 0x18 16 read-write 0x0 0xFFFF DFE_SLICEPOINTVALUE slice point value in error slicers, positive [5:0] read-write DFE_SLICEPOINTSIGN1 1: error slicer 1 has positive slice point; 0: negative [6:6] read-write DFE_SLICEPOINTSIGN2 1: error slicer 2 has positive slice point; 0: negative [7:7] read-write VGA_MU mu/16 multiplier for VGA tap0 adaptation [11:8] read-write DFE_MU mu/16 multiplier for DFE taps adaptation [15:12] read-write RX_DFE_CFG3 DFE FSM (DFE) Configuration 0x1C 16 read-write 0x0 0x7FF DFE_BAL_AVRG # of cycles averaging tap updates [2:0] read-write DFE_BALANCE_SCALE Scaling for DFE balances when subtracting error/non_error [4:3] read-write VGA_POLARITY VGA tap polarity swapping, default 0 [5:5] read-write DFE_POLARITY DFE taps polarity swapping, default 0 [6:6] read-write VGA_ADAPT_EN VGA adaptation enable, active high [7:7] read-write DFE_ENABLE DFE adaptation enable, active high [8:8] read-write VGA_FREEZE freeze VGA adaptation with present values [9:9] read-write DFE_FREEZE freeze DFE adaptation with all present values [10:10] read-write RX_DFE_STAT0 DFE FSM (DFE) status 0x20 16 read-only 0x0 0x7F1F VGATAP VGA tap, gain control (Note, Dynamic async to CSR clock, need sync or being frozen for read) [4:0] read-only DFETAP1 DFE tap 1 DAC input (Note, Dynamic async to CSR clock, need sync or being frozen for read) [14:8] read-only RX_DFE_STAT1 DFE FSM (DFE) status 0x24 16 read-only 0x0 0x7F7F DFETAP2 DFE tap 2 DAC input (Note, Dynamic async to CSR clock, need sync or being frozen for read) [6:0] read-only DFETAP3 DFE tap 3 DAC input (Note, Dynamic async to CSR clock, need sync or being frozen for read) [14:8] read-only RX_DFE_STAT2 DFE FSM (DFE) status 0x28 16 read-only 0x0 0x7F7F ERRSLIC1DELTA Error slicer 1 offset+(sign)delta [6:0] read-only ERRSLIC2DELTA Error slicer 2 offset+(sign)delta [14:8] read-only RX_OSA_CFG0 Offset Calibration FSM (OSA) Configuration 0x2C 16 read-write 0x0 0xFFFF OVRD_EDGSLICE1OS Edge slicer 1 offset adjustment override [6:0] read-write OVRD_EDGSLICE1OS_EN Edge slicer 1 offset adjustment override enable [7:7] read-write OVRD_EDGSLICE2OS Edge slicer 2 offset adjustment override [14:8] read-write OVRD_EDGSLICE2OS_EN Edge slicer 2 offset adjustment override enable [15:15] read-write RX_OSA_CFG1 Offset Calibration FSM (OSA) Configuration 0x30 16 read-write 0x0 0xFFFF OVRD_DATSLICE1OS Data slicer 1 offset adjustment override [6:0] read-write OVRD_DATSLICE1OS_EN Data slicer 1 offset adjustment override enable [7:7] read-write OVRD_DATSLICE2OS Data slicer 2 offset adjustment override [14:8] read-write OVRD_DATSLICE2OS_EN Data slicer 2 offset adjustment override enable [15:15] read-write RX_OSA_CFG2 Offset Calibration FSM (OSA) Configuration 0x34 16 read-write 0x0 0xFFFF OVRD_ERRSLICE1OS Error slicer 1 offset adjustment override [6:0] read-write OVRD_ERRSLICE1OS_EN Error slicer 1 offset adjustment override enable [7:7] read-write OVRD_ERRSLICE2OS Error slicer 2 offset adjustment override [14:8] read-write OVRD_ERRSLICE2OS_EN Error slicer 2 offset adjustment override enable [15:15] read-write RX_OSA_CFG3 Offset Calibration FSM (OSA) Configuration 0x38 16 read-write 0x0 0xFFFF OVRD_ROAMSLICE1OS Roam slicer 1 offset adjustment override [6:0] read-write OVRD_ROAMSLICE1OS_EN Roam slicer 1 offset adjustment override enable [7:7] read-write OVRD_ROAMSLICE2OS Roam slicer 2 offset adjustment override [14:8] read-write OVRD_ROAMSLICE2OS_EN Roam slicer 2 offset adjustment override enable [15:15] read-write RX_OSA_CFG4 Offset Calibration FSM (OSA) Configuration 0x3C 16 read-write 0x0 0xFF OVRD_AFEOSDAC AFE offset adjustment override [6:0] read-write OVRD_AFEOSDAC_EN AFE offset adjustment override enable [7:7] read-write RX_OSA_CFG5 Offset Calibration FSM (OSA) Configuration 0x40 16 read-write 0x0 0x7 OSA_DFE_START DFE offset calibration start, AFE calibration will follow [0:0] read-write OSA_AFE_START AFE offset calibration on demand start [1:1] read-write OSA_RESETB AFE offset calibration block reset, active low [2:2] read-write RX_OSA_STAT0 Offset Calibration FSM (OSA) status 0x44 16 read-only 0x0 0x7F7F EDGSLICE1OS Edge slicer 1 adjusted offset [6:0] read-only EDGSLICE2OS Edge slicer 2 adjusted offset [14:8] read-only RX_OSA_STAT1 Offset Calibration FSM (OSA) status 0x48 16 read-only 0x0 0x7F7F DATSLICE1OS Edge slicer 1 adjusted offset [6:0] read-only DATSLICE2OS Edge slicer 2 adjusted offset [14:8] read-only RX_OSA_STAT2 Offset Calibration FSM (OSA) status 0x4C 16 read-only 0x0 0x7F7F ERRSLICE1OS Error slicer 1 adjusted offset [6:0] read-only ERRSLICE2OS Error slicer 2 adjusted offset [14:8] read-only RX_OSA_STAT3 Offset Calibration FSM (OSA) status 0x50 16 read-only 0x0 0x7F7F ROAMSLICE1OS Roam slicer 1 adjusted offset [6:0] read-only ROAMSLICE2OS Roam slicer 2 adjusted offset [14:8] read-only RX_OSA_STAT4 Offset Calibration FSM (OSA) status 0x54 16 read-only 0x0 0x7F AFEOSDAC AFE adjusted offset [6:0] read-only RX_OSA_STAT5 Offset Calibration FSM (OSA) status 0x58 16 read-only 0x0 0x77 OSA_DFE_DONE Offset calibration for DFE blocks (summer+slicer) is completed [0:0] read-only OSA_AFE_DONE Offset calibration for AFE Blocks (AGC+CTLE) is completed [1:1] read-only OSA_ALL_DONE All offset calibrations are completed [2:2] read-only OSA_DFE_ERROR There has been some error during offset calibration for DFE blocks [4:4] read-only OSA_AFE_ERROR There has been some error during offset calibration for AFE blocks [5:5] read-only OSA_ERROR There has been some error during offset calibration for one the blocks, output as interupt, read specific error at osa_err_bits#. [6:6] read-only RX_OSA_STAT6 Offset Calibration FSM (OSA) status 0x5C 16 read-only 0x0 0xFFFF OSA_ERR_BITS0 Error bits indicating what went wrong in which block,bits 15:0 [15:0] read-only RX_OSA_STAT7 Offset Calibration FSM (OSA) status 0x60 16 read-only 0x0 0xFFFF OSA_ERR_BITS1 Error bits indicating what went wrong in which block, bits 31:16 [15:0] read-only RX_OSA_STAT8 Offset Calibration FSM (OSA) status 0x64 16 read-only 0x0 0xF OSA_ERR_BITS2 Error bits indicating what went wrong in which block, bits 39:32 [3:0] read-only RX_CTLE_CFG0 CTLE controls Configuration 0x68 16 read-write 0x0 0x1F03 CTLE_EYEHT_EN Enable eye hieght measurement for CTLE adaptation [0:0] read-write EYEHT_START_CNT Start error count for CTLE adaptation [1:1] read-write CTLE_STG1_CMADJ Adjust CTLE cap values for desired EQ [10:8] read-write CTLE_CAP_FZERO_EN Adjust CTLE resistor values for desired EQ [11:11] read-write CTLE_CAP_GAIN_ADJ Strobe/update CTLE EQ settings [12:12] read-write RX_CTLE_CFG1 CTLE controls Configuration 0x6C 16 read-write 0x0 0xFFFF CTLE_STG1RES Adjust CTLE stage 1 resistor value [3:0] read-write CTLE_STG1CAP Adjust CTLE stage 1 cap value [6:4] read-write CTLE_STG1BOOST CTLE stage 1 boost [7:7] read-write CTLE_STG2RES Adjust CTLE stage 2 resistor value [11:8] read-write CTLE_STG2CAP Adjust CTLE stage 2 cap value [14:12] read-write CTLE_STG2BOOST CTLE stage 2 boost [15:15] read-write RX_CTLE_STAT0 CTLE controls status 0x70 16 read-only 0x0 0xFFFF EYEHT_ERR_CNT Error count for CTLE adaptation [15:0] read-only RX_CTLE_STAT1 CTLE controls status 0x74 16 read-only 0x0 0x1 EYEHT_CNT_DONE Error count for CTLE adaptation is done [0:0] read-only RX_EM_CFG0 Eye monitor FSM (EM) Configuration 0x78 16 read-write 0x0 0xFFFF EYE_WORD_CNT eye word count [2:0] read-write DATA_SAMPLE_DELAY data sample delay [5:3] read-write ROAM_SAMPLE_DELAY roam sample delay [8:6] read-write EM_CTRL_UNUSED unused control bits [11:9] read-write EN_EYE_ODD enable odd eye [12:12] read-write EN_EYE_EVEN enable even eye [13:13] read-write START_COUNT Eye monitor control and settings (place holder if required) [14:14] read-write EN_EYEMON Enable eye monotor controller [15:15] read-write RX_EM_CFG1 Eye monitor FSM (EM) Configuration 0x7C 16 read-write 0x0 0xFFFF ROAM_SLICEPOINT roam slicer 1 & 2 slice point amplitude [5:0] read-write ROAM_SLICEPOINTSIGN1 roam slicer 1 slicepoint, 1:positive, 0:negative [6:6] read-write ROAM_SLICEPOINTSIGN2 roam slicer 2 slicepoint, 1:positive, 0:negative [7:7] read-write PIROAMPSEL roam phase interpolator value [14:8] read-write PIROAMPSEL_EN roam phase interpolator enable [15:15] read-write RX_EM_STAT0 Eye monitor FSM (EM) status 0x80 16 read-only 0x0 0xFFFF EYE_ERROR Eye information output (place holder if required) [15:0] read-only RX_EM_STAT1 Eye monitor FSM (EM) status 0x84 16 read-only 0x0 0xFFFD EYE_DONE eye monitor done [0:0] read-only RX_ROAMSLIC1OS roam slicer 1 offset (offset null + slicepoint) [8:2] read-only RX_ROAMSLIC2OS roam slicer 2 offset (offset null + slicepoint) [15:9] read-only RX_DFEA_CFG0 DFE Analog Configuration 0x88 16 read-write 0x0 0xFFFF DFEMAINADJ Adjust summer tail current [2:0] read-write DFE_PDB DFE main power down, active low [3:3] read-write DFETAP1ADJ Adjust DFE tap1 weight [6:4] read-write DFETAP1_PDB DFE tap1 power down, active low [7:7] read-write DFETAP2ADJ Adjust DFE tap2 weight [10:8] read-write DFETAP2_PDB DFE tap1 power down, active low [11:11] read-write DFETAP3ADJ Adjust DFE tap3 weight [14:12] read-write DFETAP3_PDB DFE tap1 power down, active low [15:15] read-write RX_OSAA_CFG0 Offset Calibration Analog Configuration 0x8C 16 read-write 0x0 0x7FFF ADJEDGESLIC1 Adjust edge slicer 1 offset DAC full scale range [2:0] read-write ADJEDGESLIC2 Adjust edge slicer 2 offset DAC full scale range [5:3] read-write ADJDATSLIC1 Adjust data slicer 1 offset DAC full scale range [8:6] read-write ADJDATSLIC2 Adjust dara slicer 2 offset DAC full scale range [11:9] read-write ADJERRSLIC1 Adjust error slicer 1 offset DAC full scale range [14:12] read-write RX_OSAA_CFG1 Offset Calibration Analog Configuration 0x90 16 read-write 0x0 0xFFF ADJERRSLIC2 Adjust error slicer 2 offset DAC full scale range [2:0] read-write ADJROAMSLIC1 Adjust roam slicer 1 offset DAC full scale range [5:3] read-write ADJROAMSLIC2 Adjust roam slicer 2 offset DAC full scale range [8:6] read-write AFEOSBIASADJ Adjust AFE offset DAC full scale range [11:9] read-write RX_AFE_CFG Analog Front End (AFE) Configuration 0x94 16 read-write 0x0 0x3FF CMADJ Adjusts input common-mode voltage [2:0] read-write TERM_EN Enable for 50 Ohm (nominal) termination [3:3] read-write TERM_TRIM_CFG value of term_trim input from processor [8:4] read-write LPBK_EN Loopback path enable [9:9] read-write RX_EMA_CFG Eye Monitor Analog Configuration 0x98 16 read-write 0x0 0x17 PICAPSEL Phase Interpolator cap select [2:0] read-write PI_PDB Eye monitor phase interpolator powe down [4:4] read-write RX_REFCKSEL_CFG Reference Clock Select (REFCLKSEL) Configuration 0x9C 16 read-write 0x0 0x1 LOCK2REF_SEL Reference Clock MUX Select between 25 or 100 MHz [0:0] read-write RX_DIVH_CFG HS Divider (DIVH) Configuration 0xA0 16 read-write 0x0 0x11F RECCLK_DIVH DIVH Divider Ratio, HSREF Clock [4:0] read-write RECCLK_EN High-Speed Ref Clk Output Enable [8:8] read-write RX_PFD_CFG Phase/Frequency Detector (PFD) Configuration 0xA4 16 read-write 0x0 0xF PFDDELAY Adjust dead-zone feedback delay [3:0] read-write RX_CP_CFG Charge Pump (CP) Configuration 0xA8 16 read-write 0x0 0x77 IPUP_ADJ Charge pump up current adjustment [2:0] read-write IPDN_ADJ Charge pump down current adjustment [6:4] read-write RX_LF_CFG Loop Filter (LF) Configuration 0xAC 16 read-write 0x0 0x3 LPF_ADJ Loop filter adjustment [1:0] read-write RX_BIASGEN_CFG0 Bias Generator (BIASGEN) Configuration 0xB0 16 read-write 0x0 0xFFF AFEBIASSET0 Adjust bias for stages of AFE/CTLE - LSb [11:0] read-write RX_BIASGEN_CFG1 Bias Generator (BIASGEN) Configuration 0xB4 16 read-write 0x0 0x7F3F AFEBIASSET1 Adjust bias for stages of AFE/CTLE - Msb [5:0] read-write CFG_BIAS Adjust bias currents [13:8] read-write BIAS_PDB Bias power down, active low [14:14] read-write RX_GNRL_CFG General Controls Configuration 0xB8 16 read-write 0x0 0xFFF BUS_BIT_MODE RX output data bus width mose, 0:16, 1:20, 2:32, 3:40 [1:0] read-write DESERRESETB De-serializer reset, active low [2:2] read-write DATA_RATE 0: 10G half rate, 1:5G full rate [3:3] read-write CLKGEN_PDB Clock generation loop (PD+CP+VCO,etc.) powerdown, active low [4:4] read-write LOWPWR AFE low power mode for 5 Gb/s data rate [5:5] read-write ERR_PATH_EN DFE error path power down [6:6] read-write EDGE_DESER_EN Edge deserializer power down [7:7] read-write SUMEVN_PDB DFE even path summer power down [8:8] read-write SUMODD_PDB DFE odd path summer power down [9:9] read-write SUMVDD_PULLDOWN Summers output pull down [10:10] read-write CLKINV Invert phase of pclk [11:11] read-write RX_VREG_CFG0 Regulators Configuration 0xBC 16 read-write 0x0 0xFFFF VCPREGSEL RX CP regulated supply voltage select [3:0] read-write VREGRXASEL RX analog regulated supply voltage select [7:4] read-write VREGRXCKSEL RX clock regulated supply voltage select [11:8] read-write VREGRXDSEL RX digital regulated supply voltage select [15:12] read-write RX_VREG_CFG1 Regulators Configuration 0xC0 16 read-write 0x0 0xF1FF VCPREG_BPB RX regulator charge pump bypass, active low [0:0] read-write VREGRXA_PDB RX analog regulated supply power down, active low [1:1] read-write VREGRXCK_PDB RX clock regulated supply power down, active low [2:2] read-write VREGRXD_PDB RX digital regulated supply power down, active low [3:3] read-write VCPREG_PDB charg-pump voltage supply power down, active low [4:4] read-write VREG1P4BIASSEL Adjust vreg1p4 bias for best CDR PSRR [5:5] read-write VREG1P4_BPB Power-down vreg1p4 and bypass output to vdd1p8 [6:6] read-write CPCLK_SEL Clock select for Charge pump [7:7] read-write BURNIN_EN Enable Burn-In mode [8:8] read-write VREG1P4SEL Adjust vreg1p4 for best CDR PSRR [15:12] read-write RX_VREG_STAT Regulators Status 0xC4 16 read-only 0x0 0x7 POWER_GOOD_RXA pwr_good_rxa for read as status [0:0] read-only POWER_GOOD_RXCK pwr_good_rxck for read as status [1:1] read-only POWER_GOOD_RXD pwr_good_rxd for read as status [2:2] read-only RX_SD_CFG Signal detect/LFPS Configuration 0xC8 16 read-write 0x0 0xF LFPS_VTH LFPS threshold levels setting [2:0] read-write LFPSDET_PDB LFPS detect power down (active low) [3:3] read-write RX_SD_STAT Signal detect/LFPS Status 0xCC 16 read-only 0x0 0x1 LFPSDET_OUT LFPS output detected for read as status [0:0] read-only RX_LD_CFG Lock Detect Configuration 0xD0 16 read-write 0x0 0xFF7 LOCKIN Frequency detect tolerance = +/- 0.025 percent*2^lockin [2:0] read-write FLOCKSEL Filtered lock, #of refcklk cycles flock generated after lock [2^(flocksel+8)] [5:4] read-write LOCKOUTSEL Lockup detect timer setting, cycles of refclk, 256 or 512 [6:6] read-write LUDDISABLE Lockup detect disable [7:7] read-write FD_OVRD Force combinations of freq detect and ph detect en [9:8] read-write RESETLOCKB lock detect lock output reset, active low, will not activate lockup detect [10:10] read-write LD_RESETB lock detect main reset, active low [11:11] read-write RX_LD_STAT Lock Detect Status 0xD4 16 read-only 0x0 0x1 PLL_LOCKED flock for read as status [0:0] read-only RX_ATEST_CFG Analog Test Mux (ATEST) Configuration 0xD8 16 read-write 0x0 0xFFF ADFT_CNTL Analog test MUX Select [3:0] read-write ADFT_ENABLE Analog test MUX Enable [4:4] read-write DAC_TEST Analog test DAC current measurment [8:5] read-write DFE_TEST Analog test DFE taps current measurment [11:9] read-write RX_DTEST_CFG Digital Test Mux (DTEST) Configuration 0xDC 16 read-write 0x0 0x1F DDFT_SEL Digital test MUX Select [3:0] read-write DDFT_ENABLE Digital test MUX Enable [4:4] read-write SPARE_CFG Spare Configuration 0xE0 16 read-write 0x0 0xFFFF SPARE_OUT spare output pins [2:0] read-write SPARE_FT_OUT spare feedthrough outputs [15:3] read-write SPARE_STAT Spare Status 0xE4 16 read-only 0x0 0xFFFF SPARE_INPUTS spare input pints [2:0] read-only SPARE_FT_IN spare feedthrough inputs [15:3] read-only USB40PHY_PLL_SYS PHY PLL SYS registers 0x00000900 PLL_SDM_CFG Sigma-Delta Modulator (SDM) Configuration 0x0 16 read-write 0x0 0x1F SDM_ENABLE Sigma-Delta modulator enable, (active low power down), SSM will be down too [0:0] read-write DITHER_EN Sigma-Delta Modulator dither enable [1:1] read-write DITHER_GAIN dither gain value [4:2] read-write PLL_SSM_CFG0 Spread Spectrun Modulator (SSM) Configuration 0x4 16 read-write 0x0 0xFFFF DIVF_FRAC_MSB Feedback Divider Ratio fractional vlaue (if SSM is not enabled these input goes to SDM) [7:0] read-write DIVF_INTEGER Feedback Divider Ratio integer vlaue (if SSM is not enabled these input goes to SDM) [15:8] read-write PLL_SSM_CFG1 Spread Spectrun Modulator (SSM) Configuration 0x8 16 read-write 0x0 0xE3FF DIVF_FRAC_LSB Feedback Divider Ratio fractional vlaue (if SSM is not enabled these input goes to SDM) [9:0] read-write SPREAD SSM modulation depth setting [15:13] read-write PLL_SSM_CFG2 Spread Spectrun Modulator (SSM) Configuration 0xC 16 read-write 0x0 0x7FFF SSM_STEP_CNT SSM modulation triangle new value update count [8:0] read-write SSM_UPDATE_CNT SSM modulation triangle number of steps count [13:9] read-write SSM_ENABLE Spread spectrum modulator enable, (active low power down), SDM can be active [14:14] read-write PLL_AFC_CFG0 Automatic Frequency Control (AFC) Configuration 0x10 16 read-write 0x0 0xFFFF AFC_VCTL_SET N/A [2:0] read-write AFC_VCMP_PDB N/A [3:3] read-write AFC_VCMP_SEL N/A [7:4] read-write AFC_OVRD_CAPSEL Override value for capsel [14:8] read-write AFC_OVRRIDEN Override for capsel [15:15] read-write PLL_AFC_CFG1 Automatic Frequency Control (AFC) Configuration 0x14 16 read-write 0x0 0x3FFF AFC_VCTL_HI_CNT AFC vcontrol reset timer count [4:0] read-write AFC_VCTL_LO_CNT AFC vcontrol release timer count [9:5] read-write AFC_VCTL_ENABLE_OVERRIDE Override for afc_vctl_enable [10:10] read-write AFC_VCTL_ENABLE_OVERRIDE_VALUE Override value for afc_vctl_enable [11:11] read-write AFC_SEL_MIN Capsel min value select [12:12] read-write AFC_SEL_MAX Capsel max value select [13:13] read-write PLL_AFC_CFG2 Automatic Frequency Control (AFC) Configuration 0x18 16 read-write 0x0 0x7F AFC_CLKDIVSEL Refclk to FSM clk divide select [5:0] read-write AFC_PDB AFC active low power-down [6:6] read-write PLL_AFC_STAT Automatic Frequency Control (AFC) Status 0x1C 16 read-only 0x0 0x7F CAPSEL 'capsel' value for read [6:0] read-only PLL_AAC_CFG0 Automatic Amplitude Control (AAC) Configuration 0x20 16 read-write 0x0 0x3FF AACREFSEL Amplitude reference voltage select [3:0] read-write AAC_OVRD_AACSEL Override value for aacout [8:4] read-write AAC_OVRRIDEN AAC active low power-down [9:9] read-write PLL_AAC_CFG1 Automatic Amplitude Control (AAC) Configuration 0x24 16 read-write 0x0 0x1FF AAC_CLKDIVSEL Refclk to FSM clk divide select [5:0] read-write AAC_FRZCNT Freeze the counter output (aacout) [6:6] read-write AAC_NORECAL No recalibration after 1st lock [7:7] read-write AAC_PDB No recalibration after 1st lock [8:8] read-write PLL_AAC_STAT Automatic Amplitude Control (AAC) Status 0x28 16 read-only 0x0 0x1F AACSEL 'aacout' for read [4:0] read-only PLL_REFCKSEL_CFG Reference Clock Select (REFCLKSEL) Configuration 0x2C 16 read-write 0x0 0x7 REFCLKSEL Reference Clock MUX Select [2:0] read-write PLL_DIVR_CFG Reference Clock Divider (DIVR) Configuration 0x30 16 read-write 0x0 0xF LCDIVR DIVR Divider Ratio [3:0] read-write PLL_DIVP_CFG Post Divider (DIVP) Configuration 0x34 16 read-write 0x0 0xFF LCDIVP DIVP Divider Ratio, TX Clk [3:0] read-write LCBYPASS DIVP Divider Ratio, TX Clk [4:4] read-write TX0_DIVP_PDB DIVP Divider, power down, active low for output 0 [5:5] read-write TX1_DIVP_PDB DIVP Divider, power down, active low for output 1 [6:6] read-write PLL_SYNC_ENABLE pll_rstb synchronization enable, can be disable after sync is done [7:7] read-write PLL_DIVH_CFG HS Divider (DIVH) Configuration 0x38 16 read-write 0x0 0x3F HSREF_DIVH DIVH Divider Ratio, HSREF Clock [4:0] read-write HSREF_EN High-Speed Ref Clk Output Enable [5:5] read-write PLL_PFD_CFG Phase/Frequency Detector (PFD) Configuration 0x3C 16 read-write 0x0 0xF PFDDELAY Adjust dead-zone feedback delay [3:0] read-write PLL_CP_CFG Charge Pump (CP) Configuration 0x40 16 read-write 0x0 0x1FF CFGRCP Charge pump bias resistor adjustment [3:0] read-write ICPDAC Charge pump current adjustment [7:4] read-write CP_PDB Charge pump power down, active low [8:8] read-write PLL_LF_CFG Loop Filter (LF) Configuration 0x44 16 read-write 0x0 0x1F LF_RTUNE N/A [2:0] read-write LF_CTUNE N/A [4:3] read-write PLL_VCO_CFG Voltage-Controlled Oscillator (VCO) Configuration 0x48 16 read-write 0x0 0xFFF DCVARMODE VCO fix varactors DC bias voltage setting [3:0] read-write VCOVARCM1 VCO varactor#1 common mode voltage trimming [7:4] read-write VCOVARCM2 VCO varactor#2 common mode voltage trimming [11:8] read-write PLL_BIASGEN_CFG Bias Generator (BIASGEN) Configuration 0x4C 16 read-write 0x0 0x1F3F CFG_BIAS Adjust bias currents [5:0] read-write TERM_TRIM value for termination trim [12:8] read-write PLL_GNRL_CFG General Controls Configuration 0x50 16 read-write 0x0 0x7 PLL_PDB Global PLL active low power-down [0:0] read-write LKDT_RESETB main lock detect reset, active low [1:1] read-write RESETLOCKB lock detect, lock output reset, used for re-locking, active low [2:2] read-write PLL_VREG_CFG1 Regulators Configuration 0x54 16 read-write 0x0 0xFFFF VCPREGSEL Adjust voltage for charg-pump regulator [3:0] read-write VREGLCPLLSEL Adjust voltage for VCO Clock rate cells [7:4] read-write VREGREFSEL Adjust voltage for REFCK rate cells [11:8] read-write VREGDIGSEL Adjust voltage for async. Cells [15:12] read-write PLL_VREG_CFG2 Regulators Configuration 0x58 16 read-write 0x0 0x7F VCPREG_PDB charge-pump regulator powr down, active low [0:0] read-write VREGLCPLL_PDB LCPLL Regulator Power-Down [1:1] read-write VREGREF_PDB REF Regulator Power-Down [2:2] read-write VREGDIG_PDB DIG Regulator Power-Down [3:3] read-write VCPREG_BPB CP regulator bypass [4:4] read-write CPCLK_SEL CP regulator clock frequency select [5:5] read-write BURNIN Enable Burn-In mode [6:6] read-write PLL_VREG_STAT Regulators Status 0x5C 16 read-only 0x0 0x7 PWR_GOOD_LCPLL pwr_good_lcpll for read as status [0:0] read-only PWR_GOOD_REF pwr_good_ref for read as status [1:1] read-only PWR_GOOD_DIG pwr_good_dig for read as status [2:2] read-only PLL_LD_CFG Lock Detect Configuration 0x60 16 read-write 0x0 0x3F7 LOCKOS Frequency detect tolerance = +/- 0.025 percent*2^lockin [2:0] read-write DLFCNTSEL Filtered lock, #of refcklk cycles flock generated after lock [2^(flocksel+8)] [5:4] read-write LUDDIVSEL Lockup detect timer setting, cycles of refclk, 256 or 512 [6:6] read-write LUDDISABLE Lockup detect disable [7:7] read-write CRS_FD_AUXCLK_SEL Coarse frequency detect aux clock select [8:8] read-write CRS_FD_DISABLE Coarse frequency detect disable [9:9] read-write PLL_LD_STAT Lock Detect Status 0x64 16 read-only 0x0 0x1 FLOCK flock for read as status [0:0] read-only PLL_ATEST Analog Test Mux (ATEST) Configuration 0x68 16 read-write 0x0 0x1F ADFT_SEL Analog test MUX Select [3:0] read-write ADFT_ENABLE Analog test MUX Enable [4:4] read-write PLL_DTEST Digital Test Mux (DTEST) Configuration 0x6C 16 read-write 0x0 0x1F DDFT_SEL Digital test MUX Select [3:0] read-write DDFT_ENABLE Digital test MUX Enable [4:4] read-write SPARE_CFG Spare Configuration 0x70 16 read-write 0x0 0xFFFF SPARE_OUT spare output pins [2:0] read-write SPARE_FT_OUT spare feedthrough outputs [15:3] read-write SPARE_STAT Spare Status 0x74 16 read-only 0x0 0xFFFF SPARE_INPUTS spare input pins [2:0] read-only SPARE_FT_IN spare feedthrough inputs [15:3] read-only ADAPTER USB32 Adapter registers. 0x10000 is for Ingress and 0x20000 for egress Adapter 0x00010000 2 65536 DMA[%s] DMA Configuration Register 0x00000000 16 128 SCK[%s] Socket Registers 0x00008000 SCK_DSCR Descriptor Chain Pointer 0x0 32 read-write 0x0 0xFFFFFFFF DSCR_NUMBER Descriptor number of currently active descriptor. A value of 0xFFFF designates no (more) active descriptors available. When activating a socket CPU shall write number of first descriptor in here. Only modify this field when go_suspend=1 or go_enable=0 [15:0] read-write DSCR_COUNT Number of descriptors still left to process. This value is unrelated to actual number of descriptors in the list. It is used only to generate an interrupt to the CPU when the value goes low or zero (or both). When this value reaches 0 it will wrap around to 255. The socket will not suspend or be otherwise affected unless the descriptor chains ends with 0xFFFF descriptor number. [23:16] read-write DSCR_LOW The low watermark for dscr_count. When dscr_count is equal or less than dscr_low the status bit dscr_is_low is set and an interrupt can be generated (depending on int mask). [31:24] read-write SCK_SIZE Transfer Size Register 0x4 32 read-write 0x0 0xFFFFFFFF TRANS_SIZE The number of bytes or buffers (depends on unit bit in SCK_STATUS) that are part of this transfer. A value of 0 signals an infinite/undetermined transaction size. Valid data bytes remaining in the last buffer beyond the transfer size will be read by socket and passed on to the core. FW must ensure that no additional bytes beyond the transfer size are present in the last buffer. [31:0] read-write SCK_COUNT Transfer Count Register 0x8 32 read-write 0x0 0xFFFFFFFF TRANS_COUNT The number of bytes or buffers (depends on unit bit in SCK_STATUS) that have been transferred through this socket so far. If trans_size is >0 and trans_count>=trans_size the 'trans_done' bits in SCK_STATUS is both set. If SCK_STATUS.susp_trans=1 the socket is also suspended and the 'suspend' bit set. This count is updated only when a descriptor is completed and the socket proceeds to the next one. Exception: When socket suspends with PARTIAL_BUF=1, this value has been (incorrectly) incremented by 1 (UNIT=1) or DSCR_SIZE.BYTE_COUNT (UNIT=0). Firmware must correct this before resuming the socket. [31:0] read-write SCK_STATUS Socket Status Register 0xC 32 read-write 0x4E00000 0xFFFF87FF AVL_COUNT Number of available (free for ingress, occupied for egress) descriptors beyond the current one. This number is incremented by the adapter whenever an event is received on this socket and decremented whenever it activates a new descriptor. This value is used to create a signal to the IP Cores that indicates at least one buffer is available beyond the current one (sck_more_buf_avl). [4:0] read-write AVL_MIN Minimum number of available buffers required by the adapter before activating a new one. This can be used to guarantee a minimum number of buffers available with old data to implement rollback. If AVL_ENABLE, the socket will remain in STALL state until AVL_COUNT>=AVL_MIN. [9:5] read-write AVL_ENABLE Enables the functioning of AVL_COUNT and AVL_MIN. When 0, it will disable both stalling on AVL_MIN and generation of the sck_more_buf_avl signal described above. [10:10] read-write STATE Internal operating state of the socket. This field is used for debugging and to safely modify active sockets (see go_suspend). [17:15] read-only DESCR Descriptor state. This is the default initial state indicating the descriptor registers are NOT valid in the Adapter. The Adapter will start loading the descriptor from memory if the socket becomes enabled and not suspended. Suspend has no effect on any other state. 0 STALL Stall state. Socket is stalled waiting for data to be loaded into the Fetch Queue or waiting for an event. 1 ACTIVE Active state. Socket is available for core data transfers. 2 EVENT Event state. Core transfer is done. Descriptor is being written back to memory and an event is being generated if enabled. 3 CHECK1 Check states. An active socket gets here based on the core's EOP request to check the Transfer size and determine whether the buffer should be wrapped up. Depending on result, socket will either go back to Active state or move to the Event state. 4 SUSPENDED Socket is suspended 5 CHECK2 Check states. An active socket gets here based on the core's EOP request to check the Transfer size and determine whether the buffer should be wrapped up. Depending on result, socket will either go back to Active state or move to the Event state. 6 WAITING Waiting for confirmation that event was sent. 7 ZLP_RCVD Indicates the socket received a ZLP [18:18] read-only SUSPENDED Indicates the socket is currently in suspend state. In suspend mode there is no active descriptor; any previously active descriptor has been wrapped up, copied back to memory and SCK_DSCR.dscr_number has been updated using DSCR_CHAIN as needed. If the next descriptor is known (SCK_DSCR.dscr_number!=0xFFFF), this descriptor will be loaded after the socket resumes from suspend state. A socket can only be resumed by changing go_suspend from 1 to 0. If the socket is suspended while go_suspend=0, it must first be set and then again cleared. [19:19] read-only ENABLED Indicates the socket is currently enabled when asserted. After go_enable is changed, it may take some time for enabled to make the same change. This value can be polled to determine this fact. [20:20] read-only TRUNCATE Enable (1) or disable (0) truncating of BYTE_COUNT when TRANS_COUNT+BYTE_COUNT>=TRANS_SIZE. When enabled, ensures that an ingress transfer never contains more bytes then allowed. This function is needed to implement burst-based prototocols that can only transmit full bursts of more than 1 byte. [21:21] read-write EN_PROD_EVENTS Enable (1) or disable (0) sending of produce events from any descriptor in this socket. If 0, events will be suppressed, and the descriptor will not be copied back into memory when completed. [22:22] read-write EN_CONS_EVENTS Enable (1) or disable (0) sending of consume events from any descriptor in this socket. If 0, events will be suppressed, and the descriptor will not be copied back into memory when completed. [23:23] read-write SUSP_PARTIAL When set, the socket will suspend before activating a descriptor with BYTE_COUNT<BUFFER_SIZE. This is relevant for egress sockets only. [24:24] read-write SUSP_LAST When set, the socket will suspend before activating a descriptor with TRANS_COUNT+BUFFER_SIZE>=TRANS_SIZE. This is relevant for both ingress and egress sockets. [25:25] read-write SUSP_TRANS When set, the socket will suspend when trans_count >= trans_size. This equation is checked (and hence the socket will suspend) only at the boundary of buffers and packets (ie. buffer wrapup or EOP assertion). [26:26] read-write SUSP_EOP When set, the socket will suspend after wrapping up the first buffer with dscr.eop=1. Note that this function will work the same for both ingress and egress sockets. [27:27] read-write WRAPUP Setting this bit will forcibly wrap-up a socket, whether it is out of data or not. This option is intended mainly for ingress sockets, but works also for egress sockets. Any remaining data in fetch buffers is ignored, in write buffers is flushed. Transaction and buffer counts are updated normally, and suspend behavior also happens normally (depending on various other settings in this register).G45 [28:28] read-write UNIT Indicates whether descriptors (1) or bytes (0) are counted by trans_count and trans_size. Descriptors are counting regardless of whether they contain any data or have eop set. [29:29] read-write GO_SUSPEND Directs a socket to go into suspend mode when the current descriptor completes. The main use of this bit is to safely append descriptors to an active socket without actually suspending it (in most cases). The process is outlined in more detail in the architecture spec, and looks as follows: 1: GO_SUSPEND=1 2: modify the chain in memory 3: check if active descriptor is 0xFFFF or last in chain 4: if so, make corrections as neccessary (complicated) 5: clear any pending suspend interrupts (SCK_INTR[9:5]) 6: GO_SUSPEND=0 Note that the socket resumes only when SCK_INTR[9:5]=0 and GO_SUSPEND=0. [30:30] read-write GO_ENABLE Indicates whether socket is enabled. When go_enable is cleared while socket is active, ongoing transfers are aborted after an unspecified amount of time. No update occurs from the descriptor registers back into memory. When go_enable is changed from 0 to 1, the socket will reload the active descriptor from memory regardless of the contents of DSCR_ registers. The socket will not wait for an EVENT to become active if the descriptor is available and ready for transfer (has space or data). The 'enabled' bit indicates whether the socket is actually enabled or not. This field lags go_enable by an short but unspecificied of time. [31:31] read-write SCK_INTR Socket Interrupt Request Register 0x10 32 read-write 0x0 0x3FF PRODUCE_EVENT Indicates that a produce event has been received or transmitted since last cleared. [0:0] read-write CONSUME_EVENT Indicates that a consume event has been received or transmitted since last cleared. [1:1] read-write DSCR_IS_LOW Indicates that dscr_count has fallen below its watermark dscr_low. If dscr_count wraps around to 255 dscr_is_low will remain asserted until cleared by s/w [2:2] read-write DSCR_NOT_AVL Indicates the no descriptor is available. Not available means that the current descriptor number is 0xFFFF. Note that this bit will remain asserted until cleared by s/w, regardless of whether a new descriptor number is loaded. [3:3] read-write STALL Indicates the socket has stalled, waiting for an event signaling its descriptor has become available. Note that this bit will remain asserted until cleared by s/w, regardless of whether the socket resumes. [4:4] read-write SUSPEND Indicates the socket has gone into suspend mode. This may be caused by any hardware initiated condition (e.g. DSCR_NOT_AVL, any of the SUSP_*) or by setting GO_SUSPEND=1. Note that this bit will remain asserted until cleared by s/w, regardless of whether the suspend condition is resolved. Note that the socket resumes only when SCK_INTR[9:5]=0 and GO_SUSPEND=0. [5:5] read-write ERROR Indicates the socket is suspended because of an error condition (internal to the adapter) - if error=1 then suspend=1 as well. Possible error causes are: - dscr_size.buffer_error bit already set in the descriptor. - dscr_size.byte_count > dscr_size.buffer_size - core writes into an inactive socket. - core did not consume all the data in the buffer. Note that the socket resumes only when SCK_INTR[9:5]=0 and GO_SUSPEND=0. [6:6] read-write TRANS_DONE Indicates that TRANS_COUNT has reached the limit TRANS_SIZE. This flag is only set when SUSP_TRANS=1. Note that because TRANS_COUNT is updated only at the granularity of entire buffers, it is possible that TRANS_COUNT exceeds TRANS_SIZE before the socket suspends. Software must detect and deal with these situations. When asserting EOP to the adapter on ingress, the trans_count is not updated unless the socket actually suspends (see SUSP_TRANS). Note that the socket resumes only when SCK_INTR[9:5]=0 and GO_SUSPEND=0. [7:7] read-write PARTIAL_BUF Indicates that the (egress) socket was suspended because of SUSP_PARTIAL condition. Note that the socket resumes only when SCK_INTR[9:5]=0 and GO_SUSPEND=0. [8:8] read-write LAST_BUF Indicates that the socket was suspended because of SUSP_LAST condition. Note that the socket resumes only when SCK_INTR[9:5]=0 and GO_SUSPEND=0. [9:9] read-write SCK_INTR_MASK Socket Interrupt Mask Register 0x14 32 read-write 0x0 0x3FF PRODUCE_EVENT 1: Report interrupt to CPU [0:0] read-write CONSUME_EVENT 1: Report interrupt to CPU [1:1] read-write DSCR_IS_LOW 1: Report interrupt to CPU [2:2] read-write DSCR_NOT_AVL 1: Report interrupt to CPU [3:3] read-write STALL 1: Report interrupt to CPU [4:4] read-write SUSPEND 1: Report interrupt to CPU [5:5] read-write ERROR 1: Report interrupt to CPU [6:6] read-write TRANS_DONE 1: Report interrupt to CPU [7:7] read-write PARTIAL_BUF 1: Report interrupt to CPU [8:8] read-write LAST_BUF 1: Report interrupt to CPU [9:9] read-write DSCR_BUFFER Descriptor buffer base address register 0x20 32 read-write 0x0 0xFFFFFFFF BUFFER_ADDR The base address of the buffer where data is written. This address is not necessarily word-aligned to allow for header/trailer/length modification. [31:0] read-write DSCR_SYNC Descriptor synchronization pointers register 0x24 32 read-write 0x0 0xFFFFFFFF CONS_SCK The socket number of the consuming socket to which the produce event shall be sent. If cons_ip and cons_sck matches the socket's IP and socket number then the matching socket becomes consuming socket. [7:0] read-write CONS_IP The IP number of the consuming socket to which the produce event shall be sent. Use 0x3F to designate ARM CPU (so software) as consumer; the event will be lost in this case and an interrupt should also be generated to observe this condition. [13:8] read-write EN_CONS_EVENT Enable sending of a consume events from this descriptor only. Events are sent only if SCK_STATUS.en_consume_ev=1. When events are disabled, the adapter also does not update the descriptor in memory to clear its occupied bit. [14:14] read-write EN_CONS_INT Enable generation of a consume event interrupt for this descriptor only. This interrupt will only be seen by the CPU if SCK_STATUS.int_mask has this interrupt enabled as well. Note that this flag influences the logging of the interrupt in SCK_STATUS; it has no effect on the reporting of the interrupt to the CPU like SCK_STATUS.int_mask does. [15:15] read-write PROD_SCK The socket number of the producing socket to which the consume event shall be sent. If prod_ip and prod_sck matches the socket's IP and socket number then the matching socket becomes consuming socket. [23:16] read-write PROD_IP The IP number of the producing socket to which the consume event shall be sent. Use 0x3F to designate ARM CPU (so software) as producer; the event will be lost in this case and an interrupt should also be generated to observe this condition. [29:24] read-write EN_PROD_EVENT Enable sending of a produce events from this descriptor only. Events are sent only if SCK_STATUS.en_produce_ev=1. If 0, events will be suppressed, and the descriptor will not be copied back into memory when completed. [30:30] read-write EN_PROD_INT Enable generation of a produce event interrupt for this descriptor only. This interrupt will only be seen by the CPU if SCK_STATUS. int_mask has this interrupt enabled as well. Note that this flag influences the logging of the interrupt in SCK_STATUS; it has no effect on the reporting of the interrupt to the CPU like SCK_STATUS.int_mask does. [31:31] read-write DSCR_CHAIN Descriptor Chain Pointers Register 0x28 32 read-write 0x0 0xFFFFFFFF RD_NEXT_DSCR Descriptor number of the next task for consumer. A value of 0xFFFF signals end of this list. [15:0] read-write WR_NEXT_DSCR Descriptor number of the next task for producer. A value of 0xFFFF signals end of this list. [31:16] read-write DSCR_SIZE Descriptor Size Register 0x2C 32 read-write 0x0 0xFFFFFFFF MARKER A marker that is provided by s/w and can be observed by the IP. It's meaning is defined by the IP that uses it. This bit has no effect on the other DMA mechanisms. [0:0] read-write EOP A marker indicating this descriptor refers to the last buffer of a packet or transfer. Packets/transfers may span more than one buffer. The producing IP provides this marker by providing the EOP signal to its DMA adapter. The consuming IP observes this marker by inspecting its EOP return signal from its own DMA adapter. For more information see section on packets, buffers and transfers in DMA chapter. [1:1] read-write BUFFER_ERROR Indicates the buffer data is valid (0) or in error (1). [2:2] read-write BUFFER_OCCUPIED Indicates the buffer is in use (1) or empty (0). A consumer will interpret this as: 0: Buffer is empty, wait until filled. 1: Buffer has data that can be consumed A produce will interpret this as: 0: Buffer is ready to be filled 1: Buffer is occupied, wait until empty [3:3] read-write BUFFER_SIZE The size of the buffer in multiples of 16 bytes [15:4] read-write BYTE_COUNT The number of data bytes present in the buffer. An occupied buffer is not always full, in particular when variable length packets are transferred. [31:16] read-write EVENT Event Communication Register 0x7C 32 write-only 0x0 0x1FFFF ACTIVE_DSCR The active descriptor number for which the event is sent. [15:0] write-only EVENT_TYPE Type of event 0: Consume event descriptor is marked empty - BUFFER_OCCUPIED=0) 1: Produce event descriptor is marked full = BUFFER_OCCUPIED=1) [16:16] write-only SCK_GBL General DMA Registers 0x0000FF00 SCK_INTR Socket Interrupt Request Register 0x0 32 read-only 0x0 0xFFFFFFFF SCKINTR Socket <x> asserts interrupt when bit <x> is set in this vector. Multiple bits may be set to 1 simultaneously. This register is only as wide as the number of socket in the adapter; 256 is just the maximum width. All other bits always return 0. [31:0] read-only ADAPTER_DEBUG Adapter Debug Observation Register 0xF4 32 read-only 0x0 0xFFFFFFFF TS_COUNT Internal adapter state for debug observation [3:0] read-only TS_STATE Internal adapter state for debug observation [6:4] read-only TS_ID Internal adapter state for debug observation [12:7] read-only SS_COUNT Internal adapter state for debug observation [21:13] read-only SS_STATE Internal adapter state for debug observation [22:22] read-only SS_ID Internal adapter state for debug observation [28:23] read-only TS_ABORT Internal adapter state for debug observation [29:29] read-only BS_STATE Internal adapter state for debug observation [31:30] read-only ADAPTER_CONF Adapter Configuration Register 0xF8 32 read-write 0x0 0x7FFFFFFF FQ_THRESHOLD Number of words in a socket fetch queue (FQ) that must be present before sck_active asserts. Default value is FQ_SIZE, which means the entire FQ must fill up before sck_active asserts. NOTE: The default value for this field is FQ_DEPTH which are different for Egress/Ingress. [5:0] read-write STREAM_COUNT Number of burst requests to issue without examining the FQ depth (because IP Core can guarantee immediate consumption). [14:6] read-write STREAMING_MODE 0: Do not make fetch requests unless fetch queue has space to hold response (default). 1: Assume IP Core will drain all data as it comes in. Place fetch requests on bus as fast as possible (DO NOT USE UNLESS YOU KNOW WHAT YOU ARE DOING). [15:15] read-write TS_CYCLES Minimum cycles between prefetch requests to the bus. The adapter will wait for this number of cycles in between prefetch burst requests when activating a descriptor on a socket. If TS_CYCLES=0, the requests will be sent back-to-back (assuming queues are not full). [19:16] read-write ES_CYCLES Minimum cycles between fetch requests to the bus under normal operation. The adapter will wait for this number of cycles in between burst requests when refilling a fetch queue for a desriptor If ES_CYCLES=0, the requests may be sent back-to-back (assuming queues are not full). [23:20] read-write GBL_CYCLES Minimum cycles between any fetch requests to the bus. The adapter will wait for this number of cycles in between any fetch or prefetch burst requests when activating a descriptor on a socket. If GBL_CYCLES=0, the requests may be sent back-to-back (assuming queues are not full). [27:24] read-write MMIO_LOW_PRIORITY Sets priority between MMIO and Core requests: 0: fair arbitration. MMIO is guaranteed to win the next cycle if there was a collision with the core request in the first cycle. 1: low priority. MMIO will never win if the core has a request. [28:28] read-write SWITCH_HIGH_PRIORITY Socket swicth higher priority than interconnect [29:29] read-write TS_ABORT_EN Allow TS to be aborted [30:30] read-write ADAPTER_STATUS Adapter Global Status Fields 0xFC 32 read-only 0x0 0xFFFFFF TTL_SOCKETS Total number of sockets in this adapter. This number is different for each instance of the adapter and varies with the core IP needs. [7:0] read-only IG_ONLY First socket number that is ingress only. 0..IG_ONLY-1: Sockets capable of both in and egress IG_ONLY..TTL_SOCKETS-1: Ingress sockets only [15:8] read-only FQ_SIZE Number of words in a socket fetch queue (FQ). The total buffer space in the adapter is EG_SOCKETS*FQ_SIZE words of size WORD_SIZE. [21:16] read-only WORD_SIZE Internal word size of the prefetch queue (FQ); not the same as bus width of AHB bus or thread interface to the IP. 0: 32b 1: 64b 2: 128b 3: 256b [23:22] read-only LVDSSS LVDS IP Registers 0x404C0000 0 65536 registers LVDS LVDS IP register map 0x00000000 CTL IP Control Register 0x0 32 read-write 0x0 0x80000003 PHY_ENABLED 0 - PHY is under reset(excluding non-retention config registers) untill re-enabled again 1 - PHY is enabled and out of reset [0:0] read-write LINK_ENABLED 0 - LINK_LAYER is under reset(excluding non-retention config registers) untill re-enabled again 1 - LINK_LAYER is enabled and out of reset [1:1] read-write IP_ENABLED 0 - IP is held under reset(excluding non-retention config registers) untill re-enabled again. 1 - IP is enabled and out of reset. [31:31] read-write 2 4 LINK_CONFIG[%s] Link Configuration Register 0x4 32 read-write 0x0 0x17F LVDS_MODE Controls if link in configured as LVCMOS or LVDS link. 0 - LVCMOS 1 - LVDS [0:0] read-write GEARING_RATIO Indicates geraing ratio used by lanes of the link 0 - 1:1 1 - 2:1 2 - 4:1 3 - 8:1 In case of LVCMOS, Max gearing ratio to be used is 2:1 [2:1] read-write WIDE_LINK If set to 1, it implies both links are combined to form a wide link. This should be set only for link-0. Link-1 should always have this bit programmed to 0. [3:3] read-write NUM_LANES Indicates number of differential Lanes active for LVDS port. In case of LVCMOS indicates number of singled-ended Lanes active per port. For LVDS: 0 - 1x lane active. Ie Lane[0] 1 - 2x Lanes active. Ie Lane[1:0] 2 - 4x lanes active. Ie Lane[3:0] 3 - 8x lanes active ie Lane[7:0] 4 - 16x lanes active ie { Lane1[7:0], Lane0[7:0] } For LVCMOS, 0 - 8-lines active. ie Lane[7:0] 1 - 16-lines active. ie Lane[15:0] 2 - 24-lines active. ie { Lane1[7:0], Lane0[15:0] } 3 - 32-lines active. ie { Lane1[15:0], Lane0[15:0] } If 2-ports/links are combined to form a wider link, then GPIF-0 will serve this wider link and SW shouldn't enable GPIF-1 [6:4] read-write LINK_ENABLE When set Link is enabled [8:8] read-write THREAD_INTLV_CTL Thread interleave control register 0xC 32 read-write 0x0 0x3 TH0_TH1_INTERLEAVED Each thread has dedicated resources like payload count, event count, flags etc. And in general, only resources of a thread, specified by FPGA driven commands are updated. When this bit is set Thread 0 resources only are used for both 0 & 1 threads. Sockets/buffers are still maintained separately for both thread 0 & 1, irrespective of the value of this bit field. [0:0] read-write TH2_TH3_INTERLEAVED Each thread has dedicated resources like payload count, event count, flags etc. And in general, only resources of a thread, specified by FPGA driven commands are updated. When this bit is set Thread 0 resources only are used for both 2 & 3 threads. Sockets/buffers are still maintained separately for both thread 2 & 3, irrespective of the value of this bit field. [1:1] read-write LVDS_INTR LVDS Interrupt Request Register 0x10 32 read-write 0x0 0xFFFF00F7 GPIF0_INTERRUPT Indicates that the interrupt is from GPIF block. Consult GPIF_INTR register [0:0] read-only GPIF1_INTERRUPT Indicates that the interrupt is from GPIF block. Consult GPIF_INTR register [1:1] read-only PHY_INTERRUPT Indicates that the interrupt is from PHY block. Consult PHY_INTR register [2:2] read-only THREAD0_ERR Thread controller encountered an error and needs attention. FW clears this bit after handling the error. The error code is indicated in PIB_ERROR.PIB_ERR_CODE [4:4] read-write THREAD1_ERR Thread controller encountered an error and needs attention. FW clears this bit after handling the error. The error code is indicated in PIB_ERROR.PIB_ERR_CODE [5:5] read-write THREAD2_ERR Thread controller encountered an error and needs attention. FW clears this bit after handling the error. The error code is indicated in PIB_ERROR.PIB_ERR_CODE [6:6] read-write THREAD3_ERR Thread controller encountered an error and needs attention. FW clears this bit after handling the error. The error code is indicated in PIB_ERROR.PIB_ERR_CODE [7:7] read-write TH0_HDR_FLGS Flags which are set by LVDS commands to indicate frame/packet header/footer etc [19:16] read-write TH1_HDR_FLGS Flags which are set by LVDS commands to indicate frame/packet header/footer etc [23:20] read-write TH2_HDR_FLGS Flags which are set by LVDS commands to indicate frame/packet header/footer etc [27:24] read-write TH3_HDR_FLGS Flags which are set by LVDS commands to indicate frame/packet header/footer etc [31:28] read-write LVDS_INTR_MASK LVDS Interrupt Mask Register 0x14 32 read-write 0x0 0xFFFF00F7 GPIF0_INTERRUPT Mask for corresponding interrupt in LVDS_INTR [0:0] read-write GPIF1_INTERRUPT Mask for corresponding interrupt in LVDS_INTR [1:1] read-write PHY_INTERRUPT Mask for corresponding interrupt in LVDS_INTR [2:2] read-write THREAD0_ERR Mask for corresponding interrupt in LVDS_INTR [4:4] read-write THREAD1_ERR Mask for corresponding interrupt in LVDS_INTR [5:5] read-write THREAD2_ERR Mask for corresponding interrupt in LVDS_INTR [6:6] read-write THREAD3_ERR Mask for corresponding interrupt in LVDS_INTR [7:7] read-write TH0_HDR_FLGS Mask for corresponding interrupt in LVDS_INTR [19:16] read-write TH1_HDR_FLGS Mask for corresponding interrupt in LVDS_INTR [23:20] read-write TH2_HDR_FLGS Mask for corresponding interrupt in LVDS_INTR [27:24] read-write TH3_HDR_FLGS Mask for corresponding interrupt in LVDS_INTR [31:28] read-write LVDS_ERROR LVDS Error Indicator Register 0x20 32 read-only 0x0 0xFFFFF THREAD0_ERR_CODE The socket based link controller encountered an error and needs attention. Error codes are further described in BROS. Corresponds to interrupt bit THREAD_ERROR. [4:0] read-only TH0_DIR_ERROR Write being done to a Read Socket or Read being done to a write skt 0 THREAD1_ERR_CODE The socket based link controller encountered an error and needs attention. Error codes are further described in BROS. Corresponds to interrupt bit THREAD_ERROR. [9:5] read-only TH1_DIR_ERROR Write being done to a Read Socket or Read being done to a write skt 0 THREAD2_ERR_CODE The socket based link controller encountered an error and needs attention. Error codes are further described in BROS. Corresponds to interrupt bit THREAD_ERROR. [14:10] read-only TH2_DIR_ERROR Write being done to a Read Socket or Read being done to a write skt 0 THREAD3_ERR_CODE The socket based link controller encountered an error and needs attention. Error codes are further described in BROS. Corresponds to interrupt bit THREAD_ERROR. [19:15] read-only TH3_DIR_ERROR Write being done to a Read Socket or Read being done to a write skt 0 LVDS_EOP_EOT LVDS EOP/EOT configuration 0x24 32 read-write 0x1 0xFFFFFFFF EOP_EOT_CFG This register specifies how EOP bits are set or interpretted for Ingress and Egress sockets respectively. 1: Packet mode behavior 0: Stream mode behavior See Architecture Spec for details. [31:0] read-write GPIF_DATA_CTRL Data Control Register 0x30 32 read-write 0x0 0xFFFF ING_DATA_VALID Indicates data available in INGRESS_DATA. Cleared by s/w when data processed. [3:0] read-write EG_DATA_VALID Software writes 1 to indicate a valid word is present in the address register. Hardware writes 0 to indicate that the data is used and new word can be written. [7:4] read-write IN_ADDR_VALID Indicates address available in INGRESS_ADDRESS. Cleared by s/w when address processed. [11:8] read-write EG_ADDR_VALID Software writes 1 to indicate a valid word is present in the address register. Hardware writes 0 to indicate that the data is used and new word can be written. [15:12] read-write 2 4 GPIF_CLK_SEL[%s] GPIF Clock selection Register 0x34 32 read-write 0x4 0xD GPIC_CLK_SRC GPIF runs on clock which has different sources. This register field selects the clock sources. 0 - usb 480 MHz clock source 1 - peri clock [0:0] read-write USB_CLK_DIV_VAL This register field is valid only when GPIF clock source is USB 480MHz clock. 0 - Invalid 1 - Div by 2 2 - Div by 3 3 - Div by 4 [3:2] read-write TIME_STAMP_CLK_DW0 Timestamp counter 0x50 32 read-only 0x0 0xFFFFFFFF TS_WD0 LSB 2-bytes of free running timestamp counter. [15:0] read-only TS_WD1 Middle 2-bytes of free running timestamp counter. [31:16] read-only TIME_STAMP_CLK_DW1 Timestamp counter 0x54 32 read-only 0x0 0xFFFFFFFF TS_WD2 Middle 2-bytes of free running timestamp counter. [15:0] read-only TS_WD3 MSB 2-bytes of free running timestamp counter. [31:16] read-only 64 4 TH0_TH1_METADATA_RAM[%s] Metadata Memory 0x100 32 read-write 0x0 0xFFFFFFFF METADATA Metadata [31:0] read-write 64 4 TH2_TH3_METADATA_RAM[%s] Metadata Memory 0x200 32 read-write 0x0 0xFFFFFFFF METADATA Metadata [31:0] read-write 4 128 THREAD[%s] Set of registers for a thread 0x00000400 GPIF_INGRESS_DATA_WORD0 Socket Ingress Data 0x0 32 read-only 0x0 0xFFFFFFFF DATA Ingress Data. 4 registers together will hold 128-bits of GPIF_BUS_CONFIG.BUS_WIDTH. No packing/unpacking is done. MSB's of combined value {WORD3, WORD2, WORD1, WORD0} will be 0s [31:0] read-only GPIF_INGRESS_DATA_WORD1 Socket Ingress Data 0x4 32 read-only 0x0 0xFFFFFFFF DATA Ingress Data. 4 registers together will hold 128-bits of GPIF_BUS_CONFIG.BUS_WIDTH. No packing/unpacking is done. MSB's of combined value {WORD3, WORD2, WORD1, WORD0} will be 0s [31:0] read-only GPIF_INGRESS_DATA_WORD2 Socket Ingress Data 0x8 32 read-only 0x0 0xFFFFFFFF DATA Ingress Data. 4 registers together will hold 128-bits of GPIF_BUS_CONFIG.BUS_WIDTH. No packing/unpacking is done. MSB's of combined value {WORD3, WORD2, WORD1, WORD0} will be 0s [31:0] read-only GPIF_INGRESS_DATA_WORD3 Socket Ingress Data 0xC 32 read-only 0x0 0xFFFFFFFF DATA Ingress Data. 4 registers together will hold 128-bits of GPIF_BUS_CONFIG.BUS_WIDTH. No packing/unpacking is done. MSB's of combined value {WORD3, WORD2, WORD1, WORD0} will be 0s [31:0] read-only GPIF_EGRESS_DATA_WORD0 Socket Egress Data 0x10 32 read-write 0x0 0xFFFFFFFF DATA Egress Data. Both WORD1 and WORD0 will old only 64-bits of GPIF_BUS_CONFIG.BUS_WIDTH. No packing/unpacking is done. MSB's of combined value {WORD1, WORD0} is ignored. [31:0] read-write GPIF_EGRESS_DATA_WORD1 Socket Egress Data 0x14 32 read-write 0x0 0xFFFFFFFF DATA Egress Data. Both WORD1 and WORD0 will old only 64-bits of GPIF_BUS_CONFIG.BUS_WIDTH. No packing/unpacking is done. MSB's of combined value {WORD1, WORD0} is ignored. [31:0] read-write GPIF_INGRESS_ADDRESS Thread Ingress Address 0x18 32 read-only 0x0 0xFFFFFFFF ADDRESS Ingress Address [31:0] read-only GPIF_EGRESS_ADDRESS Thread Egress Address 0x1C 32 read-write 0x0 0xFFFFFFFF ADDRESS Egress Address [31:0] read-write GPIF_THREAD_CONFIG Thread Configuration Register 0x20 32 read-write 0x10400 0xBFFF0F9F THREAD_SOCK Active Socket Number for this thread. Can be written by software for fixed socket assignment.(all threads) Can be modified by h/w as result of PP_DMA_XFER accesses (only for thread 0) Can be modified by h/w as result of alpha 'sample AIN' (all threads. HW can only modify bits [4:2] of this field) [4:0] read-write WM_CFG 0: Assert partial flag when number of samples (remaining available for reading/writing) is less than or equal to the watermark. 1: Assert when samples are more than the watermark. [7:7] read-write BURST_SIZE Log2 of burst size ( 1: 2 words, 2: 4 words, etc). Programmed to support systems that work with fixed burst sizes. A burst is defined as a portion of transfer that unconditionally completes once initiated. The system must always transfer an entire burst before responding to a change in a partial flag . In transfers that involve short packet, the PIB HW will automatically append zeros/truncate data to do its part in preserving the above mentioned definition of burst. Burst size is a power of 2 and must be programmed to a value greater than watermark when partial flag is used.Buffer sizes used should be integral multiple of the burst size. Maximum value is 14. When value is >0, any socket switching must occur on 8 byte boundaries.Besides, this field needs to be programmed to a non-zero value to support bandwidth>200MBps on P-Port. [11:8] read-write WATERMARK Watermark position. Indicates number words that would be subtracted from the end of usable space/data. Watermark needs to be programmed to a value greater than the round trip flag latency of the system. This latency is a sum of three quantities namely (1) Benicia latency between seeing the end of the last burst that completely fills the buffer to the time the full/empty flag updates (can be calculated from generic gpif params), (2). Expected time of arrival of a flow control signal that would prevent the AP from issuing the next burst (as measured from the end of the burst) (3). Any additional group latency between the APs dma controller logic and the interface pins in both directions. 'end of usable space/data' is calculated using one of the equations depending on the context. (1) For normal write transfers in either PP modes, this is the size of the buffer to be produced into. (2) For normal read transfers in either PP modes, this is the byte count of the buffer to be consumed. (3) For partial buffer read or write transfers in PP mode 1, this is the value of written by AP into the PP_DMA_SIZE register rounded up to an integral number of BURSTSIZE quanta. [29:16] read-write ENABLE_THREAD_CTLR Enables the threadcontroller for operation. Can be set by firmware after initializing THEAD_SOCK and other fields. Will be set by h/w when THREAD_SOCK is written to by h/w. [31:31] read-write VARW Variable Register 0x30 32 read-only 0x0 0xFFFFFFFF VARW_WD0 Variable Word 0 [15:0] read-only VARW_WD1 Variable Word 1 [31:16] read-only PTSSS PTS snapshot register 0x34 32 read-only 0x0 0xFFFFFFFF PTSSS_WD0 PTS timer value [15:0] read-only PTSSS_WD1 PTS timer value [31:16] read-only SCRSS_DW0 SCR snapshot register 0x38 32 read-only 0x0 0xFFFFFFFF SCRSS_WD0 LSB 2-bytes of SCR timer value [15:0] read-only SCRSS_WD1 Middle 2-bytes of SCR timer value [31:16] read-only SCRSS_DW1 SCR snapshot register 0x3C 32 read-only 0x0 0xFFFF SCRSS_WD2 MSB 2-bytes of SCR timer, which is nothing but frame number [15:0] read-only HDR_FLGS Header Flags 0x40 32 read-only 0x0 0xF FLG Flags for indicating frame/line/packet header, footer etc. These flags will be set or clear by FPGA. Setting/Clearing of these flags will raise an interrupt to CPU. [3:0] read-only EVC_VAR0_DW0 Event Count Variable0 0x50 32 read-only 0x0 0xFFFFFFFF EVC_V0_WD0 Bytes 1 and 0 of 8-byte event counter [15:0] read-only EVC_V0_WD1 Bytes 2 and 3 of 8-byte event counter [31:16] read-only EVC_VAR0_DW1 Event Count Variable0 0x54 32 read-only 0x0 0xFFFFFFFF EVC_V0_WD2 Bytes 5 and 4 of 8-byte event counter [15:0] read-only EVC_V0_WD3 Bytes 7 and 6 of 8-byte event counter [31:16] read-only EVC_VAR1_DW0 Event Count Variable1 0x58 32 read-only 0x0 0xFFFFFFFF EVC_V1_WD0 Bytes 1 and 0 of 8-byte event counter [15:0] read-only EVC_V1_WD1 Bytes 2 and 3 of 8-byte event counter [31:16] read-only EVC_VAR1_DW1 Event Count Variable1 0x5C 32 read-only 0x0 0xFFFFFFFF EVC_V1_WD2 Bytes 5 and 4 of 8-byte event counter [15:0] read-only EVC_V1_WD3 Bytes 7 and 6 of 8-byte event counter [31:16] read-only PLC_DW0 Payload Count register 0x60 32 read-only 0x0 0xFFFFFFFF PLC_WD0 Bytes 1 and 0 of 8-byte data payload counter. Gets incremented during data transfers if EPC (Enable Payload Count), command was sent on LVDS control lane previously [15:0] read-only PLC_WD1 Bytes 3 and 2 of 8-byte of data payload counter. Gets incremented during data transfers if EPC (Enable Payload Count), command was sent on LVDS control lane previously [31:16] read-only PLC_DW1 Payload Count register 0x64 32 read-only 0x0 0xFFFFFFFF PLC_WD2 Bytes 5 and 4 of 8-byte data payload counter. Gets incremented during data transfers if EPC (Enable Payload Count), command was sent on LVDS control lane previously [15:0] read-only PLC_WD3 Bytes 7 and 6 of 8-byte of data payload counter. Gets incremented during data transfers if EPC (Enable Payload Count), command was sent on LVDS control lane previously [31:16] read-only PAYLOAD_CFG Payload Config register 0x68 32 read-write 0x0 0x3 CNT_MDATA_AS_PAYLOAD Include metadata as part of payload count [0:0] read-write CNT_CRC_AS_PAYLOAD Include CRC as part of payload count [1:1] read-write CRC CRC 0x6C 32 read-write 0x0 0xFFFFFFFF INITIAL_VALUE Initial CRC value. Whenever CLRCRC command is received, CRC calculator will be loaded with this initial value. [15:0] read-write CRC_VALUE Holds 16-bit CRC calculated on received payload data. Polynomila used is X16 + X12 + X5 + 1 [31:16] read-only MD0_CTRL Metadata-0 Control word 0x70 32 read-write 0x0 0xFFFFFFFF MD_REF_CTL Each bit of this field controls whether value present in Metadata ram is a constant or reference to a register, whose value should be used as Metadata. 0 - Metadata constant value 1 - Reference to Register Variable whose address is specified in Metadata [26:0] read-write MD_SIZE Holds the size in bytes of metadata to be inserted. Should be programmed to even number only (ie multiple of 2 bytes). Allowed values are 0, 2, 4, 6, 8......30. 0 - indicates 32 bytes If Odd value is programmed, then it'll be converted to immediate lower even value and used(ie if programmed to 9, it'll be used as 8) [31:27] read-write MD1_CTRL Metadata-1 Control word 0x74 32 read-write 0x0 0xFFFFFFFF MD_REF_CTL Each bit of this field controls whether value present in Metadata ram is a constant or reference to a register, whose value should be used as Metadata. 0 - Metadata constant value 1 - Reference to Register Variable whose address is specified in Metadata [26:0] read-write MD_SIZE Holds the size in bytes of metadata to be inserted. Should be programmed to even number only (ie multiple of 2 bytes). Allowed values are 0, 2, 4, 6, 8......30. 0 - indicates 32 bytes If Odd value is programmed, then it'll be converted to immediate lower even value and used(ie if programmed to 9, it'll be used as 8) [31:27] read-write MD2_CTRL Metadata-2 Control word 0x78 32 read-write 0x0 0xFFFFFFFF MD_REF_CTL Each bit of this field controls whether value present in Metadata ram is a constant or reference to a register, whose value should be used as Metadata. 0 - Metadata constant value 1 - Reference to Register Variable whose address is specified in Metadata [26:0] read-write MD_SIZE Holds the size in bytes of metadata to be inserted. Should be programmed to even number only (ie multiple of 2 bytes). Allowed values are 0, 2, 4, 6, 8......30. 0 - indicates 32 bytes If Odd value is programmed, then it'll be converted to immediate lower even value and used(ie if programmed to 9, it'll be used as 8) [31:27] read-write MD3_CTRL Metadata-3 Control word 0x7C 32 read-write 0x0 0xFFFFFFFF MD_REF_CTL Each bit of this field controls whether value present in Metadata ram is a constant or reference to a register, whose value should be used as Metadata. 0 - Metadata constant value 1 - Reference to Register Variable whose address is specified in Metadata [26:0] read-write MD_SIZE Holds the size in bytes of metadata to be inserted. Should be programmed to even number only (ie multiple of 2 bytes). Allowed values are 0, 2, 4, 6, 8......30. 0 - indicates 32 bytes If Odd value is programmed, then it'll be converted to immediate lower even value and used(ie if programmed to 9, it'll be used as 8) [31:27] read-write 2 12288 GPIF[%s] GPIF-II Configuration Registers 0x00001000 GPIF_CONFIG GPIF Configuration Register 0x0 32 read-write 0x0 0x8BC87 CTRL_COMP_ENABLE 1: Enable the control Comparator 0: Disable it. [0:0] read-write ADDR_COMP_ENABLE 1: Enable the address Comparator 0: Disable it. [1:1] read-write DATA_COMP_ENABLE 1: Enable the data Comparator 0: Disable it. [2:2] read-write DOUT_POP_EN 1: Use update_dout (alpha) to also trigger rq_pop (which is normally beta) 0: rq_pop is a separate beta [7:7] read-write ENDIAN Endianness of interface when PP_MODE==0 0: Little Endian 1: Big Endian [10:10] read-write ADDR_COMP_TOGGLE 1: Comparator outputs true when any of the unmasked bits change value. 0: Comparator outputs true when bits match a target value. [11:11] read-write CTRL_COMP_TOGGLE 1: Comparator outputs true when any of the unmasked bits change value. 0: Comparator outputs true when bits match a target value. [12:12] read-write DATA_COMP_TOGGLE 1: Comparator outputs true when any of the unmasked bits change value. 0: Comparator outputs true when bits match a target value. [13:13] read-write THREAD_IN_STATE 0: Normal operation 1: The thread number for an operation comes from the state description rather than the THREAD_CONFIG register (see GPIF_Modes for more information) [15:15] read-write A7OVERRIDE Overrides the use of AIN[7] to enable selection of register versus DMA access on different pins in PP_MODE=1. If A7OVERRIDE=1, register accesses are determined by beta(pp_access) instead. [19:19] read-write GPIF_BUS_CONFIG Bus Configuration Register 0x4 32 read-write 0x0 0xFF1DFFF0 ADR_CTRL Number of control lines overridden by address lines. Control signals CTRL[15] to CTRL[16-ADR_CTRL] are not connected to pins. Instead those pins are designated as address signals. Which address signals depends on the other mode fields above; see architecture spec for details. In other words: if ADR_CTRL=0 all CTRL lines are connected to pins, if ADR_CTRL=1, CTRL[15] is not connected and so on. [8:4] read-write CE_PRESENT CTRL[0] is CE and should be used to disable DQ drivers [9:9] read-write WE_PRESENT CTRL[1] is WE and should be used to disable DQ drivers Can be used together with DLE_PRESENT [10:10] read-write DATA_VLD_PRESENT When this bit is set to 1, CTRL[5] pin value will decide if DQ[7:0] will carry data or control byte information in LVCMOS mode. 1: CTRL[5] = 0, then DQ[7:0] is carrying control_byte 1: CTRL[5] = 1, then DQ[7:0] is carrying data byte [11:11] read-write OE_PRESENT CTRL[2] is OE and should be used to tri-state DQ lines. If WE_PRESENT=1 also, then OE will take precedence over WE. In other words, when WE is asserted, then output drivers are off, regardless of value of OE input. [12:12] read-write DRQ_PRESENT CTRL[4] is directly influenced by CTRL[3]/DACK as defined by DRQ_MODE This setting also overrides the CTRL_BUS_SELECT selection for this pin, in favor of betas 'assert drq' and 'deassert_drq' [13:13] read-write FIO0_PRESENT CTRL[7] is to be treated as IO that is driven out when the alpha specified in FIO0_CONF is asserted (ignore CTRL_BUS_DIRECTION) [14:14] read-write FIO1_PRESENT CTRL[8] is to be treated as IO that is driven out when the alpha specified in FIO1_CONF is asserted (ignore CTRL_BUS_DIRECTION) [15:15] read-write CNTR_PRESENT CTRL[9] is connected to the selected control counter bit instead of a control signal [16:16] read-write DRQ_MODE 0: Assert DRQ on deassertion of DACK 1: Assert DRQ on assertion of DACK 2: Deassert DRQ on deassertion of DACK 3: Deassert DRQ on assertion of DACK [19:18] read-write DRQ_ASSERT_MODE 1: Assert DRQ on rising edge of DMA_READY. Typical case, DRQ_MODE=2, this bit 1. 0: Do nothing [20:20] read-write FIO0_CONF Designates control to be used to enable output drivers of FIO0 (CTRL[7]) 0 to 3: Use the alpha 4 to 7 to switch FIO0 direction. 8-11: Use beta 0-3. [27:24] read-write FIO1_CONF Designates control to be used to enable output drivers of FIO1 (CTRL[8]) 0 to 3: Use the alpha 4-7 to switch FIO1 direction. 8-11: Use beta 0-3. [31:28] read-write GPIF_BUS_CONFIG2 Bus Configuration Register #2 0x8 32 read-write 0x0 0x3F3F3F07 STATE_FROM_CTRL 0: Normal operation 1,2,3: STATE7 indicates Lambda number to be used for state number bit 7 2,3: STATE6 indicates Lambda number to be used for state number bit 6 3: STATE5 indicates Lambda number to be used for state number bit 5 [2:0] read-write STATE5 Lambda number to be used for state number bit 5 [13:8] read-write STATE6 Lambda number to be used for state number bit 6 [21:16] read-write STATE7 Lambda number to be used for state number bit 7 [29:24] read-write GPIF_AD_CONFIG Address/Data configuration register 0xC 32 read-write 0x0 0xF03FF DQ_OEN_CFG N/A [1:0] read-write A_OEN_CFG N/A [3:2] read-write AIN_SELECT 0: Connect AIN to the active socket number of thread specified by AIN_DATA 1: Connect AIN to INGRESS_ADDRESS register 2: Connect AIN to the socket pointed to by ADDRESS_THREAD register [5:4] read-write AOUT_SELECT 0: Connect AOUT to ADDR_COUNTER 1: Connect AOUT to EGRESS_ADDRESS register 2: Connect AOUT to the socket pointed to by ADDRESS_THREAD register [7:6] read-write DOUT_SELECT 0: Connect DOUT to the socket pointed to by AIN_DATA or EGRESS_DATA register (as determined by beta 'register_access') 1: Connect DOUT to DATA_COUNTER [8:8] read-write AIN_DATA This field determines which thread number to use for data accesses: 0: specified by A1:A0. 1: specified by DATA_THREAD If AIN_SELECT=0 this field also determines the thread number for which to change the active socket on awq_push: 0: The active socket of thread A1:A0 is changed (3 bits only) 1: The active socket of thread DATA_THREAD is changed (full 5 bits) [9:9] read-write ADDRESS_THREAD Thread number to be used for addresses;only relevant when AIN_SELECT!=0 When this register is used to select the thread it must have been initialized by firmware. When both are used, ADDRESS_THREAD must be different from DATA_THREAD. [17:16] read-write DATA_THREAD Thread number to be used for data; only relevant when AIN_DATA=1 When this register is used to select the thread it must have been initialized by firmware. When both are used, ADDRESS_THREAD must be different from DATA_THREAD. [19:18] read-write GPIF_STATUS GPIF Status Register 0x10 32 read-only 0xF0000 0xFFFF07FF GPIF_DONE 1: GPIF has reached the DONE state. Non sticky. [0:0] read-only GPIF_INTR Indicates that GPIF state machine has raised an interrupt. [1:1] read-only SWITCH_TIMEOUT Indicates that the SWITCH_TIMEOUT was reached (see WAVEFORM_SWITCH). This bit clears when a new WAVEFORM_SWTICH is initiated. [2:2] read-only CRC_ERROR Indicates that an incorrect CRC was received [3:3] read-only ADDR_COUNT_HIT Address counter is at limit [4:4] read-only DATA_COUNT_HIT Data counter is at limit [5:5] read-only CTRL_COUNT_HIT Control counter is at limit [6:6] read-only ADDR_COMP_HIT Address comparator hits [7:7] read-only DATA_COMP_HIT Data comparator hits [8:8] read-only CTRL_COMP_HIT Control comparator hits [9:9] read-only WAVEFORM_BUSY CPU tried to access waveform memory w/o clearing WAVEFORM_VALID [10:10] read-only EG_DATA_EMPTY Indicates corresponding EGRESS_DATA register is empty [19:16] read-only IN_DATA_VALID Indicates corresponding INGRESS_DATA register is full. [23:20] read-only INTERRUPT_STATE State that raised the interrupt through GPIF_INTR. Pl. note that these bits do not have individual interrupt and mask bits in GPIF_INTR and GPIF_MASK [31:24] read-only GPIF_INTR GPIF Interrupt Request Register 0x14 32 read-write 0x0 0x7FFF07FF GPIF_DONE Interrupt request corresponding to same bit in GPIF_STATUS [0:0] read-write GPIF_INTR Interrupt request corresponding to same bit in GPIF_STATUS [1:1] read-write SWITCH_TIMEOUT Interrupt request corresponding to same bit in GPIF_STATUS [2:2] read-write CRC_ERROR Interrupt request corresponding to same bit in GPIF_STATUS [3:3] read-write ADDR_COUNT_HIT Interrupt request corresponding to same bit in GPIF_STATUS [4:4] read-write DATA_COUNT_HIT Interrupt request corresponding to same bit in GPIF_STATUS [5:5] read-write CTRL_COUNT_HIT Interrupt request corresponding to same bit in GPIF_STATUS [6:6] read-write ADDR_COMP_HIT Interrupt request corresponding to same bit in GPIF_STATUS [7:7] read-write DATA_COMP_HIT Interrupt request corresponding to same bit in GPIF_STATUS [8:8] read-write CTRL_COMP_HIT Interrupt request corresponding to same bit in GPIF_STATUS [9:9] read-write WAVEFORM_BUSY Interrupt request corresponding to same bit in GPIF_STATUS [10:10] read-write EG_DATA_EMPTY Interrupt request corresponding to same bit in GPIF_STATUS [19:16] read-write IN_DATA_VALID Interrupt request corresponding to same bit in GPIF_STATUS [23:20] read-write GPIF_ERR An error occurred in the GPIF. FW clears this bit after handling the error. The error code is indicated in GPIF_ERR_CODE [24:24] read-write INVLD_CMD_DET Unspecified command identified on LVDS Control Byte [25:25] read-write IDLE_CMD_DET Unspecified command identified on LVDS Control Byte [26:26] read-write LINK_IDLE_INTF_CLK_OFF Interface clock is off for programmable duration [27:27] read-write LINK_IDLE Continuous IDLE commands are received for programmable duration [28:28] read-write TRAINING_DONE Training is done and link is locked [29:29] read-write PHY_LINK_FF_OVERLOW N/A [30:30] read-write GPIF_INTR_MASK GPIF Interrupt Mask Register 0x18 32 read-write 0x0 0x7FFF07FF GPIF_DONE Mask bit that controls reporting of corresponding bit in GPIF_INTR [0:0] read-write GPIF_INTR Mask bit that controls reporting of corresponding bit in GPIF_INTR [1:1] read-write SWITCH_TIMEOUT Mask bit that controls reporting of corresponding bit in GPIF_INTR [2:2] read-write CRC_ERROR Mask bit that controls reporting of corresponding bit in GPIF_INTR [3:3] read-write ADDR_COUNT_HIT Mask bit that controls reporting of corresponding bit in GPIF_INTR [4:4] read-write DATA_COUNT_HIT Mask bit that controls reporting of corresponding bit in GPIF_INTR [5:5] read-write CTRL_COUNT_HIT Mask bit that controls reporting of corresponding bit in GPIF_INTR [6:6] read-write ADDR_COMP_HIT Mask bit that controls reporting of corresponding bit in GPIF_INTR [7:7] read-write DATA_COMP_HIT Mask bit that controls reporting of corresponding bit in GPIF_INTR [8:8] read-write CTRL_COMP_HIT Mask bit that controls reporting of corresponding bit in GPIF_INTR [9:9] read-write WAVEFORM_BUSY Mask bit that controls reporting of corresponding bit in GPIF_INTR [10:10] read-write EG_DATA_EMPTY Mask bit that controls reporting of corresponding bit in GPIF_INTR [19:16] read-write IN_DATA_VALID Mask bit that controls reporting of corresponding bit in GPIF_INTR [23:20] read-write GPIF_ERR N/A [24:24] read-write INVLD_CMD_DET N/A [25:25] read-write IDLE_CMD_DET N/A [26:26] read-write LINK_IDLE_INTF_CLK_OFF N/A [27:27] read-write LINK_IDLE N/A [28:28] read-write TRAINING_DONE N/A [29:29] read-write PHY_LINK_FF_OVERLOW N/A [30:30] read-write GPIF_INTR_MASKED GPIF Interrupt Generator 0x1C 32 read-only 0x0 0x7FFF07FF GPIF_DONE N/A [0:0] read-only GPIF_INTR N/A [1:1] read-only SWITCH_TIMEOUT N/A [2:2] read-only CRC_ERROR N/A [3:3] read-only ADDR_COUNT_HIT N/A [4:4] read-only DATA_COUNT_HIT N/A [5:5] read-only CTRL_COUNT_HIT N/A [6:6] read-only ADDR_COMP_HIT N/A [7:7] read-only DATA_COMP_HIT N/A [8:8] read-only CTRL_COMP_HIT N/A [9:9] read-only WAVEFORM_BUSY N/A [10:10] read-only EG_DATA_EMPTY N/A [19:16] read-only IN_DATA_VALID N/A [23:20] read-only GPIF_ERR N/A [24:24] read-only INVLD_CMD_DET N/A [25:25] read-only IDLE_CMD_DET N/A [26:26] read-only LINK_IDLE_INTF_CLK_OFF N/A [27:27] read-only LINK_IDLE N/A [28:28] read-only TRAINING_DONE N/A [29:29] read-only PHY_LINK_FF_OVERLOW N/A [30:30] read-only GPIF_INTR_SET GPIF Interrupt Set Register 0x20 32 read-write 0x0 0x7FFF07FF GPIF_DONE N/A [0:0] read-write GPIF_INTR N/A [1:1] read-write SWITCH_TIMEOUT N/A [2:2] read-write CRC_ERROR N/A [3:3] read-write ADDR_COUNT_HIT N/A [4:4] read-write DATA_COUNT_HIT N/A [5:5] read-write CTRL_COUNT_HIT N/A [6:6] read-write ADDR_COMP_HIT N/A [7:7] read-write DATA_COMP_HIT N/A [8:8] read-write CTRL_COMP_HIT N/A [9:9] read-write WAVEFORM_BUSY N/A [10:10] read-write EG_DATA_EMPTY N/A [19:16] read-write IN_DATA_VALID N/A [23:20] read-write GPIF_ERR N/A [24:24] read-write INVLD_CMD_DET N/A [25:25] read-write IDLE_CMD_DET N/A [26:26] read-write LINK_IDLE_INTF_CLK_OFF N/A [27:27] read-write LINK_IDLE N/A [28:28] read-write TRAINING_DONE N/A [29:29] read-write PHY_LINK_FF_OVERLOW N/A [30:30] read-write GPIF_ERROR GPIF Error Register 0x24 32 read-only 0x0 0x1F GPIF_ERR_CODE Error code for the first error code since ERROR=1 Error codes are specified in detail the USB30PIB BROS. [4:0] read-only IN_ADDR_OVER_WRITE Attempt to push to the active address thread which is not dma_ready 1 EG_ADDR_NOT_VALID Attempt to push to the active address thread which is not dma_ready 2 DMA_DATA_RD_ERROR Attempt to push to the active address thread which is not dma_ready 3 DMA_DATA_WR_ERROR Attempt to push to the active address thread which is not dma_ready 4 DMA_ADDR_RD_ERROR Attempt to push to the active address thread which is not dma_ready 5 DMA_ADDR_WR_ERROR Attempt to push to the active address thread which is not dma_ready 6 INVALID_STATE_ERROR statemachine has transitioned to an invalid state 8 GPIF_CTRL_BUS_DIRECTION_0 Control Bus in/out direction 0x28 32 read-write 0x0 0xFFFFFFFF DIRECTION Bit at (bit_number/2) has following direction: 00: Input 01:Output 10: Bidirectional IO. 11: Open drain IO. [31:0] read-write GPIF_CTRL_BUS_DIRECTION_1 Control Bus in/out direction 0x2C 32 read-write 0x0 0xFFFFFFFF DIRECTION Bit at (bit_number/2) has following direction: 00: Input 01:Output 10: Bidirectional IO. 11: Open drain IO. [31:0] read-write GPIF_CTRL_BUS_DEFAULT Control bus default values 0x30 32 read-write 0x0 0xFFFFF DEFAULT One bit for each CTRL signal indicating default value 0: Asserted (see POLARITY) 1: De-asserted (see POLARITY) [19:0] read-write GPIF_CTRL_BUS_POLARITY Control bus signal polarity 0x34 32 read-write 0x0 0xFFFFF POLARITY One bit for each CTRL signal indicating polarity 0: Asserted when 1 1: Asserted when 0 [19:0] read-write GPIF_CTRL_BUS_TOGGLE Control bus output toggle mode 0x38 32 read-write 0x0 0xFFFFF TOGGLE One bit for each CTRL signal indicating toggle mode 0: Normal mode, set value from alpha/beta 1: Toggle mode, toggle value when alpha/beta is 1, do nothing when 0 [19:0] read-write 20 4 GPIF_CTRL_BUS_SELECT[%s] Control bus connection matrix register 0x40 32 read-write 0x0 0x1F OMEGA_INDEX For each omega, 5-bits specify what is driven at to the output: 0-3: Connect to alpha 4-7 8-11: Connect to beta 0-3 16-19: Empty/Full flags for thread 0-3 20-23: Partial Flag for thread 0-3 24: Empty/Full flag for current thread 25: Partial Flag for current thread 26-31: Connected to logic 0 (cannot be used together with CTRL_BUS_TOGGLE) [4:0] read-write GPIF_CTRL_COUNT_CONFIG Control counter configuration 0x160 32 read-write 0x6 0xFF ENABLE 0: This counter is not used. 1: This counter is used. [0:0] read-write DOWN_UP_CNTR 0: Down Count 1: Up Count [1:1] read-write RELOAD_CNTR 0: Saturate on reaching the limit 1: Reload on reaching the limit [2:2] read-write SW_RESET_CNTR 1: SW writes one to reset/load the counter 0: HW write 0 to signal that counter has reset [3:3] read-write CONNECT Connect the specified bit of this counter to CTRL[9] [7:4] read-write GPIF_CTRL_COUNT_RESET Control counter reset register 0x164 32 read-write 0x0 0xFFFF RESET_LOAD_VAL Reset counter to this value. Reload to this value when limit is reached if specified. [15:0] read-write GPIF_CTRL_COUNT_LIMIT Control counter limit register 0x168 32 read-write 0xFFFF 0xFFFF LIMIT_VAL Stop counting when counter reaches this value [15:0] read-write GPIF_ADDR_COUNT_CONFIG Address counter configuration 0x170 32 read-write 0x10A 0xFF0F ENABLE 0: This counter is not used. 1: This counter is used. [0:0] read-write RELOAD 0: Saturate on reaching the limit 1: Reload on reaching the limit [1:1] read-write SW_RESET 1: SW writes one to reset/load the counter 0: HW write 0 to signal that counter has reset [2:2] read-write DOWN_UP 0: Down Count 1: Up Count [3:3] read-write INCREMENT 8-bit quantity to be added/subtracted to the counter on each clock [15:8] read-write GPIF_ADDR_COUNT_RESET Address counter reset register 0x174 32 read-write 0x0 0xFFFFFFFF RESET_LOAD Reset counter to this value. Reload to this value when limit is reached if specified. [31:0] read-write GPIF_ADDR_COUNT_LIMIT Address counter limit register 0x178 32 read-write 0xFFFF 0xFFFFFFFF LIMIT Stop counting when counter reaches this value [31:0] read-write GPIF_STATE_COUNT_CONFIG State counter configuration 0x180 32 read-write 0x0 0x3 ENABLE 0: This counter is not used. 1: This counter is used. [0:0] read-write SW_RESET_STATE_CNT 1: SW writes one to reset/load the counter 0: HW write 0 to signal that counter has reset [1:1] read-write GPIF_STATE_COUNT_LIMIT State counter limit register 0x184 32 read-write 0xFFFF 0xFFFF LIMIT_VAL Generate an output tick, reset and start counting again if enabled when this limit is reached.. [15:0] read-write GPIF_DATA_COUNT_CONFIG Data counter configuration 0x190 32 read-write 0x10A 0xFF0F ENABLE 0: This counter is not used. 1: This counter is used. [0:0] read-write RELOAD 0: Saturate on reaching the limit 1: Reload on reaching the limit [1:1] read-write SW_RESET 1: SW writes one to reset/load the counter 0: HW write 0 to signal that counter has reset [2:2] read-write DOWN_UP 0: Down Count 1: Up Count [3:3] read-write INCREMENT 8-bit quantity to be added/subtracted to the counter on each clock [15:8] read-write GPIF_DATA_COUNT_RESET_LSB Data counter reset register 0x194 32 read-write 0x0 0xFFFFFFFF RESET_LOAD Reset counter to this value. Relload to this value when limit it reached if specified. LSB bits of reset counter value. [31:0] read-write GPIF_DATA_COUNT_RESET_MSB Data counter reset register 0x19C 32 read-write 0x0 0xFFFFFFFF RESET_LOAD Reset counter to this value. Relload to this value when limit it reached if specified. MSB bits of reset counter value. [31:0] read-write GPIF_DATA_COUNT_LIMIT_LSB Data counter limit register 0x1A0 32 read-write 0xFFFF 0xFFFFFFFF LIMIT Reload data counter if this limit is reached and reload is enabled. LSB bits of limit value. [31:0] read-write GPIF_DATA_COUNT_LIMIT_MSB Data counter limit register 0x1A4 32 read-write 0xFFFF 0xFFFFFFFF LIMIT Reload data counter if this limit is reached and reload is enabled. MSB bits of limit value. [31:0] read-write GPIF_CTRL_COMP_VALUE Control comparator value 0x1A8 32 read-write 0x0 0xFFFFF COMP_VALUE Output true when CTRL bus matches this value [19:0] read-write GPIF_CTRL_COMP_MASK Control comparator mask 0x1AC 32 read-write 0x0 0xFFFFF CTRL_COMP_MASK 1: Bit at this bit position in the CTRL bus is to be used in comparison 0: Bit at this bit position is a don't-care for comparison [19:0] read-write GPIF_DATA_COMP_VALUE_WORD0 Data comparator value 0x1B0 32 read-write 0x0 0xFFFFFFFF VALUE Output true when Data bus matches this value. {WD3, WD2, WD1, WD0} [31:0] read-write GPIF_DATA_COMP_VALUE_WORD1 Data comparator value 0x1B4 32 read-write 0x0 0xFFFFFFFF VALUE Output true when Data bus matches this value [31:0] read-write GPIF_DATA_COMP_VALUE_WORD2 Data comparator value 0x1B8 32 read-write 0x0 0xFFFFFFFF VALUE Output true when Data bus matches this value [31:0] read-write GPIF_DATA_COMP_VALUE_WORD3 Data comparator value 0x1BC 32 read-write 0x0 0xFFFFFFFF VALUE Output true when Data bus matches this value [31:0] read-write GPIF_DATA_COMP_MASK_WORD0 Data comparator mask 0x1D0 32 read-write 0x0 0xFFFFFFFF MASK 1: Bit at this bit position in the Data bus is to be used in comparision 0: Bit at this bit position is a don't-care for comparision [31:0] read-write GPIF_DATA_COMP_MASK_WORD1 Data comparator mask 0x1D4 32 read-write 0x0 0xFFFFFFFF MASK 1: Bit at this bit position in the Data bus is to be used in comparision 0: Bit at this bit position is a don't-care for comparision [31:0] read-write GPIF_DATA_COMP_MASK_WORD2 Data comparator mask 0x1D8 32 read-write 0x0 0xFFFFFFFF MASK 1: Bit at this bit position in the Data bus is to be used in comparision 0: Bit at this bit position is a don't-care for comparision [31:0] read-write GPIF_DATA_COMP_MASK_WORD3 Data comparator mask 0x1DC 32 read-write 0x0 0xFFFFFFFF MASK 1: Bit at this bit position in the Data bus is to be used in comparision 0: Bit at this bit position is a don't-care for comparision [31:0] read-write GPIF_ADDR_COMP_VALUE Address comparator value 0x1E0 32 read-write 0x0 0xFFFFFFFF VALUE Output true when Data bus matches this value [31:0] read-write GPIF_ADDR_COMP_MASK Address comparator mask 0x1E4 32 read-write 0x0 0xFFFFFFFF MASK 1: Bit at this bit position in the CTRL bus is to be used in comparison 0: Bit at this bit position is a don't-care for comparison [31:0] read-write GPIF_LAMBDA_STAT0 Lambda Status Register 0x1F0 32 read-only 0x10000000 0xFFFFFFFF LAMBDA Current value of the Lambda Inputs [31:0] read-only GPIF_LAMBDA_STAT1 Lambda Status Register 0x1F4 32 read-only 0x0 0xFFFFFFFF LAMBDA Current value of the Lambda Inputs [31:0] read-only GPIF_ALPHA_STAT Alpha Status Register 0x1F8 32 read-only 0x0 0xFF ALPHA Current value of the Alpha signals [7:0] read-only GPIF_BETA_STAT Beta Status Register 0x1FC 32 read-only 0x0 0xFFFFFFFF BETA_VAL Current value of the Beta signals [31:0] read-only GPIF_WAVEFORM_CTRL_STAT Waveform program control 0x200 32 read-write 0x0 0xFFFF0F03 WAVEFORM_VALID 1: The waveform memory is consistent and valid. 0: Waveforms are no longer valid, stop operation and return outputs to default state [0:0] read-write PAUSE Write 1 here to pause GPIF. 0 to resume where left off. [1:1] read-write GPIF_STAT 0: Waveform is not valid (Initial state or WAVEFORM_VALID is cleared) 1: <unused> 2: GPIF is armed (WAVEFORM_VALID is set) 3: GPIF is running (using WAVEFORM_SWITCH) 4: GPIF is done (encountered DONE_STATE) 5: GPIF is paused (PAUSE=0) 6: GPIF is switching (waiting for timeout/terminal state) 7: An error occurred [10:8] read-only CPU_LAMBDA Visible to the state machine as lambda 34. [11:11] read-write ALPHA_INIT Initial values for alpha outputs. These are loaded into the alpha registers when GPIF execution starts (first WAVEFORM_SWITCH) is set. [23:16] read-write CURRENT_STATE Current state of GPIF. Always updated. [31:24] read-only GPIF_WAVEFORM_SWITCH Waveform switch control 0x204 32 read-write 0x0 0xFFFFFFFF WAVEFORM_SWITCH SW sets this bit after programming the switch register. HW clears it after the switch is complete. [0:0] read-write DONE_ENABLE 1: Enable checking for DONE_STATE and generation of GPIF_DONE. [1:1] read-write SWITCH_NOW 1: Do not wait for TERMINAL_STATE, switch right away [2:2] read-write TIMEOUT_MODE 0: Timeout disable 1: Timeout for reaching TERMINAL_STATE. Interrupt on timeout 2: Timeout for reaching DONE_STATE. Interrupt on timeout 3: Timeout for reaching TERMINAL STATE. Force switch on timeout. 4: Timeout for hanging in current state. Timer resets on each transition. [5:3] read-write TIMEOUT_REACHED Indicates that timeout was reached since last WAVEFORM_SWITCH [6:6] read-only TERMINATED Indicates that the TERMINAL_STATE was reached since last WAVEFORM_SWITCH [7:7] read-only TERMINAL_STATE State from which to initiate the switch. Corresponds to idle states of waveforms. [15:8] read-write DESTINATION_STATE State to jump to, may be the initial state of the new wavform. [23:16] read-write DONE_STATE Signal GPIF_DONE upon reaching this state. [31:24] read-write GPIF_WAVEFORM_SWITCH_TIMEOUT Waveform timeout register 0x208 32 read-write 0x0 0xFFFFFFFF RESET_LOAD Timeout value [31:0] read-write GPIF_CRC_CONFIG CRC Configuration Register 0x210 32 read-write 0x0 0x8070FFFF CRC_RECEIVED A CRC value received on the data inputs by the state machine [15:0] read-only BIT_ENDIAN Indicates the order in which the bits in each byte are brought through the CRC shift register. 0: LSb first 1: MSb first [20:20] read-write BYTE_ENDIAN Indicates the order in which bytes in a 32b word are brought through the CRC shift register. This is independent from the endianness of the interface. 0: LSB first 1: MSB first [21:21] read-write CRC_ERR A CRC was loaded into CRC_RECEIVED that is different from CRC_VALUE [22:22] read-only CRC_ENABLE Enables CRC calulation [31:31] read-write GPIF_BETA_DEASSERT Beta Deassert Register 0x218 32 read-write 0x1 0xFFFFFFFF APPLY_DEASSERT 1: BETA_DEASSERT from the waveform descriptor applies to this beta. This is not honored for external betas which always behave as if apply_deassert=0 0: BETA_DEASSERT does not apply. Betas remain asserted throughout the state. [31:0] read-write 32 4 GPIF_FUNCTION[%s] Transition Function Registers 0x220 32 read-write 0x0 0xFFFF FUNCTION Truth table for transition function. Bit position X contains output when the 4 inputs constitute the value X in binary. For example bit 2 = 1 means in3=0, in2=0, in1=1 and in0=0 will evaluate true for this function. [15:0] read-write LINK_IDLE_CFG Link Idle Config register 0x2B0 32 read-write 0x0 0xFFFFFFFF CLK_OFF_CNT After reset if interface clock is off continuously for duration programmed in this field, then it is considered LINK is idle and interrupt is raised. This counter runs on GPIF clock of 240MHz [15:0] read-write IDLE_CMD_CNT Link is considered idle, when it receives N number of continous IDLE commands on interface and interrupt is raised. N is value programmed in the register field [31:16] read-write 512 16 WAVEFORM[%s] GPIF State Machine Waveform memory. First 256 for Left and last 256 entries for right waveform 0x00001000 WAVEFORM0 GPIF state definition 0x0 32 read-write 0x0 0xFFFFFFFF NEXT_STATE Next state on left transition [7:0] read-write FA Index to select the first input for transition fuctions out of 32 choices. [12:8] read-write FB Second input index. [17:13] read-write FC Third input index. [22:18] read-write FD Fourth input index [27:23] read-write F0_L Lower four bits of index to select the first transition function from a choice of 32 functions. Truth-tables for the 32 4-bit functions are defined using the GPIF_FUNCTION registers. [31:28] read-write WAVEFORM1 GPIF state definition 0x4 32 read-write 0x0 0xFFFFFFFF F0_U MSB of index to select the first transition function from a choice of 32 functions. Truth-tables for the 32 4-bit functions are defined using the GPIF_FUNCTION registers. [0:0] read-write F1 Index to select the second transition function from a choice of 32 functions. Truth-tables for the 32 4-bit functions are defined using the GPIF_FUNCTION registers. [5:1] read-write ALPHA_LEFT Primary outputs for the left edge of the next state. [13:6] read-write ALPHA_RIGHT Primary outputs for the right edge of the next state [21:14] read-write BETA_L Values for the secondary outputs [9:0] associated with this state. [31:22] read-write WAVEFORM2 GPIF state definition 0x8 32 read-write 0x0 0xFFFFFFFF BETA_U Values for the secondary outputs [31:10] associated with this state. [21:0] read-write REPEAT_COUNT Number of times to stay in this state -1 [29:22] read-write BETA_DEASSERT 0: Keep betas asserted throughout the state 1: De-assert after asserting for exactly one clock cycle, irrespective of how many cycles the state is active. The normal (de-assert) state of user defined betas is defined in GPIF_CTRL_BUS_DEFAULT. The normal state of internal betas is fixed by hardware. This function is applied only to betas selected in GPIF_BETA_DEASSERT. [30:30] read-write VALID 1: This entry is valid. 0: Entry not valid. (Not programmed or edge does not exist) [31:31] read-write WAVEFORM3 GPIF state definition 0xC 32 read-write 0x0 0xFFFFFFFF RSVD N/A [31:0] read-write 2 2048 AFE[%s] Phy Configuration Registers 0x00007000 DLL_DFTLPF DLL Low-Pass Filter Config Register 0x0 32 read-write 0x3F3 0x1F MUX_SEL Selection Bits of Low-Pass Filter Multiplexer 0000b: Data Channel 0 input (fixed DC expected, DC depends on learning pattern) 0001b: Data Channel 1 input (fixed DC expected, DC depends on learning pattern) 0010b: Data Channel 2 input (fixed DC expected, DC depends on learning pattern) 0011b: Data Channel 3 input (fixed DC expected, DC depends on learning pattern) 0100b: Data Channel 4 input (fixed DC expected, DC depends on learning pattern) 0101b: Data Channel 5 input (fixed DC expected, DC depends on learning pattern) 0110b: Data Channel 6 input (fixed DC expected, DC depends on learning pattern) 0111b: Data Channel 7 input (fixed DC expected, DC depends on learning pattern) 1000b: Frame Clock input (fixed DC expected, DC depends on learning pattern) 1001b (default)-1011b: Ground input (0 percentDC expected) [3:0] read-write FILT_SEL Low-Pass Filter Charge Time Selection 0 (default): lower RC filter time constant (faster charge/discharge) [4:4] read-write DLL_CONFIG DLL Configuration Register 0x4 32 read-write 0x0 0x1 DFT_RINGO_RST DLL Reset for DfT 0 (default): Test Clock Disabled [0:0] read-write DLL_STATUS DLL Status Register 0x8 32 read-only 0x0 0x3F FT DLL Fine Tuning controlled by digital FSM [5:0] read-only DLL_M_CONFIG Master DLL Config Register 0xC 32 read-write 0x0 0x3FF EN DLL Enable 0 (default): DLL disabled [0:0] read-write CLK_SEL DLL Input Clock Selection 0b RINGO PLL serial clock 1b: external 100MHz [1:1] read-write INV_CLK_MUX DLL Clock MUX Inversion 0 (default): DLL is oscillating when in RINGO configuration [2:2] read-write DFT_EN DLL BIST Enable 0 (default): DLL BIST disabled [3:3] read-write DFT_TEST_CLK_EN DfT Clock Enable 0 (default): Test Clock Disabled [4:4] read-write DFT_BBPD_EN Used to enable dft_bbpd_o 0 (default): DFT outputs disabled [5:5] read-write DFT_BBPD_SEL Selection of dft_bbpd_o. Signal to be sent to DTB 00b (default): no signal 01b: BBPD sampling clock 10b: BBPD sampled data 11b: BBPD output [7:6] read-write SPEED_MODE Dll_m Speed Mode Selection 0 (default): High Speed (24 delay elements) 1: Low Speed (60 delay elements) [8:8] read-write ADFT_EN_LV Dll_m Connection to Analog Bus Enable 0 (default): Connection Disabled 1: Connection Enabled [9:9] read-write DLL_M_STATUS Master DLL Status Register 0x10 32 read-only 0x0 0xFFF SEL_PH DLL BIST Phase Selection controlled by digital FSM Default: 0000b [3:0] read-only CT DLL Coarse Tuning controlled by digital FSM [7:4] read-only BBPD DLL BBPD Output [8:8] read-only DFT_BBPD DLL BBPD or sampled clock or sampled data to be sent to DTB [9:9] read-only CORRECT_PERIOD False Lock Detection Output: DLL Period Check for digital FSM [10:10] read-only DLL_LOCK Lock Status Indication - 1 = DLL is locked; 0 - Not Locked [11:11] read-only 12 4 DLL_S_CONFIG[%s] Slave DLL Configuration 0x14 32 read-write 0x0 0x7 INV_CLK_MUXED DLL Clock MUX Inversion 0 (default): DLL is oscillating when in RINGO configuration [0:0] read-write SDLL_DFT_EN DLL BIST Enable 0 (default): DLL BIST disabled [1:1] read-write SDLL_EN DLL Enable 0 (default): DLL disabled [2:2] read-write 12 4 DLL_S_STATUS[%s] Slave DLL Status 0x50 32 read-only 0x457 0x1F SEL_PH DLL Replica Phase Selection These bits select the phase to be output and are controlled by the digital skew compensation FSM. Default is 1111b. [3:0] read-only CLK_DFT DfT Output Signal of the DLL Replica [4:4] read-only GENERAL_LICIO_CIO 0 0x80 32 read-write 0x0 0x3 LVDS_RTERM_EN Differential resistance enable in LVDS mode [0:0] read-write LVCMOS_LB_EN LVCMOS Core side loopback enable [1:1] read-write 27 4 LICIO_CIO[%s] 0 0x84 32 read-write 0x0 0xFFF LVCMOS_RX_EN LVCMOS receiver enable [0:0] read-write LVCMOS_TX_EN LVCMOS output enable [1:1] read-write DS Impedance control select [6:2] read-write ATST Analog test control bits [9:7] read-write SR Slew rate select [11:10] read-write GENERAL_LICIO_LI 0 0x100 32 read-write 0x0 0x1 LVDS_LB_EN LVDS Core side loopback enable [0:0] read-write 10 4 LICIO_LI[%s] 0 0x104 32 read-write 0x0 0x381 LVDS_RX_EN LVDS receiver enable [0:0] read-write ATST Analog test control bits [9:7] read-write LICIO_VSSIO_IREF 0 0x130 32 read-write 0x0 0xF EN Iref Enable [0:0] read-write IN_SEL Input iref select: 0=iref_in_10u, 1=iref_in_250n, 2=internal, 3=amuxbus_b [2:1] read-write ATST_EN Analog test enable [3:3] read-write LICIO_VSSIO_VREF 0 0x134 32 read-write 0x0 0x383 EN Vref Enable [0:0] read-write LEVEL_SEL Selection between 0:50 percent and 1:45 percent of v(Vddio); 50 percent for 1.8V and 2.5V LVCMOS, 45 percent for 3.3V & LVTTL [1:1] read-write ATST Analog test control bits [9:7] read-write PLL_CONFIG PLL Configuration register 0x138 32 read-write 0x0 0x3FFFFFFF PLL_CP_CUR_TRIM trim option of analog charge pump (scan mode - can be '0' or '1' - not High Z) [1:0] read-write PLL_LDO_VCO_TRIM pll ldo vco voltage trim (scan mode - can be '0' or '1' - not High Z) [4:2] read-write PLL_LD_DELAY trim of phase error window (scan mode - can be '0' or '1' - not High Z) [6:5] read-write PLL_EN pll operation enable [7:7] read-write PLL_LDO_VCO_BYPASS periphery ldo bypass (scan mode - can be '0' or '1' - not High Z) [8:8] read-write PLL_REF_SEL Mux selection bit for input reference clock [10:9] read-write PLL_SUPPLY_EN pll enable signal (enable at '1') (scan mode - must be '1') [11:11] read-write N_IN_DIV Input clock divider setting [13:12] read-write N_SERIAL_DIV Serial output divider setting [15:14] read-write N_FRAME_DIV Frame output divider setting [16:16] read-write N_FB_DIV Feedback divider setting [19:17] read-write PLL_ATST_SEL testmode decoded pins [23:20] read-write PLL_RUN_AWAY_DEL delay from run away comparator flip - to start forcing pll [25:24] read-write PLL_RUN_AWAY_DIS '1' - disable run away operation [26:26] read-write PLL_RUN_AWAY_TRIM define run away level [28:27] read-write PLL_VCO_INIT_DIS disable initial condition of the ring [29:29] read-write PLL_CONFIG_2 PLL Configuration register2 0x13C 32 read-write 0x0 0x1FF PLL_LDO_CORE_TRIM Spare bits [2:0] read-write PLL_CAL_UP_DN up/dn calibration mismatch [6:3] read-write PLL_RA_UP_TR define run away upper level [8:7] read-write PLL_STATUS PLL Status Register 0x140 32 read-only 0x0 0x7F PLL_VCO_GAIN Kvco trim change (scan mode - can be '0' or '1' - not High Z) [3:0] read-only PLL_DFT logic dft output [4:4] read-only PLL_LOCK pll lock signal (scan mode - forced to '0') [5:5] read-only PLL_RUN_AWAY_STICKY run away occur at the system (will be reset only when pll is disable) [6:6] read-only REG_1P25 0 0x144 32 read-write 0x0 0x7FFF IREF_DLL_SEL Selection Bits to tune DLL reference current [2:0] read-write ENABLE Enable of LDO from 3.3V to 1.2V 0 (default): LDO disabled [3:3] read-write USE_REG Use of regulator of switch from vccd to vout_1p25 0: Bypass regulator and connect vccd to vout_1p25 1: Use regulator to generate vout_1p25 [4:4] read-write ADFT_CTRL Selection of analog MUX connectivity to adft[1:0] [8:5] read-write ADFT_EN Enable of analog MUX for DfT 0 (default): AMUX disabled [9:9] read-write BURN_IN_EN Enable of DLL Burn-in for 1.2V regulated domain 0 (default): DLL Burn-In disabled [10:10] read-write TRIM_VREG_1P25 Selection of feedback resistor for LDO output voltage If DLL Burn-in Disabled 0111b (default): 1.2V if DLL Burn-In Enabled 0111b (default): 1.45V [14:11] read-write 10 4 RX[%s] 0 0x148 32 read-write 0x0 0x1F FIXTIME_FRAMECLK Inversion of Data Channel X Frame Clock This bit is used to invert the frame clock used inside Data Channel X Deserializer before the frame clock itself enters the STS. This is done to avoid setup time violations inside the STS. 0 (default): Same edge is used for deserialization in analog and resampling the STS. [0:0] read-write EN_DESER Enable of Data Deserializer 0 (default): Deserializer disabled 1: Deserializer enabled [1:1] read-write INV_CLK_FRAME Invert Polarity of Frame Clock 0 (default): rising edge of frame clock defines parallel data 1: falling edge of frame clock defines parallel data [2:2] read-write INV_CLK_SER Invert Polarity of Serial Clock 0 (default): select 0 degrees phase of serial clock 1: select 180 degrees phase of serial clock [3:3] read-write INV_DATA_SER Polarity Inversion of Serial Data 0 (default): select phase 0 of serial data 1: select 180 degrees phase shift of serial data [4:4] read-write GENERAL_RX General RX Configuration Registers 0x170 32 read-write 0x0 0x3 DR_MODE MUX Selection Signal for 8 bits output 0 (default): Double Data Rate 1: Single Data Rate [0:0] read-write BER_RSTN BER reset, active LOW [1:1] read-write GENERAL_RX_LVCMOS General LVCMOS RX Configuration Registers 0x174 32 read-write 0x0 0xE CLK_MODE Sampling Clock Inversion. 0 (default): Rising and Falling Clock Edges are not inverted 1: Rising and Falling Clock Edges are inverted (used in SDR reception) [1:1] read-write EN_DDR DDR Enable. 0 (default): DDR Sampler is off. 1: DDR Sampler is on. [2:2] read-write BYPASS_SKEW_EN Sampling Clock Selection. [3:3] read-write 26 4 RX_LVCMOS[%s] 0 0x178 32 read-write 0x0 0x1 EN_LVCMOS LVCMOS Enable. 0 (default): LVCMOS receiver is off. 1: SDR Sampler is on. Note: to enable LVCMOS DDR reception, both en_lvcmos and en_ddr are to be set to 1. [0:0] read-write PRBS_GEN State counter limit register 0x204 32 read-write 0x0 0x7F EN Enable Signal [0:0] read-write SEED Input Seed for PRBS Generation. Note: 00000 is not a valid input seed. [5:1] read-write DDR_EN DDR Bit Stream Generation Enable. 0(default): DDR generation disabled. 1: DDR generation enabled. [6:6] read-write PHY_GENERAL_CONFIG Phy Configuration register 0x208 32 read-write 0x0 0x3F DESKEW_ALGORITHM Chosen deskew algorithm: 0(default): bypass 1: slow 2: SDR fast 3: DDR fast [1:0] read-write ENABLE_SCANON Vddd related enable signal [2:2] read-write ENABLE_V1P25_VCCD Enable indicating v1p25 is powered [3:3] read-write ENABLE_V1P1_VCCD Enable indicating v1p1 is powered [4:4] read-write ENABLE_VDDIO Enable related to VDDIO [5:5] read-write PHY_GENERAL_STATUS_1 Phy Status register 0x20C 32 read-only 0x0 0x3FFFFF PRBS_CHECKER_STATE Status of the PRBS Checker 0: not activated 1: link start-up 2: locked to a detected sequence 3: sequence once found, now lost, trying to lock-up again [1:0] read-only BER_COUNTER Error counter for PRBS Loopback. [21:2] read-only PHY_GENERAL_STATUS_2 Phy Status register 0x210 32 read-only 0x0 0x1FF LVDS_LOOPBACK_FLAG LVDS Loopback Test Flag 0(default): LVDS Loopback test not passed 1: LVDS Loopback Test passed [0:0] read-only LVCMOS_LOOPBACK_FLAG LVCMOS Loopback Test Flag 0(default): LVCMOS Loopback test not passed 1: LVCMOS Loopback Test passed [1:1] read-only DESKEW_COMPLETE Deskew Algorithm Flag 0(default): deskew not completed 1: deskew completed [2:2] read-only OK_DLL_V1P1 v1p1 related enable signal [3:3] read-only OK_DLL_VCCD Indicates all DLL power supplies are ready [4:4] read-only OK_DLL_V1P25 Indicates all DLL power supplies are ready [5:5] read-only OK_VCCD_V1P1 Indicates that the vccd supply is powered [6:6] read-only OK_V1P25_VCCD Indicates that the vout_1p25 supply is powered [7:7] read-only OK_VCCD_V1P25 Indicates that the vccd supply is powered [8:8] read-only PHY_INTR Phy Interrupt Register 0x214 32 read-write 0x0 0x1FF LVDS_LOOPBACK_FLAG N/A [0:0] read-write LVCMOS_LOOPBACK_FLAG N/A [1:1] read-write DESKEW_COMPLETED Set when deskew is completed [2:2] read-write OK_DLL_V1P1 Set when power supply is stable [3:3] read-write OK_DLL_VCCD Set when power supply is stable [4:4] read-write OK_DLL_V1P25 Set when power supply is stable [5:5] read-write OK_VCCD_V1P1 Set when power supply is stable [6:6] read-write OK_V1P25_VCCD Set when power supply is stable [7:7] read-write OK_VCCD_V1P25 Set when power supply is stable [8:8] read-write PHY_INTR_MASK Phy Interrupt Mask Register 0x218 32 read-write 0x0 0x1FF LVDS_LOOPBACK_FLAG N/A [0:0] read-write LVCMOS_LOOPBACK_FLAG N/A [1:1] read-write DESKEW_COMPLETED Set when deskew is completed [2:2] read-write OK_DLL_V1P1 Set when power supply is stable [3:3] read-write OK_DLL_VCCD Set when power supply is stable [4:4] read-write OK_DLL_V1P25 Set when power supply is stable [5:5] read-write OK_VCCD_V1P1 Set when power supply is stable [6:6] read-write OK_V1P25_VCCD Set when power supply is stable [7:7] read-write OK_VCCD_V1P25 Set when power supply is stable [8:8] read-write PHY_INTR_MASKED Phy Interrupt Masked Register 0x21C 32 read-only 0x0 0x1FF LVDS_LOOPBACK_FLAG N/A [0:0] read-only LVCMOS_LOOPBACK_FLAG N/A [1:1] read-only DESKEW_COMPLETED Set when deskew is completed [2:2] read-only OK_DLL_V1P1 Set when power supply is stable [3:3] read-only OK_DLL_VCCD Set when power supply is stable [4:4] read-only OK_DLL_V1P25 Set when power supply is stable [5:5] read-only OK_VCCD_V1P1 Set when power supply is stable [6:6] read-only OK_V1P25_VCCD Set when power supply is stable [7:7] read-only OK_VCCD_V1P25 Set when power supply is stable [8:8] read-only PHY_INTR_SET Phy Interrupt Set Register 0x220 32 read-write 0x0 0x1FF LVDS_LOOPBACK_FLAG N/A [0:0] read-write LVCMOS_LOOPBACK_FLAG N/A [1:1] read-write DESKEW_COMPLETED Set when deskew is completed [2:2] read-write OK_DLL_V1P1 Set when power supply is stable [3:3] read-write OK_DLL_VCCD Set when power supply is stable [4:4] read-write OK_DLL_V1P25 Set when power supply is stable [5:5] read-write OK_VCCD_V1P1 Set when power supply is stable [6:6] read-write OK_V1P25_VCCD Set when power supply is stable [7:7] read-write OK_VCCD_V1P25 Set when power supply is stable [8:8] read-write 32 128 SCK[%s] DMA Socket & Descriptor Registers 0x00008000 SCK_DSCR Descriptor Chain Pointer 0x0 32 read-write 0x0 0x0 DSCR_NUMBER Descriptor number of currently active descriptor. A value of 0xFFFF designates no (more) active descriptors available. When activating a socket CPU shall write number of first descriptor in here. Only modify this field when go_suspend=1 or go_enable=0 [15:0] read-write DSCR_COUNT Number of descriptors still left to process. This value is unrelated to actual number of descriptors in the list. It is used only to generate an interrupt to the CPU when the value goes low or zero (or both). When this value reaches 0 it will wrap around to 255. The socket will not suspend or be otherwise affected unless the descriptor chains ends with 0xFFFF descriptor number. [23:16] read-write DSCR_LOW The low watermark for dscr_count. When dscr_count is equal or less than dscr_low the status bit dscr_is_low is set and an interrupt can be generated (depending on int mask). [31:24] read-write SCK_SIZE Transfer Size Register 0x4 32 read-write 0x0 0x0 TRANS_SIZE The number of bytes or buffers (depends on unit bit in SCK_STATUS) that are part of this transfer. A value of 0 signals an infinite/undetermined transaction size. Valid data bytes remaining in the last buffer beyond the transfer size will be read by socket and passed on to the core. FW must ensure that no additional bytes beyond the transfer size are present in the last buffer. [31:0] read-write SCK_COUNT Transfer Count Register 0x8 32 read-write 0x0 0x0 TRANS_COUNT The number of bytes or buffers (depends on unit bit in SCK_STATUS) that have been transferred through this socket so far. If trans_size is >0 and trans_count>=trans_size the 'trans_done' bits in SCK_STATUS is both set. If SCK_STATUS.susp_trans=1 the socket is also suspended and the 'suspend' bit set. This count is updated only when a descriptor is completed and the socket proceeds to the next one. Exception: When socket suspends with PARTIAL_BUF=1, this value has been (incorrectly) incremented by 1 (UNIT=1) or DSCR_SIZE.BYTE_COUNT (UNIT=0). Firmware must correct this before resuming the socket. [31:0] read-write SCK_STATUS Socket Status Register 0xC 32 read-write 0x4E00000 0xFFFF87FF AVL_COUNT Number of available (free for ingress, occupied for egress) descriptors beyond the current one. This number is incremented by the adapter whenever an event is received on this socket and decremented whenever it activates a new descriptor. This value is used to create a signal to the IP Cores that indicates at least one buffer is available beyond the current one (sck_more_buf_avl). [4:0] read-write AVL_MIN Minimum number of available buffers required by the adapter before activating a new one. This can be used to guarantee a minimum number of buffers available with old data to implement rollback. If AVL_ENABLE, the socket will remain in STALL state until AVL_COUNT>=AVL_MIN. [9:5] read-write AVL_ENABLE Enables the functioning of AVL_COUNT and AVL_MIN. When 0, it will disable both stalling on AVL_MIN and generation of the sck_more_buf_avl signal described above. [10:10] read-write STATE Internal operating state of the socket. This field is used for debugging and to safely modify active sockets (see go_suspend). [17:15] read-only DESCR Descriptor state. This is the default initial state indicating the descriptor registers are NOT valid in the Adapter. The Adapter will start loading the descriptor from memory if the socket becomes enabled and not suspended. Suspend has no effect on any other state. 0 STALL Stall state. Socket is stalled waiting for data to be loaded into the Fetch Queue or waiting for an event. 1 ACTIVE Active state. Socket is available for core data transfers. 2 EVENT Event state. Core transfer is done. Descriptor is being written back to memory and an event is being generated if enabled. 3 CHECK1 Check states. An active socket gets here based on the core's EOP request to check the Transfer size and determine whether the buffer should be wrapped up. Depending on result, socket will either go back to Active state or move to the Event state. 4 SUSPENDED Socket is suspended 5 CHECK2 Check states. An active socket gets here based on the core's EOP request to check the Transfer size and determine whether the buffer should be wrapped up. Depending on result, socket will either go back to Active state or move to the Event state. 6 WAITING Waiting for confirmation that event was sent. 7 ZLP_RCVD Indicates the socket received a ZLP [18:18] read-only SUSPENDED Indicates the socket is currently in suspend state. In suspend mode there is no active descriptor; any previously active descriptor has been wrapped up, copied back to memory and SCK_DSCR.dscr_number has been updated using DSCR_CHAIN as needed. If the next descriptor is known (SCK_DSCR.dscr_number!=0xFFFF), this descriptor will be loaded after the socket resumes from suspend state. A socket can only be resumed by changing go_suspend from 1 to 0. If the socket is suspended while go_suspend=0, it must first be set and then again cleared. [19:19] read-only ENABLED Indicates the socket is currently enabled when asserted. After go_enable is changed, it may take some time for enabled to make the same change. This value can be polled to determine this fact. [20:20] read-only TRUNCATE Enable (1) or disable (0) truncating of BYTE_COUNT when TRANS_COUNT+BYTE_COUNT>=TRANS_SIZE. When enabled, ensures that an ingress transfer never contains more bytes then allowed. This function is needed to implement burst-based prototocols that can only transmit full bursts of more than 1 byte. [21:21] read-write EN_PROD_EVENTS Enable (1) or disable (0) sending of produce events from any descriptor in this socket. If 0, events will be suppressed, and the descriptor will not be copied back into memory when completed. [22:22] read-write EN_CONS_EVENTS Enable (1) or disable (0) sending of consume events from any descriptor in this socket. If 0, events will be suppressed, and the descriptor will not be copied back into memory when completed. [23:23] read-write SUSP_PARTIAL When set, the socket will suspend before activating a descriptor with BYTE_COUNT<BUFFER_SIZE. This is relevant for egress sockets only. [24:24] read-write SUSP_LAST When set, the socket will suspend before activating a descriptor with TRANS_COUNT+BUFFER_SIZE>=TRANS_SIZE. This is relevant for both ingress and egress sockets. [25:25] read-write SUSP_TRANS When set, the socket will suspend when trans_count >= trans_size. This equation is checked (and hence the socket will suspend) only at the boundary of buffers and packets (ie. buffer wrapup or EOP assertion). [26:26] read-write SUSP_EOP When set, the socket will suspend after wrapping up the first buffer with dscr.eop=1. Note that this function will work the same for both ingress and egress sockets. [27:27] read-write WRAPUP Setting this bit will forcibly wrap-up a socket, whether it is out of data or not. This option is intended mainly for ingress sockets, but works also for egress sockets. Any remaining data in fetch buffers is ignored, in write buffers is flushed. Transaction and buffer counts are updated normally, and suspend behavior also happens normally (depending on various other settings in this register).G45 [28:28] read-write UNIT Indicates whether descriptors (1) or bytes (0) are counted by trans_count and trans_size. Descriptors are counting regardless of whether they contain any data or have eop set. [29:29] read-write GO_SUSPEND Directs a socket to go into suspend mode when the current descriptor completes. The main use of this bit is to safely append descriptors to an active socket without actually suspending it (in most cases). The process is outlined in more detail in the architecture spec, and looks as follows: 1: GO_SUSPEND=1 2: modify the chain in memory 3: check if active descriptor is 0xFFFF or last in chain 4: if so, make corrections as neccessary (complicated) 5: clear any pending suspend interrupts (SCK_INTR[9:5]) 6: GO_SUSPEND=0 Note that the socket resumes only when SCK_INTR[9:5]=0 and GO_SUSPEND=0. [30:30] read-write GO_ENABLE Indicates whether socket is enabled. When go_enable is cleared while socket is active, ongoing transfers are aborted after an unspecified amount of time. No update occurs from the descriptor registers back into memory. When go_enable is changed from 0 to 1, the socket will reload the active descriptor from memory regardless of the contents of DSCR_ registers. The socket will not wait for an EVENT to become active if the descriptor is available and ready for transfer (has space or data). The 'enabled' bit indicates whether the socket is actually enabled or not. This field lags go_enable by an short but unspecificied of time. [31:31] read-write SCK_INTR Socket Interrupt Request Register 0x10 32 read-write 0x0 0x3FF PRODUCE_EVENT Indicates that a produce event has been received or transmitted since last cleared. [0:0] read-write CONSUME_EVENT Indicates that a consume event has been received or transmitted since last cleared. [1:1] read-write DSCR_IS_LOW Indicates that dscr_count has fallen below its watermark dscr_low. If dscr_count wraps around to 255 dscr_is_low will remain asserted until cleared by s/w [2:2] read-write DSCR_NOT_AVL Indicates the no descriptor is available. Not available means that the current descriptor number is 0xFFFF. Note that this bit will remain asserted until cleared by s/w, regardless of whether a new descriptor number is loaded. [3:3] read-write STALL Indicates the socket has stalled, waiting for an event signaling its descriptor has become available. Note that this bit will remain asserted until cleared by s/w, regardless of whether the socket resumes. [4:4] read-write SUSPEND Indicates the socket has gone into suspend mode. This may be caused by any hardware initiated condition (e.g. DSCR_NOT_AVL, any of the SUSP_*) or by setting GO_SUSPEND=1. Note that this bit will remain asserted until cleared by s/w, regardless of whether the suspend condition is resolved. Note that the socket resumes only when SCK_INTR[9:5]=0 and GO_SUSPEND=0. [5:5] read-write ERROR Indicates the socket is suspended because of an error condition (internal to the adapter) - if error=1 then suspend=1 as well. Possible error causes are: - dscr_size.buffer_error bit already set in the descriptor. - dscr_size.byte_count > dscr_size.buffer_size - core writes into an inactive socket. - core did not consume all the data in the buffer. Note that the socket resumes only when SCK_INTR[9:5]=0 and GO_SUSPEND=0. [6:6] read-write TRANS_DONE Indicates that TRANS_COUNT has reached the limit TRANS_SIZE. This flag is only set when SUSP_TRANS=1. Note that because TRANS_COUNT is updated only at the granularity of entire buffers, it is possible that TRANS_COUNT exceeds TRANS_SIZE before the socket suspends. Software must detect and deal with these situations. When asserting EOP to the adapter on ingress, the trans_count is not updated unless the socket actually suspends (see SUSP_TRANS). Note that the socket resumes only when SCK_INTR[9:5]=0 and GO_SUSPEND=0. [7:7] read-write PARTIAL_BUF Indicates that the (egress) socket was suspended because of SUSP_PARTIAL condition. Note that the socket resumes only when SCK_INTR[9:5]=0 and GO_SUSPEND=0. [8:8] read-write LAST_BUF Indicates that the socket was suspended because of SUSP_LAST condition. Note that the socket resumes only when SCK_INTR[9:5]=0 and GO_SUSPEND=0. [9:9] read-write SCK_INTR_MASK Socket Interrupt Mask Register 0x14 32 read-write 0x0 0x3FF PRODUCE_EVENT 1: Report interrupt to CPU [0:0] read-write CONSUME_EVENT 1: Report interrupt to CPU [1:1] read-write DSCR_IS_LOW 1: Report interrupt to CPU [2:2] read-write DSCR_NOT_AVL 1: Report interrupt to CPU [3:3] read-write STALL 1: Report interrupt to CPU [4:4] read-write SUSPEND 1: Report interrupt to CPU [5:5] read-write ERROR 1: Report interrupt to CPU [6:6] read-write TRANS_DONE 1: Report interrupt to CPU [7:7] read-write PARTIAL_BUF 1: Report interrupt to CPU [8:8] read-write LAST_BUF 1: Report interrupt to CPU [9:9] read-write DSCR_BUFFER Descriptor buffer base address register 0x20 32 read-write 0x0 0x0 BUFFER_ADDR The base address of the buffer where data is written. This address is not necessarily word-aligned to allow for header/trailer/length modification. [31:0] read-write DSCR_SYNC Descriptor synchronization pointers register 0x24 32 read-write 0x0 0x0 CONS_SCK The socket number of the consuming socket to which the produce event shall be sent. If cons_ip and cons_sck matches the socket's IP and socket number then the matching socket becomes consuming socket. [7:0] read-write CONS_IP The IP number of the consuming socket to which the produce event shall be sent. Use 0x3F to designate ARM CPU (so software) as consumer; the event will be lost in this case and an interrupt should also be generated to observe this condition. [13:8] read-write EN_CONS_EVENT Enable sending of a consume events from this descriptor only. Events are sent only if SCK_STATUS.en_consume_ev=1. When events are disabled, the adapter also does not update the descriptor in memory to clear its occupied bit. [14:14] read-write EN_CONS_INT Enable generation of a consume event interrupt for this descriptor only. This interrupt will only be seen by the CPU if SCK_STATUS.int_mask has this interrupt enabled as well. Note that this flag influences the logging of the interrupt in SCK_STATUS; it has no effect on the reporting of the interrupt to the CPU like SCK_STATUS.int_mask does. [15:15] read-write PROD_SCK The socket number of the producing socket to which the consume event shall be sent. If prod_ip and prod_sck matches the socket's IP and socket number then the matching socket becomes consuming socket. [23:16] read-write PROD_IP The IP number of the producing socket to which the consume event shall be sent. Use 0x3F to designate ARM CPU (so software) as producer; the event will be lost in this case and an interrupt should also be generated to observe this condition. [29:24] read-write EN_PROD_EVENT Enable sending of a produce events from this descriptor only. Events are sent only if SCK_STATUS.en_produce_ev=1. If 0, events will be suppressed, and the descriptor will not be copied back into memory when completed. [30:30] read-write EN_PROD_INT Enable generation of a produce event interrupt for this descriptor only. This interrupt will only be seen by the CPU if SCK_STATUS. int_mask has this interrupt enabled as well. Note that this flag influences the logging of the interrupt in SCK_STATUS; it has no effect on the reporting of the interrupt to the CPU like SCK_STATUS.int_mask does. [31:31] read-write DSCR_CHAIN Descriptor Chain Pointers Register 0x28 32 read-write 0x0 0x0 RD_NEXT_DSCR Descriptor number of the next task for consumer. A value of 0xFFFF signals end of this list. [15:0] read-write WR_NEXT_DSCR Descriptor number of the next task for producer. A value of 0xFFFF signals end of this list. [31:16] read-write DSCR_SIZE Descriptor Size Register 0x2C 32 read-write 0x0 0x0 MARKER A marker that is provided by s/w and can be observed by the IP. It's meaning is defined by the IP that uses it. This bit has no effect on the other DMA mechanisms. [0:0] read-write EOP A marker indicating this descriptor refers to the last buffer of a packet or transfer. Packets/transfers may span more than one buffer. The producing IP provides this marker by providing the EOP signal to its DMA adapter. The consuming IP observes this marker by inspecting its EOP return signal from its own DMA adapter. For more information see section on packets, buffers and transfers in DMA chapter. [1:1] read-write BUFFER_ERROR Indicates the buffer data is valid (0) or in error (1). [2:2] read-write BUFFER_OCCUPIED Indicates the buffer is in use (1) or empty (0). A consumer will interpret this as: 0: Buffer is empty, wait until filled. 1: Buffer has data that can be consumed A produce will interpret this as: 0: Buffer is ready to be filled 1: Buffer is occupied, wait until empty [3:3] read-write BUFFER_SIZE The size of the buffer in multiples of 16 bytes [15:4] read-write BYTE_COUNT The number of data bytes present in the buffer. An occupied buffer is not always full, in particular when variable length packets are transferred. [31:16] read-write EVENT Event Communication Register 0x7C 32 write-only 0x0 0x1FFFF ACTIVE_DSCR The active descriptor number for which the event is sent. [15:0] write-only EVENT_TYPE Type of event 0: Consume event descriptor is marked empty - BUFFER_OCCUPIED=0) 1: Produce event descriptor is marked full = BUFFER_OCCUPIED=1) [16:16] write-only SCK_GBL DMA Adapter Global Registers 0x0000FF00 SCK_INTR Socket Interrupt Request Register 0x0 32 read-only 0x0 0xFFFFFFFF SCKINTR Socket <x> asserts interrupt when bit <x> is set in this vector. Multiple bits may be set to 1 simultaneously. This register is only as wide as the number of socket in the adapter; 256 is just the maximum width. All other bits always return 0. [31:0] read-only ADAPTER_DEBUG Adapter Debug Observation Register 0xF4 32 read-only 0x0 0xFFFFFFFF TS_COUNT Internal adapter state for debug observation [3:0] read-only TS_STATE Internal adapter state for debug observation [6:4] read-only TS_ID Internal adapter state for debug observation [12:7] read-only SS_COUNT Internal adapter state for debug observation [21:13] read-only SS_STATE Internal adapter state for debug observation [22:22] read-only SS_ID Internal adapter state for debug observation [28:23] read-only TS_ABORT Internal adapter state for debug observation [29:29] read-only BS_STATE Internal adapter state for debug observation [31:30] read-only ADAPTER_CONF Adapter Configuration Register 0xF8 32 read-write 0x0 0x7FFFFFFF FQ_THRESHOLD Number of words in a socket fetch queue (FQ) that must be present before sck_active asserts. Default value is FQ_SIZE, which means the entire FQ must fill up before sck_active asserts. [5:0] read-write STREAM_COUNT Number of burst requests to issue without examining the FQ depth (because IP Core can guarantee immediate consumption). [14:6] read-write STREAMING_MODE 0: Do not make fetch requests unless fetch queue has space to hold response (default). 1: Assume IP Core will drain all data as it comes in. Place fetch requests on bus as fast as possible (DO NOT USE UNLESS YOU KNOW WHAT YOU ARE DOING). [15:15] read-write TS_CYCLES Minimum cycles between prefetch requests to the bus. The adapter will wait for this number of cycles in between prefetch burst requests when activating a descriptor on a socket. If TS_CYCLES=0, the requests will be sent back-to-back (assuming queues are not full). [19:16] read-write ES_CYCLES Minimum cycles between fetch requests to the bus under normal operation. The adapter will wait for this number of cycles in between burst requests when refilling a fetch queue for a desriptor If ES_CYCLES=0, the requests may be sent back-to-back (assuming queues are not full). [23:20] read-write GBL_CYCLES Minimum cycles between any fetch requests to the bus. The adapter will wait for this number of cycles in between any fetch or prefetch burst requests when activating a descriptor on a socket. If GBL_CYCLES=0, the requests may be sent back-to-back (assuming queues are not full). [27:24] read-write MMIO_LOW_PRIORITY Sets priority between MMIO and Core requests: 0: fair arbitration. MMIO is guaranteed to win the next cycle if there was a collision with the core request in the first cycle. 1: low priority. MMIO will never win if the core has a request. [28:28] read-write SWITCH_HIGH_PRIORITY Socket swicth higher priority than interconnect [29:29] read-write TS_ABORT_EN Allow TS to be aborted [30:30] read-write ADAPTER_STATUS Adapter Global Status Fields 0xFC 32 read-only 0x0 0xFFFFFF TTL_SOCKETS Total number of sockets in this adapter. This number is different for each instance of the adapter and varies with the core IP needs. [7:0] read-only IG_ONLY First socket number that is ingress only. 0..IG_ONLY-1: Sockets capable of both in and egress IG_ONLY..TTL_SOCKETS-1: Ingress sockets only [15:8] read-only FQ_SIZE Number of words in a socket fetch queue (FQ). The total buffer space in the adapter is EG_SOCKETS*FQ_SIZE words of size WORD_SIZE. [21:16] read-only WORD_SIZE Internal word size of the prefetch queue (FQ); not the same as bus width of AHB bus or thread interface to the IP. 0: 32b 1: 64b 2: 128b 3: 256b [23:22] read-only SCB0 Serial Communications Block (SPI/UART/I2C) SCB 0x40500000 0 65536 registers CTRL Generic control 0x0 32 read-write 0x300000F 0x83031F0F OVS N/A [3:0] read-write EC_AM_MODE Internally clocked mode ('0') or externally clocked mode ('1') address matching (I2C) or selection (SPI). In internally clocked mode, the serial interface protocols run off the peripheral clock. In externally clocked mode, the serial interface protocols run off the clock as provided by the serial interface. Externally clocked mode is only used for synchronous serial interface protocols (SPI and I2C) in slave mode. In SPI mode, only Motorola submode (all Motorola modes: 0, 1, 2, 3) is supported. In UART mode this field should be '0'. [8:8] read-write EC_OP_MODE Internally clocked mode ('0') or externally clocked mode ('1') operation. In internally clocked mode, the serial interface protocols run off the peripheral clock. In externally clocked mode, the serial interface protocols run off the clock as provided by the serial interface. Externally clocked operation mode is only used for synchronous serial interface protocols (SPI and I2C) in slave mode AND EZ mode. In SPI mode, only Motorola submode (all Motorola modes: 0, 1, 2, 3) is supported. The maximum SPI slave, EZ mode bitrate is 48 Mbps (transmission and IO delays outside the IP will degrade the effective bitrate). In UART mode this field should be '0'. [9:9] read-write EZ_MODE Non EZ mode ('0') or EZ mode ('1'). In EZ mode, a meta protocol is applied to the serial interface protocol. This meta protocol adds meaning to the data frames transferred by the serial interface protocol: a data frame can represent a memory address, a write memory data element or a read memory data element. EZ mode is only used for synchronous serial interface protocols: SPI and I2C. In SPI mode, only Motorola submode (all Motorola modes: 0, 1, 2, 3) is supported and the transmitter should use continuous data frames; i.e. data frames mot separated by slave deselection. This mode is only applicable to slave functionality. In EZ mode, the slave can read from and write to an addressable memory structure of up to 256 bytes. In EZ mode, data frames should 8-bit in size and should be transmitted and received with the Most Significant Bit (MSB) first. In UART mode this field should be '0'. [10:10] read-write BYTE_MODE Determines the number of bits per FIFO data element: '0': 16-bit FIFO data elements. '1': 8-bit FIFO data elements. This mode doubles the amount of FIFO entries, but TX_CTRL.DATA_WIDTH and RX_CTRL.DATA_WIDTH are restricted to [0, 7]. [11:11] read-write CMD_RESP_MODE Determines CMD_RESP mode of operation: '0': CMD_RESP mode disabled. '1': CMD_RESP mode enabled (also requires EC_AM_MODE and EC_OP_MODE to be set to '1'). [12:12] read-write ADDR_ACCEPT Determines whether a received matching address is accepted in the RX FIFO ('1') or not ('0'). In I2C mode, this field is used to allow the slave to put the received slave address or general call address in the RX FIFO. Note that a received matching address is put in the RX FIFO when ADDR_ACCEPT is '1' for both I2C read and write transfers. In multi-processor UART receiver mode, this field is used to allow the receiver to put the received address in the RX FIFO. Note: non-matching addresses are never put in the RX FIFO. [16:16] read-write BLOCK Only used in externally clocked mode. If the externally clocked logic and the MMIO SW accesses to EZ memory coincide/collide, this bit determines whether a SW access should block and result in bus wait states ('BLOCK is 1') or not (BLOCK is '0'). IF BLOCK is '0' and the accesses collide, MMIO read operations return 0xffff:ffff and MMIO write operations are ignored. Colliding accesses are registered as interrupt causes: field BLOCKED of MMIO registers INTR_TX and INTR_RX. [17:17] read-write MODE N/A [25:24] read-write I2C Inter-Integrated Circuits (I2C) mode. 0 SPI Serial Peripheral Interface (SPI) mode. 1 UART Universal Asynchronous Receiver/Transmitter (UART) mode. 2 ENABLED IP enabled ('1') or not ('0'). The proper order in which to initialize the IP is as follows: - Program protocol specific information using SPI_CTRL, UART_CTRL (and UART_TX_CTRL and UART_RX_CTRL) or I2C_CTRL. This includes selection of a submode, master/slave functionality and transmitter/receiver functionality when applicable. - Program generic transmitter (TX_CTRL) and receiver (RX_CTRL) information. This includes enabling of the transmitter and receiver functionality. - Program transmitter FIFO (TX_FIFO_CTRL) and receiver FIFO (RX_FIFO_CTRL) information. - Program CTRL to enable IP, select the specific operation mode and oversampling factor. When the IP is enabled, no control information should be changed. Changes should be made AFTER disabling the IP, e.g. to modify the operation mode (from I2C to SPI) or to go from externally to internally clocked. The change takes effect after the IP is re-enabled. Note that disabling the IP will cause re-initialization of the design and associated state is lost (e.g. FIFO content). [31:31] read-write STATUS Generic status 0x4 32 read-only 0x0 0x0 EC_BUSY Indicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ mode). This bit can be used by SW to determine whether it is safe to issue a SW access to the EZ memory (without bus wait states (a blocked SW access) or bus errors being generated). Note that the INTR_TX.BLOCKED and INTR_RX.BLOCKED interrupt causes are used to indicate whether a SW access was actually blocked by externally clocked logic. [0:0] read-only CMD_RESP_CTRL Command/response control 0x8 32 read-write 0x0 0x1FF01FF BASE_RD_ADDR I2C/SPI read base address for CMD_RESP mode. Address is used by a I2C CMD_RESP mode read transfer (CTRL.MODE is I2C) or a SPI CMD_RESP mode read transfer (CTRL.MODE is SPI): at the start of a read transfer BASE_RD_ADDR is copied to CMD_RESP_STATUS.CURR_RD_ADDR. This field should not be modified during ongoing bus transfers. [8:0] read-write BASE_WR_ADDR I2C/SPI write base address for CMD_RESP mode. Address is used by a I2C CMD_RESP mode write transfer (CTRL.MODE is I2C) or a SPI CMD_RESP mode write transfer (CTRL.MODE is SPI): at the start of a write transfer BASE_WE_ADDR is copied to CMD_RESP_STATUS.CURR_WR_ADDR. This field should not be modified during ongoing bus transfers. [24:16] read-write CMD_RESP_STATUS Command/response status 0xC 32 read-only 0x0 0x0 CURR_RD_ADDR I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However, when the last memory buffer address is reached, the address is NOT incremented (but remains at the maximum memory buffer address). The field is used to determine how many bytes have been read (# bytes = CURR_RD_ADDR - CMD_RESP_CTRL.BASE_RD_ADDR). This field is reliable during when there is no bus transfer. This field is potentially unreliable when there is a bus transfer bus transfer: when CMD_RESP_EC_BUSY is '0', the field is reliable. [8:0] read-only CURR_WR_ADDR I2C/SPI write current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However, when the last memory buffer address is reached, the address is NOT incremented (but remains at the maximum memory buffer address). The field is used to determine how many bytes have been written (# bytes = CURR_WR_ADDR - CMD_RESP_CTRL.BASE_WR_ADDR). This field is reliable during when there is no bus transfer. This field is potentially unreliable when there is a bus transfer bus transfer: when CMD_RESP_EC_BUSY is '0', the field is reliable. [24:16] read-only CMD_RESP_EC_BUS_BUSY Indicates whether there is an ongoing bus transfer to the IP. '0': no ongoing bus transfer. '1': ongoing bus transfer. For SPI, the field is '1' when the slave is selected. For I2C, the field is set to '1' at a I2C START/RESTART. In case of an address match, the field is set to '0' on a I2C STOP. In case of NO address match, the field is set to '0' after the failing address match. [30:30] read-only CMD_RESP_EC_BUSY Indicates whether the CURR_RD_ADDR and CURR_WR_ADDR fields in this register are reliable (when CMD_RESP_EC_BUSY is '0') or not reliable (when CMD_RESP_EC_BUSY is '1'). Note: - When there is no ongoing bus transfer, CMD_RESP_EC_BUSY is '0' (reliable). - When there is a ongoing bus transfer, CMD_RESP_EC_BUSY is '0' (reliable), when the CURR_RD_ADDR and CURR_WR_ADDR are not being updated by the HW. - When there is a ongoing bus transfer, CMD_RESP_EC_BUSY is '1' (not reliable), when the CURR_RD_ADDR or CURR_WR_ADDR are being updated by the HW. Note that this update lasts one I2C clock cycle, or two SPI clock cycles. [31:31] read-only SPI_CTRL SPI control 0x20 32 read-write 0x3000000 0x8F010F3F SSEL_CONTINUOUS Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode, both continuous and non-continuous SPI data transfers are supported independent of this field. When continuous transfers are enabled individual data frame transfers are not necessarily separated by slave deselection (as indicated by the level or pulse on the SELECT line): if the TX FIFO has multiple data frames, data frames are send out without slave deselection. When continuous transfers are not enabled individual data frame transfers are always separated by slave deselection: independent of the availability of TX FIFO data frames. [0:0] read-write SELECT_PRECEDE Only used in SPI Texas Instruments' submode. When '1', the data frame start indication is a pulse on the SELECT line that precedes the transfer of the first data frame bit. When '0', the data frame start indication is a pulse on the SELECT line that coincides with the transfer of the first data frame bit. [1:1] read-write CPHA Indicates the clock phase. This field, together with the CPOL field, indicates when MOSI data is driven and MISO data is captured: - Motorola mode 0. CPOL is '0', CPHA is '0': MOSI is driven on a falling edge of SCLK. MISO is captured on a rising edge of SCLK. - Motorola mode 1. CPOL is '0', CPHA is '1': MOSI is driven on a rising edge of SCLK. MISO is captured on a falling edge of SCLK. - Motorola mode 2. CPOL is '1', CPHA is '0': MOSI is driven on a rising edge of SCLK. MISO is captured on a falling edge of SCLK. - Motorola mode 3. CPOL is '1', CPHA is '1': MOSI is driven on a falling edge of SCLK. MISO is captured on a rising edge of SCLK. In SPI Motorola submode, all four CPOL/CPHA modes are valid. in SPI NS submode, only CPOL=0 CPHA=0 mode is valid. in SPI TI submode, only CPOL=0 CPHA=1 mode is valid. [2:2] read-write CPOL Indicates the clock polarity. This field, together with the CPHA field, indicates when MOSI data is driven and MISO data is captured: - CPOL is '0': SCLK is '0' when not transmitting data. - CPOL is '1': SCLK is '1' when not transmitting data. [3:3] read-write LATE_MISO_SAMPLE Changes the SCLK edge on which MISO is captured. Only used in master mode. When '0', the default applies (for Motorola as determined by CPOL and CPHA, for Texas Instruments on the falling edge of SCLK and for National Semiconductors on the rising edge of SCLK). When '1', the alternate clock edge is used (which comes half a SPI SCLK period later). Late sampling addresses the round trip delay associated with transmitting SCLK from the master to the slave and transmitting MISO from the slave to the master. [4:4] read-write SCLK_CONTINUOUS Only applicable in master mode. '0': SCLK is generated, when the SPI master is enabled and data is transmitted. '1': SCLK is generated, when the SPI master is enabled. This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality. [5:5] read-write SSEL_POLARITY0 Slave select polarity. SSEL_POLARITY0 applies to the outgoing SPI slave select signal 0 (master mode) and to the incoming SPI slave select signal (slave mode). For Motorola and National Semiconductors submodes: '0': slave select is low/'0' active. '1': slave select is high/'1' active. For Texas Instruments submode: '0': high/'1' active precede/coincide pulse. '1': low/'0' active precede/coincide pulse. [8:8] read-write SSEL_POLARITY1 Slave select polarity. [9:9] read-write SSEL_POLARITY2 Slave select polarity. [10:10] read-write SSEL_POLARITY3 Slave select polarity. [11:11] read-write LOOPBACK Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode. '0': the SPI master MISO line 'spi_miso_in' is connected to the SPI MISO pin. '1': the SPI master MISO line 'spi_miso_in' is connected to the SPI master MOSI line 'spi_mosi_out'. In other words, in loopback mode the SPI master receives on MISO what it transmits on MOSI. [16:16] read-write MODE N/A [25:24] read-write SPI_MOTOROLA SPI Motorola submode. In master mode, when not transmitting data (SELECT is inactive), SCLK is stable at CPOL. In slave mode, when not selected, SCLK is ignored; i.e. it can be either stable or clocking. In master mode, when there is no data to transmit (TX FIFO is empty), SELECT is inactive. 0 SPI_TI SPI Texas Instruments submode. In master mode, when not transmitting data, SCLK is stable at '0'. In slave mode, when not selected, SCLK is ignored; i.e. it can be either stable or clocking. In master mode, when there is no data to transmit (TX FIFO is empty), SELECT is inactive; i.e. no pulse is generated. 1 SPI_NS SPI National Semiconductors submode. In master mode, when not transmitting data, SCLK is stable at '0'. In slave mode, when not selected, SCLK is ignored; i.e. it can be either stable or clocking. In master mode, when there is no data to transmit (TX FIFO is empty), SELECT is inactive. 2 SSEL Selects one of the four incoming/outgoing SPI slave select signals: - 0: Slave 0, SSEL[0]. - 1: Slave 1, SSEL[1]. - 2: Slave 2, SSEL[2]. - 3: Slave 3, SSEL[3]. The IP should be disabled when changes are made to this field. [27:26] read-write MASTER_MODE Master ('1') or slave ('0') mode. In master mode, transmission will commence on availability of data frames in the TX FIFO. In slave mode, when selected and there is no data frame in the TX FIFO, the slave will transmit all '1's. In both master and slave modes, received data frames will be lost if the RX FIFO is full. [31:31] read-write SPI_STATUS SPI status 0x24 32 read-only 0x0 0x0 BUS_BUSY SPI bus is busy. The bus is considered busy ('1') during an ongoing transaction. For Motorola and National submodes, the busy bit is '1', when the slave selection is activated. For TI submode, the busy bit is '1' from the time the preceding/coinciding slave select is activated for the first transmitted data frame, till the last MOSI/MISO bit of the last data frame is transmitted. [0:0] read-only SPI_EC_BUSY Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_ADDR and CURR_ADDR are reliable. [1:1] read-only CURR_EZ_ADDR SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1'), as clock domain synchronization is not performed in the design. [15:8] read-only BASE_EZ_ADDR SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable, as clock domain synchronization is not performed in the design. [23:16] read-only UART_CTRL UART control 0x40 32 read-write 0x3000000 0x3010000 LOOPBACK Local loopback control (does NOT affect the information on the pins). When '0', the transmitter TX line 'uart_tx_out' is connected to the TX pin and the receiver RX line 'uart_rx_in' is connected to the RX pin. When '1', the transmitter TX line 'uart_tx_out' is connected to the receiver RX line 'uart_rx_in'. A similar connections scheme is followed for 'uart_rts_out' and 'uart_cts_in'. This allows a SCB UART transmitter to communicate with its receiver counterpart. [16:16] read-write MODE N/A [25:24] read-write UART_STD Standard UART submode. 0 UART_SMARTCARD SmartCard (ISO7816) submode. Support for negative acknowledgement (NACK) on the receiver side and retransmission on the transmitter side. 1 UART_IRDA Infrared Data Association (IrDA) submode. Return to Zero modulation scheme. 2 UART_TX_CTRL UART transmitter control 0x44 32 read-write 0x2 0x137 STOP_BITS Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1, 7]; i.e. a stop period should last at least one bit period. [2:0] read-write PARITY Parity bit. When '0', the transmitter generates an even parity. When '1', the transmitter generates an odd parity. Only applicable in standard UART and SmartCard submodes. [4:4] read-write PARITY_ENABLED Parity generation enabled ('1') or not ('0'). Only applicable in standard UART submodes. In SmartCard submode, parity generation is always enabled through hardware. In IrDA submode, parity generation is always disabled through hardware [5:5] read-write RETRY_ON_NACK When '1', a data frame is retransmitted when a negative acknowledgement is received. Only applicable to the SmartCard submode. [8:8] read-write UART_RX_CTRL UART receiver control 0x48 32 read-write 0xA0002 0xF3777 STOP_BITS Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1, 7]; i.e. a stop period should last at least one bit period. Note that in case of a stop bits error, the successive data frames may get lost as the receiver needs to resynchronize its start bit detection. The amount of lost data frames depends on both the amount of stop bits, the idle ('1') time between data frames and the data frame value. [2:0] read-write PARITY Parity bit. When '0', the receiver expects an even parity. When '1', the receiver expects an odd parity. Only applicable in standard UART and SmartCard submodes. [4:4] read-write PARITY_ENABLED Parity checking enabled ('1') or not ('0'). Only applicable in standard UART submode. In SmartCard submode, parity checking is always enabled through hardware. In IrDA submode, parity checking is always disabled through hardware. [5:5] read-write POLARITY Inverts incoming RX line signal 'uart_rx_in'. Inversion is after local loopback. This functionality is intended for IrDA receiver functionality. [6:6] read-write DROP_ON_PARITY_ERROR Behavior when a parity check fails. When '0', received data is send to the RX FIFO. When '1', received data is dropped and lost. Only applicable in standard UART and SmartCard submodes (negatively acknowledged SmartCard data frames may be dropped with this field). [8:8] read-write DROP_ON_FRAME_ERROR Behavior when an error is detected in a start or stop period. When '0', received data is send to the RX FIFO. When '1', received data is dropped and lost. [9:9] read-write MP_MODE Multi-processor mode. When '1', multi-processor mode is enabled. In this mode, RX_CTRL.DATA_WIDTH should indicate a 9-bit data frame. In multi-processor mode, the 9th received bit of a data frame separates addresses (bit is '1') from data (bit is '0'). A received address is matched with RX_MATCH.DATA and RX_MATCH.MASK. In the case of a match, subsequent received data are sent to the RX FIFO. In the case of NO match, subsequent received data are dropped. [10:10] read-write LIN_MODE Only applicable in standard UART submode. When '1', the receiver performs break detection and baud rate detection on the incoming data. First, break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies the minimum required amount of bit periods. Successful break detection sets the INTR_RX.BREAK_DETECT interrupt cause to '1'. Second, baud rate detection counts the amount of peripheral clock periods that are use to receive the synchronization byte (0x55; least significant bit first). The count is available through UART_RX_STATUS.BR_COUNTER. Successful baud rate detection sets the INTR_RX.BAUD_DETECT interrupt cause to '1' (BR_COUNTER is reliable). This functionality is used to synchronize/refine the receiver clock to the transmitter clock. The receiver software can use the BR_COUNTER value to set the right IP clock (from the programmable clock IP) to guarantee successful receipt of the first LIN data frame (Protected Identifier Field) after the synchronization byte. [12:12] read-write SKIP_START Only applicable in standard UART submode. When '1', the receiver skips start bit detection for the first received data frame. Instead, it synchronizes on the first received data frame bit, which should be a '1'. This functionality is intended for wake up from DeepSleep when receiving a data frame. The transition from idle ('1') to START ('0') on the RX line is used to wake up the CPU. The transition detection (and the associated wake up functionality) is performed by the GPIO2 IP. The woken up CPU will enable the SCB's UART receiver functionality. Once enabled, it is assumed that the START bit is ongoing (the CPU wakeup and SCB enable time should be less than the START bit period). The SCB will synchronize to a '0' to '1' transition, which indicates the first data frame bit is received (first data frame bit should be '1'). After synchronization to the first data frame bit, the SCB will resume normal UART functionality: subsequent data frames will be synchronized on the receipt of a START bit. [13:13] read-write BREAK_WIDTH Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once, the break is detected, the INTR_RX.BREAK_DETECT bit is set to '1'. Note that break detection precedes baud rate detection, which is used to synchronize/refine the receiver clock to the transmitter clock. As a result, break detection operates with an unsynchronized/unrefined receiver clock. Therefore, the receiver's definition of a bit period is imprecise and the setting of this field should take this imprecision into account. The LIN standard also accounts for this imprecision: a LIN start bit followed by 8 data bits allows for up to 9 consecutive '0' bit periods during regular transmission, whereas the LIN break detection should be at least 13 consecutive '0' bit periods. This provides for a margin of 4 bit periods. Therefore, the default value of this field is set to 10, representing a minimal break field with of 10+1 = 11 bit periods; a value in between the 9 consecutive bit periods of a regular transmission and the 13 consecutive bit periods of a break field. This provides for slight imprecisions of the receiver clock wrt. the transmitter clock. There should not be a need to program this field to any value other than its default value. [19:16] read-write UART_RX_STATUS UART receiver status 0x4C 32 read-only 0x0 0x0 BR_COUNTER Amount of peripheral clock periods that constitute the transmission of a 0x55 data frame (sent least significant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of peripheral clock periods that constitute a bit period. This field has valid data when INTR_RX.BAUD_DETECT is set to '1'. [11:0] read-only UART_FLOW_CTRL UART flow control 0x50 32 read-write 0x0 0x30100FF TRIGGER_LEVEL Trigger level. When the receiver FIFO has less entries than the amount of this field, a Ready To Send (RTS) output signal 'uart_rts_out' is activated. By setting this field to '0', flow control is effectively SW disabled (may be useful for debug purposes). [7:0] read-write RTS_POLARITY Polarity of the RTS output signal 'uart_rts_out': '0': RTS is low/'0' active; 'uart_rts_out' is '0' when active and 'uart_rts_out' is '1' when inactive. '1': RTS is high/'1' active; 'uart_rts_out' is '1' when active and 'uart_rts_out' is '0' when inactive. During IP reset (Hibernate system power mode), 'uart_rts_out' is '1'. This represents an inactive state assuming a low/'0' active polarity. [16:16] read-write CTS_POLARITY Polarity of the CTS input signal 'uart_cts_in': '0': CTS is low/'0' active; 'uart_cts_in' is '0' when active and 'uart_cts_in' is '1' when inactive. '1': CTS is high/'1' active; 'uart_cts_in' is '1' when active and 'uart_cts_in' is '0' when inactive. [24:24] read-write CTS_ENABLED Enable use of CTS input signal 'uart_cts_in' by the UART transmitter: '0': Disabled. The UART transmitter ignores 'uart_cts_in', and transmits when a data frame is available for transmission in the TX FIFO or the TX shift register. '1': Enabled. The UART transmitter uses 'uart_cts_in' to qualify the transmission of data. It transmits when 'uart_cts_in' is active and a data frame is available for transmission in the TX FIFO or the TX shift register. If UART_CTRL.LOOPBACK is '1', 'uart_cts_in' is connected to 'uart_rts_out' in the IP (both signals are subjected to signal polarity changes as indicated by RTS_POLARITY and CTS_POLARITY). [25:25] read-write I2C_CTRL I2C control 0x60 32 read-write 0xFB88 0xC001FBFF HIGH_PHASE_OVS Serial I2C interface high phase oversampling factor. HIGH_PHASE_OVS + 1 peripheral clock periods constitute the high phase of a bit period. The valid range is [5, 15] with input signal median filtering and [4, 15] without input signal median filtering. The field is only used in master mode. In slave mode, the field is NOT used. However, there is a frequency requirement for the IP clock wrt. the regular interface (IF) high time to guarantee functional correct behavior. With input signal median filtering, the IF high time should be >= 6 IP clock cycles and <= 16 IP clock cycles. Without input signal median filtering, the IF high time should be >= 5 IP clock cycles and <= 16 IP clock cycles. [3:0] read-write LOW_PHASE_OVS Serial I2C interface low phase oversampling factor. LOW_PHASE_OVS + 1 peripheral clock periods constitute the low phase of a bit period. The valid range is [7, 15] with input signal median filtering and [6, 15] without input signal median filtering. The field is only used in master mode. In slave mode, the field is NOT used. However, there is a frequency requirement for the IP clock wrt. the regular (no stretching) interface (IF) low time to guarantee functional correct behavior. With input signal median filtering, the IF low time should be >= 8 IP clock cycles and <= 16 IP clock cycles. Without input signal median filtering, the IF low time should be >= 7 IP clock cycles and <= 16 IP clock cycles. [7:4] read-write M_READY_DATA_ACK When '1', a received data element by the master is immediately ACK'd when the receiver FIFO is not full. [8:8] read-write M_NOT_READY_DATA_NACK When '1', a received data element byte the master is immediately NACK'd when the receiver FIFO is full. When '0', clock stretching is used instead (till the receiver FIFO is no longer full). [9:9] read-write S_GENERAL_IGNORE When '1', a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. This is useful for slaves that do not need any data supplied within the general call structure. [11:11] read-write S_READY_ADDR_ACK When '1', a received (matching) slave address is immediately ACK'd when the receiver FIFO is not full. In EZ mode, this field should be set to '1'. [12:12] read-write S_READY_DATA_ACK When '1', a received data element by the slave is immediately ACK'd when the receiver FIFO is not full. In EZ mode, this field should be set to '1'. [13:13] read-write S_NOT_READY_ADDR_NACK For internally clocked logic (EC_AM is '0' and EC_OP is '0') on an address match or general call address (and S_GENERAL_IGNORE is '0'). Only used when: - EC_AM is '0', EC_OP is '0' and non EZ mode. Functionality is as follows: - 1: a received (matching) slave address is immediately NACK'd when the receiver FIFO is full. - 0: clock stretching is performed (till the receiver FIFO is no longer full). For externally clocked logic (EC_AM is '1') on an address match or general call address (and S_GENERAL_IGNORE is '0'). Only used when (NOT used when EC_AM is '1' and EC_OP is '1' and address match and EZ mode): - EC_AM is '1' and EC_OP is '0'. - EC_AM is '1' and general call address match. - EC_AM is '1' and non EZ mode. Functionality is as follows: - 1: a received (matching or general) slave address is always immediately NACK'd. There are two possibilities: 1). the internally clocked logic is enabled (we are in Active system power mode) and it handles the rest of the current transfer. In this case the I2C master will not observe the NACK. 2). the internally clocked logic is not enabled (we are in DeepSleep system power mode). In this case the I2C master will observe the NACK and may retry the transfer in the future (which gives the internally clocked logic the time to wake up from DeepSleep system power mode). - 0: clock stretching is performed (till the internally clocked logic takes over). The internally clocked logic will handle the ongoing transfer as soon as it is enabled. [14:14] read-write S_NOT_READY_DATA_NACK For internally clocked logic only. Only used when: - non EZ mode. Functionality is as follows: - 1: a received data element byte the slave is immediately NACK'd when the receiver FIFO is full. - 0: clock stretching is performed (till the receiver FIFO is no longer full). [15:15] read-write LOOPBACK Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode. When '0', the I2C SCL and SDA lines are connected to the I2C SCL and SDA pins. When '1', I2C SCL and SDA lines are routed internally in the peripheral, and as a result unaffected by other I2C devices. This allows a SCB I2C peripheral to address itself. [16:16] read-write SLAVE_MODE Slave mode enabled ('1') or not ('0'). [30:30] read-write MASTER_MODE Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the IP to address itself. [31:31] read-write I2C_STATUS I2C status 0x64 32 read-only 0x0 0x31 BUS_BUSY I2C bus is busy. The bus is considered busy ('1'), from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0'), from the time a STOP is detected. If the IP is disabled, BUS_BUSY is '0'. After enabling the IP, it takes time for the BUS_BUSY to detect a busy bus. This time is the maximum high time of the SCL line. For a 100 kHz interface frequency, this maximum high time may last roughly 5 us (half a bit period). For single master systems, BUS_BUSY does not have to be used to detect an idle bus before a master starts a transfer using I2C_M_CMD.M_START (no bus collisions). For multi-master systems, BUS_BUSY can be used to detect an idle bus before a master starts a transfer using I2C_M_CMD.M_START_ON_IDLE (to prevent bus collisions). [0:0] read-only I2C_EC_BUSY Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_EZ_ADDR and CURR_EZ_ADDR are reliable. [1:1] read-only S_READ I2C slave read transfer ('1') or I2C slave write transfer ('0'). When the I2C slave is inactive/idle or receiving START, REPEATED START, STOP or an address, this field is '0''. [4:4] read-only M_READ I2C master read transfer ('1') or I2C master write transfer ('0'). When the I2C master is inactive/idle or transmitting START, REPEATED START, STOP or an address, this field is '0''. [5:5] read-only CURR_EZ_ADDR I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1'), as clock domain synchronization is not performed in the design. [15:8] read-only BASE_EZ_ADDR I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable, as clock domain synchronization is not performed in the design. [23:16] read-only I2C_M_CMD I2C master command 0x68 32 read-write 0x0 0x1F M_START When '1', transmit a START or REPEATED START. Whether a START or REPEATED START is transmitted depends on the state of the master state machine. A START is only transmitted when the master state machine is in the default state. A REPEATED START is transmitted when the master state machine is not in the default state, but is working on an ongoing transaction. The REPEATED START can only be transmitted after a NACK or ACK has been received for a transmitted data element or after a NACK has been transmitted for a received data element. When this action is performed, the hardware sets this field to '0'. [0:0] read-write M_START_ON_IDLE When '1', transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0', note that BUSY has a default value of '0'). For bus idle detection the hardware relies on STOP detection. As a result, bus idle detection is only functional after at least one I2C bus transfer has been detected on the bus (default/reset value of BUSY is '0') . A START is only transmitted when the master state machine is in the default state. When this action is performed, the hardware sets this field to '0'. [1:1] read-write M_ACK When '1', attempt to transmit an acknowledgement (ACK). When this action is performed, the hardware sets this field to '0'. [2:2] read-write M_NACK When '1', attempt to transmit a negative acknowledgement (NACK). When this action is performed, the hardware sets this field to '0'. [3:3] read-write M_STOP When '1', attempt to transmit a STOP. When this action is performed, the hardware sets this field to '0'. I2C_M_CMD.M_START has a higher priority than this command: in situations where both a STOP and a REPEATED START could be transmitted, M_START takes precedence over M_STOP. [4:4] read-write I2C_S_CMD I2C slave command 0x6C 32 read-write 0x0 0x3 S_ACK When '1', attempt to transmit an acknowledgement (ACK). When this action is performed, the hardware sets this field to '0'. In EZ mode, this field should be set to '0' (it is only to be used in non EZ mode). [0:0] read-write S_NACK When '1', attempt to transmit a negative acknowledgement (NACK). When this action is performed, the hardware sets this field to '0'. In EZ mode, this field should be set to '0' (it is only to be used in non EZ mode). This command has a higher priority than I2C_S_CMD.S_ACK, I2C_CTRL.S_READY_ADDR_ACK or I2C_CTRL.S_READY_DATA_ACK. [1:1] read-write I2C_CFG I2C configuration 0x70 32 read-write 0x2A1013 0x303F1313 SDA_IN_FILT_TRIM Trim bits for 'i2c_sda_in' 50 ns filter. See s8i2cs BROS (001-59539) for more details on the trim bit values. SDA_IN_FILT_TRIM[1] is used to enable I2CS_EC or SPIS_EC access to internal SRAM memory. 1: enable clock_scb_en, has no effect on ec_busy_pp 0: disable clock_scb_en, enable ec_busy_pp (grant I2CS_EC or SPIS_EC access) [1:0] read-write SDA_IN_FILT_SEL Selection of 'i2c_sda_in' filter delay: '0': 0 ns. '1: 50 ns (filter enabled). [4:4] read-write SCL_IN_FILT_TRIM Trim bits for 'i2c_scl_in' 50 ns filter. See s8i2cs BROS (001-59539) for more details on the trim bit values. [9:8] read-write SCL_IN_FILT_SEL Selection of 'i2c_scl_in' filter delay: '0': 0 ns. '1: 50 ns (filter enabled). [12:12] read-write SDA_OUT_FILT0_TRIM Trim bits for 'i2c_sda_out' 50 ns filter 0. See s8i2cs BROS (001-59539) for more details on the trim bit values. [17:16] read-write SDA_OUT_FILT1_TRIM Trim bits for 'i2c_sda_out' 50 ns filter 1. See s8i2cs BROS (001-59539) for more details on the trim bit values. [19:18] read-write SDA_OUT_FILT2_TRIM Trim bits for 'i2c_sda_out' 50 ns filter 2. See s8i2cs BROS (001-59539) for more details on the trim bit values. [21:20] read-write SDA_OUT_FILT_SEL Selection of cumulative 'i2c_sda_out' filter delay: '0': 0 ns. '1': 50 ns (filter 0 enabled). '2': 100 ns (filters 0 and 1 enabled). '3': 150 ns (filters 0, 1 and 2 enabled). [29:28] read-write TX_CTRL Transmitter control 0x200 32 read-write 0x107 0x1010F DATA_WIDTH Dataframe width. DATA_WIDTH + 1 is the amount of bits in a transmitted data frame. This number does not include start, parity and stop bits. For UART mode, the valid range is [3, 8]. For SPI, the valid range is [3, 15]. For I2C the only valid value is 7. [3:0] read-write MSB_FIRST Least significant bit first ('0') or most significant bit first ('1'). For I2C, this field should be '1'. [8:8] read-write OPEN_DRAIN Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'. '0': Normal operation mode. Typically, this operation mode is used for IO cells that are connected to (board) wires/lines that are driven by a single IO cell. In this operation mode, for an IO cell 'xxx' that is used as an output, the 'xxx_out_en' output enable signal is typically constant '1' the 'xxx_out' output is the outputted value. In other words, in normal operation mode, the 'xxx_out' output is used to control the IO cell output value: 'xxx_out' is '0' to drive an IO cell output value of '0' and 'xxx_out' is '1' to drive an IO cell output value of '1'. '1': Open drain operation mode. Typically this operation mode is used for IO cells that are connected to (board) wires/lines that are driven by multiple IO cells (possibly on multiple chips). In this operation mode, for and IO cell 'xxx' that is used as an output, the 'xxx_out_en' output controls the outputted value. Typically, open drain operation mode drives low/'0' and the 'xxx_out' output is constant '1'. In other words, in open drain operation mode, the 'xxx_out_en' output is used to control the IO cell output value: in drive low/'0' mode: 'xxx_out_en' is '1' (drive enabled) to drive an IO cell output value of '0' and 'xxx_out_en' is '1' (drive disabled) to not drive an IO cell output value (another IO cell can drive the wire/line or a pull up results in a wire/line value '1'). The open drain mode is supported for: - I2C mode, 'i2c_scl' and 'i2c_sda' IO cells. - UART mode, 'uart_tx' IO cell. - SPI mode, 'spi_miso' IO cell. [16:16] read-write TX_FIFO_CTRL Transmitter FIFO control 0x204 32 read-write 0x0 0x300FF TRIGGER_LEVEL Trigger level. When the transmitter FIFO has less entries than the number of this field, a transmitter trigger event INTR_TX.TRIGGER is generated. [7:0] read-write CLEAR When '1', the transmitter FIFO and transmitter shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period. [16:16] read-write FREEZE When '1', hardware reads from the transmitter FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer. [17:17] read-write TX_FIFO_STATUS Transmitter FIFO status 0x208 32 read-only 0x0 0xFFFF81FF USED Amount of entries in the transmitter FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2). [8:0] read-only SR_VALID Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0'). The shift register can be considered the top of the TX FIFO (the data frame is not included in the USED field of the TX FIFO). The shift register is a working register and holds the data frame that is currently transmitted (when the protocol state machine is transmitting a data frame) or the data frame that is transmitted next (when the protocol state machine is not transmitting a data frame). [15:15] read-only RD_PTR FIFO read pointer: FIFO location from which a data frame is read by the hardware. [23:16] read-only WR_PTR FIFO write pointer: FIFO location at which a new data frame is written. [31:24] read-only TX_FIFO_WR Transmitter FIFO write 0x240 32 write-only 0x0 0xFFFF DATA Data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH operation. Note that when CTRL.BYTE_MODE is '1', only DATA[7:0] are used. A write to a full TX FIFO sets INTR_TX.OVERFLOW to '1'. [15:0] write-only RX_CTRL Receiver control 0x300 32 read-write 0x107 0x30F DATA_WIDTH Dataframe width. DATA_WIDTH + 1 is the expected amount of bits in received data frame. This number does not include start, parity and stop bits. For UART mode, the valid range is [3, 8]. For SPI, the valid range is [3, 15]. For I2C the only valid value is 7. In EZ mode (for both SPI and I2C), the only valid value is 7. [3:0] read-write MSB_FIRST Least significant bit first ('0') or most significant bit first ('1'). For I2C, this field should be '1'. [8:8] read-write MEDIAN Median filter. When '1', a digital 3 taps median filter is performed on input interface lines. This filter should reduce the susceptibility to errors. However, its requires higher oversampling values. For UART IrDA submode, this field should always be '1'. [9:9] read-write RX_FIFO_CTRL Receiver FIFO control 0x304 32 read-write 0x0 0x300FF TRIGGER_LEVEL Trigger level. When the receiver FIFO has more entries than the number of this field, a receiver trigger event INTR_RX.TRIGGER is generated. [7:0] read-write CLEAR When '1', the receiver FIFO and receiver shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period. [16:16] read-write FREEZE When '1', hardware writes to the receiver FIFO have no effect. Freeze will not advance the RX FIFO write pointer. [17:17] read-write RX_FIFO_STATUS Receiver FIFO status 0x308 32 read-only 0x0 0xFFFF81FF USED Amount of entries in the receiver FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2). [8:0] read-only SR_VALID Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0'). The shift register can be considered the bottom of the RX FIFO (the data frame is not included in the USED field of the RX FIFO). The shift register is a working register and holds the data frame that is currently being received (when the protocol state machine is receiving a data frame). [15:15] read-only RD_PTR FIFO read pointer: FIFO location from which a data frame is read. [23:16] read-only WR_PTR FIFO write pointer: FIFO location at which a new data frame is written by the hardware. [31:24] read-only RX_MATCH Slave address and mask 0x310 32 read-write 0x0 0xFF00FF ADDR Slave device address. In UART multi-processor mode, all 8 bits are used. In I2C slave mode, only bits 7 down to 1 are used. This reflects the organization of the first transmitted byte in a I2C transfer: the first 7 bits represent the address of the addressed slave, and the last 1 bit is a read/write indicator ('0': write, '1': read). [7:0] read-write MASK Slave device address mask. This field is a mask that specifies which of the ADDR field bits in the ADDR field take part in the matching of the slave address: MATCH = ((ADDR & MASK) == ('slave address' & MASK)). [23:16] read-write RX_FIFO_RD Receiver FIFO read 0x340 32 read-only 0x0 0x0 DATA Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.BYTE_MODE is '1', only DATA[7:0] are used. This register has a side effect when read by software: a data frame is removed from the FIFO. This may be undesirable during debug; i.e. a read during debug should NOT have a side effect. To this end, the IP uses the AHB-Lite 'hmaster[0]' input signal. When this signal is '1' in the address cycle of a bus transfer, a read transfer will not have a side effect. As a result, a read from this register will not remove a data frame from the FIFO. As a result, a read from this register behaves as a read from the SCB_RX_FIFO_RD_SILENT register. A read from an empty RX FIFO sets INTR_RX.UNDERFLOW to '1'. [15:0] read-only RX_FIFO_RD_SILENT Receiver FIFO read silent 0x344 32 read-only 0x0 0x0 DATA Data read from the receiver FIFO. Reading a data frame will NOT remove the data frame from the FIFO; i.e. behavior is similar to that of a PEEK operation. Note that when CTRL.BYTE_MODE is '1', only DATA[7:0] are used. A read from an empty RX FIFO sets INTR_RX.UNDERFLOW to '1'. [15:0] read-only INTR_CAUSE Active clocked interrupt signal 0xE00 32 read-only 0x0 0x3F M Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0. [0:0] read-only S Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0. [1:1] read-only TX Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0. [2:2] read-only RX Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0. [3:3] read-only I2C_EC Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0. [4:4] read-only SPI_EC Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0. [5:5] read-only INTR_I2C_EC Externally clocked I2C interrupt request 0xE80 32 read-write 0x0 0xF WAKE_UP Wake up request. Active on incoming slave request (with address match). Only used when EC_AM is '1'. [0:0] read-write EZ_STOP STOP detection. Activated on the end of a every transfer (I2C STOP). Only available for a slave request with an address match, in EZ and CMD_RESP modes, when EC_OP is '1'. [1:1] read-write EZ_WRITE_STOP STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address does NOT activate this event. Only available for a slave request with an address match, in EZ and CMD_RESP modes, when EC_OP is '1'. [2:2] read-write EZ_READ_STOP STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from. Only available for a slave request with an address match, in EZ and CMD_RESP modes, when EC_OP is '1'. [3:3] read-write INTR_I2C_EC_MASK Externally clocked I2C interrupt mask 0xE88 32 read-write 0x0 0xF WAKE_UP Mask bit for corresponding bit in interrupt request register. [0:0] read-write EZ_STOP Mask bit for corresponding bit in interrupt request register. [1:1] read-write EZ_WRITE_STOP Mask bit for corresponding bit in interrupt request register. [2:2] read-write EZ_READ_STOP Mask bit for corresponding bit in interrupt request register. [3:3] read-write INTR_I2C_EC_MASKED Externally clocked I2C interrupt masked 0xE8C 32 read-only 0x0 0xF WAKE_UP Logical and of corresponding request and mask bits. [0:0] read-only EZ_STOP Logical and of corresponding request and mask bits. [1:1] read-only EZ_WRITE_STOP Logical and of corresponding request and mask bits. [2:2] read-only EZ_READ_STOP Logical and of corresponding request and mask bits. [3:3] read-only INTR_SPI_EC Externally clocked SPI interrupt request 0xEC0 32 read-write 0x0 0xF WAKE_UP Wake up request. Active on incoming slave request when externally clocked selection is '1'. Only used when EC_AM is '1'. [0:0] read-write EZ_STOP STOP detection. Activated on the end of a every transfer (SPI deselection). Only available in EZ and CMD_RESP mode and when EC_OP is '1'. [1:1] read-write EZ_WRITE_STOP STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address does NOT activate this event. Only used in EZ and CMD_RESP modes and when EC_OP is '1'. [2:2] read-write EZ_READ_STOP STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from. Only used in EZ and CMD_RESP modes and when EC_OP is '1'. [3:3] read-write INTR_SPI_EC_MASK Externally clocked SPI interrupt mask 0xEC8 32 read-write 0x0 0xF WAKE_UP Mask bit for corresponding bit in interrupt request register. [0:0] read-write EZ_STOP Mask bit for corresponding bit in interrupt request register. [1:1] read-write EZ_WRITE_STOP Mask bit for corresponding bit in interrupt request register. [2:2] read-write EZ_READ_STOP Mask bit for corresponding bit in interrupt request register. [3:3] read-write INTR_SPI_EC_MASKED Externally clocked SPI interrupt masked 0xECC 32 read-only 0x0 0xF WAKE_UP Logical and of corresponding request and mask bits. [0:0] read-only EZ_STOP Logical and of corresponding request and mask bits. [1:1] read-only EZ_WRITE_STOP Logical and of corresponding request and mask bits. [2:2] read-only EZ_READ_STOP Logical and of corresponding request and mask bits. [3:3] read-only INTR_M Master interrupt request 0xF00 32 read-write 0x0 0x317 I2C_ARB_LOST I2C master lost arbitration: the value driven by the master on the SDA line is not the same as the value observed on the SDA line. [0:0] read-write I2C_NACK I2C master negative acknowledgement. Set to '1', when the master receives a NACK (typically after the master transmitted the slave address or TX data). [1:1] read-write I2C_ACK I2C master acknowledgement. Set to '1', when the master receives a ACK (typically after the master transmitted the slave address or TX data). [2:2] read-write I2C_STOP I2C master STOP. Set to '1', when the master has transmitted a STOP. [4:4] read-write I2C_BUS_ERROR I2C master bus error (unexpected detection of START or STOP condition). [8:8] read-write SPI_DONE SPI master transfer done event: all data frames in the transmit FIFO are sent, the transmit FIFO is empty (both TX FIFO and transmit shifter register are empty), and SPI select output pin is deselected. [9:9] read-write INTR_M_SET Master interrupt set request 0xF04 32 read-write 0x0 0x317 I2C_ARB_LOST Write with '1' to set corresponding bit in interrupt request register. [0:0] read-write I2C_NACK Write with '1' to set corresponding bit in interrupt request register. [1:1] read-write I2C_ACK Write with '1' to set corresponding bit in interrupt request register. [2:2] read-write I2C_STOP Write with '1' to set corresponding bit in interrupt request register. [4:4] read-write I2C_BUS_ERROR Write with '1' to set corresponding bit in interrupt request register. [8:8] read-write SPI_DONE Write with '1' to set corresponding bit in interrupt request register. [9:9] read-write INTR_M_MASK Master interrupt mask 0xF08 32 read-write 0x0 0x317 I2C_ARB_LOST Mask bit for corresponding bit in interrupt request register. [0:0] read-write I2C_NACK Mask bit for corresponding bit in interrupt request register. [1:1] read-write I2C_ACK Mask bit for corresponding bit in interrupt request register. [2:2] read-write I2C_STOP Mask bit for corresponding bit in interrupt request register. [4:4] read-write I2C_BUS_ERROR Mask bit for corresponding bit in interrupt request register. [8:8] read-write SPI_DONE Mask bit for corresponding bit in interrupt request register. [9:9] read-write INTR_M_MASKED Master interrupt masked request 0xF0C 32 read-only 0x0 0x317 I2C_ARB_LOST Logical and of corresponding request and mask bits. [0:0] read-only I2C_NACK Logical and of corresponding request and mask bits. [1:1] read-only I2C_ACK Logical and of corresponding request and mask bits. [2:2] read-only I2C_STOP Logical and of corresponding request and mask bits. [4:4] read-only I2C_BUS_ERROR Logical and of corresponding request and mask bits. [8:8] read-only SPI_DONE Logical and of corresponding request and mask bits. [9:9] read-only INTR_S Slave interrupt request 0xF40 32 read-write 0x0 0xFFF I2C_ARB_LOST I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur, it represents erroneous I2C bus behavior. In case of lost arbitration, the I2C slave state machine abort the ongoing transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error. [0:0] read-write I2C_NACK I2C slave negative acknowledgement received. Set to '1', when the slave receives a NACK (typically after the slave transmitted TX data). [1:1] read-write I2C_ACK I2C slave acknowledgement received. Set to '1', when the slave receives a ACK (typically after the slave transmitted TX data). [2:2] read-write I2C_WRITE_STOP I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1', when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C transfers separated by a REPEATED START can be distinguished and potentially treated separately by the Firmware. Note that the second I2C transfer (after a REPEATED START) may be to a different slave address. In non EZ mode, the event is detected on any I2C write transfer intended for this slave. Note that a I2C write address intended for the slave (address is matching and a it is a write transfer) will result in a I2C_WRITE_STOP event independent of whether the I2C address is ACK'd or NACK'd. In EZ mode, the event is detected only on I2C write transfers that have EZ data written to the memory structure (an I2C write transfer that only communicates an I2C address and EZ address, will not result in this event being detected). [3:3] read-write I2C_STOP I2C STOP event for I2C (read or write) transfer intended for this slave (address matching is performed). Set to '1', when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C transfers separated by a REPEATED START can be distinguished and potentially treated separately by the Firmware. Note that the second I2C transfer (after a REPEATED START) may be to a different slave address. The event is detected on any I2C transfer intended for this slave. Note that a I2C address intended for the slave (address is matching) will result in a I2C_STOP event independent of whether the I2C address is ACK'd or NACK'd. [4:4] read-write I2C_START I2C slave START received. Set to '1', when START or REPEATED START event is detected. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') AND clock stretching is performed (till the internally clocked logic takes over) (I2C_CTRL.S_NOT_READY_ADDR_NACK is '0'), this field is NOT set. The Firmware should use INTR_S_EC.WAKE_UP, INTR_S.I2C_ADDR_MATCH and INTR_S.I2C_GENERAL. [5:5] read-write I2C_ADDR_MATCH I2C slave matching address received. If CTRL.ADDR_ACCEPT, the received address (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked operation (CTRL.EC_OP_MODE is '0'), this field is set when the event is detected. [6:6] read-write I2C_GENERAL I2C slave general call address received. If CTRL.ADDR_ACCEPT, the received address 0x00 (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked operation (CTRL.EC_OP_MODE is '0'), this field is set when the event is detected. [7:7] read-write I2C_BUS_ERROR I2C slave bus error (unexpected detection of START or STOP condition). This should not occur, it represents erroneous I2C bus behavior. In case of a bus error, the I2C slave state machine abort the ongoing transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error. [8:8] read-write SPI_EZ_WRITE_STOP SPI slave deselected after a write EZ SPI transfer occurred. [9:9] read-write SPI_EZ_STOP SPI slave deselected after any EZ SPI transfer occurred. [10:10] read-write SPI_BUS_ERROR SPI slave deselected at an unexpected time in the SPI transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error. [11:11] read-write INTR_S_SET Slave interrupt set request 0xF44 32 read-write 0x0 0xFFF I2C_ARB_LOST Write with '1' to set corresponding bit in interrupt request register. [0:0] read-write I2C_NACK Write with '1' to set corresponding bit in interrupt request register. [1:1] read-write I2C_ACK Write with '1' to set corresponding bit in interrupt request register. [2:2] read-write I2C_WRITE_STOP Write with '1' to set corresponding bit in interrupt request register. [3:3] read-write I2C_STOP Write with '1' to set corresponding bit in interrupt request register. [4:4] read-write I2C_START Write with '1' to set corresponding bit in interrupt request register. [5:5] read-write I2C_ADDR_MATCH Write with '1' to set corresponding bit in interrupt request register. [6:6] read-write I2C_GENERAL Write with '1' to set corresponding bit in interrupt request register. [7:7] read-write I2C_BUS_ERROR Write with '1' to set corresponding bit in interrupt request register. [8:8] read-write SPI_EZ_WRITE_STOP Write with '1' to set corresponding bit in interrupt request register. [9:9] read-write SPI_EZ_STOP Write with '1' to set corresponding bit in interrupt request register. [10:10] read-write SPI_BUS_ERROR Write with '1' to set corresponding bit in interrupt request register. [11:11] read-write INTR_S_MASK Slave interrupt mask 0xF48 32 read-write 0x0 0xFFF I2C_ARB_LOST Mask bit for corresponding bit in interrupt request register. [0:0] read-write I2C_NACK Mask bit for corresponding bit in interrupt request register. [1:1] read-write I2C_ACK Mask bit for corresponding bit in interrupt request register. [2:2] read-write I2C_WRITE_STOP Mask bit for corresponding bit in interrupt request register. [3:3] read-write I2C_STOP Mask bit for corresponding bit in interrupt request register. [4:4] read-write I2C_START Mask bit for corresponding bit in interrupt request register. [5:5] read-write I2C_ADDR_MATCH Mask bit for corresponding bit in interrupt request register. [6:6] read-write I2C_GENERAL Mask bit for corresponding bit in interrupt request register. [7:7] read-write I2C_BUS_ERROR Mask bit for corresponding bit in interrupt request register. [8:8] read-write SPI_EZ_WRITE_STOP Mask bit for corresponding bit in interrupt request register. [9:9] read-write SPI_EZ_STOP Mask bit for corresponding bit in interrupt request register. [10:10] read-write SPI_BUS_ERROR Mask bit for corresponding bit in interrupt request register. [11:11] read-write INTR_S_MASKED Slave interrupt masked request 0xF4C 32 read-only 0x0 0xFFF I2C_ARB_LOST Logical and of corresponding request and mask bits. [0:0] read-only I2C_NACK Logical and of corresponding request and mask bits. [1:1] read-only I2C_ACK Logical and of corresponding request and mask bits. [2:2] read-only I2C_WRITE_STOP Logical and of corresponding request and mask bits. [3:3] read-only I2C_STOP Logical and of corresponding request and mask bits. [4:4] read-only I2C_START Logical and of corresponding request and mask bits. [5:5] read-only I2C_ADDR_MATCH Logical and of corresponding request and mask bits. [6:6] read-only I2C_GENERAL Logical and of corresponding request and mask bits. [7:7] read-only I2C_BUS_ERROR Logical and of corresponding request and mask bits. [8:8] read-only SPI_EZ_WRITE_STOP Logical and of corresponding request and mask bits. [9:9] read-only SPI_EZ_STOP Logical and of corresponding request and mask bits. [10:10] read-only SPI_BUS_ERROR Logical and of corresponding request and mask bits. [11:11] read-only INTR_TX Transmitter interrupt request 0xF80 32 read-write 0x0 0x7F3 TRIGGER Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL.TRIGGER_LEVEL. Only used in FIFO mode. [0:0] read-write NOT_FULL TX FIFO is not full. Dependent on CTRL.BYTE_MODE: (FF_DATA_NR = EZ_DATA_NR/2) BYTE_MODE is '0': # entries != FF_DATA_NR/2. BYTE_MODE is '1': # entries != FF_DATA_NR. Only used in FIFO mode. [1:1] read-write EMPTY TX FIFO is empty; i.e. it has 0 entries. Only used in FIFO mode. [4:4] read-write OVERFLOW Attempt to write to a full TX FIFO. Only used in FIFO mode. [5:5] read-write UNDERFLOW Attempt to read from an empty TX FIFO. This happens when the IP is ready to transfer data and EMPTY is '1'. Only used in FIFO mode. [6:6] read-write BLOCKED AHB-Lite write transfer can not get access to the EZ memory (EZ data access), due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'. [7:7] read-write UART_NACK UART transmitter received a negative acknowledgement in SmartCard mode. Set to '1', when event is detected. Write with '1' to clear bit. [8:8] read-write UART_DONE UART transmitter done event. This happens when the IP is done transferring all data in the TX FIFO, and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty). Set to '1', when event is detected. Write with '1' to clear bit. [9:9] read-write UART_ARB_LOST UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. This condition event is useful when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes. Set to '1', when event is detected. Write with '1' to clear bit. [10:10] read-write INTR_TX_SET Transmitter interrupt set request 0xF84 32 read-write 0x0 0x7F3 TRIGGER Write with '1' to set corresponding bit in interrupt request register. [0:0] read-write NOT_FULL Write with '1' to set corresponding bit in interrupt request register. [1:1] read-write EMPTY Write with '1' to set corresponding bit in interrupt request register. [4:4] read-write OVERFLOW Write with '1' to set corresponding bit in interrupt request register. [5:5] read-write UNDERFLOW Write with '1' to set corresponding bit in interrupt request register. [6:6] read-write BLOCKED Write with '1' to set corresponding bit in interrupt request register. [7:7] read-write UART_NACK Write with '1' to set corresponding bit in interrupt request register. [8:8] read-write UART_DONE Write with '1' to set corresponding bit in interrupt request register. [9:9] read-write UART_ARB_LOST Write with '1' to set corresponding bit in interrupt request register. [10:10] read-write INTR_TX_MASK Transmitter interrupt mask 0xF88 32 read-write 0x0 0x7F3 TRIGGER Mask bit for corresponding bit in interrupt request register. [0:0] read-write NOT_FULL Mask bit for corresponding bit in interrupt request register. [1:1] read-write EMPTY Mask bit for corresponding bit in interrupt request register. [4:4] read-write OVERFLOW Mask bit for corresponding bit in interrupt request register. [5:5] read-write UNDERFLOW Mask bit for corresponding bit in interrupt request register. [6:6] read-write BLOCKED Mask bit for corresponding bit in interrupt request register. [7:7] read-write UART_NACK Mask bit for corresponding bit in interrupt request register. [8:8] read-write UART_DONE Mask bit for corresponding bit in interrupt request register. [9:9] read-write UART_ARB_LOST Mask bit for corresponding bit in interrupt request register. [10:10] read-write INTR_TX_MASKED Transmitter interrupt masked request 0xF8C 32 read-only 0x0 0x7F3 TRIGGER Logical and of corresponding request and mask bits. [0:0] read-only NOT_FULL Logical and of corresponding request and mask bits. [1:1] read-only EMPTY Logical and of corresponding request and mask bits. [4:4] read-only OVERFLOW Logical and of corresponding request and mask bits. [5:5] read-only UNDERFLOW Logical and of corresponding request and mask bits. [6:6] read-only BLOCKED Logical and of corresponding request and mask bits. [7:7] read-only UART_NACK Logical and of corresponding request and mask bits. [8:8] read-only UART_DONE Logical and of corresponding request and mask bits. [9:9] read-only UART_ARB_LOST Logical and of corresponding request and mask bits. [10:10] read-only INTR_RX Receiver interrupt request 0xFC0 32 read-write 0x0 0xFED TRIGGER More entries in the RX FIFO than the value specified by RX_FIFO_CTRL.TRIGGER_LEVEL. Only used in FIFO mode. [0:0] read-write NOT_EMPTY RX FIFO is not empty. Only used in FIFO mode. [2:2] read-write FULL RX FIFO is full. Note that received data frames are lost when the RX FIFO is full. Dependent on CTRL.BYTE_MODE: (FF_DATA_NR = EZ_DATA_NR/2) BYTE_MODE is '0': # entries == FF_DATA_NR/2. BYTE_MODE is '1': # entries == FF_DATA_NR. Only used in FIFO mode. [3:3] read-write OVERFLOW Attempt to write to a full RX FIFO. Note: in I2C mode, the OVERFLOW is set when a data frame is received and the RX FIFO is full, independent of whether it is ACK'd or NACK'd. Only used in FIFO mode. [5:5] read-write UNDERFLOW Attempt to read from an empty RX FIFO. Only used in FIFO mode. [6:6] read-write BLOCKED AHB-Lite read transfer can not get access to the EZ memory (EZ_DATA accesses), due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'. [7:7] read-write FRAME_ERROR Frame error in received data frame. Set to '1', when event is detected. Write with '1' to clear bit. This can be either a start or stop bit(s) error: Start bit error: after the detection of the beginning of a start bit period (RX line changes from '1' to '0'), the middle of the start bit period is sampled erroneously (RX line is '1'). Note: a start bit error is detected BEFORE a data frame is received. Stop bit error: the RX line is sampled as '0', but a '1' was expected. Note: a stop bit error may result in failure to receive successive data frame(s). Note: a stop bit error is detected AFTER a data frame is received. A stop bit error is detected after a data frame is received, and the UART_RX_CTL.DROP_ON_FRAME_ERROR field specifies whether the received frame is dropped or send to the RX FIFO. If UART_RX_CTL.DROP_ON_FRAME_ERROR is '1', the received data frame is dropped. If UART_RX_CTL.DROP_ON_FRAME_ERROR is '0', the received data frame is send to the RX FIFO. Note that Firmware can only identify the erroneous data frame in the RX FIFO if it is fast enough to read the data frame before the hardware writes a next data frame into the RX FIFO; i.e. the RX FIFO does not have error flags to tag erroneous data frames. [8:8] read-write PARITY_ERROR Parity error in received data frame. Set to '1', when event is detected. Write with '1' to clear bit. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '1', the received frame is dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '0', the received frame is send to the RX FIFO. In SmartCard submode, negatively acknowledged data frames generate a parity error. Note that Firmware can only identify the erroneous data frame in the RX FIFO if it is fast enough to read the data frame before the hardware writes a next data frame into the RX FIFO. [9:9] read-write BAUD_DETECT LIN baudrate detection is completed. The receiver software uses the UART_RX_STATUS.BR_COUNTER value to set the right IP clock (from the programmable clock IP) to guarantee successful receipt of the first LIN data frame (Protected Identifier Field) after the synchronization byte. Set to '1', when event is detected. Write with '1' to clear bit. [10:10] read-write BREAK_DETECT Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; i.e. 'break-in-data' is supported. This feature is supported for the UART standard and LIN submodes. For the UART standard submodes, ongoing receipt of data frames is NOT affected; i.e. Firmware is expected to take the proper action. For the LIN submode, possible ongoing receipt of a data frame is stopped and the (partially) received data frame is dropped and baud rate detection is started. Set to '1', when event is detected. Write with '1' to clear bit. [11:11] read-write INTR_RX_SET Receiver interrupt set request 0xFC4 32 read-write 0x0 0xFED TRIGGER Write with '1' to set corresponding bit in interrupt request register. [0:0] read-write NOT_EMPTY Write with '1' to set corresponding bit in interrupt status register. [2:2] read-write FULL Write with '1' to set corresponding bit in interrupt status register. [3:3] read-write OVERFLOW Write with '1' to set corresponding bit in interrupt status register. [5:5] read-write UNDERFLOW Write with '1' to set corresponding bit in interrupt status register. [6:6] read-write BLOCKED Write with '1' to set corresponding bit in interrupt status register. [7:7] read-write FRAME_ERROR Write with '1' to set corresponding bit in interrupt status register. [8:8] read-write PARITY_ERROR Write with '1' to set corresponding bit in interrupt status register. [9:9] read-write BAUD_DETECT Write with '1' to set corresponding bit in interrupt status register. [10:10] read-write BREAK_DETECT Write with '1' to set corresponding bit in interrupt status register. [11:11] read-write INTR_RX_MASK Receiver interrupt mask 0xFC8 32 read-write 0x0 0xFED TRIGGER Mask bit for corresponding bit in interrupt request register. [0:0] read-write NOT_EMPTY Mask bit for corresponding bit in interrupt request register. [2:2] read-write FULL Mask bit for corresponding bit in interrupt request register. [3:3] read-write OVERFLOW Mask bit for corresponding bit in interrupt request register. [5:5] read-write UNDERFLOW Mask bit for corresponding bit in interrupt request register. [6:6] read-write BLOCKED Mask bit for corresponding bit in interrupt request register. [7:7] read-write FRAME_ERROR Mask bit for corresponding bit in interrupt request register. [8:8] read-write PARITY_ERROR Mask bit for corresponding bit in interrupt request register. [9:9] read-write BAUD_DETECT Mask bit for corresponding bit in interrupt request register. [10:10] read-write BREAK_DETECT Mask bit for corresponding bit in interrupt request register. [11:11] read-write INTR_RX_MASKED Receiver interrupt masked request 0xFCC 32 read-only 0x0 0xFED TRIGGER Logical and of corresponding request and mask bits. [0:0] read-only NOT_EMPTY Logical and of corresponding request and mask bits. [2:2] read-only FULL Logical and of corresponding request and mask bits. [3:3] read-only OVERFLOW Logical and of corresponding request and mask bits. [5:5] read-only UNDERFLOW Logical and of corresponding request and mask bits. [6:6] read-only BLOCKED Logical and of corresponding request and mask bits. [7:7] read-only FRAME_ERROR Logical and of corresponding request and mask bits. [8:8] read-only PARITY_ERROR Logical and of corresponding request and mask bits. [9:9] read-only BAUD_DETECT Logical and of corresponding request and mask bits. [10:10] read-only BREAK_DETECT Logical and of corresponding request and mask bits. [11:11] read-only SCB1 0x40510000 SCB2 0x40520000 SCB3 0x40530000 SCB4 0x40540000 SCB5 0x40550000 SCB6 0x40560000 CANFD0 CAN Controller CANFD 0x40580000 0 131072 registers CH FIFO wrapper around M_TTCAN 3PIP, to enable DMA 0x00000000 M_TTCAN TTCAN 3PIP, includes FD 0x00000000 CREL Core Release Register 0x0 32 read-only 0x0 0xFFFFFFFF DAY Time Stamp Day Two digits, BCD-coded. This field is set by generic parameter on M_TTCAN synthesis. [7:0] read-only MON Time Stamp Month Two digits, BCD-coded. This field is set by generic parameter on M_TTCAN synthesis. [15:8] read-only YEAR Time Stamp Year One digit, BCD-coded. This field is set by generic parameter on M_TTCAN synthesis. [19:16] read-only SUBSTEP Sub-step of Core Release One digit, BCD-coded. [23:20] read-only STEP Step of Core Release One digit, BCD-coded. [27:24] read-only REL Core Release One digit, BCD-coded. [31:28] read-only ENDN Endian Register 0x4 32 read-only 0x87654321 0xFFFFFFFF ETV Endianness Test Value The endianness test value is 0x87654321. [31:0] read-only DBTP Data Bit Timing & Prescaler Register 0xC 32 read-write 0xA33 0x9F1FFF DSJW Data (Re)Synchronization Jump Width 0x0-0xF Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. [3:0] read-write DTSEG2 Data time segment after sample point 0x0-0xF Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. [7:4] read-write DTSEG1 Data time segment before sample point 0x00-0x1F Valid values are 0 to 31. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. [12:8] read-write DBRP Data Bit Rate Prescaler 0x00-0x1F The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 31. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. [20:16] read-write TDC Transmitter Delay Compensation 0= Transmitter Delay Compensation disabled 1= Transmitter Delay Compensation enabled [23:23] read-write TEST Test Register 0x10 32 read-write 0x0 0x7F TAM ASC is not supported by M_TTCAN Test ASC Multiplexer Control Controls output pin m_ttcan_ascm in test mode, ORed with the signal from the FSE 0= Level at pin m_ttcan_ascm controlled by FSE 1= Level at pin m_ttcan_ascm = '1' [0:0] read-write TAT ASC is not supported by M_TTCAN Test ASC Transmit Control Controls output pin m_ttcan_asct in test mode, ORed with the signal from the FSE 0= Level at pin m_ttcan_asct controlled by FSE 1= Level at pin m_ttcan_asct = '1' [1:1] read-write CAM ASC is not supported by M_TTCAN Check ASC Multiplexer Control Monitors level at output pin m_ttcan_ascm. 0= Output pin m_ttcan_ascm = '0' 1= Output pin m_ttcan_ascm = '1' [2:2] read-write CAT ASC is not supported by M_TTCAN Check ASC Transmit Control Monitors level at output pin m_ttcan_asct. 0= Output pin m_ttcan_asct = '0' [3:3] read-write LBCK Loop Back Mode 0= Reset value, Loop Back Mode is disabled 1= Loop Back Mode is enabled (see Section 3.1.9, Test Modes) [4:4] read-write TX Control of Transmit Pin 00 Reset value, m_ttcan_tx controlled by the CAN Core, updated at the end of the CAN bit time 01 Sample Point can be monitored at pin m_ttcan_tx 10 Dominant ('0') level at pin m_ttcan_tx 11 Recessive ('1') at pin m_ttcan_tx [6:5] read-write RX Receive Pin Monitors the actual value of pin m_ttcan_rx 0= The CAN bus is dominant (m_ttcan_rx = '0') 1= The CAN bus is recessive (m_ttcan_rx = '1') [7:7] read-only RWD RAM Watchdog 0x14 32 read-write 0x0 0xFFFF WDC Watchdog Configuration Start value of the Message RAM Watchdog Counter. With the reset value of '00' the counter is disabled. [7:0] read-write WDV Watchdog Value Actual Message RAM Watchdog Counter Value. [15:8] read-only CCCR CC Control Register 0x18 32 read-write 0x1 0xF3FF INIT Initialization 0= Normal Operation 1= Initialization is started [0:0] read-write CCE Configuration Change Enable 0= The CPU has no write access to the protected configuration registers 1= The CPU has write access to the protected configuration registers (while CCCR.INIT = '1') [1:1] read-write ASM Restricted Operation Mode Bit ASM can only be set by the Host when both CCE and INIT are set to '1'. The bit can be reset by the Host at any time. For a description of the Restricted Operation Mode see Section 3.1.5. 0= Normal CAN operation 1= Restricted Operation Mode active [2:2] read-write CSA Clock Stop Acknowledge 0= No clock stop acknowledged 1= M_TTCAN may be set in power down by stopping m_ttcan_hclk and m_ttcan_cclk [3:3] read-write CSR Clock Stop Request, not supported by M_TTCAN use CTL.STOP_REQ at the group level instead. 0= No clock stop is requested 1= Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pending transfer requests have been completed and the CAN bus reached idle. [4:4] read-write MON_ Bus Monitoring Mode Bit MON can only be set by the Host when both CCE and INIT are set to '1'. The bit can be reset by the Host at any time. 0= Bus Monitoring Mode is disabled 1= Bus Monitoring Mode is enabled [5:5] read-write DAR Disable Automatic Retransmission 0= Automatic retransmission of messages not transmitted successfully enabled 1= Automatic retransmission disabled [6:6] read-write TEST Test Mode Enable 0= Normal operation, register TEST holds reset values 1= Test Mode, write access to register TEST enabled [7:7] read-write FDOE FD Operation Enable 0= FD operation disabled 1= FD operation enabled [8:8] read-write BRSE Bit Rate Switch Enable 0= Bit rate switching for transmissions disabled 1= Bit rate switching for transmissions enabled [9:9] read-write PXHD Protocol Exception Handling Disable 0= Protocol exception handling enabled 1= Protocol exception handling disabled [12:12] read-write EFBI Edge Filtering during Bus Integration 0= Edge filtering disabled 1= Two consecutive dominant tq required to detect an edge for hard synchronization [13:13] read-write TXP Transmit Pause If this bit is set, the M_TTCAN pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame (see Section 3.5). 0= Transmit pause disabled 1= Transmit pause enabled [14:14] read-write NISO Non ISO Operation If this bit is set, the M_TTCAN uses the CAN FD frame format as specified by the Bosch CAN FD Specification V1.0. 0= CAN FD frame format according to ISO 11898-1:2015 1= CAN FD frame format according to Bosch CAN FD Specification V1.0 addressing the non-ISO CAN FD [15:15] read-write NBTP Nominal Bit Timing & Prescaler Register 0x1C 32 read-write 0x6000A03 0xFFFFFF7F NTSEG2 Nominal Time segment after sample point 0x01-0x7F Valid values are 1 to 127. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. [6:0] read-write NTSEG1 Nominal Time segment before sample point 0x01-0xFF Valid values are 1 to 255. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. [15:8] read-write NBRP Nominal Bit Rate Prescaler 0x000-0x1FFThe value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 511. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. [24:16] read-write NSJW Nominal (Re)Synchronization Jump Width 0x00-0x7F Valid values are 0 to 127. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. [31:25] read-write TSCC Timestamp Counter Configuration 0x20 32 read-write 0x0 0xF0003 TSS Timestamp Select, should always be set to external timestamp counter 00= Timestamp counter value always 0x0000 01= Timestamp counter value incremented according to TCP 10= External timestamp counter value used 11= Same as '00' [1:0] read-write TCP Timestamp Counter Prescaler (still used for TOCC) 0x0-0xF Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1...16]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. [19:16] read-write TSCV Timestamp Counter Value 0x24 32 read-write 0x0 0xFFFF TSC Timestamp Counter, not used for M_TTCAN The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx). When TSCC.TSS = '01', the Timestamp Counter is incremented in multiples of CAN bit times [1...16] depending on the configuration of TSCC.TCP. A wrap around sets interrupt flag IR.TSW. Write access resets the counter to zero. When TSCC.TSS = '10', TSC reflects the external Timestamp Counter value. A write access has no impact. [15:0] read-write TOCC Timeout Counter Configuration 0x28 32 read-write 0xFFFF0000 0xFFFF0007 ETOC Enable Timeout Counter 0= Timeout Counter disabled 1= Timeout Counter enabled [0:0] read-write TOS Timeout Select When operating in Continuous mode, a write to TOCV presets the counter to the value configured by TOCC.TOP and continues down-counting. When the Timeout Counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by TOCC.TOP. Down-counting is started when the first FIFO element is stored. 00= Continuous operation 01= Timeout controlled by Tx Event FIFO 10= Timeout controlled by Rx FIFO 0 11= Timeout controlled by Rx FIFO 1 [2:1] read-write TOP Timeout Period Start value of the Timeout Counter (down-counter). Configures the Timeout Period. [31:16] read-write TOCV Timeout Counter Value 0x2C 32 read-write 0xFFFF 0xFFFF TOC Timeout Counter The Timeout Counter is decremented in multiples of CAN bit times [1...16] depending on the configuration of TSCC.TCP. When decremented to zero, interrupt flag IR.TOO is set and the Timeout Counter is stopped. Start and reset/restart conditions are configured via TOCC.TOS. [15:0] read-write ECR Error Counter Register 0x40 32 read-only 0x0 0xFFFFFF TEC Transmit Error Counter Actual state of the Transmit Error Counter, values between 0 and 255 [7:0] read-only REC Receive Error Counter Actual state of the Receive Error Counter, values between 0 and 127 [14:8] read-only RP Receive Error Passive 0= The Receive Error Counter is below the error passive level of 128 1= The Receive Error Counter has reached the error passive level of 128 [15:15] read-only CEL CAN Error Logging The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter or the Receive Error Counter to be incremented. It is reset by read access to CEL. The counter stops at 0xFF; the next increment of TEC or REC sets interrupt flag IR.ELO. [23:16] read-only PSR Protocol Status Register 0x44 32 read-only 0x707 0x7F7FFF LEC Last Error Code, Set on Read0 The LEC indicates the type of the last error to occur on the CAN bus. This field will be cleared to '0' when a message has been transferred (reception or transmission) without error. 0= No Error: No error occurred since LEC has been reset by successful reception or transmission. 1= Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. 2= Form Error: A fixed format part of a received frame has the wrong format. 3= AckError: The message transmitted by the M_TTCAN was not acknowledged by another node. 4= Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value '1'), but the monitored bus value was dominant. 5= Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value 0'), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed). 6= CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data. 7= NoChange: Any read access to the Protocol Status Register re-initializes the LEC to '7'. When the LEC shows the value '7', no CAN bus event was detected since the last CPU read access to the Protocol Status Register. [2:0] read-only ACT Activity Monitors the module's CAN communication state. 00= Synchronizing - node is synchronizing on CAN communication 01= Idle - node is neither receiver nor transmitter 10= Receiver - node is operating as receiver 11= Transmitter - node is operating as transmitter [4:3] read-only EP Error Passive 0= The M_CAN is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected 1= The M_CAN is in the Error_Passive state [5:5] read-only EW Warning Status 0= Both error counters are below the Error_Warning limit of 96 1= At least one of error counter has reached the Error_Warning limit of 96 [6:6] read-only BO Bus_Off Status 0= The M_CAN is not Bus_Off 1= The M_CAN is in Bus_Off state [7:7] read-only DLEC Data Phase Last Error Code , Set on Read Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for LEC. This field will be cleared to zero when a CAN FD format frame with its BRS flag set has been transferred (reception or transmission) without error. [10:8] read-only RESI ESI flag of last received CAN FD Message , Reset on Read This bit is set together with RFDF, independent of acceptance filtering. 0= Last received CAN FD message did not have its ESI flag set 1= Last received CAN FD message had its ESI flag set [11:11] read-only RBRS BRS flag of last received CAN FD Message , Reset on Read This bit is set together with RFDF, independent of acceptance filtering. 0= Last received CAN FD message did not have its BRS flag set 1= Last received CAN FD message had its BRS flag set [12:12] read-only RFDF Received a CAN FD Message , Reset on Read This bit is set independent of acceptance filtering. 0= Since this bit was reset by the CPU, no CAN FD message has been received 1= Message in CAN FD format with FDF flag set has been received [13:13] read-only PXE Protocol Exception Event , Reset on Read 0= No protocol exception event occurred since last read access 1= Protocol exception event occurred [14:14] read-only TDCV Transmitter Delay Compensation Value 0x00-0x7F Position of the secondary sample point, defined by the sum of the measured delay from m_can_tx to m_can_rx and TDCR.TDCO. The SSP position is, in the data phase, the number of mtq between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq. [22:16] read-only TDCR Transmitter Delay Compensation Register 0x48 32 read-write 0x0 0x7F7F TDCF Transmitter Delay Compensation Filter Window Length 0x00-0x7F Defines the minimum value for the SSP position, dominant edges on m_ttcan_rx that would result in an earlier SSP position are ignored for transmitter delay measurement. The feature is enabled when TDCF is configured to a value greater than TDCO. Valid values are 0 to 127 mtq [6:0] read-write TDCO Transmitter Delay Compensation Offset 0x00-0x7F Offset value defining the distance between the measured delay from m_ttcan_tx to m_ttcan_rx and the secondary sample point. Valid values are 0 to 127 mtq. [14:8] read-write IR Interrupt Register 0x50 32 read-write 0x0 0x3FFFFFFF RF0N Rx FIFO 0 New Message 0= No new message written to Rx FIFO 0 1= New message written to Rx FIFO 0 [0:0] read-write RF0W Rx FIFO 0 Watermark Reached 0= Rx FIFO 0 fill level below watermark 1= Rx FIFO 0 fill level reached watermark [1:1] read-write RF0F Rx FIFO 0 Full 0= Rx FIFO 0 not full 1= Rx FIFO 0 full [2:2] read-write RF0L_ Rx FIFO 0 Message Lost 0= No Rx FIFO 0 message lost 1= Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero [3:3] read-write RF1N Rx FIFO 1 New Message 0= No new message written to Rx FIFO 1 1= New message written to Rx FIFO 1 [4:4] read-write RF1W Rx FIFO 1 Watermark Reached 0= Rx FIFO 1 fill level below watermark 1= Rx FIFO 1 fill level reached watermark [5:5] read-write RF1F Rx FIFO 1 Full 0= Rx FIFO 1 not full 1= Rx FIFO 1 full [6:6] read-write RF1L_ Rx FIFO 1 Message Lost 0= No Rx FIFO 1 message lost 1= Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero [7:7] read-write HPM High Priority Message 0= No high priority message received 1= High priority message received [8:8] read-write TC Transmission Completed 0= No transmission completed 1= Transmission completed [9:9] read-write TCF Transmission Cancellation Finished 0= No transmission cancellation finished 1= Transmission cancellation finished [10:10] read-write TFE Tx FIFO Empty 0= Tx FIFO non-empty 1= Tx FIFO empty [11:11] read-write TEFN Tx Event FIFO New Entry 0= Tx Event FIFO unchanged 1= Tx Handler wrote Tx Event FIFO element [12:12] read-write TEFW Tx Event FIFO Watermark Reached 0= Tx Event FIFO fill level below watermark 1= Tx Event FIFO fill level reached watermark [13:13] read-write TEFF Tx Event FIFO Full 0= Tx Event FIFO not full 1= Tx Event FIFO full [14:14] read-write TEFL_ Tx Event FIFO Element Lost 0= No Tx Event FIFO element lost 1= Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero [15:15] read-write TSW Timestamp Wraparound 0= No timestamp counter wrap-around 1= Timestamp counter wrapped around [16:16] read-write MRAF Message RAM Access Failure The flag is set, when the Rx Handler - has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or message storage is aborted and the Rx Handler starts processing of the following message. - was not able to write a message to the Message RAM. In this case message storage is aborted. In both cases the FIFO put index is not updated resp. the New Data flag for a dedicated Rx Buffer is not set, a partly stored message is overwritten when the next message is stored to this location. The flag is also set when the Tx Handler was not able to read a message from the Message RAM in time. In this case message transmission is aborted. In case of a Tx Handler access failure the M_TTCAN is switched into Restricted Operation Mode (see Section 3.1.5). To leave Restricted Operation Mode, the Host CPU has to reset CCCR.ASM. 0= No Message RAM access failure occurred 1= Message RAM access failure occurred [17:17] read-write TOO Timeout Occurred 0= No timeout 1= Timeout reached [18:18] read-write DRX Message stored to Dedicated Rx Buffer The flag is set whenever a received message has been stored into a dedicated Rx Buffer. 0= No Rx Buffer updated 1= At least one received message stored into a Rx Buffer [19:19] read-write BEC M_TTCAN reports correctable ECC fault to the generic fault structure, this bit always reads as 0. Bit Error Corrected Message RAM bit error detected and corrected. Controlled by input signal m_ttcan_aeim_berr[0] generated by an optional external parity / ECC logic attached to the Message RAM. 0= No bit error detected when reading from Message RAM 1= Bit error detected and corrected (e.g. ECC) [20:20] read-write BEU Bit Error Uncorrected Message RAM bit error detected, uncorrected. Controlled by input signal m_ttcan_aeim_berr[1] generated by an optional external parity / ECC logic attached to the Message RAM. An uncorrected Message RAM bit error sets CCCR.INIT to '1'. This is done to avoid transmission of corrupted data. 0= No bit error detected when reading from Message RAM 1= Bit error detected, uncorrected (e.g. parity logic) [21:21] read-write ELO Error Logging Overflow 0= CAN Error Logging Counter did not overflow 1= Overflow of CAN Error Logging Counter occurred [22:22] read-write EP_ Error Passive 0= Error_Passive status unchanged 1= Error_Passive status changed [23:23] read-write EW_ Warning Status 0= Error_Warning status unchanged 1= Error_Warning status changed [24:24] read-write BO_ Bus_Off Status 0= Bus_Off status unchanged 1= Bus_Off status changed [25:25] read-write WDI Watchdog Interrupt 0= No Message RAM Watchdog event occurred 1= Message RAM Watchdog event due to missing READY [26:26] read-write PEA Protocol Error in Arbitration Phase (Nominal Bit Time is used) 0= No protocol error in arbitration phase 1= Protocol error in arbitration phase detected (PSR.LEC != 0,7) [27:27] read-write PED Protocol Error in Data Phase (Data Bit Time is used) 0= No protocol error in data phase 1= Protocol error in data phase detected (PSR.DLEC != 0,7) [28:28] read-write ARA N/A [29:29] read-write IE Interrupt Enable 0x54 32 read-write 0x0 0x3FFFFFFF RF0NE Rx FIFO 0 New Message Interrupt Enable [0:0] read-write RF0WE Rx FIFO 0 Watermark Reached Interrupt Enable [1:1] read-write RF0FE Rx FIFO 0 Full Interrupt Enable [2:2] read-write RF0LE Rx FIFO 0 Message Lost Interrupt Enable [3:3] read-write RF1NE Rx FIFO 1 New Message Interrupt Enable [4:4] read-write RF1WE Rx FIFO 1 Watermark Reached Interrupt Enable [5:5] read-write RF1FE Rx FIFO 1 Full Interrupt Enable [6:6] read-write RF1LE Rx FIFO 1 Message Lost Interrupt Enable [7:7] read-write HPME High Priority Message Interrupt Enable [8:8] read-write TCE Transmission Completed Interrupt Enable [9:9] read-write TCFE Transmission Cancellation Finished Interrupt Enable [10:10] read-write TFEE Tx FIFO Empty Interrupt Enable [11:11] read-write TEFNE Tx Event FIDO New Entry Interrupt Enable [12:12] read-write TEFWE Tx Event FIFO Watermark Reached Interrupt Enable [13:13] read-write TEFFE Tx Event FIFO Full Interrupt Enable [14:14] read-write TEFLE Tx Event FIFO Event Lost Interrupt Enable [15:15] read-write TSWE Timestamp Wraparound Interrupt Enable [16:16] read-write MRAFE Message RAM Access Failure Interrupt Enable [17:17] read-write TOOE Timeout Occurred Interrupt Enable [18:18] read-write DRXE Message stored to Dedicated Rx Buffer Interrupt Enable [19:19] read-write BECE Bit Error Corrected Interrupt Enable (not used in M_TTCAN) [20:20] read-write BEUE Bit Error Uncorrected Interrupt Enable [21:21] read-write ELOE Error Logging Overflow Interrupt Enable [22:22] read-write EPE Error Passive Interrupt Enable [23:23] read-write EWE Warning Status Interrupt Enable [24:24] read-write BOE Bus_Off Status Interrupt Enable [25:25] read-write WDIE Watchdog Interrupt Enable [26:26] read-write PEAE Protocol Error in Arbitration Phase Enable [27:27] read-write PEDE Protocol Error in Data Phase Enable [28:28] read-write ARAE N/A [29:29] read-write ILS Interrupt Line Select 0x58 32 read-write 0x0 0x3FFFFFFF RF0NL Rx FIFO 0 New Message Interrupt Line [0:0] read-write RF0WL Rx FIFO 0 Watermark Reached Interrupt Line [1:1] read-write RF0FL Rx FIFO 0 Full Interrupt Line [2:2] read-write RF0LL Rx FIFO 0 Message Lost Interrupt Line [3:3] read-write RF1NL Rx FIFO 1 New Message Interrupt Line [4:4] read-write RF1WL Rx FIFO 1 Watermark Reached Interrupt Line [5:5] read-write RF1FL Rx FIFO 1 Full Interrupt Line [6:6] read-write RF1LL Rx FIFO 1 Message Lost Interrupt Line [7:7] read-write HPML High Priority Message Interrupt Line [8:8] read-write TCL Transmission Completed Interrupt Line [9:9] read-write TCFL Transmission Cancellation Finished Interrupt Line [10:10] read-write TFEL Tx FIFO Empty Interrupt Line [11:11] read-write TEFNL Tx Event FIFO New Entry Interrupt Line [12:12] read-write TEFWL Tx Event FIFO Watermark Reached Interrupt Line [13:13] read-write TEFFL Tx Event FIFO Full Interrupt Line [14:14] read-write TEFLL Tx Event FIFO Event Lost Interrupt Line [15:15] read-write TSWL Timestamp Wraparound Interrupt Line [16:16] read-write MRAFL Message RAM Access Failure Interrupt Line [17:17] read-write TOOL Timeout Occurred Interrupt Line [18:18] read-write DRXL Message stored to Dedicated Rx Buffer Interrupt Line [19:19] read-write BECL Bit Error Corrected Interrupt Line (not used in M_TTCAN) [20:20] read-write BEUL Bit Error Uncorrected Interrupt Line [21:21] read-write ELOL Error Logging Overflow Interrupt Line [22:22] read-write EPL Error Passive Interrupt Line [23:23] read-write EWL Warning Status Interrupt Line [24:24] read-write BOL Bus_Off Status Interrupt Line [25:25] read-write WDIL Watchdog Interrupt Line [26:26] read-write PEAL Protocol Error in Arbitration Phase Line [27:27] read-write PEDL Protocol Error in Data Phase Line [28:28] read-write ARAL N/A [29:29] read-write ILE Interrupt Line Enable 0x5C 32 read-write 0x0 0x3 EINT0 Enable Interrupt Line 0 0= Interrupt line m_ttcan_int0 disabled 1= Interrupt line m_ttcan_int0 enabled [0:0] read-write EINT1 Enable Interrupt Line 1 0= Interrupt line m_ttcan_int1 disabled 1= Interrupt line m_ttcan_int1 enabled [1:1] read-write GFC Global Filter Configuration 0x80 32 read-write 0x0 0x3F RRFE Reject Remote Frames Extended 0= Filter remote frames with 29-bit extended IDs 1= Reject all remote frames with 29-bit extended IDs [0:0] read-write RRFS Reject Remote Frames Standard 0= Filter remote frames with 11-bit standard IDs 1= Reject all remote frames with 11-bit standard IDs [1:1] read-write ANFE Accept Non-matching Frames Extended Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. 00= Accept in Rx FIFO 0 01= Accept in Rx FIFO 1 10= Reject 11= Reject [3:2] read-write ANFS Accept Non-matching Frames Standard Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. 00= Accept in Rx FIFO 0 01= Accept in Rx FIFO 1 10= Reject 11= Reject [5:4] read-write SIDFC Standard ID Filter Configuration 0x84 32 read-write 0x0 0xFFFFFC FLSSA Filter List Standard Start Address Start address of standard Message ID filter list (32-bit word address, see Figure 2). [15:2] read-write LSS List Size Standard 0= No standard Message ID filter 1-128= Number of standard Message ID filter elements 128= Values greater than 128 are interpreted as 128 [23:16] read-write XIDFC Extended ID Filter Configuration 0x88 32 read-write 0x0 0x7FFFFC FLESA Filter List Extended Start Address Start address of extended Message ID filter list (32-bit word address, see Figure 2). [15:2] read-write LSE List Size Extended 0= No extended Message ID filter 1-64= Number of extended Message ID filter elements 64= Values greater than 64 are interpreted as 64 [22:16] read-write XIDAM Extended ID AND Mask 0x90 32 read-write 0x1FFFFFFF 0x1FFFFFFF EIDM Extended ID Mask For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not active. [28:0] read-write HPMS High Priority Message Status 0x94 32 read-only 0x0 0xFFFF BIDX Buffer Index Index of Rx FIFO element to which the message was stored. Only valid when MSI[1] = '1'. [5:0] read-only MSI Message Storage Indicator 00= No FIFO selected 01= FIFO message lost 10= Message stored in FIFO 0 11= Message stored in FIFO 1 [7:6] read-only FIDX Filter Index Index of matching filter element. Range is 0 to SIDFC.LSS - 1 resp. XIDFC.LSE - 1. [14:8] read-only FLST Filter List Indicates the filter list of the matching filter element. 0= Standard Filter List 1= Extended Filter List [15:15] read-only NDAT1 New Data 1 0x98 32 read-write 0x0 0xFFFFFFFF ND New Data The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host clears them. A flag is cleared by writing a '1' to the corresponding bit position. Writing a '0' has no effect. A hard reset will clear the register. 0= Rx Buffer not updated 1= Rx Buffer updated from new message [31:0] read-write NDAT2 New Data 2 0x9C 32 read-write 0x0 0xFFFFFFFF ND New Data The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host clears them. A flag is cleared by writing a '1' to the corresponding bit position. Writing a '0' has no effect. A hard reset will clear the register. 0= Rx Buffer not updated 1= Rx Buffer updated from new message [31:0] read-write RXF0C Rx FIFO 0 Configuration 0xA0 32 read-write 0x0 0xFF7FFFFC F0SA Rx FIFO 0 Start Address Start address of Rx FIFO 0 in Message RAM (32-bit word address, see Figure 2). [15:2] read-write F0S Rx FIFO 0 Size 0= No Rx FIFO 0 1-64= Number of Rx FIFO 0 elements 64= Values greater than 64 are interpreted as 64 The Rx FIFO 0 elements are indexed from 0 to F0S-1 [22:16] read-write F0WM Rx FIFO 0 Watermark 0= Watermark interrupt disabled 1-64= Level for Rx FIFO 0 watermark interrupt (IR.RF0W) 64= Watermark interrupt disabled [30:24] read-write F0OM FIFO 0 Operation Mode FIFO 0 can be operated in blocking or in overwrite mode (see Section 3.4.2). 0= FIFO 0 blocking mode 1= FIFO 0 overwrite mode [31:31] read-write RXF0S Rx FIFO 0 Status 0xA4 32 read-only 0x0 0x33F3F7F F0FL Rx FIFO 0 Fill Level Number of elements stored in Rx FIFO 0, range 0 to 64. [6:0] read-only F0GI Rx FIFO 0 Get Index Rx FIFO 0 read index pointer, range 0 to 63. This field is updated by the software writing to RxF0A.F0AI [13:8] read-only F0PI Rx FIFO 0 Put Index Rx FIFO 0 write index pointer, range 0 to 63. [21:16] read-only F0F Rx FIFO 0 Full 0= Rx FIFO 0 not full 1= Rx FIFO 0 full [24:24] read-only RF0L Rx FIFO 0 Message Lost This bit is a copy of interrupt flag IR.RF0L. When IR.RF0L is reset, this bit is also reset. 0= No Rx FIFO 0 message lost 1= Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero [25:25] read-only RXF0A Rx FIFO 0 Acknowledge 0xA8 32 read-write 0x0 0x3F F0AI Rx FIFO 0 Acknowledge Index After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI. This will set the Rx FIFO 0 Get Index RXF0S.F0GI to F0AI + 1 and update the FIFO 0 Fill Level RXF0S.F0FL. [5:0] read-write RXBC Rx Buffer Configuration 0xAC 32 read-write 0x0 0xFFFC RBSA Rx Buffer Start Address Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address). Also used to reference debug messages A,B,C. [15:2] read-write RXF1C Rx FIFO 1 Configuration 0xB0 32 read-write 0x0 0xFF7FFFFC F1SA Rx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM (32-bit word address, see Figure 2). [15:2] read-write F1S Rx FIFO 1 Size 0= No Rx FIFO 1 1-64= Number of Rx FIFO 1 elements 64= Values greater than 64 are interpreted as 64 The Rx FIFO 1 elements are indexed from 0 to F1S - 1 [22:16] read-write F1WM Rx FIFO 1 Watermark 0= Watermark interrupt disabled 1-64= Level for Rx FIFO 1 watermark interrupt (IR.RF1W) 64= Watermark interrupt disabled [30:24] read-write F1OM FIFO 1 Operation Mode FIFO 1 can be operated in blocking or in overwrite mode (see Section 3.4.2). 0= FIFO 1 blocking mode 1= FIFO 1 overwrite mode [31:31] read-write RXF1S Rx FIFO 1 Status 0xB4 32 read-only 0x0 0xC33F3F7F F1FL Rx FIFO 1 Fill Level Number of elements stored in Rx FIFO 1, range 0 to 64. [6:0] read-only F1GI Rx FIFO 1 Get Index Rx FIFO 1 read index pointer, range 0 to 63. This field is updated by the software writing to RxF1A.FAI [13:8] read-only F1PI Rx FIFO 1 Put Index Rx FIFO 1 write index pointer, range 0 to 63. [21:16] read-only F1F Rx FIFO 1 Full 0= Rx FIFO 1 not full 1= Rx FIFO 1 full [24:24] read-only RF1L Rx FIFO 1 Message Lost This bit is a copy of interrupt flag IR.RF1L. When IR.RF1L is reset, this bit is also reset. 0= No Rx FIFO 1 message lost 1= Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero [25:25] read-only DMS Debug Message Status 00= Idle state, wait for reception of debug messages, DMA request is cleared 01= Debug message A received 10= Debug messages A, B received 11= Debug messages A, B, C received, DMA request is set [31:30] read-only RXF1A Rx FIFO 1 Acknowledge 0xB8 32 read-write 0x0 0x3F F1AI Rx FIFO 1 Acknowledge Index After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI. This will set the Rx FIFO 1 Get Index RXF1S.F1GI to F1AI + 1 and update the FIFO 1 Fill Level RXF1S.F1FL. [5:0] read-write RXESC Rx Buffer / FIFO Element Size Configuration 0xBC 32 read-write 0x0 0x777 F0DS Rx FIFO 0 Data Field Size 000= 8 byte data field 001= 12 byte data field 010= 16 byte data field 011= 20 byte data field 100= 24 byte data field 101= 32 byte data field 110= 48 byte data field 111= 64 byte data field [2:0] read-write F1DS Rx FIFO 1 Data Field Size 000= 8 byte data field 001= 12 byte data field 010= 16 byte data field 011= 20 byte data field 100= 24 byte data field 101= 32 byte data field 110= 48 byte data field 111= 64 byte data field [6:4] read-write RBDS Rx Buffer Data Field Size 000= 8 byte data field 001= 12 byte data field 010= 16 byte data field 011= 20 byte data field 100= 24 byte data field 101= 32 byte data field 110= 48 byte data field 111= 64 byte data field [10:8] read-write TXBC Tx Buffer Configuration 0xC0 32 read-write 0x0 0x7F3FFFFC TBSA Tx Buffers Start Address Start address of Tx Buffers section in Message RAM (32-bit word address, see Figure 2). [15:2] read-write NDTB Number of Dedicated Transmit Buffers 0= No Dedicated Tx Buffers 1-32= Number of Dedicated Tx Buffers 32= Values greater than 32 are interpreted as 32 [21:16] read-write TFQS Transmit FIFO/Queue Size 0= No Tx FIFO/Queue 1-32= Number of Tx Buffers used for Tx FIFO/Queue 32= Values greater than 32 are interpreted as 32 [29:24] read-write TFQM Tx FIFO/Queue Mode 0= Tx FIFO operation 1= Tx Queue operation [30:30] read-write TXFQS Tx FIFO/Queue Status 0xC4 32 read-only 0x0 0x3F1F3F TFFL Tx FIFO Free Level Number of consecutive free Tx FIFO elements starting from TFGI, range 0 to 32. Read as zero when Tx Queue operation is configured (TXBC.TFQM = '1') [5:0] read-only TFGI Tx FIFO Get Index Tx FIFO read index pointer, range 0 to 31. Read as zero when Tx Queue operation is configured TXBC.TFQM = '1'). [12:8] read-only TFQPI Tx FIFO/Queue Put Index Tx FIFO/Queue write index pointer, range 0 to 31. [20:16] read-only TFQF Tx FIFO/Queue Full 0= Tx FIFO/Queue not full 1= Tx FIFO/Queue full [21:21] read-only TXESC Tx Buffer Element Size Configuration 0xC8 32 read-write 0x0 0x7 TBDS Tx Buffer Data Field Size 000= 8 byte data field 001= 12 byte data field 010= 16 byte data field 011= 20 byte data field 100= 24 byte data field 101= 32 byte data field 110= 48 byte data field 111= 64 byte data field [2:0] read-write TXBRP Tx Buffer Request Pending 0xCC 32 read-only 0x0 0xFFFFFFFF TRP Transmission Request Pending Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via register TXBAR. The bits are reset after a requested transmission has completed or has been cancelled via register TXBCR. TXBRP bits are set only for those Tx Buffers configured via TXBC. After a TXBRP bit has been set, a Tx scan (see Section 3.5, Tx Handling) is started to check for the pending Tx request with the highest priority (Tx Buffer with lowest Message ID). A cancellation request resets the corresponding transmission request pending bit of register TXBRP. In case a transmission has already been started when a cancellation is requested, this is done at the end of the transmission, regardless whether the transmission was successful or not. The cancellation request bits are reset directly after the corresponding TXBRP bit has been reset. After a cancellation has been requested, a finished cancellation is signaled via TXBCF after successful transmission together with the corresponding TXBTO bit when the transmission has not yet been started at the point of cancellation when the transmission has been aborted due to lost arbitration when an error occurred during frame transmission In DAR mode all transmissions are automatically cancelled if they are not successful. The corresponding TXBCF bit is set for all unsuccessful transmissions. 0= No transmission request pending 1= Transmission request pending [31:0] read-only TXBAR Tx Buffer Add Request 0xD0 32 read-write 0x0 0xFFFFFFFF AR Add Request Each Tx Buffer has its own Add Request bit. Writing a '1' will set the corresponding Add Request bit; writing a '0' has no impact. This enables the Host to set transmission requests for multiple Tx Buffers with one write to TXBAR. TXBAR bits are set only for those Tx Buffers configured via TXBC. When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan process has completed. 0= No transmission request added 1= Transmission requested added [31:0] read-write TXBCR Tx Buffer Cancellation Request 0xD4 32 read-write 0x0 0xFFFFFFFF CR Cancellation Request Each Tx Buffer has its own Cancellation Request bit. Writing a '1' will set the corresponding Cancellation Request bit; writing a '0' has no impact. This enables the Host to set cancellation requests for multiple Tx Buffers with one write to TXBCR. TXBCR bits are set only for those Tx Buffers configured via TXBC. The bits remain set until the corresponding bit of TXBRP is reset. 0= No cancellation pending 1= Cancellation pending [31:0] read-write TXBTO Tx Buffer Transmission Occurred 0xD8 32 read-only 0x0 0xFFFFFFFF TO Transmission Occurred Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission is requested by writing a '1' to the corresponding bit of register TXBAR. 0= No transmission occurred 1= Transmission occurred [31:0] read-only TXBCF Tx Buffer Cancellation Finished 0xDC 32 read-only 0x0 0xFFFFFFFF CF Cancellation Finished Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding TXBRP bit is cleared after a cancellation was requested via TXBCR. In case the corresponding TXBRP bit was not set at the point of cancellation, CF is set immediately. The bits are reset when a new transmission is requested by writing a '1' to the corresponding bit of register TXBAR. 0= No transmit buffer cancellation 1= Transmit buffer cancellation finished [31:0] read-only TXBTIE Tx Buffer Transmission Interrupt Enable 0xE0 32 read-write 0x0 0xFFFFFFFF TIE Transmission Interrupt Enable Each Tx Buffer has its own Transmission Interrupt Enable bit. 0= Transmission interrupt disabled 1= Transmission interrupt enable [31:0] read-write TXBCIE Tx Buffer Cancellation Finished Interrupt Enable 0xE4 32 read-write 0x0 0xFFFFFFFF CFIE Cancellation Finished Interrupt Enable Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0= Cancellation finished interrupt disabled 1= Cancellation finished interrupt enabled [31:0] read-write TXEFC Tx Event FIFO Configuration 0xF0 32 read-write 0x0 0x3F3FFFFC EFSA Event FIFO Start Address Start address of Tx Event FIFO in Message RAM (32-bit word address, see Figure 2). [15:2] read-write EFS Event FIFO Size 0= Tx Event FIFO disabled 1-32= Number of Tx Event FIFO elements 32= Values greater than 32 are interpreted as 32 The Tx Event FIFO elements are indexed from 0 to EFS-1 [21:16] read-write EFWM Event FIFO Watermark 0= Watermark interrupt disabled 1-32= Level for Tx Event FIFO watermark interrupt (IR.TEFW) 32= Watermark interrupt disabled [29:24] read-write TXEFS Tx Event FIFO Status 0xF4 32 read-only 0x0 0x31F1F3F EFFL Event FIFO Fill Level Number of elements stored in Tx Event FIFO, range 0 to 32. [5:0] read-only EFGI Event FIFO Get Index Tx Event FIFO read index pointer, range 0 to 31. [12:8] read-only EFPI Event FIFO Put Index Tx Event FIFO write index pointer, range 0 to 31. [20:16] read-only EFF Event FIFO Full 0= Tx Event FIFO not full 1= Tx Event FIFO full [24:24] read-only TEFL Tx Event FIFO Element Lost This bit is a copy of interrupt flag IR.TEFL. When IR.TEFL is reset, this bit is also reset. 0= No Tx Event FIFO element lost 1= Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero. [25:25] read-only TXEFA Tx Event FIFO Acknowledge 0xF8 32 read-write 0x0 0x1F EFAI Event FIFO Acknowledge Index After the Host has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to EFAI. This will set the Tx Event FIFO Get Index TXEFS.EFGI to EFAI + 1 and update the Event FIFO Fill Level TXEFS.EFFL. [4:0] read-write TTTMC TT Trigger Memory Configuration 0x100 32 read-write 0x0 0x7FFFFC TMSA Trigger Memory Start Address Start address of Trigger Memory in Message RAM (32-bit word address, see Figure 2). [15:2] read-write TME Trigger Memory Elements 0= No Trigger Memory 1-64= Number of Trigger Memory elements 64= Values greater than 64 are interpreted as 64 [22:16] read-write TTRMC TT Reference Message Configuration 0x104 32 read-write 0x0 0xDFFFFFFF RID Reference Identifier Identifier transmitted with reference message and used for reference message filtering. Standard or extended reference identifier depending on bit XTD. A standard identifier has to be written to ID[28:18]. [28:0] read-write XTD Extended Identifier 0= 11-bit standard identifier 1= 29-bit extended identifier [30:30] read-write RMPS Reference Message Payload Select Ignored in case of time slaves. 0= Reference message has no additional payload 1= The following elements are taken from Tx Buffer 0: Message Marker MM, Event FIFO Control EFC, Data Length Code DLC, Data Bytes DB Level 1: bytes 2-8, Level 0,2: bytes 5-8) [31:31] read-write TTOCF TT Operation Configuration 0x108 32 read-write 0x10000 0x7FFFFFB OM Operation Mode 00= Event-driven CAN communication, default 01= TTCAN level 1 10= TTCAN level 2 11= TTCAN level 0 [1:0] read-write GEN Gap Enable 0= Strictly time-triggered operation 1= External event-synchronized time-triggered operation [3:3] read-write TM Time Master 0= Time Master function disabled 1= Potential Time Master [4:4] read-write LDSDL LD of Synchronization Deviation Limit The Synchronization Deviation Limit SDL is configured by its dual logarithm LDSDL with SDL = 2(LDSDL + 5). It should not exceed the clock tolerance given by the CAN bit timing configuration. 0x0-7 LD of Synchronization Deviation Limit (SDL <= 32...4096) [7:5] read-write IRTO Initial Reference Trigger Offset 0x00-7F Positive offset, range from 0 to 127 [14:8] read-write EECS Enable External Clock Synchronization If enabled, TUR configuration (TURCF.NCL only) may be updated during TTCAN operation. 0= External clock synchronization in TTCAN Level 0,2 disabled 1= External clock synchronization in TTCAN Level 0,2 enabled [15:15] read-write AWL Application Watchdog Limit The application watchdog can be disabled by programming AWL to 0x00. 0x00-FF Maximum time after which the application has to serve the application watchdog. The application watchdog is incremented once each 256 NTUs. [23:16] read-write EGTF Enable Global Time Filtering 0= Global time filtering in TTCAN Level 0,2 is disabled 1= Global time filtering in TTCAN Level 0,2 is enabled [24:24] read-write ECC Enable Clock Calibration 0= Automatic clock calibration in TTCAN Level 0,2 is disabled 1= Automatic clock calibration in TTCAN Level 0,2 is enabled [25:25] read-write EVTP Event Trigger Polarity 0= Rising edge trigger 1= Falling edge trigger [26:26] read-write TTMLM TT Matrix Limits 0x10C 32 read-write 0x0 0xFFF0FFF CCM N/A [5:0] read-write CSS N/A [7:6] read-write TXEW Tx Enable Window 0x0-F Length of Tx enable window, 1-16 NTU cycles [11:8] read-write ENTT Expected Number of Tx Triggers 0x000-FFF Expected number of Tx Triggers in one Matrix Cycle [27:16] read-write TURCF TUR Configuration 0x110 32 read-write 0x10000000 0xBFFFFFFF NCL Numerator Configuration Low Write access to the TUR Numerator Configuration Low is only possible during configuration with TURCF.ELT = '0' or if TTOCF.EECS (external clock synchronization enabled) is set. When a new value for NCL is written outside TT Configuration Mode, the new value takes effect when TTOST.WECS is cleared to '0'. NCL is locked TTOST.WECS is '1'. 0x0000-FFFF Numerator Configuration Low [15:0] read-write DC Denominator Configuration 0x0000 Illegal value 0x0001-3FFF Denominator Configuration [29:16] read-write ELT Enable Local Time 0= Local time is stopped, default 1= Local time is enabled [31:31] read-write TTOCN TT Operation Control 0x114 32 read-write 0x0 0xBFFF SGT Set Global time Writing a '1' to SGT sets TTOST.WGDT if the node is the actual Time Master. SGT is reset after one Host clock period. The global time preset takes effect when the node transmits the next reference message with the Master_Ref_Mark modified by the preset value written to TTGTP. [0:0] read-write ECS External Clock Synchronization Writing a '1' to ECS sets TTOST.WECS if the node is the actual Time Master. ECS is reset after one Host clock period. The external clock synchronization takes effect at the start of the next basic cycle. [1:1] read-write SWP Stop Watch Polarity 0= Rising edge trigger 1= Falling edge trigger [2:2] read-write SWS Stop Watch Source 00= Stop Watch disabled 01= Actual value of cycle time is copied to TTCPT.SWV 10= Actual value of local time is copied to TTCPT.SWV 11= Actual value of global time is copied to TTCPT.SWV [4:3] read-write RTIE Register Time Mark Interrupt Pulse Enable Register time mark interrupts are configured by register TTTMK. A register time mark interrupt pulse with the length of one NTU is generated when the time referenced by TTOCN.TMC (cycle, local, or global) equals TTTMK.TM, independent of the synchronization state. 0= Register Time Mark Interrupt output m_ttcan_rtp disabled 1= Register Time Mark Interrupt output m_ttcan_rtp enabled [5:5] read-write TMC Register Time Mark Compare 00= No Register Time Mark Interrupt generated 01= Register Time Mark Interrupt if Time Mark = cycle time 10= Register Time Mark Interrupt if Time Mark = local time 11= Register Time Mark Interrupt if Time Mark = global time [7:6] read-write TTIE Trigger Time Mark Interrupt Pulse Enable External time mark events are configured by trigger memory element TMEX (see Section 2.4.7). A trigger time mark interrupt pulse is generated when the trigger memory element becomes active, and the M_TTCAN is in synchronization state In_Schedule or In_Gap. 0= Trigger Time Mark Interrupt output m_ttcan_tmp disabled 1= Trigger Time Mark Interrupt output m_ttcan_tmp enabled [8:8] read-write GCS Gap Control Select 0= Gap control independent from m_ttcan_evt 1= Gap control by input pin m_ttcan_evt [9:9] read-write FGP Finish Gap Set by the CPU, reset by each reference message 0= No reference message requested 1= Application requested start of reference message [10:10] read-write TMG Time Mark Gap 0= Reset by each reference message 1= Next reference message started when Register Time Mark interrupt TTIR.RTMI is activated [11:11] read-write NIG Next is Gap This bit can only be set when the M_TTCAN is the actual Time Master and when it is configured for external event-synchronized time-triggered operation (TTOCF.GEN = '1') 0= No action, reset by reception of any reference message 1= Transmit next reference message with Next_is_Gap = '1' [12:12] read-write ESCN External Synchronization Control If enabled the M_TTCAN synchronizes its cycle time phase to an external event signaled by a rising edge at pin m_ttcan_evt (see Section 4.11). 0= External synchronization disabled 1= External synchronization enabled [13:13] read-write LCKC TT Operation Control Register Locked Set by a write access to register TTOCN. Reset when the updated configuration has been synchronized into the CAN clock domain. 0= Write access to TTOCN enabled 1= Write access to TTOCN locked [15:15] read-only TTGTP TT Global Time Preset 0x118 32 read-write 0x0 0xFFFFFFFF TP N/A [15:0] read-write CTP Cycle Time Target Phase CTP is write-protected while TTOCN.ESCN or TTOST.SPL are set (see Section 4.11). 0x0000-FFFF Defines target value of cycle time when a rising edge of m_ttcan_evt is expected [31:16] read-write TTTMK TT Time Mark 0x11C 32 read-write 0x0 0x807FFFFF TM_ Time Mark 0x0000-FFFF Time Mark [15:0] read-write TICC Time Mark Cycle Code Cycle count for which the time mark is valid. 0b000000x valid for all cycles 0b000001c valid every second cycle at cycle count mod2 = c 0b00001cc valid every fourth cycle at cycle count mod4 = cc 0b0001ccc valid every eighth cycle at cycle count mod8 = ccc 0b001cccc valid every sixteenth cycle at cycle count mod16 = cccc 0b01ccccc valid every thirty-second cycle at cycle count mod32 = ccccc 0b1cccccc valid every sixty-fourth cycle at cycle count mod64 = cccccc [22:16] read-write LCKM TT Time Mark Register Locked Always set by a write access to registers TTOCN. Set by write access to register TTTMK when TTOCN.TMC != '00'. Reset when the registers have been synchronized into the CAN clock domain. 0= Write access to TTTMK enabled 1= Write access to TTTMK locked [31:31] read-only TTIR TT Interrupt Register 0x120 32 read-write 0x0 0x7FFFF SBC Start of Basic Cycle 0= No Basic Cycle started since bit has been reset 1= Basic Cycle started [0:0] read-write SMC Start of Matrix Cycle 0= No Matrix Cycle started since bit has been reset 1= Matrix Cycle started [1:1] read-write CSM_ Change of Synchronization Mode 0= No change in master to slave relation or schedule synchronization 1= Master to slave relation or schedule synchronization changed, also set when TTOST.SPL is reset [2:2] read-write SOG Start of Gap 0= No reference message seen with Next_is_Gap bit set 1= Reference message with Next_is_Gap bit set becomes valid [3:3] read-write RTMI Register Time Mark Interrupt Set when time referenced by TTOCN.TMC (cycle, local, or global) equals TTTMK.TM, independent of the synchronization state. 0= Time mark not reached 1= Time mark reached [4:4] read-write TTMI Trigger Time Mark Event Internal Internal time mark events are configured by trigger memory element TMIN (see Section 2.4.7). Set when the trigger memory element becomes active, and the M_TTCAN is in synchronization state In_Gap or In_Schedule. 0= Time mark not reached 1= Time mark reached (Level 0: cycle time TTOCF.IRTO * 0x200) [5:5] read-write SWE Stop Watch Event 0= No rising/falling edge at stop watch trigger pin m_ttcan_swt detected 1= Rising/falling edge at stop watch trigger pin m_ttcan_swt detected [6:6] read-write GTW Global Time Wrap 0= No global time wrap occurred 1= Global time wrap from 0xFFFF to 0x0000 occurred [7:7] read-write GTD Global Time Discontinuity 0= No discontinuity of global time 1= Discontinuity of global time [8:8] read-write GTE Global Time Error Synchronization deviation SD exceeds limit specified by TTOCF.LDSDL, TTCAN Level 0,2 only. 0= Synchronization deviation within limit 1= Synchronization deviation exceeded limit [9:9] read-write TXU Tx Count Underflow 0= Number of Tx Trigger as expected 1= Less Tx trigger than expected in one matrix cycle [10:10] read-write TXO Tx Count Overflow 0= Number of Tx Trigger as expected 1= More Tx trigger than expected in one matrix cycle [11:11] read-write SE1 Scheduling Error 1 0= No scheduling error 1 1= Scheduling error 1 occurred [12:12] read-write SE2 Scheduling Error 2 0= No scheduling error 2 1= Scheduling error 2 occurred [13:13] read-write ELC Error Level Changed Not set when error level changed during initialization. 0= No change in error level 1= Error level changed [14:14] read-write IWT Initialization Watch Trigger The initialization is restarted by resetting IWT. 0= No missing reference message during system startup 1= No system startup due to missing reference message [15:15] read-write WT Watch Trigger 0= No missing reference message 1= Missing reference message (Level 0: cycle time 0xFF00) [16:16] read-write AW Application Watchdog 0= Application watchdog served in time 1= Application watchdog not served in time [17:17] read-write CER Configuration Error Trigger out of order. 0= No error found in trigger list 1= Error found in trigger list [18:18] read-write TTIE TT Interrupt Enable 0x124 32 read-write 0x0 0x7FFFF SBCE Start of Basic Cycle Interrupt Enable [0:0] read-write SMCE Start of Matrix Cycle Interrupt Enable [1:1] read-write CSME Change of Synchronization Mode Interrupt Enable [2:2] read-write SOGE Start of Gap Interrupt Enable [3:3] read-write RTMIE Register Time Mark Interrupt Enable [4:4] read-write TTMIE Trigger Time Mark Event Internal Enable [5:5] read-write SWEE Stop Watch Event Interrupt Enable [6:6] read-write GTWE Global Time Wrap Interrupt Enable [7:7] read-write GTDE Global Time Discontinuity Interrupt Enable [8:8] read-write GTEE Global Time Error Interrupt Enable [9:9] read-write TXUE Tx Count Underflow Interrupt Enable [10:10] read-write TXOE Tx Count Overflow Interrupt Enable [11:11] read-write SE1E Scheduling Error 1 Interrupt Enable [12:12] read-write SE2E Scheduling Error 2 Interrupt Enable [13:13] read-write ELCE Change Error Level Interrupt Enable [14:14] read-write IWTE Initialization Watch Trigger Interrupt Enable [15:15] read-write WTE Watch Trigger Interrupt Enable [16:16] read-write AWE_ Application Watchdog Interrupt Enable [17:17] read-write CERE Configuration Error Interrupt Enable [18:18] read-write TTILS TT Interrupt Line Select 0x128 32 read-write 0x0 0x7FFFF SBCL Start of Basic Cycle Interrupt Line [0:0] read-write SMCL Start of Matrix Cycle Interrupt Line [1:1] read-write CSML Change of Synchronization Mode Interrupt Line [2:2] read-write SOGL Start of Gap Interrupt Line [3:3] read-write RTMIL Register Time Mark Interrupt Line [4:4] read-write TTMIL Trigger Time Mark Event Internal Line [5:5] read-write SWEL Stop Watch Event Interrupt Line [6:6] read-write GTWL Global Time Wrap Interrupt Line [7:7] read-write GTDL Global Time Discontinuity Interrupt Line [8:8] read-write GTEL Global Time Error Interrupt Line [9:9] read-write TXUL Tx Count Underflow Interrupt Line [10:10] read-write TXOL Tx Count Overflow Interrupt Line [11:11] read-write SE1L Scheduling Error 1 Interrupt Line [12:12] read-write SE2L Scheduling Error 2 Interrupt Line [13:13] read-write ELCL Change Error Level Interrupt Line [14:14] read-write IWTL Initialization Watch Trigger Interrupt Line [15:15] read-write WTL Watch Trigger Interrupt Line [16:16] read-write AWL_ Application Watchdog Interrupt Line [17:17] read-write CERL Configuration Error Interrupt Line [18:18] read-write TTOST TT Operation Status 0x12C 32 read-only 0x0 0xFFC0FFFF EL Error Level 00= Severity 0 - No Error 01= Severity 1 - Warning 10= Severity 2 - Error 11= Severity 3 - Severe Error [1:0] read-only MS Master State 00= Master_Off, no master properties relevant 01= Operating as Time Slave 10= Operating as Backup Time Master 11= Operating as current Time Master [3:2] read-only SYS Synchronization State 00= Out of Synchronization 01= Synchronizing to TTCAN communication 10= Schedule suspended by Gap (In_Gap) 11= Synchronized to schedule (In_Schedule) [5:4] read-only QGTP Quality of Global Time Phase Only relevant in TTCAN Level 0 and Level 2, otherwise fixed to '0'. 0= Global time not valid 1= Global time in phase with Time Master [6:6] read-only QCS Quality of Clock Speed Only relevant in TTCAN Level 0 and Level 2, otherwise fixed to '1'. 0= Local clock speed not synchronized to Time Master clock speed 1= Synchronization Deviation <= SDL [7:7] read-only RTO Reference Trigger Offset The Reference Trigger Offset value is a signed integer with a range from -127 (0x81) to 127 (0x7F). There is no notification when the lower limit of -127 is reached. In case the M_TTCAN becomes Time Master (MS[1:0] = '11'), the reset of RTO is delayed due to synchronization between Host and CAN clock domain. For time slaves the value configured by TTOCF.IRTO is read. 0x00-FF Actual Reference Trigger offset value [15:8] read-only WGTD Wait for Global Time Discontinuity 0= No global time preset pending 1= Node waits for the global time preset to take effect. The bit is reset when the node has transmitted a reference message with Disc_Bit = '1' or after it received a reference message. [22:22] read-only GFI Gap Finished Indicator Set when the CPU writes TTOCN.FGP, or by a time mark interrupt if TMG = '1', or via input pin m_ttcan_evt if TTOCN.GCS = '1'. Not set by Ref_Trigger_Gap or when Gap is finished by another node sending a reference message. 0= Reset at the end of each reference message 1= Gap finished by M_TTCAN [23:23] read-only TMP Time Master Priority 0x0-7 Priority of actual Time Master [26:24] read-only GSI Gap Started Indicator 0= No Gap in schedule, reset by each reference message and for all time slaves 1= Gap time after Basic Cycle has started [27:27] read-only WFE Wait for Event 0= No Gap announced, reset by a reference message with Next_is_Gap = '0' 1= Reference message with Next_is_Gap = '1' received [28:28] read-only AWE Application Watchdog Event The application watchdog is served by reading TTOST. When the watchdog is not served in time, bit AWE is set, all TTCAN communication is stopped, and the M_TTCAN is set into Bus Monitoring Mode. 0= Application Watchdog served in time 1= Failed to serve Application Watchdog in time [29:29] read-only WECS Wait for External Clock Synchronization 0= No external clock synchronization pending 1= Node waits for external clock synchronization to take effect. The bit is reset at the start of the next basic cycle. [30:30] read-only SPL Schedule Phase Lock The bit is valid only when external synchronization is enabled (TTOCN.ESCN = '1'). In this case it signals that the difference between cycle time configured by TTGTP.CTP and the cycle time at the rising edge at pin m_ttcan_evt is less or equal 9 NTU (see Section 4.11). 0= Phase outside range 1= Phase inside range [31:31] read-only TURNA TUR Numerator Actual 0x130 32 read-only 0x10000 0x3FFFF NAV N/A [17:0] read-only TTLGT TT Local & Global Time 0x134 32 read-only 0x0 0xFFFFFFFF LT Local Time Non-fractional part of local time, incremented once each local NTU (see Section 4.5). 0x0000-FFFF Local time value of TTCAN node [15:0] read-only GT Global Time Non-fractional part of the sum of the node's local time and its local offset (see Section 4.5). 0x0000-FFFF Global time value of TTCAN network [31:16] read-only TTCTC TT Cycle Time & Count 0x138 32 read-only 0x3F0000 0x3FFFFF CT Cycle Time Non-fractional part of the difference of the node's local time and Ref_Mark (see Section 4.5). 0x0000-FFFF Cycle time value of TTCAN Basic Cycle [15:0] read-only CC Cycle Count 0x00-3F Number of actual Basic Cycle in the System Matrix [21:16] read-only TTCPT TT Capture Time 0x13C 32 read-only 0x0 0xFFFF003F CCV Cycle Count Value Cycle count value captured together with SWV. 0x00-3F Captured cycle count value [5:0] read-only SWV Stop Watch Value On a rising/falling edge (as configured via TTOCN.SWP) at the Stop Watch Trigger pin m_ttcan_swt, when TTOCN.SWS is != '00' and TTIR.SWE is '0', the actual time value as selected by TTOCN.SWS (cycle, local, global) is copied to SWV and TTIR.SWE will be set to '1'. Capturing of the next stop watch value is enabled by resetting TTIR.SWE. 0x0000-FFFF Captured Stop Watch value [31:16] read-only TTCSM TT Cycle Sync Mark 0x140 32 read-only 0x0 0xFFFF CSM Cycle Sync Mark The Cycle Sync Mark is measured [15:0] read-only RXFTOP_CTL Receive FIFO Top control 0x180 32 read-write 0x0 0x3 F0TPE FIFO 0 Top Pointer Enable. This enables the FIFO top pointer logic to set the FIFO Top Address (FnTA) and message word counter. This logic is also disabled when the IP is being reconfigured (CCCR.CCE=1). When this logic is disabled a Read from RXFTOP0_DATA is undefined. [0:0] read-write F1TPE FIFO 1 Top Pointer Enable. [1:1] read-write RXFTOP0_STAT Receive FIFO 0 Top Status 0x1A0 32 read-only 0x0 0xFFFF F0TA Current FIFO 0 Top Address. This is a pointer to the next word in the message buffer defined by the FIFO Start Address (FnSA), Get Index (FnGI), the FIFO message size (FnDS) and the message word counter (FnMWC) FnTA = FnSA + FnGI * msg_size[FnDS] + FnMWC [15:0] read-only RXFTOP0_DATA Receive FIFO 0 Top Data 0x1A8 32 read-only 0x0 0x0 F0TD When enabled (F0TPE=1) read data from MRAM at location FnTA. This register can have a read side effect if the following conditions are met: - M_TTCAN not being reconfigured (CCCR.CCE=0) - FIFO Top Pointer logic is enabled (FnTPE=1) - FIFO is not empty (FnFL!=0) The read side effect is as follows: - if FnMWC pointed to the last word of the message (as indicated by FnDS) then the corresponding message index (FnGI) is automatically acknowledge by a write to FnAI - FnMWC is incremented (or restarted if FnMWC pointed to the last word of the message) - the FIFO top address FnTA is incremented (with FIFO wrap around) When this logic is disabled (F0TPE=0) a Read from this register returns undefined data. [31:0] read-only RXFTOP1_STAT Receive FIFO 1 Top Status 0x1B0 32 read-only 0x0 0xFFFF F1TA See F0TA description [15:0] read-only RXFTOP1_DATA Receive FIFO 1 Top Data 0x1B8 32 read-only 0x0 0x0 F1TD See F0TD description [31:0] read-only CTL Global CAN control register 0x1000 32 read-write 0x0 0x800000FF STOP_REQ Clock Stop Request for each TTCAN IP . The m_ttcan_clkstop_req of each TTCAN IP is directly driven by these bits. [7:0] read-write MRAM_OFF MRAM off 0= Default MRAM on (with MRAM retained in DeepSleep). 1= Switch MRAM off (not retained) to save power. Before setting this bit all the CAN channels have to be powered down using the STOP_REQ/ACK bits. When the MRAM is off any access attempt to it is considered an address error (as if MRAM_SIZE=0). After switching the MRAM on again software needs to allow for a certain power up time before MRAM can be used, i.e. before STOP_REQ can be de-asserted. The power up time is equivalent to the system SRAM power up time specified in the CPUSS.RAM_PWR_DELAY_CTL register. To meet S8 platform requirements, MRAM_OFF should be set to 0 prior to transitioning to Hibernate mode. [31:31] read-write STATUS Global CAN status register 0x1004 32 read-only 0x0 0xFF STOP_ACK Clock Stop Acknowledge for each TTCAN IP. These bits are directly driven by m_ttcan_clkstop_ack of each TTCAN IP. When this bit is set the corresponding TTCAN IP clocks will be gated off, except HCLK will enabled for each AHB write [7:0] read-only INTR0_CAUSE Consolidated interrupt0 cause register 0x1010 32 read-only 0x0 0xFF INT0 Show pending m_ttcan_int0 of each channel [7:0] read-only INTR1_CAUSE Consolidated interrupt1 cause register 0x1014 32 read-only 0x0 0xFF INT1 Show pending m_ttcan_int1 of each channel [7:0] read-only TS_CTL Time Stamp control register 0x1020 32 read-write 0x0 0x8000FFFF PRESCALE Time Stamp counter prescale value. When enabled divide the Host clock (HCLK) by PRESCALE+1 to create Time Stamp clock ticks. [15:0] read-write ENABLED Counter enable bit 0 = Count disabled. Stop counting up and keep the counter value 1 = Count enabled. Start counting up from the current value [31:31] read-write TS_CNT Time Stamp counter value 0x1024 32 read-write 0x0 0xFFFF VALUE The counter value of the Time Stamp Counter. When enabled this counter will count Time Stamp clock ticks from the pre-scaler. When written this counter and the pre-scaler will reset to 0 (write data is ignored). [15:0] read-write ECC_CTL ECC control 0x1080 32 read-write 0x0 0x10000 ECC_EN Enable ECC for CANFD SRAM When disabled also all error injection functionality is disabled. [16:16] read-write ECC_ERR_INJ ECC error injection 0x1084 32 read-write 0xFFFC 0x7F10FFFC ERR_ADDR Specifies the address of the word where an error will be injected on write or an non-correctable error will be suppressed. When the ERR_EN bit is set an error parity (ERR_PAR) is injected when any write, from bus or a CAN channel, is done to this address. When the ERR_EN bit is set and the access address matches ERR_ADDR then a non-correctable ECC error or an Address error will NOT result in a bus error or CAN channel shutdown. Note that error reporting to the fault structure cannot be suppressed. [15:2] read-write ERR_EN Enable error injection (ECC_EN must be 1). When this bit is set the error parity (ERR_PAR) will be used when an AHB write is done to the ERR_ADDR address. When the error word is read a single or double error will be reported to the fault structure just like for a real ECC error (even if this bit is no longer set). When this bit is set (and ECC_EN=1) a non-correctable error (ECC or address error) for the ERR_ADDR will not be reported back to the CAN channel or AHB bus. [20:20] read-write ERR_PAR ECC Parity bits to use for ECC error injection at address ERR_ADDR. [30:24] read-write TDM0 TDM TDM 0x405A0000 0 65536 registers TDM_STRUCT TDM structure 0x00008000 TDM_TX_STRUCT TDM TX structure 0x00000000 TX_CTL TX control 0x0 32 read-write 0x10000 0x8001300F WORD_SIZE PCM word size: '0': 8 bit. '1': 10 bit. '2': 12 bit. '3': 14 bit. '4': 16 bit. '5': 18 bit. '6': 20 bit. '7': 24 bit. '8': 32 bit. '9'-'15': Undefined. [3:0] read-write SIZE_8 N/A 0 SIZE_10 N/A 1 SIZE_12 N/A 2 SIZE_14 N/A 3 SIZE_16 N/A 4 SIZE_18 N/A 5 SIZE_20 N/A 6 SIZE_24 N/A 7 SIZE_32 N/A 8 FORMAT Format: '0': Left-aligned delayed. '1': Left-aligned. '2': Right-aligned delayed. '3': Right-aligned. [13:12] read-write LEFT_DELAYED N/A 0 LEFT N/A 1 RIGHT_DELAYED N/A 2 RIGHT N/A 3 MS Master/slave setting: '0': Slave. - External transmitter 'tdm_tx_sck_in' and transmitter 'tdm_tx_fsync_in'. '1': Master. - Interface clock 'clk_if' is used to generate transmitter 'tdm_tx_sck_out' and transmitter 'tdm_tx_fsync_out'. [16:16] read-write SLAVE N/A 0 MASTER N/A 1 ENABLED Transmitter (TX) enable: '0': Disabled. All non-retained MMIO registers (e.g. the TX_FIFO_STATUS and INTR_TX registers) have their fields reset to their default value. '1': Enabled. Note: when all transmitters and receivers are disabled, the SRAMs are driven into low power mode, if supported by the SRAM. When exiting such low power mode software needs to allow for a certain power up time before SRAM can be used, i.e. before ACTIVE can be asserted. The power up time is equivalent to the system SRAM power up time specified in the CPUSS.RAM_PWR_DELAY_CTL register (or equivalent for platforms other than MXS40). [31:31] read-write TX_IF_CTL TX interface control 0x10 32 read-write 0x1F018707 0x9F1FB7FF CLOCK_DIV Interface clock divider (legal range [1, 255]). The TDM interface 'tdm_tx_sck_out' output signal is defined as clk_if / (CLOCK_DIV + 1). CLOCK_DIV should be set to an odd value ({1, 3, 5, ..., 255}), to ensure a 50/50 percent duty cycle clock. Note: Used in master configuration only. [7:0] read-write CLOCK_SEL Interface clock 'clk_if' selection: '0': SRSS clock clk_if_srss[0]. '1': SRSS clock clk_if_srss[1]. '2': SRSS clock clk_if_srss[2]. '3': SRSS clock clk_if_srss[3]. '4': Master interface clock 'tdm_tx_mck_in'. '5'-'7': undefined. Note: the application is always required to program this field to a value different from the default. [10:8] read-write SEL_SRSS_CLOCK0 N/A 0 SEL_SRSS_CLOCK1 N/A 1 SEL_SRSS_CLOCK2 N/A 2 SEL_SRSS_CLOCK3 N/A 3 SEL_TDM_TX_MCK_IN N/A 4 SCK_POLARITY Clock polarity: '0': Clock signal is used 'as is'. '1': Clock signal is inverted. Note: Used in BOTH master and slave configurations. [12:12] read-write FSYNC_POLARITY Channel synchronization polarity: '0': Channel synchronization signal is used 'as is'. '1': Channel synchronization signal is inverted. Note: Used in BOTH master and slave configurations. [13:13] read-write FSYNC_FORMAT Channel synchronization pulse format: '0': Duration of a single bit period. '1': Duration of the first channel. [15:15] read-write BIT_PERIOD N/A 0 CH_PERIOD N/A 1 CH_NR Number of channels in the frame: '0': Undefined/illegal. '1': 2 channels. '2': 3 channels. ... '31': 32 channels. Note: the field value chould be less than CH_NR (the number of support channels). Note: the TX_CH_CTL.CH_EN fields can be used to enable/disable indvidual channels. [20:16] read-write CH_SIZE Channel size: '0'-'2': Undefined/illegal. '3': 4 bits. ... '31': 32 bits. Note: if TX_CTL.WORD_SIZE is greater than CH_SIZE, the more significant bits of the word are transmitted and the lesser significant bits of the word are dropped. [28:24] read-write SIZE_1 N/A 0 SIZE_2 N/A 1 SIZE_32 N/A 31 I2S_MODE I2S mode setting: '0': TDM mode. '1': I2S mode. [31:31] read-write TDM N/A 0 I2S N/A 1 TX_CH_CTL TX channel control 0x14 32 read-write 0x0 0xFFFFFFFF CH_EN Channel enables: channel i is controlled by CH_EN[i]. '0': Disabled. The TX FIFO does not produce channel i words and the transmitted channel i words on the interface are not driven (the output enable of the 'tdm_tx_sd_out' output signal is not driven). '1': Enabled. Note: Only bit 0 through TX_IF_CTL.CH_NR may be set to '1'; i.e. only channels that are present in the frame can be enabled. [31:0] read-write TX_TEST_CTL TX test control 0x20 32 read-write 0x0 0x80000000 ENABLED Test mode enable. '0': Disabled. Functional mode. - Transmitter tx_sck_in = IOSS tdm_tx_sck_in. - Transmitter tx_fsync_in = IOSS tdm_tx_fsync_in. - Receiver rx_sd_in = IOSS tdm_rx_sd_in. '1': Enabled. Test mode (intended to be used with (slave transmitter, master receiver) configuration). - Transmitter tx_sck_in = Receiver tdm_rx_sck_out. - Transmitter tx_fsync_in = Receiver tdm_rx_fsync_out. - Receiver rx_sd_in = Transmitter tdm_tx_sd_out. Note: TX_TEST_CTL.ENABLED and RX_TEST_CTL.ENABLED should not be set to '1' simultaneously. [31:31] read-write FUNCTIONAL N/A 0 TEST N/A 1 TX_ROUTE_CTL TX route control 0x24 32 read-write 0x0 0x3 MODE Controls routing to the TX slave signalling inputs (FSYNC/SCK): '0': TX slave signaling indipendent from RX signaling: - Transmitter tx_sck_in = IOSS tdm_tx_sck_in - Transmitter tx_fsync_in = IOSS tdm_tx_fsync_in '1': TX slave signalling inputs driven by RX Slave: - Transmitter tx_sck_in = IOSS tdm_rx_sck_in - Transmitter tx_fsync_in = IOSS tdm_rx_fsync_in '2': TX slave signalling inputs driven by RX Master: - Transmitter tx_sck_in = receiver tdm_rx_sck_out - Transmitter tx_fsync_in = receiver tdm_rx_fsync_out Note: MODE=0 is the default behaviour. MODE=1 or 2 is intended to allow the TX slave to share the same signaling used by the RX. This feature can be used to reduce the number of IO pins necessary to connect to an external codec supporting common TX/RX signaling. Note: when MODE=1 or 2, TX_TEST_CTL.ENABLED and RX_TEST_CTL.ENABLED should not be set to '1'. [1:0] read-write TX_IN_DRIVEN_BY_IOSS_TX_IN N/A 0 TX_IN_DRIVEN_BY_IOSS_RX_IN N/A 1 TX_IN_DRIVEN_BY_RX_OUT N/A 2 TX_FIFO_CTL TX FIFO control 0x80 32 read-write 0x0 0xF007F TRIGGER_LEVEL Trigger level. When the TX FIFO has less entries than the number of this field, a transmitter trigger event is generated: - INTR_TX.FIFO_TRIGGER = (# FIFO entries < TRIGGER_LEVEL) [6:0] read-write MUTE Mute functionality: '0': HW uses TX FIFO data. '1': HW uses a constant PCM data value of '0'. Mute does advance the FIFO read pointer. Note: HW ensures that mute functionality synchronizes on the first channel of a frame to ensure that either all or none of the frame's channels are muted. [16:16] read-write FREEZE Freeze functionality: '0': HW uses TX FIFO data and advances the FIFO read pointer. '1': HW uses a constant PCM data value of '0' or the previous channel PCM data is replayed. Freeze does not advance the FIFO read pointer (the FIFO data is not used). Note: HW ensures that freeze functionality synchronizes on the first channel of a frame to ensure that PCM data of one channel is not misassigned to another channel. As a result, the freeze functionality can be activated at any time. Note: This functionality is intended for debugging purposes. [17:17] read-write ACTIVE Activate functionality: '0': Transmitter off. The FIFO_UNDERFLOW interrupt cause will not be activated. '1': Transmitter on. The FIFO_UNDERFLOW interrupt may be activated (when an underflow event occurs). Note: This functionality is intended for startup purposes. [18:18] read-write REPLAY Replay functionality (used when FREEZE is '1' or in case of a FIFO underflow event): '0': HW uses a constant PCM data value of '0'. '1': HW uses the previous PCM data value. [19:19] read-write TX_FIFO_STATUS TX FIFO status 0x84 32 read-only 0x0 0x7F7F00FF USED Number of used/occupied entries in the TX FIFO. The field value is in the range [0, 128]. When '0', the FIFO is empty. When '128', the FIFO is full. [7:0] read-only RD_PTR TX FIFO read pointer: FIFO location from which a data is read. Note: This functionality is intended for debugging purposes. [22:16] read-only WR_PTR TX FIFO write pointer: FIFO location at which a new data is written by the hardware. Note: This functionality is intended for debugging purposes. [30:24] read-only TX_FIFO_WR TX FIFO write 0x88 32 write-only 0x0 0xFFFFFFFF DATA Data (PCM sample) written to the TX FIFO. Writing adds the data to the TX FIFO; i.e. behavior is similar to that of a PUSH operation (TX_FIFO_STATUS.WR_PTR is incremented and TX_FIFO_STATUS.USED is incremented). The write data (DATA) should be right aligned when it is written to the FIFO entry (data[31:0]): - 8 bit, data[31:0] = DATA[7:0] << 24. - 10 bit, data[31:0] = DATA[9:0] << 22. - 12 bit, data[31:0] = DATA[11:0] << 20. - 14 bit, data[31:0] = DATA[13:0] << 18. - 16 bit, data[31:0] = DATA[15:0] << 16. - 18 bit, data[31:0] = DATA[17:0] << 14. - 20 bit, data[31:0] = DATA[19:0] << 12. - 24 bit, data[31:0] = DATA[23:0] << 8. - 32 bit, data[31:0] = DATA[31:0]. Note: Writing to a full TX FIFO activates INTR.TX_FIFO_OVERFLOW. [31:0] write-only INTR_TX Interrupt 0xC0 32 read-write 0x0 0x107 FIFO_TRIGGER HW sets this field to '1', when a TX trigger is generated. [0:0] read-write FIFO_OVERFLOW HW sets this field to '1', when writing to a full TX FIFO (TX_FIFO_STATUS.USED is '128'). [1:1] read-write FIFO_UNDERFLOW HW sets this field to '1', when reading from an (almost) empty TX FIFO (TX_FIFO_STATUS.USED < 'number of enabled channels per frame'). This is referred to as an underflow event. Note: HW ensures that either all or none of the frame's channels are transmitted. In a TX FIFO underflow situation, HW replays previous PCM data or uses a constant PCM data value of '0'. [2:2] read-write IF_UNDERFLOW HW sets this field to '1', when PCM samples are not generated in time for the interface logic (interface underflow). This may be an indication that the IP system frequency is too low wrt. the interface frequency (a SW configuration error). The interface underflow is a non-recoverable error and requires SW disabling of the channel (a SW write to INTR_TX.IF_UNDERFLOW does not resolve the interface underflow). Note: This functionality is intended for debug purposes. [8:8] read-write INTR_TX_SET Interrupt set 0xC4 32 read-write 0x0 0x107 FIFO_TRIGGER Write this field with '1' to set corresponding INTR_TX field (a write of '0' has no effect). [0:0] read-write FIFO_OVERFLOW Write this field with '1' to set corresponding INTR_TX field (a write of '0' has no effect). [1:1] read-write FIFO_UNDERFLOW Write this field with '1' to set corresponding INTR_TX field (a write of '0' has no effect). [2:2] read-write IF_UNDERFLOW Write this field with '1' to set corresponding INTR_TX field (a write of '0' has no effect). [8:8] read-write INTR_TX_MASK Interrupt mask 0xC8 32 read-write 0x0 0x107 FIFO_TRIGGER Mask for corresponding field in INTR_TX register. [0:0] read-write FIFO_OVERFLOW Mask for corresponding field in INTR_TX register. [1:1] read-write FIFO_UNDERFLOW Mask for corresponding field in INTR_TX register. [2:2] read-write IF_UNDERFLOW Mask for corresponding field in INTR_TX register. [8:8] read-write INTR_TX_MASKED Interrupt masked 0xCC 32 read-only 0x0 0x107 FIFO_TRIGGER Logical AND of corresponding INTR_TX and INTR_TX_MASK fields. [0:0] read-only FIFO_OVERFLOW Logical AND of corresponding INTR_TX and INTR_TX_MASK fields. [1:1] read-only FIFO_UNDERFLOW Logical AND of corresponding INTR_TX and INTR_TX_MASK fields. [2:2] read-only IF_UNDERFLOW Logical AND of corresponding INTR_TX and INTR_TX_MASK fields. [8:8] read-only TDM_RX_STRUCT TDM RX structure 0x00000100 RX_CTL RX control 0x0 32 read-write 0x100 0x8001310F WORD_SIZE PCM word size: '0': 8 bit. '1': 10 bit. '2': 12 bit. '3': 14 bit. '4': 16 bit. '5': 18 bit. '6': 20 bit. '7': 24 bit. '8': 32 bit. '9'-'15': Undefined. [3:0] read-write SIZE_8 N/A 0 SIZE_10 N/A 1 SIZE_12 N/A 2 SIZE_14 N/A 3 SIZE_16 N/A 4 SIZE_18 N/A 5 SIZE_20 N/A 6 SIZE_24 N/A 7 SIZE_32 N/A 8 WORD_SIGN_EXTEND Word extension: '0': zero extension. '1': sign extension. [8:8] read-write ZERO_EXTEND N/A 0 SIGN_EXTEND N/A 1 FORMAT Format: '0': Left-aligned delayed. '1': Left-aligned. '2': Right-aligned delayed. '3': Right-aligned. [13:12] read-write LEFT_DELAYED N/A 0 LEFT N/A 1 RIGHT_DELAYED N/A 2 RIGHT N/A 3 MS Master/slave setting: '0': Slave. - External receiver 'tdm_rx_sck_in' and receiver 'tdm_rx_fsync_in'. '1': Master. - Interface clock 'clk_if' is used to generate receiver 'tdm_rx_sck_out' and receiver 'tdm_rx_fsync_out'. [16:16] read-write SLAVE N/A 0 MASTER N/A 1 ENABLED Receiver (RX) enable: '0': Disabled. All non-retained MMIO registers (e.g. the RX_FIFO_STATUS and INTR_RX registers) have their fields reset to their default value. '1': Enabled. Note: when all transmitters and receivers are disabled, the SRAMs are driven into low power mode, if supported by the SRAM. When exiting such low power mode software needs to allow for a certain power up time before SRAM can be used, i.e. before ACTIVE can be asserted. The power up time is equivalent to the system SRAM power up time specified in the CPUSS.RAM_PWR_DELAY_CTL register (or equivalent for platforms other than MXS40). [31:31] read-write RX_IF_CTL RX interface control 0x10 32 read-write 0x1F018707 0xFF1FF7FF CLOCK_DIV Interface clock divider (legal range [1, 255]). The TDM interface 'tdm_rx_sck_out' output signals is defined as clk_if / (CLOCK_DIV + 1). CLOCK_DIV should be set to an odd value ({1, 3, 5, ..., 255}), to ensure a 50/50 percent duty cycle clock. Note: Used in master configuration only. Note: Due to delays in the IO SubSystem (specifically the IO cells), the maximum TDM interface clock 'tdm_rx_sck_out' may be restricted. As a result, the maximum bitrate is less than the theoretical maximum (32 channels, 32 bits per channel and a high Fs of e.g. 48 kHz). This restriction is most applicable to the master, receiver configuration. [7:0] read-write CLOCK_SEL Interface clock 'clk_if' selection: '0': SRSS clock clk_if_srss[0]. '1': SRSS clock clk_if_srss[1]. '2': SRSS clock clk_if_srss[2]. '3': SRSS clock clk_if_srss[3]. '4': Master interface clock 'tdm_rx_mck_in'. '5'-'7': undefined. Note: the application is always required to program this field to a value different from the default. [10:8] read-write SEL_SRSS_CLOCK0 N/A 0 SEL_SRSS_CLOCK1 N/A 1 SEL_SRSS_CLOCK2 N/A 2 SEL_SRSS_CLOCK3 N/A 3 SEL_TDM_RX_MCK_IN N/A 4 SCK_POLARITY Clock polarity: '0': Clock signal is used 'as is'. '1': Clock signal is inverted. Note: Used in BOTH master and slave configurations. [12:12] read-write FSYNC_POLARITY Channel synchronization polarity: '0': Channel synchronization signal is used 'as is'. '1': Channel synchronization signal is inverted. Note: Used in BOTH master and slave configurations. [13:13] read-write LATE_SAMPLE Interface late sample sample delay: Slave configuration (RX_CTL.MS is '0'). '0': Sample PCM bit value on rising edge (SCK_POLARITY is '0') or falling edge (SCK_POLARITY is '1') of receiver 'rx_sck_in'. '1': Sample PCM bit value on falling edge (SCK_POLARITY is '0') or rising edge (SCK_POLARITY is '1') of receiver 'rx_sck_in' (half a cycle delay). Master configuration (RX_CTL.MS is '1'). '0': Sample PCM bit value on rising edge (SCK_POLARITY is '0') or falling edge (SCK_POLARITY is '1') of receiver 'rx_sck_out'. '1': Sample PCM bit value on falling edge (SCK_POLARITY is '0') or rising edge (SCK_POLARITY is '1') of receiver 'rx_sck_out' (half a cycle delay). Note: This field can be set to '1' when the roundtrip delay is large (typically) in a master receiver configuration. [14:14] read-write RISING N/A 0 FALLING N/A 1 FSYNC_FORMAT Channel synchronization pulse format: '0': Duration of a single bit period. '1': Duration of the first channel. [15:15] read-write BIT_PERIOD N/A 0 CH_PERIOD N/A 1 CH_NR Number of channels in the frame: '0': Undefined/illegal. '1': 2 channels. '2': 3 channels. ... '31': 32 channels. Note: the field value chould be less than CH_NR (the number of support channels). Note: the RX_CH_CTL.CH_EN fields can be used to enable/disable indvidual channels. [20:16] read-write CH_SIZE Channel size: '0'-'2': Undefined/illegal. '3': 4 bits. ... '31': 32 bits. Note: if RX_CTL.WORD_SIZE is greater than CH_SIZE, the lesser significant bits of the word are filled with '0's. [28:24] read-write SIZE_1 N/A 0 SIZE_2 N/A 1 SIZE_32 N/A 31 LATE_CAPTURE Extra delay (in 'rx_sck_out' cycles) for capturing 'tdm_rx_sd_in': '0': no extra delay '1': 1 cycle extra delay '2': 2 cycles extra delay '3': 3 cycles extra delay Note: the value of this field pushes further out the capturing edges used by the receiver to sample 'tdm_rx_sd_in'. This function is intended to support very large round-trip delays in a master receiver configuration, where the delay at the receiver between 'tdm_rx_fsync_out' and the arrival of the first bit on 'tdm_rx_sd_in' is multiple clock cycles. [30:29] read-write EXTRA_DELAY_0 N/A 0 EXTRA_DELAY_1 N/A 1 EXTRA_DELAY_2 N/A 2 EXTRA_DELAY_3 N/A 3 I2S_MODE I2S mode setting: '0': TDM mode. '1': I2S mode. [31:31] read-write TDM N/A 0 I2S N/A 1 RX_CH_CTL RX channel control 0x14 32 read-write 0x0 0xFFFFFFFF CH_EN Channel enables: channel i is controlled by CH_EN[i]. '0': Disabled. The RX FIFO does not consume channel i words and the received channel i words on the interface are discarded. '1': Enabled.. Note: Only bit 0 through RX_IF_CTL.CH_NR may be set to '1'; i.e. only channels that are present in the frame can be enabled. [31:0] read-write RX_TEST_CTL RX test control 0x20 32 read-write 0x0 0x80000000 ENABLED Test mode enable. '0': Disabled. Functional mode. - Receiver rx_sck_in = IOSS tdm_rx_sck_in. - Receiver rx_fsync_in = IOSS tdm_rx_fsync_in. - Receiver rx_sd_in = IOSS tdm_rx_sd_in. '1': Enabled. Test mode (intended to be used with (master transmitter, slave receiver) configuration). - Receiver rx_sck_in = Transmitter tdm_tx_sck_out. - Receiver rx_fsync_in = Transmitter tdm_tx_fsync_out. - Receiver rx_sd_in = Transmitter tdm_tx_sd_out. Note: TX_TEST_CTL.ENABLED and RX_TEST_CTL.ENABLED should not be set to '1' simultaneously. [31:31] read-write FUNCTIONAL N/A 0 TEST N/A 1 RX_ROUTE_CTL RX route control 0x24 32 read-write 0x0 0x3 MODE Controls routing to the RX slave signalling inputs (FSYNC/SCK): '0': RX slave signaling indipendent from TX signaling: - Receiver rx_sck_in = IOSS tdm_rx_sck_in - Receiver rx_fsync_in = IOSS tdm_rx_fsync_in '1': RX slave signalling inputs driven by TX Slave: - Receiver rx_sck_in = IOSS tdm_tx_sck_in - Receiver rx_fsync_in = IOSS tdm_tx_fsync_in '2': RX slave signalling inputs driven by TX Master: - Receiver rx_sck_in = transmitter tdm_tx_sck_out - Receiver rx_fsync_in = transmitter tdm_tx_fsync_out Note: MODE=0 is the default behaviour. MODE=1 or 2 is intended to allow the RX slave to share the same signaling used by the TX. This feature can be used to reduce the number of IO pins necessary to connect to an external codec supporting common TX/RX signaling. Note: when MODE=1 or 2, TX_TEST_CTL.ENABLED and RX_TEST_CTL.ENABLED should not be set to '1'. [1:0] read-write RX_IN_DRIVEN_BY_IOSS_RX_IN N/A 0 RX_IN_DRIVEN_BY_IOSS_TX_IN N/A 1 RX_IN_DRIVEN_BY_TX_OUT N/A 2 RX_FIFO_CTL RX FIFO control 0x80 32 read-write 0x0 0x6007F TRIGGER_LEVEL Trigger level. When the RX FIFO has more entries than the number of this field, a receiver trigger event is generated: - INTR_RX.FIFO_TRIGGER = (# FIFO entries > TRIGGER_LEVEL) [6:0] read-write FREEZE Freeze functionality: '0': HW writes to the RX FIFO and advances the FIFO write pointer. '1': HW writes from the RX FIFO have no effect: freeze will not advance the FIFO write pointer. Note: HW ensures that freeze functionality synchronizes on the first channel of a frame to ensure that PCM data of one channel is not misassigned to another channel. As a result, the freeze functionality can be activated at any time. Note: This functionality is intended for debugging purposes. [17:17] read-write ACTIVE Activate functionality: '0': Receiver off. The FIFO_OVERFLOW interrupt cause will not be activated. '1': Receiver on. The FIFO_OVERFLOW interrupt may be activated (when an overflow event occurs). Note: This functionality is intended for stopping purposes. [18:18] read-write RX_FIFO_STATUS RX FIFO status 0x84 32 read-only 0x0 0x7F7F00FF USED Number of used/occupied entries in the RX FIFO. The field value is in the range [0, 128]. When '0', the FIFO is empty. When '128', the FIFO is full. [7:0] read-only RD_PTR RX FIFO read pointer: FIFO location from which a data is read. Note: This functionality is intended for debugging purposes. [22:16] read-only WR_PTR RX FIFO write pointer: FIFO location at which a new data is written by the hardware. Note: This functionality is intended for debugging purposes. [30:24] read-only RX_FIFO_RD RX FIFO read 0x88 32 read-only 0x0 0xFFFFFFFF DATA Data (PCM sample) read from the RX FIFO. Reading removes the data from the RX FIFO; i.e. behavior is similar to that of a POP operation (RX_FIFO_STATUS.RD_PTR is incremented and RX_FIFO_STATUS.USED is decremented). The read data (DATA) is right aligned (unused bit positions follow the specified sign extension per RX_CTL.WORD_SIGN_EXTEND) when it is read from the FIFO entry (data[31:0]): - 8 bit, DATA[7:0] = data[31:24]. - 10 bit, DATA[9:0] = data[31:22]. - 12 bit, DATA[11:0] = data[31:20]. - 14 bit, DATA[13:0] = data[31:18]. - 16 bit, DATA[15:0] = data[31:16]. - 18 bit, DATA[17:0] = data[31:14]. - 20 bit, DATA[19:0] = data[31:12]. - 24 bit, DATA[23:0] = data[31:8]. - 32 bit, DATA[31:0] = data[31:0]. Note: Reading from an empty RX FIFO activates INTR_RX.FIFO_UNDERFLOW. [31:0] read-only RX_FIFO_RD_SILENT RX FIFO silent read 0x8C 32 read-only 0x0 0xFFFFFFFF DATA N/A [31:0] read-only INTR_RX Interrupt 0xC0 32 read-write 0x0 0x107 FIFO_TRIGGER HW sets this field to '1', when a RX trigger is generated. [0:0] read-write FIFO_OVERFLOW HW sets this field to '1', when writing to a (almost) full RX FIFO (128 -RX_FIFO_STATUS.USED < 'number of enabled channels per frame'). This is referred to as an overflow event. Note: HW ensures that either all or none of the frame's channels are received. In a RX FIFO overflow situation, HW discards received PCM data values. [1:1] read-write FIFO_UNDERFLOW HW sets this field to '1', when reading from an empty RX FIFO (RX_FIFO_STATUS.USED is '0'). [2:2] read-write IF_OVERFLOW HW sets this field to '1', when PCM samples are generated too fast by the interface logic (interface overflow). This may be an indication that the IP system frequency is too low wrt. the interface frequency (a SW configuration error). The interface overflow is a non-recoverable error and requires SW disabling of the channel (a SW write to INTR_RX.IF_OVERFLOW does not resolve the interface underflow). Note: This functionality is intended for debug purposes. [8:8] read-write INTR_RX_SET Interrupt set 0xC4 32 read-write 0x0 0x107 FIFO_TRIGGER Write this field with '1' to set corresponding INTR_RX field (a write of '0' has no effect). [0:0] read-write FIFO_OVERFLOW Write this field with '1' to set corresponding INTR_RX field (a write of '0' has no effect). [1:1] read-write FIFO_UNDERFLOW Write this field with '1' to set corresponding INTR_RX field (a write of '0' has no effect). [2:2] read-write IF_OVERFLOW Write this field with '1' to set corresponding INTR_RX field (a write of '0' has no effect). [8:8] read-write INTR_RX_MASK Interrupt mask 0xC8 32 read-write 0x0 0x107 FIFO_TRIGGER Mask for corresponding field in INTR_RX register. [0:0] read-write FIFO_OVERFLOW Mask for corresponding field in INTR_RX register. [1:1] read-write FIFO_UNDERFLOW Mask for corresponding field in INTR_RX register. [2:2] read-write IF_OVERFLOW Mask for corresponding field in INTR_RX register. [8:8] read-write INTR_RX_MASKED Interrupt masked 0xCC 32 read-only 0x0 0x107 FIFO_TRIGGER Logical AND of corresponding INTR_RX and INTR_RX_MASK fields. [0:0] read-only FIFO_OVERFLOW Logical AND of corresponding INTR_RX and INTR_RX_MASK fields. [1:1] read-only FIFO_UNDERFLOW Logical AND of corresponding INTR_RX and INTR_RX_MASK fields. [2:2] read-only IF_OVERFLOW Logical AND of corresponding INTR_RX and INTR_RX_MASK fields. [8:8] read-only