1 /***************************************************************************//** 2 * \file cyhal_psc3_vqfn_48.h 3 * 4 * \brief 5 * PSC3 device GPIO HAL header for VQFN-48 package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYHAL_PSC3_VQFN_48_H_ 28 #define _CYHAL_PSC3_VQFN_48_H_ 29 30 #include "cyhal_hw_resources.h" 31 32 /** 33 * \addtogroup group_hal_impl_pin_package_psc3_vqfn_48 PSC3 VQFN-48 34 * \ingroup group_hal_impl_pin_package 35 * \{ 36 * Pin definitions and connections specific to the PSC3 VQFN-48 package. 37 */ 38 39 #if defined(__cplusplus) 40 extern "C" { 41 #endif /* __cplusplus */ 42 43 /** Gets a pin definition from the provided port and pin numbers */ 44 #define CYHAL_GET_GPIO(port, pin) ((((uint8_t)(port)) << 3U) + ((uint8_t)(pin))) 45 46 /** Macro that, given a gpio, will extract the pin number */ 47 #define CYHAL_GET_PIN(pin) ((uint8_t)(((uint8_t)pin) & 0x07U)) 48 /** Macro that, given a gpio, will extract the port number */ 49 #define CYHAL_GET_PORT(pin) ((uint8_t)(((uint8_t)pin) >> 3U)) 50 51 /** Definitions for all of the pins that are bonded out on in the VQFN-48 package for the PSC3 series. */ 52 typedef enum { 53 NC = 0xFF, //!< No Connect/Invalid Pin 54 55 P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0 56 57 P1_2 = CYHAL_GET_GPIO(CYHAL_PORT_1, 2), //!< Port 1 Pin 2 58 P1_3 = CYHAL_GET_GPIO(CYHAL_PORT_1, 3), //!< Port 1 Pin 3 59 60 P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0), //!< Port 2 Pin 0 61 P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1), //!< Port 2 Pin 1 62 P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2), //!< Port 2 Pin 2 63 P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3), //!< Port 2 Pin 3 64 65 P4_0 = CYHAL_GET_GPIO(CYHAL_PORT_4, 0), //!< Port 4 Pin 0 66 P4_1 = CYHAL_GET_GPIO(CYHAL_PORT_4, 1), //!< Port 4 Pin 1 67 P4_2 = CYHAL_GET_GPIO(CYHAL_PORT_4, 2), //!< Port 4 Pin 2 68 P4_3 = CYHAL_GET_GPIO(CYHAL_PORT_4, 3), //!< Port 4 Pin 3 69 P4_4 = CYHAL_GET_GPIO(CYHAL_PORT_4, 4), //!< Port 4 Pin 4 70 P4_5 = CYHAL_GET_GPIO(CYHAL_PORT_4, 5), //!< Port 4 Pin 5 71 P4_6 = CYHAL_GET_GPIO(CYHAL_PORT_4, 6), //!< Port 4 Pin 6 72 P4_7 = CYHAL_GET_GPIO(CYHAL_PORT_4, 7), //!< Port 4 Pin 7 73 74 P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), //!< Port 6 Pin 0 75 P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), //!< Port 6 Pin 1 76 P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2 77 P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3 78 79 P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0 80 P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1 81 P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2 82 83 P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), //!< Port 8 Pin 0 84 P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), //!< Port 8 Pin 1 85 P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), //!< Port 8 Pin 2 86 P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), //!< Port 8 Pin 3 87 88 P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0 89 P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2 90 P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3 91 92 AN_A0 = CYHAL_GET_GPIO(NC, 0), //!< AN_A Pin 0 93 AN_A1 = CYHAL_GET_GPIO(NC, 1), //!< AN_A Pin 1 94 AN_A2 = CYHAL_GET_GPIO(NC, 2), //!< AN_A Pin 2 95 AN_A3 = CYHAL_GET_GPIO(NC, 3), //!< AN_A Pin 3 96 AN_A4 = CYHAL_GET_GPIO(NC, 4), //!< AN_A Pin 4 97 AN_A5 = CYHAL_GET_GPIO(NC, 5), //!< AN_A Pin 5 98 99 AN_B1 = CYHAL_GET_GPIO(NC, 9), //!< AN_B Pin 1 100 AN_B2 = CYHAL_GET_GPIO(NC, 10), //!< AN_B Pin 2 101 AN_B3 = CYHAL_GET_GPIO(NC, 11), //!< AN_B Pin 3 102 AN_B4 = CYHAL_GET_GPIO(NC, 12), //!< AN_B Pin 4 103 } cyhal_gpio_psc3_vqfn_48_t; 104 105 /** Create generic name for the series/package specific type. */ 106 typedef cyhal_gpio_psc3_vqfn_48_t cyhal_gpio_t; 107 108 /* Connection type definition */ 109 /** Represents an association between a pin and a resource */ 110 typedef struct 111 { 112 uint8_t block_num; //!< The block number of the resource with this connection 113 uint8_t channel_num; //!< The channel number of the block with this connection 114 cyhal_gpio_t pin; //!< The GPIO pin the connection is with 115 en_hsiom_sel_t hsiom; //!< The HSIOM configuration value 116 } cyhal_resource_pin_mapping_t; 117 118 /* Pin connections */ 119 /** Indicates that a pin map exists for canfd_ttcan_rx*/ 120 #define CYHAL_PIN_MAP_DRIVE_MODE_CANFD_TTCAN_RX (CY_GPIO_DM_HIGHZ) 121 /** List of valid pin to peripheral connections for the canfd_ttcan_rx signal. */ 122 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_rx[3]; 123 /** Indicates that a pin map exists for canfd_ttcan_tx*/ 124 #define CYHAL_PIN_MAP_DRIVE_MODE_CANFD_TTCAN_TX (CY_GPIO_DM_STRONG_IN_OFF) 125 /** List of valid pin to peripheral connections for the canfd_ttcan_tx signal. */ 126 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_tx[3]; 127 /** Indicates that a pin map exists for cpuss_clk_fm_pump*/ 128 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_CLK_FM_PUMP (CY_GPIO_DM_STRONG_IN_OFF) 129 /** List of valid pin to peripheral connections for the cpuss_clk_fm_pump signal. */ 130 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_clk_fm_pump[1]; 131 /** Indicates that a pin map exists for cpuss_fault*/ 132 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_FAULT (CY_GPIO_DM_STRONG_IN_OFF) 133 /** List of valid pin to peripheral connections for the cpuss_fault signal. */ 134 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_fault[2]; 135 /** Indicates that a pin map exists for debug600_clk_swj_swclk_tclk*/ 136 #define CYHAL_PIN_MAP_DRIVE_MODE_DEBUG600_CLK_SWJ_SWCLK_TCLK (CY_GPIO_DM_PULLDOWN) 137 /** List of valid pin to peripheral connections for the debug600_clk_swj_swclk_tclk signal. */ 138 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_debug600_clk_swj_swclk_tclk[1]; 139 /** Indicates that a pin map exists for debug600_rst_swj_trstn*/ 140 #define CYHAL_PIN_MAP_DRIVE_MODE_DEBUG600_RST_SWJ_TRSTN (CY_GPIO_DM_PULLDOWN) 141 /** List of valid pin to peripheral connections for the debug600_rst_swj_trstn signal. */ 142 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_debug600_rst_swj_trstn[1]; 143 /** Indicates that a pin map exists for debug600_swj_swdio_tms*/ 144 #define CYHAL_PIN_MAP_DRIVE_MODE_DEBUG600_SWJ_SWDIO_TMS (CY_GPIO_DM_PULLUP) 145 /** List of valid pin to peripheral connections for the debug600_swj_swdio_tms signal. */ 146 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_debug600_swj_swdio_tms[1]; 147 /** Indicates that a pin map exists for debug600_swj_swdoe_tdi*/ 148 #define CYHAL_PIN_MAP_DRIVE_MODE_DEBUG600_SWJ_SWDOE_TDI (CY_GPIO_DM_PULLUP) 149 /** List of valid pin to peripheral connections for the debug600_swj_swdoe_tdi signal. */ 150 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_debug600_swj_swdoe_tdi[1]; 151 /** Indicates that a pin map exists for debug600_swj_swo_tdo*/ 152 #define CYHAL_PIN_MAP_DRIVE_MODE_DEBUG600_SWJ_SWO_TDO (CY_GPIO_DM_STRONG_IN_OFF) 153 /** List of valid pin to peripheral connections for the debug600_swj_swo_tdo signal. */ 154 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_debug600_swj_swo_tdo[1]; 155 /** Indicates that a pin map exists for debug600_trace_clock*/ 156 #define CYHAL_PIN_MAP_DRIVE_MODE_DEBUG600_TRACE_CLOCK (CY_GPIO_DM_STRONG_IN_OFF) 157 /** List of valid pin to peripheral connections for the debug600_trace_clock signal. */ 158 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_debug600_trace_clock[1]; 159 /** Indicates that a pin map exists for debug600_trace_data*/ 160 #define CYHAL_PIN_MAP_DRIVE_MODE_DEBUG600_TRACE_DATA (CY_GPIO_DM_STRONG_IN_OFF) 161 /** List of valid pin to peripheral connections for the debug600_trace_data signal. */ 162 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_debug600_trace_data[7]; 163 /** Indicates that a pin map exists for lpcomp_inn_comp*/ 164 #define CYHAL_PIN_MAP_DRIVE_MODE_LPCOMP_INN_COMP (CY_GPIO_DM_ANALOG) 165 /** List of valid pin to peripheral connections for the lpcomp_inn_comp signal. */ 166 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp[2]; 167 /** Indicates that a pin map exists for lpcomp_inp_comp*/ 168 #define CYHAL_PIN_MAP_DRIVE_MODE_LPCOMP_INP_COMP (CY_GPIO_DM_ANALOG) 169 /** List of valid pin to peripheral connections for the lpcomp_inp_comp signal. */ 170 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp[2]; 171 /** Indicates that a pin map exists for pass_an_a_pad_aio*/ 172 #define CYHAL_PIN_MAP_DRIVE_MODE_PASS_AN_A_PAD_AIO (CY_GPIO_DM_HIGHZ) 173 /** List of valid pin to peripheral connections for the pass_an_a_pad_aio signal. */ 174 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_an_a_pad_aio[6]; 175 /** Indicates that a pin map exists for pass_an_b_pad_aio*/ 176 #define CYHAL_PIN_MAP_DRIVE_MODE_PASS_AN_B_PAD_AIO (CY_GPIO_DM_HIGHZ) 177 /** List of valid pin to peripheral connections for the pass_an_b_pad_aio signal. */ 178 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_an_b_pad_aio[4]; 179 /** Indicates that a pin map exists for pass_gpio_00_aio*/ 180 #define CYHAL_PIN_MAP_DRIVE_MODE_PASS_GPIO_00_AIO (CY_GPIO_DM_ANALOG) 181 /** List of valid pin to peripheral connections for the pass_gpio_00_aio signal. */ 182 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_gpio_00_aio[1]; 183 /** Indicates that a pin map exists for pass_gpio_01_aio*/ 184 #define CYHAL_PIN_MAP_DRIVE_MODE_PASS_GPIO_01_AIO (CY_GPIO_DM_ANALOG) 185 /** List of valid pin to peripheral connections for the pass_gpio_01_aio signal. */ 186 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_gpio_01_aio[1]; 187 /** Indicates that a pin map exists for pass_mcpass_dclk*/ 188 #define CYHAL_PIN_MAP_DRIVE_MODE_PASS_MCPASS_DCLK (CY_GPIO_DM_STRONG_IN_OFF) 189 /** List of valid pin to peripheral connections for the pass_mcpass_dclk signal. */ 190 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_mcpass_dclk[1]; 191 /** Indicates that a pin map exists for pass_mcpass_dout*/ 192 #define CYHAL_PIN_MAP_DRIVE_MODE_PASS_MCPASS_DOUT (CY_GPIO_DM_STRONG_IN_OFF) 193 /** List of valid pin to peripheral connections for the pass_mcpass_dout signal. */ 194 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_mcpass_dout[7]; 195 /** Indicates that a pin map exists for peri_tr_io_input*/ 196 #define CYHAL_PIN_MAP_DRIVE_MODE_PERI_TR_IO_INPUT (CY_GPIO_DM_HIGHZ) 197 /** List of valid pin to peripheral connections for the peri_tr_io_input signal. */ 198 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[29]; 199 /** Indicates that a pin map exists for peri_tr_io_output*/ 200 #define CYHAL_PIN_MAP_DRIVE_MODE_PERI_TR_IO_OUTPUT (CY_GPIO_DM_HIGHZ) 201 /** List of valid pin to peripheral connections for the peri_tr_io_output signal. */ 202 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[59]; 203 /** Indicates that a pin map exists for scb_i2c_scl*/ 204 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_I2C_SCL (CY_GPIO_DM_OD_DRIVESLOW) 205 /** List of valid pin to peripheral connections for the scb_i2c_scl signal. */ 206 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[7]; 207 /** Indicates that a pin map exists for scb_i2c_sda*/ 208 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_I2C_SDA (CY_GPIO_DM_OD_DRIVESLOW) 209 /** List of valid pin to peripheral connections for the scb_i2c_sda signal. */ 210 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[7]; 211 /** Indicates that a pin map exists for scb_spi_m_clk*/ 212 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_CLK (CY_GPIO_DM_STRONG_IN_OFF) 213 /** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */ 214 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[6]; 215 /** Indicates that a pin map exists for scb_spi_m_miso*/ 216 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_MISO (CY_GPIO_DM_HIGHZ) 217 /** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */ 218 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[7]; 219 /** Indicates that a pin map exists for scb_spi_m_mosi*/ 220 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_MOSI (CY_GPIO_DM_STRONG_IN_OFF) 221 /** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */ 222 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[7]; 223 /** Indicates that a pin map exists for scb_spi_m_select0*/ 224 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT0 (CY_GPIO_DM_STRONG_IN_OFF) 225 /** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */ 226 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[4]; 227 /** Indicates that a pin map exists for scb_spi_m_select1*/ 228 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT1 (CY_GPIO_DM_STRONG_IN_OFF) 229 /** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */ 230 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[1]; 231 /** Indicates that a pin map exists for scb_spi_m_select2*/ 232 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT2 (CY_GPIO_DM_STRONG_IN_OFF) 233 /** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */ 234 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[1]; 235 /** Indicates that a pin map exists for scb_spi_s_clk*/ 236 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_CLK (CY_GPIO_DM_HIGHZ) 237 /** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */ 238 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[6]; 239 /** Indicates that a pin map exists for scb_spi_s_miso*/ 240 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_MISO (CY_GPIO_DM_STRONG_IN_OFF) 241 /** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */ 242 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[7]; 243 /** Indicates that a pin map exists for scb_spi_s_mosi*/ 244 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_MOSI (CY_GPIO_DM_HIGHZ) 245 /** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */ 246 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[7]; 247 /** Indicates that a pin map exists for scb_spi_s_select0*/ 248 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT0 (CY_GPIO_DM_HIGHZ) 249 /** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */ 250 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[4]; 251 /** Indicates that a pin map exists for scb_spi_s_select1*/ 252 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT1 (CY_GPIO_DM_HIGHZ) 253 /** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */ 254 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[1]; 255 /** Indicates that a pin map exists for scb_spi_s_select2*/ 256 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT2 (CY_GPIO_DM_HIGHZ) 257 /** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */ 258 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[1]; 259 /** Indicates that a pin map exists for scb_uart_cts*/ 260 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_CTS (CY_GPIO_DM_HIGHZ) 261 /** List of valid pin to peripheral connections for the scb_uart_cts signal. */ 262 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[6]; 263 /** Indicates that a pin map exists for scb_uart_rts*/ 264 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_RTS (CY_GPIO_DM_STRONG_IN_OFF) 265 /** List of valid pin to peripheral connections for the scb_uart_rts signal. */ 266 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[4]; 267 /** Indicates that a pin map exists for scb_uart_rx*/ 268 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_RX (CY_GPIO_DM_HIGHZ) 269 /** List of valid pin to peripheral connections for the scb_uart_rx signal. */ 270 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[7]; 271 /** Indicates that a pin map exists for scb_uart_tx*/ 272 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_TX (CY_GPIO_DM_STRONG_IN_OFF) 273 /** List of valid pin to peripheral connections for the scb_uart_tx signal. */ 274 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[7]; 275 /** Indicates that a pin map exists for tcpwm_line*/ 276 #define CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_LINE (CY_GPIO_DM_STRONG_IN_OFF) 277 /** List of valid pin to peripheral connections for the tcpwm_line signal. */ 278 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[14]; 279 /** Indicates that a pin map exists for tcpwm_line_compl*/ 280 #define CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_LINE_COMPL (CY_GPIO_DM_STRONG_IN_OFF) 281 /** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */ 282 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[12]; 283 284 #if defined(__cplusplus) 285 } 286 #endif /* __cplusplus */ 287 288 /** \} group_hal_impl_pin_package */ 289 290 #endif /* _CYHAL_PSC3_VQFN_48_H_ */ 291 292 293 /* [] END OF FILE */ 294
