/***************************************************************************//** * \file cyhal_psc3_vqfn_48.h * * \brief * PSC3 device GPIO HAL header for VQFN-48 package * ******************************************************************************** * \copyright * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or * an affiliate of Cypress Semiconductor Corporation. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. *******************************************************************************/ #ifndef _CYHAL_PSC3_VQFN_48_H_ #define _CYHAL_PSC3_VQFN_48_H_ #include "cyhal_hw_resources.h" /** * \addtogroup group_hal_impl_pin_package_psc3_vqfn_48 PSC3 VQFN-48 * \ingroup group_hal_impl_pin_package * \{ * Pin definitions and connections specific to the PSC3 VQFN-48 package. */ #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ /** Gets a pin definition from the provided port and pin numbers */ #define CYHAL_GET_GPIO(port, pin) ((((uint8_t)(port)) << 3U) + ((uint8_t)(pin))) /** Macro that, given a gpio, will extract the pin number */ #define CYHAL_GET_PIN(pin) ((uint8_t)(((uint8_t)pin) & 0x07U)) /** Macro that, given a gpio, will extract the port number */ #define CYHAL_GET_PORT(pin) ((uint8_t)(((uint8_t)pin) >> 3U)) /** Definitions for all of the pins that are bonded out on in the VQFN-48 package for the PSC3 series. */ typedef enum { NC = 0xFF, //!< No Connect/Invalid Pin P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0 P1_2 = CYHAL_GET_GPIO(CYHAL_PORT_1, 2), //!< Port 1 Pin 2 P1_3 = CYHAL_GET_GPIO(CYHAL_PORT_1, 3), //!< Port 1 Pin 3 P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0), //!< Port 2 Pin 0 P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1), //!< Port 2 Pin 1 P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2), //!< Port 2 Pin 2 P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3), //!< Port 2 Pin 3 P4_0 = CYHAL_GET_GPIO(CYHAL_PORT_4, 0), //!< Port 4 Pin 0 P4_1 = CYHAL_GET_GPIO(CYHAL_PORT_4, 1), //!< Port 4 Pin 1 P4_2 = CYHAL_GET_GPIO(CYHAL_PORT_4, 2), //!< Port 4 Pin 2 P4_3 = CYHAL_GET_GPIO(CYHAL_PORT_4, 3), //!< Port 4 Pin 3 P4_4 = CYHAL_GET_GPIO(CYHAL_PORT_4, 4), //!< Port 4 Pin 4 P4_5 = CYHAL_GET_GPIO(CYHAL_PORT_4, 5), //!< Port 4 Pin 5 P4_6 = CYHAL_GET_GPIO(CYHAL_PORT_4, 6), //!< Port 4 Pin 6 P4_7 = CYHAL_GET_GPIO(CYHAL_PORT_4, 7), //!< Port 4 Pin 7 P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), //!< Port 6 Pin 0 P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), //!< Port 6 Pin 1 P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2 P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3 P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0 P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1 P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2 P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), //!< Port 8 Pin 0 P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), //!< Port 8 Pin 1 P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), //!< Port 8 Pin 2 P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), //!< Port 8 Pin 3 P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0 P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2 P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3 AN_A0 = CYHAL_GET_GPIO(NC, 0), //!< AN_A Pin 0 AN_A1 = CYHAL_GET_GPIO(NC, 1), //!< AN_A Pin 1 AN_A2 = CYHAL_GET_GPIO(NC, 2), //!< AN_A Pin 2 AN_A3 = CYHAL_GET_GPIO(NC, 3), //!< AN_A Pin 3 AN_A4 = CYHAL_GET_GPIO(NC, 4), //!< AN_A Pin 4 AN_A5 = CYHAL_GET_GPIO(NC, 5), //!< AN_A Pin 5 AN_B1 = CYHAL_GET_GPIO(NC, 9), //!< AN_B Pin 1 AN_B2 = CYHAL_GET_GPIO(NC, 10), //!< AN_B Pin 2 AN_B3 = CYHAL_GET_GPIO(NC, 11), //!< AN_B Pin 3 AN_B4 = CYHAL_GET_GPIO(NC, 12), //!< AN_B Pin 4 } cyhal_gpio_psc3_vqfn_48_t; /** Create generic name for the series/package specific type. */ typedef cyhal_gpio_psc3_vqfn_48_t cyhal_gpio_t; /* Connection type definition */ /** Represents an association between a pin and a resource */ typedef struct { uint8_t block_num; //!< The block number of the resource with this connection uint8_t channel_num; //!< The channel number of the block with this connection cyhal_gpio_t pin; //!< The GPIO pin the connection is with en_hsiom_sel_t hsiom; //!< The HSIOM configuration value } cyhal_resource_pin_mapping_t; /* Pin connections */ /** Indicates that a pin map exists for canfd_ttcan_rx*/ #define CYHAL_PIN_MAP_DRIVE_MODE_CANFD_TTCAN_RX (CY_GPIO_DM_HIGHZ) /** List of valid pin to peripheral connections for the canfd_ttcan_rx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_rx[3]; /** Indicates that a pin map exists for canfd_ttcan_tx*/ #define CYHAL_PIN_MAP_DRIVE_MODE_CANFD_TTCAN_TX (CY_GPIO_DM_STRONG_IN_OFF) /** List of valid pin to peripheral connections for the canfd_ttcan_tx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_tx[3]; /** Indicates that a pin map exists for cpuss_clk_fm_pump*/ #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_CLK_FM_PUMP (CY_GPIO_DM_STRONG_IN_OFF) /** List of valid pin to peripheral connections for the cpuss_clk_fm_pump signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_clk_fm_pump[1]; /** Indicates that a pin map exists for cpuss_fault*/ #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_FAULT (CY_GPIO_DM_STRONG_IN_OFF) /** List of valid pin to peripheral connections for the cpuss_fault signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_fault[2]; /** Indicates that a pin map exists for debug600_clk_swj_swclk_tclk*/ #define CYHAL_PIN_MAP_DRIVE_MODE_DEBUG600_CLK_SWJ_SWCLK_TCLK (CY_GPIO_DM_PULLDOWN) /** List of valid pin to peripheral connections for the debug600_clk_swj_swclk_tclk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_debug600_clk_swj_swclk_tclk[1]; /** Indicates that a pin map exists for debug600_rst_swj_trstn*/ #define CYHAL_PIN_MAP_DRIVE_MODE_DEBUG600_RST_SWJ_TRSTN (CY_GPIO_DM_PULLDOWN) /** List of valid pin to peripheral connections for the debug600_rst_swj_trstn signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_debug600_rst_swj_trstn[1]; /** Indicates that a pin map exists for debug600_swj_swdio_tms*/ #define CYHAL_PIN_MAP_DRIVE_MODE_DEBUG600_SWJ_SWDIO_TMS (CY_GPIO_DM_PULLUP) /** List of valid pin to peripheral connections for the debug600_swj_swdio_tms signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_debug600_swj_swdio_tms[1]; /** Indicates that a pin map exists for debug600_swj_swdoe_tdi*/ #define CYHAL_PIN_MAP_DRIVE_MODE_DEBUG600_SWJ_SWDOE_TDI (CY_GPIO_DM_PULLUP) /** List of valid pin to peripheral connections for the debug600_swj_swdoe_tdi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_debug600_swj_swdoe_tdi[1]; /** Indicates that a pin map exists for debug600_swj_swo_tdo*/ #define CYHAL_PIN_MAP_DRIVE_MODE_DEBUG600_SWJ_SWO_TDO (CY_GPIO_DM_STRONG_IN_OFF) /** List of valid pin to peripheral connections for the debug600_swj_swo_tdo signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_debug600_swj_swo_tdo[1]; /** Indicates that a pin map exists for debug600_trace_clock*/ #define CYHAL_PIN_MAP_DRIVE_MODE_DEBUG600_TRACE_CLOCK (CY_GPIO_DM_STRONG_IN_OFF) /** List of valid pin to peripheral connections for the debug600_trace_clock signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_debug600_trace_clock[1]; /** Indicates that a pin map exists for debug600_trace_data*/ #define CYHAL_PIN_MAP_DRIVE_MODE_DEBUG600_TRACE_DATA (CY_GPIO_DM_STRONG_IN_OFF) /** List of valid pin to peripheral connections for the debug600_trace_data signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_debug600_trace_data[7]; /** Indicates that a pin map exists for lpcomp_inn_comp*/ #define CYHAL_PIN_MAP_DRIVE_MODE_LPCOMP_INN_COMP (CY_GPIO_DM_ANALOG) /** List of valid pin to peripheral connections for the lpcomp_inn_comp signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp[2]; /** Indicates that a pin map exists for lpcomp_inp_comp*/ #define CYHAL_PIN_MAP_DRIVE_MODE_LPCOMP_INP_COMP (CY_GPIO_DM_ANALOG) /** List of valid pin to peripheral connections for the lpcomp_inp_comp signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp[2]; /** Indicates that a pin map exists for pass_an_a_pad_aio*/ #define CYHAL_PIN_MAP_DRIVE_MODE_PASS_AN_A_PAD_AIO (CY_GPIO_DM_HIGHZ) /** List of valid pin to peripheral connections for the pass_an_a_pad_aio signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_an_a_pad_aio[6]; /** Indicates that a pin map exists for pass_an_b_pad_aio*/ #define CYHAL_PIN_MAP_DRIVE_MODE_PASS_AN_B_PAD_AIO (CY_GPIO_DM_HIGHZ) /** List of valid pin to peripheral connections for the pass_an_b_pad_aio signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_an_b_pad_aio[4]; /** Indicates that a pin map exists for pass_gpio_00_aio*/ #define CYHAL_PIN_MAP_DRIVE_MODE_PASS_GPIO_00_AIO (CY_GPIO_DM_ANALOG) /** List of valid pin to peripheral connections for the pass_gpio_00_aio signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_gpio_00_aio[1]; /** Indicates that a pin map exists for pass_gpio_01_aio*/ #define CYHAL_PIN_MAP_DRIVE_MODE_PASS_GPIO_01_AIO (CY_GPIO_DM_ANALOG) /** List of valid pin to peripheral connections for the pass_gpio_01_aio signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_gpio_01_aio[1]; /** Indicates that a pin map exists for pass_mcpass_dclk*/ #define CYHAL_PIN_MAP_DRIVE_MODE_PASS_MCPASS_DCLK (CY_GPIO_DM_STRONG_IN_OFF) /** List of valid pin to peripheral connections for the pass_mcpass_dclk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_mcpass_dclk[1]; /** Indicates that a pin map exists for pass_mcpass_dout*/ #define CYHAL_PIN_MAP_DRIVE_MODE_PASS_MCPASS_DOUT (CY_GPIO_DM_STRONG_IN_OFF) /** List of valid pin to peripheral connections for the pass_mcpass_dout signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_mcpass_dout[7]; /** Indicates that a pin map exists for peri_tr_io_input*/ #define CYHAL_PIN_MAP_DRIVE_MODE_PERI_TR_IO_INPUT (CY_GPIO_DM_HIGHZ) /** List of valid pin to peripheral connections for the peri_tr_io_input signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[29]; /** Indicates that a pin map exists for peri_tr_io_output*/ #define CYHAL_PIN_MAP_DRIVE_MODE_PERI_TR_IO_OUTPUT (CY_GPIO_DM_HIGHZ) /** List of valid pin to peripheral connections for the peri_tr_io_output signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[59]; /** Indicates that a pin map exists for scb_i2c_scl*/ #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_I2C_SCL (CY_GPIO_DM_OD_DRIVESLOW) /** List of valid pin to peripheral connections for the scb_i2c_scl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[7]; /** Indicates that a pin map exists for scb_i2c_sda*/ #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_I2C_SDA (CY_GPIO_DM_OD_DRIVESLOW) /** List of valid pin to peripheral connections for the scb_i2c_sda signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[7]; /** Indicates that a pin map exists for scb_spi_m_clk*/ #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_CLK (CY_GPIO_DM_STRONG_IN_OFF) /** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[6]; /** Indicates that a pin map exists for scb_spi_m_miso*/ #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_MISO (CY_GPIO_DM_HIGHZ) /** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[7]; /** Indicates that a pin map exists for scb_spi_m_mosi*/ #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_MOSI (CY_GPIO_DM_STRONG_IN_OFF) /** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[7]; /** Indicates that a pin map exists for scb_spi_m_select0*/ #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT0 (CY_GPIO_DM_STRONG_IN_OFF) /** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[4]; /** Indicates that a pin map exists for scb_spi_m_select1*/ #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT1 (CY_GPIO_DM_STRONG_IN_OFF) /** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[1]; /** Indicates that a pin map exists for scb_spi_m_select2*/ #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT2 (CY_GPIO_DM_STRONG_IN_OFF) /** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[1]; /** Indicates that a pin map exists for scb_spi_s_clk*/ #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_CLK (CY_GPIO_DM_HIGHZ) /** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[6]; /** Indicates that a pin map exists for scb_spi_s_miso*/ #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_MISO (CY_GPIO_DM_STRONG_IN_OFF) /** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[7]; /** Indicates that a pin map exists for scb_spi_s_mosi*/ #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_MOSI (CY_GPIO_DM_HIGHZ) /** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[7]; /** Indicates that a pin map exists for scb_spi_s_select0*/ #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT0 (CY_GPIO_DM_HIGHZ) /** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[4]; /** Indicates that a pin map exists for scb_spi_s_select1*/ #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT1 (CY_GPIO_DM_HIGHZ) /** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[1]; /** Indicates that a pin map exists for scb_spi_s_select2*/ #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT2 (CY_GPIO_DM_HIGHZ) /** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[1]; /** Indicates that a pin map exists for scb_uart_cts*/ #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_CTS (CY_GPIO_DM_HIGHZ) /** List of valid pin to peripheral connections for the scb_uart_cts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[6]; /** Indicates that a pin map exists for scb_uart_rts*/ #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_RTS (CY_GPIO_DM_STRONG_IN_OFF) /** List of valid pin to peripheral connections for the scb_uart_rts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[4]; /** Indicates that a pin map exists for scb_uart_rx*/ #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_RX (CY_GPIO_DM_HIGHZ) /** List of valid pin to peripheral connections for the scb_uart_rx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[7]; /** Indicates that a pin map exists for scb_uart_tx*/ #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_TX (CY_GPIO_DM_STRONG_IN_OFF) /** List of valid pin to peripheral connections for the scb_uart_tx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[7]; /** Indicates that a pin map exists for tcpwm_line*/ #define CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_LINE (CY_GPIO_DM_STRONG_IN_OFF) /** List of valid pin to peripheral connections for the tcpwm_line signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[14]; /** Indicates that a pin map exists for tcpwm_line_compl*/ #define CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_LINE_COMPL (CY_GPIO_DM_STRONG_IN_OFF) /** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[12]; #if defined(__cplusplus) } #endif /* __cplusplus */ /** \} group_hal_impl_pin_package */ #endif /* _CYHAL_PSC3_VQFN_48_H_ */ /* [] END OF FILE */