1 /*
2  * Autogenerated file
3  *
4  * SPDX-License-Identifier: Apache 2.0
5  */
6 
7 #include "gd32f403xx-afio.h"
8 
9 /* ADC012_IN0 */
10 #define ADC012_IN0_PA0 \
11 	GD32_PINMUX_AFIO('A', 0, ANALOG, NORMP)
12 
13 /* ADC012_IN1 */
14 #define ADC012_IN1_PA1 \
15 	GD32_PINMUX_AFIO('A', 1, ANALOG, NORMP)
16 
17 /* ADC012_IN10 */
18 #define ADC012_IN10_PC0 \
19 	GD32_PINMUX_AFIO('C', 0, ANALOG, NORMP)
20 
21 /* ADC012_IN11 */
22 #define ADC012_IN11_PC1 \
23 	GD32_PINMUX_AFIO('C', 1, ANALOG, NORMP)
24 
25 /* ADC012_IN12 */
26 #define ADC012_IN12_PC2 \
27 	GD32_PINMUX_AFIO('C', 2, ANALOG, NORMP)
28 
29 /* ADC012_IN13 */
30 #define ADC012_IN13_PC3 \
31 	GD32_PINMUX_AFIO('C', 3, ANALOG, NORMP)
32 
33 /* ADC012_IN2 */
34 #define ADC012_IN2_PA2 \
35 	GD32_PINMUX_AFIO('A', 2, ANALOG, NORMP)
36 
37 /* ADC012_IN3 */
38 #define ADC012_IN3_PA3 \
39 	GD32_PINMUX_AFIO('A', 3, ANALOG, NORMP)
40 
41 /* ADC01_IN14 */
42 #define ADC01_IN14_PC4 \
43 	GD32_PINMUX_AFIO('C', 4, ANALOG, NORMP)
44 
45 /* ADC01_IN15 */
46 #define ADC01_IN15_PC5 \
47 	GD32_PINMUX_AFIO('C', 5, ANALOG, NORMP)
48 
49 /* ADC01_IN4 */
50 #define ADC01_IN4_PA4 \
51 	GD32_PINMUX_AFIO('A', 4, ANALOG, NORMP)
52 
53 /* ADC01_IN5 */
54 #define ADC01_IN5_PA5 \
55 	GD32_PINMUX_AFIO('A', 5, ANALOG, NORMP)
56 
57 /* ADC01_IN6 */
58 #define ADC01_IN6_PA6 \
59 	GD32_PINMUX_AFIO('A', 6, ANALOG, NORMP)
60 
61 /* ADC01_IN7 */
62 #define ADC01_IN7_PA7 \
63 	GD32_PINMUX_AFIO('A', 7, ANALOG, NORMP)
64 
65 /* ADC01_IN8 */
66 #define ADC01_IN8_PB0 \
67 	GD32_PINMUX_AFIO('B', 0, ANALOG, NORMP)
68 
69 /* ADC01_IN9 */
70 #define ADC01_IN9_PB1 \
71 	GD32_PINMUX_AFIO('B', 1, ANALOG, NORMP)
72 
73 /* ANALOG */
74 #define ANALOG_PA0 \
75 	GD32_PINMUX_AFIO('A', 0, ANALOG, NORMP)
76 #define ANALOG_PA1 \
77 	GD32_PINMUX_AFIO('A', 1, ANALOG, NORMP)
78 #define ANALOG_PA2 \
79 	GD32_PINMUX_AFIO('A', 2, ANALOG, NORMP)
80 #define ANALOG_PA3 \
81 	GD32_PINMUX_AFIO('A', 3, ANALOG, NORMP)
82 #define ANALOG_PA4 \
83 	GD32_PINMUX_AFIO('A', 4, ANALOG, NORMP)
84 #define ANALOG_PA5 \
85 	GD32_PINMUX_AFIO('A', 5, ANALOG, NORMP)
86 #define ANALOG_PA6 \
87 	GD32_PINMUX_AFIO('A', 6, ANALOG, NORMP)
88 #define ANALOG_PA7 \
89 	GD32_PINMUX_AFIO('A', 7, ANALOG, NORMP)
90 #define ANALOG_PA8 \
91 	GD32_PINMUX_AFIO('A', 8, ANALOG, NORMP)
92 #define ANALOG_PA9 \
93 	GD32_PINMUX_AFIO('A', 9, ANALOG, NORMP)
94 #define ANALOG_PA10 \
95 	GD32_PINMUX_AFIO('A', 10, ANALOG, NORMP)
96 #define ANALOG_PA11 \
97 	GD32_PINMUX_AFIO('A', 11, ANALOG, NORMP)
98 #define ANALOG_PA12 \
99 	GD32_PINMUX_AFIO('A', 12, ANALOG, NORMP)
100 #define ANALOG_PA13 \
101 	GD32_PINMUX_AFIO('A', 13, ANALOG, NORMP)
102 #define ANALOG_PA14 \
103 	GD32_PINMUX_AFIO('A', 14, ANALOG, NORMP)
104 #define ANALOG_PA15 \
105 	GD32_PINMUX_AFIO('A', 15, ANALOG, NORMP)
106 #define ANALOG_PB0 \
107 	GD32_PINMUX_AFIO('B', 0, ANALOG, NORMP)
108 #define ANALOG_PB1 \
109 	GD32_PINMUX_AFIO('B', 1, ANALOG, NORMP)
110 #define ANALOG_PB2 \
111 	GD32_PINMUX_AFIO('B', 2, ANALOG, NORMP)
112 #define ANALOG_PB3 \
113 	GD32_PINMUX_AFIO('B', 3, ANALOG, NORMP)
114 #define ANALOG_PB4 \
115 	GD32_PINMUX_AFIO('B', 4, ANALOG, NORMP)
116 #define ANALOG_PB5 \
117 	GD32_PINMUX_AFIO('B', 5, ANALOG, NORMP)
118 #define ANALOG_PB6 \
119 	GD32_PINMUX_AFIO('B', 6, ANALOG, NORMP)
120 #define ANALOG_PB7 \
121 	GD32_PINMUX_AFIO('B', 7, ANALOG, NORMP)
122 #define ANALOG_PB8 \
123 	GD32_PINMUX_AFIO('B', 8, ANALOG, NORMP)
124 #define ANALOG_PB9 \
125 	GD32_PINMUX_AFIO('B', 9, ANALOG, NORMP)
126 #define ANALOG_PB10 \
127 	GD32_PINMUX_AFIO('B', 10, ANALOG, NORMP)
128 #define ANALOG_PB11 \
129 	GD32_PINMUX_AFIO('B', 11, ANALOG, NORMP)
130 #define ANALOG_PB12 \
131 	GD32_PINMUX_AFIO('B', 12, ANALOG, NORMP)
132 #define ANALOG_PB13 \
133 	GD32_PINMUX_AFIO('B', 13, ANALOG, NORMP)
134 #define ANALOG_PB14 \
135 	GD32_PINMUX_AFIO('B', 14, ANALOG, NORMP)
136 #define ANALOG_PB15 \
137 	GD32_PINMUX_AFIO('B', 15, ANALOG, NORMP)
138 #define ANALOG_PC0 \
139 	GD32_PINMUX_AFIO('C', 0, ANALOG, NORMP)
140 #define ANALOG_PC1 \
141 	GD32_PINMUX_AFIO('C', 1, ANALOG, NORMP)
142 #define ANALOG_PC2 \
143 	GD32_PINMUX_AFIO('C', 2, ANALOG, NORMP)
144 #define ANALOG_PC3 \
145 	GD32_PINMUX_AFIO('C', 3, ANALOG, NORMP)
146 #define ANALOG_PC4 \
147 	GD32_PINMUX_AFIO('C', 4, ANALOG, NORMP)
148 #define ANALOG_PC5 \
149 	GD32_PINMUX_AFIO('C', 5, ANALOG, NORMP)
150 #define ANALOG_PC6 \
151 	GD32_PINMUX_AFIO('C', 6, ANALOG, NORMP)
152 #define ANALOG_PC7 \
153 	GD32_PINMUX_AFIO('C', 7, ANALOG, NORMP)
154 #define ANALOG_PC8 \
155 	GD32_PINMUX_AFIO('C', 8, ANALOG, NORMP)
156 #define ANALOG_PC9 \
157 	GD32_PINMUX_AFIO('C', 9, ANALOG, NORMP)
158 #define ANALOG_PC10 \
159 	GD32_PINMUX_AFIO('C', 10, ANALOG, NORMP)
160 #define ANALOG_PC11 \
161 	GD32_PINMUX_AFIO('C', 11, ANALOG, NORMP)
162 #define ANALOG_PC12 \
163 	GD32_PINMUX_AFIO('C', 12, ANALOG, NORMP)
164 #define ANALOG_PC13 \
165 	GD32_PINMUX_AFIO('C', 13, ANALOG, NORMP)
166 #define ANALOG_PC14 \
167 	GD32_PINMUX_AFIO('C', 14, ANALOG, NORMP)
168 #define ANALOG_PC15 \
169 	GD32_PINMUX_AFIO('C', 15, ANALOG, NORMP)
170 #define ANALOG_PD0 \
171 	GD32_PINMUX_AFIO('D', 0, ANALOG, NORMP)
172 #define ANALOG_PD1 \
173 	GD32_PINMUX_AFIO('D', 1, ANALOG, NORMP)
174 #define ANALOG_PD2 \
175 	GD32_PINMUX_AFIO('D', 2, ANALOG, NORMP)
176 #define ANALOG_PD3 \
177 	GD32_PINMUX_AFIO('D', 3, ANALOG, NORMP)
178 #define ANALOG_PD4 \
179 	GD32_PINMUX_AFIO('D', 4, ANALOG, NORMP)
180 #define ANALOG_PD5 \
181 	GD32_PINMUX_AFIO('D', 5, ANALOG, NORMP)
182 #define ANALOG_PD6 \
183 	GD32_PINMUX_AFIO('D', 6, ANALOG, NORMP)
184 #define ANALOG_PD7 \
185 	GD32_PINMUX_AFIO('D', 7, ANALOG, NORMP)
186 #define ANALOG_PD8 \
187 	GD32_PINMUX_AFIO('D', 8, ANALOG, NORMP)
188 #define ANALOG_PD9 \
189 	GD32_PINMUX_AFIO('D', 9, ANALOG, NORMP)
190 #define ANALOG_PD10 \
191 	GD32_PINMUX_AFIO('D', 10, ANALOG, NORMP)
192 #define ANALOG_PD11 \
193 	GD32_PINMUX_AFIO('D', 11, ANALOG, NORMP)
194 #define ANALOG_PD12 \
195 	GD32_PINMUX_AFIO('D', 12, ANALOG, NORMP)
196 #define ANALOG_PD13 \
197 	GD32_PINMUX_AFIO('D', 13, ANALOG, NORMP)
198 #define ANALOG_PD14 \
199 	GD32_PINMUX_AFIO('D', 14, ANALOG, NORMP)
200 #define ANALOG_PD15 \
201 	GD32_PINMUX_AFIO('D', 15, ANALOG, NORMP)
202 #define ANALOG_PE0 \
203 	GD32_PINMUX_AFIO('E', 0, ANALOG, NORMP)
204 #define ANALOG_PE1 \
205 	GD32_PINMUX_AFIO('E', 1, ANALOG, NORMP)
206 #define ANALOG_PE2 \
207 	GD32_PINMUX_AFIO('E', 2, ANALOG, NORMP)
208 #define ANALOG_PE3 \
209 	GD32_PINMUX_AFIO('E', 3, ANALOG, NORMP)
210 #define ANALOG_PE4 \
211 	GD32_PINMUX_AFIO('E', 4, ANALOG, NORMP)
212 #define ANALOG_PE5 \
213 	GD32_PINMUX_AFIO('E', 5, ANALOG, NORMP)
214 #define ANALOG_PE6 \
215 	GD32_PINMUX_AFIO('E', 6, ANALOG, NORMP)
216 #define ANALOG_PE7 \
217 	GD32_PINMUX_AFIO('E', 7, ANALOG, NORMP)
218 #define ANALOG_PE8 \
219 	GD32_PINMUX_AFIO('E', 8, ANALOG, NORMP)
220 #define ANALOG_PE9 \
221 	GD32_PINMUX_AFIO('E', 9, ANALOG, NORMP)
222 #define ANALOG_PE10 \
223 	GD32_PINMUX_AFIO('E', 10, ANALOG, NORMP)
224 #define ANALOG_PE11 \
225 	GD32_PINMUX_AFIO('E', 11, ANALOG, NORMP)
226 #define ANALOG_PE12 \
227 	GD32_PINMUX_AFIO('E', 12, ANALOG, NORMP)
228 #define ANALOG_PE13 \
229 	GD32_PINMUX_AFIO('E', 13, ANALOG, NORMP)
230 #define ANALOG_PE14 \
231 	GD32_PINMUX_AFIO('E', 14, ANALOG, NORMP)
232 #define ANALOG_PE15 \
233 	GD32_PINMUX_AFIO('E', 15, ANALOG, NORMP)
234 
235 /* CAN0_RX */
236 #define CAN0_RX_PA11_NORMP \
237 	GD32_PINMUX_AFIO('A', 11, GPIO_IN, CAN0_NORMP)
238 #define CAN0_RX_PB8_PRMP \
239 	GD32_PINMUX_AFIO('B', 8, GPIO_IN, CAN0_PRMP)
240 #define CAN0_RX_PD0_FRMP \
241 	GD32_PINMUX_AFIO('D', 0, GPIO_IN, CAN0_FRMP)
242 
243 /* CAN0_TX */
244 #define CAN0_TX_PA12_NORMP \
245 	GD32_PINMUX_AFIO('A', 12, ALTERNATE, CAN0_NORMP)
246 #define CAN0_TX_PB9_PRMP \
247 	GD32_PINMUX_AFIO('B', 9, ALTERNATE, CAN0_PRMP)
248 #define CAN0_TX_PD1_FRMP \
249 	GD32_PINMUX_AFIO('D', 1, ALTERNATE, CAN0_FRMP)
250 
251 /* CAN1_RX */
252 #define CAN1_RX_PB12_NORMP \
253 	GD32_PINMUX_AFIO('B', 12, GPIO_IN, CAN1_NORMP)
254 #define CAN1_RX_PB5_RMP \
255 	GD32_PINMUX_AFIO('B', 5, GPIO_IN, CAN1_RMP)
256 
257 /* CAN1_TX */
258 #define CAN1_TX_PB13_NORMP \
259 	GD32_PINMUX_AFIO('B', 13, ALTERNATE, CAN1_NORMP)
260 #define CAN1_TX_PB6_RMP \
261 	GD32_PINMUX_AFIO('B', 6, ALTERNATE, CAN1_RMP)
262 
263 /* CK_OUT0 */
264 #define CK_OUT0_PA8 \
265 	GD32_PINMUX_AFIO('A', 8, ALTERNATE, NORMP)
266 
267 /* CTC_SYNC */
268 #define CTC_SYNC_PA8_NORMP \
269 	GD32_PINMUX_AFIO('A', 8, ALTERNATE, CTC_NORMP)
270 #define CTC_SYNC_PD15_PRMP \
271 	GD32_PINMUX_AFIO('D', 15, ALTERNATE, CTC_PRMP)
272 
273 /* DAC_OUT0 */
274 #define DAC_OUT0_PA4 \
275 	GD32_PINMUX_AFIO('A', 4, ANALOG, NORMP)
276 
277 /* DAC_OUT1 */
278 #define DAC_OUT1_PA5 \
279 	GD32_PINMUX_AFIO('A', 5, ANALOG, NORMP)
280 
281 /* EXMC_A16 */
282 #define EXMC_A16_PD11 \
283 	GD32_PINMUX_AFIO('D', 11, ALTERNATE, NORMP)
284 
285 /* EXMC_A17 */
286 #define EXMC_A17_PD12 \
287 	GD32_PINMUX_AFIO('D', 12, ALTERNATE, NORMP)
288 
289 /* EXMC_A18 */
290 #define EXMC_A18_PD13 \
291 	GD32_PINMUX_AFIO('D', 13, ALTERNATE, NORMP)
292 
293 /* EXMC_A19 */
294 #define EXMC_A19_PE3 \
295 	GD32_PINMUX_AFIO('E', 3, ALTERNATE, NORMP)
296 
297 /* EXMC_A20 */
298 #define EXMC_A20_PE4 \
299 	GD32_PINMUX_AFIO('E', 4, ALTERNATE, NORMP)
300 
301 /* EXMC_A21 */
302 #define EXMC_A21_PE5 \
303 	GD32_PINMUX_AFIO('E', 5, ALTERNATE, NORMP)
304 
305 /* EXMC_A22 */
306 #define EXMC_A22_PE6 \
307 	GD32_PINMUX_AFIO('E', 6, ALTERNATE, NORMP)
308 
309 /* EXMC_A23 */
310 #define EXMC_A23_PE2 \
311 	GD32_PINMUX_AFIO('E', 2, ALTERNATE, NORMP)
312 
313 /* EXMC_CLK */
314 #define EXMC_CLK_PD3 \
315 	GD32_PINMUX_AFIO('D', 3, ALTERNATE, NORMP)
316 
317 /* EXMC_D0 */
318 #define EXMC_D0_PD14 \
319 	GD32_PINMUX_AFIO('D', 14, ALTERNATE, NORMP)
320 
321 /* EXMC_D1 */
322 #define EXMC_D1_PD15 \
323 	GD32_PINMUX_AFIO('D', 15, ALTERNATE, NORMP)
324 
325 /* EXMC_D10 */
326 #define EXMC_D10_PE13 \
327 	GD32_PINMUX_AFIO('E', 13, ALTERNATE, NORMP)
328 
329 /* EXMC_D11 */
330 #define EXMC_D11_PE14 \
331 	GD32_PINMUX_AFIO('E', 14, ALTERNATE, NORMP)
332 
333 /* EXMC_D12 */
334 #define EXMC_D12_PE15 \
335 	GD32_PINMUX_AFIO('E', 15, ALTERNATE, NORMP)
336 
337 /* EXMC_D13 */
338 #define EXMC_D13_PD8 \
339 	GD32_PINMUX_AFIO('D', 8, ALTERNATE, NORMP)
340 
341 /* EXMC_D14 */
342 #define EXMC_D14_PD9 \
343 	GD32_PINMUX_AFIO('D', 9, ALTERNATE, NORMP)
344 
345 /* EXMC_D15 */
346 #define EXMC_D15_PD10 \
347 	GD32_PINMUX_AFIO('D', 10, ALTERNATE, NORMP)
348 
349 /* EXMC_D2 */
350 #define EXMC_D2_PD0 \
351 	GD32_PINMUX_AFIO('D', 0, ALTERNATE, NORMP)
352 
353 /* EXMC_D3 */
354 #define EXMC_D3_PD1 \
355 	GD32_PINMUX_AFIO('D', 1, ALTERNATE, NORMP)
356 
357 /* EXMC_D4 */
358 #define EXMC_D4_PE7 \
359 	GD32_PINMUX_AFIO('E', 7, ALTERNATE, NORMP)
360 
361 /* EXMC_D5 */
362 #define EXMC_D5_PE8 \
363 	GD32_PINMUX_AFIO('E', 8, ALTERNATE, NORMP)
364 
365 /* EXMC_D6 */
366 #define EXMC_D6_PE9 \
367 	GD32_PINMUX_AFIO('E', 9, ALTERNATE, NORMP)
368 
369 /* EXMC_D7 */
370 #define EXMC_D7_PE10 \
371 	GD32_PINMUX_AFIO('E', 10, ALTERNATE, NORMP)
372 
373 /* EXMC_D8 */
374 #define EXMC_D8_PE11 \
375 	GD32_PINMUX_AFIO('E', 11, ALTERNATE, NORMP)
376 
377 /* EXMC_D9 */
378 #define EXMC_D9_PE12 \
379 	GD32_PINMUX_AFIO('E', 12, ALTERNATE, NORMP)
380 
381 /* EXMC_NADV */
382 #define EXMC_NADV_PB7 \
383 	GD32_PINMUX_AFIO('B', 7, ALTERNATE, NORMP)
384 
385 /* EXMC_NBL0 */
386 #define EXMC_NBL0_PE0 \
387 	GD32_PINMUX_AFIO('E', 0, ALTERNATE, NORMP)
388 
389 /* EXMC_NBL1 */
390 #define EXMC_NBL1_PE1 \
391 	GD32_PINMUX_AFIO('E', 1, ALTERNATE, NORMP)
392 
393 /* EXMC_NCE1 */
394 #define EXMC_NCE1_PD7 \
395 	GD32_PINMUX_AFIO('D', 7, ALTERNATE, NORMP)
396 
397 /* EXMC_NE0 */
398 #define EXMC_NE0_PD7 \
399 	GD32_PINMUX_AFIO('D', 7, ALTERNATE, NORMP)
400 
401 /* EXMC_NOE */
402 #define EXMC_NOE_PD4 \
403 	GD32_PINMUX_AFIO('D', 4, ALTERNATE, NORMP)
404 
405 /* EXMC_NWAIT */
406 #define EXMC_NWAIT_PD6 \
407 	GD32_PINMUX_AFIO('D', 6, GPIO_IN, NORMP)
408 
409 /* EXMC_NWE */
410 #define EXMC_NWE_PD5 \
411 	GD32_PINMUX_AFIO('D', 5, ALTERNATE, NORMP)
412 
413 /* I2C0_SCL */
414 #define I2C0_SCL_PB6_NORMP \
415 	GD32_PINMUX_AFIO('B', 6, ALTERNATE, I2C0_NORMP)
416 #define I2C0_SCL_PB8_RMP \
417 	GD32_PINMUX_AFIO('B', 8, ALTERNATE, I2C0_RMP)
418 
419 /* I2C0_SDA */
420 #define I2C0_SDA_PB7_NORMP \
421 	GD32_PINMUX_AFIO('B', 7, ALTERNATE, I2C0_NORMP)
422 #define I2C0_SDA_PB9_RMP \
423 	GD32_PINMUX_AFIO('B', 9, ALTERNATE, I2C0_RMP)
424 
425 /* I2C0_SMBA */
426 #define I2C0_SMBA_PB5 \
427 	GD32_PINMUX_AFIO('B', 5, ALTERNATE, NORMP)
428 
429 /* I2C1_SCL */
430 #define I2C1_SCL_PB10 \
431 	GD32_PINMUX_AFIO('B', 10, ALTERNATE, NORMP)
432 
433 /* I2C1_SDA */
434 #define I2C1_SDA_PB11 \
435 	GD32_PINMUX_AFIO('B', 11, ALTERNATE, NORMP)
436 
437 /* I2C1_SMBA */
438 #define I2C1_SMBA_PB12 \
439 	GD32_PINMUX_AFIO('B', 12, ALTERNATE, NORMP)
440 
441 /* I2S1_CK */
442 #define I2S1_CK_PB13_INP \
443 	GD32_PINMUX_AFIO('B', 13, GPIO_IN, NORMP)
444 #define I2S1_CK_PB13_OUT \
445 	GD32_PINMUX_AFIO('B', 13, ALTERNATE, NORMP)
446 
447 /* I2S1_MCK */
448 #define I2S1_MCK_PC6 \
449 	GD32_PINMUX_AFIO('C', 6, ALTERNATE, NORMP)
450 
451 /* I2S1_SD */
452 #define I2S1_SD_PB15_INP \
453 	GD32_PINMUX_AFIO('B', 15, GPIO_IN, NORMP)
454 #define I2S1_SD_PB15_OUT \
455 	GD32_PINMUX_AFIO('B', 15, ALTERNATE, NORMP)
456 
457 /* I2S1_WS */
458 #define I2S1_WS_PB12_INP \
459 	GD32_PINMUX_AFIO('B', 12, GPIO_IN, NORMP)
460 #define I2S1_WS_PB12_OUT \
461 	GD32_PINMUX_AFIO('B', 12, ALTERNATE, NORMP)
462 
463 /* I2S2_CK */
464 #define I2S2_CK_PB3_INP_NORMP \
465 	GD32_PINMUX_AFIO('B', 3, GPIO_IN, I2S2_NORMP)
466 #define I2S2_CK_PB3_OUT_NORMP \
467 	GD32_PINMUX_AFIO('B', 3, ALTERNATE, I2S2_NORMP)
468 #define I2S2_CK_PC10_INP_RMP \
469 	GD32_PINMUX_AFIO('C', 10, GPIO_IN, I2S2_RMP)
470 #define I2S2_CK_PC10_OUT_RMP \
471 	GD32_PINMUX_AFIO('C', 10, ALTERNATE, I2S2_RMP)
472 
473 /* I2S2_MCK */
474 #define I2S2_MCK_PC7 \
475 	GD32_PINMUX_AFIO('C', 7, ALTERNATE, NORMP)
476 
477 /* I2S2_SD */
478 #define I2S2_SD_PB5_INP_NORMP \
479 	GD32_PINMUX_AFIO('B', 5, GPIO_IN, I2S2_NORMP)
480 #define I2S2_SD_PB5_OUT_NORMP \
481 	GD32_PINMUX_AFIO('B', 5, ALTERNATE, I2S2_NORMP)
482 #define I2S2_SD_PC12_INP_RMP \
483 	GD32_PINMUX_AFIO('C', 12, GPIO_IN, I2S2_RMP)
484 #define I2S2_SD_PC12_OUT_RMP \
485 	GD32_PINMUX_AFIO('C', 12, ALTERNATE, I2S2_RMP)
486 
487 /* I2S2_WS */
488 #define I2S2_WS_PA15_INP_NORMP \
489 	GD32_PINMUX_AFIO('A', 15, GPIO_IN, I2S2_NORMP)
490 #define I2S2_WS_PA15_OUT_NORMP \
491 	GD32_PINMUX_AFIO('A', 15, ALTERNATE, I2S2_NORMP)
492 #define I2S2_WS_PA4_INP_RMP \
493 	GD32_PINMUX_AFIO('A', 4, GPIO_IN, I2S2_RMP)
494 #define I2S2_WS_PA4_OUT_RMP \
495 	GD32_PINMUX_AFIO('A', 4, ALTERNATE, I2S2_RMP)
496 
497 /* SDIO_CK */
498 #define SDIO_CK_PC12 \
499 	GD32_PINMUX_AFIO('C', 12, ALTERNATE, NORMP)
500 
501 /* SDIO_D0 */
502 #define SDIO_D0_PC8 \
503 	GD32_PINMUX_AFIO('C', 8, ALTERNATE, NORMP)
504 
505 /* SDIO_D1 */
506 #define SDIO_D1_PC9 \
507 	GD32_PINMUX_AFIO('C', 9, ALTERNATE, NORMP)
508 
509 /* SDIO_D2 */
510 #define SDIO_D2_PC10 \
511 	GD32_PINMUX_AFIO('C', 10, ALTERNATE, NORMP)
512 
513 /* SDIO_D3 */
514 #define SDIO_D3_PC11 \
515 	GD32_PINMUX_AFIO('C', 11, ALTERNATE, NORMP)
516 
517 /* SDIO_D4 */
518 #define SDIO_D4_PB8 \
519 	GD32_PINMUX_AFIO('B', 8, ALTERNATE, NORMP)
520 
521 /* SDIO_D5 */
522 #define SDIO_D5_PB9 \
523 	GD32_PINMUX_AFIO('B', 9, ALTERNATE, NORMP)
524 
525 /* SDIO_D6 */
526 #define SDIO_D6_PC6 \
527 	GD32_PINMUX_AFIO('C', 6, ALTERNATE, NORMP)
528 
529 /* SDIO_D7 */
530 #define SDIO_D7_PC7 \
531 	GD32_PINMUX_AFIO('C', 7, ALTERNATE, NORMP)
532 
533 /* SPI0_IO2 */
534 #define SPI0_IO2_PA2 \
535 	GD32_PINMUX_AFIO('A', 2, ALTERNATE, NORMP)
536 
537 /* SPI0_IO3 */
538 #define SPI0_IO3_PA3 \
539 	GD32_PINMUX_AFIO('A', 3, ALTERNATE, NORMP)
540 
541 /* SPI0_MISO */
542 #define SPI0_MISO_PA6_INP_NORMP \
543 	GD32_PINMUX_AFIO('A', 6, GPIO_IN, SPI0_NORMP)
544 #define SPI0_MISO_PA6_OUT_NORMP \
545 	GD32_PINMUX_AFIO('A', 6, ALTERNATE, SPI0_NORMP)
546 #define SPI0_MISO_PB4_INP_RMP \
547 	GD32_PINMUX_AFIO('B', 4, GPIO_IN, SPI0_RMP)
548 #define SPI0_MISO_PB4_OUT_RMP \
549 	GD32_PINMUX_AFIO('B', 4, ALTERNATE, SPI0_RMP)
550 
551 /* SPI0_MOSI */
552 #define SPI0_MOSI_PA7_INP_NORMP \
553 	GD32_PINMUX_AFIO('A', 7, GPIO_IN, SPI0_NORMP)
554 #define SPI0_MOSI_PA7_OUT_NORMP \
555 	GD32_PINMUX_AFIO('A', 7, ALTERNATE, SPI0_NORMP)
556 #define SPI0_MOSI_PB5_INP_RMP \
557 	GD32_PINMUX_AFIO('B', 5, GPIO_IN, SPI0_RMP)
558 #define SPI0_MOSI_PB5_OUT_RMP \
559 	GD32_PINMUX_AFIO('B', 5, ALTERNATE, SPI0_RMP)
560 
561 /* SPI0_NSS */
562 #define SPI0_NSS_PA4_INP_NORMP \
563 	GD32_PINMUX_AFIO('A', 4, GPIO_IN, SPI0_NORMP)
564 #define SPI0_NSS_PA4_OUT_NORMP \
565 	GD32_PINMUX_AFIO('A', 4, ALTERNATE, SPI0_NORMP)
566 #define SPI0_NSS_PA15_INP_RMP \
567 	GD32_PINMUX_AFIO('A', 15, GPIO_IN, SPI0_RMP)
568 #define SPI0_NSS_PA15_OUT_RMP \
569 	GD32_PINMUX_AFIO('A', 15, ALTERNATE, SPI0_RMP)
570 
571 /* SPI0_SCK */
572 #define SPI0_SCK_PA5_INP_NORMP \
573 	GD32_PINMUX_AFIO('A', 5, GPIO_IN, SPI0_NORMP)
574 #define SPI0_SCK_PA5_OUT_NORMP \
575 	GD32_PINMUX_AFIO('A', 5, ALTERNATE, SPI0_NORMP)
576 #define SPI0_SCK_PB3_INP_RMP \
577 	GD32_PINMUX_AFIO('B', 3, GPIO_IN, SPI0_RMP)
578 #define SPI0_SCK_PB3_OUT_RMP \
579 	GD32_PINMUX_AFIO('B', 3, ALTERNATE, SPI0_RMP)
580 
581 /* SPI1_MISO */
582 #define SPI1_MISO_PB14_INP \
583 	GD32_PINMUX_AFIO('B', 14, GPIO_IN, NORMP)
584 #define SPI1_MISO_PB14_OUT \
585 	GD32_PINMUX_AFIO('B', 14, ALTERNATE, NORMP)
586 
587 /* SPI1_MOSI */
588 #define SPI1_MOSI_PB15_INP \
589 	GD32_PINMUX_AFIO('B', 15, GPIO_IN, NORMP)
590 #define SPI1_MOSI_PB15_OUT \
591 	GD32_PINMUX_AFIO('B', 15, ALTERNATE, NORMP)
592 
593 /* SPI1_NSS */
594 #define SPI1_NSS_PB12_INP \
595 	GD32_PINMUX_AFIO('B', 12, GPIO_IN, NORMP)
596 #define SPI1_NSS_PB12_OUT \
597 	GD32_PINMUX_AFIO('B', 12, ALTERNATE, NORMP)
598 
599 /* SPI1_SCK */
600 #define SPI1_SCK_PB13_INP \
601 	GD32_PINMUX_AFIO('B', 13, GPIO_IN, NORMP)
602 #define SPI1_SCK_PB13_OUT \
603 	GD32_PINMUX_AFIO('B', 13, ALTERNATE, NORMP)
604 
605 /* SPI2_MISO */
606 #define SPI2_MISO_PB4_INP_NORMP \
607 	GD32_PINMUX_AFIO('B', 4, GPIO_IN, SPI2_NORMP)
608 #define SPI2_MISO_PB4_OUT_NORMP \
609 	GD32_PINMUX_AFIO('B', 4, ALTERNATE, SPI2_NORMP)
610 #define SPI2_MISO_PC11_INP_RMP \
611 	GD32_PINMUX_AFIO('C', 11, GPIO_IN, SPI2_RMP)
612 #define SPI2_MISO_PC11_OUT_RMP \
613 	GD32_PINMUX_AFIO('C', 11, ALTERNATE, SPI2_RMP)
614 
615 /* SPI2_MOSI */
616 #define SPI2_MOSI_PB5_INP_NORMP \
617 	GD32_PINMUX_AFIO('B', 5, GPIO_IN, SPI2_NORMP)
618 #define SPI2_MOSI_PB5_OUT_NORMP \
619 	GD32_PINMUX_AFIO('B', 5, ALTERNATE, SPI2_NORMP)
620 #define SPI2_MOSI_PC12_INP_RMP \
621 	GD32_PINMUX_AFIO('C', 12, GPIO_IN, SPI2_RMP)
622 #define SPI2_MOSI_PC12_OUT_RMP \
623 	GD32_PINMUX_AFIO('C', 12, ALTERNATE, SPI2_RMP)
624 
625 /* SPI2_NSS */
626 #define SPI2_NSS_PA15_INP_NORMP \
627 	GD32_PINMUX_AFIO('A', 15, GPIO_IN, SPI2_NORMP)
628 #define SPI2_NSS_PA15_OUT_NORMP \
629 	GD32_PINMUX_AFIO('A', 15, ALTERNATE, SPI2_NORMP)
630 #define SPI2_NSS_PA4_INP_RMP \
631 	GD32_PINMUX_AFIO('A', 4, GPIO_IN, SPI2_RMP)
632 #define SPI2_NSS_PA4_OUT_RMP \
633 	GD32_PINMUX_AFIO('A', 4, ALTERNATE, SPI2_RMP)
634 
635 /* SPI2_SCK */
636 #define SPI2_SCK_PB3_INP_NORMP \
637 	GD32_PINMUX_AFIO('B', 3, GPIO_IN, SPI2_NORMP)
638 #define SPI2_SCK_PB3_OUT_NORMP \
639 	GD32_PINMUX_AFIO('B', 3, ALTERNATE, SPI2_NORMP)
640 #define SPI2_SCK_PC10_INP_RMP \
641 	GD32_PINMUX_AFIO('C', 10, GPIO_IN, SPI2_RMP)
642 #define SPI2_SCK_PC10_OUT_RMP \
643 	GD32_PINMUX_AFIO('C', 10, ALTERNATE, SPI2_RMP)
644 
645 /* TAMPER_RTC */
646 #define TAMPER_RTC_PC13 \
647 	GD32_PINMUX_AFIO('C', 13, GPIO_IN, NORMP)
648 
649 /* TIMER0_BRKIN */
650 #define TIMER0_BRKIN_PB12 \
651 	GD32_PINMUX_AFIO('B', 12, GPIO_IN, NORMP)
652 
653 /* TIMER0_CH0 */
654 #define TIMER0_CH0_PA8_INP_NORMP \
655 	GD32_PINMUX_AFIO('A', 8, GPIO_IN, TIMER0_NORMP)
656 #define TIMER0_CH0_PA8_OUT_NORMP \
657 	GD32_PINMUX_AFIO('A', 8, ALTERNATE, TIMER0_NORMP)
658 #define TIMER0_CH0_PA8_INP_PRMP \
659 	GD32_PINMUX_AFIO('A', 8, GPIO_IN, TIMER0_PRMP)
660 #define TIMER0_CH0_PA8_OUT_PRMP \
661 	GD32_PINMUX_AFIO('A', 8, ALTERNATE, TIMER0_PRMP)
662 #define TIMER0_CH0_PE9_INP_FRMP \
663 	GD32_PINMUX_AFIO('E', 9, GPIO_IN, TIMER0_FRMP)
664 #define TIMER0_CH0_PE9_OUT_FRMP \
665 	GD32_PINMUX_AFIO('E', 9, ALTERNATE, TIMER0_FRMP)
666 
667 /* TIMER0_CH0_ON */
668 #define TIMER0_CH0_ON_PB13_NORMP \
669 	GD32_PINMUX_AFIO('B', 13, ALTERNATE, TIMER0_NORMP)
670 #define TIMER0_CH0_ON_PA7_PRMP \
671 	GD32_PINMUX_AFIO('A', 7, ALTERNATE, TIMER0_PRMP)
672 #define TIMER0_CH0_ON_PE8_FRMP \
673 	GD32_PINMUX_AFIO('E', 8, ALTERNATE, TIMER0_FRMP)
674 
675 /* TIMER0_CH1 */
676 #define TIMER0_CH1_PA9_INP_NORMP \
677 	GD32_PINMUX_AFIO('A', 9, GPIO_IN, TIMER0_NORMP)
678 #define TIMER0_CH1_PA9_OUT_NORMP \
679 	GD32_PINMUX_AFIO('A', 9, ALTERNATE, TIMER0_NORMP)
680 #define TIMER0_CH1_PA9_INP_PRMP \
681 	GD32_PINMUX_AFIO('A', 9, GPIO_IN, TIMER0_PRMP)
682 #define TIMER0_CH1_PA9_OUT_PRMP \
683 	GD32_PINMUX_AFIO('A', 9, ALTERNATE, TIMER0_PRMP)
684 #define TIMER0_CH1_PE11_INP_FRMP \
685 	GD32_PINMUX_AFIO('E', 11, GPIO_IN, TIMER0_FRMP)
686 #define TIMER0_CH1_PE11_OUT_FRMP \
687 	GD32_PINMUX_AFIO('E', 11, ALTERNATE, TIMER0_FRMP)
688 
689 /* TIMER0_CH1_ON */
690 #define TIMER0_CH1_ON_PB14_NORMP \
691 	GD32_PINMUX_AFIO('B', 14, ALTERNATE, TIMER0_NORMP)
692 #define TIMER0_CH1_ON_PB0_PRMP \
693 	GD32_PINMUX_AFIO('B', 0, ALTERNATE, TIMER0_PRMP)
694 #define TIMER0_CH1_ON_PE10_FRMP \
695 	GD32_PINMUX_AFIO('E', 10, ALTERNATE, TIMER0_FRMP)
696 
697 /* TIMER0_CH2 */
698 #define TIMER0_CH2_PA10_INP_NORMP \
699 	GD32_PINMUX_AFIO('A', 10, GPIO_IN, TIMER0_NORMP)
700 #define TIMER0_CH2_PA10_OUT_NORMP \
701 	GD32_PINMUX_AFIO('A', 10, ALTERNATE, TIMER0_NORMP)
702 #define TIMER0_CH2_PA10_INP_PRMP \
703 	GD32_PINMUX_AFIO('A', 10, GPIO_IN, TIMER0_PRMP)
704 #define TIMER0_CH2_PA10_OUT_PRMP \
705 	GD32_PINMUX_AFIO('A', 10, ALTERNATE, TIMER0_PRMP)
706 #define TIMER0_CH2_PE13_INP_FRMP \
707 	GD32_PINMUX_AFIO('E', 13, GPIO_IN, TIMER0_FRMP)
708 #define TIMER0_CH2_PE13_OUT_FRMP \
709 	GD32_PINMUX_AFIO('E', 13, ALTERNATE, TIMER0_FRMP)
710 
711 /* TIMER0_CH2_ON */
712 #define TIMER0_CH2_ON_PB15_NORMP \
713 	GD32_PINMUX_AFIO('B', 15, ALTERNATE, TIMER0_NORMP)
714 #define TIMER0_CH2_ON_PB1_PRMP \
715 	GD32_PINMUX_AFIO('B', 1, ALTERNATE, TIMER0_PRMP)
716 #define TIMER0_CH2_ON_PE12_FRMP \
717 	GD32_PINMUX_AFIO('E', 12, ALTERNATE, TIMER0_FRMP)
718 
719 /* TIMER0_CH3 */
720 #define TIMER0_CH3_PA11_INP_NORMP \
721 	GD32_PINMUX_AFIO('A', 11, GPIO_IN, TIMER0_NORMP)
722 #define TIMER0_CH3_PA11_OUT_NORMP \
723 	GD32_PINMUX_AFIO('A', 11, ALTERNATE, TIMER0_NORMP)
724 #define TIMER0_CH3_PA11_INP_PRMP \
725 	GD32_PINMUX_AFIO('A', 11, GPIO_IN, TIMER0_PRMP)
726 #define TIMER0_CH3_PA11_OUT_PRMP \
727 	GD32_PINMUX_AFIO('A', 11, ALTERNATE, TIMER0_PRMP)
728 #define TIMER0_CH3_PE14_INP_FRMP \
729 	GD32_PINMUX_AFIO('E', 14, GPIO_IN, TIMER0_FRMP)
730 #define TIMER0_CH3_PE14_OUT_FRMP \
731 	GD32_PINMUX_AFIO('E', 14, ALTERNATE, TIMER0_FRMP)
732 
733 /* TIMER0_ETI */
734 #define TIMER0_ETI_PA12_NORMP \
735 	GD32_PINMUX_AFIO('A', 12, GPIO_IN, TIMER0_NORMP)
736 #define TIMER0_ETI_PA12_PRMP \
737 	GD32_PINMUX_AFIO('A', 12, GPIO_IN, TIMER0_PRMP)
738 #define TIMER0_ETI_PE7_FRMP \
739 	GD32_PINMUX_AFIO('E', 7, GPIO_IN, TIMER0_FRMP)
740 
741 /* TIMER10_CH0 */
742 #define TIMER10_CH0_PB9_INP_NORMP \
743 	GD32_PINMUX_AFIO('B', 9, GPIO_IN, TIMER10_NORMP)
744 #define TIMER10_CH0_PB9_OUT_NORMP \
745 	GD32_PINMUX_AFIO('B', 9, ALTERNATE, TIMER10_NORMP)
746 
747 /* TIMER11_CH0 */
748 #define TIMER11_CH0_PB14_INP \
749 	GD32_PINMUX_AFIO('B', 14, GPIO_IN, NORMP)
750 #define TIMER11_CH0_PB14_OUT \
751 	GD32_PINMUX_AFIO('B', 14, ALTERNATE, NORMP)
752 
753 /* TIMER11_CH1 */
754 #define TIMER11_CH1_PB15_INP \
755 	GD32_PINMUX_AFIO('B', 15, GPIO_IN, NORMP)
756 #define TIMER11_CH1_PB15_OUT \
757 	GD32_PINMUX_AFIO('B', 15, ALTERNATE, NORMP)
758 
759 /* TIMER12_CH0 */
760 #define TIMER12_CH0_PA6_INP_NORMP \
761 	GD32_PINMUX_AFIO('A', 6, GPIO_IN, TIMER12_NORMP)
762 #define TIMER12_CH0_PA6_OUT_NORMP \
763 	GD32_PINMUX_AFIO('A', 6, ALTERNATE, TIMER12_NORMP)
764 
765 /* TIMER13_CH0 */
766 #define TIMER13_CH0_PA7_INP_NORMP \
767 	GD32_PINMUX_AFIO('A', 7, GPIO_IN, TIMER13_NORMP)
768 #define TIMER13_CH0_PA7_OUT_NORMP \
769 	GD32_PINMUX_AFIO('A', 7, ALTERNATE, TIMER13_NORMP)
770 
771 /* TIMER2_CH0 */
772 #define TIMER2_CH0_PA6_INP_NORMP \
773 	GD32_PINMUX_AFIO('A', 6, GPIO_IN, TIMER2_NORMP)
774 #define TIMER2_CH0_PA6_OUT_NORMP \
775 	GD32_PINMUX_AFIO('A', 6, ALTERNATE, TIMER2_NORMP)
776 #define TIMER2_CH0_PB4_INP_PRMP \
777 	GD32_PINMUX_AFIO('B', 4, GPIO_IN, TIMER2_PRMP)
778 #define TIMER2_CH0_PB4_OUT_PRMP \
779 	GD32_PINMUX_AFIO('B', 4, ALTERNATE, TIMER2_PRMP)
780 #define TIMER2_CH0_PC6_INP_FRMP \
781 	GD32_PINMUX_AFIO('C', 6, GPIO_IN, TIMER2_FRMP)
782 #define TIMER2_CH0_PC6_OUT_FRMP \
783 	GD32_PINMUX_AFIO('C', 6, ALTERNATE, TIMER2_FRMP)
784 
785 /* TIMER2_CH1 */
786 #define TIMER2_CH1_PA7_INP_NORMP \
787 	GD32_PINMUX_AFIO('A', 7, GPIO_IN, TIMER2_NORMP)
788 #define TIMER2_CH1_PA7_OUT_NORMP \
789 	GD32_PINMUX_AFIO('A', 7, ALTERNATE, TIMER2_NORMP)
790 #define TIMER2_CH1_PB5_INP_PRMP \
791 	GD32_PINMUX_AFIO('B', 5, GPIO_IN, TIMER2_PRMP)
792 #define TIMER2_CH1_PB5_OUT_PRMP \
793 	GD32_PINMUX_AFIO('B', 5, ALTERNATE, TIMER2_PRMP)
794 #define TIMER2_CH1_PC7_INP_FRMP \
795 	GD32_PINMUX_AFIO('C', 7, GPIO_IN, TIMER2_FRMP)
796 #define TIMER2_CH1_PC7_OUT_FRMP \
797 	GD32_PINMUX_AFIO('C', 7, ALTERNATE, TIMER2_FRMP)
798 
799 /* TIMER2_CH2 */
800 #define TIMER2_CH2_PB0_INP_NORMP \
801 	GD32_PINMUX_AFIO('B', 0, GPIO_IN, TIMER2_NORMP)
802 #define TIMER2_CH2_PB0_OUT_NORMP \
803 	GD32_PINMUX_AFIO('B', 0, ALTERNATE, TIMER2_NORMP)
804 #define TIMER2_CH2_PB0_INP_PRMP \
805 	GD32_PINMUX_AFIO('B', 0, GPIO_IN, TIMER2_PRMP)
806 #define TIMER2_CH2_PB0_OUT_PRMP \
807 	GD32_PINMUX_AFIO('B', 0, ALTERNATE, TIMER2_PRMP)
808 #define TIMER2_CH2_PC8_INP_FRMP \
809 	GD32_PINMUX_AFIO('C', 8, GPIO_IN, TIMER2_FRMP)
810 #define TIMER2_CH2_PC8_OUT_FRMP \
811 	GD32_PINMUX_AFIO('C', 8, ALTERNATE, TIMER2_FRMP)
812 
813 /* TIMER2_CH3 */
814 #define TIMER2_CH3_PB1_INP_NORMP \
815 	GD32_PINMUX_AFIO('B', 1, GPIO_IN, TIMER2_NORMP)
816 #define TIMER2_CH3_PB1_OUT_NORMP \
817 	GD32_PINMUX_AFIO('B', 1, ALTERNATE, TIMER2_NORMP)
818 #define TIMER2_CH3_PB1_INP_PRMP \
819 	GD32_PINMUX_AFIO('B', 1, GPIO_IN, TIMER2_PRMP)
820 #define TIMER2_CH3_PB1_OUT_PRMP \
821 	GD32_PINMUX_AFIO('B', 1, ALTERNATE, TIMER2_PRMP)
822 #define TIMER2_CH3_PC9_INP_FRMP \
823 	GD32_PINMUX_AFIO('C', 9, GPIO_IN, TIMER2_FRMP)
824 #define TIMER2_CH3_PC9_OUT_FRMP \
825 	GD32_PINMUX_AFIO('C', 9, ALTERNATE, TIMER2_FRMP)
826 
827 /* TIMER2_ETI */
828 #define TIMER2_ETI_PD2 \
829 	GD32_PINMUX_AFIO('D', 2, GPIO_IN, NORMP)
830 
831 /* TIMER3_CH0 */
832 #define TIMER3_CH0_PB6_INP_NORMP \
833 	GD32_PINMUX_AFIO('B', 6, GPIO_IN, TIMER3_NORMP)
834 #define TIMER3_CH0_PB6_OUT_NORMP \
835 	GD32_PINMUX_AFIO('B', 6, ALTERNATE, TIMER3_NORMP)
836 #define TIMER3_CH0_PD12_INP_RMP \
837 	GD32_PINMUX_AFIO('D', 12, GPIO_IN, TIMER3_RMP)
838 #define TIMER3_CH0_PD12_OUT_RMP \
839 	GD32_PINMUX_AFIO('D', 12, ALTERNATE, TIMER3_RMP)
840 
841 /* TIMER3_CH1 */
842 #define TIMER3_CH1_PB7_INP_NORMP \
843 	GD32_PINMUX_AFIO('B', 7, GPIO_IN, TIMER3_NORMP)
844 #define TIMER3_CH1_PB7_OUT_NORMP \
845 	GD32_PINMUX_AFIO('B', 7, ALTERNATE, TIMER3_NORMP)
846 #define TIMER3_CH1_PD13_INP_RMP \
847 	GD32_PINMUX_AFIO('D', 13, GPIO_IN, TIMER3_RMP)
848 #define TIMER3_CH1_PD13_OUT_RMP \
849 	GD32_PINMUX_AFIO('D', 13, ALTERNATE, TIMER3_RMP)
850 
851 /* TIMER3_CH2 */
852 #define TIMER3_CH2_PB8_INP_NORMP \
853 	GD32_PINMUX_AFIO('B', 8, GPIO_IN, TIMER3_NORMP)
854 #define TIMER3_CH2_PB8_OUT_NORMP \
855 	GD32_PINMUX_AFIO('B', 8, ALTERNATE, TIMER3_NORMP)
856 #define TIMER3_CH2_PD14_INP_RMP \
857 	GD32_PINMUX_AFIO('D', 14, GPIO_IN, TIMER3_RMP)
858 #define TIMER3_CH2_PD14_OUT_RMP \
859 	GD32_PINMUX_AFIO('D', 14, ALTERNATE, TIMER3_RMP)
860 
861 /* TIMER3_CH3 */
862 #define TIMER3_CH3_PB9_INP_NORMP \
863 	GD32_PINMUX_AFIO('B', 9, GPIO_IN, TIMER3_NORMP)
864 #define TIMER3_CH3_PB9_OUT_NORMP \
865 	GD32_PINMUX_AFIO('B', 9, ALTERNATE, TIMER3_NORMP)
866 #define TIMER3_CH3_PD15_INP_RMP \
867 	GD32_PINMUX_AFIO('D', 15, GPIO_IN, TIMER3_RMP)
868 #define TIMER3_CH3_PD15_OUT_RMP \
869 	GD32_PINMUX_AFIO('D', 15, ALTERNATE, TIMER3_RMP)
870 
871 /* TIMER3_ETI */
872 #define TIMER3_ETI_PE0 \
873 	GD32_PINMUX_AFIO('E', 0, GPIO_IN, NORMP)
874 
875 /* TIMER7_BRKIN */
876 #define TIMER7_BRKIN_PA6 \
877 	GD32_PINMUX_AFIO('A', 6, GPIO_IN, NORMP)
878 
879 /* TIMER7_CH0 */
880 #define TIMER7_CH0_PC6_INP \
881 	GD32_PINMUX_AFIO('C', 6, GPIO_IN, NORMP)
882 #define TIMER7_CH0_PC6_OUT \
883 	GD32_PINMUX_AFIO('C', 6, ALTERNATE, NORMP)
884 
885 /* TIMER7_CH0_ON */
886 #define TIMER7_CH0_ON_PA7 \
887 	GD32_PINMUX_AFIO('A', 7, ALTERNATE, NORMP)
888 
889 /* TIMER7_CH1 */
890 #define TIMER7_CH1_PC7_INP \
891 	GD32_PINMUX_AFIO('C', 7, GPIO_IN, NORMP)
892 #define TIMER7_CH1_PC7_OUT \
893 	GD32_PINMUX_AFIO('C', 7, ALTERNATE, NORMP)
894 
895 /* TIMER7_CH1_ON */
896 #define TIMER7_CH1_ON_PB0 \
897 	GD32_PINMUX_AFIO('B', 0, ALTERNATE, NORMP)
898 
899 /* TIMER7_CH2 */
900 #define TIMER7_CH2_PC8_INP \
901 	GD32_PINMUX_AFIO('C', 8, GPIO_IN, NORMP)
902 #define TIMER7_CH2_PC8_OUT \
903 	GD32_PINMUX_AFIO('C', 8, ALTERNATE, NORMP)
904 
905 /* TIMER7_CH2_ON */
906 #define TIMER7_CH2_ON_PB1 \
907 	GD32_PINMUX_AFIO('B', 1, ALTERNATE, NORMP)
908 
909 /* TIMER7_CH3 */
910 #define TIMER7_CH3_PC9_INP \
911 	GD32_PINMUX_AFIO('C', 9, GPIO_IN, NORMP)
912 #define TIMER7_CH3_PC9_OUT \
913 	GD32_PINMUX_AFIO('C', 9, ALTERNATE, NORMP)
914 
915 /* TIMER7_ETI */
916 #define TIMER7_ETI_PA0 \
917 	GD32_PINMUX_AFIO('A', 0, GPIO_IN, NORMP)
918 
919 /* TIMER8_CH0 */
920 #define TIMER8_CH0_PA2_INP_NORMP \
921 	GD32_PINMUX_AFIO('A', 2, GPIO_IN, TIMER8_NORMP)
922 #define TIMER8_CH0_PA2_OUT_NORMP \
923 	GD32_PINMUX_AFIO('A', 2, ALTERNATE, TIMER8_NORMP)
924 #define TIMER8_CH0_PE5_INP_RMP \
925 	GD32_PINMUX_AFIO('E', 5, GPIO_IN, TIMER8_RMP)
926 #define TIMER8_CH0_PE5_OUT_RMP \
927 	GD32_PINMUX_AFIO('E', 5, ALTERNATE, TIMER8_RMP)
928 
929 /* TIMER8_CH1 */
930 #define TIMER8_CH1_PA3_INP_NORMP \
931 	GD32_PINMUX_AFIO('A', 3, GPIO_IN, TIMER8_NORMP)
932 #define TIMER8_CH1_PA3_OUT_NORMP \
933 	GD32_PINMUX_AFIO('A', 3, ALTERNATE, TIMER8_NORMP)
934 #define TIMER8_CH1_PE6_INP_RMP \
935 	GD32_PINMUX_AFIO('E', 6, GPIO_IN, TIMER8_RMP)
936 #define TIMER8_CH1_PE6_OUT_RMP \
937 	GD32_PINMUX_AFIO('E', 6, ALTERNATE, TIMER8_RMP)
938 
939 /* TIMER9_CH0 */
940 #define TIMER9_CH0_PB8_INP_NORMP \
941 	GD32_PINMUX_AFIO('B', 8, GPIO_IN, TIMER9_NORMP)
942 #define TIMER9_CH0_PB8_OUT_NORMP \
943 	GD32_PINMUX_AFIO('B', 8, ALTERNATE, TIMER9_NORMP)
944 
945 /* TRACECK */
946 #define TRACECK_PE2 \
947 	GD32_PINMUX_AFIO('E', 2, ALTERNATE, NORMP)
948 
949 /* TRACED0 */
950 #define TRACED0_PE3 \
951 	GD32_PINMUX_AFIO('E', 3, ALTERNATE, NORMP)
952 
953 /* TRACED1 */
954 #define TRACED1_PE4 \
955 	GD32_PINMUX_AFIO('E', 4, ALTERNATE, NORMP)
956 
957 /* TRACED2 */
958 #define TRACED2_PE5 \
959 	GD32_PINMUX_AFIO('E', 5, ALTERNATE, NORMP)
960 
961 /* TRACED3 */
962 #define TRACED3_PE6 \
963 	GD32_PINMUX_AFIO('E', 6, ALTERNATE, NORMP)
964 
965 /* UART3_RX */
966 #define UART3_RX_PC11 \
967 	GD32_PINMUX_AFIO('C', 11, GPIO_IN, NORMP)
968 
969 /* UART3_TX */
970 #define UART3_TX_PC10 \
971 	GD32_PINMUX_AFIO('C', 10, ALTERNATE, NORMP)
972 
973 /* UART4_RX */
974 #define UART4_RX_PD2 \
975 	GD32_PINMUX_AFIO('D', 2, GPIO_IN, NORMP)
976 
977 /* UART4_TX */
978 #define UART4_TX_PC12 \
979 	GD32_PINMUX_AFIO('C', 12, ALTERNATE, NORMP)
980 
981 /* USART0_CK */
982 #define USART0_CK_PA8 \
983 	GD32_PINMUX_AFIO('A', 8, ALTERNATE, NORMP)
984 
985 /* USART0_CTS */
986 #define USART0_CTS_PA11 \
987 	GD32_PINMUX_AFIO('A', 11, GPIO_IN, NORMP)
988 
989 /* USART0_RTS */
990 #define USART0_RTS_PA12 \
991 	GD32_PINMUX_AFIO('A', 12, ALTERNATE, NORMP)
992 
993 /* USART0_RX */
994 #define USART0_RX_PA10_NORMP \
995 	GD32_PINMUX_AFIO('A', 10, GPIO_IN, USART0_NORMP)
996 #define USART0_RX_PB7_RMP \
997 	GD32_PINMUX_AFIO('B', 7, GPIO_IN, USART0_RMP)
998 
999 /* USART0_TX */
1000 #define USART0_TX_PA9_NORMP \
1001 	GD32_PINMUX_AFIO('A', 9, ALTERNATE, USART0_NORMP)
1002 #define USART0_TX_PB6_RMP \
1003 	GD32_PINMUX_AFIO('B', 6, ALTERNATE, USART0_RMP)
1004 
1005 /* USART1_CK */
1006 #define USART1_CK_PA4_NORMP \
1007 	GD32_PINMUX_AFIO('A', 4, ALTERNATE, USART1_NORMP)
1008 #define USART1_CK_PD7_RMP \
1009 	GD32_PINMUX_AFIO('D', 7, ALTERNATE, USART1_RMP)
1010 
1011 /* USART1_CTS */
1012 #define USART1_CTS_PA0_NORMP \
1013 	GD32_PINMUX_AFIO('A', 0, GPIO_IN, USART1_NORMP)
1014 #define USART1_CTS_PD3_RMP \
1015 	GD32_PINMUX_AFIO('D', 3, GPIO_IN, USART1_RMP)
1016 
1017 /* USART1_RTS */
1018 #define USART1_RTS_PA1_NORMP \
1019 	GD32_PINMUX_AFIO('A', 1, ALTERNATE, USART1_NORMP)
1020 #define USART1_RTS_PD4_RMP \
1021 	GD32_PINMUX_AFIO('D', 4, ALTERNATE, USART1_RMP)
1022 
1023 /* USART1_RX */
1024 #define USART1_RX_PA3_NORMP \
1025 	GD32_PINMUX_AFIO('A', 3, GPIO_IN, USART1_NORMP)
1026 #define USART1_RX_PD6_RMP \
1027 	GD32_PINMUX_AFIO('D', 6, GPIO_IN, USART1_RMP)
1028 
1029 /* USART1_TX */
1030 #define USART1_TX_PA2_NORMP \
1031 	GD32_PINMUX_AFIO('A', 2, ALTERNATE, USART1_NORMP)
1032 #define USART1_TX_PD5_RMP \
1033 	GD32_PINMUX_AFIO('D', 5, ALTERNATE, USART1_RMP)
1034 
1035 /* USART2_CK */
1036 #define USART2_CK_PB12_NORMP \
1037 	GD32_PINMUX_AFIO('B', 12, ALTERNATE, USART2_NORMP)
1038 #define USART2_CK_PC12_PRMP \
1039 	GD32_PINMUX_AFIO('C', 12, ALTERNATE, USART2_PRMP)
1040 #define USART2_CK_PD10_FRMP \
1041 	GD32_PINMUX_AFIO('D', 10, ALTERNATE, USART2_FRMP)
1042 
1043 /* USART2_CTS */
1044 #define USART2_CTS_PB13_NORMP \
1045 	GD32_PINMUX_AFIO('B', 13, GPIO_IN, USART2_NORMP)
1046 #define USART2_CTS_PB13_PRMP \
1047 	GD32_PINMUX_AFIO('B', 13, GPIO_IN, USART2_PRMP)
1048 #define USART2_CTS_PD11_FRMP \
1049 	GD32_PINMUX_AFIO('D', 11, GPIO_IN, USART2_FRMP)
1050 
1051 /* USART2_RTS */
1052 #define USART2_RTS_PB14_NORMP \
1053 	GD32_PINMUX_AFIO('B', 14, ALTERNATE, USART2_NORMP)
1054 #define USART2_RTS_PB14_PRMP \
1055 	GD32_PINMUX_AFIO('B', 14, ALTERNATE, USART2_PRMP)
1056 #define USART2_RTS_PD12_FRMP \
1057 	GD32_PINMUX_AFIO('D', 12, ALTERNATE, USART2_FRMP)
1058 
1059 /* USART2_RX */
1060 #define USART2_RX_PB11_NORMP \
1061 	GD32_PINMUX_AFIO('B', 11, GPIO_IN, USART2_NORMP)
1062 #define USART2_RX_PC11_PRMP \
1063 	GD32_PINMUX_AFIO('C', 11, GPIO_IN, USART2_PRMP)
1064 #define USART2_RX_PD9_FRMP \
1065 	GD32_PINMUX_AFIO('D', 9, GPIO_IN, USART2_FRMP)
1066 
1067 /* USART2_TX */
1068 #define USART2_TX_PB10_NORMP \
1069 	GD32_PINMUX_AFIO('B', 10, ALTERNATE, USART2_NORMP)
1070 #define USART2_TX_PC10_PRMP \
1071 	GD32_PINMUX_AFIO('C', 10, ALTERNATE, USART2_PRMP)
1072 #define USART2_TX_PD8_FRMP \
1073 	GD32_PINMUX_AFIO('D', 8, ALTERNATE, USART2_FRMP)
1074 
1075 /* USBFS_DM */
1076 #define USBFS_DM_PA11_INP \
1077 	GD32_PINMUX_AFIO('A', 11, GPIO_IN, NORMP)
1078 #define USBFS_DM_PA11_OUT \
1079 	GD32_PINMUX_AFIO('A', 11, ALTERNATE, NORMP)
1080 
1081 /* USBFS_DP */
1082 #define USBFS_DP_PA12_INP \
1083 	GD32_PINMUX_AFIO('A', 12, GPIO_IN, NORMP)
1084 #define USBFS_DP_PA12_OUT \
1085 	GD32_PINMUX_AFIO('A', 12, ALTERNATE, NORMP)
1086 
1087 /* USBFS_ID */
1088 #define USBFS_ID_PA10_INP \
1089 	GD32_PINMUX_AFIO('A', 10, GPIO_IN, NORMP)
1090 #define USBFS_ID_PA10_OUT \
1091 	GD32_PINMUX_AFIO('A', 10, ALTERNATE, NORMP)
1092 
1093 /* USBFS_SOF */
1094 #define USBFS_SOF_PA8 \
1095 	GD32_PINMUX_AFIO('A', 8, ALTERNATE, NORMP)
1096 
1097 /* USBFS_VBUS */
1098 #define USBFS_VBUS_PA9 \
1099 	GD32_PINMUX_AFIO('A', 9, GPIO_IN, NORMP)
1100 
1101 /* WKUP */
1102 #define WKUP_PA0 \
1103 	GD32_PINMUX_AFIO('A', 0, GPIO_IN, NORMP)
1104