/* * Autogenerated file * * SPDX-License-Identifier: Apache 2.0 */ #include "gd32f403xx-afio.h" /* ADC012_IN0 */ #define ADC012_IN0_PA0 \ GD32_PINMUX_AFIO('A', 0, ANALOG, NORMP) /* ADC012_IN1 */ #define ADC012_IN1_PA1 \ GD32_PINMUX_AFIO('A', 1, ANALOG, NORMP) /* ADC012_IN10 */ #define ADC012_IN10_PC0 \ GD32_PINMUX_AFIO('C', 0, ANALOG, NORMP) /* ADC012_IN11 */ #define ADC012_IN11_PC1 \ GD32_PINMUX_AFIO('C', 1, ANALOG, NORMP) /* ADC012_IN12 */ #define ADC012_IN12_PC2 \ GD32_PINMUX_AFIO('C', 2, ANALOG, NORMP) /* ADC012_IN13 */ #define ADC012_IN13_PC3 \ GD32_PINMUX_AFIO('C', 3, ANALOG, NORMP) /* ADC012_IN2 */ #define ADC012_IN2_PA2 \ GD32_PINMUX_AFIO('A', 2, ANALOG, NORMP) /* ADC012_IN3 */ #define ADC012_IN3_PA3 \ GD32_PINMUX_AFIO('A', 3, ANALOG, NORMP) /* ADC01_IN14 */ #define ADC01_IN14_PC4 \ GD32_PINMUX_AFIO('C', 4, ANALOG, NORMP) /* ADC01_IN15 */ #define ADC01_IN15_PC5 \ GD32_PINMUX_AFIO('C', 5, ANALOG, NORMP) /* ADC01_IN4 */ #define ADC01_IN4_PA4 \ GD32_PINMUX_AFIO('A', 4, ANALOG, NORMP) /* ADC01_IN5 */ #define ADC01_IN5_PA5 \ GD32_PINMUX_AFIO('A', 5, ANALOG, NORMP) /* ADC01_IN6 */ #define ADC01_IN6_PA6 \ GD32_PINMUX_AFIO('A', 6, ANALOG, NORMP) /* ADC01_IN7 */ #define ADC01_IN7_PA7 \ GD32_PINMUX_AFIO('A', 7, ANALOG, NORMP) /* ADC01_IN8 */ #define ADC01_IN8_PB0 \ GD32_PINMUX_AFIO('B', 0, ANALOG, NORMP) /* ADC01_IN9 */ #define ADC01_IN9_PB1 \ GD32_PINMUX_AFIO('B', 1, ANALOG, NORMP) /* ANALOG */ #define ANALOG_PA0 \ GD32_PINMUX_AFIO('A', 0, ANALOG, NORMP) #define ANALOG_PA1 \ GD32_PINMUX_AFIO('A', 1, ANALOG, NORMP) #define ANALOG_PA2 \ GD32_PINMUX_AFIO('A', 2, ANALOG, NORMP) #define ANALOG_PA3 \ GD32_PINMUX_AFIO('A', 3, ANALOG, NORMP) #define ANALOG_PA4 \ GD32_PINMUX_AFIO('A', 4, ANALOG, NORMP) #define ANALOG_PA5 \ GD32_PINMUX_AFIO('A', 5, ANALOG, NORMP) #define ANALOG_PA6 \ GD32_PINMUX_AFIO('A', 6, ANALOG, NORMP) #define ANALOG_PA7 \ GD32_PINMUX_AFIO('A', 7, ANALOG, NORMP) #define ANALOG_PA8 \ GD32_PINMUX_AFIO('A', 8, ANALOG, NORMP) #define ANALOG_PA9 \ GD32_PINMUX_AFIO('A', 9, ANALOG, NORMP) #define ANALOG_PA10 \ GD32_PINMUX_AFIO('A', 10, ANALOG, NORMP) #define ANALOG_PA11 \ GD32_PINMUX_AFIO('A', 11, ANALOG, NORMP) #define ANALOG_PA12 \ GD32_PINMUX_AFIO('A', 12, ANALOG, NORMP) #define ANALOG_PA13 \ GD32_PINMUX_AFIO('A', 13, ANALOG, NORMP) #define ANALOG_PA14 \ GD32_PINMUX_AFIO('A', 14, ANALOG, NORMP) #define ANALOG_PA15 \ GD32_PINMUX_AFIO('A', 15, ANALOG, NORMP) #define ANALOG_PB0 \ GD32_PINMUX_AFIO('B', 0, ANALOG, NORMP) #define ANALOG_PB1 \ GD32_PINMUX_AFIO('B', 1, ANALOG, NORMP) #define ANALOG_PB2 \ GD32_PINMUX_AFIO('B', 2, ANALOG, NORMP) #define ANALOG_PB3 \ GD32_PINMUX_AFIO('B', 3, ANALOG, NORMP) #define ANALOG_PB4 \ GD32_PINMUX_AFIO('B', 4, ANALOG, NORMP) #define ANALOG_PB5 \ GD32_PINMUX_AFIO('B', 5, ANALOG, NORMP) #define ANALOG_PB6 \ GD32_PINMUX_AFIO('B', 6, ANALOG, NORMP) #define ANALOG_PB7 \ GD32_PINMUX_AFIO('B', 7, ANALOG, NORMP) #define ANALOG_PB8 \ GD32_PINMUX_AFIO('B', 8, ANALOG, NORMP) #define ANALOG_PB9 \ GD32_PINMUX_AFIO('B', 9, ANALOG, NORMP) #define ANALOG_PB10 \ GD32_PINMUX_AFIO('B', 10, ANALOG, NORMP) #define ANALOG_PB11 \ GD32_PINMUX_AFIO('B', 11, ANALOG, NORMP) #define ANALOG_PB12 \ GD32_PINMUX_AFIO('B', 12, ANALOG, NORMP) #define ANALOG_PB13 \ GD32_PINMUX_AFIO('B', 13, ANALOG, NORMP) #define ANALOG_PB14 \ GD32_PINMUX_AFIO('B', 14, ANALOG, NORMP) #define ANALOG_PB15 \ GD32_PINMUX_AFIO('B', 15, ANALOG, NORMP) #define ANALOG_PC0 \ GD32_PINMUX_AFIO('C', 0, ANALOG, NORMP) #define ANALOG_PC1 \ GD32_PINMUX_AFIO('C', 1, ANALOG, NORMP) #define ANALOG_PC2 \ GD32_PINMUX_AFIO('C', 2, ANALOG, NORMP) #define ANALOG_PC3 \ GD32_PINMUX_AFIO('C', 3, ANALOG, NORMP) #define ANALOG_PC4 \ GD32_PINMUX_AFIO('C', 4, ANALOG, NORMP) #define ANALOG_PC5 \ GD32_PINMUX_AFIO('C', 5, ANALOG, NORMP) #define ANALOG_PC6 \ GD32_PINMUX_AFIO('C', 6, ANALOG, NORMP) #define ANALOG_PC7 \ GD32_PINMUX_AFIO('C', 7, ANALOG, NORMP) #define ANALOG_PC8 \ GD32_PINMUX_AFIO('C', 8, ANALOG, NORMP) #define ANALOG_PC9 \ GD32_PINMUX_AFIO('C', 9, ANALOG, NORMP) #define ANALOG_PC10 \ GD32_PINMUX_AFIO('C', 10, ANALOG, NORMP) #define ANALOG_PC11 \ GD32_PINMUX_AFIO('C', 11, ANALOG, NORMP) #define ANALOG_PC12 \ GD32_PINMUX_AFIO('C', 12, ANALOG, NORMP) #define ANALOG_PC13 \ GD32_PINMUX_AFIO('C', 13, ANALOG, NORMP) #define ANALOG_PC14 \ GD32_PINMUX_AFIO('C', 14, ANALOG, NORMP) #define ANALOG_PC15 \ GD32_PINMUX_AFIO('C', 15, ANALOG, NORMP) #define ANALOG_PD0 \ GD32_PINMUX_AFIO('D', 0, ANALOG, NORMP) #define ANALOG_PD1 \ GD32_PINMUX_AFIO('D', 1, ANALOG, NORMP) #define ANALOG_PD2 \ GD32_PINMUX_AFIO('D', 2, ANALOG, NORMP) #define ANALOG_PD3 \ GD32_PINMUX_AFIO('D', 3, ANALOG, NORMP) #define ANALOG_PD4 \ GD32_PINMUX_AFIO('D', 4, ANALOG, NORMP) #define ANALOG_PD5 \ GD32_PINMUX_AFIO('D', 5, ANALOG, NORMP) #define ANALOG_PD6 \ GD32_PINMUX_AFIO('D', 6, ANALOG, NORMP) #define ANALOG_PD7 \ GD32_PINMUX_AFIO('D', 7, ANALOG, NORMP) #define ANALOG_PD8 \ GD32_PINMUX_AFIO('D', 8, ANALOG, NORMP) #define ANALOG_PD9 \ GD32_PINMUX_AFIO('D', 9, ANALOG, NORMP) #define ANALOG_PD10 \ GD32_PINMUX_AFIO('D', 10, ANALOG, NORMP) #define ANALOG_PD11 \ GD32_PINMUX_AFIO('D', 11, ANALOG, NORMP) #define ANALOG_PD12 \ GD32_PINMUX_AFIO('D', 12, ANALOG, NORMP) #define ANALOG_PD13 \ GD32_PINMUX_AFIO('D', 13, ANALOG, NORMP) #define ANALOG_PD14 \ GD32_PINMUX_AFIO('D', 14, ANALOG, NORMP) #define ANALOG_PD15 \ GD32_PINMUX_AFIO('D', 15, ANALOG, NORMP) #define ANALOG_PE0 \ GD32_PINMUX_AFIO('E', 0, ANALOG, NORMP) #define ANALOG_PE1 \ GD32_PINMUX_AFIO('E', 1, ANALOG, NORMP) #define ANALOG_PE2 \ GD32_PINMUX_AFIO('E', 2, ANALOG, NORMP) #define ANALOG_PE3 \ GD32_PINMUX_AFIO('E', 3, ANALOG, NORMP) #define ANALOG_PE4 \ GD32_PINMUX_AFIO('E', 4, ANALOG, NORMP) #define ANALOG_PE5 \ GD32_PINMUX_AFIO('E', 5, ANALOG, NORMP) #define ANALOG_PE6 \ GD32_PINMUX_AFIO('E', 6, ANALOG, NORMP) #define ANALOG_PE7 \ GD32_PINMUX_AFIO('E', 7, ANALOG, NORMP) #define ANALOG_PE8 \ GD32_PINMUX_AFIO('E', 8, ANALOG, NORMP) #define ANALOG_PE9 \ GD32_PINMUX_AFIO('E', 9, ANALOG, NORMP) #define ANALOG_PE10 \ GD32_PINMUX_AFIO('E', 10, ANALOG, NORMP) #define ANALOG_PE11 \ GD32_PINMUX_AFIO('E', 11, ANALOG, NORMP) #define ANALOG_PE12 \ GD32_PINMUX_AFIO('E', 12, ANALOG, NORMP) #define ANALOG_PE13 \ GD32_PINMUX_AFIO('E', 13, ANALOG, NORMP) #define ANALOG_PE14 \ GD32_PINMUX_AFIO('E', 14, ANALOG, NORMP) #define ANALOG_PE15 \ GD32_PINMUX_AFIO('E', 15, ANALOG, NORMP) /* CAN0_RX */ #define CAN0_RX_PA11_NORMP \ GD32_PINMUX_AFIO('A', 11, GPIO_IN, CAN0_NORMP) #define CAN0_RX_PB8_PRMP \ GD32_PINMUX_AFIO('B', 8, GPIO_IN, CAN0_PRMP) #define CAN0_RX_PD0_FRMP \ GD32_PINMUX_AFIO('D', 0, GPIO_IN, CAN0_FRMP) /* CAN0_TX */ #define CAN0_TX_PA12_NORMP \ GD32_PINMUX_AFIO('A', 12, ALTERNATE, CAN0_NORMP) #define CAN0_TX_PB9_PRMP \ GD32_PINMUX_AFIO('B', 9, ALTERNATE, CAN0_PRMP) #define CAN0_TX_PD1_FRMP \ GD32_PINMUX_AFIO('D', 1, ALTERNATE, CAN0_FRMP) /* CAN1_RX */ #define CAN1_RX_PB12_NORMP \ GD32_PINMUX_AFIO('B', 12, GPIO_IN, CAN1_NORMP) #define CAN1_RX_PB5_RMP \ GD32_PINMUX_AFIO('B', 5, GPIO_IN, CAN1_RMP) /* CAN1_TX */ #define CAN1_TX_PB13_NORMP \ GD32_PINMUX_AFIO('B', 13, ALTERNATE, CAN1_NORMP) #define CAN1_TX_PB6_RMP \ GD32_PINMUX_AFIO('B', 6, ALTERNATE, CAN1_RMP) /* CK_OUT0 */ #define CK_OUT0_PA8 \ GD32_PINMUX_AFIO('A', 8, ALTERNATE, NORMP) /* CTC_SYNC */ #define CTC_SYNC_PA8_NORMP \ GD32_PINMUX_AFIO('A', 8, ALTERNATE, CTC_NORMP) #define CTC_SYNC_PD15_PRMP \ GD32_PINMUX_AFIO('D', 15, ALTERNATE, CTC_PRMP) /* DAC_OUT0 */ #define DAC_OUT0_PA4 \ GD32_PINMUX_AFIO('A', 4, ANALOG, NORMP) /* DAC_OUT1 */ #define DAC_OUT1_PA5 \ GD32_PINMUX_AFIO('A', 5, ANALOG, NORMP) /* EXMC_A16 */ #define EXMC_A16_PD11 \ GD32_PINMUX_AFIO('D', 11, ALTERNATE, NORMP) /* EXMC_A17 */ #define EXMC_A17_PD12 \ GD32_PINMUX_AFIO('D', 12, ALTERNATE, NORMP) /* EXMC_A18 */ #define EXMC_A18_PD13 \ GD32_PINMUX_AFIO('D', 13, ALTERNATE, NORMP) /* EXMC_A19 */ #define EXMC_A19_PE3 \ GD32_PINMUX_AFIO('E', 3, ALTERNATE, NORMP) /* EXMC_A20 */ #define EXMC_A20_PE4 \ GD32_PINMUX_AFIO('E', 4, ALTERNATE, NORMP) /* EXMC_A21 */ #define EXMC_A21_PE5 \ GD32_PINMUX_AFIO('E', 5, ALTERNATE, NORMP) /* EXMC_A22 */ #define EXMC_A22_PE6 \ GD32_PINMUX_AFIO('E', 6, ALTERNATE, NORMP) /* EXMC_A23 */ #define EXMC_A23_PE2 \ GD32_PINMUX_AFIO('E', 2, ALTERNATE, NORMP) /* EXMC_CLK */ #define EXMC_CLK_PD3 \ GD32_PINMUX_AFIO('D', 3, ALTERNATE, NORMP) /* EXMC_D0 */ #define EXMC_D0_PD14 \ GD32_PINMUX_AFIO('D', 14, ALTERNATE, NORMP) /* EXMC_D1 */ #define EXMC_D1_PD15 \ GD32_PINMUX_AFIO('D', 15, ALTERNATE, NORMP) /* EXMC_D10 */ #define EXMC_D10_PE13 \ GD32_PINMUX_AFIO('E', 13, ALTERNATE, NORMP) /* EXMC_D11 */ #define EXMC_D11_PE14 \ GD32_PINMUX_AFIO('E', 14, ALTERNATE, NORMP) /* EXMC_D12 */ #define EXMC_D12_PE15 \ GD32_PINMUX_AFIO('E', 15, ALTERNATE, NORMP) /* EXMC_D13 */ #define EXMC_D13_PD8 \ GD32_PINMUX_AFIO('D', 8, ALTERNATE, NORMP) /* EXMC_D14 */ #define EXMC_D14_PD9 \ GD32_PINMUX_AFIO('D', 9, ALTERNATE, NORMP) /* EXMC_D15 */ #define EXMC_D15_PD10 \ GD32_PINMUX_AFIO('D', 10, ALTERNATE, NORMP) /* EXMC_D2 */ #define EXMC_D2_PD0 \ GD32_PINMUX_AFIO('D', 0, ALTERNATE, NORMP) /* EXMC_D3 */ #define EXMC_D3_PD1 \ GD32_PINMUX_AFIO('D', 1, ALTERNATE, NORMP) /* EXMC_D4 */ #define EXMC_D4_PE7 \ GD32_PINMUX_AFIO('E', 7, ALTERNATE, NORMP) /* EXMC_D5 */ #define EXMC_D5_PE8 \ GD32_PINMUX_AFIO('E', 8, ALTERNATE, NORMP) /* EXMC_D6 */ #define EXMC_D6_PE9 \ GD32_PINMUX_AFIO('E', 9, ALTERNATE, NORMP) /* EXMC_D7 */ #define EXMC_D7_PE10 \ GD32_PINMUX_AFIO('E', 10, ALTERNATE, NORMP) /* EXMC_D8 */ #define EXMC_D8_PE11 \ GD32_PINMUX_AFIO('E', 11, ALTERNATE, NORMP) /* EXMC_D9 */ #define EXMC_D9_PE12 \ GD32_PINMUX_AFIO('E', 12, ALTERNATE, NORMP) /* EXMC_NADV */ #define EXMC_NADV_PB7 \ GD32_PINMUX_AFIO('B', 7, ALTERNATE, NORMP) /* EXMC_NBL0 */ #define EXMC_NBL0_PE0 \ GD32_PINMUX_AFIO('E', 0, ALTERNATE, NORMP) /* EXMC_NBL1 */ #define EXMC_NBL1_PE1 \ GD32_PINMUX_AFIO('E', 1, ALTERNATE, NORMP) /* EXMC_NCE1 */ #define EXMC_NCE1_PD7 \ GD32_PINMUX_AFIO('D', 7, ALTERNATE, NORMP) /* EXMC_NE0 */ #define EXMC_NE0_PD7 \ GD32_PINMUX_AFIO('D', 7, ALTERNATE, NORMP) /* EXMC_NOE */ #define EXMC_NOE_PD4 \ GD32_PINMUX_AFIO('D', 4, ALTERNATE, NORMP) /* EXMC_NWAIT */ #define EXMC_NWAIT_PD6 \ GD32_PINMUX_AFIO('D', 6, GPIO_IN, NORMP) /* EXMC_NWE */ #define EXMC_NWE_PD5 \ GD32_PINMUX_AFIO('D', 5, ALTERNATE, NORMP) /* I2C0_SCL */ #define I2C0_SCL_PB6_NORMP \ GD32_PINMUX_AFIO('B', 6, ALTERNATE, I2C0_NORMP) #define I2C0_SCL_PB8_RMP \ GD32_PINMUX_AFIO('B', 8, ALTERNATE, I2C0_RMP) /* I2C0_SDA */ #define I2C0_SDA_PB7_NORMP \ GD32_PINMUX_AFIO('B', 7, ALTERNATE, I2C0_NORMP) #define I2C0_SDA_PB9_RMP \ GD32_PINMUX_AFIO('B', 9, ALTERNATE, I2C0_RMP) /* I2C0_SMBA */ #define I2C0_SMBA_PB5 \ GD32_PINMUX_AFIO('B', 5, ALTERNATE, NORMP) /* I2C1_SCL */ #define I2C1_SCL_PB10 \ GD32_PINMUX_AFIO('B', 10, ALTERNATE, NORMP) /* I2C1_SDA */ #define I2C1_SDA_PB11 \ GD32_PINMUX_AFIO('B', 11, ALTERNATE, NORMP) /* I2C1_SMBA */ #define I2C1_SMBA_PB12 \ GD32_PINMUX_AFIO('B', 12, ALTERNATE, NORMP) /* I2S1_CK */ #define I2S1_CK_PB13_INP \ GD32_PINMUX_AFIO('B', 13, GPIO_IN, NORMP) #define I2S1_CK_PB13_OUT \ GD32_PINMUX_AFIO('B', 13, ALTERNATE, NORMP) /* I2S1_MCK */ #define I2S1_MCK_PC6 \ GD32_PINMUX_AFIO('C', 6, ALTERNATE, NORMP) /* I2S1_SD */ #define I2S1_SD_PB15_INP \ GD32_PINMUX_AFIO('B', 15, GPIO_IN, NORMP) #define I2S1_SD_PB15_OUT \ GD32_PINMUX_AFIO('B', 15, ALTERNATE, NORMP) /* I2S1_WS */ #define I2S1_WS_PB12_INP \ GD32_PINMUX_AFIO('B', 12, GPIO_IN, NORMP) #define I2S1_WS_PB12_OUT \ GD32_PINMUX_AFIO('B', 12, ALTERNATE, NORMP) /* I2S2_CK */ #define I2S2_CK_PB3_INP_NORMP \ GD32_PINMUX_AFIO('B', 3, GPIO_IN, I2S2_NORMP) #define I2S2_CK_PB3_OUT_NORMP \ GD32_PINMUX_AFIO('B', 3, ALTERNATE, I2S2_NORMP) #define I2S2_CK_PC10_INP_RMP \ GD32_PINMUX_AFIO('C', 10, GPIO_IN, I2S2_RMP) #define I2S2_CK_PC10_OUT_RMP \ GD32_PINMUX_AFIO('C', 10, ALTERNATE, I2S2_RMP) /* I2S2_MCK */ #define I2S2_MCK_PC7 \ GD32_PINMUX_AFIO('C', 7, ALTERNATE, NORMP) /* I2S2_SD */ #define I2S2_SD_PB5_INP_NORMP \ GD32_PINMUX_AFIO('B', 5, GPIO_IN, I2S2_NORMP) #define I2S2_SD_PB5_OUT_NORMP \ GD32_PINMUX_AFIO('B', 5, ALTERNATE, I2S2_NORMP) #define I2S2_SD_PC12_INP_RMP \ GD32_PINMUX_AFIO('C', 12, GPIO_IN, I2S2_RMP) #define I2S2_SD_PC12_OUT_RMP \ GD32_PINMUX_AFIO('C', 12, ALTERNATE, I2S2_RMP) /* I2S2_WS */ #define I2S2_WS_PA15_INP_NORMP \ GD32_PINMUX_AFIO('A', 15, GPIO_IN, I2S2_NORMP) #define I2S2_WS_PA15_OUT_NORMP \ GD32_PINMUX_AFIO('A', 15, ALTERNATE, I2S2_NORMP) #define I2S2_WS_PA4_INP_RMP \ GD32_PINMUX_AFIO('A', 4, GPIO_IN, I2S2_RMP) #define I2S2_WS_PA4_OUT_RMP \ GD32_PINMUX_AFIO('A', 4, ALTERNATE, I2S2_RMP) /* SDIO_CK */ #define SDIO_CK_PC12 \ GD32_PINMUX_AFIO('C', 12, ALTERNATE, NORMP) /* SDIO_D0 */ #define SDIO_D0_PC8 \ GD32_PINMUX_AFIO('C', 8, ALTERNATE, NORMP) /* SDIO_D1 */ #define SDIO_D1_PC9 \ GD32_PINMUX_AFIO('C', 9, ALTERNATE, NORMP) /* SDIO_D2 */ #define SDIO_D2_PC10 \ GD32_PINMUX_AFIO('C', 10, ALTERNATE, NORMP) /* SDIO_D3 */ #define SDIO_D3_PC11 \ GD32_PINMUX_AFIO('C', 11, ALTERNATE, NORMP) /* SDIO_D4 */ #define SDIO_D4_PB8 \ GD32_PINMUX_AFIO('B', 8, ALTERNATE, NORMP) /* SDIO_D5 */ #define SDIO_D5_PB9 \ GD32_PINMUX_AFIO('B', 9, ALTERNATE, NORMP) /* SDIO_D6 */ #define SDIO_D6_PC6 \ GD32_PINMUX_AFIO('C', 6, ALTERNATE, NORMP) /* SDIO_D7 */ #define SDIO_D7_PC7 \ GD32_PINMUX_AFIO('C', 7, ALTERNATE, NORMP) /* SPI0_IO2 */ #define SPI0_IO2_PA2 \ GD32_PINMUX_AFIO('A', 2, ALTERNATE, NORMP) /* SPI0_IO3 */ #define SPI0_IO3_PA3 \ GD32_PINMUX_AFIO('A', 3, ALTERNATE, NORMP) /* SPI0_MISO */ #define SPI0_MISO_PA6_INP_NORMP \ GD32_PINMUX_AFIO('A', 6, GPIO_IN, SPI0_NORMP) #define SPI0_MISO_PA6_OUT_NORMP \ GD32_PINMUX_AFIO('A', 6, ALTERNATE, SPI0_NORMP) #define SPI0_MISO_PB4_INP_RMP \ GD32_PINMUX_AFIO('B', 4, GPIO_IN, SPI0_RMP) #define SPI0_MISO_PB4_OUT_RMP \ GD32_PINMUX_AFIO('B', 4, ALTERNATE, SPI0_RMP) /* SPI0_MOSI */ #define SPI0_MOSI_PA7_INP_NORMP \ GD32_PINMUX_AFIO('A', 7, GPIO_IN, SPI0_NORMP) #define SPI0_MOSI_PA7_OUT_NORMP \ GD32_PINMUX_AFIO('A', 7, ALTERNATE, SPI0_NORMP) #define SPI0_MOSI_PB5_INP_RMP \ GD32_PINMUX_AFIO('B', 5, GPIO_IN, SPI0_RMP) #define SPI0_MOSI_PB5_OUT_RMP \ GD32_PINMUX_AFIO('B', 5, ALTERNATE, SPI0_RMP) /* SPI0_NSS */ #define SPI0_NSS_PA4_INP_NORMP \ GD32_PINMUX_AFIO('A', 4, GPIO_IN, SPI0_NORMP) #define SPI0_NSS_PA4_OUT_NORMP \ GD32_PINMUX_AFIO('A', 4, ALTERNATE, SPI0_NORMP) #define SPI0_NSS_PA15_INP_RMP \ GD32_PINMUX_AFIO('A', 15, GPIO_IN, SPI0_RMP) #define SPI0_NSS_PA15_OUT_RMP \ GD32_PINMUX_AFIO('A', 15, ALTERNATE, SPI0_RMP) /* SPI0_SCK */ #define SPI0_SCK_PA5_INP_NORMP \ GD32_PINMUX_AFIO('A', 5, GPIO_IN, SPI0_NORMP) #define SPI0_SCK_PA5_OUT_NORMP \ GD32_PINMUX_AFIO('A', 5, ALTERNATE, SPI0_NORMP) #define SPI0_SCK_PB3_INP_RMP \ GD32_PINMUX_AFIO('B', 3, GPIO_IN, SPI0_RMP) #define SPI0_SCK_PB3_OUT_RMP \ GD32_PINMUX_AFIO('B', 3, ALTERNATE, SPI0_RMP) /* SPI1_MISO */ #define SPI1_MISO_PB14_INP \ GD32_PINMUX_AFIO('B', 14, GPIO_IN, NORMP) #define SPI1_MISO_PB14_OUT \ GD32_PINMUX_AFIO('B', 14, ALTERNATE, NORMP) /* SPI1_MOSI */ #define SPI1_MOSI_PB15_INP \ GD32_PINMUX_AFIO('B', 15, GPIO_IN, NORMP) #define SPI1_MOSI_PB15_OUT \ GD32_PINMUX_AFIO('B', 15, ALTERNATE, NORMP) /* SPI1_NSS */ #define SPI1_NSS_PB12_INP \ GD32_PINMUX_AFIO('B', 12, GPIO_IN, NORMP) #define SPI1_NSS_PB12_OUT \ GD32_PINMUX_AFIO('B', 12, ALTERNATE, NORMP) /* SPI1_SCK */ #define SPI1_SCK_PB13_INP \ GD32_PINMUX_AFIO('B', 13, GPIO_IN, NORMP) #define SPI1_SCK_PB13_OUT \ GD32_PINMUX_AFIO('B', 13, ALTERNATE, NORMP) /* SPI2_MISO */ #define SPI2_MISO_PB4_INP_NORMP \ GD32_PINMUX_AFIO('B', 4, GPIO_IN, SPI2_NORMP) #define SPI2_MISO_PB4_OUT_NORMP \ GD32_PINMUX_AFIO('B', 4, ALTERNATE, SPI2_NORMP) #define SPI2_MISO_PC11_INP_RMP \ GD32_PINMUX_AFIO('C', 11, GPIO_IN, SPI2_RMP) #define SPI2_MISO_PC11_OUT_RMP \ GD32_PINMUX_AFIO('C', 11, ALTERNATE, SPI2_RMP) /* SPI2_MOSI */ #define SPI2_MOSI_PB5_INP_NORMP \ GD32_PINMUX_AFIO('B', 5, GPIO_IN, SPI2_NORMP) #define SPI2_MOSI_PB5_OUT_NORMP \ GD32_PINMUX_AFIO('B', 5, ALTERNATE, SPI2_NORMP) #define SPI2_MOSI_PC12_INP_RMP \ GD32_PINMUX_AFIO('C', 12, GPIO_IN, SPI2_RMP) #define SPI2_MOSI_PC12_OUT_RMP \ GD32_PINMUX_AFIO('C', 12, ALTERNATE, SPI2_RMP) /* SPI2_NSS */ #define SPI2_NSS_PA15_INP_NORMP \ GD32_PINMUX_AFIO('A', 15, GPIO_IN, SPI2_NORMP) #define SPI2_NSS_PA15_OUT_NORMP \ GD32_PINMUX_AFIO('A', 15, ALTERNATE, SPI2_NORMP) #define SPI2_NSS_PA4_INP_RMP \ GD32_PINMUX_AFIO('A', 4, GPIO_IN, SPI2_RMP) #define SPI2_NSS_PA4_OUT_RMP \ GD32_PINMUX_AFIO('A', 4, ALTERNATE, SPI2_RMP) /* SPI2_SCK */ #define SPI2_SCK_PB3_INP_NORMP \ GD32_PINMUX_AFIO('B', 3, GPIO_IN, SPI2_NORMP) #define SPI2_SCK_PB3_OUT_NORMP \ GD32_PINMUX_AFIO('B', 3, ALTERNATE, SPI2_NORMP) #define SPI2_SCK_PC10_INP_RMP \ GD32_PINMUX_AFIO('C', 10, GPIO_IN, SPI2_RMP) #define SPI2_SCK_PC10_OUT_RMP \ GD32_PINMUX_AFIO('C', 10, ALTERNATE, SPI2_RMP) /* TAMPER_RTC */ #define TAMPER_RTC_PC13 \ GD32_PINMUX_AFIO('C', 13, GPIO_IN, NORMP) /* TIMER0_BRKIN */ #define TIMER0_BRKIN_PB12 \ GD32_PINMUX_AFIO('B', 12, GPIO_IN, NORMP) /* TIMER0_CH0 */ #define TIMER0_CH0_PA8_INP_NORMP \ GD32_PINMUX_AFIO('A', 8, GPIO_IN, TIMER0_NORMP) #define TIMER0_CH0_PA8_OUT_NORMP \ GD32_PINMUX_AFIO('A', 8, ALTERNATE, TIMER0_NORMP) #define TIMER0_CH0_PA8_INP_PRMP \ GD32_PINMUX_AFIO('A', 8, GPIO_IN, TIMER0_PRMP) #define TIMER0_CH0_PA8_OUT_PRMP \ GD32_PINMUX_AFIO('A', 8, ALTERNATE, TIMER0_PRMP) #define TIMER0_CH0_PE9_INP_FRMP \ GD32_PINMUX_AFIO('E', 9, GPIO_IN, TIMER0_FRMP) #define TIMER0_CH0_PE9_OUT_FRMP \ GD32_PINMUX_AFIO('E', 9, ALTERNATE, TIMER0_FRMP) /* TIMER0_CH0_ON */ #define TIMER0_CH0_ON_PB13_NORMP \ GD32_PINMUX_AFIO('B', 13, ALTERNATE, TIMER0_NORMP) #define TIMER0_CH0_ON_PA7_PRMP \ GD32_PINMUX_AFIO('A', 7, ALTERNATE, TIMER0_PRMP) #define TIMER0_CH0_ON_PE8_FRMP \ GD32_PINMUX_AFIO('E', 8, ALTERNATE, TIMER0_FRMP) /* TIMER0_CH1 */ #define TIMER0_CH1_PA9_INP_NORMP \ GD32_PINMUX_AFIO('A', 9, GPIO_IN, TIMER0_NORMP) #define TIMER0_CH1_PA9_OUT_NORMP \ GD32_PINMUX_AFIO('A', 9, ALTERNATE, TIMER0_NORMP) #define TIMER0_CH1_PA9_INP_PRMP \ GD32_PINMUX_AFIO('A', 9, GPIO_IN, TIMER0_PRMP) #define TIMER0_CH1_PA9_OUT_PRMP \ GD32_PINMUX_AFIO('A', 9, ALTERNATE, TIMER0_PRMP) #define TIMER0_CH1_PE11_INP_FRMP \ GD32_PINMUX_AFIO('E', 11, GPIO_IN, TIMER0_FRMP) #define TIMER0_CH1_PE11_OUT_FRMP \ GD32_PINMUX_AFIO('E', 11, ALTERNATE, TIMER0_FRMP) /* TIMER0_CH1_ON */ #define TIMER0_CH1_ON_PB14_NORMP \ GD32_PINMUX_AFIO('B', 14, ALTERNATE, TIMER0_NORMP) #define TIMER0_CH1_ON_PB0_PRMP \ GD32_PINMUX_AFIO('B', 0, ALTERNATE, TIMER0_PRMP) #define TIMER0_CH1_ON_PE10_FRMP \ GD32_PINMUX_AFIO('E', 10, ALTERNATE, TIMER0_FRMP) /* TIMER0_CH2 */ #define TIMER0_CH2_PA10_INP_NORMP \ GD32_PINMUX_AFIO('A', 10, GPIO_IN, TIMER0_NORMP) #define TIMER0_CH2_PA10_OUT_NORMP \ GD32_PINMUX_AFIO('A', 10, ALTERNATE, TIMER0_NORMP) #define TIMER0_CH2_PA10_INP_PRMP \ GD32_PINMUX_AFIO('A', 10, GPIO_IN, TIMER0_PRMP) #define TIMER0_CH2_PA10_OUT_PRMP \ GD32_PINMUX_AFIO('A', 10, ALTERNATE, TIMER0_PRMP) #define TIMER0_CH2_PE13_INP_FRMP \ GD32_PINMUX_AFIO('E', 13, GPIO_IN, TIMER0_FRMP) #define TIMER0_CH2_PE13_OUT_FRMP \ GD32_PINMUX_AFIO('E', 13, ALTERNATE, TIMER0_FRMP) /* TIMER0_CH2_ON */ #define TIMER0_CH2_ON_PB15_NORMP \ GD32_PINMUX_AFIO('B', 15, ALTERNATE, TIMER0_NORMP) #define TIMER0_CH2_ON_PB1_PRMP \ GD32_PINMUX_AFIO('B', 1, ALTERNATE, TIMER0_PRMP) #define TIMER0_CH2_ON_PE12_FRMP \ GD32_PINMUX_AFIO('E', 12, ALTERNATE, TIMER0_FRMP) /* TIMER0_CH3 */ #define TIMER0_CH3_PA11_INP_NORMP \ GD32_PINMUX_AFIO('A', 11, GPIO_IN, TIMER0_NORMP) #define TIMER0_CH3_PA11_OUT_NORMP \ GD32_PINMUX_AFIO('A', 11, ALTERNATE, TIMER0_NORMP) #define TIMER0_CH3_PA11_INP_PRMP \ GD32_PINMUX_AFIO('A', 11, GPIO_IN, TIMER0_PRMP) #define TIMER0_CH3_PA11_OUT_PRMP \ GD32_PINMUX_AFIO('A', 11, ALTERNATE, TIMER0_PRMP) #define TIMER0_CH3_PE14_INP_FRMP \ GD32_PINMUX_AFIO('E', 14, GPIO_IN, TIMER0_FRMP) #define TIMER0_CH3_PE14_OUT_FRMP \ GD32_PINMUX_AFIO('E', 14, ALTERNATE, TIMER0_FRMP) /* TIMER0_ETI */ #define TIMER0_ETI_PA12_NORMP \ GD32_PINMUX_AFIO('A', 12, GPIO_IN, TIMER0_NORMP) #define TIMER0_ETI_PA12_PRMP \ GD32_PINMUX_AFIO('A', 12, GPIO_IN, TIMER0_PRMP) #define TIMER0_ETI_PE7_FRMP \ GD32_PINMUX_AFIO('E', 7, GPIO_IN, TIMER0_FRMP) /* TIMER10_CH0 */ #define TIMER10_CH0_PB9_INP_NORMP \ GD32_PINMUX_AFIO('B', 9, GPIO_IN, TIMER10_NORMP) #define TIMER10_CH0_PB9_OUT_NORMP \ GD32_PINMUX_AFIO('B', 9, ALTERNATE, TIMER10_NORMP) /* TIMER11_CH0 */ #define TIMER11_CH0_PB14_INP \ GD32_PINMUX_AFIO('B', 14, GPIO_IN, NORMP) #define TIMER11_CH0_PB14_OUT \ GD32_PINMUX_AFIO('B', 14, ALTERNATE, NORMP) /* TIMER11_CH1 */ #define TIMER11_CH1_PB15_INP \ GD32_PINMUX_AFIO('B', 15, GPIO_IN, NORMP) #define TIMER11_CH1_PB15_OUT \ GD32_PINMUX_AFIO('B', 15, ALTERNATE, NORMP) /* TIMER12_CH0 */ #define TIMER12_CH0_PA6_INP_NORMP \ GD32_PINMUX_AFIO('A', 6, GPIO_IN, TIMER12_NORMP) #define TIMER12_CH0_PA6_OUT_NORMP \ GD32_PINMUX_AFIO('A', 6, ALTERNATE, TIMER12_NORMP) /* TIMER13_CH0 */ #define TIMER13_CH0_PA7_INP_NORMP \ GD32_PINMUX_AFIO('A', 7, GPIO_IN, TIMER13_NORMP) #define TIMER13_CH0_PA7_OUT_NORMP \ GD32_PINMUX_AFIO('A', 7, ALTERNATE, TIMER13_NORMP) /* TIMER2_CH0 */ #define TIMER2_CH0_PA6_INP_NORMP \ GD32_PINMUX_AFIO('A', 6, GPIO_IN, TIMER2_NORMP) #define TIMER2_CH0_PA6_OUT_NORMP \ GD32_PINMUX_AFIO('A', 6, ALTERNATE, TIMER2_NORMP) #define TIMER2_CH0_PB4_INP_PRMP \ GD32_PINMUX_AFIO('B', 4, GPIO_IN, TIMER2_PRMP) #define TIMER2_CH0_PB4_OUT_PRMP \ GD32_PINMUX_AFIO('B', 4, ALTERNATE, TIMER2_PRMP) #define TIMER2_CH0_PC6_INP_FRMP \ GD32_PINMUX_AFIO('C', 6, GPIO_IN, TIMER2_FRMP) #define TIMER2_CH0_PC6_OUT_FRMP \ GD32_PINMUX_AFIO('C', 6, ALTERNATE, TIMER2_FRMP) /* TIMER2_CH1 */ #define TIMER2_CH1_PA7_INP_NORMP \ GD32_PINMUX_AFIO('A', 7, GPIO_IN, TIMER2_NORMP) #define TIMER2_CH1_PA7_OUT_NORMP \ GD32_PINMUX_AFIO('A', 7, ALTERNATE, TIMER2_NORMP) #define TIMER2_CH1_PB5_INP_PRMP \ GD32_PINMUX_AFIO('B', 5, GPIO_IN, TIMER2_PRMP) #define TIMER2_CH1_PB5_OUT_PRMP \ GD32_PINMUX_AFIO('B', 5, ALTERNATE, TIMER2_PRMP) #define TIMER2_CH1_PC7_INP_FRMP \ GD32_PINMUX_AFIO('C', 7, GPIO_IN, TIMER2_FRMP) #define TIMER2_CH1_PC7_OUT_FRMP \ GD32_PINMUX_AFIO('C', 7, ALTERNATE, TIMER2_FRMP) /* TIMER2_CH2 */ #define TIMER2_CH2_PB0_INP_NORMP \ GD32_PINMUX_AFIO('B', 0, GPIO_IN, TIMER2_NORMP) #define TIMER2_CH2_PB0_OUT_NORMP \ GD32_PINMUX_AFIO('B', 0, ALTERNATE, TIMER2_NORMP) #define TIMER2_CH2_PB0_INP_PRMP \ GD32_PINMUX_AFIO('B', 0, GPIO_IN, TIMER2_PRMP) #define TIMER2_CH2_PB0_OUT_PRMP \ GD32_PINMUX_AFIO('B', 0, ALTERNATE, TIMER2_PRMP) #define TIMER2_CH2_PC8_INP_FRMP \ GD32_PINMUX_AFIO('C', 8, GPIO_IN, TIMER2_FRMP) #define TIMER2_CH2_PC8_OUT_FRMP \ GD32_PINMUX_AFIO('C', 8, ALTERNATE, TIMER2_FRMP) /* TIMER2_CH3 */ #define TIMER2_CH3_PB1_INP_NORMP \ GD32_PINMUX_AFIO('B', 1, GPIO_IN, TIMER2_NORMP) #define TIMER2_CH3_PB1_OUT_NORMP \ GD32_PINMUX_AFIO('B', 1, ALTERNATE, TIMER2_NORMP) #define TIMER2_CH3_PB1_INP_PRMP \ GD32_PINMUX_AFIO('B', 1, GPIO_IN, TIMER2_PRMP) #define TIMER2_CH3_PB1_OUT_PRMP \ GD32_PINMUX_AFIO('B', 1, ALTERNATE, TIMER2_PRMP) #define TIMER2_CH3_PC9_INP_FRMP \ GD32_PINMUX_AFIO('C', 9, GPIO_IN, TIMER2_FRMP) #define TIMER2_CH3_PC9_OUT_FRMP \ GD32_PINMUX_AFIO('C', 9, ALTERNATE, TIMER2_FRMP) /* TIMER2_ETI */ #define TIMER2_ETI_PD2 \ GD32_PINMUX_AFIO('D', 2, GPIO_IN, NORMP) /* TIMER3_CH0 */ #define TIMER3_CH0_PB6_INP_NORMP \ GD32_PINMUX_AFIO('B', 6, GPIO_IN, TIMER3_NORMP) #define TIMER3_CH0_PB6_OUT_NORMP \ GD32_PINMUX_AFIO('B', 6, ALTERNATE, TIMER3_NORMP) #define TIMER3_CH0_PD12_INP_RMP \ GD32_PINMUX_AFIO('D', 12, GPIO_IN, TIMER3_RMP) #define TIMER3_CH0_PD12_OUT_RMP \ GD32_PINMUX_AFIO('D', 12, ALTERNATE, TIMER3_RMP) /* TIMER3_CH1 */ #define TIMER3_CH1_PB7_INP_NORMP \ GD32_PINMUX_AFIO('B', 7, GPIO_IN, TIMER3_NORMP) #define TIMER3_CH1_PB7_OUT_NORMP \ GD32_PINMUX_AFIO('B', 7, ALTERNATE, TIMER3_NORMP) #define TIMER3_CH1_PD13_INP_RMP \ GD32_PINMUX_AFIO('D', 13, GPIO_IN, TIMER3_RMP) #define TIMER3_CH1_PD13_OUT_RMP \ GD32_PINMUX_AFIO('D', 13, ALTERNATE, TIMER3_RMP) /* TIMER3_CH2 */ #define TIMER3_CH2_PB8_INP_NORMP \ GD32_PINMUX_AFIO('B', 8, GPIO_IN, TIMER3_NORMP) #define TIMER3_CH2_PB8_OUT_NORMP \ GD32_PINMUX_AFIO('B', 8, ALTERNATE, TIMER3_NORMP) #define TIMER3_CH2_PD14_INP_RMP \ GD32_PINMUX_AFIO('D', 14, GPIO_IN, TIMER3_RMP) #define TIMER3_CH2_PD14_OUT_RMP \ GD32_PINMUX_AFIO('D', 14, ALTERNATE, TIMER3_RMP) /* TIMER3_CH3 */ #define TIMER3_CH3_PB9_INP_NORMP \ GD32_PINMUX_AFIO('B', 9, GPIO_IN, TIMER3_NORMP) #define TIMER3_CH3_PB9_OUT_NORMP \ GD32_PINMUX_AFIO('B', 9, ALTERNATE, TIMER3_NORMP) #define TIMER3_CH3_PD15_INP_RMP \ GD32_PINMUX_AFIO('D', 15, GPIO_IN, TIMER3_RMP) #define TIMER3_CH3_PD15_OUT_RMP \ GD32_PINMUX_AFIO('D', 15, ALTERNATE, TIMER3_RMP) /* TIMER3_ETI */ #define TIMER3_ETI_PE0 \ GD32_PINMUX_AFIO('E', 0, GPIO_IN, NORMP) /* TIMER7_BRKIN */ #define TIMER7_BRKIN_PA6 \ GD32_PINMUX_AFIO('A', 6, GPIO_IN, NORMP) /* TIMER7_CH0 */ #define TIMER7_CH0_PC6_INP \ GD32_PINMUX_AFIO('C', 6, GPIO_IN, NORMP) #define TIMER7_CH0_PC6_OUT \ GD32_PINMUX_AFIO('C', 6, ALTERNATE, NORMP) /* TIMER7_CH0_ON */ #define TIMER7_CH0_ON_PA7 \ GD32_PINMUX_AFIO('A', 7, ALTERNATE, NORMP) /* TIMER7_CH1 */ #define TIMER7_CH1_PC7_INP \ GD32_PINMUX_AFIO('C', 7, GPIO_IN, NORMP) #define TIMER7_CH1_PC7_OUT \ GD32_PINMUX_AFIO('C', 7, ALTERNATE, NORMP) /* TIMER7_CH1_ON */ #define TIMER7_CH1_ON_PB0 \ GD32_PINMUX_AFIO('B', 0, ALTERNATE, NORMP) /* TIMER7_CH2 */ #define TIMER7_CH2_PC8_INP \ GD32_PINMUX_AFIO('C', 8, GPIO_IN, NORMP) #define TIMER7_CH2_PC8_OUT \ GD32_PINMUX_AFIO('C', 8, ALTERNATE, NORMP) /* TIMER7_CH2_ON */ #define TIMER7_CH2_ON_PB1 \ GD32_PINMUX_AFIO('B', 1, ALTERNATE, NORMP) /* TIMER7_CH3 */ #define TIMER7_CH3_PC9_INP \ GD32_PINMUX_AFIO('C', 9, GPIO_IN, NORMP) #define TIMER7_CH3_PC9_OUT \ GD32_PINMUX_AFIO('C', 9, ALTERNATE, NORMP) /* TIMER7_ETI */ #define TIMER7_ETI_PA0 \ GD32_PINMUX_AFIO('A', 0, GPIO_IN, NORMP) /* TIMER8_CH0 */ #define TIMER8_CH0_PA2_INP_NORMP \ GD32_PINMUX_AFIO('A', 2, GPIO_IN, TIMER8_NORMP) #define TIMER8_CH0_PA2_OUT_NORMP \ GD32_PINMUX_AFIO('A', 2, ALTERNATE, TIMER8_NORMP) #define TIMER8_CH0_PE5_INP_RMP \ GD32_PINMUX_AFIO('E', 5, GPIO_IN, TIMER8_RMP) #define TIMER8_CH0_PE5_OUT_RMP \ GD32_PINMUX_AFIO('E', 5, ALTERNATE, TIMER8_RMP) /* TIMER8_CH1 */ #define TIMER8_CH1_PA3_INP_NORMP \ GD32_PINMUX_AFIO('A', 3, GPIO_IN, TIMER8_NORMP) #define TIMER8_CH1_PA3_OUT_NORMP \ GD32_PINMUX_AFIO('A', 3, ALTERNATE, TIMER8_NORMP) #define TIMER8_CH1_PE6_INP_RMP \ GD32_PINMUX_AFIO('E', 6, GPIO_IN, TIMER8_RMP) #define TIMER8_CH1_PE6_OUT_RMP \ GD32_PINMUX_AFIO('E', 6, ALTERNATE, TIMER8_RMP) /* TIMER9_CH0 */ #define TIMER9_CH0_PB8_INP_NORMP \ GD32_PINMUX_AFIO('B', 8, GPIO_IN, TIMER9_NORMP) #define TIMER9_CH0_PB8_OUT_NORMP \ GD32_PINMUX_AFIO('B', 8, ALTERNATE, TIMER9_NORMP) /* TRACECK */ #define TRACECK_PE2 \ GD32_PINMUX_AFIO('E', 2, ALTERNATE, NORMP) /* TRACED0 */ #define TRACED0_PE3 \ GD32_PINMUX_AFIO('E', 3, ALTERNATE, NORMP) /* TRACED1 */ #define TRACED1_PE4 \ GD32_PINMUX_AFIO('E', 4, ALTERNATE, NORMP) /* TRACED2 */ #define TRACED2_PE5 \ GD32_PINMUX_AFIO('E', 5, ALTERNATE, NORMP) /* TRACED3 */ #define TRACED3_PE6 \ GD32_PINMUX_AFIO('E', 6, ALTERNATE, NORMP) /* UART3_RX */ #define UART3_RX_PC11 \ GD32_PINMUX_AFIO('C', 11, GPIO_IN, NORMP) /* UART3_TX */ #define UART3_TX_PC10 \ GD32_PINMUX_AFIO('C', 10, ALTERNATE, NORMP) /* UART4_RX */ #define UART4_RX_PD2 \ GD32_PINMUX_AFIO('D', 2, GPIO_IN, NORMP) /* UART4_TX */ #define UART4_TX_PC12 \ GD32_PINMUX_AFIO('C', 12, ALTERNATE, NORMP) /* USART0_CK */ #define USART0_CK_PA8 \ GD32_PINMUX_AFIO('A', 8, ALTERNATE, NORMP) /* USART0_CTS */ #define USART0_CTS_PA11 \ GD32_PINMUX_AFIO('A', 11, GPIO_IN, NORMP) /* USART0_RTS */ #define USART0_RTS_PA12 \ GD32_PINMUX_AFIO('A', 12, ALTERNATE, NORMP) /* USART0_RX */ #define USART0_RX_PA10_NORMP \ GD32_PINMUX_AFIO('A', 10, GPIO_IN, USART0_NORMP) #define USART0_RX_PB7_RMP \ GD32_PINMUX_AFIO('B', 7, GPIO_IN, USART0_RMP) /* USART0_TX */ #define USART0_TX_PA9_NORMP \ GD32_PINMUX_AFIO('A', 9, ALTERNATE, USART0_NORMP) #define USART0_TX_PB6_RMP \ GD32_PINMUX_AFIO('B', 6, ALTERNATE, USART0_RMP) /* USART1_CK */ #define USART1_CK_PA4_NORMP \ GD32_PINMUX_AFIO('A', 4, ALTERNATE, USART1_NORMP) #define USART1_CK_PD7_RMP \ GD32_PINMUX_AFIO('D', 7, ALTERNATE, USART1_RMP) /* USART1_CTS */ #define USART1_CTS_PA0_NORMP \ GD32_PINMUX_AFIO('A', 0, GPIO_IN, USART1_NORMP) #define USART1_CTS_PD3_RMP \ GD32_PINMUX_AFIO('D', 3, GPIO_IN, USART1_RMP) /* USART1_RTS */ #define USART1_RTS_PA1_NORMP \ GD32_PINMUX_AFIO('A', 1, ALTERNATE, USART1_NORMP) #define USART1_RTS_PD4_RMP \ GD32_PINMUX_AFIO('D', 4, ALTERNATE, USART1_RMP) /* USART1_RX */ #define USART1_RX_PA3_NORMP \ GD32_PINMUX_AFIO('A', 3, GPIO_IN, USART1_NORMP) #define USART1_RX_PD6_RMP \ GD32_PINMUX_AFIO('D', 6, GPIO_IN, USART1_RMP) /* USART1_TX */ #define USART1_TX_PA2_NORMP \ GD32_PINMUX_AFIO('A', 2, ALTERNATE, USART1_NORMP) #define USART1_TX_PD5_RMP \ GD32_PINMUX_AFIO('D', 5, ALTERNATE, USART1_RMP) /* USART2_CK */ #define USART2_CK_PB12_NORMP \ GD32_PINMUX_AFIO('B', 12, ALTERNATE, USART2_NORMP) #define USART2_CK_PC12_PRMP \ GD32_PINMUX_AFIO('C', 12, ALTERNATE, USART2_PRMP) #define USART2_CK_PD10_FRMP \ GD32_PINMUX_AFIO('D', 10, ALTERNATE, USART2_FRMP) /* USART2_CTS */ #define USART2_CTS_PB13_NORMP \ GD32_PINMUX_AFIO('B', 13, GPIO_IN, USART2_NORMP) #define USART2_CTS_PB13_PRMP \ GD32_PINMUX_AFIO('B', 13, GPIO_IN, USART2_PRMP) #define USART2_CTS_PD11_FRMP \ GD32_PINMUX_AFIO('D', 11, GPIO_IN, USART2_FRMP) /* USART2_RTS */ #define USART2_RTS_PB14_NORMP \ GD32_PINMUX_AFIO('B', 14, ALTERNATE, USART2_NORMP) #define USART2_RTS_PB14_PRMP \ GD32_PINMUX_AFIO('B', 14, ALTERNATE, USART2_PRMP) #define USART2_RTS_PD12_FRMP \ GD32_PINMUX_AFIO('D', 12, ALTERNATE, USART2_FRMP) /* USART2_RX */ #define USART2_RX_PB11_NORMP \ GD32_PINMUX_AFIO('B', 11, GPIO_IN, USART2_NORMP) #define USART2_RX_PC11_PRMP \ GD32_PINMUX_AFIO('C', 11, GPIO_IN, USART2_PRMP) #define USART2_RX_PD9_FRMP \ GD32_PINMUX_AFIO('D', 9, GPIO_IN, USART2_FRMP) /* USART2_TX */ #define USART2_TX_PB10_NORMP \ GD32_PINMUX_AFIO('B', 10, ALTERNATE, USART2_NORMP) #define USART2_TX_PC10_PRMP \ GD32_PINMUX_AFIO('C', 10, ALTERNATE, USART2_PRMP) #define USART2_TX_PD8_FRMP \ GD32_PINMUX_AFIO('D', 8, ALTERNATE, USART2_FRMP) /* USBFS_DM */ #define USBFS_DM_PA11_INP \ GD32_PINMUX_AFIO('A', 11, GPIO_IN, NORMP) #define USBFS_DM_PA11_OUT \ GD32_PINMUX_AFIO('A', 11, ALTERNATE, NORMP) /* USBFS_DP */ #define USBFS_DP_PA12_INP \ GD32_PINMUX_AFIO('A', 12, GPIO_IN, NORMP) #define USBFS_DP_PA12_OUT \ GD32_PINMUX_AFIO('A', 12, ALTERNATE, NORMP) /* USBFS_ID */ #define USBFS_ID_PA10_INP \ GD32_PINMUX_AFIO('A', 10, GPIO_IN, NORMP) #define USBFS_ID_PA10_OUT \ GD32_PINMUX_AFIO('A', 10, ALTERNATE, NORMP) /* USBFS_SOF */ #define USBFS_SOF_PA8 \ GD32_PINMUX_AFIO('A', 8, ALTERNATE, NORMP) /* USBFS_VBUS */ #define USBFS_VBUS_PA9 \ GD32_PINMUX_AFIO('A', 9, GPIO_IN, NORMP) /* WKUP */ #define WKUP_PA0 \ GD32_PINMUX_AFIO('A', 0, GPIO_IN, NORMP)