1 /*
2  * Autogenerated file
3  *
4  * SPDX-License-Identifier: Apache 2.0
5  */
6 
7 #include "gd32e103xx-afio.h"
8 
9 /* ADC01_IN0 */
10 #define ADC01_IN0_PA0 \
11 	GD32_PINMUX_AFIO('A', 0, ANALOG, NORMP)
12 
13 /* ADC01_IN1 */
14 #define ADC01_IN1_PA1 \
15 	GD32_PINMUX_AFIO('A', 1, ANALOG, NORMP)
16 
17 /* ADC01_IN2 */
18 #define ADC01_IN2_PA2 \
19 	GD32_PINMUX_AFIO('A', 2, ANALOG, NORMP)
20 
21 /* ADC01_IN3 */
22 #define ADC01_IN3_PA3 \
23 	GD32_PINMUX_AFIO('A', 3, ANALOG, NORMP)
24 
25 /* ADC01_IN4 */
26 #define ADC01_IN4_PA4 \
27 	GD32_PINMUX_AFIO('A', 4, ANALOG, NORMP)
28 
29 /* ADC01_IN5 */
30 #define ADC01_IN5_PA5 \
31 	GD32_PINMUX_AFIO('A', 5, ANALOG, NORMP)
32 
33 /* ADC01_IN6 */
34 #define ADC01_IN6_PA6 \
35 	GD32_PINMUX_AFIO('A', 6, ANALOG, NORMP)
36 
37 /* ADC01_IN7 */
38 #define ADC01_IN7_PA7 \
39 	GD32_PINMUX_AFIO('A', 7, ANALOG, NORMP)
40 
41 /* ADC01_IN8 */
42 #define ADC01_IN8_PB0 \
43 	GD32_PINMUX_AFIO('B', 0, ANALOG, NORMP)
44 
45 /* ADC01_IN9 */
46 #define ADC01_IN9_PB1 \
47 	GD32_PINMUX_AFIO('B', 1, ANALOG, NORMP)
48 
49 /* ANALOG */
50 #define ANALOG_PA0 \
51 	GD32_PINMUX_AFIO('A', 0, ANALOG, NORMP)
52 #define ANALOG_PA1 \
53 	GD32_PINMUX_AFIO('A', 1, ANALOG, NORMP)
54 #define ANALOG_PA2 \
55 	GD32_PINMUX_AFIO('A', 2, ANALOG, NORMP)
56 #define ANALOG_PA3 \
57 	GD32_PINMUX_AFIO('A', 3, ANALOG, NORMP)
58 #define ANALOG_PA4 \
59 	GD32_PINMUX_AFIO('A', 4, ANALOG, NORMP)
60 #define ANALOG_PA5 \
61 	GD32_PINMUX_AFIO('A', 5, ANALOG, NORMP)
62 #define ANALOG_PA6 \
63 	GD32_PINMUX_AFIO('A', 6, ANALOG, NORMP)
64 #define ANALOG_PA7 \
65 	GD32_PINMUX_AFIO('A', 7, ANALOG, NORMP)
66 #define ANALOG_PA8 \
67 	GD32_PINMUX_AFIO('A', 8, ANALOG, NORMP)
68 #define ANALOG_PA9 \
69 	GD32_PINMUX_AFIO('A', 9, ANALOG, NORMP)
70 #define ANALOG_PA10 \
71 	GD32_PINMUX_AFIO('A', 10, ANALOG, NORMP)
72 #define ANALOG_PA11 \
73 	GD32_PINMUX_AFIO('A', 11, ANALOG, NORMP)
74 #define ANALOG_PA12 \
75 	GD32_PINMUX_AFIO('A', 12, ANALOG, NORMP)
76 #define ANALOG_PA13 \
77 	GD32_PINMUX_AFIO('A', 13, ANALOG, NORMP)
78 #define ANALOG_PA14 \
79 	GD32_PINMUX_AFIO('A', 14, ANALOG, NORMP)
80 #define ANALOG_PA15 \
81 	GD32_PINMUX_AFIO('A', 15, ANALOG, NORMP)
82 #define ANALOG_PB0 \
83 	GD32_PINMUX_AFIO('B', 0, ANALOG, NORMP)
84 #define ANALOG_PB1 \
85 	GD32_PINMUX_AFIO('B', 1, ANALOG, NORMP)
86 #define ANALOG_PB2 \
87 	GD32_PINMUX_AFIO('B', 2, ANALOG, NORMP)
88 #define ANALOG_PB3 \
89 	GD32_PINMUX_AFIO('B', 3, ANALOG, NORMP)
90 #define ANALOG_PB4 \
91 	GD32_PINMUX_AFIO('B', 4, ANALOG, NORMP)
92 #define ANALOG_PB5 \
93 	GD32_PINMUX_AFIO('B', 5, ANALOG, NORMP)
94 #define ANALOG_PB6 \
95 	GD32_PINMUX_AFIO('B', 6, ANALOG, NORMP)
96 #define ANALOG_PB7 \
97 	GD32_PINMUX_AFIO('B', 7, ANALOG, NORMP)
98 #define ANALOG_PB8 \
99 	GD32_PINMUX_AFIO('B', 8, ANALOG, NORMP)
100 #define ANALOG_PB9 \
101 	GD32_PINMUX_AFIO('B', 9, ANALOG, NORMP)
102 #define ANALOG_PB10 \
103 	GD32_PINMUX_AFIO('B', 10, ANALOG, NORMP)
104 #define ANALOG_PB11 \
105 	GD32_PINMUX_AFIO('B', 11, ANALOG, NORMP)
106 #define ANALOG_PB12 \
107 	GD32_PINMUX_AFIO('B', 12, ANALOG, NORMP)
108 #define ANALOG_PB13 \
109 	GD32_PINMUX_AFIO('B', 13, ANALOG, NORMP)
110 #define ANALOG_PB14 \
111 	GD32_PINMUX_AFIO('B', 14, ANALOG, NORMP)
112 #define ANALOG_PB15 \
113 	GD32_PINMUX_AFIO('B', 15, ANALOG, NORMP)
114 #define ANALOG_PC13 \
115 	GD32_PINMUX_AFIO('C', 13, ANALOG, NORMP)
116 #define ANALOG_PC14 \
117 	GD32_PINMUX_AFIO('C', 14, ANALOG, NORMP)
118 #define ANALOG_PC15 \
119 	GD32_PINMUX_AFIO('C', 15, ANALOG, NORMP)
120 #define ANALOG_PD0 \
121 	GD32_PINMUX_AFIO('D', 0, ANALOG, NORMP)
122 #define ANALOG_PD1 \
123 	GD32_PINMUX_AFIO('D', 1, ANALOG, NORMP)
124 
125 /* CK_OUT0 */
126 #define CK_OUT0_PA8 \
127 	GD32_PINMUX_AFIO('A', 8, ALTERNATE, NORMP)
128 
129 /* CTC_SYNC */
130 #define CTC_SYNC_PA8 \
131 	GD32_PINMUX_AFIO('A', 8, ALTERNATE, NORMP)
132 
133 /* DAC_OUT0 */
134 #define DAC_OUT0_PA4 \
135 	GD32_PINMUX_AFIO('A', 4, ANALOG, NORMP)
136 
137 /* DAC_OUT1 */
138 #define DAC_OUT1_PA5 \
139 	GD32_PINMUX_AFIO('A', 5, ANALOG, NORMP)
140 
141 /* I2C0_SCL */
142 #define I2C0_SCL_PB6_NORMP \
143 	GD32_PINMUX_AFIO('B', 6, ALTERNATE, I2C0_NORMP)
144 #define I2C0_SCL_PB8_RMP \
145 	GD32_PINMUX_AFIO('B', 8, ALTERNATE, I2C0_RMP)
146 
147 /* I2C0_SDA */
148 #define I2C0_SDA_PB7_NORMP \
149 	GD32_PINMUX_AFIO('B', 7, ALTERNATE, I2C0_NORMP)
150 #define I2C0_SDA_PB9_RMP \
151 	GD32_PINMUX_AFIO('B', 9, ALTERNATE, I2C0_RMP)
152 
153 /* I2C0_SMBA */
154 #define I2C0_SMBA_PB5 \
155 	GD32_PINMUX_AFIO('B', 5, ALTERNATE, NORMP)
156 
157 /* I2C0_TXFRAME */
158 #define I2C0_TXFRAME_PB4 \
159 	GD32_PINMUX_AFIO('B', 4, ALTERNATE, NORMP)
160 
161 /* I2C1_SCL */
162 #define I2C1_SCL_PB10 \
163 	GD32_PINMUX_AFIO('B', 10, ALTERNATE, NORMP)
164 
165 /* I2C1_SDA */
166 #define I2C1_SDA_PB11 \
167 	GD32_PINMUX_AFIO('B', 11, ALTERNATE, NORMP)
168 
169 /* I2C1_SMBA */
170 #define I2C1_SMBA_PB12 \
171 	GD32_PINMUX_AFIO('B', 12, ALTERNATE, NORMP)
172 
173 /* I2C1_TXFRAME */
174 #define I2C1_TXFRAME_PB13 \
175 	GD32_PINMUX_AFIO('B', 13, ALTERNATE, NORMP)
176 
177 /* I2S1_CK */
178 #define I2S1_CK_PB13 \
179 	GD32_PINMUX_AFIO('B', 13, ALTERNATE, NORMP)
180 
181 /* I2S1_SD */
182 #define I2S1_SD_PB15_INP \
183 	GD32_PINMUX_AFIO('B', 15, GPIO_IN, NORMP)
184 #define I2S1_SD_PB15_OUT \
185 	GD32_PINMUX_AFIO('B', 15, ALTERNATE, NORMP)
186 
187 /* I2S1_WS */
188 #define I2S1_WS_PB12_INP \
189 	GD32_PINMUX_AFIO('B', 12, GPIO_IN, NORMP)
190 #define I2S1_WS_PB12_OUT \
191 	GD32_PINMUX_AFIO('B', 12, ALTERNATE, NORMP)
192 
193 /* I2S2_CK */
194 #define I2S2_CK_PB3_NORMP \
195 	GD32_PINMUX_AFIO('B', 3, ALTERNATE, I2S2_NORMP)
196 
197 /* I2S2_SD */
198 #define I2S2_SD_PB5_INP_NORMP \
199 	GD32_PINMUX_AFIO('B', 5, GPIO_IN, I2S2_NORMP)
200 #define I2S2_SD_PB5_OUT_NORMP \
201 	GD32_PINMUX_AFIO('B', 5, ALTERNATE, I2S2_NORMP)
202 
203 /* I2S2_WS */
204 #define I2S2_WS_PA15_INP_NORMP \
205 	GD32_PINMUX_AFIO('A', 15, GPIO_IN, I2S2_NORMP)
206 #define I2S2_WS_PA15_OUT_NORMP \
207 	GD32_PINMUX_AFIO('A', 15, ALTERNATE, I2S2_NORMP)
208 #define I2S2_WS_PA4_INP_RMP \
209 	GD32_PINMUX_AFIO('A', 4, GPIO_IN, I2S2_RMP)
210 #define I2S2_WS_PA4_OUT_RMP \
211 	GD32_PINMUX_AFIO('A', 4, ALTERNATE, I2S2_RMP)
212 
213 /* RTC_TAMPER */
214 #define RTC_TAMPER_PC13 \
215 	GD32_PINMUX_AFIO('C', 13, GPIO_IN, NORMP)
216 
217 /* SPI0_IO2 */
218 #define SPI0_IO2_PA2_NORMP \
219 	GD32_PINMUX_AFIO('A', 2, ALTERNATE, SPI0_NORMP)
220 #define SPI0_IO2_PB6_RMP \
221 	GD32_PINMUX_AFIO('B', 6, ALTERNATE, SPI0_RMP)
222 
223 /* SPI0_IO3 */
224 #define SPI0_IO3_PA3_NORMP \
225 	GD32_PINMUX_AFIO('A', 3, ALTERNATE, SPI0_NORMP)
226 #define SPI0_IO3_PB7_RMP \
227 	GD32_PINMUX_AFIO('B', 7, ALTERNATE, SPI0_RMP)
228 
229 /* SPI0_MISO */
230 #define SPI0_MISO_PA6_INP_NORMP \
231 	GD32_PINMUX_AFIO('A', 6, GPIO_IN, SPI0_NORMP)
232 #define SPI0_MISO_PA6_OUT_NORMP \
233 	GD32_PINMUX_AFIO('A', 6, ALTERNATE, SPI0_NORMP)
234 #define SPI0_MISO_PB4_INP_RMP \
235 	GD32_PINMUX_AFIO('B', 4, GPIO_IN, SPI0_RMP)
236 #define SPI0_MISO_PB4_OUT_RMP \
237 	GD32_PINMUX_AFIO('B', 4, ALTERNATE, SPI0_RMP)
238 
239 /* SPI0_MOSI */
240 #define SPI0_MOSI_PA7_INP_NORMP \
241 	GD32_PINMUX_AFIO('A', 7, GPIO_IN, SPI0_NORMP)
242 #define SPI0_MOSI_PA7_OUT_NORMP \
243 	GD32_PINMUX_AFIO('A', 7, ALTERNATE, SPI0_NORMP)
244 #define SPI0_MOSI_PB5_INP_RMP \
245 	GD32_PINMUX_AFIO('B', 5, GPIO_IN, SPI0_RMP)
246 #define SPI0_MOSI_PB5_OUT_RMP \
247 	GD32_PINMUX_AFIO('B', 5, ALTERNATE, SPI0_RMP)
248 
249 /* SPI0_NSS */
250 #define SPI0_NSS_PA4_INP_NORMP \
251 	GD32_PINMUX_AFIO('A', 4, GPIO_IN, SPI0_NORMP)
252 #define SPI0_NSS_PA4_OUT_NORMP \
253 	GD32_PINMUX_AFIO('A', 4, ALTERNATE, SPI0_NORMP)
254 #define SPI0_NSS_PA15_INP_RMP \
255 	GD32_PINMUX_AFIO('A', 15, GPIO_IN, SPI0_RMP)
256 #define SPI0_NSS_PA15_OUT_RMP \
257 	GD32_PINMUX_AFIO('A', 15, ALTERNATE, SPI0_RMP)
258 
259 /* SPI0_SCK */
260 #define SPI0_SCK_PA5_INP_NORMP \
261 	GD32_PINMUX_AFIO('A', 5, GPIO_IN, SPI0_NORMP)
262 #define SPI0_SCK_PA5_OUT_NORMP \
263 	GD32_PINMUX_AFIO('A', 5, ALTERNATE, SPI0_NORMP)
264 #define SPI0_SCK_PB3_INP_RMP \
265 	GD32_PINMUX_AFIO('B', 3, GPIO_IN, SPI0_RMP)
266 #define SPI0_SCK_PB3_OUT_RMP \
267 	GD32_PINMUX_AFIO('B', 3, ALTERNATE, SPI0_RMP)
268 
269 /* SPI1_MISO */
270 #define SPI1_MISO_PB14_INP \
271 	GD32_PINMUX_AFIO('B', 14, GPIO_IN, NORMP)
272 #define SPI1_MISO_PB14_OUT \
273 	GD32_PINMUX_AFIO('B', 14, ALTERNATE, NORMP)
274 
275 /* SPI1_MOSI */
276 #define SPI1_MOSI_PB15_INP \
277 	GD32_PINMUX_AFIO('B', 15, GPIO_IN, NORMP)
278 #define SPI1_MOSI_PB15_OUT \
279 	GD32_PINMUX_AFIO('B', 15, ALTERNATE, NORMP)
280 
281 /* SPI1_NSS */
282 #define SPI1_NSS_PB12_INP \
283 	GD32_PINMUX_AFIO('B', 12, GPIO_IN, NORMP)
284 #define SPI1_NSS_PB12_OUT \
285 	GD32_PINMUX_AFIO('B', 12, ALTERNATE, NORMP)
286 
287 /* SPI1_SCK */
288 #define SPI1_SCK_PB13_INP \
289 	GD32_PINMUX_AFIO('B', 13, GPIO_IN, NORMP)
290 #define SPI1_SCK_PB13_OUT \
291 	GD32_PINMUX_AFIO('B', 13, ALTERNATE, NORMP)
292 
293 /* SPI2_MISO */
294 #define SPI2_MISO_PB4_INP_NORMP \
295 	GD32_PINMUX_AFIO('B', 4, GPIO_IN, SPI2_NORMP)
296 #define SPI2_MISO_PB4_OUT_NORMP \
297 	GD32_PINMUX_AFIO('B', 4, ALTERNATE, SPI2_NORMP)
298 
299 /* SPI2_MOSI */
300 #define SPI2_MOSI_PB5_INP_NORMP \
301 	GD32_PINMUX_AFIO('B', 5, GPIO_IN, SPI2_NORMP)
302 #define SPI2_MOSI_PB5_OUT_NORMP \
303 	GD32_PINMUX_AFIO('B', 5, ALTERNATE, SPI2_NORMP)
304 
305 /* SPI2_NSS */
306 #define SPI2_NSS_PA15_INP_NORMP \
307 	GD32_PINMUX_AFIO('A', 15, GPIO_IN, SPI2_NORMP)
308 #define SPI2_NSS_PA15_OUT_NORMP \
309 	GD32_PINMUX_AFIO('A', 15, ALTERNATE, SPI2_NORMP)
310 #define SPI2_NSS_PA4_INP_RMP \
311 	GD32_PINMUX_AFIO('A', 4, GPIO_IN, SPI2_RMP)
312 #define SPI2_NSS_PA4_OUT_RMP \
313 	GD32_PINMUX_AFIO('A', 4, ALTERNATE, SPI2_RMP)
314 
315 /* SPI2_SCK */
316 #define SPI2_SCK_PB3_INP_NORMP \
317 	GD32_PINMUX_AFIO('B', 3, GPIO_IN, SPI2_NORMP)
318 #define SPI2_SCK_PB3_OUT_NORMP \
319 	GD32_PINMUX_AFIO('B', 3, ALTERNATE, SPI2_NORMP)
320 
321 /* TIMER0_BKIN */
322 #define TIMER0_BKIN_PB12_NORMP \
323 	GD32_PINMUX_AFIO('B', 12, GPIO_IN, TIMER0_NORMP)
324 #define TIMER0_BKIN_PA6_PRMP \
325 	GD32_PINMUX_AFIO('A', 6, GPIO_IN, TIMER0_PRMP)
326 
327 /* TIMER0_CH0 */
328 #define TIMER0_CH0_PA8_INP_NORMP \
329 	GD32_PINMUX_AFIO('A', 8, GPIO_IN, TIMER0_NORMP)
330 #define TIMER0_CH0_PA8_OUT_NORMP \
331 	GD32_PINMUX_AFIO('A', 8, ALTERNATE, TIMER0_NORMP)
332 #define TIMER0_CH0_PA8_INP_PRMP \
333 	GD32_PINMUX_AFIO('A', 8, GPIO_IN, TIMER0_PRMP)
334 #define TIMER0_CH0_PA8_OUT_PRMP \
335 	GD32_PINMUX_AFIO('A', 8, ALTERNATE, TIMER0_PRMP)
336 
337 /* TIMER0_CH0_ON */
338 #define TIMER0_CH0_ON_PB13_INP_NORMP \
339 	GD32_PINMUX_AFIO('B', 13, GPIO_IN, TIMER0_NORMP)
340 #define TIMER0_CH0_ON_PB13_OUT_NORMP \
341 	GD32_PINMUX_AFIO('B', 13, ALTERNATE, TIMER0_NORMP)
342 #define TIMER0_CH0_ON_PA7_INP_PRMP \
343 	GD32_PINMUX_AFIO('A', 7, GPIO_IN, TIMER0_PRMP)
344 #define TIMER0_CH0_ON_PA7_OUT_PRMP \
345 	GD32_PINMUX_AFIO('A', 7, ALTERNATE, TIMER0_PRMP)
346 
347 /* TIMER0_CH1 */
348 #define TIMER0_CH1_PA9_INP_NORMP \
349 	GD32_PINMUX_AFIO('A', 9, GPIO_IN, TIMER0_NORMP)
350 #define TIMER0_CH1_PA9_OUT_NORMP \
351 	GD32_PINMUX_AFIO('A', 9, ALTERNATE, TIMER0_NORMP)
352 #define TIMER0_CH1_PA9_INP_PRMP \
353 	GD32_PINMUX_AFIO('A', 9, GPIO_IN, TIMER0_PRMP)
354 #define TIMER0_CH1_PA9_OUT_PRMP \
355 	GD32_PINMUX_AFIO('A', 9, ALTERNATE, TIMER0_PRMP)
356 
357 /* TIMER0_CH1_ON */
358 #define TIMER0_CH1_ON_PB14_INP_NORMP \
359 	GD32_PINMUX_AFIO('B', 14, GPIO_IN, TIMER0_NORMP)
360 #define TIMER0_CH1_ON_PB14_OUT_NORMP \
361 	GD32_PINMUX_AFIO('B', 14, ALTERNATE, TIMER0_NORMP)
362 #define TIMER0_CH1_ON_PB0_INP_PRMP \
363 	GD32_PINMUX_AFIO('B', 0, GPIO_IN, TIMER0_PRMP)
364 #define TIMER0_CH1_ON_PB0_OUT_PRMP \
365 	GD32_PINMUX_AFIO('B', 0, ALTERNATE, TIMER0_PRMP)
366 
367 /* TIMER0_CH2 */
368 #define TIMER0_CH2_PA10_INP_NORMP \
369 	GD32_PINMUX_AFIO('A', 10, GPIO_IN, TIMER0_NORMP)
370 #define TIMER0_CH2_PA10_OUT_NORMP \
371 	GD32_PINMUX_AFIO('A', 10, ALTERNATE, TIMER0_NORMP)
372 #define TIMER0_CH2_PA10_INP_PRMP \
373 	GD32_PINMUX_AFIO('A', 10, GPIO_IN, TIMER0_PRMP)
374 #define TIMER0_CH2_PA10_OUT_PRMP \
375 	GD32_PINMUX_AFIO('A', 10, ALTERNATE, TIMER0_PRMP)
376 
377 /* TIMER0_CH2_ON */
378 #define TIMER0_CH2_ON_PB15_NORMP \
379 	GD32_PINMUX_AFIO('B', 15, ALTERNATE, TIMER0_NORMP)
380 #define TIMER0_CH2_ON_PB1_PRMP \
381 	GD32_PINMUX_AFIO('B', 1, ALTERNATE, TIMER0_PRMP)
382 
383 /* TIMER0_CH3 */
384 #define TIMER0_CH3_PA11_INP_NORMP \
385 	GD32_PINMUX_AFIO('A', 11, GPIO_IN, TIMER0_NORMP)
386 #define TIMER0_CH3_PA11_OUT_NORMP \
387 	GD32_PINMUX_AFIO('A', 11, ALTERNATE, TIMER0_NORMP)
388 #define TIMER0_CH3_PA11_INP_PRMP \
389 	GD32_PINMUX_AFIO('A', 11, GPIO_IN, TIMER0_PRMP)
390 #define TIMER0_CH3_PA11_OUT_PRMP \
391 	GD32_PINMUX_AFIO('A', 11, ALTERNATE, TIMER0_PRMP)
392 
393 /* TIMER0_ETI */
394 #define TIMER0_ETI_PA12_NORMP \
395 	GD32_PINMUX_AFIO('A', 12, GPIO_IN, TIMER0_NORMP)
396 #define TIMER0_ETI_PA12_PRMP \
397 	GD32_PINMUX_AFIO('A', 12, GPIO_IN, TIMER0_PRMP)
398 
399 /* TIMER10_CH0 */
400 #define TIMER10_CH0_PB9_INP \
401 	GD32_PINMUX_AFIO('B', 9, GPIO_IN, NORMP)
402 #define TIMER10_CH0_PB9_OUT \
403 	GD32_PINMUX_AFIO('B', 9, ALTERNATE, NORMP)
404 
405 /* TIMER11_CH0 */
406 #define TIMER11_CH0_PB14_INP \
407 	GD32_PINMUX_AFIO('B', 14, GPIO_IN, NORMP)
408 #define TIMER11_CH0_PB14_OUT \
409 	GD32_PINMUX_AFIO('B', 14, ALTERNATE, NORMP)
410 
411 /* TIMER11_CH11 */
412 #define TIMER11_CH11_PB15_INP \
413 	GD32_PINMUX_AFIO('B', 15, GPIO_IN, NORMP)
414 #define TIMER11_CH11_PB15_OUT \
415 	GD32_PINMUX_AFIO('B', 15, ALTERNATE, NORMP)
416 
417 /* TIMER12_CH0 */
418 #define TIMER12_CH0_PA6_INP \
419 	GD32_PINMUX_AFIO('A', 6, GPIO_IN, NORMP)
420 #define TIMER12_CH0_PA6_OUT \
421 	GD32_PINMUX_AFIO('A', 6, ALTERNATE, NORMP)
422 
423 /* TIMER13_CH0 */
424 #define TIMER13_CH0_PA7_INP \
425 	GD32_PINMUX_AFIO('A', 7, GPIO_IN, NORMP)
426 #define TIMER13_CH0_PA7_OUT \
427 	GD32_PINMUX_AFIO('A', 7, ALTERNATE, NORMP)
428 
429 /* TIMER1_CH0_ETI */
430 #define TIMER1_CH0_ETI_PA0 \
431 	GD32_PINMUX_AFIO('A', 0, GPIO_IN, NORMP)
432 
433 /* TIMER1_CH1 */
434 #define TIMER1_CH1_PA1_INP_NORMP \
435 	GD32_PINMUX_AFIO('A', 1, GPIO_IN, TIMER1_NORMP)
436 #define TIMER1_CH1_PA1_OUT_NORMP \
437 	GD32_PINMUX_AFIO('A', 1, ALTERNATE, TIMER1_NORMP)
438 #define TIMER1_CH1_PA1_INP_PRMP2 \
439 	GD32_PINMUX_AFIO('A', 1, GPIO_IN, TIMER1_PRMP2)
440 #define TIMER1_CH1_PA1_OUT_PRMP2 \
441 	GD32_PINMUX_AFIO('A', 1, ALTERNATE, TIMER1_PRMP2)
442 #define TIMER1_CH1_PB3_INP_PRMP1 \
443 	GD32_PINMUX_AFIO('B', 3, GPIO_IN, TIMER1_PRMP1)
444 #define TIMER1_CH1_PB3_OUT_PRMP1 \
445 	GD32_PINMUX_AFIO('B', 3, ALTERNATE, TIMER1_PRMP1)
446 #define TIMER1_CH1_PB3_INP_FRMP \
447 	GD32_PINMUX_AFIO('B', 3, GPIO_IN, TIMER1_FRMP)
448 #define TIMER1_CH1_PB3_OUT_FRMP \
449 	GD32_PINMUX_AFIO('B', 3, ALTERNATE, TIMER1_FRMP)
450 
451 /* TIMER1_CH2 */
452 #define TIMER1_CH2_PA2_INP_NORMP \
453 	GD32_PINMUX_AFIO('A', 2, GPIO_IN, TIMER1_NORMP)
454 #define TIMER1_CH2_PA2_OUT_NORMP \
455 	GD32_PINMUX_AFIO('A', 2, ALTERNATE, TIMER1_NORMP)
456 #define TIMER1_CH2_PA2_INP_PRMP1 \
457 	GD32_PINMUX_AFIO('A', 2, GPIO_IN, TIMER1_PRMP1)
458 #define TIMER1_CH2_PA2_OUT_PRMP1 \
459 	GD32_PINMUX_AFIO('A', 2, ALTERNATE, TIMER1_PRMP1)
460 #define TIMER1_CH2_PB10_INP_PRMP2 \
461 	GD32_PINMUX_AFIO('B', 10, GPIO_IN, TIMER1_PRMP2)
462 #define TIMER1_CH2_PB10_OUT_PRMP2 \
463 	GD32_PINMUX_AFIO('B', 10, ALTERNATE, TIMER1_PRMP2)
464 #define TIMER1_CH2_PB10_INP_FRMP \
465 	GD32_PINMUX_AFIO('B', 10, GPIO_IN, TIMER1_FRMP)
466 #define TIMER1_CH2_PB10_OUT_FRMP \
467 	GD32_PINMUX_AFIO('B', 10, ALTERNATE, TIMER1_FRMP)
468 
469 /* TIMER1_CH3 */
470 #define TIMER1_CH3_PA3_INP_NORMP \
471 	GD32_PINMUX_AFIO('A', 3, GPIO_IN, TIMER1_NORMP)
472 #define TIMER1_CH3_PA3_OUT_NORMP \
473 	GD32_PINMUX_AFIO('A', 3, ALTERNATE, TIMER1_NORMP)
474 #define TIMER1_CH3_PA3_INP_PRMP1 \
475 	GD32_PINMUX_AFIO('A', 3, GPIO_IN, TIMER1_PRMP1)
476 #define TIMER1_CH3_PA3_OUT_PRMP1 \
477 	GD32_PINMUX_AFIO('A', 3, ALTERNATE, TIMER1_PRMP1)
478 #define TIMER1_CH3_PB11_INP_PRMP2 \
479 	GD32_PINMUX_AFIO('B', 11, GPIO_IN, TIMER1_PRMP2)
480 #define TIMER1_CH3_PB11_OUT_PRMP2 \
481 	GD32_PINMUX_AFIO('B', 11, ALTERNATE, TIMER1_PRMP2)
482 #define TIMER1_CH3_PB11_INP_FRMP \
483 	GD32_PINMUX_AFIO('B', 11, GPIO_IN, TIMER1_FRMP)
484 #define TIMER1_CH3_PB11_OUT_FRMP \
485 	GD32_PINMUX_AFIO('B', 11, ALTERNATE, TIMER1_FRMP)
486 
487 /* TIMER2_CH0 */
488 #define TIMER2_CH0_PA6_INP_NORMP \
489 	GD32_PINMUX_AFIO('A', 6, GPIO_IN, TIMER2_NORMP)
490 #define TIMER2_CH0_PA6_OUT_NORMP \
491 	GD32_PINMUX_AFIO('A', 6, ALTERNATE, TIMER2_NORMP)
492 #define TIMER2_CH0_PB4_INP_PRMP \
493 	GD32_PINMUX_AFIO('B', 4, GPIO_IN, TIMER2_PRMP)
494 #define TIMER2_CH0_PB4_OUT_PRMP \
495 	GD32_PINMUX_AFIO('B', 4, ALTERNATE, TIMER2_PRMP)
496 
497 /* TIMER2_CH1 */
498 #define TIMER2_CH1_PA7_INP_NORMP \
499 	GD32_PINMUX_AFIO('A', 7, GPIO_IN, TIMER2_NORMP)
500 #define TIMER2_CH1_PA7_OUT_NORMP \
501 	GD32_PINMUX_AFIO('A', 7, ALTERNATE, TIMER2_NORMP)
502 #define TIMER2_CH1_PB5_INP_PRMP \
503 	GD32_PINMUX_AFIO('B', 5, GPIO_IN, TIMER2_PRMP)
504 #define TIMER2_CH1_PB5_OUT_PRMP \
505 	GD32_PINMUX_AFIO('B', 5, ALTERNATE, TIMER2_PRMP)
506 
507 /* TIMER2_CH2 */
508 #define TIMER2_CH2_PB0_INP_NORMP \
509 	GD32_PINMUX_AFIO('B', 0, GPIO_IN, TIMER2_NORMP)
510 #define TIMER2_CH2_PB0_OUT_NORMP \
511 	GD32_PINMUX_AFIO('B', 0, ALTERNATE, TIMER2_NORMP)
512 #define TIMER2_CH2_PB0_INP_PRMP \
513 	GD32_PINMUX_AFIO('B', 0, GPIO_IN, TIMER2_PRMP)
514 #define TIMER2_CH2_PB0_OUT_PRMP \
515 	GD32_PINMUX_AFIO('B', 0, ALTERNATE, TIMER2_PRMP)
516 
517 /* TIMER2_CH3 */
518 #define TIMER2_CH3_PB1_INP_NORMP \
519 	GD32_PINMUX_AFIO('B', 1, GPIO_IN, TIMER2_NORMP)
520 #define TIMER2_CH3_PB1_OUT_NORMP \
521 	GD32_PINMUX_AFIO('B', 1, ALTERNATE, TIMER2_NORMP)
522 #define TIMER2_CH3_PB1_INP_PRMP \
523 	GD32_PINMUX_AFIO('B', 1, GPIO_IN, TIMER2_PRMP)
524 #define TIMER2_CH3_PB1_OUT_PRMP \
525 	GD32_PINMUX_AFIO('B', 1, ALTERNATE, TIMER2_PRMP)
526 
527 /* TIMER3_CH0 */
528 #define TIMER3_CH0_PB6_INP_NORMP \
529 	GD32_PINMUX_AFIO('B', 6, GPIO_IN, TIMER3_NORMP)
530 #define TIMER3_CH0_PB6_OUT_NORMP \
531 	GD32_PINMUX_AFIO('B', 6, ALTERNATE, TIMER3_NORMP)
532 
533 /* TIMER3_CH1 */
534 #define TIMER3_CH1_PB7_INP_NORMP \
535 	GD32_PINMUX_AFIO('B', 7, GPIO_IN, TIMER3_NORMP)
536 #define TIMER3_CH1_PB7_OUT_NORMP \
537 	GD32_PINMUX_AFIO('B', 7, ALTERNATE, TIMER3_NORMP)
538 
539 /* TIMER3_CH2 */
540 #define TIMER3_CH2_PB8_INP_NORMP \
541 	GD32_PINMUX_AFIO('B', 8, GPIO_IN, TIMER3_NORMP)
542 #define TIMER3_CH2_PB8_OUT_NORMP \
543 	GD32_PINMUX_AFIO('B', 8, ALTERNATE, TIMER3_NORMP)
544 
545 /* TIMER3_CH3 */
546 #define TIMER3_CH3_PB9_INP_NORMP \
547 	GD32_PINMUX_AFIO('B', 9, GPIO_IN, TIMER3_NORMP)
548 #define TIMER3_CH3_PB9_OUT_NORMP \
549 	GD32_PINMUX_AFIO('B', 9, ALTERNATE, TIMER3_NORMP)
550 
551 /* TIMER4_CH0 */
552 #define TIMER4_CH0_PA0_INP \
553 	GD32_PINMUX_AFIO('A', 0, GPIO_IN, NORMP)
554 #define TIMER4_CH0_PA0_OUT \
555 	GD32_PINMUX_AFIO('A', 0, ALTERNATE, NORMP)
556 
557 /* TIMER4_CH1 */
558 #define TIMER4_CH1_PA1_INP \
559 	GD32_PINMUX_AFIO('A', 1, GPIO_IN, NORMP)
560 #define TIMER4_CH1_PA1_OUT \
561 	GD32_PINMUX_AFIO('A', 1, ALTERNATE, NORMP)
562 
563 /* TIMER4_CH2 */
564 #define TIMER4_CH2_PA2_INP \
565 	GD32_PINMUX_AFIO('A', 2, GPIO_IN, NORMP)
566 #define TIMER4_CH2_PA2_OUT \
567 	GD32_PINMUX_AFIO('A', 2, ALTERNATE, NORMP)
568 
569 /* TIMER4_CH3 */
570 #define TIMER4_CH3_PA3_INP \
571 	GD32_PINMUX_AFIO('A', 3, GPIO_IN, NORMP)
572 #define TIMER4_CH3_PA3_OUT \
573 	GD32_PINMUX_AFIO('A', 3, ALTERNATE, NORMP)
574 
575 /* TIMER8_CH0 */
576 #define TIMER8_CH0_PA2_INP \
577 	GD32_PINMUX_AFIO('A', 2, GPIO_IN, NORMP)
578 #define TIMER8_CH0_PA2_OUT \
579 	GD32_PINMUX_AFIO('A', 2, ALTERNATE, NORMP)
580 
581 /* TIMER8_CH1 */
582 #define TIMER8_CH1_PA3_INP \
583 	GD32_PINMUX_AFIO('A', 3, GPIO_IN, NORMP)
584 #define TIMER8_CH1_PA3_OUT \
585 	GD32_PINMUX_AFIO('A', 3, ALTERNATE, NORMP)
586 
587 /* TIMER9_CH0 */
588 #define TIMER9_CH0_PB8_INP \
589 	GD32_PINMUX_AFIO('B', 8, GPIO_IN, NORMP)
590 #define TIMER9_CH0_PB8_OUT \
591 	GD32_PINMUX_AFIO('B', 8, ALTERNATE, NORMP)
592 
593 /* USART0_CK */
594 #define USART0_CK_PA8 \
595 	GD32_PINMUX_AFIO('A', 8, ALTERNATE, NORMP)
596 
597 /* USART0_CTS */
598 #define USART0_CTS_PA11 \
599 	GD32_PINMUX_AFIO('A', 11, GPIO_IN, NORMP)
600 
601 /* USART0_RTS */
602 #define USART0_RTS_PA12 \
603 	GD32_PINMUX_AFIO('A', 12, ALTERNATE, NORMP)
604 
605 /* USART0_RX */
606 #define USART0_RX_PA10_NORMP \
607 	GD32_PINMUX_AFIO('A', 10, GPIO_IN, USART0_NORMP)
608 #define USART0_RX_PB7_RMP \
609 	GD32_PINMUX_AFIO('B', 7, GPIO_IN, USART0_RMP)
610 
611 /* USART0_TX */
612 #define USART0_TX_PA9_NORMP \
613 	GD32_PINMUX_AFIO('A', 9, ALTERNATE, USART0_NORMP)
614 #define USART0_TX_PB6_RMP \
615 	GD32_PINMUX_AFIO('B', 6, ALTERNATE, USART0_RMP)
616 
617 /* USART1_CK */
618 #define USART1_CK_PA4_NORMP \
619 	GD32_PINMUX_AFIO('A', 4, ALTERNATE, USART1_NORMP)
620 
621 /* USART1_CTS */
622 #define USART1_CTS_PA0_NORMP \
623 	GD32_PINMUX_AFIO('A', 0, GPIO_IN, USART1_NORMP)
624 
625 /* USART1_RTS */
626 #define USART1_RTS_PA1_NORMP \
627 	GD32_PINMUX_AFIO('A', 1, ALTERNATE, USART1_NORMP)
628 
629 /* USART1_RX */
630 #define USART1_RX_PA3_NORMP \
631 	GD32_PINMUX_AFIO('A', 3, GPIO_IN, USART1_NORMP)
632 
633 /* USART1_TX */
634 #define USART1_TX_PA2_NORMP \
635 	GD32_PINMUX_AFIO('A', 2, ALTERNATE, USART1_NORMP)
636 
637 /* USART2_CK */
638 #define USART2_CK_PB12_NORMP \
639 	GD32_PINMUX_AFIO('B', 12, ALTERNATE, USART2_NORMP)
640 
641 /* USART2_CTS */
642 #define USART2_CTS_PB13_NORMP \
643 	GD32_PINMUX_AFIO('B', 13, GPIO_IN, USART2_NORMP)
644 #define USART2_CTS_PB13_PRMP \
645 	GD32_PINMUX_AFIO('B', 13, GPIO_IN, USART2_PRMP)
646 
647 /* USART2_RTS */
648 #define USART2_RTS_PB14_NORMP \
649 	GD32_PINMUX_AFIO('B', 14, ALTERNATE, USART2_NORMP)
650 #define USART2_RTS_PB14_PRMP \
651 	GD32_PINMUX_AFIO('B', 14, ALTERNATE, USART2_PRMP)
652 
653 /* USART2_RX */
654 #define USART2_RX_PB11_NORMP \
655 	GD32_PINMUX_AFIO('B', 11, GPIO_IN, USART2_NORMP)
656 
657 /* USART2_TX */
658 #define USART2_TX_PB10_NORMP \
659 	GD32_PINMUX_AFIO('B', 10, ALTERNATE, USART2_NORMP)
660 
661 /* USBFS_DM */
662 #define USBFS_DM_PA11_INP \
663 	GD32_PINMUX_AFIO('A', 11, GPIO_IN, NORMP)
664 #define USBFS_DM_PA11_OUT \
665 	GD32_PINMUX_AFIO('A', 11, ALTERNATE, NORMP)
666 
667 /* USBFS_DP */
668 #define USBFS_DP_PA12_INP \
669 	GD32_PINMUX_AFIO('A', 12, GPIO_IN, NORMP)
670 #define USBFS_DP_PA12_OUT \
671 	GD32_PINMUX_AFIO('A', 12, ALTERNATE, NORMP)
672 
673 /* USBFS_ID */
674 #define USBFS_ID_PA10_INP \
675 	GD32_PINMUX_AFIO('A', 10, GPIO_IN, NORMP)
676 #define USBFS_ID_PA10_OUT \
677 	GD32_PINMUX_AFIO('A', 10, ALTERNATE, NORMP)
678 
679 /* USBFS_SOF */
680 #define USBFS_SOF_PA8 \
681 	GD32_PINMUX_AFIO('A', 8, ALTERNATE, NORMP)
682 
683 /* USBFS_VBUS */
684 #define USBFS_VBUS_PA9 \
685 	GD32_PINMUX_AFIO('A', 9, GPIO_IN, NORMP)
686 
687 /* WKUP */
688 #define WKUP_PA0 \
689 	GD32_PINMUX_AFIO('A', 0, GPIO_IN, NORMP)
690