/* * Autogenerated file * * SPDX-License-Identifier: Apache 2.0 */ #include "gd32e103xx-afio.h" /* ADC01_IN0 */ #define ADC01_IN0_PA0 \ GD32_PINMUX_AFIO('A', 0, ANALOG, NORMP) /* ADC01_IN1 */ #define ADC01_IN1_PA1 \ GD32_PINMUX_AFIO('A', 1, ANALOG, NORMP) /* ADC01_IN2 */ #define ADC01_IN2_PA2 \ GD32_PINMUX_AFIO('A', 2, ANALOG, NORMP) /* ADC01_IN3 */ #define ADC01_IN3_PA3 \ GD32_PINMUX_AFIO('A', 3, ANALOG, NORMP) /* ADC01_IN4 */ #define ADC01_IN4_PA4 \ GD32_PINMUX_AFIO('A', 4, ANALOG, NORMP) /* ADC01_IN5 */ #define ADC01_IN5_PA5 \ GD32_PINMUX_AFIO('A', 5, ANALOG, NORMP) /* ADC01_IN6 */ #define ADC01_IN6_PA6 \ GD32_PINMUX_AFIO('A', 6, ANALOG, NORMP) /* ADC01_IN7 */ #define ADC01_IN7_PA7 \ GD32_PINMUX_AFIO('A', 7, ANALOG, NORMP) /* ADC01_IN8 */ #define ADC01_IN8_PB0 \ GD32_PINMUX_AFIO('B', 0, ANALOG, NORMP) /* ADC01_IN9 */ #define ADC01_IN9_PB1 \ GD32_PINMUX_AFIO('B', 1, ANALOG, NORMP) /* ANALOG */ #define ANALOG_PA0 \ GD32_PINMUX_AFIO('A', 0, ANALOG, NORMP) #define ANALOG_PA1 \ GD32_PINMUX_AFIO('A', 1, ANALOG, NORMP) #define ANALOG_PA2 \ GD32_PINMUX_AFIO('A', 2, ANALOG, NORMP) #define ANALOG_PA3 \ GD32_PINMUX_AFIO('A', 3, ANALOG, NORMP) #define ANALOG_PA4 \ GD32_PINMUX_AFIO('A', 4, ANALOG, NORMP) #define ANALOG_PA5 \ GD32_PINMUX_AFIO('A', 5, ANALOG, NORMP) #define ANALOG_PA6 \ GD32_PINMUX_AFIO('A', 6, ANALOG, NORMP) #define ANALOG_PA7 \ GD32_PINMUX_AFIO('A', 7, ANALOG, NORMP) #define ANALOG_PA8 \ GD32_PINMUX_AFIO('A', 8, ANALOG, NORMP) #define ANALOG_PA9 \ GD32_PINMUX_AFIO('A', 9, ANALOG, NORMP) #define ANALOG_PA10 \ GD32_PINMUX_AFIO('A', 10, ANALOG, NORMP) #define ANALOG_PA11 \ GD32_PINMUX_AFIO('A', 11, ANALOG, NORMP) #define ANALOG_PA12 \ GD32_PINMUX_AFIO('A', 12, ANALOG, NORMP) #define ANALOG_PA13 \ GD32_PINMUX_AFIO('A', 13, ANALOG, NORMP) #define ANALOG_PA14 \ GD32_PINMUX_AFIO('A', 14, ANALOG, NORMP) #define ANALOG_PA15 \ GD32_PINMUX_AFIO('A', 15, ANALOG, NORMP) #define ANALOG_PB0 \ GD32_PINMUX_AFIO('B', 0, ANALOG, NORMP) #define ANALOG_PB1 \ GD32_PINMUX_AFIO('B', 1, ANALOG, NORMP) #define ANALOG_PB2 \ GD32_PINMUX_AFIO('B', 2, ANALOG, NORMP) #define ANALOG_PB3 \ GD32_PINMUX_AFIO('B', 3, ANALOG, NORMP) #define ANALOG_PB4 \ GD32_PINMUX_AFIO('B', 4, ANALOG, NORMP) #define ANALOG_PB5 \ GD32_PINMUX_AFIO('B', 5, ANALOG, NORMP) #define ANALOG_PB6 \ GD32_PINMUX_AFIO('B', 6, ANALOG, NORMP) #define ANALOG_PB7 \ GD32_PINMUX_AFIO('B', 7, ANALOG, NORMP) #define ANALOG_PB8 \ GD32_PINMUX_AFIO('B', 8, ANALOG, NORMP) #define ANALOG_PB9 \ GD32_PINMUX_AFIO('B', 9, ANALOG, NORMP) #define ANALOG_PB10 \ GD32_PINMUX_AFIO('B', 10, ANALOG, NORMP) #define ANALOG_PB11 \ GD32_PINMUX_AFIO('B', 11, ANALOG, NORMP) #define ANALOG_PB12 \ GD32_PINMUX_AFIO('B', 12, ANALOG, NORMP) #define ANALOG_PB13 \ GD32_PINMUX_AFIO('B', 13, ANALOG, NORMP) #define ANALOG_PB14 \ GD32_PINMUX_AFIO('B', 14, ANALOG, NORMP) #define ANALOG_PB15 \ GD32_PINMUX_AFIO('B', 15, ANALOG, NORMP) #define ANALOG_PC13 \ GD32_PINMUX_AFIO('C', 13, ANALOG, NORMP) #define ANALOG_PC14 \ GD32_PINMUX_AFIO('C', 14, ANALOG, NORMP) #define ANALOG_PC15 \ GD32_PINMUX_AFIO('C', 15, ANALOG, NORMP) #define ANALOG_PD0 \ GD32_PINMUX_AFIO('D', 0, ANALOG, NORMP) #define ANALOG_PD1 \ GD32_PINMUX_AFIO('D', 1, ANALOG, NORMP) /* CK_OUT0 */ #define CK_OUT0_PA8 \ GD32_PINMUX_AFIO('A', 8, ALTERNATE, NORMP) /* CTC_SYNC */ #define CTC_SYNC_PA8 \ GD32_PINMUX_AFIO('A', 8, ALTERNATE, NORMP) /* DAC_OUT0 */ #define DAC_OUT0_PA4 \ GD32_PINMUX_AFIO('A', 4, ANALOG, NORMP) /* DAC_OUT1 */ #define DAC_OUT1_PA5 \ GD32_PINMUX_AFIO('A', 5, ANALOG, NORMP) /* I2C0_SCL */ #define I2C0_SCL_PB6_NORMP \ GD32_PINMUX_AFIO('B', 6, ALTERNATE, I2C0_NORMP) #define I2C0_SCL_PB8_RMP \ GD32_PINMUX_AFIO('B', 8, ALTERNATE, I2C0_RMP) /* I2C0_SDA */ #define I2C0_SDA_PB7_NORMP \ GD32_PINMUX_AFIO('B', 7, ALTERNATE, I2C0_NORMP) #define I2C0_SDA_PB9_RMP \ GD32_PINMUX_AFIO('B', 9, ALTERNATE, I2C0_RMP) /* I2C0_SMBA */ #define I2C0_SMBA_PB5 \ GD32_PINMUX_AFIO('B', 5, ALTERNATE, NORMP) /* I2C0_TXFRAME */ #define I2C0_TXFRAME_PB4 \ GD32_PINMUX_AFIO('B', 4, ALTERNATE, NORMP) /* I2C1_SCL */ #define I2C1_SCL_PB10 \ GD32_PINMUX_AFIO('B', 10, ALTERNATE, NORMP) /* I2C1_SDA */ #define I2C1_SDA_PB11 \ GD32_PINMUX_AFIO('B', 11, ALTERNATE, NORMP) /* I2C1_SMBA */ #define I2C1_SMBA_PB12 \ GD32_PINMUX_AFIO('B', 12, ALTERNATE, NORMP) /* I2C1_TXFRAME */ #define I2C1_TXFRAME_PB13 \ GD32_PINMUX_AFIO('B', 13, ALTERNATE, NORMP) /* I2S1_CK */ #define I2S1_CK_PB13 \ GD32_PINMUX_AFIO('B', 13, ALTERNATE, NORMP) /* I2S1_SD */ #define I2S1_SD_PB15_INP \ GD32_PINMUX_AFIO('B', 15, GPIO_IN, NORMP) #define I2S1_SD_PB15_OUT \ GD32_PINMUX_AFIO('B', 15, ALTERNATE, NORMP) /* I2S1_WS */ #define I2S1_WS_PB12_INP \ GD32_PINMUX_AFIO('B', 12, GPIO_IN, NORMP) #define I2S1_WS_PB12_OUT \ GD32_PINMUX_AFIO('B', 12, ALTERNATE, NORMP) /* I2S2_CK */ #define I2S2_CK_PB3_NORMP \ GD32_PINMUX_AFIO('B', 3, ALTERNATE, I2S2_NORMP) /* I2S2_SD */ #define I2S2_SD_PB5_INP_NORMP \ GD32_PINMUX_AFIO('B', 5, GPIO_IN, I2S2_NORMP) #define I2S2_SD_PB5_OUT_NORMP \ GD32_PINMUX_AFIO('B', 5, ALTERNATE, I2S2_NORMP) /* I2S2_WS */ #define I2S2_WS_PA15_INP_NORMP \ GD32_PINMUX_AFIO('A', 15, GPIO_IN, I2S2_NORMP) #define I2S2_WS_PA15_OUT_NORMP \ GD32_PINMUX_AFIO('A', 15, ALTERNATE, I2S2_NORMP) #define I2S2_WS_PA4_INP_RMP \ GD32_PINMUX_AFIO('A', 4, GPIO_IN, I2S2_RMP) #define I2S2_WS_PA4_OUT_RMP \ GD32_PINMUX_AFIO('A', 4, ALTERNATE, I2S2_RMP) /* RTC_TAMPER */ #define RTC_TAMPER_PC13 \ GD32_PINMUX_AFIO('C', 13, GPIO_IN, NORMP) /* SPI0_IO2 */ #define SPI0_IO2_PA2_NORMP \ GD32_PINMUX_AFIO('A', 2, ALTERNATE, SPI0_NORMP) #define SPI0_IO2_PB6_RMP \ GD32_PINMUX_AFIO('B', 6, ALTERNATE, SPI0_RMP) /* SPI0_IO3 */ #define SPI0_IO3_PA3_NORMP \ GD32_PINMUX_AFIO('A', 3, ALTERNATE, SPI0_NORMP) #define SPI0_IO3_PB7_RMP \ GD32_PINMUX_AFIO('B', 7, ALTERNATE, SPI0_RMP) /* SPI0_MISO */ #define SPI0_MISO_PA6_INP_NORMP \ GD32_PINMUX_AFIO('A', 6, GPIO_IN, SPI0_NORMP) #define SPI0_MISO_PA6_OUT_NORMP \ GD32_PINMUX_AFIO('A', 6, ALTERNATE, SPI0_NORMP) #define SPI0_MISO_PB4_INP_RMP \ GD32_PINMUX_AFIO('B', 4, GPIO_IN, SPI0_RMP) #define SPI0_MISO_PB4_OUT_RMP \ GD32_PINMUX_AFIO('B', 4, ALTERNATE, SPI0_RMP) /* SPI0_MOSI */ #define SPI0_MOSI_PA7_INP_NORMP \ GD32_PINMUX_AFIO('A', 7, GPIO_IN, SPI0_NORMP) #define SPI0_MOSI_PA7_OUT_NORMP \ GD32_PINMUX_AFIO('A', 7, ALTERNATE, SPI0_NORMP) #define SPI0_MOSI_PB5_INP_RMP \ GD32_PINMUX_AFIO('B', 5, GPIO_IN, SPI0_RMP) #define SPI0_MOSI_PB5_OUT_RMP \ GD32_PINMUX_AFIO('B', 5, ALTERNATE, SPI0_RMP) /* SPI0_NSS */ #define SPI0_NSS_PA4_INP_NORMP \ GD32_PINMUX_AFIO('A', 4, GPIO_IN, SPI0_NORMP) #define SPI0_NSS_PA4_OUT_NORMP \ GD32_PINMUX_AFIO('A', 4, ALTERNATE, SPI0_NORMP) #define SPI0_NSS_PA15_INP_RMP \ GD32_PINMUX_AFIO('A', 15, GPIO_IN, SPI0_RMP) #define SPI0_NSS_PA15_OUT_RMP \ GD32_PINMUX_AFIO('A', 15, ALTERNATE, SPI0_RMP) /* SPI0_SCK */ #define SPI0_SCK_PA5_INP_NORMP \ GD32_PINMUX_AFIO('A', 5, GPIO_IN, SPI0_NORMP) #define SPI0_SCK_PA5_OUT_NORMP \ GD32_PINMUX_AFIO('A', 5, ALTERNATE, SPI0_NORMP) #define SPI0_SCK_PB3_INP_RMP \ GD32_PINMUX_AFIO('B', 3, GPIO_IN, SPI0_RMP) #define SPI0_SCK_PB3_OUT_RMP \ GD32_PINMUX_AFIO('B', 3, ALTERNATE, SPI0_RMP) /* SPI1_MISO */ #define SPI1_MISO_PB14_INP \ GD32_PINMUX_AFIO('B', 14, GPIO_IN, NORMP) #define SPI1_MISO_PB14_OUT \ GD32_PINMUX_AFIO('B', 14, ALTERNATE, NORMP) /* SPI1_MOSI */ #define SPI1_MOSI_PB15_INP \ GD32_PINMUX_AFIO('B', 15, GPIO_IN, NORMP) #define SPI1_MOSI_PB15_OUT \ GD32_PINMUX_AFIO('B', 15, ALTERNATE, NORMP) /* SPI1_NSS */ #define SPI1_NSS_PB12_INP \ GD32_PINMUX_AFIO('B', 12, GPIO_IN, NORMP) #define SPI1_NSS_PB12_OUT \ GD32_PINMUX_AFIO('B', 12, ALTERNATE, NORMP) /* SPI1_SCK */ #define SPI1_SCK_PB13_INP \ GD32_PINMUX_AFIO('B', 13, GPIO_IN, NORMP) #define SPI1_SCK_PB13_OUT \ GD32_PINMUX_AFIO('B', 13, ALTERNATE, NORMP) /* SPI2_MISO */ #define SPI2_MISO_PB4_INP_NORMP \ GD32_PINMUX_AFIO('B', 4, GPIO_IN, SPI2_NORMP) #define SPI2_MISO_PB4_OUT_NORMP \ GD32_PINMUX_AFIO('B', 4, ALTERNATE, SPI2_NORMP) /* SPI2_MOSI */ #define SPI2_MOSI_PB5_INP_NORMP \ GD32_PINMUX_AFIO('B', 5, GPIO_IN, SPI2_NORMP) #define SPI2_MOSI_PB5_OUT_NORMP \ GD32_PINMUX_AFIO('B', 5, ALTERNATE, SPI2_NORMP) /* SPI2_NSS */ #define SPI2_NSS_PA15_INP_NORMP \ GD32_PINMUX_AFIO('A', 15, GPIO_IN, SPI2_NORMP) #define SPI2_NSS_PA15_OUT_NORMP \ GD32_PINMUX_AFIO('A', 15, ALTERNATE, SPI2_NORMP) #define SPI2_NSS_PA4_INP_RMP \ GD32_PINMUX_AFIO('A', 4, GPIO_IN, SPI2_RMP) #define SPI2_NSS_PA4_OUT_RMP \ GD32_PINMUX_AFIO('A', 4, ALTERNATE, SPI2_RMP) /* SPI2_SCK */ #define SPI2_SCK_PB3_INP_NORMP \ GD32_PINMUX_AFIO('B', 3, GPIO_IN, SPI2_NORMP) #define SPI2_SCK_PB3_OUT_NORMP \ GD32_PINMUX_AFIO('B', 3, ALTERNATE, SPI2_NORMP) /* TIMER0_BKIN */ #define TIMER0_BKIN_PB12_NORMP \ GD32_PINMUX_AFIO('B', 12, GPIO_IN, TIMER0_NORMP) #define TIMER0_BKIN_PA6_PRMP \ GD32_PINMUX_AFIO('A', 6, GPIO_IN, TIMER0_PRMP) /* TIMER0_CH0 */ #define TIMER0_CH0_PA8_INP_NORMP \ GD32_PINMUX_AFIO('A', 8, GPIO_IN, TIMER0_NORMP) #define TIMER0_CH0_PA8_OUT_NORMP \ GD32_PINMUX_AFIO('A', 8, ALTERNATE, TIMER0_NORMP) #define TIMER0_CH0_PA8_INP_PRMP \ GD32_PINMUX_AFIO('A', 8, GPIO_IN, TIMER0_PRMP) #define TIMER0_CH0_PA8_OUT_PRMP \ GD32_PINMUX_AFIO('A', 8, ALTERNATE, TIMER0_PRMP) /* TIMER0_CH0_ON */ #define TIMER0_CH0_ON_PB13_INP_NORMP \ GD32_PINMUX_AFIO('B', 13, GPIO_IN, TIMER0_NORMP) #define TIMER0_CH0_ON_PB13_OUT_NORMP \ GD32_PINMUX_AFIO('B', 13, ALTERNATE, TIMER0_NORMP) #define TIMER0_CH0_ON_PA7_INP_PRMP \ GD32_PINMUX_AFIO('A', 7, GPIO_IN, TIMER0_PRMP) #define TIMER0_CH0_ON_PA7_OUT_PRMP \ GD32_PINMUX_AFIO('A', 7, ALTERNATE, TIMER0_PRMP) /* TIMER0_CH1 */ #define TIMER0_CH1_PA9_INP_NORMP \ GD32_PINMUX_AFIO('A', 9, GPIO_IN, TIMER0_NORMP) #define TIMER0_CH1_PA9_OUT_NORMP \ GD32_PINMUX_AFIO('A', 9, ALTERNATE, TIMER0_NORMP) #define TIMER0_CH1_PA9_INP_PRMP \ GD32_PINMUX_AFIO('A', 9, GPIO_IN, TIMER0_PRMP) #define TIMER0_CH1_PA9_OUT_PRMP \ GD32_PINMUX_AFIO('A', 9, ALTERNATE, TIMER0_PRMP) /* TIMER0_CH1_ON */ #define TIMER0_CH1_ON_PB14_INP_NORMP \ GD32_PINMUX_AFIO('B', 14, GPIO_IN, TIMER0_NORMP) #define TIMER0_CH1_ON_PB14_OUT_NORMP \ GD32_PINMUX_AFIO('B', 14, ALTERNATE, TIMER0_NORMP) #define TIMER0_CH1_ON_PB0_INP_PRMP \ GD32_PINMUX_AFIO('B', 0, GPIO_IN, TIMER0_PRMP) #define TIMER0_CH1_ON_PB0_OUT_PRMP \ GD32_PINMUX_AFIO('B', 0, ALTERNATE, TIMER0_PRMP) /* TIMER0_CH2 */ #define TIMER0_CH2_PA10_INP_NORMP \ GD32_PINMUX_AFIO('A', 10, GPIO_IN, TIMER0_NORMP) #define TIMER0_CH2_PA10_OUT_NORMP \ GD32_PINMUX_AFIO('A', 10, ALTERNATE, TIMER0_NORMP) #define TIMER0_CH2_PA10_INP_PRMP \ GD32_PINMUX_AFIO('A', 10, GPIO_IN, TIMER0_PRMP) #define TIMER0_CH2_PA10_OUT_PRMP \ GD32_PINMUX_AFIO('A', 10, ALTERNATE, TIMER0_PRMP) /* TIMER0_CH2_ON */ #define TIMER0_CH2_ON_PB15_NORMP \ GD32_PINMUX_AFIO('B', 15, ALTERNATE, TIMER0_NORMP) #define TIMER0_CH2_ON_PB1_PRMP \ GD32_PINMUX_AFIO('B', 1, ALTERNATE, TIMER0_PRMP) /* TIMER0_CH3 */ #define TIMER0_CH3_PA11_INP_NORMP \ GD32_PINMUX_AFIO('A', 11, GPIO_IN, TIMER0_NORMP) #define TIMER0_CH3_PA11_OUT_NORMP \ GD32_PINMUX_AFIO('A', 11, ALTERNATE, TIMER0_NORMP) #define TIMER0_CH3_PA11_INP_PRMP \ GD32_PINMUX_AFIO('A', 11, GPIO_IN, TIMER0_PRMP) #define TIMER0_CH3_PA11_OUT_PRMP \ GD32_PINMUX_AFIO('A', 11, ALTERNATE, TIMER0_PRMP) /* TIMER0_ETI */ #define TIMER0_ETI_PA12_NORMP \ GD32_PINMUX_AFIO('A', 12, GPIO_IN, TIMER0_NORMP) #define TIMER0_ETI_PA12_PRMP \ GD32_PINMUX_AFIO('A', 12, GPIO_IN, TIMER0_PRMP) /* TIMER10_CH0 */ #define TIMER10_CH0_PB9_INP \ GD32_PINMUX_AFIO('B', 9, GPIO_IN, NORMP) #define TIMER10_CH0_PB9_OUT \ GD32_PINMUX_AFIO('B', 9, ALTERNATE, NORMP) /* TIMER11_CH0 */ #define TIMER11_CH0_PB14_INP \ GD32_PINMUX_AFIO('B', 14, GPIO_IN, NORMP) #define TIMER11_CH0_PB14_OUT \ GD32_PINMUX_AFIO('B', 14, ALTERNATE, NORMP) /* TIMER11_CH11 */ #define TIMER11_CH11_PB15_INP \ GD32_PINMUX_AFIO('B', 15, GPIO_IN, NORMP) #define TIMER11_CH11_PB15_OUT \ GD32_PINMUX_AFIO('B', 15, ALTERNATE, NORMP) /* TIMER12_CH0 */ #define TIMER12_CH0_PA6_INP \ GD32_PINMUX_AFIO('A', 6, GPIO_IN, NORMP) #define TIMER12_CH0_PA6_OUT \ GD32_PINMUX_AFIO('A', 6, ALTERNATE, NORMP) /* TIMER13_CH0 */ #define TIMER13_CH0_PA7_INP \ GD32_PINMUX_AFIO('A', 7, GPIO_IN, NORMP) #define TIMER13_CH0_PA7_OUT \ GD32_PINMUX_AFIO('A', 7, ALTERNATE, NORMP) /* TIMER1_CH0_ETI */ #define TIMER1_CH0_ETI_PA0 \ GD32_PINMUX_AFIO('A', 0, GPIO_IN, NORMP) /* TIMER1_CH1 */ #define TIMER1_CH1_PA1_INP_NORMP \ GD32_PINMUX_AFIO('A', 1, GPIO_IN, TIMER1_NORMP) #define TIMER1_CH1_PA1_OUT_NORMP \ GD32_PINMUX_AFIO('A', 1, ALTERNATE, TIMER1_NORMP) #define TIMER1_CH1_PA1_INP_PRMP2 \ GD32_PINMUX_AFIO('A', 1, GPIO_IN, TIMER1_PRMP2) #define TIMER1_CH1_PA1_OUT_PRMP2 \ GD32_PINMUX_AFIO('A', 1, ALTERNATE, TIMER1_PRMP2) #define TIMER1_CH1_PB3_INP_PRMP1 \ GD32_PINMUX_AFIO('B', 3, GPIO_IN, TIMER1_PRMP1) #define TIMER1_CH1_PB3_OUT_PRMP1 \ GD32_PINMUX_AFIO('B', 3, ALTERNATE, TIMER1_PRMP1) #define TIMER1_CH1_PB3_INP_FRMP \ GD32_PINMUX_AFIO('B', 3, GPIO_IN, TIMER1_FRMP) #define TIMER1_CH1_PB3_OUT_FRMP \ GD32_PINMUX_AFIO('B', 3, ALTERNATE, TIMER1_FRMP) /* TIMER1_CH2 */ #define TIMER1_CH2_PA2_INP_NORMP \ GD32_PINMUX_AFIO('A', 2, GPIO_IN, TIMER1_NORMP) #define TIMER1_CH2_PA2_OUT_NORMP \ GD32_PINMUX_AFIO('A', 2, ALTERNATE, TIMER1_NORMP) #define TIMER1_CH2_PA2_INP_PRMP1 \ GD32_PINMUX_AFIO('A', 2, GPIO_IN, TIMER1_PRMP1) #define TIMER1_CH2_PA2_OUT_PRMP1 \ GD32_PINMUX_AFIO('A', 2, ALTERNATE, TIMER1_PRMP1) #define TIMER1_CH2_PB10_INP_PRMP2 \ GD32_PINMUX_AFIO('B', 10, GPIO_IN, TIMER1_PRMP2) #define TIMER1_CH2_PB10_OUT_PRMP2 \ GD32_PINMUX_AFIO('B', 10, ALTERNATE, TIMER1_PRMP2) #define TIMER1_CH2_PB10_INP_FRMP \ GD32_PINMUX_AFIO('B', 10, GPIO_IN, TIMER1_FRMP) #define TIMER1_CH2_PB10_OUT_FRMP \ GD32_PINMUX_AFIO('B', 10, ALTERNATE, TIMER1_FRMP) /* TIMER1_CH3 */ #define TIMER1_CH3_PA3_INP_NORMP \ GD32_PINMUX_AFIO('A', 3, GPIO_IN, TIMER1_NORMP) #define TIMER1_CH3_PA3_OUT_NORMP \ GD32_PINMUX_AFIO('A', 3, ALTERNATE, TIMER1_NORMP) #define TIMER1_CH3_PA3_INP_PRMP1 \ GD32_PINMUX_AFIO('A', 3, GPIO_IN, TIMER1_PRMP1) #define TIMER1_CH3_PA3_OUT_PRMP1 \ GD32_PINMUX_AFIO('A', 3, ALTERNATE, TIMER1_PRMP1) #define TIMER1_CH3_PB11_INP_PRMP2 \ GD32_PINMUX_AFIO('B', 11, GPIO_IN, TIMER1_PRMP2) #define TIMER1_CH3_PB11_OUT_PRMP2 \ GD32_PINMUX_AFIO('B', 11, ALTERNATE, TIMER1_PRMP2) #define TIMER1_CH3_PB11_INP_FRMP \ GD32_PINMUX_AFIO('B', 11, GPIO_IN, TIMER1_FRMP) #define TIMER1_CH3_PB11_OUT_FRMP \ GD32_PINMUX_AFIO('B', 11, ALTERNATE, TIMER1_FRMP) /* TIMER2_CH0 */ #define TIMER2_CH0_PA6_INP_NORMP \ GD32_PINMUX_AFIO('A', 6, GPIO_IN, TIMER2_NORMP) #define TIMER2_CH0_PA6_OUT_NORMP \ GD32_PINMUX_AFIO('A', 6, ALTERNATE, TIMER2_NORMP) #define TIMER2_CH0_PB4_INP_PRMP \ GD32_PINMUX_AFIO('B', 4, GPIO_IN, TIMER2_PRMP) #define TIMER2_CH0_PB4_OUT_PRMP \ GD32_PINMUX_AFIO('B', 4, ALTERNATE, TIMER2_PRMP) /* TIMER2_CH1 */ #define TIMER2_CH1_PA7_INP_NORMP \ GD32_PINMUX_AFIO('A', 7, GPIO_IN, TIMER2_NORMP) #define TIMER2_CH1_PA7_OUT_NORMP \ GD32_PINMUX_AFIO('A', 7, ALTERNATE, TIMER2_NORMP) #define TIMER2_CH1_PB5_INP_PRMP \ GD32_PINMUX_AFIO('B', 5, GPIO_IN, TIMER2_PRMP) #define TIMER2_CH1_PB5_OUT_PRMP \ GD32_PINMUX_AFIO('B', 5, ALTERNATE, TIMER2_PRMP) /* TIMER2_CH2 */ #define TIMER2_CH2_PB0_INP_NORMP \ GD32_PINMUX_AFIO('B', 0, GPIO_IN, TIMER2_NORMP) #define TIMER2_CH2_PB0_OUT_NORMP \ GD32_PINMUX_AFIO('B', 0, ALTERNATE, TIMER2_NORMP) #define TIMER2_CH2_PB0_INP_PRMP \ GD32_PINMUX_AFIO('B', 0, GPIO_IN, TIMER2_PRMP) #define TIMER2_CH2_PB0_OUT_PRMP \ GD32_PINMUX_AFIO('B', 0, ALTERNATE, TIMER2_PRMP) /* TIMER2_CH3 */ #define TIMER2_CH3_PB1_INP_NORMP \ GD32_PINMUX_AFIO('B', 1, GPIO_IN, TIMER2_NORMP) #define TIMER2_CH3_PB1_OUT_NORMP \ GD32_PINMUX_AFIO('B', 1, ALTERNATE, TIMER2_NORMP) #define TIMER2_CH3_PB1_INP_PRMP \ GD32_PINMUX_AFIO('B', 1, GPIO_IN, TIMER2_PRMP) #define TIMER2_CH3_PB1_OUT_PRMP \ GD32_PINMUX_AFIO('B', 1, ALTERNATE, TIMER2_PRMP) /* TIMER3_CH0 */ #define TIMER3_CH0_PB6_INP_NORMP \ GD32_PINMUX_AFIO('B', 6, GPIO_IN, TIMER3_NORMP) #define TIMER3_CH0_PB6_OUT_NORMP \ GD32_PINMUX_AFIO('B', 6, ALTERNATE, TIMER3_NORMP) /* TIMER3_CH1 */ #define TIMER3_CH1_PB7_INP_NORMP \ GD32_PINMUX_AFIO('B', 7, GPIO_IN, TIMER3_NORMP) #define TIMER3_CH1_PB7_OUT_NORMP \ GD32_PINMUX_AFIO('B', 7, ALTERNATE, TIMER3_NORMP) /* TIMER3_CH2 */ #define TIMER3_CH2_PB8_INP_NORMP \ GD32_PINMUX_AFIO('B', 8, GPIO_IN, TIMER3_NORMP) #define TIMER3_CH2_PB8_OUT_NORMP \ GD32_PINMUX_AFIO('B', 8, ALTERNATE, TIMER3_NORMP) /* TIMER3_CH3 */ #define TIMER3_CH3_PB9_INP_NORMP \ GD32_PINMUX_AFIO('B', 9, GPIO_IN, TIMER3_NORMP) #define TIMER3_CH3_PB9_OUT_NORMP \ GD32_PINMUX_AFIO('B', 9, ALTERNATE, TIMER3_NORMP) /* TIMER4_CH0 */ #define TIMER4_CH0_PA0_INP \ GD32_PINMUX_AFIO('A', 0, GPIO_IN, NORMP) #define TIMER4_CH0_PA0_OUT \ GD32_PINMUX_AFIO('A', 0, ALTERNATE, NORMP) /* TIMER4_CH1 */ #define TIMER4_CH1_PA1_INP \ GD32_PINMUX_AFIO('A', 1, GPIO_IN, NORMP) #define TIMER4_CH1_PA1_OUT \ GD32_PINMUX_AFIO('A', 1, ALTERNATE, NORMP) /* TIMER4_CH2 */ #define TIMER4_CH2_PA2_INP \ GD32_PINMUX_AFIO('A', 2, GPIO_IN, NORMP) #define TIMER4_CH2_PA2_OUT \ GD32_PINMUX_AFIO('A', 2, ALTERNATE, NORMP) /* TIMER4_CH3 */ #define TIMER4_CH3_PA3_INP \ GD32_PINMUX_AFIO('A', 3, GPIO_IN, NORMP) #define TIMER4_CH3_PA3_OUT \ GD32_PINMUX_AFIO('A', 3, ALTERNATE, NORMP) /* TIMER8_CH0 */ #define TIMER8_CH0_PA2_INP \ GD32_PINMUX_AFIO('A', 2, GPIO_IN, NORMP) #define TIMER8_CH0_PA2_OUT \ GD32_PINMUX_AFIO('A', 2, ALTERNATE, NORMP) /* TIMER8_CH1 */ #define TIMER8_CH1_PA3_INP \ GD32_PINMUX_AFIO('A', 3, GPIO_IN, NORMP) #define TIMER8_CH1_PA3_OUT \ GD32_PINMUX_AFIO('A', 3, ALTERNATE, NORMP) /* TIMER9_CH0 */ #define TIMER9_CH0_PB8_INP \ GD32_PINMUX_AFIO('B', 8, GPIO_IN, NORMP) #define TIMER9_CH0_PB8_OUT \ GD32_PINMUX_AFIO('B', 8, ALTERNATE, NORMP) /* USART0_CK */ #define USART0_CK_PA8 \ GD32_PINMUX_AFIO('A', 8, ALTERNATE, NORMP) /* USART0_CTS */ #define USART0_CTS_PA11 \ GD32_PINMUX_AFIO('A', 11, GPIO_IN, NORMP) /* USART0_RTS */ #define USART0_RTS_PA12 \ GD32_PINMUX_AFIO('A', 12, ALTERNATE, NORMP) /* USART0_RX */ #define USART0_RX_PA10_NORMP \ GD32_PINMUX_AFIO('A', 10, GPIO_IN, USART0_NORMP) #define USART0_RX_PB7_RMP \ GD32_PINMUX_AFIO('B', 7, GPIO_IN, USART0_RMP) /* USART0_TX */ #define USART0_TX_PA9_NORMP \ GD32_PINMUX_AFIO('A', 9, ALTERNATE, USART0_NORMP) #define USART0_TX_PB6_RMP \ GD32_PINMUX_AFIO('B', 6, ALTERNATE, USART0_RMP) /* USART1_CK */ #define USART1_CK_PA4_NORMP \ GD32_PINMUX_AFIO('A', 4, ALTERNATE, USART1_NORMP) /* USART1_CTS */ #define USART1_CTS_PA0_NORMP \ GD32_PINMUX_AFIO('A', 0, GPIO_IN, USART1_NORMP) /* USART1_RTS */ #define USART1_RTS_PA1_NORMP \ GD32_PINMUX_AFIO('A', 1, ALTERNATE, USART1_NORMP) /* USART1_RX */ #define USART1_RX_PA3_NORMP \ GD32_PINMUX_AFIO('A', 3, GPIO_IN, USART1_NORMP) /* USART1_TX */ #define USART1_TX_PA2_NORMP \ GD32_PINMUX_AFIO('A', 2, ALTERNATE, USART1_NORMP) /* USART2_CK */ #define USART2_CK_PB12_NORMP \ GD32_PINMUX_AFIO('B', 12, ALTERNATE, USART2_NORMP) /* USART2_CTS */ #define USART2_CTS_PB13_NORMP \ GD32_PINMUX_AFIO('B', 13, GPIO_IN, USART2_NORMP) #define USART2_CTS_PB13_PRMP \ GD32_PINMUX_AFIO('B', 13, GPIO_IN, USART2_PRMP) /* USART2_RTS */ #define USART2_RTS_PB14_NORMP \ GD32_PINMUX_AFIO('B', 14, ALTERNATE, USART2_NORMP) #define USART2_RTS_PB14_PRMP \ GD32_PINMUX_AFIO('B', 14, ALTERNATE, USART2_PRMP) /* USART2_RX */ #define USART2_RX_PB11_NORMP \ GD32_PINMUX_AFIO('B', 11, GPIO_IN, USART2_NORMP) /* USART2_TX */ #define USART2_TX_PB10_NORMP \ GD32_PINMUX_AFIO('B', 10, ALTERNATE, USART2_NORMP) /* USBFS_DM */ #define USBFS_DM_PA11_INP \ GD32_PINMUX_AFIO('A', 11, GPIO_IN, NORMP) #define USBFS_DM_PA11_OUT \ GD32_PINMUX_AFIO('A', 11, ALTERNATE, NORMP) /* USBFS_DP */ #define USBFS_DP_PA12_INP \ GD32_PINMUX_AFIO('A', 12, GPIO_IN, NORMP) #define USBFS_DP_PA12_OUT \ GD32_PINMUX_AFIO('A', 12, ALTERNATE, NORMP) /* USBFS_ID */ #define USBFS_ID_PA10_INP \ GD32_PINMUX_AFIO('A', 10, GPIO_IN, NORMP) #define USBFS_ID_PA10_OUT \ GD32_PINMUX_AFIO('A', 10, ALTERNATE, NORMP) /* USBFS_SOF */ #define USBFS_SOF_PA8 \ GD32_PINMUX_AFIO('A', 8, ALTERNATE, NORMP) /* USBFS_VBUS */ #define USBFS_VBUS_PA9 \ GD32_PINMUX_AFIO('A', 9, GPIO_IN, NORMP) /* WKUP */ #define WKUP_PA0 \ GD32_PINMUX_AFIO('A', 0, GPIO_IN, NORMP)