1 /*
2  * Autogenerated file
3  *
4  * SPDX-License-Identifier: Apache 2.0
5  */
6 
7 #include "gd32-af.h"
8 
9 /* ADC0_IN0 */
10 #define ADC0_IN0_PC11 \
11 	GD32_PINMUX_AF('C', 11, ANALOG)
12 
13 /* ADC0_IN1 */
14 #define ADC0_IN1_PC10 \
15 	GD32_PINMUX_AF('C', 10, ANALOG)
16 
17 /* ADC0_IN10 */
18 #define ADC0_IN10_PA4 \
19 	GD32_PINMUX_AF('A', 4, ANALOG)
20 
21 /* ADC0_IN11 */
22 #define ADC0_IN11_PA3 \
23 	GD32_PINMUX_AF('A', 3, ANALOG)
24 
25 /* ADC0_IN12 */
26 #define ADC0_IN12_PE12 \
27 	GD32_PINMUX_AF('E', 12, ANALOG)
28 
29 /* ADC0_IN13 */
30 #define ADC0_IN13_PE11 \
31 	GD32_PINMUX_AF('E', 11, ANALOG)
32 
33 /* ADC0_IN14 */
34 #define ADC0_IN14_PE10 \
35 	GD32_PINMUX_AF('E', 10, ANALOG)
36 
37 /* ADC0_IN15 */
38 #define ADC0_IN15_PE9 \
39 	GD32_PINMUX_AF('E', 9, ANALOG)
40 
41 /* ADC0_IN2 */
42 #define ADC0_IN2_PD10 \
43 	GD32_PINMUX_AF('D', 10, ANALOG)
44 
45 /* ADC0_IN3 */
46 #define ADC0_IN3_PD9 \
47 	GD32_PINMUX_AF('D', 9, ANALOG)
48 
49 /* ADC0_IN4 */
50 #define ADC0_IN4_PB14 \
51 	GD32_PINMUX_AF('B', 14, ANALOG)
52 
53 /* ADC0_IN5 */
54 #define ADC0_IN5_PB13 \
55 	GD32_PINMUX_AF('B', 13, ANALOG)
56 
57 /* ADC0_IN6 */
58 #define ADC0_IN6_PE14 \
59 	GD32_PINMUX_AF('E', 14, ANALOG)
60 
61 /* ADC0_IN7 */
62 #define ADC0_IN7_PE13 \
63 	GD32_PINMUX_AF('E', 13, ANALOG)
64 
65 /* ADC0_IN8 */
66 #define ADC0_IN8_PB2 \
67 	GD32_PINMUX_AF('B', 2, ANALOG)
68 #define ADC0_IN8_PC7 \
69 	GD32_PINMUX_AF('C', 7, ANALOG)
70 
71 /* ADC0_IN9 */
72 #define ADC0_IN9_PB1 \
73 	GD32_PINMUX_AF('B', 1, ANALOG)
74 #define ADC0_IN9_PC6 \
75 	GD32_PINMUX_AF('C', 6, ANALOG)
76 
77 /* ADC1_IN0 */
78 #define ADC1_IN0_PA11 \
79 	GD32_PINMUX_AF('A', 11, ANALOG)
80 
81 /* ADC1_IN1 */
82 #define ADC1_IN1_PA10 \
83 	GD32_PINMUX_AF('A', 10, ANALOG)
84 
85 /* ADC1_IN10 */
86 #define ADC1_IN10_PD4 \
87 	GD32_PINMUX_AF('D', 4, ANALOG)
88 
89 /* ADC1_IN11 */
90 #define ADC1_IN11_PD3 \
91 	GD32_PINMUX_AF('D', 3, ANALOG)
92 
93 /* ADC1_IN12 */
94 #define ADC1_IN12_PD2 \
95 	GD32_PINMUX_AF('D', 2, ANALOG)
96 
97 /* ADC1_IN13 */
98 #define ADC1_IN13_PD1 \
99 	GD32_PINMUX_AF('D', 1, ANALOG)
100 
101 /* ADC1_IN14 */
102 #define ADC1_IN14_PB14 \
103 	GD32_PINMUX_AF('B', 14, ANALOG)
104 #define ADC1_IN14_PD15 \
105 	GD32_PINMUX_AF('D', 15, ANALOG)
106 
107 /* ADC1_IN15 */
108 #define ADC1_IN15_PB13 \
109 	GD32_PINMUX_AF('B', 13, ANALOG)
110 #define ADC1_IN15_PD14 \
111 	GD32_PINMUX_AF('D', 14, ANALOG)
112 
113 /* ADC1_IN2 */
114 #define ADC1_IN2_PA9 \
115 	GD32_PINMUX_AF('A', 9, ANALOG)
116 
117 /* ADC1_IN3 */
118 #define ADC1_IN3_PA8 \
119 	GD32_PINMUX_AF('A', 8, ANALOG)
120 
121 /* ADC1_IN4 */
122 #define ADC1_IN4_PD0 \
123 	GD32_PINMUX_AF('D', 0, ANALOG)
124 
125 /* ADC1_IN5 */
126 #define ADC1_IN5_PC12 \
127 	GD32_PINMUX_AF('C', 12, ANALOG)
128 
129 /* ADC1_IN6 */
130 #define ADC1_IN6_PC9 \
131 	GD32_PINMUX_AF('C', 9, ANALOG)
132 
133 /* ADC1_IN7 */
134 #define ADC1_IN7_PC8 \
135 	GD32_PINMUX_AF('C', 8, ANALOG)
136 
137 /* ADC1_IN8 */
138 #define ADC1_IN8_PC7 \
139 	GD32_PINMUX_AF('C', 7, ANALOG)
140 
141 /* ADC1_IN9 */
142 #define ADC1_IN9_PC6 \
143 	GD32_PINMUX_AF('C', 6, ANALOG)
144 
145 /* ANALOG */
146 #define ANALOG_PA0 \
147 	GD32_PINMUX_AF('A', 0, ANALOG)
148 #define ANALOG_PA1 \
149 	GD32_PINMUX_AF('A', 1, ANALOG)
150 #define ANALOG_PA2 \
151 	GD32_PINMUX_AF('A', 2, ANALOG)
152 #define ANALOG_PA3 \
153 	GD32_PINMUX_AF('A', 3, ANALOG)
154 #define ANALOG_PA4 \
155 	GD32_PINMUX_AF('A', 4, ANALOG)
156 #define ANALOG_PA5 \
157 	GD32_PINMUX_AF('A', 5, ANALOG)
158 #define ANALOG_PA6 \
159 	GD32_PINMUX_AF('A', 6, ANALOG)
160 #define ANALOG_PA7 \
161 	GD32_PINMUX_AF('A', 7, ANALOG)
162 #define ANALOG_PA8 \
163 	GD32_PINMUX_AF('A', 8, ANALOG)
164 #define ANALOG_PA9 \
165 	GD32_PINMUX_AF('A', 9, ANALOG)
166 #define ANALOG_PA10 \
167 	GD32_PINMUX_AF('A', 10, ANALOG)
168 #define ANALOG_PA11 \
169 	GD32_PINMUX_AF('A', 11, ANALOG)
170 #define ANALOG_PA12 \
171 	GD32_PINMUX_AF('A', 12, ANALOG)
172 #define ANALOG_PA13 \
173 	GD32_PINMUX_AF('A', 13, ANALOG)
174 #define ANALOG_PA14 \
175 	GD32_PINMUX_AF('A', 14, ANALOG)
176 #define ANALOG_PA15 \
177 	GD32_PINMUX_AF('A', 15, ANALOG)
178 #define ANALOG_PB0 \
179 	GD32_PINMUX_AF('B', 0, ANALOG)
180 #define ANALOG_PB1 \
181 	GD32_PINMUX_AF('B', 1, ANALOG)
182 #define ANALOG_PB2 \
183 	GD32_PINMUX_AF('B', 2, ANALOG)
184 #define ANALOG_PB3 \
185 	GD32_PINMUX_AF('B', 3, ANALOG)
186 #define ANALOG_PB4 \
187 	GD32_PINMUX_AF('B', 4, ANALOG)
188 #define ANALOG_PB5 \
189 	GD32_PINMUX_AF('B', 5, ANALOG)
190 #define ANALOG_PB6 \
191 	GD32_PINMUX_AF('B', 6, ANALOG)
192 #define ANALOG_PB7 \
193 	GD32_PINMUX_AF('B', 7, ANALOG)
194 #define ANALOG_PB8 \
195 	GD32_PINMUX_AF('B', 8, ANALOG)
196 #define ANALOG_PB9 \
197 	GD32_PINMUX_AF('B', 9, ANALOG)
198 #define ANALOG_PB10 \
199 	GD32_PINMUX_AF('B', 10, ANALOG)
200 #define ANALOG_PB11 \
201 	GD32_PINMUX_AF('B', 11, ANALOG)
202 #define ANALOG_PB12 \
203 	GD32_PINMUX_AF('B', 12, ANALOG)
204 #define ANALOG_PB13 \
205 	GD32_PINMUX_AF('B', 13, ANALOG)
206 #define ANALOG_PB14 \
207 	GD32_PINMUX_AF('B', 14, ANALOG)
208 #define ANALOG_PB15 \
209 	GD32_PINMUX_AF('B', 15, ANALOG)
210 #define ANALOG_PC0 \
211 	GD32_PINMUX_AF('C', 0, ANALOG)
212 #define ANALOG_PC1 \
213 	GD32_PINMUX_AF('C', 1, ANALOG)
214 #define ANALOG_PC2 \
215 	GD32_PINMUX_AF('C', 2, ANALOG)
216 #define ANALOG_PC3 \
217 	GD32_PINMUX_AF('C', 3, ANALOG)
218 #define ANALOG_PC4 \
219 	GD32_PINMUX_AF('C', 4, ANALOG)
220 #define ANALOG_PC5 \
221 	GD32_PINMUX_AF('C', 5, ANALOG)
222 #define ANALOG_PC6 \
223 	GD32_PINMUX_AF('C', 6, ANALOG)
224 #define ANALOG_PC7 \
225 	GD32_PINMUX_AF('C', 7, ANALOG)
226 #define ANALOG_PC8 \
227 	GD32_PINMUX_AF('C', 8, ANALOG)
228 #define ANALOG_PC9 \
229 	GD32_PINMUX_AF('C', 9, ANALOG)
230 #define ANALOG_PC10 \
231 	GD32_PINMUX_AF('C', 10, ANALOG)
232 #define ANALOG_PC11 \
233 	GD32_PINMUX_AF('C', 11, ANALOG)
234 #define ANALOG_PC12 \
235 	GD32_PINMUX_AF('C', 12, ANALOG)
236 #define ANALOG_PC13 \
237 	GD32_PINMUX_AF('C', 13, ANALOG)
238 #define ANALOG_PC14 \
239 	GD32_PINMUX_AF('C', 14, ANALOG)
240 #define ANALOG_PC15 \
241 	GD32_PINMUX_AF('C', 15, ANALOG)
242 #define ANALOG_PD0 \
243 	GD32_PINMUX_AF('D', 0, ANALOG)
244 #define ANALOG_PD1 \
245 	GD32_PINMUX_AF('D', 1, ANALOG)
246 #define ANALOG_PD2 \
247 	GD32_PINMUX_AF('D', 2, ANALOG)
248 #define ANALOG_PD3 \
249 	GD32_PINMUX_AF('D', 3, ANALOG)
250 #define ANALOG_PD4 \
251 	GD32_PINMUX_AF('D', 4, ANALOG)
252 #define ANALOG_PD5 \
253 	GD32_PINMUX_AF('D', 5, ANALOG)
254 #define ANALOG_PD6 \
255 	GD32_PINMUX_AF('D', 6, ANALOG)
256 #define ANALOG_PD7 \
257 	GD32_PINMUX_AF('D', 7, ANALOG)
258 #define ANALOG_PD8 \
259 	GD32_PINMUX_AF('D', 8, ANALOG)
260 #define ANALOG_PD9 \
261 	GD32_PINMUX_AF('D', 9, ANALOG)
262 #define ANALOG_PD10 \
263 	GD32_PINMUX_AF('D', 10, ANALOG)
264 #define ANALOG_PD11 \
265 	GD32_PINMUX_AF('D', 11, ANALOG)
266 #define ANALOG_PD12 \
267 	GD32_PINMUX_AF('D', 12, ANALOG)
268 #define ANALOG_PD13 \
269 	GD32_PINMUX_AF('D', 13, ANALOG)
270 #define ANALOG_PD14 \
271 	GD32_PINMUX_AF('D', 14, ANALOG)
272 #define ANALOG_PD15 \
273 	GD32_PINMUX_AF('D', 15, ANALOG)
274 #define ANALOG_PE0 \
275 	GD32_PINMUX_AF('E', 0, ANALOG)
276 #define ANALOG_PE1 \
277 	GD32_PINMUX_AF('E', 1, ANALOG)
278 #define ANALOG_PE2 \
279 	GD32_PINMUX_AF('E', 2, ANALOG)
280 #define ANALOG_PE3 \
281 	GD32_PINMUX_AF('E', 3, ANALOG)
282 #define ANALOG_PE4 \
283 	GD32_PINMUX_AF('E', 4, ANALOG)
284 #define ANALOG_PE5 \
285 	GD32_PINMUX_AF('E', 5, ANALOG)
286 #define ANALOG_PE6 \
287 	GD32_PINMUX_AF('E', 6, ANALOG)
288 #define ANALOG_PE7 \
289 	GD32_PINMUX_AF('E', 7, ANALOG)
290 #define ANALOG_PE8 \
291 	GD32_PINMUX_AF('E', 8, ANALOG)
292 #define ANALOG_PE9 \
293 	GD32_PINMUX_AF('E', 9, ANALOG)
294 #define ANALOG_PE10 \
295 	GD32_PINMUX_AF('E', 10, ANALOG)
296 #define ANALOG_PE11 \
297 	GD32_PINMUX_AF('E', 11, ANALOG)
298 #define ANALOG_PE12 \
299 	GD32_PINMUX_AF('E', 12, ANALOG)
300 #define ANALOG_PE13 \
301 	GD32_PINMUX_AF('E', 13, ANALOG)
302 #define ANALOG_PE14 \
303 	GD32_PINMUX_AF('E', 14, ANALOG)
304 #define ANALOG_PE15 \
305 	GD32_PINMUX_AF('E', 15, ANALOG)
306 #define ANALOG_PF0 \
307 	GD32_PINMUX_AF('F', 0, ANALOG)
308 #define ANALOG_PF1 \
309 	GD32_PINMUX_AF('F', 1, ANALOG)
310 #define ANALOG_PF2 \
311 	GD32_PINMUX_AF('F', 2, ANALOG)
312 #define ANALOG_PF3 \
313 	GD32_PINMUX_AF('F', 3, ANALOG)
314 #define ANALOG_PF4 \
315 	GD32_PINMUX_AF('F', 4, ANALOG)
316 #define ANALOG_PF5 \
317 	GD32_PINMUX_AF('F', 5, ANALOG)
318 #define ANALOG_PF6 \
319 	GD32_PINMUX_AF('F', 6, ANALOG)
320 #define ANALOG_PF7 \
321 	GD32_PINMUX_AF('F', 7, ANALOG)
322 
323 /* CAN0_RX */
324 #define CAN0_RX_PA4 \
325 	GD32_PINMUX_AF('A', 4, AF6)
326 #define CAN0_RX_PB14 \
327 	GD32_PINMUX_AF('B', 14, AF6)
328 #define CAN0_RX_PF0 \
329 	GD32_PINMUX_AF('F', 0, AF6)
330 
331 /* CAN0_TX */
332 #define CAN0_TX_PA3 \
333 	GD32_PINMUX_AF('A', 3, AF6)
334 #define CAN0_TX_PB13 \
335 	GD32_PINMUX_AF('B', 13, AF6)
336 #define CAN0_TX_PC15 \
337 	GD32_PINMUX_AF('C', 15, AF6)
338 
339 /* CAN1_RX */
340 #define CAN1_RX_PD0 \
341 	GD32_PINMUX_AF('D', 0, AF6)
342 #define CAN1_RX_PD7 \
343 	GD32_PINMUX_AF('D', 7, AF6)
344 
345 /* CAN1_TX */
346 #define CAN1_TX_PC12 \
347 	GD32_PINMUX_AF('C', 12, AF6)
348 #define CAN1_TX_PD6 \
349 	GD32_PINMUX_AF('D', 6, AF6)
350 
351 /* CK_OUT */
352 #define CK_OUT_PC2 \
353 	GD32_PINMUX_AF('C', 2, AF0)
354 #define CK_OUT_PC13 \
355 	GD32_PINMUX_AF('C', 13, AF0)
356 
357 /* CK_OUT0 */
358 #define CK_OUT0_PA1 \
359 	GD32_PINMUX_AF('A', 1, AF0)
360 
361 /* CMP_OUT */
362 #define CMP_OUT_PB9 \
363 	GD32_PINMUX_AF('B', 9, AF7)
364 #define CMP_OUT_PF2 \
365 	GD32_PINMUX_AF('F', 2, AF7)
366 
367 /* DAC_OUT */
368 #define DAC_OUT_PA7 \
369 	GD32_PINMUX_AF('A', 7, ANALOG)
370 
371 /* EVENTOUT */
372 #define EVENTOUT_PA0 \
373 	GD32_PINMUX_AF('A', 0, AF9)
374 #define EVENTOUT_PA1 \
375 	GD32_PINMUX_AF('A', 1, AF9)
376 #define EVENTOUT_PA2 \
377 	GD32_PINMUX_AF('A', 2, AF9)
378 #define EVENTOUT_PA3 \
379 	GD32_PINMUX_AF('A', 3, AF9)
380 #define EVENTOUT_PA4 \
381 	GD32_PINMUX_AF('A', 4, AF9)
382 #define EVENTOUT_PA5 \
383 	GD32_PINMUX_AF('A', 5, AF9)
384 #define EVENTOUT_PA7 \
385 	GD32_PINMUX_AF('A', 7, AF9)
386 #define EVENTOUT_PA8 \
387 	GD32_PINMUX_AF('A', 8, AF9)
388 #define EVENTOUT_PA9 \
389 	GD32_PINMUX_AF('A', 9, AF9)
390 #define EVENTOUT_PA10 \
391 	GD32_PINMUX_AF('A', 10, AF9)
392 #define EVENTOUT_PA11 \
393 	GD32_PINMUX_AF('A', 11, AF9)
394 #define EVENTOUT_PA12 \
395 	GD32_PINMUX_AF('A', 12, AF9)
396 #define EVENTOUT_PA13 \
397 	GD32_PINMUX_AF('A', 13, AF9)
398 #define EVENTOUT_PA14 \
399 	GD32_PINMUX_AF('A', 14, AF9)
400 #define EVENTOUT_PA15 \
401 	GD32_PINMUX_AF('A', 15, AF9)
402 #define EVENTOUT_PB0 \
403 	GD32_PINMUX_AF('B', 0, AF9)
404 #define EVENTOUT_PB1 \
405 	GD32_PINMUX_AF('B', 1, AF9)
406 #define EVENTOUT_PB2 \
407 	GD32_PINMUX_AF('B', 2, AF9)
408 #define EVENTOUT_PB3 \
409 	GD32_PINMUX_AF('B', 3, AF9)
410 #define EVENTOUT_PB4 \
411 	GD32_PINMUX_AF('B', 4, AF9)
412 #define EVENTOUT_PB5 \
413 	GD32_PINMUX_AF('B', 5, AF9)
414 #define EVENTOUT_PB6 \
415 	GD32_PINMUX_AF('B', 6, AF9)
416 #define EVENTOUT_PB7 \
417 	GD32_PINMUX_AF('B', 7, AF9)
418 #define EVENTOUT_PB8 \
419 	GD32_PINMUX_AF('B', 8, AF9)
420 #define EVENTOUT_PB9 \
421 	GD32_PINMUX_AF('B', 9, AF9)
422 #define EVENTOUT_PB10 \
423 	GD32_PINMUX_AF('B', 10, AF9)
424 #define EVENTOUT_PB11 \
425 	GD32_PINMUX_AF('B', 11, AF9)
426 #define EVENTOUT_PB12 \
427 	GD32_PINMUX_AF('B', 12, AF9)
428 #define EVENTOUT_PB13 \
429 	GD32_PINMUX_AF('B', 13, AF9)
430 #define EVENTOUT_PB14 \
431 	GD32_PINMUX_AF('B', 14, AF9)
432 #define EVENTOUT_PB15 \
433 	GD32_PINMUX_AF('B', 15, AF9)
434 #define EVENTOUT_PC0 \
435 	GD32_PINMUX_AF('C', 0, AF9)
436 #define EVENTOUT_PC1 \
437 	GD32_PINMUX_AF('C', 1, AF9)
438 #define EVENTOUT_PC2 \
439 	GD32_PINMUX_AF('C', 2, AF9)
440 #define EVENTOUT_PC3 \
441 	GD32_PINMUX_AF('C', 3, AF9)
442 #define EVENTOUT_PC4 \
443 	GD32_PINMUX_AF('C', 4, AF9)
444 #define EVENTOUT_PC5 \
445 	GD32_PINMUX_AF('C', 5, AF9)
446 #define EVENTOUT_PC6 \
447 	GD32_PINMUX_AF('C', 6, AF9)
448 #define EVENTOUT_PC7 \
449 	GD32_PINMUX_AF('C', 7, AF9)
450 #define EVENTOUT_PC8 \
451 	GD32_PINMUX_AF('C', 8, AF9)
452 #define EVENTOUT_PC9 \
453 	GD32_PINMUX_AF('C', 9, AF9)
454 #define EVENTOUT_PC10 \
455 	GD32_PINMUX_AF('C', 10, AF9)
456 #define EVENTOUT_PC11 \
457 	GD32_PINMUX_AF('C', 11, AF9)
458 #define EVENTOUT_PC12 \
459 	GD32_PINMUX_AF('C', 12, AF9)
460 #define EVENTOUT_PC13 \
461 	GD32_PINMUX_AF('C', 13, AF9)
462 #define EVENTOUT_PC14 \
463 	GD32_PINMUX_AF('C', 14, AF9)
464 #define EVENTOUT_PC15 \
465 	GD32_PINMUX_AF('C', 15, AF9)
466 #define EVENTOUT_PD0 \
467 	GD32_PINMUX_AF('D', 0, AF9)
468 #define EVENTOUT_PD1 \
469 	GD32_PINMUX_AF('D', 1, AF9)
470 #define EVENTOUT_PD2 \
471 	GD32_PINMUX_AF('D', 2, AF9)
472 #define EVENTOUT_PD3 \
473 	GD32_PINMUX_AF('D', 3, AF9)
474 #define EVENTOUT_PD4 \
475 	GD32_PINMUX_AF('D', 4, AF9)
476 #define EVENTOUT_PD5 \
477 	GD32_PINMUX_AF('D', 5, AF9)
478 #define EVENTOUT_PD6 \
479 	GD32_PINMUX_AF('D', 6, AF9)
480 #define EVENTOUT_PD7 \
481 	GD32_PINMUX_AF('D', 7, AF9)
482 #define EVENTOUT_PD8 \
483 	GD32_PINMUX_AF('D', 8, AF9)
484 #define EVENTOUT_PD9 \
485 	GD32_PINMUX_AF('D', 9, AF9)
486 #define EVENTOUT_PD10 \
487 	GD32_PINMUX_AF('D', 10, AF9)
488 #define EVENTOUT_PD11 \
489 	GD32_PINMUX_AF('D', 11, AF9)
490 #define EVENTOUT_PD12 \
491 	GD32_PINMUX_AF('D', 12, AF9)
492 #define EVENTOUT_PD13 \
493 	GD32_PINMUX_AF('D', 13, AF9)
494 #define EVENTOUT_PD14 \
495 	GD32_PINMUX_AF('D', 14, AF9)
496 #define EVENTOUT_PD15 \
497 	GD32_PINMUX_AF('D', 15, AF9)
498 #define EVENTOUT_PE0 \
499 	GD32_PINMUX_AF('E', 0, AF9)
500 #define EVENTOUT_PE1 \
501 	GD32_PINMUX_AF('E', 1, AF9)
502 #define EVENTOUT_PE2 \
503 	GD32_PINMUX_AF('E', 2, AF9)
504 #define EVENTOUT_PE3 \
505 	GD32_PINMUX_AF('E', 3, AF9)
506 #define EVENTOUT_PE4 \
507 	GD32_PINMUX_AF('E', 4, AF9)
508 #define EVENTOUT_PE5 \
509 	GD32_PINMUX_AF('E', 5, AF9)
510 #define EVENTOUT_PE6 \
511 	GD32_PINMUX_AF('E', 6, AF9)
512 #define EVENTOUT_PE7 \
513 	GD32_PINMUX_AF('E', 7, AF9)
514 #define EVENTOUT_PE8 \
515 	GD32_PINMUX_AF('E', 8, AF9)
516 #define EVENTOUT_PE9 \
517 	GD32_PINMUX_AF('E', 9, AF9)
518 #define EVENTOUT_PE10 \
519 	GD32_PINMUX_AF('E', 10, AF9)
520 #define EVENTOUT_PE11 \
521 	GD32_PINMUX_AF('E', 11, AF9)
522 #define EVENTOUT_PE12 \
523 	GD32_PINMUX_AF('E', 12, AF9)
524 #define EVENTOUT_PE13 \
525 	GD32_PINMUX_AF('E', 13, AF9)
526 #define EVENTOUT_PE14 \
527 	GD32_PINMUX_AF('E', 14, AF9)
528 #define EVENTOUT_PE15 \
529 	GD32_PINMUX_AF('E', 15, AF9)
530 #define EVENTOUT_PF0 \
531 	GD32_PINMUX_AF('F', 0, AF9)
532 #define EVENTOUT_PF1 \
533 	GD32_PINMUX_AF('F', 1, AF9)
534 #define EVENTOUT_PF2 \
535 	GD32_PINMUX_AF('F', 2, AF9)
536 #define EVENTOUT_PF3 \
537 	GD32_PINMUX_AF('F', 3, AF9)
538 #define EVENTOUT_PF4 \
539 	GD32_PINMUX_AF('F', 4, AF9)
540 #define EVENTOUT_PF5 \
541 	GD32_PINMUX_AF('F', 5, AF9)
542 #define EVENTOUT_PF6 \
543 	GD32_PINMUX_AF('F', 6, AF9)
544 #define EVENTOUT_PF7 \
545 	GD32_PINMUX_AF('F', 7, AF9)
546 
547 /* I2C0_SCL */
548 #define I2C0_SCL_PA10 \
549 	GD32_PINMUX_AF('A', 10, AF3)
550 #define I2C0_SCL_PA14 \
551 	GD32_PINMUX_AF('A', 14, AF3)
552 #define I2C0_SCL_PC11 \
553 	GD32_PINMUX_AF('C', 11, AF3)
554 #define I2C0_SCL_PF6 \
555 	GD32_PINMUX_AF('F', 6, AF3)
556 
557 /* I2C0_SDA */
558 #define I2C0_SDA_PA11 \
559 	GD32_PINMUX_AF('A', 11, AF3)
560 #define I2C0_SDA_PA13 \
561 	GD32_PINMUX_AF('A', 13, AF3)
562 #define I2C0_SDA_PC10 \
563 	GD32_PINMUX_AF('C', 10, AF3)
564 #define I2C0_SDA_PF7 \
565 	GD32_PINMUX_AF('F', 7, AF3)
566 
567 /* I2C0_SMBA */
568 #define I2C0_SMBA_PA12 \
569 	GD32_PINMUX_AF('A', 12, AF3)
570 #define I2C0_SMBA_PB5 \
571 	GD32_PINMUX_AF('B', 5, AF3)
572 
573 /* I2C1_SCL */
574 #define I2C1_SCL_PB7 \
575 	GD32_PINMUX_AF('B', 7, AF5)
576 #define I2C1_SCL_PD6 \
577 	GD32_PINMUX_AF('D', 6, AF5)
578 #define I2C1_SCL_PE10 \
579 	GD32_PINMUX_AF('E', 10, AF5)
580 
581 /* I2C1_SDA */
582 #define I2C1_SDA_PB8 \
583 	GD32_PINMUX_AF('B', 8, AF5)
584 #define I2C1_SDA_PD7 \
585 	GD32_PINMUX_AF('D', 7, AF5)
586 #define I2C1_SDA_PE11 \
587 	GD32_PINMUX_AF('E', 11, AF5)
588 
589 /* I2C1_SMBA */
590 #define I2C1_SMBA_PB9 \
591 	GD32_PINMUX_AF('B', 9, AF5)
592 #define I2C1_SMBA_PD11 \
593 	GD32_PINMUX_AF('D', 11, AF5)
594 #define I2C1_SMBA_PE12 \
595 	GD32_PINMUX_AF('E', 12, AF5)
596 
597 /* I2S1_CK */
598 #define I2S1_CK_PC6 \
599 	GD32_PINMUX_AF('C', 6, AF4)
600 #define I2S1_CK_PE5 \
601 	GD32_PINMUX_AF('E', 5, AF4)
602 
603 /* I2S1_MCK */
604 #define I2S1_MCK_PC7 \
605 	GD32_PINMUX_AF('C', 7, AF4)
606 #define I2S1_MCK_PE6 \
607 	GD32_PINMUX_AF('E', 6, AF4)
608 
609 /* I2S1_SD */
610 #define I2S1_SD_PA9 \
611 	GD32_PINMUX_AF('A', 9, AF4)
612 #define I2S1_SD_PB6 \
613 	GD32_PINMUX_AF('B', 6, AF5)
614 #define I2S1_SD_PD14 \
615 	GD32_PINMUX_AF('D', 14, AF4)
616 
617 /* I2S1_WS */
618 #define I2S1_WS_PA8 \
619 	GD32_PINMUX_AF('A', 8, AF4)
620 #define I2S1_WS_PB5 \
621 	GD32_PINMUX_AF('B', 5, AF6)
622 #define I2S1_WS_PD1 \
623 	GD32_PINMUX_AF('D', 1, AF4)
624 #define I2S1_WS_PD10 \
625 	GD32_PINMUX_AF('D', 10, AF4)
626 #define I2S1_WS_PD13 \
627 	GD32_PINMUX_AF('D', 13, AF4)
628 
629 /* JTCK */
630 #define JTCK_PB8 \
631 	GD32_PINMUX_AF('B', 8, AF0)
632 
633 /* JTDI */
634 #define JTDI_PB7 \
635 	GD32_PINMUX_AF('B', 7, AF0)
636 
637 /* JTDO */
638 #define JTDO_PB4 \
639 	GD32_PINMUX_AF('B', 4, AF0)
640 
641 /* JTMS */
642 #define JTMS_PB9 \
643 	GD32_PINMUX_AF('B', 9, AF0)
644 
645 /* MFCOM_D0 */
646 #define MFCOM_D0_PB4 \
647 	GD32_PINMUX_AF('B', 4, AF6)
648 #define MFCOM_D0_PE5 \
649 	GD32_PINMUX_AF('E', 5, AF6)
650 #define MFCOM_D0_PE7 \
651 	GD32_PINMUX_AF('E', 7, AF6)
652 
653 /* MFCOM_D1 */
654 #define MFCOM_D1_PB3 \
655 	GD32_PINMUX_AF('B', 3, AF6)
656 #define MFCOM_D1_PE4 \
657 	GD32_PINMUX_AF('E', 4, AF6)
658 #define MFCOM_D1_PE8 \
659 	GD32_PINMUX_AF('E', 8, AF6)
660 
661 /* MFCOM_D2 */
662 #define MFCOM_D2_PC11 \
663 	GD32_PINMUX_AF('C', 11, AF6)
664 #define MFCOM_D2_PE3 \
665 	GD32_PINMUX_AF('E', 3, AF12)
666 
667 /* MFCOM_D3 */
668 #define MFCOM_D3_PC10 \
669 	GD32_PINMUX_AF('C', 10, AF6)
670 #define MFCOM_D3_PE2 \
671 	GD32_PINMUX_AF('E', 2, AF6)
672 
673 /* MFCOM_D4 */
674 #define MFCOM_D4_PA9 \
675 	GD32_PINMUX_AF('A', 9, AF6)
676 #define MFCOM_D4_PA11 \
677 	GD32_PINMUX_AF('A', 11, AF6)
678 #define MFCOM_D4_PC13 \
679 	GD32_PINMUX_AF('C', 13, AF6)
680 
681 /* MFCOM_D5 */
682 #define MFCOM_D5_PA8 \
683 	GD32_PINMUX_AF('A', 8, AF6)
684 #define MFCOM_D5_PA10 \
685 	GD32_PINMUX_AF('A', 10, AF6)
686 #define MFCOM_D5_PE6 \
687 	GD32_PINMUX_AF('E', 6, AF6)
688 
689 /* MFCOM_D6 */
690 #define MFCOM_D6_PA9 \
691 	GD32_PINMUX_AF('A', 9, AF5)
692 #define MFCOM_D6_PE1 \
693 	GD32_PINMUX_AF('E', 1, AF6)
694 #define MFCOM_D6_PF0 \
695 	GD32_PINMUX_AF('F', 0, AF7)
696 
697 /* MFCOM_D7 */
698 #define MFCOM_D7_PA8 \
699 	GD32_PINMUX_AF('A', 8, AF5)
700 #define MFCOM_D7_PC15 \
701 	GD32_PINMUX_AF('C', 15, AF7)
702 #define MFCOM_D7_PE0 \
703 	GD32_PINMUX_AF('E', 0, AF6)
704 
705 /* NJTRST */
706 #define NJTRST_PB3 \
707 	GD32_PINMUX_AF('B', 3, AF0)
708 
709 /* SPI0_IO2 */
710 #define SPI0_IO2_PB3 \
711 	GD32_PINMUX_AF('B', 3, AF4)
712 #define SPI0_IO2_PE15 \
713 	GD32_PINMUX_AF('E', 15, AF4)
714 
715 /* SPI0_IO3 */
716 #define SPI0_IO3_PB4 \
717 	GD32_PINMUX_AF('B', 4, AF4)
718 #define SPI0_IO3_PB10 \
719 	GD32_PINMUX_AF('B', 10, AF4)
720 
721 /* SPI0_MISO */
722 #define SPI0_MISO_PB5 \
723 	GD32_PINMUX_AF('B', 5, AF4)
724 #define SPI0_MISO_PE13 \
725 	GD32_PINMUX_AF('E', 13, AF4)
726 #define SPI0_MISO_PF5 \
727 	GD32_PINMUX_AF('F', 5, AF4)
728 
729 /* SPI0_MOSI */
730 #define SPI0_MOSI_PA2 \
731 	GD32_PINMUX_AF('A', 2, AF4)
732 #define SPI0_MOSI_PB13 \
733 	GD32_PINMUX_AF('B', 13, AF4)
734 #define SPI0_MOSI_PD4 \
735 	GD32_PINMUX_AF('D', 4, AF4)
736 
737 /* SPI0_NSS */
738 #define SPI0_NSS_PA1 \
739 	GD32_PINMUX_AF('A', 1, AF4)
740 #define SPI0_NSS_PB14 \
741 	GD32_PINMUX_AF('B', 14, AF3)
742 #define SPI0_NSS_PD2 \
743 	GD32_PINMUX_AF('D', 2, AF4)
744 #define SPI0_NSS_PD3 \
745 	GD32_PINMUX_AF('D', 3, AF4)
746 
747 /* SPI0_SCK */
748 #define SPI0_SCK_PB6 \
749 	GD32_PINMUX_AF('B', 6, AF4)
750 #define SPI0_SCK_PC0 \
751 	GD32_PINMUX_AF('C', 0, AF4)
752 #define SPI0_SCK_PE14 \
753 	GD32_PINMUX_AF('E', 14, AF4)
754 
755 /* SPI1_MISO */
756 #define SPI1_MISO_PD15 \
757 	GD32_PINMUX_AF('D', 15, AF4)
758 #define SPI1_MISO_PE4 \
759 	GD32_PINMUX_AF('E', 4, AF4)
760 
761 /* SPI1_MOSI */
762 #define SPI1_MOSI_PA9 \
763 	GD32_PINMUX_AF('A', 9, AF4)
764 #define SPI1_MOSI_PB6 \
765 	GD32_PINMUX_AF('B', 6, AF5)
766 #define SPI1_MOSI_PD14 \
767 	GD32_PINMUX_AF('D', 14, AF4)
768 
769 /* SPI1_NSS */
770 #define SPI1_NSS_PA8 \
771 	GD32_PINMUX_AF('A', 8, AF4)
772 #define SPI1_NSS_PB5 \
773 	GD32_PINMUX_AF('B', 5, AF5)
774 #define SPI1_NSS_PD1 \
775 	GD32_PINMUX_AF('D', 1, AF4)
776 #define SPI1_NSS_PD10 \
777 	GD32_PINMUX_AF('D', 10, AF4)
778 #define SPI1_NSS_PD13 \
779 	GD32_PINMUX_AF('D', 13, AF4)
780 
781 /* SPI1_SCK */
782 #define SPI1_SCK_PC6 \
783 	GD32_PINMUX_AF('C', 6, AF4)
784 #define SPI1_SCK_PE5 \
785 	GD32_PINMUX_AF('E', 5, AF4)
786 
787 /* SWCLK */
788 #define SWCLK_PB8 \
789 	GD32_PINMUX_AF('B', 8, AF0)
790 
791 /* SWDIO */
792 #define SWDIO_PB9 \
793 	GD32_PINMUX_AF('B', 9, AF0)
794 
795 /* TIMER0_BRKIN0 */
796 #define TIMER0_BRKIN0_PA8 \
797 	GD32_PINMUX_AF('A', 8, AF1)
798 #define TIMER0_BRKIN0_PD5 \
799 	GD32_PINMUX_AF('D', 5, AF7)
800 #define TIMER0_BRKIN0_PF2 \
801 	GD32_PINMUX_AF('F', 2, AF1)
802 
803 /* TIMER0_BRKIN1 */
804 #define TIMER0_BRKIN1_PD10 \
805 	GD32_PINMUX_AF('D', 10, AF2)
806 #define TIMER0_BRKIN1_PF1 \
807 	GD32_PINMUX_AF('F', 1, AF1)
808 
809 /* TIMER0_BRKIN2 */
810 #define TIMER0_BRKIN2_PD9 \
811 	GD32_PINMUX_AF('D', 9, AF2)
812 #define TIMER0_BRKIN2_PF4 \
813 	GD32_PINMUX_AF('F', 4, AF2)
814 
815 /* TIMER0_BRKIN3 */
816 #define TIMER0_BRKIN3_PC9 \
817 	GD32_PINMUX_AF('C', 9, AF1)
818 #define TIMER0_BRKIN3_PF3 \
819 	GD32_PINMUX_AF('F', 3, AF2)
820 
821 /* TIMER0_CH0 */
822 #define TIMER0_CH0_PB2 \
823 	GD32_PINMUX_AF('B', 2, AF1)
824 #define TIMER0_CH0_PC0 \
825 	GD32_PINMUX_AF('C', 0, AF1)
826 #define TIMER0_CH0_PC8 \
827 	GD32_PINMUX_AF('C', 8, AF1)
828 
829 /* TIMER0_CH1 */
830 #define TIMER0_CH1_PA4 \
831 	GD32_PINMUX_AF('A', 4, AF1)
832 #define TIMER0_CH1_PC6 \
833 	GD32_PINMUX_AF('C', 6, AF1)
834 #define TIMER0_CH1_PE5 \
835 	GD32_PINMUX_AF('E', 5, AF1)
836 
837 /* TIMER0_CH2 */
838 #define TIMER0_CH2_PA2 \
839 	GD32_PINMUX_AF('A', 2, AF1)
840 #define TIMER0_CH2_PD14 \
841 	GD32_PINMUX_AF('D', 14, AF1)
842 
843 /* TIMER0_CH3 */
844 #define TIMER0_CH3_PA0 \
845 	GD32_PINMUX_AF('A', 0, AF1)
846 #define TIMER0_CH3_PD12 \
847 	GD32_PINMUX_AF('D', 12, AF1)
848 
849 /* TIMER0_MCH0 */
850 #define TIMER0_MCH0_PB1 \
851 	GD32_PINMUX_AF('B', 1, AF1)
852 #define TIMER0_MCH0_PC7 \
853 	GD32_PINMUX_AF('C', 7, AF1)
854 #define TIMER0_MCH0_PF5 \
855 	GD32_PINMUX_AF('F', 5, AF1)
856 
857 /* TIMER0_MCH1 */
858 #define TIMER0_MCH1_PA3 \
859 	GD32_PINMUX_AF('A', 3, AF1)
860 #define TIMER0_MCH1_PD15 \
861 	GD32_PINMUX_AF('D', 15, AF1)
862 #define TIMER0_MCH1_PE4 \
863 	GD32_PINMUX_AF('E', 4, AF1)
864 
865 /* TIMER0_MCH2 */
866 #define TIMER0_MCH2_PA1 \
867 	GD32_PINMUX_AF('A', 1, AF1)
868 #define TIMER0_MCH2_PD13 \
869 	GD32_PINMUX_AF('D', 13, AF1)
870 
871 /* TIMER0_MCH3 */
872 #define TIMER0_MCH3_PC1 \
873 	GD32_PINMUX_AF('C', 1, AF1)
874 #define TIMER0_MCH3_PD11 \
875 	GD32_PINMUX_AF('D', 11, AF1)
876 
877 /* TIMER19_BRKIN0 */
878 #define TIMER19_BRKIN0_PC14 \
879 	GD32_PINMUX_AF('C', 14, AF2)
880 
881 /* TIMER19_BRKIN1 */
882 #define TIMER19_BRKIN1_PA7 \
883 	GD32_PINMUX_AF('A', 7, AF3)
884 #define TIMER19_BRKIN1_PF1 \
885 	GD32_PINMUX_AF('F', 1, AF2)
886 
887 /* TIMER19_BRKIN2 */
888 #define TIMER19_BRKIN2_PA6 \
889 	GD32_PINMUX_AF('A', 6, AF2)
890 #define TIMER19_BRKIN2_PE8 \
891 	GD32_PINMUX_AF('E', 8, AF2)
892 
893 /* TIMER19_BRKIN3 */
894 #define TIMER19_BRKIN3_PA5 \
895 	GD32_PINMUX_AF('A', 5, AF2)
896 #define TIMER19_BRKIN3_PE7 \
897 	GD32_PINMUX_AF('E', 7, AF2)
898 
899 /* TIMER19_CH0 */
900 #define TIMER19_CH0_PB0 \
901 	GD32_PINMUX_AF('B', 0, AF1)
902 #define TIMER19_CH0_PB7 \
903 	GD32_PINMUX_AF('B', 7, AF1)
904 #define TIMER19_CH0_PC5 \
905 	GD32_PINMUX_AF('C', 5, AF2)
906 #define TIMER19_CH0_PC11 \
907 	GD32_PINMUX_AF('C', 11, AF2)
908 #define TIMER19_CH0_PD6 \
909 	GD32_PINMUX_AF('D', 6, AF2)
910 #define TIMER19_CH0_PE5 \
911 	GD32_PINMUX_AF('E', 5, AF2)
912 
913 /* TIMER19_CH1 */
914 #define TIMER19_CH1_PB0 \
915 	GD32_PINMUX_AF('B', 0, AF2)
916 #define TIMER19_CH1_PB7 \
917 	GD32_PINMUX_AF('B', 7, AF2)
918 #define TIMER19_CH1_PC4 \
919 	GD32_PINMUX_AF('C', 4, AF1)
920 #define TIMER19_CH1_PC15 \
921 	GD32_PINMUX_AF('C', 15, AF2)
922 #define TIMER19_CH1_PD7 \
923 	GD32_PINMUX_AF('D', 7, AF2)
924 #define TIMER19_CH1_PF0 \
925 	GD32_PINMUX_AF('F', 0, AF1)
926 
927 /* TIMER19_CH2 */
928 #define TIMER19_CH2_PC3 \
929 	GD32_PINMUX_AF('C', 3, AF1)
930 #define TIMER19_CH2_PC13 \
931 	GD32_PINMUX_AF('C', 13, AF1)
932 
933 /* TIMER19_CH3 */
934 #define TIMER19_CH3_PB10 \
935 	GD32_PINMUX_AF('B', 10, AF2)
936 #define TIMER19_CH3_PE3 \
937 	GD32_PINMUX_AF('E', 3, AF0)
938 
939 /* TIMER19_MCH0 */
940 #define TIMER19_MCH0_PC5 \
941 	GD32_PINMUX_AF('C', 5, AF1)
942 #define TIMER19_MCH0_PC11 \
943 	GD32_PINMUX_AF('C', 11, AF1)
944 #define TIMER19_MCH0_PE4 \
945 	GD32_PINMUX_AF('E', 4, AF2)
946 
947 /* TIMER19_MCH1 */
948 #define TIMER19_MCH1_PA7 \
949 	GD32_PINMUX_AF('A', 7, AF1)
950 #define TIMER19_MCH1_PC15 \
951 	GD32_PINMUX_AF('C', 15, AF1)
952 
953 /* TIMER19_MCH2 */
954 #define TIMER19_MCH2_PC2 \
955 	GD32_PINMUX_AF('C', 2, AF1)
956 #define TIMER19_MCH2_PE6 \
957 	GD32_PINMUX_AF('E', 6, AF2)
958 
959 /* TIMER19_MCH3 */
960 #define TIMER19_MCH3_PE2 \
961 	GD32_PINMUX_AF('E', 2, AF2)
962 #define TIMER19_MCH3_PE15 \
963 	GD32_PINMUX_AF('E', 15, AF2)
964 
965 /* TIMER1_CH0 */
966 #define TIMER1_CH0_PE6 \
967 	GD32_PINMUX_AF('E', 6, AF1)
968 
969 /* TIMER1_CH1 */
970 #define TIMER1_CH1_PA7 \
971 	GD32_PINMUX_AF('A', 7, AF2)
972 
973 /* TIMER1_CH2 */
974 #define TIMER1_CH2_PB14 \
975 	GD32_PINMUX_AF('B', 14, AF1)
976 #define TIMER1_CH2_PD4 \
977 	GD32_PINMUX_AF('D', 4, AF2)
978 
979 /* TIMER1_CH3 */
980 #define TIMER1_CH3_PA3 \
981 	GD32_PINMUX_AF('A', 3, AF2)
982 #define TIMER1_CH3_PB11 \
983 	GD32_PINMUX_AF('B', 11, AF2)
984 
985 /* TIMER1_ETI */
986 #define TIMER1_ETI_PE6 \
987 	GD32_PINMUX_AF('E', 6, AF1)
988 
989 /* TIMER20_BRKIN0 */
990 #define TIMER20_BRKIN0_PD11 \
991 	GD32_PINMUX_AF('D', 11, AF2)
992 #define TIMER20_BRKIN0_PD12 \
993 	GD32_PINMUX_AF('D', 12, AF2)
994 
995 /* TIMER20_BRKIN1 */
996 #define TIMER20_BRKIN1_PC7 \
997 	GD32_PINMUX_AF('C', 7, AF2)
998 #define TIMER20_BRKIN1_PD5 \
999 	GD32_PINMUX_AF('D', 5, AF12)
1000 
1001 /* TIMER20_BRKIN2 */
1002 #define TIMER20_BRKIN2_PC8 \
1003 	GD32_PINMUX_AF('C', 8, AF2)
1004 #define TIMER20_BRKIN2_PE0 \
1005 	GD32_PINMUX_AF('E', 0, AF1)
1006 
1007 /* TIMER20_BRKIN3 */
1008 #define TIMER20_BRKIN3_PC9 \
1009 	GD32_PINMUX_AF('C', 9, AF2)
1010 #define TIMER20_BRKIN3_PE1 \
1011 	GD32_PINMUX_AF('E', 1, AF1)
1012 
1013 /* TIMER20_CH0 */
1014 #define TIMER20_CH0_PA11 \
1015 	GD32_PINMUX_AF('A', 11, AF1)
1016 #define TIMER20_CH0_PA15 \
1017 	GD32_PINMUX_AF('A', 15, AF1)
1018 
1019 /* TIMER20_CH1 */
1020 #define TIMER20_CH1_PA13 \
1021 	GD32_PINMUX_AF('A', 13, AF1)
1022 #define TIMER20_CH1_PD0 \
1023 	GD32_PINMUX_AF('D', 0, AF1)
1024 
1025 /* TIMER20_CH2 */
1026 #define TIMER20_CH2_PA9 \
1027 	GD32_PINMUX_AF('A', 9, AF1)
1028 #define TIMER20_CH2_PB12 \
1029 	GD32_PINMUX_AF('B', 12, AF1)
1030 
1031 /* TIMER20_CH3 */
1032 #define TIMER20_CH3_PB10 \
1033 	GD32_PINMUX_AF('B', 10, AF1)
1034 #define TIMER20_CH3_PD4 \
1035 	GD32_PINMUX_AF('D', 4, AF1)
1036 
1037 /* TIMER20_MCH0 */
1038 #define TIMER20_MCH0_PA10 \
1039 	GD32_PINMUX_AF('A', 10, AF1)
1040 #define TIMER20_MCH0_PA14 \
1041 	GD32_PINMUX_AF('A', 14, AF1)
1042 
1043 /* TIMER20_MCH1 */
1044 #define TIMER20_MCH1_PA12 \
1045 	GD32_PINMUX_AF('A', 12, AF1)
1046 #define TIMER20_MCH1_PC12 \
1047 	GD32_PINMUX_AF('C', 12, AF1)
1048 
1049 /* TIMER20_MCH2 */
1050 #define TIMER20_MCH2_PA8 \
1051 	GD32_PINMUX_AF('A', 8, AF2)
1052 #define TIMER20_MCH2_PB11 \
1053 	GD32_PINMUX_AF('B', 11, AF1)
1054 
1055 /* TIMER20_MCH3 */
1056 #define TIMER20_MCH3_PD3 \
1057 	GD32_PINMUX_AF('D', 3, AF1)
1058 #define TIMER20_MCH3_PE15 \
1059 	GD32_PINMUX_AF('E', 15, AF1)
1060 
1061 /* TIMER7_BRKIN0 */
1062 #define TIMER7_BRKIN0_PD5 \
1063 	GD32_PINMUX_AF('D', 5, AF12)
1064 #define TIMER7_BRKIN0_PD8 \
1065 	GD32_PINMUX_AF('D', 8, AF2)
1066 
1067 /* TIMER7_BRKIN1 */
1068 #define TIMER7_BRKIN1_PB5 \
1069 	GD32_PINMUX_AF('B', 5, AF2)
1070 #define TIMER7_BRKIN1_PB15 \
1071 	GD32_PINMUX_AF('B', 15, AF2)
1072 
1073 /* TIMER7_BRKIN2 */
1074 #define TIMER7_BRKIN2_PB6 \
1075 	GD32_PINMUX_AF('B', 6, AF2)
1076 #define TIMER7_BRKIN2_PE10 \
1077 	GD32_PINMUX_AF('E', 10, AF2)
1078 
1079 /* TIMER7_BRKIN3 */
1080 #define TIMER7_BRKIN3_PE0 \
1081 	GD32_PINMUX_AF('E', 0, AF2)
1082 #define TIMER7_BRKIN3_PE9 \
1083 	GD32_PINMUX_AF('E', 9, AF2)
1084 
1085 /* TIMER7_CH0 */
1086 #define TIMER7_CH0_PB8 \
1087 	GD32_PINMUX_AF('B', 8, AF1)
1088 #define TIMER7_CH0_PC10 \
1089 	GD32_PINMUX_AF('C', 10, AF2)
1090 #define TIMER7_CH0_PC12 \
1091 	GD32_PINMUX_AF('C', 12, AF2)
1092 #define TIMER7_CH0_PE13 \
1093 	GD32_PINMUX_AF('E', 13, AF2)
1094 #define TIMER7_CH0_PE14 \
1095 	GD32_PINMUX_AF('E', 14, AF1)
1096 
1097 /* TIMER7_CH1 */
1098 #define TIMER7_CH1_PB8 \
1099 	GD32_PINMUX_AF('B', 8, AF2)
1100 #define TIMER7_CH1_PD0 \
1101 	GD32_PINMUX_AF('D', 0, AF2)
1102 #define TIMER7_CH1_PD2 \
1103 	GD32_PINMUX_AF('D', 2, AF1)
1104 #define TIMER7_CH1_PE12 \
1105 	GD32_PINMUX_AF('E', 12, AF1)
1106 #define TIMER7_CH1_PE14 \
1107 	GD32_PINMUX_AF('E', 14, AF2)
1108 
1109 /* TIMER7_CH2 */
1110 #define TIMER7_CH2_PB4 \
1111 	GD32_PINMUX_AF('B', 4, AF1)
1112 #define TIMER7_CH2_PE8 \
1113 	GD32_PINMUX_AF('E', 8, AF1)
1114 
1115 /* TIMER7_CH3 */
1116 #define TIMER7_CH3_PB2 \
1117 	GD32_PINMUX_AF('B', 2, AF2)
1118 #define TIMER7_CH3_PD7 \
1119 	GD32_PINMUX_AF('D', 7, AF1)
1120 
1121 /* TIMER7_MCH0 */
1122 #define TIMER7_MCH0_PC10 \
1123 	GD32_PINMUX_AF('C', 10, AF1)
1124 #define TIMER7_MCH0_PE13 \
1125 	GD32_PINMUX_AF('E', 13, AF1)
1126 
1127 /* TIMER7_MCH1 */
1128 #define TIMER7_MCH1_PD1 \
1129 	GD32_PINMUX_AF('D', 1, AF1)
1130 #define TIMER7_MCH1_PE11 \
1131 	GD32_PINMUX_AF('E', 11, AF1)
1132 
1133 /* TIMER7_MCH2 */
1134 #define TIMER7_MCH2_PB3 \
1135 	GD32_PINMUX_AF('B', 3, AF1)
1136 #define TIMER7_MCH2_PE7 \
1137 	GD32_PINMUX_AF('E', 7, AF1)
1138 
1139 /* TIMER7_MCH3 */
1140 #define TIMER7_MCH3_PB1 \
1141 	GD32_PINMUX_AF('B', 1, AF2)
1142 #define TIMER7_MCH3_PD6 \
1143 	GD32_PINMUX_AF('D', 6, AF1)
1144 
1145 /* TIMER_ETI0 */
1146 #define TIMER_ETI0_PB13 \
1147 	GD32_PINMUX_AF('B', 13, AF0)
1148 
1149 /* TIMER_ETI1 */
1150 #define TIMER_ETI1_PB6 \
1151 	GD32_PINMUX_AF('B', 6, AF3)
1152 
1153 /* TIMER_ETI2 */
1154 #define TIMER_ETI2_PC15 \
1155 	GD32_PINMUX_AF('C', 15, AF0)
1156 
1157 /* TIMRE19_BRKIN0 */
1158 #define TIMRE19_BRKIN0_PF2 \
1159 	GD32_PINMUX_AF('F', 2, AF2)
1160 
1161 /* TRIGSEL_IN0 */
1162 #define TRIGSEL_IN0_PA1 \
1163 	GD32_PINMUX_AF('A', 1, AF7)
1164 
1165 /* TRIGSEL_IN1 */
1166 #define TRIGSEL_IN1_PA2 \
1167 	GD32_PINMUX_AF('A', 2, AF7)
1168 
1169 /* TRIGSEL_IN10 */
1170 #define TRIGSEL_IN10_PB11 \
1171 	GD32_PINMUX_AF('B', 11, AF7)
1172 
1173 /* TRIGSEL_IN11 */
1174 #define TRIGSEL_IN11_PB12 \
1175 	GD32_PINMUX_AF('B', 12, AF7)
1176 
1177 /* TRIGSEL_IN12 */
1178 #define TRIGSEL_IN12_PA15 \
1179 	GD32_PINMUX_AF('A', 15, AF7)
1180 
1181 /* TRIGSEL_IN13 */
1182 #define TRIGSEL_IN13_PA11 \
1183 	GD32_PINMUX_AF('A', 11, AF7)
1184 
1185 /* TRIGSEL_IN2 */
1186 #define TRIGSEL_IN2_PE13 \
1187 	GD32_PINMUX_AF('E', 13, AF7)
1188 
1189 /* TRIGSEL_IN3 */
1190 #define TRIGSEL_IN3_PE14 \
1191 	GD32_PINMUX_AF('E', 14, AF7)
1192 
1193 /* TRIGSEL_IN4 */
1194 #define TRIGSEL_IN4_PA8 \
1195 	GD32_PINMUX_AF('A', 8, AF7)
1196 
1197 /* TRIGSEL_IN5 */
1198 #define TRIGSEL_IN5_PA9 \
1199 	GD32_PINMUX_AF('A', 9, AF7)
1200 
1201 /* TRIGSEL_IN6 */
1202 #define TRIGSEL_IN6_PF2 \
1203 	GD32_PINMUX_AF('F', 2, AF6)
1204 
1205 /* TRIGSEL_IN7 */
1206 #define TRIGSEL_IN7_PA7 \
1207 	GD32_PINMUX_AF('A', 7, AF7)
1208 
1209 /* TRIGSEL_IN8 */
1210 #define TRIGSEL_IN8_PE11 \
1211 	GD32_PINMUX_AF('E', 11, AF7)
1212 
1213 /* TRIGSEL_IN9 */
1214 #define TRIGSEL_IN9_PE12 \
1215 	GD32_PINMUX_AF('E', 12, AF7)
1216 
1217 /* TRIGSEL_OUT0 */
1218 #define TRIGSEL_OUT0_PC10 \
1219 	GD32_PINMUX_AF('C', 10, AF7)
1220 
1221 /* TRIGSEL_OUT1 */
1222 #define TRIGSEL_OUT1_PE5 \
1223 	GD32_PINMUX_AF('E', 5, AF7)
1224 
1225 /* TRIGSEL_OUT2 */
1226 #define TRIGSEL_OUT2_PE4 \
1227 	GD32_PINMUX_AF('E', 4, AF7)
1228 
1229 /* TRIGSEL_OUT3 */
1230 #define TRIGSEL_OUT3_PC11 \
1231 	GD32_PINMUX_AF('C', 11, AF7)
1232 
1233 /* TRIGSEL_OUT4 */
1234 #define TRIGSEL_OUT4_PC13 \
1235 	GD32_PINMUX_AF('C', 13, AF7)
1236 
1237 /* TRIGSEL_OUT5 */
1238 #define TRIGSEL_OUT5_PE6 \
1239 	GD32_PINMUX_AF('E', 6, AF7)
1240 
1241 /* TRIGSEL_OUT6 */
1242 #define TRIGSEL_OUT6_PE3 \
1243 	GD32_PINMUX_AF('E', 3, AF12)
1244 
1245 /* TRIGSEL_OUT7 */
1246 #define TRIGSEL_OUT7_PE2 \
1247 	GD32_PINMUX_AF('E', 2, AF7)
1248 
1249 /* USART0_CK */
1250 #define USART0_CK_PA12 \
1251 	GD32_PINMUX_AF('A', 12, AF5)
1252 
1253 /* USART0_CTS */
1254 #define USART0_CTS_PC11 \
1255 	GD32_PINMUX_AF('C', 11, AF5)
1256 #define USART0_CTS_PD8 \
1257 	GD32_PINMUX_AF('D', 8, AF5)
1258 
1259 /* USART0_DE */
1260 #define USART0_DE_PB15 \
1261 	GD32_PINMUX_AF('B', 15, AF5)
1262 #define USART0_DE_PC10 \
1263 	GD32_PINMUX_AF('C', 10, AF5)
1264 
1265 /* USART0_RTS */
1266 #define USART0_RTS_PB15 \
1267 	GD32_PINMUX_AF('B', 15, AF5)
1268 #define USART0_RTS_PC10 \
1269 	GD32_PINMUX_AF('C', 10, AF5)
1270 
1271 /* USART0_RX */
1272 #define USART0_RX_PA4 \
1273 	GD32_PINMUX_AF('A', 4, AF5)
1274 #define USART0_RX_PA11 \
1275 	GD32_PINMUX_AF('A', 11, AF5)
1276 #define USART0_RX_PB14 \
1277 	GD32_PINMUX_AF('B', 14, AF5)
1278 
1279 /* USART0_TX */
1280 #define USART0_TX_PA3 \
1281 	GD32_PINMUX_AF('A', 3, AF5)
1282 #define USART0_TX_PA10 \
1283 	GD32_PINMUX_AF('A', 10, AF5)
1284 #define USART0_TX_PB13 \
1285 	GD32_PINMUX_AF('B', 13, AF5)
1286 
1287 /* USART1_CK */
1288 #define USART1_CK_PD5 \
1289 	GD32_PINMUX_AF('D', 5, AF12)
1290 
1291 /* USART1_CTS */
1292 #define USART1_CTS_PD4 \
1293 	GD32_PINMUX_AF('D', 4, AF5)
1294 #define USART1_CTS_PD10 \
1295 	GD32_PINMUX_AF('D', 10, AF5)
1296 #define USART1_CTS_PE3 \
1297 	GD32_PINMUX_AF('E', 3, AF12)
1298 #define USART1_CTS_PF5 \
1299 	GD32_PINMUX_AF('F', 5, AF5)
1300 
1301 /* USART1_DE */
1302 #define USART1_DE_PD3 \
1303 	GD32_PINMUX_AF('D', 3, AF5)
1304 #define USART1_DE_PD9 \
1305 	GD32_PINMUX_AF('D', 9, AF5)
1306 #define USART1_DE_PE2 \
1307 	GD32_PINMUX_AF('E', 2, AF5)
1308 
1309 /* USART1_RTS */
1310 #define USART1_RTS_PD3 \
1311 	GD32_PINMUX_AF('D', 3, AF5)
1312 #define USART1_RTS_PD9 \
1313 	GD32_PINMUX_AF('D', 9, AF5)
1314 #define USART1_RTS_PE2 \
1315 	GD32_PINMUX_AF('E', 2, AF5)
1316 
1317 /* USART1_RX */
1318 #define USART1_RX_PC3 \
1319 	GD32_PINMUX_AF('C', 3, AF5)
1320 #define USART1_RX_PD0 \
1321 	GD32_PINMUX_AF('D', 0, AF5)
1322 #define USART1_RX_PD8 \
1323 	GD32_PINMUX_AF('D', 8, AF4)
1324 
1325 /* USART1_TX */
1326 #define USART1_TX_PB15 \
1327 	GD32_PINMUX_AF('B', 15, AF4)
1328 #define USART1_TX_PC2 \
1329 	GD32_PINMUX_AF('C', 2, AF5)
1330 #define USART1_TX_PC12 \
1331 	GD32_PINMUX_AF('C', 12, AF5)
1332 
1333 /* USART2_CK */
1334 #define USART2_CK_PA7 \
1335 	GD32_PINMUX_AF('A', 7, AF5)
1336 
1337 /* USART2_CTS */
1338 #define USART2_CTS_PB10 \
1339 	GD32_PINMUX_AF('B', 10, AF5)
1340 #define USART2_CTS_PC1 \
1341 	GD32_PINMUX_AF('C', 1, AF5)
1342 #define USART2_CTS_PC5 \
1343 	GD32_PINMUX_AF('C', 5, AF5)
1344 
1345 /* USART2_DE */
1346 #define USART2_DE_PC4 \
1347 	GD32_PINMUX_AF('C', 4, AF5)
1348 #define USART2_DE_PE15 \
1349 	GD32_PINMUX_AF('E', 15, AF5)
1350 #define USART2_DE_PF2 \
1351 	GD32_PINMUX_AF('F', 2, AF5)
1352 
1353 /* USART2_RTS */
1354 #define USART2_RTS_PC4 \
1355 	GD32_PINMUX_AF('C', 4, AF5)
1356 #define USART2_RTS_PE15 \
1357 	GD32_PINMUX_AF('E', 15, AF5)
1358 #define USART2_RTS_PF2 \
1359 	GD32_PINMUX_AF('F', 2, AF5)
1360 
1361 /* USART2_RX */
1362 #define USART2_RX_PA6 \
1363 	GD32_PINMUX_AF('A', 6, AF5)
1364 #define USART2_RX_PE1 \
1365 	GD32_PINMUX_AF('E', 1, AF5)
1366 #define USART2_RX_PF4 \
1367 	GD32_PINMUX_AF('F', 4, AF5)
1368 
1369 /* USART2_TX */
1370 #define USART2_TX_PA5 \
1371 	GD32_PINMUX_AF('A', 5, AF5)
1372 #define USART2_TX_PE0 \
1373 	GD32_PINMUX_AF('E', 0, AF5)
1374 #define USART2_TX_PF3 \
1375 	GD32_PINMUX_AF('F', 3, AF5)
1376