/* * Autogenerated file * * SPDX-License-Identifier: Apache 2.0 */ #include "gd32-af.h" /* ADC0_IN0 */ #define ADC0_IN0_PC11 \ GD32_PINMUX_AF('C', 11, ANALOG) /* ADC0_IN1 */ #define ADC0_IN1_PC10 \ GD32_PINMUX_AF('C', 10, ANALOG) /* ADC0_IN10 */ #define ADC0_IN10_PA4 \ GD32_PINMUX_AF('A', 4, ANALOG) /* ADC0_IN11 */ #define ADC0_IN11_PA3 \ GD32_PINMUX_AF('A', 3, ANALOG) /* ADC0_IN12 */ #define ADC0_IN12_PE12 \ GD32_PINMUX_AF('E', 12, ANALOG) /* ADC0_IN13 */ #define ADC0_IN13_PE11 \ GD32_PINMUX_AF('E', 11, ANALOG) /* ADC0_IN14 */ #define ADC0_IN14_PE10 \ GD32_PINMUX_AF('E', 10, ANALOG) /* ADC0_IN15 */ #define ADC0_IN15_PE9 \ GD32_PINMUX_AF('E', 9, ANALOG) /* ADC0_IN2 */ #define ADC0_IN2_PD10 \ GD32_PINMUX_AF('D', 10, ANALOG) /* ADC0_IN3 */ #define ADC0_IN3_PD9 \ GD32_PINMUX_AF('D', 9, ANALOG) /* ADC0_IN4 */ #define ADC0_IN4_PB14 \ GD32_PINMUX_AF('B', 14, ANALOG) /* ADC0_IN5 */ #define ADC0_IN5_PB13 \ GD32_PINMUX_AF('B', 13, ANALOG) /* ADC0_IN6 */ #define ADC0_IN6_PE14 \ GD32_PINMUX_AF('E', 14, ANALOG) /* ADC0_IN7 */ #define ADC0_IN7_PE13 \ GD32_PINMUX_AF('E', 13, ANALOG) /* ADC0_IN8 */ #define ADC0_IN8_PB2 \ GD32_PINMUX_AF('B', 2, ANALOG) #define ADC0_IN8_PC7 \ GD32_PINMUX_AF('C', 7, ANALOG) /* ADC0_IN9 */ #define ADC0_IN9_PB1 \ GD32_PINMUX_AF('B', 1, ANALOG) #define ADC0_IN9_PC6 \ GD32_PINMUX_AF('C', 6, ANALOG) /* ADC1_IN0 */ #define ADC1_IN0_PA11 \ GD32_PINMUX_AF('A', 11, ANALOG) /* ADC1_IN1 */ #define ADC1_IN1_PA10 \ GD32_PINMUX_AF('A', 10, ANALOG) /* ADC1_IN10 */ #define ADC1_IN10_PD4 \ GD32_PINMUX_AF('D', 4, ANALOG) /* ADC1_IN11 */ #define ADC1_IN11_PD3 \ GD32_PINMUX_AF('D', 3, ANALOG) /* ADC1_IN12 */ #define ADC1_IN12_PD2 \ GD32_PINMUX_AF('D', 2, ANALOG) /* ADC1_IN13 */ #define ADC1_IN13_PD1 \ GD32_PINMUX_AF('D', 1, ANALOG) /* ADC1_IN14 */ #define ADC1_IN14_PB14 \ GD32_PINMUX_AF('B', 14, ANALOG) #define ADC1_IN14_PD15 \ GD32_PINMUX_AF('D', 15, ANALOG) /* ADC1_IN15 */ #define ADC1_IN15_PB13 \ GD32_PINMUX_AF('B', 13, ANALOG) #define ADC1_IN15_PD14 \ GD32_PINMUX_AF('D', 14, ANALOG) /* ADC1_IN2 */ #define ADC1_IN2_PA9 \ GD32_PINMUX_AF('A', 9, ANALOG) /* ADC1_IN3 */ #define ADC1_IN3_PA8 \ GD32_PINMUX_AF('A', 8, ANALOG) /* ADC1_IN4 */ #define ADC1_IN4_PD0 \ GD32_PINMUX_AF('D', 0, ANALOG) /* ADC1_IN5 */ #define ADC1_IN5_PC12 \ GD32_PINMUX_AF('C', 12, ANALOG) /* ADC1_IN6 */ #define ADC1_IN6_PC9 \ GD32_PINMUX_AF('C', 9, ANALOG) /* ADC1_IN7 */ #define ADC1_IN7_PC8 \ GD32_PINMUX_AF('C', 8, ANALOG) /* ADC1_IN8 */ #define ADC1_IN8_PC7 \ GD32_PINMUX_AF('C', 7, ANALOG) /* ADC1_IN9 */ #define ADC1_IN9_PC6 \ GD32_PINMUX_AF('C', 6, ANALOG) /* ANALOG */ #define ANALOG_PA0 \ GD32_PINMUX_AF('A', 0, ANALOG) #define ANALOG_PA1 \ GD32_PINMUX_AF('A', 1, ANALOG) #define ANALOG_PA2 \ GD32_PINMUX_AF('A', 2, ANALOG) #define ANALOG_PA3 \ GD32_PINMUX_AF('A', 3, ANALOG) #define ANALOG_PA4 \ GD32_PINMUX_AF('A', 4, ANALOG) #define ANALOG_PA5 \ GD32_PINMUX_AF('A', 5, ANALOG) #define ANALOG_PA6 \ GD32_PINMUX_AF('A', 6, ANALOG) #define ANALOG_PA7 \ GD32_PINMUX_AF('A', 7, ANALOG) #define ANALOG_PA8 \ GD32_PINMUX_AF('A', 8, ANALOG) #define ANALOG_PA9 \ GD32_PINMUX_AF('A', 9, ANALOG) #define ANALOG_PA10 \ GD32_PINMUX_AF('A', 10, ANALOG) #define ANALOG_PA11 \ GD32_PINMUX_AF('A', 11, ANALOG) #define ANALOG_PA12 \ GD32_PINMUX_AF('A', 12, ANALOG) #define ANALOG_PA13 \ GD32_PINMUX_AF('A', 13, ANALOG) #define ANALOG_PA14 \ GD32_PINMUX_AF('A', 14, ANALOG) #define ANALOG_PA15 \ GD32_PINMUX_AF('A', 15, ANALOG) #define ANALOG_PB0 \ GD32_PINMUX_AF('B', 0, ANALOG) #define ANALOG_PB1 \ GD32_PINMUX_AF('B', 1, ANALOG) #define ANALOG_PB2 \ GD32_PINMUX_AF('B', 2, ANALOG) #define ANALOG_PB3 \ GD32_PINMUX_AF('B', 3, ANALOG) #define ANALOG_PB4 \ GD32_PINMUX_AF('B', 4, ANALOG) #define ANALOG_PB5 \ GD32_PINMUX_AF('B', 5, ANALOG) #define ANALOG_PB6 \ GD32_PINMUX_AF('B', 6, ANALOG) #define ANALOG_PB7 \ GD32_PINMUX_AF('B', 7, ANALOG) #define ANALOG_PB8 \ GD32_PINMUX_AF('B', 8, ANALOG) #define ANALOG_PB9 \ GD32_PINMUX_AF('B', 9, ANALOG) #define ANALOG_PB10 \ GD32_PINMUX_AF('B', 10, ANALOG) #define ANALOG_PB11 \ GD32_PINMUX_AF('B', 11, ANALOG) #define ANALOG_PB12 \ GD32_PINMUX_AF('B', 12, ANALOG) #define ANALOG_PB13 \ GD32_PINMUX_AF('B', 13, ANALOG) #define ANALOG_PB14 \ GD32_PINMUX_AF('B', 14, ANALOG) #define ANALOG_PB15 \ GD32_PINMUX_AF('B', 15, ANALOG) #define ANALOG_PC0 \ GD32_PINMUX_AF('C', 0, ANALOG) #define ANALOG_PC1 \ GD32_PINMUX_AF('C', 1, ANALOG) #define ANALOG_PC2 \ GD32_PINMUX_AF('C', 2, ANALOG) #define ANALOG_PC3 \ GD32_PINMUX_AF('C', 3, ANALOG) #define ANALOG_PC4 \ GD32_PINMUX_AF('C', 4, ANALOG) #define ANALOG_PC5 \ GD32_PINMUX_AF('C', 5, ANALOG) #define ANALOG_PC6 \ GD32_PINMUX_AF('C', 6, ANALOG) #define ANALOG_PC7 \ GD32_PINMUX_AF('C', 7, ANALOG) #define ANALOG_PC8 \ GD32_PINMUX_AF('C', 8, ANALOG) #define ANALOG_PC9 \ GD32_PINMUX_AF('C', 9, ANALOG) #define ANALOG_PC10 \ GD32_PINMUX_AF('C', 10, ANALOG) #define ANALOG_PC11 \ GD32_PINMUX_AF('C', 11, ANALOG) #define ANALOG_PC12 \ GD32_PINMUX_AF('C', 12, ANALOG) #define ANALOG_PC13 \ GD32_PINMUX_AF('C', 13, ANALOG) #define ANALOG_PC14 \ GD32_PINMUX_AF('C', 14, ANALOG) #define ANALOG_PC15 \ GD32_PINMUX_AF('C', 15, ANALOG) #define ANALOG_PD0 \ GD32_PINMUX_AF('D', 0, ANALOG) #define ANALOG_PD1 \ GD32_PINMUX_AF('D', 1, ANALOG) #define ANALOG_PD2 \ GD32_PINMUX_AF('D', 2, ANALOG) #define ANALOG_PD3 \ GD32_PINMUX_AF('D', 3, ANALOG) #define ANALOG_PD4 \ GD32_PINMUX_AF('D', 4, ANALOG) #define ANALOG_PD5 \ GD32_PINMUX_AF('D', 5, ANALOG) #define ANALOG_PD6 \ GD32_PINMUX_AF('D', 6, ANALOG) #define ANALOG_PD7 \ GD32_PINMUX_AF('D', 7, ANALOG) #define ANALOG_PD8 \ GD32_PINMUX_AF('D', 8, ANALOG) #define ANALOG_PD9 \ GD32_PINMUX_AF('D', 9, ANALOG) #define ANALOG_PD10 \ GD32_PINMUX_AF('D', 10, ANALOG) #define ANALOG_PD11 \ GD32_PINMUX_AF('D', 11, ANALOG) #define ANALOG_PD12 \ GD32_PINMUX_AF('D', 12, ANALOG) #define ANALOG_PD13 \ GD32_PINMUX_AF('D', 13, ANALOG) #define ANALOG_PD14 \ GD32_PINMUX_AF('D', 14, ANALOG) #define ANALOG_PD15 \ GD32_PINMUX_AF('D', 15, ANALOG) #define ANALOG_PE0 \ GD32_PINMUX_AF('E', 0, ANALOG) #define ANALOG_PE1 \ GD32_PINMUX_AF('E', 1, ANALOG) #define ANALOG_PE2 \ GD32_PINMUX_AF('E', 2, ANALOG) #define ANALOG_PE3 \ GD32_PINMUX_AF('E', 3, ANALOG) #define ANALOG_PE4 \ GD32_PINMUX_AF('E', 4, ANALOG) #define ANALOG_PE5 \ GD32_PINMUX_AF('E', 5, ANALOG) #define ANALOG_PE6 \ GD32_PINMUX_AF('E', 6, ANALOG) #define ANALOG_PE7 \ GD32_PINMUX_AF('E', 7, ANALOG) #define ANALOG_PE8 \ GD32_PINMUX_AF('E', 8, ANALOG) #define ANALOG_PE9 \ GD32_PINMUX_AF('E', 9, ANALOG) #define ANALOG_PE10 \ GD32_PINMUX_AF('E', 10, ANALOG) #define ANALOG_PE11 \ GD32_PINMUX_AF('E', 11, ANALOG) #define ANALOG_PE12 \ GD32_PINMUX_AF('E', 12, ANALOG) #define ANALOG_PE13 \ GD32_PINMUX_AF('E', 13, ANALOG) #define ANALOG_PE14 \ GD32_PINMUX_AF('E', 14, ANALOG) #define ANALOG_PE15 \ GD32_PINMUX_AF('E', 15, ANALOG) #define ANALOG_PF0 \ GD32_PINMUX_AF('F', 0, ANALOG) #define ANALOG_PF1 \ GD32_PINMUX_AF('F', 1, ANALOG) #define ANALOG_PF2 \ GD32_PINMUX_AF('F', 2, ANALOG) #define ANALOG_PF3 \ GD32_PINMUX_AF('F', 3, ANALOG) #define ANALOG_PF4 \ GD32_PINMUX_AF('F', 4, ANALOG) #define ANALOG_PF5 \ GD32_PINMUX_AF('F', 5, ANALOG) #define ANALOG_PF6 \ GD32_PINMUX_AF('F', 6, ANALOG) #define ANALOG_PF7 \ GD32_PINMUX_AF('F', 7, ANALOG) /* CAN0_RX */ #define CAN0_RX_PA4 \ GD32_PINMUX_AF('A', 4, AF6) #define CAN0_RX_PB14 \ GD32_PINMUX_AF('B', 14, AF6) #define CAN0_RX_PF0 \ GD32_PINMUX_AF('F', 0, AF6) /* CAN0_TX */ #define CAN0_TX_PA3 \ GD32_PINMUX_AF('A', 3, AF6) #define CAN0_TX_PB13 \ GD32_PINMUX_AF('B', 13, AF6) #define CAN0_TX_PC15 \ GD32_PINMUX_AF('C', 15, AF6) /* CAN1_RX */ #define CAN1_RX_PD0 \ GD32_PINMUX_AF('D', 0, AF6) #define CAN1_RX_PD7 \ GD32_PINMUX_AF('D', 7, AF6) /* CAN1_TX */ #define CAN1_TX_PC12 \ GD32_PINMUX_AF('C', 12, AF6) #define CAN1_TX_PD6 \ GD32_PINMUX_AF('D', 6, AF6) /* CK_OUT */ #define CK_OUT_PC2 \ GD32_PINMUX_AF('C', 2, AF0) #define CK_OUT_PC13 \ GD32_PINMUX_AF('C', 13, AF0) /* CK_OUT0 */ #define CK_OUT0_PA1 \ GD32_PINMUX_AF('A', 1, AF0) /* CMP_OUT */ #define CMP_OUT_PB9 \ GD32_PINMUX_AF('B', 9, AF7) #define CMP_OUT_PF2 \ GD32_PINMUX_AF('F', 2, AF7) /* DAC_OUT */ #define DAC_OUT_PA7 \ GD32_PINMUX_AF('A', 7, ANALOG) /* EVENTOUT */ #define EVENTOUT_PA0 \ GD32_PINMUX_AF('A', 0, AF9) #define EVENTOUT_PA1 \ GD32_PINMUX_AF('A', 1, AF9) #define EVENTOUT_PA2 \ GD32_PINMUX_AF('A', 2, AF9) #define EVENTOUT_PA3 \ GD32_PINMUX_AF('A', 3, AF9) #define EVENTOUT_PA4 \ GD32_PINMUX_AF('A', 4, AF9) #define EVENTOUT_PA5 \ GD32_PINMUX_AF('A', 5, AF9) #define EVENTOUT_PA7 \ GD32_PINMUX_AF('A', 7, AF9) #define EVENTOUT_PA8 \ GD32_PINMUX_AF('A', 8, AF9) #define EVENTOUT_PA9 \ GD32_PINMUX_AF('A', 9, AF9) #define EVENTOUT_PA10 \ GD32_PINMUX_AF('A', 10, AF9) #define EVENTOUT_PA11 \ GD32_PINMUX_AF('A', 11, AF9) #define EVENTOUT_PA12 \ GD32_PINMUX_AF('A', 12, AF9) #define EVENTOUT_PA13 \ GD32_PINMUX_AF('A', 13, AF9) #define EVENTOUT_PA14 \ GD32_PINMUX_AF('A', 14, AF9) #define EVENTOUT_PA15 \ GD32_PINMUX_AF('A', 15, AF9) #define EVENTOUT_PB0 \ GD32_PINMUX_AF('B', 0, AF9) #define EVENTOUT_PB1 \ GD32_PINMUX_AF('B', 1, AF9) #define EVENTOUT_PB2 \ GD32_PINMUX_AF('B', 2, AF9) #define EVENTOUT_PB3 \ GD32_PINMUX_AF('B', 3, AF9) #define EVENTOUT_PB4 \ GD32_PINMUX_AF('B', 4, AF9) #define EVENTOUT_PB5 \ GD32_PINMUX_AF('B', 5, AF9) #define EVENTOUT_PB6 \ GD32_PINMUX_AF('B', 6, AF9) #define EVENTOUT_PB7 \ GD32_PINMUX_AF('B', 7, AF9) #define EVENTOUT_PB8 \ GD32_PINMUX_AF('B', 8, AF9) #define EVENTOUT_PB9 \ GD32_PINMUX_AF('B', 9, AF9) #define EVENTOUT_PB10 \ GD32_PINMUX_AF('B', 10, AF9) #define EVENTOUT_PB11 \ GD32_PINMUX_AF('B', 11, AF9) #define EVENTOUT_PB12 \ GD32_PINMUX_AF('B', 12, AF9) #define EVENTOUT_PB13 \ GD32_PINMUX_AF('B', 13, AF9) #define EVENTOUT_PB14 \ GD32_PINMUX_AF('B', 14, AF9) #define EVENTOUT_PB15 \ GD32_PINMUX_AF('B', 15, AF9) #define EVENTOUT_PC0 \ GD32_PINMUX_AF('C', 0, AF9) #define EVENTOUT_PC1 \ GD32_PINMUX_AF('C', 1, AF9) #define EVENTOUT_PC2 \ GD32_PINMUX_AF('C', 2, AF9) #define EVENTOUT_PC3 \ GD32_PINMUX_AF('C', 3, AF9) #define EVENTOUT_PC4 \ GD32_PINMUX_AF('C', 4, AF9) #define EVENTOUT_PC5 \ GD32_PINMUX_AF('C', 5, AF9) #define EVENTOUT_PC6 \ GD32_PINMUX_AF('C', 6, AF9) #define EVENTOUT_PC7 \ GD32_PINMUX_AF('C', 7, AF9) #define EVENTOUT_PC8 \ GD32_PINMUX_AF('C', 8, AF9) #define EVENTOUT_PC9 \ GD32_PINMUX_AF('C', 9, AF9) #define EVENTOUT_PC10 \ GD32_PINMUX_AF('C', 10, AF9) #define EVENTOUT_PC11 \ GD32_PINMUX_AF('C', 11, AF9) #define EVENTOUT_PC12 \ GD32_PINMUX_AF('C', 12, AF9) #define EVENTOUT_PC13 \ GD32_PINMUX_AF('C', 13, AF9) #define EVENTOUT_PC14 \ GD32_PINMUX_AF('C', 14, AF9) #define EVENTOUT_PC15 \ GD32_PINMUX_AF('C', 15, AF9) #define EVENTOUT_PD0 \ GD32_PINMUX_AF('D', 0, AF9) #define EVENTOUT_PD1 \ GD32_PINMUX_AF('D', 1, AF9) #define EVENTOUT_PD2 \ GD32_PINMUX_AF('D', 2, AF9) #define EVENTOUT_PD3 \ GD32_PINMUX_AF('D', 3, AF9) #define EVENTOUT_PD4 \ GD32_PINMUX_AF('D', 4, AF9) #define EVENTOUT_PD5 \ GD32_PINMUX_AF('D', 5, AF9) #define EVENTOUT_PD6 \ GD32_PINMUX_AF('D', 6, AF9) #define EVENTOUT_PD7 \ GD32_PINMUX_AF('D', 7, AF9) #define EVENTOUT_PD8 \ GD32_PINMUX_AF('D', 8, AF9) #define EVENTOUT_PD9 \ GD32_PINMUX_AF('D', 9, AF9) #define EVENTOUT_PD10 \ GD32_PINMUX_AF('D', 10, AF9) #define EVENTOUT_PD11 \ GD32_PINMUX_AF('D', 11, AF9) #define EVENTOUT_PD12 \ GD32_PINMUX_AF('D', 12, AF9) #define EVENTOUT_PD13 \ GD32_PINMUX_AF('D', 13, AF9) #define EVENTOUT_PD14 \ GD32_PINMUX_AF('D', 14, AF9) #define EVENTOUT_PD15 \ GD32_PINMUX_AF('D', 15, AF9) #define EVENTOUT_PE0 \ GD32_PINMUX_AF('E', 0, AF9) #define EVENTOUT_PE1 \ GD32_PINMUX_AF('E', 1, AF9) #define EVENTOUT_PE2 \ GD32_PINMUX_AF('E', 2, AF9) #define EVENTOUT_PE3 \ GD32_PINMUX_AF('E', 3, AF9) #define EVENTOUT_PE4 \ GD32_PINMUX_AF('E', 4, AF9) #define EVENTOUT_PE5 \ GD32_PINMUX_AF('E', 5, AF9) #define EVENTOUT_PE6 \ GD32_PINMUX_AF('E', 6, AF9) #define EVENTOUT_PE7 \ GD32_PINMUX_AF('E', 7, AF9) #define EVENTOUT_PE8 \ GD32_PINMUX_AF('E', 8, AF9) #define EVENTOUT_PE9 \ GD32_PINMUX_AF('E', 9, AF9) #define EVENTOUT_PE10 \ GD32_PINMUX_AF('E', 10, AF9) #define EVENTOUT_PE11 \ GD32_PINMUX_AF('E', 11, AF9) #define EVENTOUT_PE12 \ GD32_PINMUX_AF('E', 12, AF9) #define EVENTOUT_PE13 \ GD32_PINMUX_AF('E', 13, AF9) #define EVENTOUT_PE14 \ GD32_PINMUX_AF('E', 14, AF9) #define EVENTOUT_PE15 \ GD32_PINMUX_AF('E', 15, AF9) #define EVENTOUT_PF0 \ GD32_PINMUX_AF('F', 0, AF9) #define EVENTOUT_PF1 \ GD32_PINMUX_AF('F', 1, AF9) #define EVENTOUT_PF2 \ GD32_PINMUX_AF('F', 2, AF9) #define EVENTOUT_PF3 \ GD32_PINMUX_AF('F', 3, AF9) #define EVENTOUT_PF4 \ GD32_PINMUX_AF('F', 4, AF9) #define EVENTOUT_PF5 \ GD32_PINMUX_AF('F', 5, AF9) #define EVENTOUT_PF6 \ GD32_PINMUX_AF('F', 6, AF9) #define EVENTOUT_PF7 \ GD32_PINMUX_AF('F', 7, AF9) /* I2C0_SCL */ #define I2C0_SCL_PA10 \ GD32_PINMUX_AF('A', 10, AF3) #define I2C0_SCL_PA14 \ GD32_PINMUX_AF('A', 14, AF3) #define I2C0_SCL_PC11 \ GD32_PINMUX_AF('C', 11, AF3) #define I2C0_SCL_PF6 \ GD32_PINMUX_AF('F', 6, AF3) /* I2C0_SDA */ #define I2C0_SDA_PA11 \ GD32_PINMUX_AF('A', 11, AF3) #define I2C0_SDA_PA13 \ GD32_PINMUX_AF('A', 13, AF3) #define I2C0_SDA_PC10 \ GD32_PINMUX_AF('C', 10, AF3) #define I2C0_SDA_PF7 \ GD32_PINMUX_AF('F', 7, AF3) /* I2C0_SMBA */ #define I2C0_SMBA_PA12 \ GD32_PINMUX_AF('A', 12, AF3) #define I2C0_SMBA_PB5 \ GD32_PINMUX_AF('B', 5, AF3) /* I2C1_SCL */ #define I2C1_SCL_PB7 \ GD32_PINMUX_AF('B', 7, AF5) #define I2C1_SCL_PD6 \ GD32_PINMUX_AF('D', 6, AF5) #define I2C1_SCL_PE10 \ GD32_PINMUX_AF('E', 10, AF5) /* I2C1_SDA */ #define I2C1_SDA_PB8 \ GD32_PINMUX_AF('B', 8, AF5) #define I2C1_SDA_PD7 \ GD32_PINMUX_AF('D', 7, AF5) #define I2C1_SDA_PE11 \ GD32_PINMUX_AF('E', 11, AF5) /* I2C1_SMBA */ #define I2C1_SMBA_PB9 \ GD32_PINMUX_AF('B', 9, AF5) #define I2C1_SMBA_PD11 \ GD32_PINMUX_AF('D', 11, AF5) #define I2C1_SMBA_PE12 \ GD32_PINMUX_AF('E', 12, AF5) /* I2S1_CK */ #define I2S1_CK_PC6 \ GD32_PINMUX_AF('C', 6, AF4) #define I2S1_CK_PE5 \ GD32_PINMUX_AF('E', 5, AF4) /* I2S1_MCK */ #define I2S1_MCK_PC7 \ GD32_PINMUX_AF('C', 7, AF4) #define I2S1_MCK_PE6 \ GD32_PINMUX_AF('E', 6, AF4) /* I2S1_SD */ #define I2S1_SD_PA9 \ GD32_PINMUX_AF('A', 9, AF4) #define I2S1_SD_PB6 \ GD32_PINMUX_AF('B', 6, AF5) #define I2S1_SD_PD14 \ GD32_PINMUX_AF('D', 14, AF4) /* I2S1_WS */ #define I2S1_WS_PA8 \ GD32_PINMUX_AF('A', 8, AF4) #define I2S1_WS_PB5 \ GD32_PINMUX_AF('B', 5, AF6) #define I2S1_WS_PD1 \ GD32_PINMUX_AF('D', 1, AF4) #define I2S1_WS_PD10 \ GD32_PINMUX_AF('D', 10, AF4) #define I2S1_WS_PD13 \ GD32_PINMUX_AF('D', 13, AF4) /* JTCK */ #define JTCK_PB8 \ GD32_PINMUX_AF('B', 8, AF0) /* JTDI */ #define JTDI_PB7 \ GD32_PINMUX_AF('B', 7, AF0) /* JTDO */ #define JTDO_PB4 \ GD32_PINMUX_AF('B', 4, AF0) /* JTMS */ #define JTMS_PB9 \ GD32_PINMUX_AF('B', 9, AF0) /* MFCOM_D0 */ #define MFCOM_D0_PB4 \ GD32_PINMUX_AF('B', 4, AF6) #define MFCOM_D0_PE5 \ GD32_PINMUX_AF('E', 5, AF6) #define MFCOM_D0_PE7 \ GD32_PINMUX_AF('E', 7, AF6) /* MFCOM_D1 */ #define MFCOM_D1_PB3 \ GD32_PINMUX_AF('B', 3, AF6) #define MFCOM_D1_PE4 \ GD32_PINMUX_AF('E', 4, AF6) #define MFCOM_D1_PE8 \ GD32_PINMUX_AF('E', 8, AF6) /* MFCOM_D2 */ #define MFCOM_D2_PC11 \ GD32_PINMUX_AF('C', 11, AF6) #define MFCOM_D2_PE3 \ GD32_PINMUX_AF('E', 3, AF12) /* MFCOM_D3 */ #define MFCOM_D3_PC10 \ GD32_PINMUX_AF('C', 10, AF6) #define MFCOM_D3_PE2 \ GD32_PINMUX_AF('E', 2, AF6) /* MFCOM_D4 */ #define MFCOM_D4_PA9 \ GD32_PINMUX_AF('A', 9, AF6) #define MFCOM_D4_PA11 \ GD32_PINMUX_AF('A', 11, AF6) #define MFCOM_D4_PC13 \ GD32_PINMUX_AF('C', 13, AF6) /* MFCOM_D5 */ #define MFCOM_D5_PA8 \ GD32_PINMUX_AF('A', 8, AF6) #define MFCOM_D5_PA10 \ GD32_PINMUX_AF('A', 10, AF6) #define MFCOM_D5_PE6 \ GD32_PINMUX_AF('E', 6, AF6) /* MFCOM_D6 */ #define MFCOM_D6_PA9 \ GD32_PINMUX_AF('A', 9, AF5) #define MFCOM_D6_PE1 \ GD32_PINMUX_AF('E', 1, AF6) #define MFCOM_D6_PF0 \ GD32_PINMUX_AF('F', 0, AF7) /* MFCOM_D7 */ #define MFCOM_D7_PA8 \ GD32_PINMUX_AF('A', 8, AF5) #define MFCOM_D7_PC15 \ GD32_PINMUX_AF('C', 15, AF7) #define MFCOM_D7_PE0 \ GD32_PINMUX_AF('E', 0, AF6) /* NJTRST */ #define NJTRST_PB3 \ GD32_PINMUX_AF('B', 3, AF0) /* SPI0_IO2 */ #define SPI0_IO2_PB3 \ GD32_PINMUX_AF('B', 3, AF4) #define SPI0_IO2_PE15 \ GD32_PINMUX_AF('E', 15, AF4) /* SPI0_IO3 */ #define SPI0_IO3_PB4 \ GD32_PINMUX_AF('B', 4, AF4) #define SPI0_IO3_PB10 \ GD32_PINMUX_AF('B', 10, AF4) /* SPI0_MISO */ #define SPI0_MISO_PB5 \ GD32_PINMUX_AF('B', 5, AF4) #define SPI0_MISO_PE13 \ GD32_PINMUX_AF('E', 13, AF4) #define SPI0_MISO_PF5 \ GD32_PINMUX_AF('F', 5, AF4) /* SPI0_MOSI */ #define SPI0_MOSI_PA2 \ GD32_PINMUX_AF('A', 2, AF4) #define SPI0_MOSI_PB13 \ GD32_PINMUX_AF('B', 13, AF4) #define SPI0_MOSI_PD4 \ GD32_PINMUX_AF('D', 4, AF4) /* SPI0_NSS */ #define SPI0_NSS_PA1 \ GD32_PINMUX_AF('A', 1, AF4) #define SPI0_NSS_PB14 \ GD32_PINMUX_AF('B', 14, AF3) #define SPI0_NSS_PD2 \ GD32_PINMUX_AF('D', 2, AF4) #define SPI0_NSS_PD3 \ GD32_PINMUX_AF('D', 3, AF4) /* SPI0_SCK */ #define SPI0_SCK_PB6 \ GD32_PINMUX_AF('B', 6, AF4) #define SPI0_SCK_PC0 \ GD32_PINMUX_AF('C', 0, AF4) #define SPI0_SCK_PE14 \ GD32_PINMUX_AF('E', 14, AF4) /* SPI1_MISO */ #define SPI1_MISO_PD15 \ GD32_PINMUX_AF('D', 15, AF4) #define SPI1_MISO_PE4 \ GD32_PINMUX_AF('E', 4, AF4) /* SPI1_MOSI */ #define SPI1_MOSI_PA9 \ GD32_PINMUX_AF('A', 9, AF4) #define SPI1_MOSI_PB6 \ GD32_PINMUX_AF('B', 6, AF5) #define SPI1_MOSI_PD14 \ GD32_PINMUX_AF('D', 14, AF4) /* SPI1_NSS */ #define SPI1_NSS_PA8 \ GD32_PINMUX_AF('A', 8, AF4) #define SPI1_NSS_PB5 \ GD32_PINMUX_AF('B', 5, AF5) #define SPI1_NSS_PD1 \ GD32_PINMUX_AF('D', 1, AF4) #define SPI1_NSS_PD10 \ GD32_PINMUX_AF('D', 10, AF4) #define SPI1_NSS_PD13 \ GD32_PINMUX_AF('D', 13, AF4) /* SPI1_SCK */ #define SPI1_SCK_PC6 \ GD32_PINMUX_AF('C', 6, AF4) #define SPI1_SCK_PE5 \ GD32_PINMUX_AF('E', 5, AF4) /* SWCLK */ #define SWCLK_PB8 \ GD32_PINMUX_AF('B', 8, AF0) /* SWDIO */ #define SWDIO_PB9 \ GD32_PINMUX_AF('B', 9, AF0) /* TIMER0_BRKIN0 */ #define TIMER0_BRKIN0_PA8 \ GD32_PINMUX_AF('A', 8, AF1) #define TIMER0_BRKIN0_PD5 \ GD32_PINMUX_AF('D', 5, AF7) #define TIMER0_BRKIN0_PF2 \ GD32_PINMUX_AF('F', 2, AF1) /* TIMER0_BRKIN1 */ #define TIMER0_BRKIN1_PD10 \ GD32_PINMUX_AF('D', 10, AF2) #define TIMER0_BRKIN1_PF1 \ GD32_PINMUX_AF('F', 1, AF1) /* TIMER0_BRKIN2 */ #define TIMER0_BRKIN2_PD9 \ GD32_PINMUX_AF('D', 9, AF2) #define TIMER0_BRKIN2_PF4 \ GD32_PINMUX_AF('F', 4, AF2) /* TIMER0_BRKIN3 */ #define TIMER0_BRKIN3_PC9 \ GD32_PINMUX_AF('C', 9, AF1) #define TIMER0_BRKIN3_PF3 \ GD32_PINMUX_AF('F', 3, AF2) /* TIMER0_CH0 */ #define TIMER0_CH0_PB2 \ GD32_PINMUX_AF('B', 2, AF1) #define TIMER0_CH0_PC0 \ GD32_PINMUX_AF('C', 0, AF1) #define TIMER0_CH0_PC8 \ GD32_PINMUX_AF('C', 8, AF1) /* TIMER0_CH1 */ #define TIMER0_CH1_PA4 \ GD32_PINMUX_AF('A', 4, AF1) #define TIMER0_CH1_PC6 \ GD32_PINMUX_AF('C', 6, AF1) #define TIMER0_CH1_PE5 \ GD32_PINMUX_AF('E', 5, AF1) /* TIMER0_CH2 */ #define TIMER0_CH2_PA2 \ GD32_PINMUX_AF('A', 2, AF1) #define TIMER0_CH2_PD14 \ GD32_PINMUX_AF('D', 14, AF1) /* TIMER0_CH3 */ #define TIMER0_CH3_PA0 \ GD32_PINMUX_AF('A', 0, AF1) #define TIMER0_CH3_PD12 \ GD32_PINMUX_AF('D', 12, AF1) /* TIMER0_MCH0 */ #define TIMER0_MCH0_PB1 \ GD32_PINMUX_AF('B', 1, AF1) #define TIMER0_MCH0_PC7 \ GD32_PINMUX_AF('C', 7, AF1) #define TIMER0_MCH0_PF5 \ GD32_PINMUX_AF('F', 5, AF1) /* TIMER0_MCH1 */ #define TIMER0_MCH1_PA3 \ GD32_PINMUX_AF('A', 3, AF1) #define TIMER0_MCH1_PD15 \ GD32_PINMUX_AF('D', 15, AF1) #define TIMER0_MCH1_PE4 \ GD32_PINMUX_AF('E', 4, AF1) /* TIMER0_MCH2 */ #define TIMER0_MCH2_PA1 \ GD32_PINMUX_AF('A', 1, AF1) #define TIMER0_MCH2_PD13 \ GD32_PINMUX_AF('D', 13, AF1) /* TIMER0_MCH3 */ #define TIMER0_MCH3_PC1 \ GD32_PINMUX_AF('C', 1, AF1) #define TIMER0_MCH3_PD11 \ GD32_PINMUX_AF('D', 11, AF1) /* TIMER19_BRKIN0 */ #define TIMER19_BRKIN0_PC14 \ GD32_PINMUX_AF('C', 14, AF2) /* TIMER19_BRKIN1 */ #define TIMER19_BRKIN1_PA7 \ GD32_PINMUX_AF('A', 7, AF3) #define TIMER19_BRKIN1_PF1 \ GD32_PINMUX_AF('F', 1, AF2) /* TIMER19_BRKIN2 */ #define TIMER19_BRKIN2_PA6 \ GD32_PINMUX_AF('A', 6, AF2) #define TIMER19_BRKIN2_PE8 \ GD32_PINMUX_AF('E', 8, AF2) /* TIMER19_BRKIN3 */ #define TIMER19_BRKIN3_PA5 \ GD32_PINMUX_AF('A', 5, AF2) #define TIMER19_BRKIN3_PE7 \ GD32_PINMUX_AF('E', 7, AF2) /* TIMER19_CH0 */ #define TIMER19_CH0_PB0 \ GD32_PINMUX_AF('B', 0, AF1) #define TIMER19_CH0_PB7 \ GD32_PINMUX_AF('B', 7, AF1) #define TIMER19_CH0_PC5 \ GD32_PINMUX_AF('C', 5, AF2) #define TIMER19_CH0_PC11 \ GD32_PINMUX_AF('C', 11, AF2) #define TIMER19_CH0_PD6 \ GD32_PINMUX_AF('D', 6, AF2) #define TIMER19_CH0_PE5 \ GD32_PINMUX_AF('E', 5, AF2) /* TIMER19_CH1 */ #define TIMER19_CH1_PB0 \ GD32_PINMUX_AF('B', 0, AF2) #define TIMER19_CH1_PB7 \ GD32_PINMUX_AF('B', 7, AF2) #define TIMER19_CH1_PC4 \ GD32_PINMUX_AF('C', 4, AF1) #define TIMER19_CH1_PC15 \ GD32_PINMUX_AF('C', 15, AF2) #define TIMER19_CH1_PD7 \ GD32_PINMUX_AF('D', 7, AF2) #define TIMER19_CH1_PF0 \ GD32_PINMUX_AF('F', 0, AF1) /* TIMER19_CH2 */ #define TIMER19_CH2_PC3 \ GD32_PINMUX_AF('C', 3, AF1) #define TIMER19_CH2_PC13 \ GD32_PINMUX_AF('C', 13, AF1) /* TIMER19_CH3 */ #define TIMER19_CH3_PB10 \ GD32_PINMUX_AF('B', 10, AF2) #define TIMER19_CH3_PE3 \ GD32_PINMUX_AF('E', 3, AF0) /* TIMER19_MCH0 */ #define TIMER19_MCH0_PC5 \ GD32_PINMUX_AF('C', 5, AF1) #define TIMER19_MCH0_PC11 \ GD32_PINMUX_AF('C', 11, AF1) #define TIMER19_MCH0_PE4 \ GD32_PINMUX_AF('E', 4, AF2) /* TIMER19_MCH1 */ #define TIMER19_MCH1_PA7 \ GD32_PINMUX_AF('A', 7, AF1) #define TIMER19_MCH1_PC15 \ GD32_PINMUX_AF('C', 15, AF1) /* TIMER19_MCH2 */ #define TIMER19_MCH2_PC2 \ GD32_PINMUX_AF('C', 2, AF1) #define TIMER19_MCH2_PE6 \ GD32_PINMUX_AF('E', 6, AF2) /* TIMER19_MCH3 */ #define TIMER19_MCH3_PE2 \ GD32_PINMUX_AF('E', 2, AF2) #define TIMER19_MCH3_PE15 \ GD32_PINMUX_AF('E', 15, AF2) /* TIMER1_CH0 */ #define TIMER1_CH0_PE6 \ GD32_PINMUX_AF('E', 6, AF1) /* TIMER1_CH1 */ #define TIMER1_CH1_PA7 \ GD32_PINMUX_AF('A', 7, AF2) /* TIMER1_CH2 */ #define TIMER1_CH2_PB14 \ GD32_PINMUX_AF('B', 14, AF1) #define TIMER1_CH2_PD4 \ GD32_PINMUX_AF('D', 4, AF2) /* TIMER1_CH3 */ #define TIMER1_CH3_PA3 \ GD32_PINMUX_AF('A', 3, AF2) #define TIMER1_CH3_PB11 \ GD32_PINMUX_AF('B', 11, AF2) /* TIMER1_ETI */ #define TIMER1_ETI_PE6 \ GD32_PINMUX_AF('E', 6, AF1) /* TIMER20_BRKIN0 */ #define TIMER20_BRKIN0_PD11 \ GD32_PINMUX_AF('D', 11, AF2) #define TIMER20_BRKIN0_PD12 \ GD32_PINMUX_AF('D', 12, AF2) /* TIMER20_BRKIN1 */ #define TIMER20_BRKIN1_PC7 \ GD32_PINMUX_AF('C', 7, AF2) #define TIMER20_BRKIN1_PD5 \ GD32_PINMUX_AF('D', 5, AF12) /* TIMER20_BRKIN2 */ #define TIMER20_BRKIN2_PC8 \ GD32_PINMUX_AF('C', 8, AF2) #define TIMER20_BRKIN2_PE0 \ GD32_PINMUX_AF('E', 0, AF1) /* TIMER20_BRKIN3 */ #define TIMER20_BRKIN3_PC9 \ GD32_PINMUX_AF('C', 9, AF2) #define TIMER20_BRKIN3_PE1 \ GD32_PINMUX_AF('E', 1, AF1) /* TIMER20_CH0 */ #define TIMER20_CH0_PA11 \ GD32_PINMUX_AF('A', 11, AF1) #define TIMER20_CH0_PA15 \ GD32_PINMUX_AF('A', 15, AF1) /* TIMER20_CH1 */ #define TIMER20_CH1_PA13 \ GD32_PINMUX_AF('A', 13, AF1) #define TIMER20_CH1_PD0 \ GD32_PINMUX_AF('D', 0, AF1) /* TIMER20_CH2 */ #define TIMER20_CH2_PA9 \ GD32_PINMUX_AF('A', 9, AF1) #define TIMER20_CH2_PB12 \ GD32_PINMUX_AF('B', 12, AF1) /* TIMER20_CH3 */ #define TIMER20_CH3_PB10 \ GD32_PINMUX_AF('B', 10, AF1) #define TIMER20_CH3_PD4 \ GD32_PINMUX_AF('D', 4, AF1) /* TIMER20_MCH0 */ #define TIMER20_MCH0_PA10 \ GD32_PINMUX_AF('A', 10, AF1) #define TIMER20_MCH0_PA14 \ GD32_PINMUX_AF('A', 14, AF1) /* TIMER20_MCH1 */ #define TIMER20_MCH1_PA12 \ GD32_PINMUX_AF('A', 12, AF1) #define TIMER20_MCH1_PC12 \ GD32_PINMUX_AF('C', 12, AF1) /* TIMER20_MCH2 */ #define TIMER20_MCH2_PA8 \ GD32_PINMUX_AF('A', 8, AF2) #define TIMER20_MCH2_PB11 \ GD32_PINMUX_AF('B', 11, AF1) /* TIMER20_MCH3 */ #define TIMER20_MCH3_PD3 \ GD32_PINMUX_AF('D', 3, AF1) #define TIMER20_MCH3_PE15 \ GD32_PINMUX_AF('E', 15, AF1) /* TIMER7_BRKIN0 */ #define TIMER7_BRKIN0_PD5 \ GD32_PINMUX_AF('D', 5, AF12) #define TIMER7_BRKIN0_PD8 \ GD32_PINMUX_AF('D', 8, AF2) /* TIMER7_BRKIN1 */ #define TIMER7_BRKIN1_PB5 \ GD32_PINMUX_AF('B', 5, AF2) #define TIMER7_BRKIN1_PB15 \ GD32_PINMUX_AF('B', 15, AF2) /* TIMER7_BRKIN2 */ #define TIMER7_BRKIN2_PB6 \ GD32_PINMUX_AF('B', 6, AF2) #define TIMER7_BRKIN2_PE10 \ GD32_PINMUX_AF('E', 10, AF2) /* TIMER7_BRKIN3 */ #define TIMER7_BRKIN3_PE0 \ GD32_PINMUX_AF('E', 0, AF2) #define TIMER7_BRKIN3_PE9 \ GD32_PINMUX_AF('E', 9, AF2) /* TIMER7_CH0 */ #define TIMER7_CH0_PB8 \ GD32_PINMUX_AF('B', 8, AF1) #define TIMER7_CH0_PC10 \ GD32_PINMUX_AF('C', 10, AF2) #define TIMER7_CH0_PC12 \ GD32_PINMUX_AF('C', 12, AF2) #define TIMER7_CH0_PE13 \ GD32_PINMUX_AF('E', 13, AF2) #define TIMER7_CH0_PE14 \ GD32_PINMUX_AF('E', 14, AF1) /* TIMER7_CH1 */ #define TIMER7_CH1_PB8 \ GD32_PINMUX_AF('B', 8, AF2) #define TIMER7_CH1_PD0 \ GD32_PINMUX_AF('D', 0, AF2) #define TIMER7_CH1_PD2 \ GD32_PINMUX_AF('D', 2, AF1) #define TIMER7_CH1_PE12 \ GD32_PINMUX_AF('E', 12, AF1) #define TIMER7_CH1_PE14 \ GD32_PINMUX_AF('E', 14, AF2) /* TIMER7_CH2 */ #define TIMER7_CH2_PB4 \ GD32_PINMUX_AF('B', 4, AF1) #define TIMER7_CH2_PE8 \ GD32_PINMUX_AF('E', 8, AF1) /* TIMER7_CH3 */ #define TIMER7_CH3_PB2 \ GD32_PINMUX_AF('B', 2, AF2) #define TIMER7_CH3_PD7 \ GD32_PINMUX_AF('D', 7, AF1) /* TIMER7_MCH0 */ #define TIMER7_MCH0_PC10 \ GD32_PINMUX_AF('C', 10, AF1) #define TIMER7_MCH0_PE13 \ GD32_PINMUX_AF('E', 13, AF1) /* TIMER7_MCH1 */ #define TIMER7_MCH1_PD1 \ GD32_PINMUX_AF('D', 1, AF1) #define TIMER7_MCH1_PE11 \ GD32_PINMUX_AF('E', 11, AF1) /* TIMER7_MCH2 */ #define TIMER7_MCH2_PB3 \ GD32_PINMUX_AF('B', 3, AF1) #define TIMER7_MCH2_PE7 \ GD32_PINMUX_AF('E', 7, AF1) /* TIMER7_MCH3 */ #define TIMER7_MCH3_PB1 \ GD32_PINMUX_AF('B', 1, AF2) #define TIMER7_MCH3_PD6 \ GD32_PINMUX_AF('D', 6, AF1) /* TIMER_ETI0 */ #define TIMER_ETI0_PB13 \ GD32_PINMUX_AF('B', 13, AF0) /* TIMER_ETI1 */ #define TIMER_ETI1_PB6 \ GD32_PINMUX_AF('B', 6, AF3) /* TIMER_ETI2 */ #define TIMER_ETI2_PC15 \ GD32_PINMUX_AF('C', 15, AF0) /* TIMRE19_BRKIN0 */ #define TIMRE19_BRKIN0_PF2 \ GD32_PINMUX_AF('F', 2, AF2) /* TRIGSEL_IN0 */ #define TRIGSEL_IN0_PA1 \ GD32_PINMUX_AF('A', 1, AF7) /* TRIGSEL_IN1 */ #define TRIGSEL_IN1_PA2 \ GD32_PINMUX_AF('A', 2, AF7) /* TRIGSEL_IN10 */ #define TRIGSEL_IN10_PB11 \ GD32_PINMUX_AF('B', 11, AF7) /* TRIGSEL_IN11 */ #define TRIGSEL_IN11_PB12 \ GD32_PINMUX_AF('B', 12, AF7) /* TRIGSEL_IN12 */ #define TRIGSEL_IN12_PA15 \ GD32_PINMUX_AF('A', 15, AF7) /* TRIGSEL_IN13 */ #define TRIGSEL_IN13_PA11 \ GD32_PINMUX_AF('A', 11, AF7) /* TRIGSEL_IN2 */ #define TRIGSEL_IN2_PE13 \ GD32_PINMUX_AF('E', 13, AF7) /* TRIGSEL_IN3 */ #define TRIGSEL_IN3_PE14 \ GD32_PINMUX_AF('E', 14, AF7) /* TRIGSEL_IN4 */ #define TRIGSEL_IN4_PA8 \ GD32_PINMUX_AF('A', 8, AF7) /* TRIGSEL_IN5 */ #define TRIGSEL_IN5_PA9 \ GD32_PINMUX_AF('A', 9, AF7) /* TRIGSEL_IN6 */ #define TRIGSEL_IN6_PF2 \ GD32_PINMUX_AF('F', 2, AF6) /* TRIGSEL_IN7 */ #define TRIGSEL_IN7_PA7 \ GD32_PINMUX_AF('A', 7, AF7) /* TRIGSEL_IN8 */ #define TRIGSEL_IN8_PE11 \ GD32_PINMUX_AF('E', 11, AF7) /* TRIGSEL_IN9 */ #define TRIGSEL_IN9_PE12 \ GD32_PINMUX_AF('E', 12, AF7) /* TRIGSEL_OUT0 */ #define TRIGSEL_OUT0_PC10 \ GD32_PINMUX_AF('C', 10, AF7) /* TRIGSEL_OUT1 */ #define TRIGSEL_OUT1_PE5 \ GD32_PINMUX_AF('E', 5, AF7) /* TRIGSEL_OUT2 */ #define TRIGSEL_OUT2_PE4 \ GD32_PINMUX_AF('E', 4, AF7) /* TRIGSEL_OUT3 */ #define TRIGSEL_OUT3_PC11 \ GD32_PINMUX_AF('C', 11, AF7) /* TRIGSEL_OUT4 */ #define TRIGSEL_OUT4_PC13 \ GD32_PINMUX_AF('C', 13, AF7) /* TRIGSEL_OUT5 */ #define TRIGSEL_OUT5_PE6 \ GD32_PINMUX_AF('E', 6, AF7) /* TRIGSEL_OUT6 */ #define TRIGSEL_OUT6_PE3 \ GD32_PINMUX_AF('E', 3, AF12) /* TRIGSEL_OUT7 */ #define TRIGSEL_OUT7_PE2 \ GD32_PINMUX_AF('E', 2, AF7) /* USART0_CK */ #define USART0_CK_PA12 \ GD32_PINMUX_AF('A', 12, AF5) /* USART0_CTS */ #define USART0_CTS_PC11 \ GD32_PINMUX_AF('C', 11, AF5) #define USART0_CTS_PD8 \ GD32_PINMUX_AF('D', 8, AF5) /* USART0_DE */ #define USART0_DE_PB15 \ GD32_PINMUX_AF('B', 15, AF5) #define USART0_DE_PC10 \ GD32_PINMUX_AF('C', 10, AF5) /* USART0_RTS */ #define USART0_RTS_PB15 \ GD32_PINMUX_AF('B', 15, AF5) #define USART0_RTS_PC10 \ GD32_PINMUX_AF('C', 10, AF5) /* USART0_RX */ #define USART0_RX_PA4 \ GD32_PINMUX_AF('A', 4, AF5) #define USART0_RX_PA11 \ GD32_PINMUX_AF('A', 11, AF5) #define USART0_RX_PB14 \ GD32_PINMUX_AF('B', 14, AF5) /* USART0_TX */ #define USART0_TX_PA3 \ GD32_PINMUX_AF('A', 3, AF5) #define USART0_TX_PA10 \ GD32_PINMUX_AF('A', 10, AF5) #define USART0_TX_PB13 \ GD32_PINMUX_AF('B', 13, AF5) /* USART1_CK */ #define USART1_CK_PD5 \ GD32_PINMUX_AF('D', 5, AF12) /* USART1_CTS */ #define USART1_CTS_PD4 \ GD32_PINMUX_AF('D', 4, AF5) #define USART1_CTS_PD10 \ GD32_PINMUX_AF('D', 10, AF5) #define USART1_CTS_PE3 \ GD32_PINMUX_AF('E', 3, AF12) #define USART1_CTS_PF5 \ GD32_PINMUX_AF('F', 5, AF5) /* USART1_DE */ #define USART1_DE_PD3 \ GD32_PINMUX_AF('D', 3, AF5) #define USART1_DE_PD9 \ GD32_PINMUX_AF('D', 9, AF5) #define USART1_DE_PE2 \ GD32_PINMUX_AF('E', 2, AF5) /* USART1_RTS */ #define USART1_RTS_PD3 \ GD32_PINMUX_AF('D', 3, AF5) #define USART1_RTS_PD9 \ GD32_PINMUX_AF('D', 9, AF5) #define USART1_RTS_PE2 \ GD32_PINMUX_AF('E', 2, AF5) /* USART1_RX */ #define USART1_RX_PC3 \ GD32_PINMUX_AF('C', 3, AF5) #define USART1_RX_PD0 \ GD32_PINMUX_AF('D', 0, AF5) #define USART1_RX_PD8 \ GD32_PINMUX_AF('D', 8, AF4) /* USART1_TX */ #define USART1_TX_PB15 \ GD32_PINMUX_AF('B', 15, AF4) #define USART1_TX_PC2 \ GD32_PINMUX_AF('C', 2, AF5) #define USART1_TX_PC12 \ GD32_PINMUX_AF('C', 12, AF5) /* USART2_CK */ #define USART2_CK_PA7 \ GD32_PINMUX_AF('A', 7, AF5) /* USART2_CTS */ #define USART2_CTS_PB10 \ GD32_PINMUX_AF('B', 10, AF5) #define USART2_CTS_PC1 \ GD32_PINMUX_AF('C', 1, AF5) #define USART2_CTS_PC5 \ GD32_PINMUX_AF('C', 5, AF5) /* USART2_DE */ #define USART2_DE_PC4 \ GD32_PINMUX_AF('C', 4, AF5) #define USART2_DE_PE15 \ GD32_PINMUX_AF('E', 15, AF5) #define USART2_DE_PF2 \ GD32_PINMUX_AF('F', 2, AF5) /* USART2_RTS */ #define USART2_RTS_PC4 \ GD32_PINMUX_AF('C', 4, AF5) #define USART2_RTS_PE15 \ GD32_PINMUX_AF('E', 15, AF5) #define USART2_RTS_PF2 \ GD32_PINMUX_AF('F', 2, AF5) /* USART2_RX */ #define USART2_RX_PA6 \ GD32_PINMUX_AF('A', 6, AF5) #define USART2_RX_PE1 \ GD32_PINMUX_AF('E', 1, AF5) #define USART2_RX_PF4 \ GD32_PINMUX_AF('F', 4, AF5) /* USART2_TX */ #define USART2_TX_PA5 \ GD32_PINMUX_AF('A', 5, AF5) #define USART2_TX_PE0 \ GD32_PINMUX_AF('E', 0, AF5) #define USART2_TX_PF3 \ GD32_PINMUX_AF('F', 3, AF5)