1 // Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14
15 /*
16 The cache has an interrupt that can be raised as soon as an access to a cached
17 region (flash) is done without the cache being enabled. We use that here
18 to panic the CPU, which from a debugging perspective is better than grabbing bad
19 data from the bus.
20 */
21 #include "esp32h2/rom/ets_sys.h"
22 #include "esp_attr.h"
23 #include "esp_intr_alloc.h"
24 #include "soc/extmem_reg.h"
25 #include "soc/periph_defs.h"
26 #include "riscv/interrupt.h"
27
esp_cache_err_int_init(void)28 void esp_cache_err_int_init(void)
29 {
30 const uint32_t core_id = 0;
31
32 /* Disable cache interrupts if enabled. */
33 ESP_INTR_DISABLE(ETS_CACHEERR_INUM);
34
35 /**
36 * Bind all cache errors to ETS_CACHEERR_INUM interrupt. we will deal with
37 * them in handler by different types
38 * I) Cache access error
39 * 1. dbus trying to write to icache
40 * 2. dbus authentication fail
41 * 3. cpu access icache while dbus is disabled [1]
42 * 4. ibus authentication fail
43 * 5. ibus trying to write icache
44 * 6. cpu access icache while ibus is disabled
45 * II) Cache illegal error
46 * 1. dbus counter overflow
47 * 2. ibus counter overflow
48 * 3. mmu entry fault
49 * 4. icache preload configurations fault
50 * 5. icache sync configuration fault
51 *
52 * [1]: On ESP32H2 boards, the caches are shared but buses are still
53 * distinct. So, we have an ibus and a dbus sharing the same cache.
54 * This error can occur if the dbus performs a request but the icache
55 * (or simply cache) is disabled.
56 */
57 intr_matrix_set(core_id, ETS_CACHE_IA_INTR_SOURCE, ETS_CACHEERR_INUM);
58 intr_matrix_set(core_id, ETS_CACHE_CORE0_ACS_INTR_SOURCE, ETS_CACHEERR_INUM);
59
60 /* Set the type and priority to cache error interrupts. */
61 esprv_intc_int_set_type(BIT(ETS_CACHEERR_INUM), INTR_TYPE_LEVEL);
62 esprv_intc_int_set_priority(ETS_CACHEERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM);
63
64 /* On the hardware side, stat by clearing all the bits reponsible for
65 * enabling cache access error interrupts. */
66 SET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_CLR_REG,
67 EXTMEM_CORE0_DBUS_WR_IC_INT_CLR |
68 EXTMEM_CORE0_DBUS_REJECT_INT_CLR |
69 EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR |
70 EXTMEM_CORE0_IBUS_REJECT_INT_CLR |
71 EXTMEM_CORE0_IBUS_WR_IC_INT_CLR |
72 EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR);
73
74 /* Enable these interrupts. */
75 SET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_ENA_REG,
76 EXTMEM_CORE0_DBUS_WR_IC_INT_ENA |
77 EXTMEM_CORE0_DBUS_REJECT_INT_ENA |
78 EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA |
79 EXTMEM_CORE0_IBUS_REJECT_INT_ENA |
80 EXTMEM_CORE0_IBUS_WR_IC_INT_ENA |
81 EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA);
82
83 /* Same goes for cache illegal error: start by clearing the bits and then
84 * set them back. */
85 SET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_CLR_REG,
86 EXTMEM_MMU_ENTRY_FAULT_INT_CLR |
87 EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR |
88 EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR);
89
90 SET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_ENA_REG,
91 EXTMEM_MMU_ENTRY_FAULT_INT_ENA |
92 EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA |
93 EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA);
94
95 /* Enable the interrupts for cache error. */
96 ESP_INTR_ENABLE(ETS_CACHEERR_INUM);
97 }
98
esp_cache_err_get_cpuid(void)99 int IRAM_ATTR esp_cache_err_get_cpuid(void)
100 {
101 return 0;
102 }
103
