1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>WDT</name> 5 <description>Windowed Watchdog Timer</description> 6 <baseAddress>0x40003000</baseAddress> 7 <addressBlock> 8 <offset>0x00</offset> 9 <size>0x0400</size> 10 <usage>registers</usage> 11 </addressBlock> 12 <interrupt> 13 <name>WWDT</name> 14<!-- IRQ Name --> 15 <value>1</value> 16<!-- IRQ Number Device Specific --> 17 </interrupt> 18 <registers> 19 <register> 20 <name>CTRL</name> 21 <description>Watchdog Timer Control Register.</description> 22 <addressOffset>0x00</addressOffset> 23 <access>read-write</access> 24 <fields> 25 <field> 26 <name>INT_LATE_VAL</name> 27 <description>Windowed Watchdog Interrupt Upper Limit. Sets the number of WDTCLK cycles until a windowed watchdog timer interrupt is generated (if enabled) if the CPU does not write the windowed watchdog reset sequence to the WWDT_RST register before the watchdog timer has counted this time period since the last timer reset.</description> 28 <bitOffset>0</bitOffset> 29 <bitWidth>4</bitWidth> 30 <enumeratedValues> 31 <enumeratedValue> 32 <name>wdt2pow31</name> 33 <description>2**31 clock cycles.</description> 34 <value>0</value> 35 </enumeratedValue> 36 <enumeratedValue> 37 <name>wdt2pow30</name> 38 <description>2**30 clock cycles.</description> 39 <value>1</value> 40 </enumeratedValue> 41 <enumeratedValue> 42 <name>wdt2pow29</name> 43 <description>2**29 clock cycles.</description> 44 <value>2</value> 45 </enumeratedValue> 46 <enumeratedValue> 47 <name>wdt2pow28</name> 48 <description>2**28 clock cycles.</description> 49 <value>3</value> 50 </enumeratedValue> 51 <enumeratedValue> 52 <name>wdt2pow27</name> 53 <description>2^27 clock cycles.</description> 54 <value>4</value> 55 </enumeratedValue> 56 <enumeratedValue> 57 <name>wdt2pow26</name> 58 <description>2**26 clock cycles.</description> 59 <value>5</value> 60 </enumeratedValue> 61 <enumeratedValue> 62 <name>wdt2pow25</name> 63 <description>2**25 clock cycles.</description> 64 <value>6</value> 65 </enumeratedValue> 66 <enumeratedValue> 67 <name>wdt2pow24</name> 68 <description>2**24 clock cycles.</description> 69 <value>7</value> 70 </enumeratedValue> 71 <enumeratedValue> 72 <name>wdt2pow23</name> 73 <description>2**23 clock cycles.</description> 74 <value>8</value> 75 </enumeratedValue> 76 <enumeratedValue> 77 <name>wdt2pow22</name> 78 <description>2**22 clock cycles.</description> 79 <value>9</value> 80 </enumeratedValue> 81 <enumeratedValue> 82 <name>wdt2pow21</name> 83 <description>2**21 clock cycles.</description> 84 <value>10</value> 85 </enumeratedValue> 86 <enumeratedValue> 87 <name>wdt2pow20</name> 88 <description>2**20 clock cycles.</description> 89 <value>11</value> 90 </enumeratedValue> 91 <enumeratedValue> 92 <name>wdt2pow19</name> 93 <description>2**19 clock cycles.</description> 94 <value>12</value> 95 </enumeratedValue> 96 <enumeratedValue> 97 <name>wdt2pow18</name> 98 <description>2**18 clock cycles.</description> 99 <value>13</value> 100 </enumeratedValue> 101 <enumeratedValue> 102 <name>wdt2pow17</name> 103 <description>2**17 clock cycles.</description> 104 <value>14</value> 105 </enumeratedValue> 106 <enumeratedValue> 107 <name>wdt2pow16</name> 108 <description>2**16 clock cycles.</description> 109 <value>15</value> 110 </enumeratedValue> 111 </enumeratedValues> 112 </field> 113 <field> 114 <name>RST_LATE_VAL</name> 115 <description>Windowed Watchdog Reset Upper Limit. Sets the number of WDTCLK cycles until a system reset occurs (if enabled) if the CPU does not write the watchdog reset sequence to the WDT_RST register before the watchdog timer has counted this time period since the last timer reset.</description> 116 <bitOffset>4</bitOffset> 117 <bitWidth>4</bitWidth> 118 <enumeratedValues> 119 <enumeratedValue> 120 <name>wdt2pow31</name> 121 <description>2**31 clock cycles.</description> 122 <value>0</value> 123 </enumeratedValue> 124 <enumeratedValue> 125 <name>wdt2pow30</name> 126 <description>2**30 clock cycles.</description> 127 <value>1</value> 128 </enumeratedValue> 129 <enumeratedValue> 130 <name>wdt2pow29</name> 131 <description>2**29 clock cycles.</description> 132 <value>2</value> 133 </enumeratedValue> 134 <enumeratedValue> 135 <name>wdt2pow28</name> 136 <description>2**28 clock cycles.</description> 137 <value>3</value> 138 </enumeratedValue> 139 <enumeratedValue> 140 <name>wdt2pow27</name> 141 <description>2^27 clock cycles.</description> 142 <value>4</value> 143 </enumeratedValue> 144 <enumeratedValue> 145 <name>wdt2pow26</name> 146 <description>2**26 clock cycles.</description> 147 <value>5</value> 148 </enumeratedValue> 149 <enumeratedValue> 150 <name>wdt2pow25</name> 151 <description>2**25 clock cycles.</description> 152 <value>6</value> 153 </enumeratedValue> 154 <enumeratedValue> 155 <name>wdt2pow24</name> 156 <description>2**24 clock cycles.</description> 157 <value>7</value> 158 </enumeratedValue> 159 <enumeratedValue> 160 <name>wdt2pow23</name> 161 <description>2**23 clock cycles.</description> 162 <value>8</value> 163 </enumeratedValue> 164 <enumeratedValue> 165 <name>wdt2pow22</name> 166 <description>2**22 clock cycles.</description> 167 <value>9</value> 168 </enumeratedValue> 169 <enumeratedValue> 170 <name>wdt2pow21</name> 171 <description>2**21 clock cycles.</description> 172 <value>10</value> 173 </enumeratedValue> 174 <enumeratedValue> 175 <name>wdt2pow20</name> 176 <description>2**20 clock cycles.</description> 177 <value>11</value> 178 </enumeratedValue> 179 <enumeratedValue> 180 <name>wdt2pow19</name> 181 <description>2**19 clock cycles.</description> 182 <value>12</value> 183 </enumeratedValue> 184 <enumeratedValue> 185 <name>wdt2pow18</name> 186 <description>2**18 clock cycles.</description> 187 <value>13</value> 188 </enumeratedValue> 189 <enumeratedValue> 190 <name>wdt2pow17</name> 191 <description>2**17 clock cycles.</description> 192 <value>14</value> 193 </enumeratedValue> 194 <enumeratedValue> 195 <name>wdt2pow16</name> 196 <description>2**16 clock cycles.</description> 197 <value>15</value> 198 </enumeratedValue> 199 </enumeratedValues> 200 </field> 201 <field> 202 <name>EN</name> 203 <description>Windowed Watchdog Timer Enable.</description> 204 <bitOffset>8</bitOffset> 205 <bitWidth>1</bitWidth> 206 <enumeratedValues> 207 <enumeratedValue> 208 <name>dis</name> 209 <description>Disable.</description> 210 <value>0</value> 211 </enumeratedValue> 212 <enumeratedValue> 213 <name>en</name> 214 <description>Enable.</description> 215 <value>1</value> 216 </enumeratedValue> 217 </enumeratedValues> 218 </field> 219 <field> 220 <name>INT_LATE</name> 221 <description>Windowed Watchdog Timer Interrupt Flag Too Late.</description> 222 <bitOffset>9</bitOffset> 223 <bitWidth>1</bitWidth> 224 <enumeratedValues> 225 <usage>read-write</usage> 226 <enumeratedValue> 227 <name>inactive</name> 228 <description>No interrupt is pending.</description> 229 <value>0</value> 230 </enumeratedValue> 231 <enumeratedValue> 232 <name>pending</name> 233 <description>An interrupt is pending.</description> 234 <value>1</value> 235 </enumeratedValue> 236 </enumeratedValues> 237 </field> 238 <field> 239 <name>WDT_INT_EN</name> 240 <description>Windowed Watchdog Timer Interrupt Enable.</description> 241 <bitOffset>10</bitOffset> 242 <bitWidth>1</bitWidth> 243 <enumeratedValues> 244 <enumeratedValue> 245 <name>dis</name> 246 <description>Disable.</description> 247 <value>0</value> 248 </enumeratedValue> 249 <enumeratedValue> 250 <name>en</name> 251 <description>Enable.</description> 252 <value>1</value> 253 </enumeratedValue> 254 </enumeratedValues> 255 </field> 256 <field> 257 <name>WDT_RST_EN</name> 258 <description>Windowed Watchdog Timer Reset Enable.</description> 259 <bitOffset>11</bitOffset> 260 <bitWidth>1</bitWidth> 261 <enumeratedValues> 262 <enumeratedValue> 263 <name>dis</name> 264 <description>Disable.</description> 265 <value>0</value> 266 </enumeratedValue> 267 <enumeratedValue> 268 <name>en</name> 269 <description>Enable.</description> 270 <value>1</value> 271 </enumeratedValue> 272 </enumeratedValues> 273 </field> 274 <field> 275 <name>INT_EARLY</name> 276 <description>Windowed Watchdog Timer Interrupt Flag Too Soon.</description> 277 <bitOffset>12</bitOffset> 278 <bitWidth>1</bitWidth> 279 <enumeratedValues> 280 <usage>read-write</usage> 281 <enumeratedValue> 282 <name>inactive</name> 283 <description>No interrupt is pending.</description> 284 <value>0</value> 285 </enumeratedValue> 286 <enumeratedValue> 287 <name>pending</name> 288 <description>An interrupt is pending.</description> 289 <value>1</value> 290 </enumeratedValue> 291 </enumeratedValues> 292 </field> 293 <field> 294 <name>INT_EARLY_VAL</name> 295 <description>Windowed Watchdog Interrupt Lower Limit. Sets the number of WDTCLK cycles that establishes the lower boundary of the watchdog window. A windowed watchdog timer interrupt is generated (if enabled) if the CPU writes the windowed watchdog reset sequence to the WWDT_RST register before the watchdog timer has counted this time period since the last timer reset.</description> 296 <bitOffset>16</bitOffset> 297 <bitWidth>4</bitWidth> 298 <enumeratedValues> 299 <enumeratedValue> 300 <name>wdt2pow31</name> 301 <description>2**31 clock cycles.</description> 302 <value>0</value> 303 </enumeratedValue> 304 <enumeratedValue> 305 <name>wdt2pow30</name> 306 <description>2**30 clock cycles.</description> 307 <value>1</value> 308 </enumeratedValue> 309 <enumeratedValue> 310 <name>wdt2pow29</name> 311 <description>2**29 clock cycles.</description> 312 <value>2</value> 313 </enumeratedValue> 314 <enumeratedValue> 315 <name>wdt2pow28</name> 316 <description>2**28 clock cycles.</description> 317 <value>3</value> 318 </enumeratedValue> 319 <enumeratedValue> 320 <name>wdt2pow27</name> 321 <description>2^27 clock cycles.</description> 322 <value>4</value> 323 </enumeratedValue> 324 <enumeratedValue> 325 <name>wdt2pow26</name> 326 <description>2**26 clock cycles.</description> 327 <value>5</value> 328 </enumeratedValue> 329 <enumeratedValue> 330 <name>wdt2pow25</name> 331 <description>2**25 clock cycles.</description> 332 <value>6</value> 333 </enumeratedValue> 334 <enumeratedValue> 335 <name>wdt2pow24</name> 336 <description>2**24 clock cycles.</description> 337 <value>7</value> 338 </enumeratedValue> 339 <enumeratedValue> 340 <name>wdt2pow23</name> 341 <description>2**23 clock cycles.</description> 342 <value>8</value> 343 </enumeratedValue> 344 <enumeratedValue> 345 <name>wdt2pow22</name> 346 <description>2**22 clock cycles.</description> 347 <value>9</value> 348 </enumeratedValue> 349 <enumeratedValue> 350 <name>wdt2pow21</name> 351 <description>2**21 clock cycles.</description> 352 <value>10</value> 353 </enumeratedValue> 354 <enumeratedValue> 355 <name>wdt2pow20</name> 356 <description>2**20 clock cycles.</description> 357 <value>11</value> 358 </enumeratedValue> 359 <enumeratedValue> 360 <name>wdt2pow19</name> 361 <description>2**19 clock cycles.</description> 362 <value>12</value> 363 </enumeratedValue> 364 <enumeratedValue> 365 <name>wdt2pow18</name> 366 <description>2**18 clock cycles.</description> 367 <value>13</value> 368 </enumeratedValue> 369 <enumeratedValue> 370 <name>wdt2pow17</name> 371 <description>2**17 clock cycles.</description> 372 <value>14</value> 373 </enumeratedValue> 374 <enumeratedValue> 375 <name>wdt2pow16</name> 376 <description>2**16 clock cycles.</description> 377 <value>15</value> 378 </enumeratedValue> 379 </enumeratedValues> 380 </field> 381 <field> 382 <name>RST_EARLY_VAL</name> 383 <description>Windowed Watchdog Reset Lower Limit. Sets the number of WDTCLK cycles that establishes the lower boundary of the watchdog window. A system reset occurs (if enabled) if the CPU writes the windowed watchdog reset sequence to the WWDT_RST register before the watchdog timer has counted this time period since the last timer reset.</description> 384 <bitOffset>20</bitOffset> 385 <bitWidth>4</bitWidth> 386 <enumeratedValues> 387 <enumeratedValue> 388 <name>wdt2pow31</name> 389 <description>2**31 clock cycles.</description> 390 <value>0</value> 391 </enumeratedValue> 392 <enumeratedValue> 393 <name>wdt2pow30</name> 394 <description>2**30 clock cycles.</description> 395 <value>1</value> 396 </enumeratedValue> 397 <enumeratedValue> 398 <name>wdt2pow29</name> 399 <description>2**29 clock cycles.</description> 400 <value>2</value> 401 </enumeratedValue> 402 <enumeratedValue> 403 <name>wdt2pow28</name> 404 <description>2**28 clock cycles.</description> 405 <value>3</value> 406 </enumeratedValue> 407 <enumeratedValue> 408 <name>wdt2pow27</name> 409 <description>2^27 clock cycles.</description> 410 <value>4</value> 411 </enumeratedValue> 412 <enumeratedValue> 413 <name>wdt2pow26</name> 414 <description>2**26 clock cycles.</description> 415 <value>5</value> 416 </enumeratedValue> 417 <enumeratedValue> 418 <name>wdt2pow25</name> 419 <description>2**25 clock cycles.</description> 420 <value>6</value> 421 </enumeratedValue> 422 <enumeratedValue> 423 <name>wdt2pow24</name> 424 <description>2**24 clock cycles.</description> 425 <value>7</value> 426 </enumeratedValue> 427 <enumeratedValue> 428 <name>wdt2pow23</name> 429 <description>2**23 clock cycles.</description> 430 <value>8</value> 431 </enumeratedValue> 432 <enumeratedValue> 433 <name>wdt2pow22</name> 434 <description>2**22 clock cycles.</description> 435 <value>9</value> 436 </enumeratedValue> 437 <enumeratedValue> 438 <name>wdt2pow21</name> 439 <description>2**21 clock cycles.</description> 440 <value>10</value> 441 </enumeratedValue> 442 <enumeratedValue> 443 <name>wdt2pow20</name> 444 <description>2**20 clock cycles.</description> 445 <value>11</value> 446 </enumeratedValue> 447 <enumeratedValue> 448 <name>wdt2pow19</name> 449 <description>2**19 clock cycles.</description> 450 <value>12</value> 451 </enumeratedValue> 452 <enumeratedValue> 453 <name>wdt2pow18</name> 454 <description>2**18 clock cycles.</description> 455 <value>13</value> 456 </enumeratedValue> 457 <enumeratedValue> 458 <name>wdt2pow17</name> 459 <description>2**17 clock cycles.</description> 460 <value>14</value> 461 </enumeratedValue> 462 <enumeratedValue> 463 <name>wdt2pow16</name> 464 <description>2**16 clock cycles.</description> 465 <value>15</value> 466 </enumeratedValue> 467 </enumeratedValues> 468 </field> 469 <field> 470 <name>CLKRDY_IE</name> 471 <description>Switch Ready Interrupt Enable. Fires an interrupt when it is safe to swithc the clock.</description> 472 <bitOffset>27</bitOffset> 473 <bitWidth>1</bitWidth> 474 </field> 475 <field> 476 <name>CLKRDY</name> 477 <description>Clock Status.</description> 478 <bitOffset>28</bitOffset> 479 <bitWidth>1</bitWidth> 480 </field> 481 <field> 482 <name>WIN_EN</name> 483 <description>Enables the Windowed Watchdog Function.</description> 484 <bitOffset>29</bitOffset> 485 <bitWidth>1</bitWidth> 486 <enumeratedValues> 487 <enumeratedValue> 488 <name>dis</name> 489 <description>Windowed Mode Disabled (i.e. Compatibility Mode).</description> 490 <value>0</value> 491 </enumeratedValue> 492 <enumeratedValue> 493 <name>en</name> 494 <description>Windowed Mode Enabled.</description> 495 <value>1</value> 496 </enumeratedValue> 497 </enumeratedValues> 498 </field> 499 <field> 500 <name>RST_EARLY</name> 501 <description>Windowed Watchdog Timer Reset Flag Too Soon.</description> 502 <bitOffset>30</bitOffset> 503 <bitWidth>1</bitWidth> 504 <enumeratedValues> 505 <usage>read-write</usage> 506 <enumeratedValue> 507 <name>noEvent</name> 508 <description>The event has not occurred.</description> 509 <value>0</value> 510 </enumeratedValue> 511 <enumeratedValue> 512 <name>occurred</name> 513 <description>The event has occurred.</description> 514 <value>1</value> 515 </enumeratedValue> 516 </enumeratedValues> 517 </field> 518 <field> 519 <name>RST_LATE</name> 520 <description>Windowed Watchdog Timer Reset Flag Too Late.</description> 521 <bitOffset>31</bitOffset> 522 <bitWidth>1</bitWidth> 523 <enumeratedValues> 524 <usage>read-write</usage> 525 <enumeratedValue> 526 <name>noEvent</name> 527 <description>The event has not occurred.</description> 528 <value>0</value> 529 </enumeratedValue> 530 <enumeratedValue> 531 <name>occurred</name> 532 <description>The event has occurred.</description> 533 <value>1</value> 534 </enumeratedValue> 535 </enumeratedValues> 536 </field> 537 </fields> 538 </register> 539 <register> 540 <name>RST</name> 541 <description>Windowed Watchdog Timer Reset Register.</description> 542 <addressOffset>0x04</addressOffset> 543 <access>write-only</access> 544 <fields> 545 <field> 546 <name>RESET</name> 547 <description>Writing the watchdog counter 'reset sequence' to this register resets the watchdog counter. If the watchdog count exceeds INT_PERIOD_UPPER_LIMIT then a watchdog interrupt will occur, if enabled. If the watchdog count exceeds RST_PERIOD_UPPER_LIMIT then a watchdog reset will occur, if enabled.</description> 548 <bitOffset>0</bitOffset> 549 <bitWidth>8</bitWidth> 550 <enumeratedValues> 551 <enumeratedValue> 552 <name>seq0</name> 553 <description>The first value to be written to reset the WDT.</description> 554 <value>0x000000A5</value> 555 </enumeratedValue> 556 <enumeratedValue> 557 <name>seq1</name> 558 <description>The second value to be written to reset the WDT.</description> 559 <value>0x0000005A</value> 560 </enumeratedValue> 561 </enumeratedValues> 562 </field> 563 </fields> 564 </register> 565 <register> 566 <name>CLKSEL</name> 567 <description>Windowed Watchdog Timer Clock Select Register.</description> 568 <addressOffset>0x08</addressOffset> 569 <access>read-write</access> 570 <fields> 571 <field> 572 <name>SOURCE</name> 573 <description>WWDT Clock Selection Register.</description> 574 <bitOffset>0</bitOffset> 575 <bitWidth>3</bitWidth> 576 </field> 577 </fields> 578 </register> 579 <register> 580 <name>CNT</name> 581 <description>Windowed Watchdog Timer Count Register.</description> 582 <addressOffset>0x0C</addressOffset> 583 <access>read-only</access> 584 <fields> 585 <field> 586 <name>COUNT</name> 587 <description>Current Value of the Windowed Watchdog Timer Counter.</description> 588 <bitOffset>0</bitOffset> 589 <bitWidth>32</bitWidth> 590 </field> 591 </fields> 592 </register> 593 </registers> 594 </peripheral> 595<!-- WWDT:Watchdog Timer --> 596</device> 597
