WDT Windowed Watchdog Timer 0x40003000 0x00 0x0400 registers WWDT 1 CTRL Watchdog Timer Control Register. 0x00 read-write INT_LATE_VAL Windowed Watchdog Interrupt Upper Limit. Sets the number of WDTCLK cycles until a windowed watchdog timer interrupt is generated (if enabled) if the CPU does not write the windowed watchdog reset sequence to the WWDT_RST register before the watchdog timer has counted this time period since the last timer reset. 0 4 wdt2pow31 2**31 clock cycles. 0 wdt2pow30 2**30 clock cycles. 1 wdt2pow29 2**29 clock cycles. 2 wdt2pow28 2**28 clock cycles. 3 wdt2pow27 2^27 clock cycles. 4 wdt2pow26 2**26 clock cycles. 5 wdt2pow25 2**25 clock cycles. 6 wdt2pow24 2**24 clock cycles. 7 wdt2pow23 2**23 clock cycles. 8 wdt2pow22 2**22 clock cycles. 9 wdt2pow21 2**21 clock cycles. 10 wdt2pow20 2**20 clock cycles. 11 wdt2pow19 2**19 clock cycles. 12 wdt2pow18 2**18 clock cycles. 13 wdt2pow17 2**17 clock cycles. 14 wdt2pow16 2**16 clock cycles. 15 RST_LATE_VAL Windowed Watchdog Reset Upper Limit. Sets the number of WDTCLK cycles until a system reset occurs (if enabled) if the CPU does not write the watchdog reset sequence to the WDT_RST register before the watchdog timer has counted this time period since the last timer reset. 4 4 wdt2pow31 2**31 clock cycles. 0 wdt2pow30 2**30 clock cycles. 1 wdt2pow29 2**29 clock cycles. 2 wdt2pow28 2**28 clock cycles. 3 wdt2pow27 2^27 clock cycles. 4 wdt2pow26 2**26 clock cycles. 5 wdt2pow25 2**25 clock cycles. 6 wdt2pow24 2**24 clock cycles. 7 wdt2pow23 2**23 clock cycles. 8 wdt2pow22 2**22 clock cycles. 9 wdt2pow21 2**21 clock cycles. 10 wdt2pow20 2**20 clock cycles. 11 wdt2pow19 2**19 clock cycles. 12 wdt2pow18 2**18 clock cycles. 13 wdt2pow17 2**17 clock cycles. 14 wdt2pow16 2**16 clock cycles. 15 EN Windowed Watchdog Timer Enable. 8 1 dis Disable. 0 en Enable. 1 INT_LATE Windowed Watchdog Timer Interrupt Flag Too Late. 9 1 read-write inactive No interrupt is pending. 0 pending An interrupt is pending. 1 WDT_INT_EN Windowed Watchdog Timer Interrupt Enable. 10 1 dis Disable. 0 en Enable. 1 WDT_RST_EN Windowed Watchdog Timer Reset Enable. 11 1 dis Disable. 0 en Enable. 1 INT_EARLY Windowed Watchdog Timer Interrupt Flag Too Soon. 12 1 read-write inactive No interrupt is pending. 0 pending An interrupt is pending. 1 INT_EARLY_VAL Windowed Watchdog Interrupt Lower Limit. Sets the number of WDTCLK cycles that establishes the lower boundary of the watchdog window. A windowed watchdog timer interrupt is generated (if enabled) if the CPU writes the windowed watchdog reset sequence to the WWDT_RST register before the watchdog timer has counted this time period since the last timer reset. 16 4 wdt2pow31 2**31 clock cycles. 0 wdt2pow30 2**30 clock cycles. 1 wdt2pow29 2**29 clock cycles. 2 wdt2pow28 2**28 clock cycles. 3 wdt2pow27 2^27 clock cycles. 4 wdt2pow26 2**26 clock cycles. 5 wdt2pow25 2**25 clock cycles. 6 wdt2pow24 2**24 clock cycles. 7 wdt2pow23 2**23 clock cycles. 8 wdt2pow22 2**22 clock cycles. 9 wdt2pow21 2**21 clock cycles. 10 wdt2pow20 2**20 clock cycles. 11 wdt2pow19 2**19 clock cycles. 12 wdt2pow18 2**18 clock cycles. 13 wdt2pow17 2**17 clock cycles. 14 wdt2pow16 2**16 clock cycles. 15 RST_EARLY_VAL Windowed Watchdog Reset Lower Limit. Sets the number of WDTCLK cycles that establishes the lower boundary of the watchdog window. A system reset occurs (if enabled) if the CPU writes the windowed watchdog reset sequence to the WWDT_RST register before the watchdog timer has counted this time period since the last timer reset. 20 4 wdt2pow31 2**31 clock cycles. 0 wdt2pow30 2**30 clock cycles. 1 wdt2pow29 2**29 clock cycles. 2 wdt2pow28 2**28 clock cycles. 3 wdt2pow27 2^27 clock cycles. 4 wdt2pow26 2**26 clock cycles. 5 wdt2pow25 2**25 clock cycles. 6 wdt2pow24 2**24 clock cycles. 7 wdt2pow23 2**23 clock cycles. 8 wdt2pow22 2**22 clock cycles. 9 wdt2pow21 2**21 clock cycles. 10 wdt2pow20 2**20 clock cycles. 11 wdt2pow19 2**19 clock cycles. 12 wdt2pow18 2**18 clock cycles. 13 wdt2pow17 2**17 clock cycles. 14 wdt2pow16 2**16 clock cycles. 15 CLKRDY_IE Switch Ready Interrupt Enable. Fires an interrupt when it is safe to swithc the clock. 27 1 CLKRDY Clock Status. 28 1 WIN_EN Enables the Windowed Watchdog Function. 29 1 dis Windowed Mode Disabled (i.e. Compatibility Mode). 0 en Windowed Mode Enabled. 1 RST_EARLY Windowed Watchdog Timer Reset Flag Too Soon. 30 1 read-write noEvent The event has not occurred. 0 occurred The event has occurred. 1 RST_LATE Windowed Watchdog Timer Reset Flag Too Late. 31 1 read-write noEvent The event has not occurred. 0 occurred The event has occurred. 1 RST Windowed Watchdog Timer Reset Register. 0x04 write-only RESET Writing the watchdog counter 'reset sequence' to this register resets the watchdog counter. If the watchdog count exceeds INT_PERIOD_UPPER_LIMIT then a watchdog interrupt will occur, if enabled. If the watchdog count exceeds RST_PERIOD_UPPER_LIMIT then a watchdog reset will occur, if enabled. 0 8 seq0 The first value to be written to reset the WDT. 0x000000A5 seq1 The second value to be written to reset the WDT. 0x0000005A CLKSEL Windowed Watchdog Timer Clock Select Register. 0x08 read-write SOURCE WWDT Clock Selection Register. 0 3 CNT Windowed Watchdog Timer Count Register. 0x0C read-only COUNT Current Value of the Windowed Watchdog Timer Counter. 0 32