1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>UART0</name> 5 <description>UART</description> 6 <baseAddress>0x40020000</baseAddress> 7 <addressBlock> 8 <offset>0</offset> 9 <size>0x1000</size> 10 <usage>registers</usage> 11 </addressBlock> 12 <interrupt> 13 <name>UART0</name> 14 <description>UART0 IRQ</description> 15 <value>14</value> 16 </interrupt> 17 <registers> 18 <register> 19 <name>CTRL</name> 20 <description>Control Register.</description> 21 <addressOffset>0x00</addressOffset> 22 <size>32</size> 23 <fields> 24 <field> 25 <name>RXTHD</name> 26 <description>Receive Threshhold.</description> 27 <bitOffset>0</bitOffset> 28 <bitWidth>4</bitWidth> 29 </field> 30 <field> 31 <name>PARITY_EN</name> 32 <description>Enable/disable Parity bit (9th character).</description> 33 <bitOffset>4</bitOffset> 34 <bitWidth>1</bitWidth> 35 <enumeratedValues> 36 <enumeratedValue> 37 <name>dis</name> 38 <description>No Parity </description> 39 <value>0</value> 40 </enumeratedValue> 41 <enumeratedValue> 42 <name>en</name> 43 <description>Parity enabled as 9th bit</description> 44 <value>1</value> 45 </enumeratedValue> 46 </enumeratedValues> 47 </field> 48 <field> 49 <name>PARITY</name> 50 <description>When PARITY_EN=1, selects odd or even parity.</description> 51 <bitOffset>5</bitOffset> 52 <bitWidth>1</bitWidth> 53 <enumeratedValues> 54 <enumeratedValue> 55 <name>Even</name> 56 <description>Even parity selected.</description> 57 <value>0</value> 58 </enumeratedValue> 59 <enumeratedValue> 60 <name>ODD</name> 61 <description>Odd parity selected.</description> 62 <value>1</value> 63 </enumeratedValue> 64 </enumeratedValues> 65 </field> 66 <field> 67 <name>PARMD</name> 68 <description>Selects parity based on 1s or 0s count (when PARITY_EN=1).</description> 69 <bitOffset>6</bitOffset> 70 <bitWidth>1</bitWidth> 71 <enumeratedValues> 72 <enumeratedValue> 73 <name>1</name> 74 <description>Parity calculation is based on number of 1s in frame.</description> 75 <value>0</value> 76 </enumeratedValue> 77 <enumeratedValue> 78 <name>0</name> 79 <description>Parity calculation is based on number of 0s in frame.</description> 80 <value>1</value> 81 </enumeratedValue> 82 </enumeratedValues> 83 </field> 84 <field> 85 <name>TX_FLUSH</name> 86 <description>Flushes the TX FIFO buffer.</description> 87 <bitOffset>8</bitOffset> 88 <bitWidth>1</bitWidth> 89 </field> 90 <field> 91 <name>RX_FLUSH</name> 92 <description>Flushes the RX FIFO buffer.</description> 93 <bitOffset>9</bitOffset> 94 <bitWidth>1</bitWidth> 95 </field> 96 <field> 97 <name>CHAR_SIZE</name> 98 <description>Selects UART character size.</description> 99 <bitOffset>10</bitOffset> 100 <bitWidth>2</bitWidth> 101 <enumeratedValues> 102 <enumeratedValue> 103 <name>5</name> 104 <description>5 bits.</description> 105 <value>0</value> 106 </enumeratedValue> 107 <enumeratedValue> 108 <name>6</name> 109 <description>6 bits.</description> 110 <value>1</value> 111 </enumeratedValue> 112 <enumeratedValue> 113 <name>7</name> 114 <description>7 bits.</description> 115 <value>2</value> 116 </enumeratedValue> 117 <enumeratedValue> 118 <name>8</name> 119 <description>8 bits.</description> 120 <value>3</value> 121 </enumeratedValue> 122 </enumeratedValues> 123 </field> 124 <field> 125 <name>STOPBITS</name> 126 <description>Selects the number of stop bits that will be generated.</description> 127 <bitOffset>12</bitOffset> 128 <bitWidth>1</bitWidth> 129 <enumeratedValues> 130 <enumeratedValue> 131 <name>1</name> 132 <description>1 stop bit.</description> 133 <value>0</value> 134 </enumeratedValue> 135 <enumeratedValue> 136 <name>1_5</name> 137 <description>1.5 stop bits.</description> 138 <value>1</value> 139 </enumeratedValue> 140 </enumeratedValues> 141 </field> 142 <field> 143 <name>FLOW_CTRL</name> 144 <description>Enables/disables hardware flow control.</description> 145 <bitOffset>13</bitOffset> 146 <bitWidth>1</bitWidth> 147 <enumeratedValues> 148 <enumeratedValue> 149 <name>en</name> 150 <description>HW Flow Control with RTS/CTS enabled</description> 151 <value>1</value> 152 </enumeratedValue> 153 <enumeratedValue> 154 <name>dis</name> 155 <description>HW Flow Control disabled</description> 156 <value>0</value> 157 </enumeratedValue> 158 </enumeratedValues> 159 </field> 160 </fields> 161 </register> 162 <register> 163 <name>STATUS</name> 164 <description>Status Register.</description> 165 <addressOffset>0x04</addressOffset> 166 <size>32</size> 167 <access>read-only</access> 168 <fields> 169 <field> 170 <name>TX_BUSY</name> 171 <description>Read-only flag indicating the UART transmit status.</description> 172 <bitOffset>0</bitOffset> 173 <bitWidth>1</bitWidth> 174 <access>read-only</access> 175 </field> 176 <field> 177 <name>RX_BUSY</name> 178 <description>Read-only flag indicating the UART receiver status.</description> 179 <bitOffset>1</bitOffset> 180 <bitWidth>1</bitWidth> 181 <access>read-only</access> 182 </field> 183 <field> 184 <name>RX_EMPTY</name> 185 <description>Read-only flag indicating the RX FIFO state.</description> 186 <bitOffset>4</bitOffset> 187 <bitWidth>1</bitWidth> 188 <access>read-only</access> 189 </field> 190 <field> 191 <name>RX_FULL</name> 192 <description>Read-only flag indicating the RX FIFO state.</description> 193 <bitOffset>5</bitOffset> 194 <bitWidth>1</bitWidth> 195 <access>read-only</access> 196 </field> 197 <field> 198 <name>TX_EMPTY</name> 199 <description>Read-only flag indicating the TX FIFO state.</description> 200 <bitOffset>6</bitOffset> 201 <bitWidth>1</bitWidth> 202 <access>read-only</access> 203 </field> 204 <field> 205 <name>TX_FULL</name> 206 <description>Read-only flag indicating the TX FIFO state.</description> 207 <bitOffset>7</bitOffset> 208 <bitWidth>1</bitWidth> 209 <access>read-only</access> 210 </field> 211 <field> 212 <name>RX_FIFO_CNT</name> 213 <description>Indicates the number of bytes currently in the RX FIFO.</description> 214 <bitOffset>8</bitOffset> 215 <bitWidth>4</bitWidth> 216 <access>read-only</access> 217 </field> 218 <field> 219 <name>TX_FIFO_CNT</name> 220 <description>Indicates the number of bytes currently in the TX FIFO.</description> 221 <bitOffset>12</bitOffset> 222 <bitWidth>4</bitWidth> 223 <access>read-only</access> 224 </field> 225 </fields> 226 </register> 227 <register> 228 <name>INT_EN</name> 229 <description>Interrupt Enable Register.</description> 230 <addressOffset>0x08</addressOffset> 231 <size>32</size> 232 <fields> 233 <field> 234 <name>RX_FRAME_ERROR</name> 235 <description>Enable for RX Frame Error Interrupt.</description> 236 <bitOffset>0</bitOffset> 237 <bitWidth>1</bitWidth> 238 </field> 239 <field> 240 <name>RX_PARITY_ERROR</name> 241 <description>Enable for RX Parity Error interrupt.</description> 242 <bitOffset>1</bitOffset> 243 <bitWidth>1</bitWidth> 244 </field> 245 <field> 246 <name>RX_OVERRUN</name> 247 <description>Enable for RX FIFO OVerrun interrupt.</description> 248 <bitOffset>3</bitOffset> 249 <bitWidth>1</bitWidth> 250 </field> 251 <field> 252 <name>RX_FIFO_THRESH</name> 253 <description>Enable for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field.</description> 254 <bitOffset>4</bitOffset> 255 <bitWidth>1</bitWidth> 256 </field> 257 <field> 258 <name>TX_FIFO_ALMOST_EMPTY</name> 259 <description>Enable for interrupt when TX FIFO has only one byte remaining.</description> 260 <bitOffset>5</bitOffset> 261 <bitWidth>1</bitWidth> 262 </field> 263 <field> 264 <name>TX_FIFO_HALF_EMPTY</name> 265 <description>Enable for interrupt when TX FIFO reaches half the number of bytes allowed in the fifo or less.</description> 266 <bitOffset>6</bitOffset> 267 <bitWidth>1</bitWidth> 268 </field> 269 </fields> 270 </register> 271 <register> 272 <name>INT_FL</name> 273 <description>Interrupt Status Flags.</description> 274 <addressOffset>0x0C</addressOffset> 275 <size>32</size> 276 <modifiedWriteValues>oneToClear</modifiedWriteValues> 277 <fields> 278 <field> 279 <name>RX_FRAME_ERROR</name> 280 <description>FLAG for RX Frame Error Interrupt.</description> 281 <bitOffset>0</bitOffset> 282 <bitWidth>1</bitWidth> 283 </field> 284 <field> 285 <name>RX_PARITY_ERROR</name> 286 <description>FLAG for RX Parity Error interrupt.</description> 287 <bitOffset>1</bitOffset> 288 <bitWidth>1</bitWidth> 289 </field> 290 <field> 291 <name>RX_OVERRUN</name> 292 <description>FLAG for RX FIFO Overrun interrupt.</description> 293 <bitOffset>3</bitOffset> 294 <bitWidth>1</bitWidth> 295 </field> 296 <field> 297 <name>RX_FIFO_THRESH</name> 298 <description>FLAG for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field.</description> 299 <bitOffset>4</bitOffset> 300 <bitWidth>1</bitWidth> 301 </field> 302 <field> 303 <name>TX_FIFO_ALMOST_EMPTY</name> 304 <description>FLAG for interrupt when TX FIFO has only one byte remaining.</description> 305 <bitOffset>5</bitOffset> 306 <bitWidth>1</bitWidth> 307 </field> 308 <field> 309 <name>TX_FIFO_HALF_EMPTY</name> 310 <description>FLAG for interrupt when TX FIFO reaches half the number of bytes allowed in the fifo or less.</description> 311 <bitOffset>6</bitOffset> 312 <bitWidth>1</bitWidth> 313 </field> 314 </fields> 315 </register> 316 <register> 317 <name>BAUD0</name> 318 <description>Baud rate register. Integer portion.</description> 319 <addressOffset>0x10</addressOffset> 320 <size>32</size> 321 <fields> 322 <field> 323 <name>IBAUD</name> 324 <description>Integer portion of baud rate divisor value. IBAUD = InputClock / (factor * Baud Rate Frequency).</description> 325 <bitOffset>0</bitOffset> 326 <bitWidth>12</bitWidth> 327 </field> 328 </fields> 329 </register> 330 <register> 331 <name>BAUD1</name> 332 <description>Baud rate register. Decimal Setting.</description> 333 <addressOffset>0x14</addressOffset> 334 <size>32</size> 335 <fields> 336 <field> 337 <name>DBAUD</name> 338 <description>Decimal portion of baud rate divisor value. DIV = InputClock/(factor*Baud Rate Frequency). DDIV=(DIV-IDIV)*128.</description> 339 <bitOffset>0</bitOffset> 340 <bitWidth>7</bitWidth> 341 </field> 342 </fields> 343 </register> 344 <register> 345 <name>PIN</name> 346 <description>UART Pin Control Register.</description> 347 <addressOffset>0x1C</addressOffset> 348 <size>32</size> 349 <fields> 350 <field> 351 <name>CTS</name> 352 <description>Current state of CTS pin.</description> 353 <bitOffset>0</bitOffset> 354 <bitWidth>1</bitWidth> 355 </field> 356 <field> 357 <name>RTS</name> 358 <description>If hardware flow control is disabled, this bit may be used to control RTS output.</description> 359 <bitOffset>1</bitOffset> 360 <bitWidth>1</bitWidth> 361 </field> 362 </fields> 363 </register> 364 <register> 365 <name>FIFO</name> 366 <description>FIFO Data buffer.</description> 367 <addressOffset>0x20</addressOffset> 368 <size>32</size> 369 <fields> 370 <field> 371 <name>FIFO</name> 372 <description>Load/unload location for TX and RX FIFO buffers.</description> 373 <bitOffset>0</bitOffset> 374 <bitWidth>8</bitWidth> 375 </field> 376 <field> 377 <name>PARITY</name> 378 <description>Parity error flag for next byte to be read from FIFO.</description> 379 <bitOffset>8</bitOffset> 380 <bitWidth>1</bitWidth> 381 </field> 382 </fields> 383 </register> 384 <register> 385 <name>DMA</name> 386 <description>DMA Configuration.</description> 387 <addressOffset>0x30</addressOffset> 388 <size>32</size> 389 <fields> 390 <field> 391 <name>TXDMA_LEVEL</name> 392 <description>TX threshold for DMA transmission.</description> 393 <bitOffset>0</bitOffset> 394 <bitWidth>4</bitWidth> 395 </field> 396 <field> 397 <name>TXDMA_EN</name> 398 <description>TX DMA channel enable.</description> 399 <bitOffset>4</bitOffset> 400 <bitWidth>1</bitWidth> 401 <enumeratedValues> 402 <enumeratedValue> 403 <name>dis</name> 404 <description>DMA is disabled </description> 405 <value>0</value> 406 </enumeratedValue> 407 <enumeratedValue> 408 <name>en</name> 409 <description>DMA is enabled </description> 410 <value>1</value> 411 </enumeratedValue> 412 </enumeratedValues> 413 </field> 414 <field> 415 <name>RXDMA_LEVEL</name> 416 <description>RX threshold for DMA transmission.</description> 417 <bitOffset>5</bitOffset> 418 <bitWidth>4</bitWidth> 419 </field> 420 <field> 421 <name>RXDMA_EN</name> 422 <description>RX DMA channel enable.</description> 423 <bitOffset>9</bitOffset> 424 <bitWidth>1</bitWidth> 425 <enumeratedValues> 426 <enumeratedValue> 427 <name>dis</name> 428 <description>DMA is disabled </description> 429 <value>0</value> 430 </enumeratedValue> 431 <enumeratedValue> 432 <name>en</name> 433 <description>DMA is enabled </description> 434 <value>1</value> 435 </enumeratedValue> 436 </enumeratedValues> 437 </field> 438 </fields> 439 </register> 440 </registers> 441 </peripheral> 442 <!-- UART: UART --> 443</device> 444
