UART0 UART 0x40020000 0 0x1000 registers UART0 UART0 IRQ 14 CTRL Control Register. 0x00 32 RXTHD Receive Threshhold. 0 4 PARITY_EN Enable/disable Parity bit (9th character). 4 1 dis No Parity 0 en Parity enabled as 9th bit 1 PARITY When PARITY_EN=1, selects odd or even parity. 5 1 Even Even parity selected. 0 ODD Odd parity selected. 1 PARMD Selects parity based on 1s or 0s count (when PARITY_EN=1). 6 1 1 Parity calculation is based on number of 1s in frame. 0 0 Parity calculation is based on number of 0s in frame. 1 TX_FLUSH Flushes the TX FIFO buffer. 8 1 RX_FLUSH Flushes the RX FIFO buffer. 9 1 CHAR_SIZE Selects UART character size. 10 2 5 5 bits. 0 6 6 bits. 1 7 7 bits. 2 8 8 bits. 3 STOPBITS Selects the number of stop bits that will be generated. 12 1 1 1 stop bit. 0 1_5 1.5 stop bits. 1 FLOW_CTRL Enables/disables hardware flow control. 13 1 en HW Flow Control with RTS/CTS enabled 1 dis HW Flow Control disabled 0 STATUS Status Register. 0x04 32 read-only TX_BUSY Read-only flag indicating the UART transmit status. 0 1 read-only RX_BUSY Read-only flag indicating the UART receiver status. 1 1 read-only RX_EMPTY Read-only flag indicating the RX FIFO state. 4 1 read-only RX_FULL Read-only flag indicating the RX FIFO state. 5 1 read-only TX_EMPTY Read-only flag indicating the TX FIFO state. 6 1 read-only TX_FULL Read-only flag indicating the TX FIFO state. 7 1 read-only RX_FIFO_CNT Indicates the number of bytes currently in the RX FIFO. 8 4 read-only TX_FIFO_CNT Indicates the number of bytes currently in the TX FIFO. 12 4 read-only INT_EN Interrupt Enable Register. 0x08 32 RX_FRAME_ERROR Enable for RX Frame Error Interrupt. 0 1 RX_PARITY_ERROR Enable for RX Parity Error interrupt. 1 1 RX_OVERRUN Enable for RX FIFO OVerrun interrupt. 3 1 RX_FIFO_THRESH Enable for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field. 4 1 TX_FIFO_ALMOST_EMPTY Enable for interrupt when TX FIFO has only one byte remaining. 5 1 TX_FIFO_HALF_EMPTY Enable for interrupt when TX FIFO reaches half the number of bytes allowed in the fifo or less. 6 1 INT_FL Interrupt Status Flags. 0x0C 32 oneToClear RX_FRAME_ERROR FLAG for RX Frame Error Interrupt. 0 1 RX_PARITY_ERROR FLAG for RX Parity Error interrupt. 1 1 RX_OVERRUN FLAG for RX FIFO Overrun interrupt. 3 1 RX_FIFO_THRESH FLAG for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field. 4 1 TX_FIFO_ALMOST_EMPTY FLAG for interrupt when TX FIFO has only one byte remaining. 5 1 TX_FIFO_HALF_EMPTY FLAG for interrupt when TX FIFO reaches half the number of bytes allowed in the fifo or less. 6 1 BAUD0 Baud rate register. Integer portion. 0x10 32 IBAUD Integer portion of baud rate divisor value. IBAUD = InputClock / (factor * Baud Rate Frequency). 0 12 BAUD1 Baud rate register. Decimal Setting. 0x14 32 DBAUD Decimal portion of baud rate divisor value. DIV = InputClock/(factor*Baud Rate Frequency). DDIV=(DIV-IDIV)*128. 0 7 PIN UART Pin Control Register. 0x1C 32 CTS Current state of CTS pin. 0 1 RTS If hardware flow control is disabled, this bit may be used to control RTS output. 1 1 FIFO FIFO Data buffer. 0x20 32 FIFO Load/unload location for TX and RX FIFO buffers. 0 8 PARITY Parity error flag for next byte to be read from FIFO. 8 1 DMA DMA Configuration. 0x30 32 TXDMA_LEVEL TX threshold for DMA transmission. 0 4 TXDMA_EN TX DMA channel enable. 4 1 dis DMA is disabled 0 en DMA is enabled 1 RXDMA_LEVEL RX threshold for DMA transmission. 5 4 RXDMA_EN RX DMA channel enable. 9 1 dis DMA is disabled 0 en DMA is enabled 1