1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>TMR0</name> 5 <description>32-bit reloadable timer that can be used for timing and event counting.</description> 6 <groupName>Timers</groupName> 7 <baseAddress>0x40010000</baseAddress> 8 <addressBlock> 9 <offset>0x00</offset> 10 <size>0x1000</size> 11 <usage>registers</usage> 12 </addressBlock> 13 <interrupt> 14 <name>TMR0</name> 15 <description>TMR0 IRQ</description> 16 <value>5</value> 17 </interrupt> 18 <registers> 19 <register> 20 <name>CNT</name> 21 <description>Count. This register stores the current timer count.</description> 22 <addressOffset>0x00</addressOffset> 23 <resetValue>0x00000001</resetValue> 24 <fields> 25 <field> 26 <name>COUNT</name> 27 <description>Current count on the timer.</description> 28 <bitOffset>0</bitOffset> 29 <bitWidth>32</bitWidth> 30 </field> 31 </fields> 32 </register> 33 <register> 34 <name>CMP</name> 35 <description>Compare. This register stores the compare value, which is used to set the maximum count value to initiate a reload of the timer to 0x0001.</description> 36 <addressOffset>0x04</addressOffset> 37 <resetValue>0x0000FFFF</resetValue> 38 <fields> 39 <field> 40 <name>COMPARE</name> 41 <description>Timer compare value.</description> 42 <bitOffset>0</bitOffset> 43 <bitWidth>32</bitWidth> 44 </field> 45 </fields> 46 </register> 47 <register> 48 <name>PWM</name> 49 <description>PWM. This register stores the value that is compared to the current timer count.</description> 50 <addressOffset>0x08</addressOffset> 51 <fields> 52 <field> 53 <name>PWM</name> 54 <description>Timer PWM match value.</description> 55 <bitOffset>0</bitOffset> 56 <bitWidth>32</bitWidth> 57 </field> 58 </fields> 59 </register> 60 <register> 61 <name>INTR</name> 62 <description>Clear Interrupt. Writing a value (0 or 1) to a bit in this register clears the associated interrupt.</description> 63 <addressOffset>0x0C</addressOffset> 64 <modifiedWriteValues>oneToClear</modifiedWriteValues> 65 <fields> 66 <field> 67 <name>IRQ</name> 68 <description>Clear Interrupt.</description> 69 <bitOffset>0</bitOffset> 70 <bitWidth>1</bitWidth> 71 </field> 72 </fields> 73 </register> 74 <register> 75 <name>CN</name> 76 <description>Timer Control Register.</description> 77 <addressOffset>0x10</addressOffset> 78 <fields> 79 <field> 80 <name>TMODE</name> 81 <description>Timer Mode.</description> 82 <bitOffset>0</bitOffset> 83 <bitWidth>3</bitWidth> 84 <enumeratedValues> 85 <enumeratedValue> 86 <name>oneshot</name> 87 <description>One Shot Mode.</description> 88 <value>0</value> 89 </enumeratedValue> 90 <enumeratedValue> 91 <name>continuous</name> 92 <description>Continuous Mode.</description> 93 <value>1</value> 94 </enumeratedValue> 95 <enumeratedValue> 96 <name>counter</name> 97 <description>Counter Mode.</description> 98 <value>2</value> 99 </enumeratedValue> 100 <enumeratedValue> 101 <name>pwm</name> 102 <description>PWM Mode.</description> 103 <value>3</value> 104 </enumeratedValue> 105 <enumeratedValue> 106 <name>capture</name> 107 <description>Capture Mode.</description> 108 <value>4</value> 109 </enumeratedValue> 110 <enumeratedValue> 111 <name>compare</name> 112 <description>Compare Mode.</description> 113 <value>5</value> 114 </enumeratedValue> 115 <enumeratedValue> 116 <name>gated</name> 117 <description>Gated Mode.</description> 118 <value>6</value> 119 </enumeratedValue> 120 <enumeratedValue> 121 <name>capturecompare</name> 122 <description>Capture/Compare Mode.</description> 123 <value>7</value> 124 </enumeratedValue> 125 </enumeratedValues> 126 </field> 127 <field> 128 <name>PRES</name> 129 <description>Prescaler. Set the Timer's prescaler value. The prescaler divides the PCLK input to the timer and sets the Timer's Count Clock, F_CNT_CLK = PCLK (HZ) /prescaler. The Timer's prescaler setting is a 4-bit value with pres3:pres[2:0].</description> 130 <bitOffset>3</bitOffset> 131 <bitWidth>3</bitWidth> 132 <enumeratedValues> 133 <enumeratedValue> 134 <name>div1</name> 135 <description>Divide by 1.</description> 136 <value>0</value> 137 </enumeratedValue> 138 <enumeratedValue> 139 <name>div2</name> 140 <description>Divide by 2.</description> 141 <value>1</value> 142 </enumeratedValue> 143 <enumeratedValue> 144 <name>div4</name> 145 <description>Divide by 4.</description> 146 <value>2</value> 147 </enumeratedValue> 148 <enumeratedValue> 149 <name>div8</name> 150 <description>Divide by 8.</description> 151 <value>3</value> 152 </enumeratedValue> 153 <enumeratedValue> 154 <name>div16</name> 155 <description>Divide by 16.</description> 156 <value>4</value> 157 </enumeratedValue> 158 <enumeratedValue> 159 <name>div32</name> 160 <description>Divide by 32.</description> 161 <value>5</value> 162 </enumeratedValue> 163 <enumeratedValue> 164 <name>div64</name> 165 <description>Divide by 64.</description> 166 <value>6</value> 167 </enumeratedValue> 168 <enumeratedValue> 169 <name>div128</name> 170 <description>Divide by 128.</description> 171 <value>7</value> 172 </enumeratedValue> 173 <enumeratedValue> 174 <name>div256</name> 175 <description>Divide by 256. Additionally, TMRn->cn.pres3 must be set.</description> 176 <value>0</value> 177 </enumeratedValue> 178 <enumeratedValue> 179 <name>div512</name> 180 <description>Divide by 512. Additionally, TMRn->cn.pres3 must be set.</description> 181 <value>2</value> 182 </enumeratedValue> 183 <enumeratedValue> 184 <name>div1024</name> 185 <description>Divide by 1024. Additionally, TMRn->cn.pres3 must be set.</description> 186 <value>3</value> 187 </enumeratedValue> 188 <enumeratedValue> 189 <name>div2048</name> 190 <description>Divide by 2048. Additionally, TMRn->cn.pres3 must be set.</description> 191 <value>4</value> 192 </enumeratedValue> 193 <enumeratedValue> 194 <name>div4096</name> 195 <description>Divide by 4096. Additionally, TMRn->cn.pres3 must be set.</description> 196 <value>5</value> 197 </enumeratedValue> 198 </enumeratedValues> 199 </field> 200 <field> 201 <name>TPOL</name> 202 <description>Timer input/output polarity bit.</description> 203 <bitOffset>6</bitOffset> 204 <bitWidth>1</bitWidth> 205 <enumeratedValues> 206 <enumeratedValue> 207 <name>activeHi</name> 208 <description>Active High.</description> 209 <value>0</value> 210 </enumeratedValue> 211 <enumeratedValue> 212 <name>activeLo</name> 213 <description>Active Low.</description> 214 <value>1</value> 215 </enumeratedValue> 216 </enumeratedValues> 217 </field> 218 <field> 219 <name>TEN</name> 220 <description>Timer Enable.</description> 221 <bitOffset>7</bitOffset> 222 <bitWidth>1</bitWidth> 223 <enumeratedValues> 224 <enumeratedValue> 225 <name>dis</name> 226 <description>Disable.</description> 227 <value>0</value> 228 </enumeratedValue> 229 <enumeratedValue> 230 <name>en</name> 231 <description>Enable.</description> 232 <value>1</value> 233 </enumeratedValue> 234 </enumeratedValues> 235 </field> 236 <field> 237 <name>PRES3</name> 238 <description>MSB of prescaler value.</description> 239 <bitOffset>8</bitOffset> 240 <bitWidth>1</bitWidth> 241 <enumeratedValues> 242 <enumeratedValue> 243 <name>div1</name> 244 <description>Divide by 1.</description> 245 <value>0</value> 246 </enumeratedValue> 247 <enumeratedValue> 248 <name>div2</name> 249 <description>Divide by 2.</description> 250 <value>0</value> 251 </enumeratedValue> 252 <enumeratedValue> 253 <name>div4</name> 254 <description>Divide by 4.</description> 255 <value>0</value> 256 </enumeratedValue> 257 <enumeratedValue> 258 <name>div8</name> 259 <description>Divide by 8.</description> 260 <value>0</value> 261 </enumeratedValue> 262 <enumeratedValue> 263 <name>div16</name> 264 <description>Divide by 16.</description> 265 <value>0</value> 266 </enumeratedValue> 267 <enumeratedValue> 268 <name>div32</name> 269 <description>Divide by 32.</description> 270 <value>0</value> 271 </enumeratedValue> 272 <enumeratedValue> 273 <name>div64</name> 274 <description>Divide by 64.</description> 275 <value>0</value> 276 </enumeratedValue> 277 <enumeratedValue> 278 <name>div128</name> 279 <description>Divide by 128.</description> 280 <value>0</value> 281 </enumeratedValue> 282 <enumeratedValue> 283 <name>div256</name> 284 <description>Divide by 256. Additionally, TMRn->cn.pres3 must be set.</description> 285 <value>1</value> 286 </enumeratedValue> 287 <enumeratedValue> 288 <name>div512</name> 289 <description>Divide by 512. Additionally, TMRn->cn.pres3 must be set.</description> 290 <value>1</value> 291 </enumeratedValue> 292 <enumeratedValue> 293 <name>div1024</name> 294 <description>Divide by 1024. Additionally, TMRn->cn.pres3 must be set.</description> 295 <value>1</value> 296 </enumeratedValue> 297 <enumeratedValue> 298 <name>div2048</name> 299 <description>Divide by 2048. Additionally, TMRn->cn.pres3 must be set.</description> 300 <value>1</value> 301 </enumeratedValue> 302 <enumeratedValue> 303 <name>div4096</name> 304 <description>Divide by 4096. Additionally, TMRn->cn.pres3 must be set.</description> 305 <value>1</value> 306 </enumeratedValue> 307 </enumeratedValues> 308 </field> 309 <field> 310 <name>PWMSYNC</name> 311 <description>Timer PWM Synchronization Mode Enable.</description> 312 <bitOffset>9</bitOffset> 313 <bitWidth>1</bitWidth> 314 <enumeratedValues> 315 <enumeratedValue> 316 <name>dis</name> 317 <description>Disable.</description> 318 <value>0</value> 319 </enumeratedValue> 320 <enumeratedValue> 321 <name>en</name> 322 <description>Enable.</description> 323 <value>1</value> 324 </enumeratedValue> 325 </enumeratedValues> 326 </field> 327 <field> 328 <name>NOLHPOL</name> 329 <description>Timer PWM output 0A polarity bit.</description> 330 <bitOffset>10</bitOffset> 331 <bitWidth>1</bitWidth> 332 <enumeratedValues> 333 <enumeratedValue> 334 <name>normal</name> 335 <description>Normal output polarity.</description> 336 <value>0</value> 337 </enumeratedValue> 338 <enumeratedValue> 339 <name>invert</name> 340 <description>Inverted output polarity.</description> 341 <value>1</value> 342 </enumeratedValue> 343 </enumeratedValues> 344 </field> 345 <field> 346 <name>NOLLPOL</name> 347 <description>Timer PWM output 0A' polarity bit.</description> 348 <bitOffset>11</bitOffset> 349 <bitWidth>1</bitWidth> 350 <enumeratedValues> 351 <enumeratedValue> 352 <name>normal</name> 353 <description>Normal output polarity.</description> 354 <value>0</value> 355 </enumeratedValue> 356 <enumeratedValue> 357 <name>invert</name> 358 <description>Inverted output polarity.</description> 359 <value>1</value> 360 </enumeratedValue> 361 </enumeratedValues> 362 </field> 363 <field> 364 <name>PWMCKBD</name> 365 <description>Timer PWM output 0A Mode Disable.</description> 366 <bitOffset>12</bitOffset> 367 <bitWidth>1</bitWidth> 368 <enumeratedValues> 369 <enumeratedValue> 370 <name>dis</name> 371 <description>Disable.</description> 372 <value>1</value> 373 </enumeratedValue> 374 <enumeratedValue> 375 <name>en</name> 376 <description>Enable.</description> 377 <value>0</value> 378 </enumeratedValue> 379 </enumeratedValues> 380 </field> 381 </fields> 382 </register> 383 <register> 384 <name>NOLCMP</name> 385 <description>Timer Non-Overlapping Compare Register.</description> 386 <addressOffset>0x14</addressOffset> 387 <fields> 388 <field> 389 <name>NOLLCMP</name> 390 <description>Non-overlapping Low Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A and next rising edge of PWM output 0A'.</description> 391 <bitOffset>0</bitOffset> 392 <bitWidth>8</bitWidth> 393 </field> 394 <field> 395 <name>NOLHCMP</name> 396 <description>Non-overlapping High Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A' and next rising edge of PWM output 0A.</description> 397 <bitOffset>8</bitOffset> 398 <bitWidth>8</bitWidth> 399 </field> 400 </fields> 401 </register> 402 </registers> 403 </peripheral> 404<!-- TMR0: 32-bit reloadable timer Port 0 --> 405</device> 406
