TMR0 32-bit reloadable timer that can be used for timing and event counting. Timers 0x40010000 0x00 0x1000 registers TMR0 TMR0 IRQ 5 CNT Count. This register stores the current timer count. 0x00 0x00000001 COUNT Current count on the timer. 0 32 CMP Compare. This register stores the compare value, which is used to set the maximum count value to initiate a reload of the timer to 0x0001. 0x04 0x0000FFFF COMPARE Timer compare value. 0 32 PWM PWM. This register stores the value that is compared to the current timer count. 0x08 PWM Timer PWM match value. 0 32 INTR Clear Interrupt. Writing a value (0 or 1) to a bit in this register clears the associated interrupt. 0x0C oneToClear IRQ Clear Interrupt. 0 1 CN Timer Control Register. 0x10 TMODE Timer Mode. 0 3 oneshot One Shot Mode. 0 continuous Continuous Mode. 1 counter Counter Mode. 2 pwm PWM Mode. 3 capture Capture Mode. 4 compare Compare Mode. 5 gated Gated Mode. 6 capturecompare Capture/Compare Mode. 7 PRES Prescaler. Set the Timer's prescaler value. The prescaler divides the PCLK input to the timer and sets the Timer's Count Clock, F_CNT_CLK = PCLK (HZ) /prescaler. The Timer's prescaler setting is a 4-bit value with pres3:pres[2:0]. 3 3 div1 Divide by 1. 0 div2 Divide by 2. 1 div4 Divide by 4. 2 div8 Divide by 8. 3 div16 Divide by 16. 4 div32 Divide by 32. 5 div64 Divide by 64. 6 div128 Divide by 128. 7 div256 Divide by 256. Additionally, TMRn->cn.pres3 must be set. 0 div512 Divide by 512. Additionally, TMRn->cn.pres3 must be set. 2 div1024 Divide by 1024. Additionally, TMRn->cn.pres3 must be set. 3 div2048 Divide by 2048. Additionally, TMRn->cn.pres3 must be set. 4 div4096 Divide by 4096. Additionally, TMRn->cn.pres3 must be set. 5 TPOL Timer input/output polarity bit. 6 1 activeHi Active High. 0 activeLo Active Low. 1 TEN Timer Enable. 7 1 dis Disable. 0 en Enable. 1 PRES3 MSB of prescaler value. 8 1 div1 Divide by 1. 0 div2 Divide by 2. 0 div4 Divide by 4. 0 div8 Divide by 8. 0 div16 Divide by 16. 0 div32 Divide by 32. 0 div64 Divide by 64. 0 div128 Divide by 128. 0 div256 Divide by 256. Additionally, TMRn->cn.pres3 must be set. 1 div512 Divide by 512. Additionally, TMRn->cn.pres3 must be set. 1 div1024 Divide by 1024. Additionally, TMRn->cn.pres3 must be set. 1 div2048 Divide by 2048. Additionally, TMRn->cn.pres3 must be set. 1 div4096 Divide by 4096. Additionally, TMRn->cn.pres3 must be set. 1 PWMSYNC Timer PWM Synchronization Mode Enable. 9 1 dis Disable. 0 en Enable. 1 NOLHPOL Timer PWM output 0A polarity bit. 10 1 normal Normal output polarity. 0 invert Inverted output polarity. 1 NOLLPOL Timer PWM output 0A' polarity bit. 11 1 normal Normal output polarity. 0 invert Inverted output polarity. 1 PWMCKBD Timer PWM output 0A Mode Disable. 12 1 dis Disable. 1 en Enable. 0 NOLCMP Timer Non-Overlapping Compare Register. 0x14 NOLLCMP Non-overlapping Low Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A and next rising edge of PWM output 0A'. 0 8 NOLHCMP Non-overlapping High Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A' and next rising edge of PWM output 0A. 8 8