1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.1" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>SPIXR</name> 5 <description>SPIXR peripheral.</description> 6 <baseAddress>0x4003A000</baseAddress> 7 <addressBlock> 8 <offset>0x00</offset> 9 <size>0x1000</size> 10 <usage>registers</usage> 11 </addressBlock> 12 <registers> 13 <register> 14 <name>DATA32</name> 15 <description>Register for reading and writing the FIFO.</description> 16 <addressOffset>0x00</addressOffset> 17 <size>32</size> 18 <access>read-write</access> 19 <fields> 20 <field> 21 <name>DATA</name> 22 <description>Read to pull from RX FIFO, write to put into TX FIFO.</description> 23 <bitOffset>0</bitOffset> 24 <bitWidth>32</bitWidth> 25 </field> 26 </fields> 27 </register> 28 <register> 29 <dim>2</dim> 30 <dimIncrement>2</dimIncrement> 31 <name>DATA16[%s]</name> 32 <description>Register for reading and writing the FIFO.</description> 33 <alternateRegister>DATA32</alternateRegister> 34 <addressOffset>0x00</addressOffset> 35 <size>16</size> 36 <access>read-write</access> 37 <fields> 38 <field> 39 <name>DATA</name> 40 <description>Read to pull from RX FIFO, write to put into TX FIFO.</description> 41 <bitOffset>0</bitOffset> 42 <bitWidth>16</bitWidth> 43 </field> 44 </fields> 45 </register> 46 <register> 47 <dim>4</dim> 48 <dimIncrement>1</dimIncrement> 49 <name>DATA8[%s]</name> 50 <description>Register for reading and writing the FIFO.</description> 51 <alternateRegister>DATA32</alternateRegister> 52 <addressOffset>0x00</addressOffset> 53 <size>8</size> 54 <access>read-write</access> 55 <fields> 56 <field> 57 <name>DATA</name> 58 <description>Read to pull from RX FIFO, write to put into TX FIFO.</description> 59 <bitOffset>0</bitOffset> 60 <bitWidth>8</bitWidth> 61 </field> 62 </fields> 63 </register> 64 <register> 65 <name>ctrl1</name> 66 <description>Register for controlling SPI peripheral.</description> 67 <addressOffset>0x04</addressOffset> 68 <access>read-write</access> 69 <fields> 70 <field> 71 <name>ENABLE</name> 72 <description>SPI Enable.</description> 73 <bitOffset>0</bitOffset> 74 <bitWidth>1</bitWidth> 75 <enumeratedValues> 76 <enumeratedValue> 77 <name>dis</name> 78 <description>SPI is disabled.</description> 79 <value>0</value> 80 </enumeratedValue> 81 <enumeratedValue> 82 <name>en</name> 83 <description>SPI is enabled.</description> 84 <value>1</value> 85 </enumeratedValue> 86 </enumeratedValues> 87 </field> 88 <field> 89 <name>MASTER</name> 90 <description>Master Mode Enable.</description> 91 <bitOffset>1</bitOffset> 92 <bitWidth>1</bitWidth> 93 <enumeratedValues> 94 <enumeratedValue> 95 <name>dis</name> 96 <description>SPI is Slave mode.</description> 97 <value>0</value> 98 </enumeratedValue> 99 <enumeratedValue> 100 <name>en</name> 101 <description>SPI is Master mode.</description> 102 <value>1</value> 103 </enumeratedValue> 104 </enumeratedValues> 105 </field> 106 <field> 107 <name>SS_IO</name> 108 <description>Slave Select 0, IO direction, to support Multi-Master mode, Slave Select 0 can be input in Master mode. This bit has no effect in slave mode.</description> 109 <bitOffset>4</bitOffset> 110 <bitWidth>1</bitWidth> 111 <enumeratedValues> 112 <enumeratedValue> 113 <name>output</name> 114 <description>Slave select 0 is output.</description> 115 <value>0</value> 116 </enumeratedValue> 117 <enumeratedValue> 118 <name>input</name> 119 <description>Slave Select 0 is input, only valid if MMEN=1.</description> 120 <value>1</value> 121 </enumeratedValue> 122 </enumeratedValues> 123 </field> 124 <field> 125 <name>START</name> 126 <description>Start Transmit.</description> 127 <bitOffset>5</bitOffset> 128 <bitWidth>1</bitWidth> 129 <enumeratedValues> 130 <enumeratedValue> 131 <name>start</name> 132 <description>Master Initiates a transaction, this bit is self clearing when transactions are done. If a transaction completes, and the TX FIFO is empty, the Master halts, if a transaction completes, and the TX FIFO is not empty, the Master initiates another transaction. </description> 133 <value>1</value> 134 </enumeratedValue> 135 </enumeratedValues> 136 </field> 137 <field> 138 <name>SS_CTRL</name> 139 <description>Slave Select Control.</description> 140 <bitOffset>8</bitOffset> 141 <bitWidth>1</bitWidth> 142 <enumeratedValues> 143 <enumeratedValue> 144 <name>deassert</name> 145 <description>SPI de-asserts Slave Select at the end of a transaction.</description> 146 <value>0</value> 147 </enumeratedValue> 148 <enumeratedValue> 149 <name>assert</name> 150 <description>SPI leaves Slave Select asserted at the end of a transaction.</description> 151 <value>1</value> 152 </enumeratedValue> 153 </enumeratedValues> 154 </field> 155 <field> 156 <name>SS</name> 157 <description>Slave Select, when in Master mode selects which Slave devices are selected. More than one Slave device can be selected.</description> 158 <bitOffset>16</bitOffset> 159 <bitWidth>1</bitWidth> 160 </field> 161 </fields> 162 </register> 163 <register> 164 <name>ctrl2</name> 165 <description>Register for controlling SPI peripheral.</description> 166 <addressOffset>0x08</addressOffset> 167 <access>read-write</access> 168 <fields> 169 <field> 170 <name>TX_NUM_CHAR</name> 171 <description>Nubmer of Characters to transmit.</description> 172 <bitOffset>0</bitOffset> 173 <bitWidth>16</bitWidth> 174 </field> 175 <field> 176 <name>RX_NUM_CHAR</name> 177 <description>Nubmer of Characters to receive.</description> 178 <bitOffset>16</bitOffset> 179 <bitWidth>16</bitWidth> 180 </field> 181 </fields> 182 </register> 183 <register> 184 <name>ctrl3</name> 185 <description>Register for controlling SPI peripheral.</description> 186 <addressOffset>0x0C</addressOffset> 187 <access>read-write</access> 188 <fields> 189 <field> 190 <name>CPHA</name> 191 <description>Clock Phase.</description> 192 <bitOffset>0</bitOffset> 193 <bitWidth>1</bitWidth> 194 <enumeratedValues> 195 <enumeratedValue> 196 <name>risingEdge</name> 197 <description>Data sampled on rising edge.</description> 198 <value>0</value> 199 </enumeratedValue> 200 <enumeratedValue> 201 <name>fallingEdge</name> 202 <description>Data sample on falling edge.</description> 203 <value>1</value> 204 </enumeratedValue> 205 </enumeratedValues> 206 </field> 207 <field> 208 <name>CPOL</name> 209 <description>Clock Polarity.</description> 210 <bitOffset>1</bitOffset> 211 <bitWidth>1</bitWidth> 212 <enumeratedValues> 213 <enumeratedValue> 214 <name>normal</name> 215 <description>Normal clock.</description> 216 <value>0</value> 217 </enumeratedValue> 218 <enumeratedValue> 219 <name>inverted</name> 220 <description>Inverted clock.</description> 221 <value>1</value> 222 </enumeratedValue> 223 </enumeratedValues> 224 </field> 225 <field> 226 <name>SCLK_INV</name> 227 <description>Invert SCLK Feedback in Master Mode.</description> 228 <bitOffset>4</bitOffset> 229 <bitWidth>1</bitWidth> 230 <enumeratedValues> 231 <enumeratedValue> 232 <name>Normal</name> 233 <description>SCLK is not inverted to Line Receiver.</description> 234 <value>0</value> 235 </enumeratedValue> 236 </enumeratedValues> 237 </field> 238 <field> 239 <name>NUMBITS</name> 240 <description>Number of Bits per character.</description> 241 <bitOffset>8</bitOffset> 242 <bitWidth>4</bitWidth> 243 <enumeratedValues> 244 <enumeratedValue> 245 <name>16BITS</name> 246 <description>16 bits per character.</description> 247 <value>0</value> 248 </enumeratedValue> 249 <enumeratedValue> 250 <name>1BITS</name> 251 <description>1 bits per character.</description> 252 <value>1</value> 253 </enumeratedValue> 254 <enumeratedValue> 255 <name>2BITS</name> 256 <description>2 bits per character.</description> 257 <value>2</value> 258 </enumeratedValue> 259 <enumeratedValue> 260 <name>3BITS</name> 261 <description>3 bits per character.</description> 262 <value>3</value> 263 </enumeratedValue> 264 <enumeratedValue> 265 <name>4BITS</name> 266 <description>4 bits per character.</description> 267 <value>4</value> 268 </enumeratedValue> 269 <enumeratedValue> 270 <name>5BITS</name> 271 <description>5 bits per character.</description> 272 <value>5</value> 273 </enumeratedValue> 274 <enumeratedValue> 275 <name>6BITS</name> 276 <description>6 bits per character.</description> 277 <value>6</value> 278 </enumeratedValue> 279 <enumeratedValue> 280 <name>7BITS</name> 281 <description>7 bits per character.</description> 282 <value>7</value> 283 </enumeratedValue> 284 <enumeratedValue> 285 <name>8BITS</name> 286 <description>8 bits per character.</description> 287 <value>8</value> 288 </enumeratedValue> 289 <enumeratedValue> 290 <name>9BITS</name> 291 <description>9 bits per character.</description> 292 <value>9</value> 293 </enumeratedValue> 294 <enumeratedValue> 295 <name>10BITS</name> 296 <description>10 bits per character.</description> 297 <value>10</value> 298 </enumeratedValue> 299 <enumeratedValue> 300 <name>11BITS</name> 301 <description>11 bits per character.</description> 302 <value>11</value> 303 </enumeratedValue> 304 <enumeratedValue> 305 <name>12BITS</name> 306 <description>12 bits per character.</description> 307 <value>12</value> 308 </enumeratedValue> 309 <enumeratedValue> 310 <name>13BITS</name> 311 <description>13 bits per character.</description> 312 <value>13</value> 313 </enumeratedValue> 314 <enumeratedValue> 315 <name>14BITS</name> 316 <description>14 bits per character.</description> 317 <value>14</value> 318 </enumeratedValue> 319 <enumeratedValue> 320 <name>15BITS</name> 321 <description>15 bits per character.</description> 322 <value>15</value> 323 </enumeratedValue> 324 </enumeratedValues> 325 </field> 326 <field> 327 <name>DATA_WIDTH</name> 328 <description>SPI Data width.</description> 329 <bitOffset>12</bitOffset> 330 <bitWidth>2</bitWidth> 331 <enumeratedValues> 332 <enumeratedValue> 333 <name>Mono</name> 334 <description>1 data pin.</description> 335 <value>0</value> 336 </enumeratedValue> 337 <enumeratedValue> 338 <name>Dual</name> 339 <description>2 data pins.</description> 340 <value>1</value> 341 </enumeratedValue> 342 <enumeratedValue> 343 <name>Quad</name> 344 <description>4 data pins.</description> 345 <value>2</value> 346 </enumeratedValue> 347 </enumeratedValues> 348 </field> 349 <field> 350 <name>THREE_WIRE</name> 351 <description>Three Wire mode. MOSI/MISO pin (s) shared. Only Mono mode suports Four-Wire.</description> 352 <bitOffset>15</bitOffset> 353 <bitWidth>1</bitWidth> 354 <enumeratedValues> 355 <enumeratedValue> 356 <name>4wire</name> 357 <description>Use four wire mode (Mono only).</description> 358 <value>0</value> 359 </enumeratedValue> 360 <enumeratedValue> 361 <name>3wire</name> 362 <description>Use three wire mode.</description> 363 <value>1</value> 364 </enumeratedValue> 365 </enumeratedValues> 366 </field> 367 <field> 368 <name>SSPOL</name> 369 <description>Slave Select Polarity</description> 370 <bitOffset>16</bitOffset> 371 <bitWidth>1</bitWidth> 372 <enumeratedValues> 373 <enumeratedValue> 374 <name>activeLow</name> 375 <description>Slave select is active low.</description> 376 <value>0</value> 377 </enumeratedValue> 378 <enumeratedValue> 379 <name>activeHigh</name> 380 <description>Slave select is active high.</description> 381 <value>1</value> 382 </enumeratedValue> 383 </enumeratedValues> 384 </field> 385 </fields> 386 </register> 387 <register> 388 <name>SS_TIME</name> 389 <description>Register for controlling SPI peripheral.</description> 390 <addressOffset>0x10</addressOffset> 391 <access>read-write</access> 392 <fields> 393 <field> 394 <name>SSACT1</name> 395 <description>Slave Select Action delay 1.</description> 396 <bitOffset>0</bitOffset> 397 <bitWidth>8</bitWidth> 398 </field> 399 <field> 400 <name>SSACT2</name> 401 <description>Slave Select Action delay 2.</description> 402 <bitOffset>8</bitOffset> 403 <bitWidth>8</bitWidth> 404 </field> 405 <field> 406 <name>SSINACT</name> 407 <description>Slave Select Inactive delay.</description> 408 <bitOffset>16</bitOffset> 409 <bitWidth>8</bitWidth> 410 </field> 411 </fields> 412 </register> 413 <register> 414 <name>BRG_CTRL</name> 415 <description>Register for controlling SPI clock rate.</description> 416 <addressOffset>0x14</addressOffset> 417 <access>read-write</access> 418 <fields> 419 <field> 420 <name>LO</name> 421 <description>Low duty cycle control. In timer mode, reload[7:0].</description> 422 <bitOffset>0</bitOffset> 423 <bitWidth>8</bitWidth> 424 </field> 425 <field> 426 <name>HI</name> 427 <description>High duty cycle control. In timer mode, reload[15:8].</description> 428 <bitOffset>8</bitOffset> 429 <bitWidth>8</bitWidth> 430 </field> 431 <field> 432 <name>SCALE</name> 433 <description>System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock.</description> 434 <bitOffset>16</bitOffset> 435 <bitWidth>4</bitWidth> 436 <enumeratedValues> 437 <enumeratedValue> 438 <name>div1</name> 439 <description>clk_freq = f_pclk/1.</description> 440 <value>0</value> 441 </enumeratedValue> 442 <enumeratedValue> 443 <name>div2</name> 444 <description>clk_freq = f_pclk/2.</description> 445 <value>1</value> 446 </enumeratedValue> 447 <enumeratedValue> 448 <name>div4</name> 449 <description>clk_freq = f_pclk/4.</description> 450 <value>2</value> 451 </enumeratedValue> 452 <enumeratedValue> 453 <name>div8</name> 454 <description>clk_freq = f_pclk/8.</description> 455 <value>3</value> 456 </enumeratedValue> 457 <enumeratedValue> 458 <name>div16</name> 459 <description>clk_freq = f_pclk/16.</description> 460 <value>4</value> 461 </enumeratedValue> 462 <enumeratedValue> 463 <name>div32</name> 464 <description>clk_freq = f_pclk/32.</description> 465 <value>5</value> 466 </enumeratedValue> 467 <enumeratedValue> 468 <name>div64</name> 469 <description>clk_freq = f_pclk/64.</description> 470 <value>6</value> 471 </enumeratedValue> 472 <enumeratedValue> 473 <name>div128</name> 474 <description>clk_freq = f_pclk/128.</description> 475 <value>7</value> 476 </enumeratedValue> 477 <enumeratedValue> 478 <name>div256</name> 479 <description>clk_freq = f_pclk/256.</description> 480 <value>8</value> 481 </enumeratedValue> 482 </enumeratedValues> 483 </field> 484 </fields> 485 </register> 486 <register> 487 <name>DMA</name> 488 <description>Register for controlling DMA.</description> 489 <addressOffset>0x1C</addressOffset> 490 <access>read-write</access> 491 <fields> 492 <field> 493 <name>TX_FIFO_LEVEL</name> 494 <description>Transmit FIFO level that will trigger a DMA request, also level for threshold status. When TX FIFO has fewer than this many bytes, the associated events and conditions are triggered.</description> 495 <bitOffset>0</bitOffset> 496 <bitWidth>5</bitWidth> 497 </field> 498 <field> 499 <name>TX_FIFO_EN</name> 500 <description>Transmit FIFO enabled for SPI transactions.</description> 501 <bitOffset>6</bitOffset> 502 <bitWidth>1</bitWidth> 503 <enumeratedValues> 504 <enumeratedValue> 505 <name>dis</name> 506 <description>Transmit FIFO is not enabled.</description> 507 <value>0</value> 508 </enumeratedValue> 509 <enumeratedValue> 510 <name>en</name> 511 <description>Transmit FIFO is enabled.</description> 512 <value>1</value> 513 </enumeratedValue> 514 </enumeratedValues> 515 </field> 516 <field> 517 <name>TX_FIFO_CLEAR</name> 518 <description>Clear TX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side.</description> 519 <bitOffset>7</bitOffset> 520 <bitWidth>1</bitWidth> 521 <enumeratedValues> 522 <enumeratedValue> 523 <name>clear</name> 524 <description>Clear the Transmit FIFO, clears any pending TX FIFO status.</description> 525 <value>1</value> 526 </enumeratedValue> 527 </enumeratedValues> 528 </field> 529 <field> 530 <name>TX_FIFO_CNT</name> 531 <description>Count of entries in TX FIFO.</description> 532 <bitOffset>8</bitOffset> 533 <bitWidth>6</bitWidth> 534 </field> 535 <field> 536 <name>TX_DMA_EN</name> 537 <description>TX DMA Enable.</description> 538 <bitOffset>15</bitOffset> 539 <bitWidth>1</bitWidth> 540 <enumeratedValues> 541 <enumeratedValue> 542 <name>dis</name> 543 <description>TX DMA requests are disabled, andy pending DMA requests are cleared.</description> 544 <value>0</value> 545 </enumeratedValue> 546 <enumeratedValue> 547 <name>en</name> 548 <description>TX DMA requests are enabled.</description> 549 <value>1</value> 550 </enumeratedValue> 551 </enumeratedValues> 552 </field> 553 <field> 554 <name>RX_FIFO_LEVEL</name> 555 <description>Receive FIFO level that will trigger a DMA request, also level for threshold status. When RX FIFO has more than this many bytes, the associated events and conditions are triggered.</description> 556 <bitOffset>16</bitOffset> 557 <bitWidth>5</bitWidth> 558 </field> 559 <field> 560 <name>RX_FIFO_EN</name> 561 <description>Receive FIFO enabled for SPI transactions.</description> 562 <bitOffset>22</bitOffset> 563 <bitWidth>1</bitWidth> 564 <enumeratedValues> 565 <enumeratedValue> 566 <name>dis</name> 567 <description>Receive FIFO is not enabled.</description> 568 <value>0</value> 569 </enumeratedValue> 570 <enumeratedValue> 571 <name>en</name> 572 <description>Receive FIFO is enabled.</description> 573 <value>1</value> 574 </enumeratedValue> 575 </enumeratedValues> 576 </field> 577 <field> 578 <name>RX_FIFO_CLEAR</name> 579 <description>Clear RX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side.</description> 580 <bitOffset>23</bitOffset> 581 <bitWidth>1</bitWidth> 582 <enumeratedValues> 583 <enumeratedValue> 584 <name>clear</name> 585 <description>Clear the Receive FIFIO, clears any pending RX FIFO status.</description> 586 <value>1</value> 587 </enumeratedValue> 588 </enumeratedValues> 589 </field> 590 <field> 591 <name>RX_FIFO_CNT</name> 592 <description>Count of entries in RX FIFO.</description> 593 <bitOffset>24</bitOffset> 594 <bitWidth>6</bitWidth> 595 </field> 596 <field> 597 <name>RX_DMA_EN</name> 598 <description>RX DMA Enable.</description> 599 <bitOffset>31</bitOffset> 600 <bitWidth>1</bitWidth> 601 <enumeratedValues> 602 <enumeratedValue> 603 <name>dis</name> 604 <description>RX DMA requests are disabled, any pending DMA requests are cleared.</description> 605 <value>0</value> 606 </enumeratedValue> 607 <enumeratedValue> 608 <name>en</name> 609 <description>RX DMA requests are enabled.</description> 610 <value>1</value> 611 </enumeratedValue> 612 </enumeratedValues> 613 </field> 614 </fields> 615 </register> 616 <register> 617 <name>int_fl</name> 618 <description>Register for reading and clearing interrupt flags. All bits are write 1 to clear.</description> 619 <addressOffset>0x20</addressOffset> 620 <access>read-write</access> 621 <fields> 622 <field> 623 <name>TX_LEVEL</name> 624 <description>TX FIFO Threshold Crossed.</description> 625 <bitOffset>0</bitOffset> 626 <bitWidth>1</bitWidth> 627 <enumeratedValues> 628 <enumeratedValue> 629 <name>clear</name> 630 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 631 <value>1</value> 632 </enumeratedValue> 633 </enumeratedValues> 634 </field> 635 <field> 636 <name>TX_EMPTY</name> 637 <description>TX FIFO Empty.</description> 638 <bitOffset>1</bitOffset> 639 <bitWidth>1</bitWidth> 640 <enumeratedValues> 641 <enumeratedValue> 642 <name>clear</name> 643 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 644 <value>1</value> 645 </enumeratedValue> 646 </enumeratedValues> 647 </field> 648 <field> 649 <name>RX_LEVEL</name> 650 <description>RX FIFO Threshold Crossed.</description> 651 <bitOffset>2</bitOffset> 652 <bitWidth>1</bitWidth> 653 <enumeratedValues> 654 <enumeratedValue> 655 <name>clear</name> 656 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 657 <value>1</value> 658 </enumeratedValue> 659 </enumeratedValues> 660 </field> 661 <field> 662 <name>RX_FULL</name> 663 <description>RX FIFO FULL.</description> 664 <bitOffset>3</bitOffset> 665 <bitWidth>1</bitWidth> 666 <enumeratedValues> 667 <enumeratedValue> 668 <name>clear</name> 669 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 670 <value>1</value> 671 </enumeratedValue> 672 </enumeratedValues> 673 </field> 674 <field> 675 <name>SSA</name> 676 <description>Slave Select Asserted.</description> 677 <bitOffset>4</bitOffset> 678 <bitWidth>1</bitWidth> 679 <enumeratedValues> 680 <enumeratedValue> 681 <name>clear</name> 682 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 683 <value>1</value> 684 </enumeratedValue> 685 </enumeratedValues> 686 </field> 687 <field> 688 <name>SSD</name> 689 <description>Slave Select Deasserted.</description> 690 <bitOffset>5</bitOffset> 691 <bitWidth>1</bitWidth> 692 <enumeratedValues> 693 <enumeratedValue> 694 <name>clear</name> 695 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 696 <value>1</value> 697 </enumeratedValue> 698 </enumeratedValues> 699 </field> 700 <field> 701 <name>FAULT</name> 702 <description>Multi-Master Mode Fault.</description> 703 <bitOffset>8</bitOffset> 704 <bitWidth>1</bitWidth> 705 <enumeratedValues> 706 <enumeratedValue> 707 <name>clear</name> 708 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 709 <value>1</value> 710 </enumeratedValue> 711 </enumeratedValues> 712 </field> 713 <field> 714 <name>ABORT</name> 715 <description>Slave Abort Detected.</description> 716 <bitOffset>9</bitOffset> 717 <bitWidth>1</bitWidth> 718 <enumeratedValues> 719 <enumeratedValue> 720 <name>clear</name> 721 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 722 <value>1</value> 723 </enumeratedValue> 724 </enumeratedValues> 725 </field> 726 <field> 727 <name>M_DONE</name> 728 <description>Master Done, set when SPI Master has completed any transactions.</description> 729 <bitOffset>11</bitOffset> 730 <bitWidth>1</bitWidth> 731 <enumeratedValues> 732 <enumeratedValue> 733 <name>clear</name> 734 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 735 <value>1</value> 736 </enumeratedValue> 737 </enumeratedValues> 738 </field> 739 <field> 740 <name>TX_OVR</name> 741 <description>Transmit FIFO Overrun, set when the AMBA side attempts to write data to a full transmit FIFO.</description> 742 <bitOffset>12</bitOffset> 743 <bitWidth>1</bitWidth> 744 <enumeratedValues> 745 <enumeratedValue> 746 <name>clear</name> 747 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 748 <value>1</value> 749 </enumeratedValue> 750 </enumeratedValues> 751 </field> 752 <field> 753 <name>TX_UND</name> 754 <description>Transmit FIFO Underrun, set when the SPI side attempts to read data from an empty transmit FIFO.</description> 755 <bitOffset>13</bitOffset> 756 <bitWidth>1</bitWidth> 757 <enumeratedValues> 758 <enumeratedValue> 759 <name>clear</name> 760 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 761 <value>1</value> 762 </enumeratedValue> 763 </enumeratedValues> 764 </field> 765 <field> 766 <name>RX_OVR</name> 767 <description>Receive FIFO Overrun, set when the SPI side attempts to write to a full receive FIFO.</description> 768 <bitOffset>14</bitOffset> 769 <bitWidth>1</bitWidth> 770 <enumeratedValues> 771 <enumeratedValue> 772 <name>clear</name> 773 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 774 <value>1</value> 775 </enumeratedValue> 776 </enumeratedValues> 777 </field> 778 <field> 779 <name>RX_UND</name> 780 <description>Receive FIFO Underrun, set when the AMBA side attempts to read data from an empty receive FIFO.</description> 781 <bitOffset>15</bitOffset> 782 <bitWidth>1</bitWidth> 783 <enumeratedValues> 784 <enumeratedValue> 785 <name>clear</name> 786 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 787 <value>1</value> 788 </enumeratedValue> 789 </enumeratedValues> 790 </field> 791 </fields> 792 </register> 793 <register> 794 <name>int_en</name> 795 <description>Register for enabling interrupts.</description> 796 <addressOffset>0x24</addressOffset> 797 <access>read-write</access> 798 <fields> 799 <field> 800 <name>TX_LEVEL</name> 801 <description>TX FIFO Threshold interrupt enable.</description> 802 <bitOffset>0</bitOffset> 803 <bitWidth>1</bitWidth> 804 <enumeratedValues> 805 <enumeratedValue> 806 <name>dis</name> 807 <description>Interrupt is disabled.</description> 808 <value>0</value> 809 </enumeratedValue> 810 <enumeratedValue> 811 <name>en</name> 812 <description>Interrupt is enabled.</description> 813 <value>1</value> 814 </enumeratedValue> 815 </enumeratedValues> 816 </field> 817 <field> 818 <name>TX_EMPTY</name> 819 <description>TX FIFO Empty interrupt enable.</description> 820 <bitOffset>1</bitOffset> 821 <bitWidth>1</bitWidth> 822 <enumeratedValues> 823 <enumeratedValue> 824 <name>dis</name> 825 <description>Interrupt is disabled.</description> 826 <value>0</value> 827 </enumeratedValue> 828 <enumeratedValue> 829 <name>en</name> 830 <description>Interrupt is enabled.</description> 831 <value>1</value> 832 </enumeratedValue> 833 </enumeratedValues> 834 </field> 835 <field> 836 <name>RX_LEVEL</name> 837 <description>RX FIFO Threshold Crossed interrupt enable.</description> 838 <bitOffset>2</bitOffset> 839 <bitWidth>1</bitWidth> 840 <enumeratedValues> 841 <enumeratedValue> 842 <name>dis</name> 843 <description>Interrupt is disabled.</description> 844 <value>0</value> 845 </enumeratedValue> 846 <enumeratedValue> 847 <name>en</name> 848 <description>Interrupt is enabled.</description> 849 <value>1</value> 850 </enumeratedValue> 851 </enumeratedValues> 852 </field> 853 <field> 854 <name>RX_FULL</name> 855 <description>RX FIFO FULL interrupt enable.</description> 856 <bitOffset>3</bitOffset> 857 <bitWidth>1</bitWidth> 858 <enumeratedValues> 859 <enumeratedValue> 860 <name>dis</name> 861 <description>Interrupt is disabled.</description> 862 <value>0</value> 863 </enumeratedValue> 864 <enumeratedValue> 865 <name>en</name> 866 <description>Interrupt is enabled.</description> 867 <value>1</value> 868 </enumeratedValue> 869 </enumeratedValues> 870 </field> 871 <field> 872 <name>SSA</name> 873 <description>Slave Select Asserted interrupt enable.</description> 874 <bitOffset>4</bitOffset> 875 <bitWidth>1</bitWidth> 876 <enumeratedValues> 877 <enumeratedValue> 878 <name>dis</name> 879 <description>Interrupt is disabled.</description> 880 <value>0</value> 881 </enumeratedValue> 882 <enumeratedValue> 883 <name>en</name> 884 <description>Interrupt is enabled.</description> 885 <value>1</value> 886 </enumeratedValue> 887 </enumeratedValues> 888 </field> 889 <field> 890 <name>SSD</name> 891 <description>Slave Select Deasserted interrupt enable.</description> 892 <bitOffset>5</bitOffset> 893 <bitWidth>1</bitWidth> 894 <enumeratedValues> 895 <enumeratedValue> 896 <name>dis</name> 897 <description>Interrupt is disabled.</description> 898 <value>0</value> 899 </enumeratedValue> 900 <enumeratedValue> 901 <name>en</name> 902 <description>Interrupt is enabled.</description> 903 <value>1</value> 904 </enumeratedValue> 905 </enumeratedValues> 906 </field> 907 <field> 908 <name>FAULT</name> 909 <description>Multi-Master Mode Fault interrupt enable.</description> 910 <bitOffset>8</bitOffset> 911 <bitWidth>1</bitWidth> 912 <enumeratedValues> 913 <enumeratedValue> 914 <name>dis</name> 915 <description>Interrupt is disabled.</description> 916 <value>0</value> 917 </enumeratedValue> 918 <enumeratedValue> 919 <name>en</name> 920 <description>Interrupt is enabled.</description> 921 <value>1</value> 922 </enumeratedValue> 923 </enumeratedValues> 924 </field> 925 <field> 926 <name>ABORT</name> 927 <description>Slave Abort Detected interrupt enable.</description> 928 <bitOffset>9</bitOffset> 929 <bitWidth>1</bitWidth> 930 <enumeratedValues> 931 <enumeratedValue> 932 <name>dis</name> 933 <description>Interrupt is disabled.</description> 934 <value>0</value> 935 </enumeratedValue> 936 <enumeratedValue> 937 <name>en</name> 938 <description>Interrupt is enabled.</description> 939 <value>1</value> 940 </enumeratedValue> 941 </enumeratedValues> 942 </field> 943 <field> 944 <name>M_DONE</name> 945 <description>Master Done interrupt enable.</description> 946 <bitOffset>11</bitOffset> 947 <bitWidth>1</bitWidth> 948 <enumeratedValues> 949 <enumeratedValue> 950 <name>dis</name> 951 <description>Interrupt is disabled.</description> 952 <value>0</value> 953 </enumeratedValue> 954 <enumeratedValue> 955 <name>en</name> 956 <description>Interrupt is enabled.</description> 957 <value>1</value> 958 </enumeratedValue> 959 </enumeratedValues> 960 </field> 961 <field> 962 <name>TX_OVR</name> 963 <description>Transmit FIFO Overrun interrupt enable.</description> 964 <bitOffset>12</bitOffset> 965 <bitWidth>1</bitWidth> 966 <enumeratedValues> 967 <enumeratedValue> 968 <name>dis</name> 969 <description>Interrupt is disabled.</description> 970 <value>0</value> 971 </enumeratedValue> 972 <enumeratedValue> 973 <name>en</name> 974 <description>Interrupt is enabled.</description> 975 <value>1</value> 976 </enumeratedValue> 977 </enumeratedValues> 978 </field> 979 <field> 980 <name>TX_UND</name> 981 <description>Transmit FIFO Underrun interrupt enable.</description> 982 <bitOffset>13</bitOffset> 983 <bitWidth>1</bitWidth> 984 <enumeratedValues> 985 <enumeratedValue> 986 <name>dis</name> 987 <description>Interrupt is disabled.</description> 988 <value>0</value> 989 </enumeratedValue> 990 <enumeratedValue> 991 <name>en</name> 992 <description>Interrupt is enabled.</description> 993 <value>1</value> 994 </enumeratedValue> 995 </enumeratedValues> 996 </field> 997 <field> 998 <name>RX_OVR</name> 999 <description>Receive FIFO Overrun interrupt enable.</description> 1000 <bitOffset>14</bitOffset> 1001 <bitWidth>1</bitWidth> 1002 <enumeratedValues> 1003 <enumeratedValue> 1004 <name>dis</name> 1005 <description>Interrupt is disabled.</description> 1006 <value>0</value> 1007 </enumeratedValue> 1008 <enumeratedValue> 1009 <name>en</name> 1010 <description>Interrupt is enabled.</description> 1011 <value>1</value> 1012 </enumeratedValue> 1013 </enumeratedValues> 1014 </field> 1015 <field> 1016 <name>RX_UND</name> 1017 <description>Receive FIFO Underrun interrupt enable.</description> 1018 <bitOffset>15</bitOffset> 1019 <bitWidth>1</bitWidth> 1020 <enumeratedValues> 1021 <enumeratedValue> 1022 <name>dis</name> 1023 <description>Interrupt is disabled.</description> 1024 <value>0</value> 1025 </enumeratedValue> 1026 <enumeratedValue> 1027 <name>en</name> 1028 <description>Interrupt is enabled.</description> 1029 <value>1</value> 1030 </enumeratedValue> 1031 </enumeratedValues> 1032 </field> 1033 </fields> 1034 </register> 1035 <register> 1036 <name>WAKE_FL</name> 1037 <description>Register for wake up flags. All bits in this register are write 1 to clear.</description> 1038 <addressOffset>0x28</addressOffset> 1039 <access>read-write</access> 1040 <fields> 1041 <field> 1042 <name>TX_LEVEL</name> 1043 <description>Wake on TX FIFO Threshold Crossed.</description> 1044 <bitOffset>0</bitOffset> 1045 <bitWidth>1</bitWidth> 1046 <enumeratedValues> 1047 <enumeratedValue> 1048 <name>clear</name> 1049 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 1050 <value>1</value> 1051 </enumeratedValue> 1052 </enumeratedValues> 1053 </field> 1054 <field> 1055 <name>TX_EMPTY</name> 1056 <description>Wake on TX FIFO Empty.</description> 1057 <bitOffset>1</bitOffset> 1058 <bitWidth>1</bitWidth> 1059 <enumeratedValues> 1060 <enumeratedValue> 1061 <name>clear</name> 1062 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 1063 <value>1</value> 1064 </enumeratedValue> 1065 </enumeratedValues> 1066 </field> 1067 <field> 1068 <name>RX_LEVEL</name> 1069 <description>Wake on RX FIFO Threshold Crossed.</description> 1070 <bitOffset>2</bitOffset> 1071 <bitWidth>1</bitWidth> 1072 <enumeratedValues> 1073 <enumeratedValue> 1074 <name>clear</name> 1075 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 1076 <value>1</value> 1077 </enumeratedValue> 1078 </enumeratedValues> 1079 </field> 1080 <field> 1081 <name>RX_FULL</name> 1082 <description>Wake on RX FIFO Full.</description> 1083 <bitOffset>3</bitOffset> 1084 <bitWidth>1</bitWidth> 1085 <enumeratedValues> 1086 <enumeratedValue> 1087 <name>clear</name> 1088 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 1089 <value>1</value> 1090 </enumeratedValue> 1091 </enumeratedValues> 1092 </field> 1093 </fields> 1094 </register> 1095 <register> 1096 <name>WAKE_EN</name> 1097 <description>Register for wake up enable.</description> 1098 <addressOffset>0x2C</addressOffset> 1099 <access>read-write</access> 1100 <fields> 1101 <field> 1102 <name>TX_LEVEL</name> 1103 <description>Wake on TX FIFO Threshold Crossed Enable.</description> 1104 <bitOffset>0</bitOffset> 1105 <bitWidth>1</bitWidth> 1106 <enumeratedValues> 1107 <enumeratedValue> 1108 <name>dis</name> 1109 <description>Wakeup source disabled.</description> 1110 <value>0</value> 1111 </enumeratedValue> 1112 <enumeratedValue> 1113 <name>en</name> 1114 <description>Wakeup source enabled.</description> 1115 <value>1</value> 1116 </enumeratedValue> 1117 </enumeratedValues> 1118 </field> 1119 <field> 1120 <name>TX_EMPTY</name> 1121 <description>Wake on TX FIFO Empty Enable.</description> 1122 <bitOffset>1</bitOffset> 1123 <bitWidth>1</bitWidth> 1124 <enumeratedValues> 1125 <enumeratedValue> 1126 <name>dis</name> 1127 <description>Wakeup source disabled.</description> 1128 <value>0</value> 1129 </enumeratedValue> 1130 <enumeratedValue> 1131 <name>en</name> 1132 <description>Wakeup source enabled.</description> 1133 <value>1</value> 1134 </enumeratedValue> 1135 </enumeratedValues> 1136 </field> 1137 <field> 1138 <name>RX_LEVEL</name> 1139 <description>Wake on RX FIFO Threshold Crossed Enable.</description> 1140 <bitOffset>2</bitOffset> 1141 <bitWidth>1</bitWidth> 1142 <enumeratedValues> 1143 <enumeratedValue> 1144 <name>dis</name> 1145 <description>Wakeup source disabled.</description> 1146 <value>0</value> 1147 </enumeratedValue> 1148 <enumeratedValue> 1149 <name>en</name> 1150 <description>Wakeup source enabled.</description> 1151 <value>1</value> 1152 </enumeratedValue> 1153 </enumeratedValues> 1154 </field> 1155 <field> 1156 <name>RX_FULL</name> 1157 <description>Wake on RX FIFO Full Enable.</description> 1158 <bitOffset>3</bitOffset> 1159 <bitWidth>1</bitWidth> 1160 <enumeratedValues> 1161 <enumeratedValue> 1162 <name>dis</name> 1163 <description>Wakeup source disabled.</description> 1164 <value>0</value> 1165 </enumeratedValue> 1166 <enumeratedValue> 1167 <name>en</name> 1168 <description>Wakeup source enabled.</description> 1169 <value>1</value> 1170 </enumeratedValue> 1171 </enumeratedValues> 1172 </field> 1173 </fields> 1174 </register> 1175 <register> 1176 <name>STAT</name> 1177 <description>SPI Status register.</description> 1178 <addressOffset>0x30</addressOffset> 1179 <access>read-only</access> 1180 <fields> 1181 <field> 1182 <name>BUSY</name> 1183 <description>SPI active status. In Master mode, set when transaction starts, cleared when last bit of last character is acted upon and Slave Select de-assertion would occur. In Slave mode, set when Slave Select is asserted, cleared when Slave Select is de-asserted. Not used in Timer mode.</description> 1184 <bitOffset>0</bitOffset> 1185 <bitWidth>1</bitWidth> 1186 <enumeratedValues> 1187 <enumeratedValue> 1188 <name>notActive</name> 1189 <description>SPI not active.</description> 1190 <value>0</value> 1191 </enumeratedValue> 1192 <enumeratedValue> 1193 <name>active</name> 1194 <description>SPI active.</description> 1195 <value>1</value> 1196 </enumeratedValue> 1197 </enumeratedValues> 1198 </field> 1199 </fields> 1200 </register> 1201 <register> 1202 <name>XMEM_CTRL</name> 1203 <description>Register to control external memory.</description> 1204 <addressOffset>0x34</addressOffset> 1205 <access>read-write</access> 1206 <fields> 1207 <field> 1208 <name>XMEM_RD_CMD</name> 1209 <description>Read command.</description> 1210 <bitOffset>0</bitOffset> 1211 <bitWidth>8</bitWidth> 1212 </field> 1213 <field> 1214 <name>XMEM_WR_CMD</name> 1215 <description>Write command.</description> 1216 <bitOffset>8</bitOffset> 1217 <bitWidth>8</bitWidth> 1218 </field> 1219 <field> 1220 <name>XMEM_DCLKS</name> 1221 <description>Dummy clocks.</description> 1222 <bitOffset>16</bitOffset> 1223 <bitWidth>8</bitWidth> 1224 </field> 1225 <field> 1226 <name>XMEM_EN</name> 1227 <description>XMEM enable.</description> 1228 <bitOffset>31</bitOffset> 1229 <bitWidth>1</bitWidth> 1230 <enumeratedValues> 1231 <enumeratedValue> 1232 <name>dis</name> 1233 <description>External memory disabled.</description> 1234 <value>0</value> 1235 </enumeratedValue> 1236 <enumeratedValue> 1237 <name>en</name> 1238 <description>External memory enabled.</description> 1239 <value>1</value> 1240 </enumeratedValue> 1241 </enumeratedValues> 1242 </field> 1243 </fields> 1244 </register> 1245 </registers> 1246 </peripheral> 1247<!-- SPIXR for Data XIP interface --> 1248</device> 1249
